From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/misc/habanalabs/include/common/cpucp_if.h | 1320 + .../misc/habanalabs/include/common/hl_boot_if.h | 702 + drivers/misc/habanalabs/include/common/qman_if.h | 68 + .../include/gaudi/asic_reg/cpu_if_regs.h | 174 + .../include/gaudi/asic_reg/dma0_core_masks.h | 348 + .../include/gaudi/asic_reg/dma0_core_regs.h | 156 + .../include/gaudi/asic_reg/dma0_qm_masks.h | 800 + .../include/gaudi/asic_reg/dma0_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma1_core_regs.h | 156 + .../include/gaudi/asic_reg/dma1_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma2_core_regs.h | 156 + .../include/gaudi/asic_reg/dma2_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma3_core_regs.h | 156 + .../include/gaudi/asic_reg/dma3_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma4_core_regs.h | 156 + .../include/gaudi/asic_reg/dma4_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma5_core_regs.h | 156 + .../include/gaudi/asic_reg/dma5_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma6_core_regs.h | 156 + .../include/gaudi/asic_reg/dma6_qm_regs.h | 834 + .../include/gaudi/asic_reg/dma7_core_regs.h | 156 + .../include/gaudi/asic_reg/dma7_qm_regs.h | 834 + .../gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h | 896 + .../gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h | 896 + .../include/gaudi/asic_reg/dma_if_e_n_regs.h | 860 + .../gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h | 896 + .../gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h | 896 + .../include/gaudi/asic_reg/dma_if_e_s_regs.h | 860 + .../gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h | 896 + .../gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h | 896 + .../include/gaudi/asic_reg/dma_if_w_n_regs.h | 860 + .../gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h | 896 + .../gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h | 896 + .../include/gaudi/asic_reg/dma_if_w_s_regs.h | 860 + .../include/gaudi/asic_reg/gaudi_blocks.h | 4974 ++ .../habanalabs/include/gaudi/asic_reg/gaudi_regs.h | 323 + .../include/gaudi/asic_reg/mme0_ctrl_regs.h | 1456 + .../include/gaudi/asic_reg/mme0_qm_masks.h | 800 + .../include/gaudi/asic_reg/mme0_qm_regs.h | 834 + .../include/gaudi/asic_reg/mme1_ctrl_regs.h | 1456 + .../include/gaudi/asic_reg/mme2_ctrl_regs.h | 1456 + .../include/gaudi/asic_reg/mme2_qm_regs.h | 834 + .../include/gaudi/asic_reg/mme3_ctrl_regs.h | 1456 + .../include/gaudi/asic_reg/mmu_up_regs.h | 72 + .../include/gaudi/asic_reg/nic0_qm0_masks.h | 800 + .../include/gaudi/asic_reg/nic0_qm0_regs.h | 834 + .../include/gaudi/asic_reg/nic0_qm1_regs.h | 834 + .../include/gaudi/asic_reg/nic1_qm0_regs.h | 834 + .../include/gaudi/asic_reg/nic1_qm1_regs.h | 834 + .../include/gaudi/asic_reg/nic2_qm0_regs.h | 834 + .../include/gaudi/asic_reg/nic2_qm1_regs.h | 834 + .../include/gaudi/asic_reg/nic3_qm0_regs.h | 834 + .../include/gaudi/asic_reg/nic3_qm1_regs.h | 834 + .../include/gaudi/asic_reg/nic4_qm0_regs.h | 834 + .../include/gaudi/asic_reg/nic4_qm1_regs.h | 834 + .../include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h | 896 + .../include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h | 896 + .../include/gaudi/asic_reg/psoc_cpu_pll_regs.h | 114 + .../include/gaudi/asic_reg/psoc_etr_regs.h | 114 + .../gaudi/asic_reg/psoc_global_conf_masks.h | 502 + .../include/gaudi/asic_reg/psoc_global_conf_regs.h | 1062 + .../include/gaudi/asic_reg/psoc_timestamp_regs.h | 56 + .../include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h | 896 + .../include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h | 896 + .../habanalabs/include/gaudi/asic_reg/stlb_regs.h | 82 + .../include/gaudi/asic_reg/tpc0_cfg_masks.h | 2578 ++ .../include/gaudi/asic_reg/tpc0_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc0_qm_masks.h | 800 + .../include/gaudi/asic_reg/tpc0_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc1_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc1_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc2_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc2_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc3_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc3_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc4_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc4_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc5_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc5_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc6_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc6_qm_regs.h | 834 + .../include/gaudi/asic_reg/tpc7_cfg_regs.h | 1226 + .../include/gaudi/asic_reg/tpc7_qm_regs.h | 834 + drivers/misc/habanalabs/include/gaudi/gaudi.h | 61 + .../habanalabs/include/gaudi/gaudi_async_events.h | 332 + .../include/gaudi/gaudi_async_ids_map_extended.h | 710 + .../habanalabs/include/gaudi/gaudi_coresight.h | 367 + .../misc/habanalabs/include/gaudi/gaudi_fw_if.h | 91 + .../misc/habanalabs/include/gaudi/gaudi_masks.h | 470 + .../misc/habanalabs/include/gaudi/gaudi_packets.h | 194 + .../misc/habanalabs/include/gaudi/gaudi_reg_map.h | 39 + .../include/gaudi2/arc/gaudi2_arc_common_packets.h | 213 + .../gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h | 567 + .../gaudi2/asic_reg/arc_farm_arc0_aux_masks.h | 819 + .../gaudi2/asic_reg/arc_farm_arc0_aux_regs.h | 591 + .../asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h | 61 + .../gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h | 575 + .../asic_reg/arc_farm_kdma_ctx_axuser_masks.h | 135 + .../asic_reg/arc_farm_kdma_ctx_axuser_regs.h | 61 + .../gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h | 221 + .../gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h | 95 + .../gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/arc_farm_kdma_masks.h | 415 + .../include/gaudi2/asic_reg/arc_farm_kdma_regs.h | 157 + .../include/gaudi2/asic_reg/cpu_if_regs.h | 777 + .../gaudi2/asic_reg/dcore0_dec0_cmd_masks.h | 229 + .../include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h | 85 + .../asic_reg/dcore0_edma0_core_ctx_axuser_regs.h | 61 + .../gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h | 95 + .../gaudi2/asic_reg/dcore0_edma0_core_masks.h | 415 + .../gaudi2/asic_reg/dcore0_edma0_core_regs.h | 157 + .../gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h | 591 + .../dcore0_edma0_qm_axuser_nonsecured_regs.h | 61 + .../gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h | 29 + .../gaudi2/asic_reg/dcore0_edma0_qm_masks.h | 1165 + .../include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h | 1057 + .../asic_reg/dcore0_edma1_core_ctx_axuser_regs.h | 61 + .../dcore0_edma1_qm_axuser_nonsecured_regs.h | 61 + .../gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h | 294 + .../gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h | 237 + .../gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h | 348 + .../gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h | 141 + .../include/gaudi2/asic_reg/dcore0_mme_acc_regs.h | 73 + ...dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h | 33 + ...dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h | 33 + .../dcore0_mme_ctrl_lo_arch_base_addr_regs.h | 39 + .../dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h | 73 + ...dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h | 35 + .../dcore0_mme_ctrl_lo_arch_tensor_a_regs.h | 67 + .../dcore0_mme_ctrl_lo_arch_tensor_b_regs.h | 67 + .../dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h | 67 + .../gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h | 468 + .../asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h | 61 + .../gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h | 163 + .../asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h | 567 + .../gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h | 591 + .../dcore0_mme_qm_arc_dup_eng_axuser_regs.h | 61 + .../asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h | 575 + .../dcore0_mme_qm_axuser_nonsecured_regs.h | 61 + .../asic_reg/dcore0_mme_qm_axuser_secured_regs.h | 61 + .../gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/dcore0_mme_qm_regs.h | 1057 + .../gaudi2/asic_reg/dcore0_mme_sbte0_masks.h | 107 + .../dcore0_mme_sbte0_mstr_if_axuser_regs.h | 61 + .../asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h | 61 + .../gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h | 291 + .../dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h | 213 + .../dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h | 189 + .../dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h | 213 + .../dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h | 189 + .../gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h | 135 + .../gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h | 1203 + .../dcore0_sync_mngr_mstr_if_axuser_masks.h | 135 + .../dcore0_sync_mngr_mstr_if_axuser_regs.h | 61 + .../gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h | 87 + .../gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h | 43543 ++++++++++++++++++ .../gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h | 61 + .../gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h | 129 + .../dcore0_tpc0_cfg_kernel_tensor_0_regs.h | 63 + .../gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h | 509 + .../gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h | 129 + .../asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h | 27 + .../asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h | 63 + .../include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h | 229 + .../gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h | 185 + .../asic_reg/dcore0_tpc0_eml_busmon_0_regs.h | 163 + .../gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h | 113 + .../gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h | 75 + .../gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h | 151 + .../gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h | 131 + .../gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h | 591 + .../dcore0_tpc0_qm_axuser_nonsecured_regs.h | 61 + .../gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h | 1057 + .../dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h | 61 + ...dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h | 61 + .../dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h | 61 + .../dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h | 61 + .../dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h | 61 + .../gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h | 581 + .../gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h | 245 + .../asic_reg/dcore0_vdec0_ctrl_special_regs.h | 185 + .../gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h | 163 + .../gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h | 163 + .../gaudi2/asic_reg/gaudi2_blocks_linux_driver.h | 45067 +++++++++++++++++++ .../include/gaudi2/asic_reg/gaudi2_regs.h | 552 + .../include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/nic0_qm0_regs.h | 1057 + .../gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h | 591 + .../include/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 + .../nic0_umr0_0_completion_queue_ci_1_regs.h | 27 + .../asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h | 31 + .../include/gaudi2/asic_reg/pcie_aux_regs.h | 293 + .../include/gaudi2/asic_reg/pcie_dbi_regs.h | 422 + .../include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h | 229 + .../include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h | 85 + .../pcie_vdec0_brdg_ctrl_axuser_dec_regs.h | 61 + .../pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h | 61 + .../pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h | 61 + .../pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h | 61 + .../pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h | 61 + .../gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h | 580 + .../gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h | 245 + .../gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h | 185 + .../include/gaudi2/asic_reg/pcie_wrap_regs.h | 601 + .../gaudi2/asic_reg/pcie_wrap_special_regs.h | 185 + .../gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h | 61 + .../include/gaudi2/asic_reg/pdma0_core_ctx_regs.h | 95 + .../include/gaudi2/asic_reg/pdma0_core_masks.h | 415 + .../include/gaudi2/asic_reg/pdma0_core_regs.h | 157 + .../gaudi2/asic_reg/pdma0_core_special_masks.h | 135 + .../gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h | 591 + .../asic_reg/pdma0_qm_axuser_nonsecured_regs.h | 61 + .../gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h | 61 + .../include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/pdma0_qm_masks.h | 1165 + .../include/gaudi2/asic_reg/pdma0_qm_regs.h | 1057 + .../gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h | 61 + .../asic_reg/pdma1_qm_axuser_nonsecured_regs.h | 61 + .../include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h | 334 + .../include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h | 141 + .../include/gaudi2/asic_reg/pmmu_pif_regs.h | 135 + .../include/gaudi2/asic_reg/psoc_etr_masks.h | 311 + .../include/gaudi2/asic_reg/psoc_etr_regs.h | 115 + .../gaudi2/asic_reg/psoc_global_conf_masks.h | 1406 + .../gaudi2/asic_reg/psoc_global_conf_regs.h | 1337 + .../gaudi2/asic_reg/psoc_reset_conf_masks.h | 2321 + .../include/gaudi2/asic_reg/psoc_reset_conf_regs.h | 989 + .../include/gaudi2/asic_reg/psoc_timestamp_regs.h | 57 + .../include/gaudi2/asic_reg/rot0_desc_regs.h | 155 + .../include/gaudi2/asic_reg/rot0_masks.h | 313 + .../include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h | 591 + .../asic_reg/rot0_qm_axuser_nonsecured_regs.h | 61 + .../include/gaudi2/asic_reg/rot0_qm_cgm_regs.h | 29 + .../include/gaudi2/asic_reg/rot0_qm_regs.h | 1057 + .../habanalabs/include/gaudi2/asic_reg/rot0_regs.h | 111 + .../include/gaudi2/asic_reg/xbar_edge_0_regs.h | 199 + .../include/gaudi2/asic_reg/xbar_mid_0_regs.h | 199 + drivers/misc/habanalabs/include/gaudi2/gaudi2.h | 123 + .../include/gaudi2/gaudi2_async_events.h | 963 + .../include/gaudi2/gaudi2_async_ids_map_extended.h | 2668 ++ .../habanalabs/include/gaudi2/gaudi2_coresight.h | 984 + .../misc/habanalabs/include/gaudi2/gaudi2_fw_if.h | 99 + .../habanalabs/include/gaudi2/gaudi2_packets.h | 197 + .../habanalabs/include/gaudi2/gaudi2_reg_map.h | 59 + .../include/goya/asic_reg/cpu_ca53_cfg_masks.h | 190 + .../include/goya/asic_reg/cpu_ca53_cfg_regs.h | 60 + .../habanalabs/include/goya/asic_reg/cpu_if_regs.h | 48 + .../include/goya/asic_reg/cpu_pll_regs.h | 104 + .../include/goya/asic_reg/dma_ch_0_masks.h | 418 + .../include/goya/asic_reg/dma_ch_0_regs.h | 208 + .../include/goya/asic_reg/dma_ch_1_regs.h | 208 + .../include/goya/asic_reg/dma_ch_2_regs.h | 208 + .../include/goya/asic_reg/dma_ch_3_regs.h | 208 + .../include/goya/asic_reg/dma_ch_4_regs.h | 208 + .../include/goya/asic_reg/dma_macro_masks.h | 104 + .../include/goya/asic_reg/dma_macro_regs.h | 180 + .../include/goya/asic_reg/dma_nrtr_masks.h | 208 + .../include/goya/asic_reg/dma_nrtr_regs.h | 226 + .../include/goya/asic_reg/dma_qm_0_masks.h | 464 + .../include/goya/asic_reg/dma_qm_0_regs.h | 178 + .../include/goya/asic_reg/dma_qm_1_regs.h | 178 + .../include/goya/asic_reg/dma_qm_2_regs.h | 178 + .../include/goya/asic_reg/dma_qm_3_regs.h | 178 + .../include/goya/asic_reg/dma_qm_4_regs.h | 178 + .../habanalabs/include/goya/asic_reg/goya_blocks.h | 1372 + .../habanalabs/include/goya/asic_reg/goya_masks.h | 267 + .../habanalabs/include/goya/asic_reg/goya_regs.h | 122 + .../habanalabs/include/goya/asic_reg/ic_pll_regs.h | 104 + .../habanalabs/include/goya/asic_reg/mc_pll_regs.h | 104 + .../include/goya/asic_reg/mme1_rtr_masks.h | 652 + .../include/goya/asic_reg/mme1_rtr_regs.h | 330 + .../include/goya/asic_reg/mme2_rtr_regs.h | 330 + .../include/goya/asic_reg/mme3_rtr_regs.h | 330 + .../include/goya/asic_reg/mme4_rtr_regs.h | 330 + .../include/goya/asic_reg/mme5_rtr_regs.h | 330 + .../include/goya/asic_reg/mme6_rtr_regs.h | 330 + .../include/goya/asic_reg/mme_cmdq_masks.h | 372 + .../include/goya/asic_reg/mme_cmdq_regs.h | 138 + .../habanalabs/include/goya/asic_reg/mme_masks.h | 1536 + .../include/goya/asic_reg/mme_qm_masks.h | 464 + .../habanalabs/include/goya/asic_reg/mme_qm_regs.h | 178 + .../habanalabs/include/goya/asic_reg/mme_regs.h | 1152 + .../habanalabs/include/goya/asic_reg/mmu_masks.h | 142 + .../habanalabs/include/goya/asic_reg/mmu_regs.h | 52 + .../include/goya/asic_reg/pci_nrtr_masks.h | 208 + .../include/goya/asic_reg/pci_nrtr_regs.h | 226 + .../include/goya/asic_reg/pcie_aux_regs.h | 242 + .../include/goya/asic_reg/pcie_wrap_regs.h | 306 + .../include/goya/asic_reg/psoc_emmc_pll_regs.h | 104 + .../include/goya/asic_reg/psoc_etr_regs.h | 114 + .../include/goya/asic_reg/psoc_global_conf_masks.h | 446 + .../include/goya/asic_reg/psoc_global_conf_regs.h | 744 + .../include/goya/asic_reg/psoc_mme_pll_regs.h | 104 + .../include/goya/asic_reg/psoc_pci_pll_regs.h | 104 + .../include/goya/asic_reg/psoc_spi_regs.h | 142 + .../include/goya/asic_reg/psoc_timestamp_regs.h | 56 + .../include/goya/asic_reg/sram_y0_x0_rtr_regs.h | 82 + .../include/goya/asic_reg/sram_y0_x1_rtr_regs.h | 82 + .../include/goya/asic_reg/sram_y0_x2_rtr_regs.h | 82 + .../include/goya/asic_reg/sram_y0_x3_rtr_regs.h | 82 + .../include/goya/asic_reg/sram_y0_x4_rtr_regs.h | 82 + .../habanalabs/include/goya/asic_reg/stlb_masks.h | 116 + .../habanalabs/include/goya/asic_reg/stlb_regs.h | 54 + .../include/goya/asic_reg/tpc0_cfg_masks.h | 1606 + .../include/goya/asic_reg/tpc0_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc0_cmdq_masks.h | 372 + .../include/goya/asic_reg/tpc0_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc0_eml_cfg_masks.h | 346 + .../include/goya/asic_reg/tpc0_eml_cfg_regs.h | 312 + .../include/goya/asic_reg/tpc0_nrtr_masks.h | 208 + .../include/goya/asic_reg/tpc0_nrtr_regs.h | 226 + .../include/goya/asic_reg/tpc0_qm_masks.h | 464 + .../include/goya/asic_reg/tpc0_qm_regs.h | 178 + .../include/goya/asic_reg/tpc1_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc1_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc1_qm_regs.h | 178 + .../include/goya/asic_reg/tpc1_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc2_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc2_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc2_qm_regs.h | 178 + .../include/goya/asic_reg/tpc2_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc3_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc3_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc3_qm_regs.h | 178 + .../include/goya/asic_reg/tpc3_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc4_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc4_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc4_qm_regs.h | 178 + .../include/goya/asic_reg/tpc4_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc5_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc5_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc5_qm_regs.h | 178 + .../include/goya/asic_reg/tpc5_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc6_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc6_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc6_qm_regs.h | 178 + .../include/goya/asic_reg/tpc6_rtr_regs.h | 322 + .../include/goya/asic_reg/tpc7_cfg_regs.h | 886 + .../include/goya/asic_reg/tpc7_cmdq_regs.h | 138 + .../include/goya/asic_reg/tpc7_nrtr_regs.h | 226 + .../include/goya/asic_reg/tpc7_qm_regs.h | 178 + .../include/goya/asic_reg/tpc_pll_regs.h | 104 + drivers/misc/habanalabs/include/goya/goya.h | 43 + .../habanalabs/include/goya/goya_async_events.h | 200 + .../misc/habanalabs/include/goya/goya_coresight.h | 199 + drivers/misc/habanalabs/include/goya/goya_fw_if.h | 20 + .../misc/habanalabs/include/goya/goya_packets.h | 130 + .../misc/habanalabs/include/goya/goya_reg_map.h | 43 + .../habanalabs/include/hw_ip/mmu/mmu_general.h | 57 + .../misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h | 27 + .../misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h | 28 + .../misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h | 51 + .../habanalabs/include/hw_ip/pci/pci_general.h | 23 + 378 files changed, 251873 insertions(+) create mode 100644 drivers/misc/habanalabs/include/common/cpucp_if.h create mode 100644 drivers/misc/habanalabs/include/common/hl_boot_if.h create mode 100644 drivers/misc/habanalabs/include/common/qman_if.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h create mode 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drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_packets.h create mode 100644 drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h create mode 100644 drivers/misc/habanalabs/include/goya/goya.h create mode 100644 drivers/misc/habanalabs/include/goya/goya_async_events.h create mode 100644 drivers/misc/habanalabs/include/goya/goya_coresight.h create mode 100644 drivers/misc/habanalabs/include/goya/goya_fw_if.h create mode 100644 drivers/misc/habanalabs/include/goya/goya_packets.h create mode 100644 drivers/misc/habanalabs/include/goya/goya_reg_map.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h create mode 100644 drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h (limited to 'drivers/misc/habanalabs/include') diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h new file mode 100644 index 000000000..baa5aa43b --- /dev/null +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -0,0 +1,1320 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef CPUCP_IF_H +#define CPUCP_IF_H + +#include +#include + +#include "hl_boot_if.h" + +#define NUM_HBM_PSEUDO_CH 2 +#define NUM_HBM_CH_PER_DEV 8 +#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 +#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 +#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 +#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 +#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 +#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 +#define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 +#define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 +#define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 +#define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 +#define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 +#define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 +#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 +#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 + +#define PLL_MAP_MAX_BITS 128 +#define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) + +/* + * info of the pkt queue pointers in the first async occurrence + */ +struct cpucp_pkt_sync_err { + __le32 pi; + __le32 ci; +}; + +struct hl_eq_hbm_ecc_data { + /* SERR counter */ + __le32 sec_cnt; + /* DERR counter */ + __le32 dec_cnt; + /* Supplemental Information according to the mask bits */ + __le32 hbm_ecc_info; + /* Address in hbm where the ecc happened */ + __le32 first_addr; + /* SERR continuous address counter */ + __le32 sec_cont_cnt; + __le32 pad; +}; + +/* + * EVENT QUEUE + */ + +struct hl_eq_header { + __le32 reserved; + __le32 ctl; +}; + +struct hl_eq_ecc_data { + __le64 ecc_address; + __le64 ecc_syndrom; + __u8 memory_wrapper_idx; + __u8 is_critical; + __u8 pad[6]; +}; + +enum hl_sm_sei_cause { + SM_SEI_SO_OVERFLOW, + SM_SEI_LBW_4B_UNALIGNED, + SM_SEI_AXI_RESPONSE_ERR +}; + +struct hl_eq_sm_sei_data { + __le32 sei_log; + /* enum hl_sm_sei_cause */ + __u8 sei_cause; + __u8 pad[3]; +}; + +enum hl_fw_alive_severity { + FW_ALIVE_SEVERITY_MINOR, + FW_ALIVE_SEVERITY_CRITICAL +}; + +struct hl_eq_fw_alive { + __le64 uptime_seconds; + __le32 process_id; + __le32 thread_id; + /* enum hl_fw_alive_severity */ + __u8 severity; + __u8 pad[7]; +}; + +struct hl_eq_intr_cause { + __le64 intr_cause_data; +}; + +struct hl_eq_pcie_drain_ind_data { + struct hl_eq_intr_cause intr_cause; + __le64 drain_wr_addr_lbw; + __le64 drain_rd_addr_lbw; + __le64 drain_wr_addr_hbw; + __le64 drain_rd_addr_hbw; +}; + +struct hl_eq_razwi_lbw_info_regs { + __le32 rr_aw_razwi_reg; + __le32 rr_aw_razwi_id_reg; + __le32 rr_ar_razwi_reg; + __le32 rr_ar_razwi_id_reg; +}; + +struct hl_eq_razwi_hbw_info_regs { + __le32 rr_aw_razwi_hi_reg; + __le32 rr_aw_razwi_lo_reg; + __le32 rr_aw_razwi_id_reg; + __le32 rr_ar_razwi_hi_reg; + __le32 rr_ar_razwi_lo_reg; + __le32 rr_ar_razwi_id_reg; +}; + +/* razwi_happened masks */ +#define RAZWI_HAPPENED_HBW 0x1 +#define RAZWI_HAPPENED_LBW 0x2 +#define RAZWI_HAPPENED_AW 0x4 +#define RAZWI_HAPPENED_AR 0x8 + +struct hl_eq_razwi_info { + __le32 razwi_happened_mask; + union { + struct hl_eq_razwi_lbw_info_regs lbw; + struct hl_eq_razwi_hbw_info_regs hbw; + }; + __le32 pad; +}; + +struct hl_eq_razwi_with_intr_cause { + struct hl_eq_razwi_info razwi_info; + struct hl_eq_intr_cause intr_cause; +}; + +#define HBM_CA_ERR_CMD_LIFO_LEN 8 +#define HBM_RD_ERR_DATA_LIFO_LEN 8 +#define HBM_WR_PAR_CMD_LIFO_LEN 11 + +enum hl_hbm_sei_cause { + /* Command/address parity error event is split into 2 events due to + * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix + * for even HBM CK_t cycles + */ + HBM_SEI_CMD_PARITY_EVEN, + HBM_SEI_CMD_PARITY_ODD, + /* Read errors can be reflected as a combination of SERR/DERR/parity + * errors. Therefore, we define one event for all read error types. + * LKD will perform further proccessing. + */ + HBM_SEI_READ_ERR, + HBM_SEI_WRITE_DATA_PARITY_ERR, + HBM_SEI_CATTRIP, + HBM_SEI_MEM_BIST_FAIL, + HBM_SEI_DFI, + HBM_SEI_INV_TEMP_READ_OUT, + HBM_SEI_BIST_FAIL, +}; + +/* Masks for parsing hl_hbm_sei_headr fields */ +#define HBM_ECC_SERR_CNTR_MASK 0xFF +#define HBM_ECC_DERR_CNTR_MASK 0xFF00 +#define HBM_RD_PARITY_CNTR_MASK 0xFF0000 + +/* HBM index and MC index are known by the event_id */ +struct hl_hbm_sei_header { + union { + /* relevant only in case of HBM read error */ + struct { + __u8 ecc_serr_cnt; + __u8 ecc_derr_cnt; + __u8 read_par_cnt; + __u8 reserved; + }; + /* All other cases */ + __le32 cnt; + }; + __u8 sei_cause; /* enum hl_hbm_sei_cause */ + __u8 mc_channel; /* range: 0-3 */ + __u8 mc_pseudo_channel; /* range: 0-7 */ + __u8 is_critical; +}; + +#define HBM_RD_ADDR_SID_SHIFT 0 +#define HBM_RD_ADDR_SID_MASK 0x1 +#define HBM_RD_ADDR_BG_SHIFT 1 +#define HBM_RD_ADDR_BG_MASK 0x6 +#define HBM_RD_ADDR_BA_SHIFT 3 +#define HBM_RD_ADDR_BA_MASK 0x18 +#define HBM_RD_ADDR_COL_SHIFT 5 +#define HBM_RD_ADDR_COL_MASK 0x7E0 +#define HBM_RD_ADDR_ROW_SHIFT 11 +#define HBM_RD_ADDR_ROW_MASK 0x3FFF800 + +struct hbm_rd_addr { + union { + /* bit fields are only for FW use */ + struct { + u32 dbg_rd_err_addr_sid:1; + u32 dbg_rd_err_addr_bg:2; + u32 dbg_rd_err_addr_ba:2; + u32 dbg_rd_err_addr_col:6; + u32 dbg_rd_err_addr_row:15; + u32 reserved:6; + }; + __le32 rd_addr_val; + }; +}; + +#define HBM_RD_ERR_BEAT_SHIFT 2 +/* dbg_rd_err_misc fields: */ +/* Read parity is calculated per DW on every beat */ +#define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 +#define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 +#define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 +#define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 +/* ECC is calculated per PC on every beat */ +#define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 +#define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 +#define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 +#define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 + +struct hl_eq_hbm_sei_read_err_intr_info { + /* DFI_RD_ERR_REP_ADDR */ + struct hbm_rd_addr dbg_rd_err_addr; + /* DFI_RD_ERR_REP_ERR */ + union { + struct { + /* bit fields are only for FW use */ + u32 dbg_rd_err_par:8; + u32 dbg_rd_err_par_data:8; + u32 dbg_rd_err_serr:4; + u32 dbg_rd_err_derr:4; + u32 reserved:8; + }; + __le32 dbg_rd_err_misc; + }; + /* DFI_RD_ERR_REP_DM */ + __le32 dbg_rd_err_dm; + /* DFI_RD_ERR_REP_SYNDROME */ + __le32 dbg_rd_err_syndrome; + /* DFI_RD_ERR_REP_DATA */ + __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; +}; + +struct hl_eq_hbm_sei_ca_par_intr_info { + /* 14 LSBs */ + __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; + /* 18 LSBs */ + __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; +}; + +#define WR_PAR_LAST_CMD_COL_SHIFT 0 +#define WR_PAR_LAST_CMD_COL_MASK 0x3F +#define WR_PAR_LAST_CMD_BG_SHIFT 6 +#define WR_PAR_LAST_CMD_BG_MASK 0xC0 +#define WR_PAR_LAST_CMD_BA_SHIFT 8 +#define WR_PAR_LAST_CMD_BA_MASK 0x300 +#define WR_PAR_LAST_CMD_SID_SHIFT 10 +#define WR_PAR_LAST_CMD_SID_MASK 0x400 + +/* Row address isn't latched */ +struct hbm_sei_wr_cmd_address { + /* DFI_DERR_LAST_CMD */ + union { + struct { + /* bit fields are only for FW use */ + u32 col:6; + u32 bg:2; + u32 ba:2; + u32 sid:1; + u32 reserved:21; + }; + __le32 dbg_wr_cmd_addr; + }; +}; + +struct hl_eq_hbm_sei_wr_par_intr_info { + /* entry 0: WR command address from the 1st cycle prior to the error + * entry 1: WR command address from the 2nd cycle prior to the error + * and so on... + */ + struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; + /* derr[0:1] - 1st HBM cycle DERR output + * derr[2:3] - 2nd HBM cycle DERR output + */ + __u8 dbg_derr; + /* extend to reach 8B */ + __u8 pad[3]; +}; + +/* + * this struct represents the following sei causes: + * command parity, ECC double error, ECC single error, dfi error, cattrip, + * temperature read-out, read parity error and write parity error. + * some only use the header while some have extra data. + */ +struct hl_eq_hbm_sei_data { + struct hl_hbm_sei_header hdr; + union { + struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; + struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; + struct hl_eq_hbm_sei_read_err_intr_info read_err_info; + struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; + }; +}; + +/* Engine/farm arc interrupt type */ +enum hl_engine_arc_interrupt_type { + /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ + ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 +}; + +/* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ +struct hl_engine_arc_dccm_queue_full_irq { + /* Queue index value which caused DCCM QUEUE FULL */ + __le32 queue_index; + __le32 pad; +}; + +/* Data structure specifies details of QM/FARM ARC interrupt */ +struct hl_eq_engine_arc_intr_data { + /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ + __le32 engine_id; + __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ + /* More info related to the interrupt e.g. queue index + * incase of DCCM_QUEUE_FULL interrupt. + */ + __le64 payload; + __le64 pad[5]; +}; + +struct hl_eq_entry { + struct hl_eq_header hdr; + union { + struct hl_eq_ecc_data ecc_data; + struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Gaudi1 HBM */ + struct hl_eq_sm_sei_data sm_sei_data; + struct cpucp_pkt_sync_err pkt_sync_err; + struct hl_eq_fw_alive fw_alive; + struct hl_eq_intr_cause intr_cause; + struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; + struct hl_eq_razwi_info razwi_info; + struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; + struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ + struct hl_eq_engine_arc_intr_data arc_data; + __le64 data[7]; + }; +}; + +#define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) + +#define EQ_CTL_READY_SHIFT 31 +#define EQ_CTL_READY_MASK 0x80000000 + +#define EQ_CTL_EVENT_TYPE_SHIFT 16 +#define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 + +#define EQ_CTL_INDEX_SHIFT 0 +#define EQ_CTL_INDEX_MASK 0x0000FFFF + +enum pq_init_status { + PQ_INIT_STATUS_NA = 0, + PQ_INIT_STATUS_READY_FOR_CP, + PQ_INIT_STATUS_READY_FOR_HOST, + PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, + PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, + PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR +}; + +/* + * CpuCP Primary Queue Packets + * + * During normal operation, the host's kernel driver needs to send various + * messages to CpuCP, usually either to SET some value into a H/W periphery or + * to GET the current value of some H/W periphery. For example, SET the + * frequency of MME/TPC and GET the value of the thermal sensor. + * + * These messages can be initiated either by the User application or by the + * host's driver itself, e.g. power management code. In either case, the + * communication from the host's driver to CpuCP will *always* be in + * synchronous mode, meaning that the host will send a single message and poll + * until the message was acknowledged and the results are ready (if results are + * needed). + * + * This means that only a single message can be sent at a time and the host's + * driver must wait for its result before sending the next message. Having said + * that, because these are control messages which are sent in a relatively low + * frequency, this limitation seems acceptable. It's important to note that + * in case of multiple devices, messages to different devices *can* be sent + * at the same time. + * + * The message, inputs/outputs (if relevant) and fence object will be located + * on the device DDR at an address that will be determined by the host's driver. + * During device initialization phase, the host will pass to CpuCP that address. + * Most of the message types will contain inputs/outputs inside the message + * itself. The common part of each message will contain the opcode of the + * message (its type) and a field representing a fence object. + * + * When the host's driver wishes to send a message to CPU CP, it will write the + * message contents to the device DDR, clear the fence object and then write to + * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. + * + * Upon receiving the interrupt (#121), CpuCP will read the message from the + * DDR. In case the message is a SET operation, CpuCP will first perform the + * operation and then write to the fence object on the device DDR. In case the + * message is a GET operation, CpuCP will first fill the results section on the + * device DDR and then write to the fence object. If an error occurred, CpuCP + * will fill the rc field with the right error code. + * + * In the meantime, the host's driver will poll on the fence object. Once the + * host sees that the fence object is signaled, it will read the results from + * the device DDR (if relevant) and resume the code execution in the host's + * driver. + * + * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 + * so the value being put by the host's driver matches the value read by CpuCP + * + * Non-QMAN packets should be limited to values 1 through (2^8 - 1) + * + * Detailed description: + * + * CPUCP_PACKET_DISABLE_PCI_ACCESS - + * After receiving this packet the embedded CPU must NOT issue PCI + * transactions (read/write) towards the Host CPU. This also include + * sending MSI-X interrupts. + * This packet is usually sent before the device is moved to D3Hot state. + * + * CPUCP_PACKET_ENABLE_PCI_ACCESS - + * After receiving this packet the embedded CPU is allowed to issue PCI + * transactions towards the Host CPU, including sending MSI-X interrupts. + * This packet is usually send after the device is moved to D0 state. + * + * CPUCP_PACKET_TEMPERATURE_GET - + * Fetch the current temperature / Max / Max Hyst / Critical / + * Critical Hyst of a specified thermal sensor. The packet's + * arguments specify the desired sensor and the field to get. + * + * CPUCP_PACKET_VOLTAGE_GET - + * Fetch the voltage / Max / Min of a specified sensor. The packet's + * arguments specify the sensor and type. + * + * CPUCP_PACKET_CURRENT_GET - + * Fetch the current / Max / Min of a specified sensor. The packet's + * arguments specify the sensor and type. + * + * CPUCP_PACKET_FAN_SPEED_GET - + * Fetch the speed / Max / Min of a specified fan. The packet's + * arguments specify the sensor and type. + * + * CPUCP_PACKET_PWM_GET - + * Fetch the pwm value / mode of a specified pwm. The packet's + * arguments specify the sensor and type. + * + * CPUCP_PACKET_PWM_SET - + * Set the pwm value / mode of a specified pwm. The packet's + * arguments specify the sensor, type and value. + * + * CPUCP_PACKET_FREQUENCY_SET - + * Set the frequency of a specified PLL. The packet's arguments specify + * the PLL and the desired frequency. The actual frequency in the device + * might differ from the requested frequency. + * + * CPUCP_PACKET_FREQUENCY_GET - + * Fetch the frequency of a specified PLL. The packet's arguments specify + * the PLL. + * + * CPUCP_PACKET_LED_SET - + * Set the state of a specified led. The packet's arguments + * specify the led and the desired state. + * + * CPUCP_PACKET_I2C_WR - + * Write 32-bit value to I2C device. The packet's arguments specify the + * I2C bus, address and value. + * + * CPUCP_PACKET_I2C_RD - + * Read 32-bit value from I2C device. The packet's arguments specify the + * I2C bus and address. + * + * CPUCP_PACKET_INFO_GET - + * Fetch information from the device as specified in the packet's + * structure. The host's driver passes the max size it allows the CpuCP to + * write to the structure, to prevent data corruption in case of + * mismatched driver/FW versions. + * + * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed + * + * CPUCP_PACKET_UNMASK_RAZWI_IRQ - + * Unmask the given IRQ. The IRQ number is specified in the value field. + * The packet is sent after receiving an interrupt and printing its + * relevant information. + * + * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - + * Unmask the given IRQs. The IRQs numbers are specified in an array right + * after the cpucp_packet structure, where its first element is the array + * length. The packet is sent after a soft reset was done in order to + * handle any interrupts that were sent during the reset process. + * + * CPUCP_PACKET_TEST - + * Test packet for CpuCP connectivity. The CPU will put the fence value + * in the result field. + * + * CPUCP_PACKET_FREQUENCY_CURR_GET - + * Fetch the current frequency of a specified PLL. The packet's arguments + * specify the PLL. + * + * CPUCP_PACKET_MAX_POWER_GET - + * Fetch the maximal power of the device. + * + * CPUCP_PACKET_MAX_POWER_SET - + * Set the maximal power of the device. The packet's arguments specify + * the power. + * + * CPUCP_PACKET_EEPROM_DATA_GET - + * Get EEPROM data from the CpuCP kernel. The buffer is specified in the + * addr field. The CPU will put the returned data size in the result + * field. In addition, the host's driver passes the max size it allows the + * CpuCP to write to the structure, to prevent data corruption in case of + * mismatched driver/FW versions. + * + * CPUCP_PACKET_NIC_INFO_GET - + * Fetch information from the device regarding the NIC. the host's driver + * passes the max size it allows the CpuCP to write to the structure, to + * prevent data corruption in case of mismatched driver/FW versions. + * + * CPUCP_PACKET_TEMPERATURE_SET - + * Set the value of the offset property of a specified thermal sensor. + * The packet's arguments specify the desired sensor and the field to + * set. + * + * CPUCP_PACKET_VOLTAGE_SET - + * Trigger the reset_history property of a specified voltage sensor. + * The packet's arguments specify the desired sensor and the field to + * set. + * + * CPUCP_PACKET_CURRENT_SET - + * Trigger the reset_history property of a specified current sensor. + * The packet's arguments specify the desired sensor and the field to + * set. + * + * CPUCP_PACKET_PCIE_THROUGHPUT_GET - + * Get throughput of PCIe. + * The packet's arguments specify the transaction direction (TX/RX). + * The window measurement is 10[msec], and the return value is in KB/sec. + * + * CPUCP_PACKET_PCIE_REPLAY_CNT_GET + * Replay count measures number of "replay" events, which is basicly + * number of retries done by PCIe. + * + * CPUCP_PACKET_TOTAL_ENERGY_GET - + * Total Energy is measurement of energy from the time FW Linux + * is loaded. It is calculated by multiplying the average power + * by time (passed from armcp start). The units are in MilliJouls. + * + * CPUCP_PACKET_PLL_INFO_GET - + * Fetch frequencies of PLL from the required PLL IP. + * The packet's arguments specify the device PLL type + * Pll type is the PLL from device pll_index enum. + * The result is composed of 4 outputs, each is 16-bit + * frequency in MHz. + * + * CPUCP_PACKET_POWER_GET - + * Fetch the present power consumption of the device (Current * Voltage). + * + * CPUCP_PACKET_NIC_PFC_SET - + * Enable/Disable the NIC PFC feature. The packet's arguments specify the + * NIC port, relevant lanes to configure and one bit indication for + * enable/disable. + * + * CPUCP_PACKET_NIC_FAULT_GET - + * Fetch the current indication for local/remote faults from the NIC MAC. + * The result is 32-bit value of the relevant register. + * + * CPUCP_PACKET_NIC_LPBK_SET - + * Enable/Disable the MAC loopback feature. The packet's arguments specify + * the NIC port, relevant lanes to configure and one bit indication for + * enable/disable. + * + * CPUCP_PACKET_NIC_MAC_INIT - + * Configure the NIC MAC channels. The packet's arguments specify the + * NIC port and the speed. + * + * CPUCP_PACKET_MSI_INFO_SET - + * set the index number for each supported msi type going from + * host to device + * + * CPUCP_PACKET_NIC_XPCS91_REGS_GET - + * Fetch the un/correctable counters values from the NIC MAC. + * + * CPUCP_PACKET_NIC_STAT_REGS_GET - + * Fetch various NIC MAC counters from the NIC STAT. + * + * CPUCP_PACKET_NIC_STAT_REGS_CLR - + * Clear the various NIC MAC counters in the NIC STAT. + * + * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - + * Fetch all NIC MAC counters from the NIC STAT. + * + * CPUCP_PACKET_IS_IDLE_CHECK - + * Check if the device is IDLE in regard to the DMA/compute engines + * and QMANs. The f/w will return a bitmask where each bit represents + * a different engine or QMAN according to enum cpucp_idle_mask. + * The bit will be 1 if the engine is NOT idle. + * + * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - + * Fetch all HBM replaced-rows and prending to be replaced rows data. + * + * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - + * Fetch status of HBM rows pending replacement and need a reboot to + * be replaced. + * + * CPUCP_PACKET_POWER_SET - + * Resets power history of device to 0 + * + * CPUCP_PACKET_ENGINE_CORE_ASID_SET - + * Packet to perform engine core ASID configuration + * + * CPUCP_PACKET_SEC_ATTEST_GET - + * Get the attestaion data that is collected during various stages of the + * boot sequence. the attestation data is also hashed with some unique + * number (nonce) provided by the host to prevent replay attacks. + * public key and certificate also provided as part of the FW response. + * + * CPUCP_PACKET_MONITOR_DUMP_GET - + * Get monitors registers dump from the CpuCP kernel. + * The CPU will put the registers dump in the a buffer allocated by the driver + * which address is passed via the CpuCp packet. In addition, the host's driver + * passes the max size it allows the CpuCP to write to the structure, to prevent + * data corruption in case of mismatched driver/FW versions. + * Relevant only to Gaudi. + * + * CPUCP_PACKET_ACTIVE_STATUS_SET - + * LKD sends FW indication whether device is free or in use, this indication is reported + * also to the BMC. + */ + +enum cpucp_packet_id { + CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ + CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ + CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ + CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ + CPUCP_PACKET_CURRENT_GET, /* sysfs */ + CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ + CPUCP_PACKET_PWM_GET, /* sysfs */ + CPUCP_PACKET_PWM_SET, /* sysfs */ + CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ + CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ + CPUCP_PACKET_LED_SET, /* debugfs */ + CPUCP_PACKET_I2C_WR, /* debugfs */ + CPUCP_PACKET_I2C_RD, /* debugfs */ + CPUCP_PACKET_INFO_GET, /* IOCTL */ + CPUCP_PACKET_FLASH_PROGRAM_REMOVED, + CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ + CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ + CPUCP_PACKET_TEST, /* internal */ + CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ + CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ + CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ + CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ + CPUCP_PACKET_NIC_INFO_GET, /* internal */ + CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ + CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ + CPUCP_PACKET_CURRENT_SET, /* sysfs */ + CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ + CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ + CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ + CPUCP_PACKET_PLL_INFO_GET, /* internal */ + CPUCP_PACKET_NIC_STATUS, /* internal */ + CPUCP_PACKET_POWER_GET, /* internal */ + CPUCP_PACKET_NIC_PFC_SET, /* internal */ + CPUCP_PACKET_NIC_FAULT_GET, /* internal */ + CPUCP_PACKET_NIC_LPBK_SET, /* internal */ + CPUCP_PACKET_NIC_MAC_CFG, /* internal */ + CPUCP_PACKET_MSI_INFO_SET, /* internal */ + CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ + CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ + CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ + CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ + CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ + CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ + CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ + CPUCP_PACKET_POWER_SET, /* internal */ + CPUCP_PACKET_RESERVED, /* not used */ + CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ + CPUCP_PACKET_RESERVED2, /* not used */ + CPUCP_PACKET_SEC_ATTEST_GET, /* internal */ + CPUCP_PACKET_RESERVED3, /* not used */ + CPUCP_PACKET_RESERVED4, /* not used */ + CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ + CPUCP_PACKET_RESERVED5, /* not used */ + CPUCP_PACKET_RESERVED6, /* not used */ + CPUCP_PACKET_RESERVED7, /* not used */ + CPUCP_PACKET_RESERVED8, /* not used */ + CPUCP_PACKET_RESERVED9, /* not used */ + CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */ + CPUCP_PACKET_ID_MAX /* must be last */ +}; + +#define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 + +#define CPUCP_PKT_CTL_RC_SHIFT 12 +#define CPUCP_PKT_CTL_RC_MASK 0x0000F000 + +#define CPUCP_PKT_CTL_OPCODE_SHIFT 16 +#define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 + +#define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 +#define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull +#define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 +#define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull +#define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 +#define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull +#define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 +#define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull + +#define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 +#define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull +#define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 +#define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull + +#define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 +#define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull +#define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 +#define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull + +#define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 +#define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull +#define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 +#define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull + +/* heartbeat status bits */ +#define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 +#define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 + +struct cpucp_packet { + union { + __le64 value; /* For SET packets */ + __le64 result; /* For GET packets */ + __le64 addr; /* For PQ */ + }; + + __le32 ctl; + + __le32 fence; /* Signal to host that message is completed */ + + union { + struct {/* For temperature/current/voltage/fan/pwm get/set */ + __le16 sensor_index; + __le16 type; + }; + + struct { /* For I2C read/write */ + __u8 i2c_bus; + __u8 i2c_addr; + __u8 i2c_reg; + /* + * In legacy implemetations, i2c_len was not present, + * was unused and just added as pad. + * So if i2c_len is 0, it is treated as legacy + * and r/w 1 Byte, else if i2c_len is specified, + * its treated as new multibyte r/w support. + */ + __u8 i2c_len; + }; + + struct {/* For PLL info fetch */ + __le16 pll_type; + /* TODO pll_reg is kept temporary before removal */ + __le16 pll_reg; + }; + + /* For any general request */ + __le32 index; + + /* For frequency get/set */ + __le32 pll_index; + + /* For led set */ + __le32 led_index; + + /* For get CpuCP info/EEPROM data/NIC info */ + __le32 data_max_size; + + /* + * For any general status bitmask. Shall be used whenever the + * result cannot be used to hold general purpose data. + */ + __le32 status_mask; + + /* random, used once number, for security packets */ + __le32 nonce; + }; + + /* For NIC requests */ + __le32 port_index; +}; + +struct cpucp_unmask_irq_arr_packet { + struct cpucp_packet cpucp_pkt; + __le32 length; + __le32 irqs[]; +}; + +struct cpucp_nic_status_packet { + struct cpucp_packet cpucp_pkt; + __le32 length; + __le32 data[]; +}; + +struct cpucp_array_data_packet { + struct cpucp_packet cpucp_pkt; + __le32 length; + __le32 data[]; +}; + +enum cpucp_led_index { + CPUCP_LED0_INDEX = 0, + CPUCP_LED1_INDEX, + CPUCP_LED2_INDEX +}; + +/* + * enum cpucp_packet_rc - Error return code + * @cpucp_packet_success -> in case of success. + * @cpucp_packet_invalid -> this is to support Goya and Gaudi platform. + * @cpucp_packet_fault -> in case of processing error like failing to + * get device binding or semaphore etc. + * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. This is + * supported Greco onwards. + * @cpucp_packet_invalid_params -> when checking parameter like length of buffer + * or attribute value etc. Supported Greco onwards. + * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. + */ +enum cpucp_packet_rc { + cpucp_packet_success, + cpucp_packet_invalid, + cpucp_packet_fault, + cpucp_packet_invalid_pkt, + cpucp_packet_invalid_params, + cpucp_packet_rc_max +}; + +/* + * cpucp_temp_type should adhere to hwmon_temp_attributes + * defined in Linux kernel hwmon.h file + */ +enum cpucp_temp_type { + cpucp_temp_input, + cpucp_temp_min = 4, + cpucp_temp_min_hyst, + cpucp_temp_max = 6, + cpucp_temp_max_hyst, + cpucp_temp_crit, + cpucp_temp_crit_hyst, + cpucp_temp_offset = 19, + cpucp_temp_lowest = 21, + cpucp_temp_highest = 22, + cpucp_temp_reset_history = 23, + cpucp_temp_warn = 24, + cpucp_temp_max_crit = 25, + cpucp_temp_max_warn = 26, +}; + +enum cpucp_in_attributes { + cpucp_in_input, + cpucp_in_min, + cpucp_in_max, + cpucp_in_lowest = 6, + cpucp_in_highest = 7, + cpucp_in_reset_history +}; + +enum cpucp_curr_attributes { + cpucp_curr_input, + cpucp_curr_min, + cpucp_curr_max, + cpucp_curr_lowest = 6, + cpucp_curr_highest = 7, + cpucp_curr_reset_history +}; + +enum cpucp_fan_attributes { + cpucp_fan_input, + cpucp_fan_min = 2, + cpucp_fan_max +}; + +enum cpucp_pwm_attributes { + cpucp_pwm_input, + cpucp_pwm_enable +}; + +enum cpucp_pcie_throughput_attributes { + cpucp_pcie_throughput_tx, + cpucp_pcie_throughput_rx +}; + +/* TODO temporary kept before removal */ +enum cpucp_pll_reg_attributes { + cpucp_pll_nr_reg, + cpucp_pll_nf_reg, + cpucp_pll_od_reg, + cpucp_pll_div_factor_reg, + cpucp_pll_div_sel_reg +}; + +/* TODO temporary kept before removal */ +enum cpucp_pll_type_attributes { + cpucp_pll_cpu, + cpucp_pll_pci, +}; + +/* + * cpucp_power_type aligns with hwmon_power_attributes + * defined in Linux kernel hwmon.h file + */ +enum cpucp_power_type { + CPUCP_POWER_INPUT = 8, + CPUCP_POWER_INPUT_HIGHEST = 9, + CPUCP_POWER_RESET_INPUT_HISTORY = 11 +}; + +/* + * MSI type enumeration table for all ASICs and future SW versions. + * For future ASIC-LKD compatibility, we can only add new enumerations. + * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). + * Changing the order of entries or removing entries is not allowed. + */ +enum cpucp_msi_type { + CPUCP_EVENT_QUEUE_MSI_TYPE, + CPUCP_NIC_PORT1_MSI_TYPE, + CPUCP_NIC_PORT3_MSI_TYPE, + CPUCP_NIC_PORT5_MSI_TYPE, + CPUCP_NIC_PORT7_MSI_TYPE, + CPUCP_NIC_PORT9_MSI_TYPE, + CPUCP_NUM_OF_MSI_TYPES +}; + +/* + * PLL enumeration table used for all ASICs and future SW versions. + * For future ASIC-LKD compatibility, we can only add new enumerations. + * at the end of the table. + * Changing the order of entries or removing entries is not allowed. + */ +enum pll_index { + CPU_PLL = 0, + PCI_PLL = 1, + NIC_PLL = 2, + DMA_PLL = 3, + MESH_PLL = 4, + MME_PLL = 5, + TPC_PLL = 6, + IF_PLL = 7, + SRAM_PLL = 8, + NS_PLL = 9, + HBM_PLL = 10, + MSS_PLL = 11, + DDR_PLL = 12, + VID_PLL = 13, + BANK_PLL = 14, + MMU_PLL = 15, + IC_PLL = 16, + MC_PLL = 17, + EMMC_PLL = 18, + PLL_MAX +}; + +enum rl_index { + TPC_RL = 0, + MME_RL, + EDMA_RL, +}; + +enum pvt_index { + PVT_SW, + PVT_SE, + PVT_NW, + PVT_NE +}; + +/* Event Queue Packets */ + +struct eq_generic_event { + __le64 data[7]; +}; + +/* + * CpuCP info + */ + +#define CARD_NAME_MAX_LEN 16 +#define CPUCP_MAX_SENSORS 128 +#define CPUCP_MAX_NICS 128 +#define CPUCP_LANES_PER_NIC 4 +#define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 +#define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) +#define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) +#define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) +#define CPUCP_HBM_ROW_REPLACE_MAX 32 + +struct cpucp_sensor { + __le32 type; + __le32 flags; +}; + +/** + * struct cpucp_card_types - ASIC card type. + * @cpucp_card_type_pci: PCI card. + * @cpucp_card_type_pmc: PCI Mezzanine Card. + */ +enum cpucp_card_types { + cpucp_card_type_pci, + cpucp_card_type_pmc +}; + +#define CPUCP_SEC_CONF_ENABLED_SHIFT 0 +#define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 + +#define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 +#define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 + +#define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 +#define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 + +/** + * struct cpucp_security_info - Security information. + * @config: configuration bit field + * @keys_num: number of stored keys + * @revoked_keys: revoked keys bit field + * @min_svn: minimal security version + */ +struct cpucp_security_info { + __u8 config; + __u8 keys_num; + __u8 revoked_keys; + __u8 min_svn; +}; + +/** + * struct cpucp_info - Info from CpuCP that is necessary to the host's driver + * @sensors: available sensors description. + * @kernel_version: CpuCP linux kernel version. + * @reserved: reserved field. + * @card_type: card configuration type. + * @card_location: in a server, each card has different connections topology + * depending on its location (relevant for PMC card type) + * @cpld_version: CPLD programmed F/W version. + * @infineon_version: Infineon main DC-DC version. + * @fuse_version: silicon production FUSE information. + * @thermal_version: thermald S/W version. + * @cpucp_version: CpuCP S/W version. + * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. + * @dram_size: available DRAM size. + * @card_name: card name that will be displayed in HWMON subsystem on the host + * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance + * (0 = functional, 1 = binned) + * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance + * (0 = functional, 1 = binned), maximum 1 per dcore + * @sram_binning: Categorize SRAM functionality + * (0 = fully functional, 1 = lower-half is not functional, + * 2 = upper-half is not functional) + * @sec_info: security information + * @pll_map: Bit map of supported PLLs for current ASIC version. + * @mme_binning_mask: MME binning mask, + * bits [0:6] <==> dcore0 mme fma + * bits [7:13] <==> dcore1 mme fma + * bits [14:20] <==> dcore0 mme ima + * bits [21:27] <==> dcore1 mme ima + * For each group, if the 6th bit is set then first 5 bits + * represent the col's idx [0-31], otherwise these bits are + * ignored, and col idx 32 is binned. 7th bit is don't care. + * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance + * (0 = functional 1 = binned) + * @memory_repair_flag: eFuse flag indicating memory repair + * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance + * (0 = functional 1 = binned) + * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance + * (0 = functional 1 = binned) + * @interposer_version: Interposer version programmed in eFuse + * @substrate_version: Substrate version programmed in eFuse + * @fw_os_version: Firmware OS Version + */ +struct cpucp_info { + struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; + __u8 kernel_version[VERSION_MAX_LEN]; + __le32 reserved; + __le32 card_type; + __le32 card_location; + __le32 cpld_version; + __le32 infineon_version; + __u8 fuse_version[VERSION_MAX_LEN]; + __u8 thermal_version[VERSION_MAX_LEN]; + __u8 cpucp_version[VERSION_MAX_LEN]; + __le32 infineon_second_stage_version; + __le64 dram_size; + char card_name[CARD_NAME_MAX_LEN]; + __le64 tpc_binning_mask; + __le64 decoder_binning_mask; + __u8 sram_binning; + __u8 dram_binning_mask; + __u8 memory_repair_flag; + __u8 edma_binning_mask; + __u8 xbar_binning_mask; + __u8 interposer_version; + __u8 substrate_version; + __u8 reserved2; + struct cpucp_security_info sec_info; + __le32 reserved3; + __u8 pll_map[PLL_MAP_LEN]; + __le64 mme_binning_mask; + __u8 fw_os_version[VERSION_MAX_LEN]; +}; + +struct cpucp_mac_addr { + __u8 mac_addr[ETH_ALEN]; +}; + +enum cpucp_serdes_type { + TYPE_1_SERDES_TYPE, + TYPE_2_SERDES_TYPE, + HLS1_SERDES_TYPE, + HLS1H_SERDES_TYPE, + HLS2_SERDES_TYPE, + UNKNOWN_SERDES_TYPE, + MAX_NUM_SERDES_TYPE = UNKNOWN_SERDES_TYPE +}; + +struct cpucp_nic_info { + struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; + __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; + __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; + __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; + __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; + __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; + __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; + __le16 serdes_type; /* enum cpucp_serdes_type */ + __le16 tx_swap_map[CPUCP_MAX_NICS]; + __u8 reserved[6]; +}; + +#define PAGE_DISCARD_MAX 64 + +struct page_discard_info { + __u8 num_entries; + __u8 reserved[7]; + __le32 mmu_page_idx[PAGE_DISCARD_MAX]; +}; + +/* + * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". + * @integer: the integer part of the SER value; + * @exp: the exponent part of the SER value. + */ +struct ser_val { + __le16 integer; + __le16 exp; +}; + +/* + * struct cpucp_nic_status - describes the status of a NIC port. + * @port: NIC port index. + * @bad_format_cnt: e.g. CRC. + * @responder_out_of_sequence_psn_cnt: e.g NAK. + * @high_ber_reinit_cnt: link reinit due to high BER. + * @correctable_err_cnt: e.g. bit-flip. + * @uncorrectable_err_cnt: e.g. MAC errors. + * @retraining_cnt: re-training counter. + * @up: is port up. + * @pcs_link: has PCS link. + * @phy_ready: is PHY ready. + * @auto_neg: is Autoneg enabled. + * @timeout_retransmission_cnt: timeout retransmission events + * @high_ber_cnt: high ber events + */ +struct cpucp_nic_status { + __le32 port; + __le32 bad_format_cnt; + __le32 responder_out_of_sequence_psn_cnt; + __le32 high_ber_reinit; + __le32 correctable_err_cnt; + __le32 uncorrectable_err_cnt; + __le32 retraining_cnt; + __u8 up; + __u8 pcs_link; + __u8 phy_ready; + __u8 auto_neg; + __le32 timeout_retransmission_cnt; + __le32 high_ber_cnt; +}; + +enum cpucp_hbm_row_replace_cause { + REPLACE_CAUSE_DOUBLE_ECC_ERR, + REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, +}; + +struct cpucp_hbm_row_info { + __u8 hbm_idx; + __u8 pc; + __u8 sid; + __u8 bank_idx; + __le16 row_addr; + __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ + __u8 pad; +}; + +struct cpucp_hbm_row_replaced_rows_info { + __le16 num_replaced_rows; + __u8 pad[6]; + struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; +}; + +enum cpu_reset_status { + CPU_RST_STATUS_NA = 0, + CPU_RST_STATUS_SOFT_RST_DONE = 1, +}; + +#define SEC_PCR_DATA_BUF_SZ 256 +#define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ +#define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ +#define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ +#define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ + +/* + * struct cpucp_sec_attest_info - attestation report of the boot + * @pcr_data: raw values of the PCR registers + * @pcr_num_reg: number of PCR registers in the pcr_data array + * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) + * @nonce: number only used once. random number provided by host. this also + * passed to the quote command as a qualifying data. + * @pcr_quote_len: length of the attestation quote data (bytes) + * @pcr_quote: attestation report data structure + * @quote_sig_len: length of the attestation report signature (bytes) + * @quote_sig: signature structure of the attestation report + * @pub_data_len: length of the public data (bytes) + * @public_data: public key for the signed attestation + * (outPublic + name + qualifiedName) + * @certificate_len: length of the certificate (bytes) + * @certificate: certificate for the attestation signing key + */ +struct cpucp_sec_attest_info { + __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; + __u8 pcr_num_reg; + __u8 pcr_reg_len; + __le16 pad0; + __le32 nonce; + __le16 pcr_quote_len; + __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; + __u8 quote_sig_len; + __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; + __le16 pub_data_len; + __u8 public_data[SEC_PUB_DATA_BUF_SZ]; + __le16 certificate_len; + __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; +}; + +/* + * struct cpucp_dev_info_signed - device information signed by a secured device + * @info: device information structure as defined above + * @nonce: number only used once. random number provided by host. this number is + * hashed and signed along with the device information. + * @info_sig_len: length of the attestation signature (bytes) + * @info_sig: signature of the info + nonce data. + * @pub_data_len: length of the public data (bytes) + * @public_data: public key info signed info data + * (outPublic + name + qualifiedName) + * @certificate_len: length of the certificate (bytes) + * @certificate: certificate for the signing key + */ +struct cpucp_dev_info_signed { + struct cpucp_info info; /* assumed to be 64bit aligned */ + __le32 nonce; + __le32 pad0; + __u8 info_sig_len; + __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; + __le16 pub_data_len; + __u8 public_data[SEC_PUB_DATA_BUF_SZ]; + __le16 certificate_len; + __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; +}; + +/* + * struct dcore_monitor_regs_data - DCORE monitor regs data. + * the structure follows sync manager block layout. relevant only to Gaudi. + * @mon_pay_addrl: array of payload address low bits. + * @mon_pay_addrh: array of payload address high bits. + * @mon_pay_data: array of payload data. + * @mon_arm: array of monitor arm. + * @mon_status: array of monitor status. + */ +struct dcore_monitor_regs_data { + __le32 mon_pay_addrl[512]; + __le32 mon_pay_addrh[512]; + __le32 mon_pay_data[512]; + __le32 mon_arm[512]; + __le32 mon_status[512]; +}; + +/* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */ +struct cpucp_monitor_dump { + struct dcore_monitor_regs_data sync_mngr_w_s; + struct dcore_monitor_regs_data sync_mngr_e_s; + struct dcore_monitor_regs_data sync_mngr_w_n; + struct dcore_monitor_regs_data sync_mngr_e_n; +}; + +#endif /* CPUCP_IF_H */ diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h new file mode 100644 index 000000000..e0ea51cc7 --- /dev/null +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -0,0 +1,702 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef HL_BOOT_IF_H +#define HL_BOOT_IF_H + +#define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */ +#define HL_POWER9_HOST_MAGIC 0x1DA30009 + +#define BOOT_FIT_SRAM_OFFSET 0x200000 + +#define VERSION_MAX_LEN 128 + +enum cpu_boot_err { + CPU_BOOT_ERR_DRAM_INIT_FAIL = 0, + CPU_BOOT_ERR_FIT_CORRUPTED = 1, + CPU_BOOT_ERR_TS_INIT_FAIL = 2, + CPU_BOOT_ERR_DRAM_SKIPPED = 3, + CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4, + CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5, + CPU_BOOT_ERR_NIC_FW_FAIL = 6, + CPU_BOOT_ERR_SECURITY_NOT_RDY = 7, + CPU_BOOT_ERR_SECURITY_FAIL = 8, + CPU_BOOT_ERR_EFUSE_FAIL = 9, + CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10, + CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11, + CPU_BOOT_ERR_PLL_FAIL = 12, + CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13, + CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18, + CPU_BOOT_ERR_BINNING_FAIL = 19, + CPU_BOOT_ERR_TPM_FAIL = 20, + CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21, + CPU_BOOT_ERR_EEPROM_FAIL = 22, + CPU_BOOT_ERR_ENABLED = 31, + CPU_BOOT_ERR_SCND_EN = 63, + CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */ +}; + +/* + * CPU error bits in BOOT_ERROR registers + * + * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. + * DRAM is not reliable to use. + * + * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the + * image provided by the host has failed. + * + * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. + * Boot continues as usual, but keep in + * mind this is a warning. + * + * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. + * Skipping DRAM initialization has been + * requested (e.g. strap, command, etc.) + * and FW skipped the DRAM initialization. + * Host can initialize the DRAM. + * + * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. + * Meaning the BMC data might not be + * available until reset. + * + * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. + * BMC has not provided the NIC data yet. + * Once provided this bit will be cleared. + * + * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. + * The NIC FW loading and initialization + * failed. This means NICs are not usable. + * + * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been + * started, but is not ready yet - chip + * cannot be accessed. + * + * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. + * The tasks are security init (root of + * trust), boot authentication (chain of + * trust), data packets authentication. + * + * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. + * The PCI device ID might be wrong. + * + * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. + * It mean that ppboot checksum + * verification for the preboot primary + * image has failed to match expected + * checksum. Trying to program image again + * might solve this. + * + * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. + * It mean that ppboot checksum + * verification for the preboot secondary + * image has failed to match expected + * checksum. Trying to program image again + * might solve this. + * + * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one + * of the PLLs remains in REF_CLK + * + * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support + * should be contacted. + * + * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR Critical error was detected during + * the execution of ppboot or preboot. + * for example: stack overflow. + * + * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning + * malfunctioning components might still be + * in use. + * + * CPU_BOOT_ERR0_TPM_FAIL TPM verification flow failed. + * + * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL Failed to set threshold for tmperature + * sensor. + * + * CPU_BOOT_ERR_EEPROM_FAIL Failed reading EEPROM data. Defaults + * are used. + * + * CPU_BOOT_ERR0_ENABLED Error registers enabled. + * This is a main indication that the + * running FW populates the error + * registers. Meaning the error bits are + * not garbage, but actual error statuses. + */ +#define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) +#define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << CPU_BOOT_ERR_FIT_CORRUPTED) +#define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << CPU_BOOT_ERR_TS_INIT_FAIL) +#define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << CPU_BOOT_ERR_DRAM_SKIPPED) +#define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED) +#define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY) +#define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << CPU_BOOT_ERR_NIC_FW_FAIL) +#define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY) +#define CPU_BOOT_ERR0_SECURITY_FAIL (1 << CPU_BOOT_ERR_SECURITY_FAIL) +#define CPU_BOOT_ERR0_EFUSE_FAIL (1 << CPU_BOOT_ERR_EFUSE_FAIL) +#define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL) +#define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL) +#define CPU_BOOT_ERR0_PLL_FAIL (1 << CPU_BOOT_ERR_PLL_FAIL) +#define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) +#define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR) +#define CPU_BOOT_ERR0_BINNING_FAIL (1 << CPU_BOOT_ERR_BINNING_FAIL) +#define CPU_BOOT_ERR0_TPM_FAIL (1 << CPU_BOOT_ERR_TPM_FAIL) +#define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL (1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL) +#define CPU_BOOT_ERR0_EEPROM_FAIL (1 << CPU_BOOT_ERR_EEPROM_FAIL) +#define CPU_BOOT_ERR0_ENABLED (1 << CPU_BOOT_ERR_ENABLED) +#define CPU_BOOT_ERR1_ENABLED (1 << CPU_BOOT_ERR_ENABLED) + +enum cpu_boot_dev_sts { + CPU_BOOT_DEV_STS_SECURITY_EN = 0, + CPU_BOOT_DEV_STS_DEBUG_EN = 1, + CPU_BOOT_DEV_STS_WATCHDOG_EN = 2, + CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3, + CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4, + CPU_BOOT_DEV_STS_E2E_CRED_EN = 5, + CPU_BOOT_DEV_STS_HBM_CRED_EN = 6, + CPU_BOOT_DEV_STS_RL_EN = 7, + CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8, + CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9, + CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10, + CPU_BOOT_DEV_STS_PLL_INFO_EN = 11, + CPU_BOOT_DEV_STS_SP_SRAM_EN = 12, + CPU_BOOT_DEV_STS_CLK_GATE_EN = 13, + CPU_BOOT_DEV_STS_HBM_ECC_EN = 14, + CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15, + CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16, + CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17, + CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18, + CPU_BOOT_DEV_STS_DYN_PLL_EN = 19, + CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20, + CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21, + CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22, + CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23, + CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24, + CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25, + CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26, + CPU_BOOT_DEV_STS_ENABLED = 31, + CPU_BOOT_DEV_STS_SCND_EN = 63, + CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */ +}; + +/* + * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers + * + * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. + * This is an indication for security + * enabled in FW, which means that + * all conditions for security are met: + * device is indicated as security enabled, + * registers are protected, and device + * uses keys for image verification. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. + * Enabled when JTAG or DEBUG is enabled + * in FW. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. + * Watchdog is enabled in FW. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. + * DRAM initialization has been done in FW. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. + * If set, it means that during boot, + * FW waited for BMC data. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. + * FW initialized E2E credits. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. + * FW initialized HBM credits. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. + * FW initialized rate limiter. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. + * FW initialized SRAM scrambler. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. + * FW initialized DRAM scrambler. + * Initialized in: u-boot + * + * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. + * FW has the hard reset procedure + * implemented. This means that FW will + * perform hard reset procedure on + * receiving the halt-machine event. + * Initialized in: preboot, u-boot, linux + * + * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available + * for use. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. + * FW initialized Clock Gating. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. + * FW handles HBM ECC indications. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd + * is set to the PI counter. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication + * protocol is enabled. + * Initialized in: preboot + * + * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. + * This bit if set, means the iATU has been + * configured and is ready for use. + * Initialized in: ppboot + * + * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and + * any access to them is done via the FW. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. + * FW sends to host a bitmap of supported + * PLLs. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from + * previleged entity. FW sets this status + * bit for host. If this bit is set then + * GIC can not be accessed from host. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running + * index for each new event sent to host. + * This is used as a method in host to + * identify that the waiting event in + * queue is actually a new event which + * was not served before. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to + * prevent IRQs overriding each other. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN + * NIC STAT and XPCS91 access is restricted + * and is done via FW only. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN + * NIC STAT get all is supported. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN + * F/W checks if the device is idle by reading defined set + * of registers. It returns a bitmask of all the engines, + * where a bit is set if the engine is not idle. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_MAP_HWMON_EN + * If set, means f/w supports proprietary + * HWMON enum mapping to cpucp enums. + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. + * This is a main indication that the + * running FW populates the device status + * register. Meaning the device status + * bits are not garbage, but actual + * statuses. + * Initialized in: preboot + * + */ +#define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << CPU_BOOT_DEV_STS_SECURITY_EN) +#define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << CPU_BOOT_DEV_STS_DEBUG_EN) +#define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN) +#define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN) +#define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN) +#define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN) +#define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN) +#define CPU_BOOT_DEV_STS0_RL_EN (1 << CPU_BOOT_DEV_STS_RL_EN) +#define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN) +#define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN) +#define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN) +#define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN) +#define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN) +#define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN) +#define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN) +#define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN) +#define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN) +#define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN) +#define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN) +#define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN) +#define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN) +#define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN) +#define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN) +#define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN) +#define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN) +#define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN) +#define CPU_BOOT_DEV_STS0_MAP_HWMON_EN (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN) +#define CPU_BOOT_DEV_STS0_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) +#define CPU_BOOT_DEV_STS1_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) + +enum cpu_boot_status { + CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ + CPU_BOOT_STATUS_IN_WFE = 1, + CPU_BOOT_STATUS_DRAM_RDY = 2, + CPU_BOOT_STATUS_SRAM_AVAIL = 3, + CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ + CPU_BOOT_STATUS_IN_PREBOOT = 5, + CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ + CPU_BOOT_STATUS_IN_UBOOT = 7, + CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ + CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ + /* U-Boot console prompt activated, commands are not processed */ + CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, + /* Finished NICs init, reported after DRAM and NICs */ + CPU_BOOT_STATUS_NIC_FW_RDY = 11, + CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ + CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ + CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ + /* Last boot loader progress status, ready to receive commands */ + CPU_BOOT_STATUS_READY_TO_BOOT = 15, + /* Internal Boot finished, ready for boot-fit */ + CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, + /* Internal Security has been initialized, device can be accessed */ + CPU_BOOT_STATUS_SECURITY_READY = 17, +}; + +enum kmd_msg { + KMD_MSG_NA = 0, + KMD_MSG_GOTO_WFE, + KMD_MSG_FIT_RDY, + KMD_MSG_SKIP_BMC, + RESERVED, + KMD_MSG_RST_DEV, + KMD_MSG_LAST +}; + +enum cpu_msg_status { + CPU_MSG_CLR = 0, + CPU_MSG_OK, + CPU_MSG_ERR, +}; + +/* communication registers mapping - consider ABI when changing */ +struct cpu_dyn_regs { + __le32 cpu_pq_base_addr_low; + __le32 cpu_pq_base_addr_high; + __le32 cpu_pq_length; + __le32 cpu_pq_init_status; + __le32 cpu_eq_base_addr_low; + __le32 cpu_eq_base_addr_high; + __le32 cpu_eq_length; + __le32 cpu_eq_ci; + __le32 cpu_cq_base_addr_low; + __le32 cpu_cq_base_addr_high; + __le32 cpu_cq_length; + __le32 cpu_pf_pq_pi; + __le32 cpu_boot_dev_sts0; + __le32 cpu_boot_dev_sts1; + __le32 cpu_boot_err0; + __le32 cpu_boot_err1; + __le32 cpu_boot_status; + __le32 fw_upd_sts; + __le32 fw_upd_cmd; + __le32 fw_upd_pending_sts; + __le32 fuse_ver_offset; + __le32 preboot_ver_offset; + __le32 uboot_ver_offset; + __le32 hw_state; + __le32 kmd_msg_to_cpu; + __le32 cpu_cmd_status_to_host; + __le32 gic_host_pi_upd_irq; + __le32 gic_tpc_qm_irq_ctrl; + __le32 gic_mme_qm_irq_ctrl; + __le32 gic_dma_qm_irq_ctrl; + __le32 gic_nic_qm_irq_ctrl; + __le32 gic_dma_core_irq_ctrl; + __le32 gic_host_halt_irq; + __le32 gic_host_ints_irq; + __le32 gic_host_soft_rst_irq; + __le32 gic_rot_qm_irq_ctrl; + __le32 cpu_rst_status; + __le32 eng_arc_irq_ctrl; + __le32 reserved1[20]; /* reserve for future use */ +}; + +/* TODO: remove the desc magic after the code is updated to use message */ +/* HCDM - Habana Communications Descriptor Magic */ +#define HL_COMMS_DESC_MAGIC 0x4843444D +#define HL_COMMS_DESC_VER 1 + +/* HCMv - Habana Communications Message + header version */ +#define HL_COMMS_MSG_MAGIC_VALUE 0x48434D00 +#define HL_COMMS_MSG_MAGIC_MASK 0xFFFFFF00 +#define HL_COMMS_MSG_MAGIC_VER_MASK 0xFF + +#define HL_COMMS_MSG_MAGIC_VER(ver) (HL_COMMS_MSG_MAGIC_VALUE | \ + ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) +#define HL_COMMS_MSG_MAGIC_V0 HL_COMMS_DESC_MAGIC +#define HL_COMMS_MSG_MAGIC_V1 HL_COMMS_MSG_MAGIC_VER(1) + +#define HL_COMMS_MSG_MAGIC HL_COMMS_MSG_MAGIC_V1 + +#define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) \ + (((magic) & HL_COMMS_MSG_MAGIC_MASK) == \ + HL_COMMS_MSG_MAGIC_VALUE) + +#define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) \ + (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >= \ + ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) + +#define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) \ + (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) && \ + HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver))) + +enum comms_msg_type { + HL_COMMS_DESC_TYPE = 0, + HL_COMMS_RESET_CAUSE_TYPE = 1, + HL_COMMS_FW_CFG_SKIP_TYPE = 2, + HL_COMMS_BINNING_CONF_TYPE = 3, +}; + +/* + * Binning information shared between LKD and FW + * @tpc_mask - TPC binning information + * @dec_mask - Decoder binning information + * @hbm_mask - HBM binning information + * @edma_mask - EDMA binning information + * @mme_mask_l - MME binning information lower 32 + * @mme_mask_h - MME binning information upper 32 + * @reserved - reserved field for 64 bit alignment + */ +struct lkd_fw_binning_info { + __le64 tpc_mask; + __le32 dec_mask; + __le32 hbm_mask; + __le32 edma_mask; + __le32 mme_mask_l; + __le32 mme_mask_h; + __le32 reserved; +}; + +/* TODO: remove this struct after the code is updated to use message */ +/* this is the comms descriptor header - meta data */ +struct comms_desc_header { + __le32 magic; /* magic for validation */ + __le32 crc32; /* CRC32 of the descriptor w/o header */ + __le16 size; /* size of the descriptor w/o header */ + __u8 version; /* descriptor version */ + __u8 reserved[5]; /* pad to 64 bit */ +}; + +/* this is the comms message header - meta data */ +struct comms_msg_header { + __le32 magic; /* magic for validation */ + __le32 crc32; /* CRC32 of the message w/o header */ + __le16 size; /* size of the message w/o header */ + __u8 version; /* message payload version */ + __u8 type; /* message type */ + __u8 reserved[4]; /* pad to 64 bit */ +}; + +/* this is the main FW descriptor - consider ABI when changing */ +struct lkd_fw_comms_desc { + struct comms_desc_header header; + struct cpu_dyn_regs cpu_dyn_regs; + char fuse_ver[VERSION_MAX_LEN]; + char cur_fw_ver[VERSION_MAX_LEN]; + /* can be used for 1 more version w/o ABI change */ + char reserved0[VERSION_MAX_LEN]; + __le64 img_addr; /* address for next FW component load */ +}; + +enum comms_reset_cause { + HL_RESET_CAUSE_UNKNOWN = 0, + HL_RESET_CAUSE_HEARTBEAT = 1, + HL_RESET_CAUSE_TDR = 2, +}; + +/* TODO: remove define after struct name is aligned on all projects */ +#define lkd_msg_comms lkd_fw_comms_msg + +/* this is the comms message descriptor */ +struct lkd_fw_comms_msg { + struct comms_msg_header header; + /* union for future expantions of new messages */ + union { + struct { + struct cpu_dyn_regs cpu_dyn_regs; + char fuse_ver[VERSION_MAX_LEN]; + char cur_fw_ver[VERSION_MAX_LEN]; + /* can be used for 1 more version w/o ABI change */ + char reserved0[VERSION_MAX_LEN]; + /* address for next FW component load */ + __le64 img_addr; + }; + struct { + __u8 reset_cause; + }; + struct { + __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */ + }; + struct lkd_fw_binning_info binning_info; + }; +}; + +/* + * LKD commands: + * + * COMMS_NOOP Used to clear the command register and no actual + * command is send. + * + * COMMS_CLR_STS Clear status command - FW should clear the + * status register. Used for synchronization + * between the commands as part of the race free + * protocol. + * + * COMMS_RST_STATE Reset the current communication state which is + * kept by FW for proper responses. + * Should be used in the beginning of the + * communication cycle to clean any leftovers from + * previous communication attempts. + * + * COMMS_PREP_DESC Prepare descriptor for setting up the + * communication and other dynamic data: + * struct lkd_fw_comms_desc. + * This command has a parameter stating the next FW + * component size, so the FW can actually prepare a + * space for it and in the status response provide + * the descriptor offset. The Offset of the next FW + * data component is a part of the descriptor + * structure. + * + * COMMS_DATA_RDY The FW data has been uploaded and is ready for + * validation. + * + * COMMS_EXEC Execute the next FW component. + * + * COMMS_RST_DEV Reset the device. + * + * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure + * devices. + * + * COMMS_SKIP_BMC Perform actions required for BMC-less servers. + * Do not wait for BMC response. + * + * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory + * space is allocated in a ELBI access only + * address range. + * + */ +enum comms_cmd { + COMMS_NOOP = 0, + COMMS_CLR_STS = 1, + COMMS_RST_STATE = 2, + COMMS_PREP_DESC = 3, + COMMS_DATA_RDY = 4, + COMMS_EXEC = 5, + COMMS_RST_DEV = 6, + COMMS_GOTO_WFE = 7, + COMMS_SKIP_BMC = 8, + COMMS_PREP_DESC_ELBI = 10, + COMMS_INVLD_LAST +}; + +#define COMMS_COMMAND_SIZE_SHIFT 0 +#define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF +#define COMMS_COMMAND_CMD_SHIFT 27 +#define COMMS_COMMAND_CMD_MASK 0xF8000000 + +/* + * LKD command to FW register structure + * @size - FW component size + * @cmd - command from enum comms_cmd + */ +struct comms_command { + union { /* bit fields are only for FW use */ + struct { + u32 size :25; /* 32MB max. */ + u32 reserved :2; + enum comms_cmd cmd :5; /* 32 commands */ + }; + __le32 val; + }; +}; + +/* + * FW status + * + * COMMS_STS_NOOP Used to clear the status register and no actual + * status is provided. + * + * COMMS_STS_ACK Command has been received and recognized. + * + * COMMS_STS_OK Command execution has finished successfully. + * + * COMMS_STS_ERR Command execution was unsuccessful and resulted + * in error. + * + * COMMS_STS_VALID_ERR FW validation has failed. + * + * COMMS_STS_TIMEOUT_ERR Command execution has timed out. + */ +enum comms_sts { + COMMS_STS_NOOP = 0, + COMMS_STS_ACK = 1, + COMMS_STS_OK = 2, + COMMS_STS_ERR = 3, + COMMS_STS_VALID_ERR = 4, + COMMS_STS_TIMEOUT_ERR = 5, + COMMS_STS_INVLD_LAST +}; + +/* RAM types for FW components loading - defines the base address */ +enum comms_ram_types { + COMMS_SRAM = 0, + COMMS_DRAM = 1, +}; + +#define COMMS_STATUS_OFFSET_SHIFT 0 +#define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF +#define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2 +#define COMMS_STATUS_RAM_TYPE_SHIFT 26 +#define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000 +#define COMMS_STATUS_STATUS_SHIFT 28 +#define COMMS_STATUS_STATUS_MASK 0xF0000000 + +/* + * FW status to LKD register structure + * @offset - an offset from the base of the ram_type shifted right by + * 2 bits (always aligned to 32 bits). + * Allows a maximum addressable offset of 256MB from RAM base. + * Example: for real offset in RAM of 0x800000 (8MB), the value + * in offset field is (0x800000 >> 2) = 0x200000. + * @ram_type - the RAM type that should be used for offset from + * enum comms_ram_types + * @status - status from enum comms_sts + */ +struct comms_status { + union { /* bit fields are only for FW use */ + struct { + u32 offset :26; + enum comms_ram_types ram_type :2; + enum comms_sts status :4; /* 16 statuses */ + }; + __le32 val; + }; +}; + +#endif /* HL_BOOT_IF_H */ diff --git a/drivers/misc/habanalabs/include/common/qman_if.h b/drivers/misc/habanalabs/include/common/qman_if.h new file mode 100644 index 000000000..7ed773957 --- /dev/null +++ b/drivers/misc/habanalabs/include/common/qman_if.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef QMAN_IF_H +#define QMAN_IF_H + +#include + +/* + * PRIMARY QUEUE + */ + +struct hl_bd { + __le64 ptr; + __le32 len; + __le32 ctl; +}; + +#define HL_BD_SIZE sizeof(struct hl_bd) + +/* + * S/W CTL FIELDS. + * + * BD_CTL_REPEAT_VALID tells the CP whether the repeat field in the BD CTL is + * valid. 1 means the repeat field is valid, 0 means not-valid, + * i.e. repeat == 1 + */ +#define BD_CTL_REPEAT_VALID_SHIFT 24 +#define BD_CTL_REPEAT_VALID_MASK 0x01000000 + +#define BD_CTL_SHADOW_INDEX_SHIFT 0 +#define BD_CTL_SHADOW_INDEX_MASK 0x00000FFF + +/* + * H/W CTL FIELDS + */ + +#define BD_CTL_COMP_OFFSET_SHIFT 16 +#define BD_CTL_COMP_OFFSET_MASK 0x0FFF0000 + +#define BD_CTL_COMP_DATA_SHIFT 0 +#define BD_CTL_COMP_DATA_MASK 0x0000FFFF + +/* + * COMPLETION QUEUE + */ + +struct hl_cq_entry { + __le32 data; +}; + +#define HL_CQ_ENTRY_SIZE sizeof(struct hl_cq_entry) + +#define CQ_ENTRY_READY_SHIFT 31 +#define CQ_ENTRY_READY_MASK 0x80000000 + +#define CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT 30 +#define CQ_ENTRY_SHADOW_INDEX_VALID_MASK 0x40000000 + +#define CQ_ENTRY_SHADOW_INDEX_SHIFT BD_CTL_SHADOW_INDEX_SHIFT +#define CQ_ENTRY_SHADOW_INDEX_MASK BD_CTL_SHADOW_INDEX_MASK + + +#endif /* QMAN_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000..cf80e3131 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#define mmCPU_IF_TOTAL_WR_CNT 0x442140 + +#define mmCPU_IF_INFLIGHT_WR_CNT 0x442144 + +#define mmCPU_IF_TOTAL_RD_CNT 0x442150 + +#define mmCPU_IF_INFLIGHT_RD_CNT 0x442154 + +#define mmCPU_IF_PF_PQ_PI 0x442200 + +#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204 + +#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208 + +#define mmCPU_IF_PQ_LENGTH 0x44220C + +#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210 + +#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214 + +#define mmCPU_IF_CQ_LENGTH 0x442218 + +#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220 + +#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224 + +#define mmCPU_IF_EQ_LENGTH 0x442228 + +#define mmCPU_IF_EQ_RD_OFFS 0x44222C + +#define mmCPU_IF_QUEUE_INIT 0x442230 + +#define mmCPU_IF_TPC_SERR_INTR_STS 0x442300 + +#define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304 + +#define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308 + +#define mmCPU_IF_TPC_DERR_INTR_STS 0x442310 + +#define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314 + +#define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318 + +#define mmCPU_IF_DMA_SERR_INTR_STS 0x442320 + +#define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324 + +#define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328 + +#define mmCPU_IF_DMA_DERR_INTR_STS 0x442330 + +#define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334 + +#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338 + +#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340 + +#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344 + +#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348 + +#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350 + +#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354 + +#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358 + +#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360 + +#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364 + +#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368 + +#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370 + +#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374 + +#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378 + +#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380 + +#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384 + +#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388 + +#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390 + +#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394 + +#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398 + +#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0 + +#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4 + +#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8 + +#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0 + +#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4 + +#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8 + +#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400 + +#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404 + +#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408 + +#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410 + +#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414 + +#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418 + +#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420 + +#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424 + +#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428 + +#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430 + +#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434 + +#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h new file mode 100644 index 000000000..d079a37ac --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_MASKS_H_ +#define ASIC_REG_DMA0_CORE_MASKS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +/* DMA0_CORE_CFG_0 */ +#define DMA0_CORE_CFG_0_EN_SHIFT 0 +#define DMA0_CORE_CFG_0_EN_MASK 0x1 + +/* DMA0_CORE_CFG_1 */ +#define DMA0_CORE_CFG_1_HALT_SHIFT 0 +#define DMA0_CORE_CFG_1_HALT_MASK 0x1 +#define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 + +/* DMA0_CORE_LBW_MAX_OUTSTAND */ +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F + +/* DMA0_CORE_SRC_BASE_LO */ +#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_BASE_HI */ +#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_LO */ +#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_HI */ +#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 + +/* DMA0_CORE_SRC_TSIZE_1 */ +#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_1 */ +#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_2 */ +#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_2 */ +#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_3 */ +#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_3 */ +#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_4 */ +#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_4 */ +#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_0 */ +#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_1 */ +#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_1 */ +#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_2 */ +#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_2 */ +#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_3 */ +#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_3 */ +#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_4 */ +#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_4 */ +#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_0 */ +#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_COMMIT */ +#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 +#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 +#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 +#define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 +#define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 +#define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 +#define DMA0_CORE_COMMIT_LIN_SHIFT 3 +#define DMA0_CORE_COMMIT_LIN_MASK 0x8 +#define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 +#define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 +#define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 +#define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 +#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 +#define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 +#define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 +#define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 + +/* DMA0_CORE_WR_COMP_WDATA */ +#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_LO */ +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_HI */ +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_AWUSER_31_11 */ +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_TE_NUMROWS */ +#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 +#define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_PROT */ +#define DMA0_CORE_PROT_VAL_SHIFT 0 +#define DMA0_CORE_PROT_VAL_MASK 0x1 +#define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* DMA0_CORE_SECURE_PROPS */ +#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_NON_SECURE_PROPS */ +#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_RD_MAX_OUTSTAND */ +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_RD_MAX_SIZE */ +#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 +#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF +#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 +#define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 + +/* DMA0_CORE_RD_ARCACHE */ +#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF + +/* DMA0_CORE_RD_ARUSER_31_11 */ +#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_RD_INFLIGHTS */ +#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_MAX_OUTSTAND */ +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_WR_MAX_AWID */ +#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF + +/* DMA0_CORE_WR_AWCACHE */ +#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF + +/* DMA0_CORE_WR_AWUSER_31_11 */ +#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_WR_INFLIGHTS */ +#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF + +/* DMA0_CORE_RD_RATE_LIM_CFG_0 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_RD_RATE_LIM_CFG_1 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_0 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_1 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_ERR_CFG */ +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* DMA0_CORE_ERR_CAUSE */ +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 + +/* DMA0_CORE_ERRMSG_ADDR_LO */ +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_ADDR_HI */ +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_WDATA */ +#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_STS0 */ +#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define DMA0_CORE_STS0_BUSY_SHIFT 31 +#define DMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* DMA0_CORE_STS1 */ +#define DMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define DMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_ADD */ +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_WR */ +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_RD */ +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_CTRL */ +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_RC */ +#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 + +/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ + +/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_DESC_CNT */ +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF + +/* DMA0_CORE_DBG_STS */ +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 + +/* DMA0_CORE_DBG_RD_DESC_ID */ + +/* DMA0_CORE_DBG_WR_DESC_ID */ + +#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h new file mode 100644 index 000000000..1fdd5d5fc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_REGS_H_ +#define ASIC_REG_DMA0_CORE_REGS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA0_CORE_CFG_0 0x500000 + +#define mmDMA0_CORE_CFG_1 0x500004 + +#define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008 + +#define mmDMA0_CORE_SRC_BASE_LO 0x500014 + +#define mmDMA0_CORE_SRC_BASE_HI 0x500018 + +#define mmDMA0_CORE_DST_BASE_LO 0x50001C + +#define mmDMA0_CORE_DST_BASE_HI 0x500020 + +#define mmDMA0_CORE_SRC_TSIZE_1 0x50002C + +#define mmDMA0_CORE_SRC_STRIDE_1 0x500030 + +#define mmDMA0_CORE_SRC_TSIZE_2 0x500034 + +#define mmDMA0_CORE_SRC_STRIDE_2 0x500038 + +#define mmDMA0_CORE_SRC_TSIZE_3 0x50003C + +#define mmDMA0_CORE_SRC_STRIDE_3 0x500040 + +#define mmDMA0_CORE_SRC_TSIZE_4 0x500044 + +#define mmDMA0_CORE_SRC_STRIDE_4 0x500048 + +#define mmDMA0_CORE_SRC_TSIZE_0 0x50004C + +#define mmDMA0_CORE_DST_TSIZE_1 0x500054 + +#define mmDMA0_CORE_DST_STRIDE_1 0x500058 + +#define mmDMA0_CORE_DST_TSIZE_2 0x50005C + +#define mmDMA0_CORE_DST_STRIDE_2 0x500060 + +#define mmDMA0_CORE_DST_TSIZE_3 0x500064 + +#define mmDMA0_CORE_DST_STRIDE_3 0x500068 + +#define mmDMA0_CORE_DST_TSIZE_4 0x50006C + +#define mmDMA0_CORE_DST_STRIDE_4 0x500070 + +#define mmDMA0_CORE_DST_TSIZE_0 0x500074 + +#define mmDMA0_CORE_COMMIT 0x500078 + +#define mmDMA0_CORE_WR_COMP_WDATA 0x50007C + +#define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080 + +#define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084 + +#define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088 + +#define mmDMA0_CORE_TE_NUMROWS 0x500094 + +#define mmDMA0_CORE_PROT 0x5000B8 + +#define mmDMA0_CORE_SECURE_PROPS 0x5000F0 + +#define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4 + +#define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100 + +#define mmDMA0_CORE_RD_MAX_SIZE 0x500104 + +#define mmDMA0_CORE_RD_ARCACHE 0x500108 + +#define mmDMA0_CORE_RD_ARUSER_31_11 0x500110 + +#define mmDMA0_CORE_RD_INFLIGHTS 0x500114 + +#define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120 + +#define mmDMA0_CORE_WR_MAX_AWID 0x500124 + +#define mmDMA0_CORE_WR_AWCACHE 0x500128 + +#define mmDMA0_CORE_WR_AWUSER_31_11 0x500130 + +#define mmDMA0_CORE_WR_INFLIGHTS 0x500134 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C + +#define mmDMA0_CORE_ERR_CFG 0x500160 + +#define mmDMA0_CORE_ERR_CAUSE 0x500164 + +#define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170 + +#define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174 + +#define mmDMA0_CORE_ERRMSG_WDATA 0x500178 + +#define mmDMA0_CORE_STS0 0x500190 + +#define mmDMA0_CORE_STS1 0x500194 + +#define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208 + +#define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C + +#define mmDMA0_CORE_RD_DBGMEM_RC 0x500210 + +#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220 + +#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224 + +#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228 + +#define mmDMA0_CORE_DBG_DESC_CNT 0x50022C + +#define mmDMA0_CORE_DBG_STS 0x500230 + +#define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234 + +#define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238 + +#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h new file mode 100644 index 000000000..48376aabc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_MASKS_H_ +#define ASIC_REG_DMA0_QM_MASKS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +/* DMA0_QM_GLBL_CFG0 */ +#define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* DMA0_QM_GLBL_CFG1 */ +#define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define DMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* DMA0_QM_GLBL_PROT */ +#define DMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define DMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define DMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define DMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define DMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define DMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define DMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define DMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define DMA0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* DMA0_QM_GLBL_ERR_CFG */ +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* DMA0_QM_GLBL_SECURE_PROPS */ +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_NON_SECURE_PROPS */ +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_STS0 */ +#define DMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define DMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define DMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define DMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define DMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* DMA0_QM_GLBL_STS1 */ +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_STS1_4 */ +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN */ +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN_4 */ +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_PQ_BASE_LO */ +#define DMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_BASE_HI */ +#define DMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_SIZE */ +#define DMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define DMA0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_PI */ +#define DMA0_QM_PQ_PI_VAL_SHIFT 0 +#define DMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CI */ +#define DMA0_QM_PQ_CI_VAL_SHIFT 0 +#define DMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CFG0 */ +#define DMA0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_PQ_CFG1 */ +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_ARUSER_31_11 */ +#define DMA0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_PQ_STS0 */ +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_STS1 */ +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define DMA0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_CFG0 */ +#define DMA0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_CQ_CFG1 */ +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_ARUSER_31_11 */ +#define DMA0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CQ_STS0 */ +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_STS1 */ +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define DMA0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_PTR_LO_0 */ +#define DMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_0 */ +#define DMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_0 */ +#define DMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_0 */ +#define DMA0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_1 */ +#define DMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_1 */ +#define DMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_1 */ +#define DMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_1 */ +#define DMA0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_2 */ +#define DMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_2 */ +#define DMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_2 */ +#define DMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_2 */ +#define DMA0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_3 */ +#define DMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_3 */ +#define DMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_3 */ +#define DMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_3 */ +#define DMA0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_4 */ +#define DMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_4 */ +#define DMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_4 */ +#define DMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_4 */ +#define DMA0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_STS */ +#define DMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_STS */ +#define DMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_STS */ +#define DMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_STS */ +#define DMA0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_IFIFO_CNT */ +#define DMA0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define DMA0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* DMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_FENCE0_RDATA */ +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE1_RDATA */ +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE2_RDATA */ +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE3_RDATA */ +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE0_CNT */ +#define DMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE1_CNT */ +#define DMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE2_CNT */ +#define DMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE3_CNT */ +#define DMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_STS */ +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CP_STS_ERDY_SHIFT 16 +#define DMA0_QM_CP_STS_ERDY_MASK 0x10000 +#define DMA0_QM_CP_STS_RRDY_SHIFT 17 +#define DMA0_QM_CP_STS_RRDY_MASK 0x20000 +#define DMA0_QM_CP_STS_MRDY_SHIFT 18 +#define DMA0_QM_CP_STS_MRDY_MASK 0x40000 +#define DMA0_QM_CP_STS_SW_STOP_SHIFT 19 +#define DMA0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define DMA0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define DMA0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* DMA0_QM_CP_CURRENT_INST_LO */ +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_CURRENT_INST_HI */ +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_BARRIER_CFG */ +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* DMA0_QM_CP_DBG_0 */ +#define DMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define DMA0_QM_CP_DBG_0_CS_MASK 0xF +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define DMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define DMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define DMA0_QM_CP_DBG_0_STALL_SHIFT 7 +#define DMA0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* DMA0_QM_CP_ARUSER_31_11 */ +#define DMA0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CP_AWUSER_31_11 */ +#define DMA0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_CFG_0 */ +#define DMA0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define DMA0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define DMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define DMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define DMA0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define DMA0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* DMA0_QM_ARB_CHOISE_Q_PUSH */ +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* DMA0_QM_ARB_WRR_WEIGHT */ +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CFG_1 */ +#define DMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define DMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* DMA0_QM_ARB_MST_AVAIL_CRED */ +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MST_CRED_INC */ +#define DMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_SLAVE_EN */ +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_QUIET_PER */ +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_CHOISE_WDT */ +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_ID */ +#define DMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* DMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* DMA0_QM_ARB_MSG_AWUSER_31_11 */ +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_BASE_LO */ +#define DMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_BASE_HI */ +#define DMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_STATE_STS */ +#define DMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CHOISE_FULLNESS_STS */ +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MSG_STS */ +#define DMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define DMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* DMA0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* DMA0_QM_ARB_ERR_CAUSE */ +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_MSG_EN */ +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_STS_DRP */ +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* DMA0_QM_ARB_MST_CRED_STS */ +#define DMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* DMA0_QM_CGM_CFG */ +#define DMA0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define DMA0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define DMA0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define DMA0_QM_CGM_CFG_EN_SHIFT 31 +#define DMA0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* DMA0_QM_CGM_STS */ +#define DMA0_QM_CGM_STS_ST_SHIFT 0 +#define DMA0_QM_CGM_STS_ST_MASK 0x3 +#define DMA0_QM_CGM_STS_CG_SHIFT 4 +#define DMA0_QM_CGM_STS_CG_MASK 0x10 +#define DMA0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define DMA0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define DMA0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define DMA0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* DMA0_QM_CGM_CFG1 */ +#define DMA0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* DMA0_QM_LOCAL_RANGE_BASE */ +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* DMA0_QM_LOCAL_RANGE_SIZE */ +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* DMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_GLBL_AXCACHE */ +#define DMA0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define DMA0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define DMA0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define DMA0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* DMA0_QM_IND_GW_APB_CFG */ +#define DMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define DMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define DMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define DMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* DMA0_QM_IND_GW_APB_WDATA */ +#define DMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_RDATA */ +#define DMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_STATUS */ +#define DMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define DMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* DMA0_QM_GLBL_ERR_ADDR_LO */ +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_ADDR_HI */ +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_WDATA */ +#define DMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_MEM_INIT_BUSY */ +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_DMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h new file mode 100644 index 000000000..8e56a93d8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_REGS_H_ +#define ASIC_REG_DMA0_QM_REGS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA0_QM_GLBL_CFG0 0x508000 + +#define mmDMA0_QM_GLBL_CFG1 0x508004 + +#define mmDMA0_QM_GLBL_PROT 0x508008 + +#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034 + +#define mmDMA0_QM_GLBL_STS0 0x508038 + +#define mmDMA0_QM_GLBL_STS1_0 0x508040 + +#define mmDMA0_QM_GLBL_STS1_1 0x508044 + +#define mmDMA0_QM_GLBL_STS1_2 0x508048 + +#define mmDMA0_QM_GLBL_STS1_3 0x50804C + +#define mmDMA0_QM_GLBL_STS1_4 0x508050 + +#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054 + +#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058 + +#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C + +#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060 + +#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068 + +#define mmDMA0_QM_PQ_BASE_LO_0 0x508070 + +#define mmDMA0_QM_PQ_BASE_LO_1 0x508074 + +#define mmDMA0_QM_PQ_BASE_LO_2 0x508078 + +#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C + +#define mmDMA0_QM_PQ_BASE_HI_0 0x508080 + +#define mmDMA0_QM_PQ_BASE_HI_1 0x508084 + +#define mmDMA0_QM_PQ_BASE_HI_2 0x508088 + +#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C + +#define mmDMA0_QM_PQ_SIZE_0 0x508090 + +#define mmDMA0_QM_PQ_SIZE_1 0x508094 + +#define mmDMA0_QM_PQ_SIZE_2 0x508098 + +#define mmDMA0_QM_PQ_SIZE_3 0x50809C + +#define mmDMA0_QM_PQ_PI_0 0x5080A0 + +#define mmDMA0_QM_PQ_PI_1 0x5080A4 + +#define mmDMA0_QM_PQ_PI_2 0x5080A8 + +#define mmDMA0_QM_PQ_PI_3 0x5080AC + +#define mmDMA0_QM_PQ_CI_0 0x5080B0 + +#define mmDMA0_QM_PQ_CI_1 0x5080B4 + +#define mmDMA0_QM_PQ_CI_2 0x5080B8 + +#define mmDMA0_QM_PQ_CI_3 0x5080BC + +#define mmDMA0_QM_PQ_CFG0_0 0x5080C0 + +#define mmDMA0_QM_PQ_CFG0_1 0x5080C4 + +#define mmDMA0_QM_PQ_CFG0_2 0x5080C8 + +#define mmDMA0_QM_PQ_CFG0_3 0x5080CC + +#define mmDMA0_QM_PQ_CFG1_0 0x5080D0 + +#define mmDMA0_QM_PQ_CFG1_1 0x5080D4 + +#define mmDMA0_QM_PQ_CFG1_2 0x5080D8 + +#define mmDMA0_QM_PQ_CFG1_3 0x5080DC + +#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0 + +#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4 + +#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8 + +#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC + +#define mmDMA0_QM_PQ_STS0_0 0x5080F0 + +#define mmDMA0_QM_PQ_STS0_1 0x5080F4 + +#define mmDMA0_QM_PQ_STS0_2 0x5080F8 + +#define mmDMA0_QM_PQ_STS0_3 0x5080FC + +#define mmDMA0_QM_PQ_STS1_0 0x508100 + +#define mmDMA0_QM_PQ_STS1_1 0x508104 + +#define mmDMA0_QM_PQ_STS1_2 0x508108 + +#define mmDMA0_QM_PQ_STS1_3 0x50810C + +#define mmDMA0_QM_CQ_CFG0_0 0x508110 + +#define mmDMA0_QM_CQ_CFG0_1 0x508114 + +#define mmDMA0_QM_CQ_CFG0_2 0x508118 + +#define mmDMA0_QM_CQ_CFG0_3 0x50811C + +#define mmDMA0_QM_CQ_CFG0_4 0x508120 + +#define mmDMA0_QM_CQ_CFG1_0 0x508124 + +#define mmDMA0_QM_CQ_CFG1_1 0x508128 + +#define mmDMA0_QM_CQ_CFG1_2 0x50812C + +#define mmDMA0_QM_CQ_CFG1_3 0x508130 + +#define mmDMA0_QM_CQ_CFG1_4 0x508134 + +#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138 + +#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C + +#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140 + +#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144 + +#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148 + +#define mmDMA0_QM_CQ_STS0_0 0x50814C + +#define mmDMA0_QM_CQ_STS0_1 0x508150 + +#define mmDMA0_QM_CQ_STS0_2 0x508154 + +#define mmDMA0_QM_CQ_STS0_3 0x508158 + +#define mmDMA0_QM_CQ_STS0_4 0x50815C + +#define mmDMA0_QM_CQ_STS1_0 0x508160 + +#define mmDMA0_QM_CQ_STS1_1 0x508164 + +#define mmDMA0_QM_CQ_STS1_2 0x508168 + +#define mmDMA0_QM_CQ_STS1_3 0x50816C + +#define mmDMA0_QM_CQ_STS1_4 0x508170 + +#define mmDMA0_QM_CQ_PTR_LO_0 0x508174 + +#define mmDMA0_QM_CQ_PTR_HI_0 0x508178 + +#define mmDMA0_QM_CQ_TSIZE_0 0x50817C + +#define mmDMA0_QM_CQ_CTL_0 0x508180 + +#define mmDMA0_QM_CQ_PTR_LO_1 0x508184 + +#define mmDMA0_QM_CQ_PTR_HI_1 0x508188 + +#define mmDMA0_QM_CQ_TSIZE_1 0x50818C + +#define mmDMA0_QM_CQ_CTL_1 0x508190 + +#define mmDMA0_QM_CQ_PTR_LO_2 0x508194 + +#define mmDMA0_QM_CQ_PTR_HI_2 0x508198 + +#define mmDMA0_QM_CQ_TSIZE_2 0x50819C + +#define mmDMA0_QM_CQ_CTL_2 0x5081A0 + +#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4 + +#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8 + +#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC + +#define mmDMA0_QM_CQ_CTL_3 0x5081B0 + +#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4 + +#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8 + +#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC + +#define mmDMA0_QM_CQ_CTL_4 0x5081C0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4 + +#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8 + +#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC + +#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8 + +#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC + +#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0 + +#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8 + +#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC + +#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0 + +#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4 + +#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8 + +#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC + +#define mmDMA0_QM_CQ_CTL_STS_0 0x508200 + +#define mmDMA0_QM_CQ_CTL_STS_1 0x508204 + +#define mmDMA0_QM_CQ_CTL_STS_2 0x508208 + +#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C + +#define mmDMA0_QM_CQ_CTL_STS_4 0x508210 + +#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214 + +#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218 + +#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C + +#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220 + +#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304 + +#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308 + +#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C + +#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310 + +#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314 + +#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318 + +#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C + +#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320 + +#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324 + +#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328 + +#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C + +#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330 + +#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334 + +#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338 + +#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C + +#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340 + +#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344 + +#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348 + +#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C + +#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350 + +#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354 + +#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358 + +#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C + +#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360 + +#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364 + +#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368 + +#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C + +#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370 + +#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374 + +#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378 + +#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C + +#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380 + +#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384 + +#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388 + +#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C + +#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390 + +#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394 + +#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398 + +#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C + +#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0 + +#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4 + +#define mmDMA0_QM_CP_STS_0 0x5083A8 + +#define mmDMA0_QM_CP_STS_1 0x5083AC + +#define mmDMA0_QM_CP_STS_2 0x5083B0 + +#define mmDMA0_QM_CP_STS_3 0x5083B4 + +#define mmDMA0_QM_CP_STS_4 0x5083B8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC + +#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0 + +#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4 + +#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8 + +#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC + +#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400 + +#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404 + +#define mmDMA0_QM_CP_DBG_0_0 0x508408 + +#define mmDMA0_QM_CP_DBG_0_1 0x50840C + +#define mmDMA0_QM_CP_DBG_0_2 0x508410 + +#define mmDMA0_QM_CP_DBG_0_3 0x508414 + +#define mmDMA0_QM_CP_DBG_0_4 0x508418 + +#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C + +#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420 + +#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424 + +#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428 + +#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C + +#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430 + +#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434 + +#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438 + +#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C + +#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440 + +#define mmDMA0_QM_ARB_CFG_0 0x508A00 + +#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C + +#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14 + +#define mmDMA0_QM_ARB_CFG_1 0x508A18 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C + +#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20 + +#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28 + +#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C + +#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34 + +#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38 + +#define mmDMA0_QM_ARB_SLV_ID 0x508B3C + +#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44 + +#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48 + +#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C + +#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50 + +#define mmDMA0_QM_ARB_BASE_LO 0x508B54 + +#define mmDMA0_QM_ARB_BASE_HI 0x508B58 + +#define mmDMA0_QM_ARB_STATE_STS 0x508B80 + +#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84 + +#define mmDMA0_QM_ARB_MSG_STS 0x508B88 + +#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C + +#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C + +#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0 + +#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC + +#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC + +#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC + +#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC + +#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC + +#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00 + +#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04 + +#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08 + +#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C + +#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10 + +#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14 + +#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18 + +#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C + +#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20 + +#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24 + +#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28 + +#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C + +#define mmDMA0_QM_CGM_CFG 0x508C70 + +#define mmDMA0_QM_CGM_STS 0x508C74 + +#define mmDMA0_QM_CGM_CFG1 0x508C78 + +#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80 + +#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84 + +#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90 + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0 + +#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4 + +#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0 + +#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4 + +#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8 + +#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC + +#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0 + +#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4 + +#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8 + +#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00 + +#endif /* ASIC_REG_DMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h new file mode 100644 index 000000000..4d8d8f26c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_CORE_REGS_H_ +#define ASIC_REG_DMA1_CORE_REGS_H_ + +/* + ***************************************** + * DMA1_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA1_CORE_CFG_0 0x520000 + +#define mmDMA1_CORE_CFG_1 0x520004 + +#define mmDMA1_CORE_LBW_MAX_OUTSTAND 0x520008 + +#define mmDMA1_CORE_SRC_BASE_LO 0x520014 + +#define mmDMA1_CORE_SRC_BASE_HI 0x520018 + +#define mmDMA1_CORE_DST_BASE_LO 0x52001C + +#define mmDMA1_CORE_DST_BASE_HI 0x520020 + +#define mmDMA1_CORE_SRC_TSIZE_1 0x52002C + +#define mmDMA1_CORE_SRC_STRIDE_1 0x520030 + +#define mmDMA1_CORE_SRC_TSIZE_2 0x520034 + +#define mmDMA1_CORE_SRC_STRIDE_2 0x520038 + +#define mmDMA1_CORE_SRC_TSIZE_3 0x52003C + +#define mmDMA1_CORE_SRC_STRIDE_3 0x520040 + +#define mmDMA1_CORE_SRC_TSIZE_4 0x520044 + +#define mmDMA1_CORE_SRC_STRIDE_4 0x520048 + +#define mmDMA1_CORE_SRC_TSIZE_0 0x52004C + +#define mmDMA1_CORE_DST_TSIZE_1 0x520054 + +#define mmDMA1_CORE_DST_STRIDE_1 0x520058 + +#define mmDMA1_CORE_DST_TSIZE_2 0x52005C + +#define mmDMA1_CORE_DST_STRIDE_2 0x520060 + +#define mmDMA1_CORE_DST_TSIZE_3 0x520064 + +#define mmDMA1_CORE_DST_STRIDE_3 0x520068 + +#define mmDMA1_CORE_DST_TSIZE_4 0x52006C + +#define mmDMA1_CORE_DST_STRIDE_4 0x520070 + +#define mmDMA1_CORE_DST_TSIZE_0 0x520074 + +#define mmDMA1_CORE_COMMIT 0x520078 + +#define mmDMA1_CORE_WR_COMP_WDATA 0x52007C + +#define mmDMA1_CORE_WR_COMP_ADDR_LO 0x520080 + +#define mmDMA1_CORE_WR_COMP_ADDR_HI 0x520084 + +#define mmDMA1_CORE_WR_COMP_AWUSER_31_11 0x520088 + +#define mmDMA1_CORE_TE_NUMROWS 0x520094 + +#define mmDMA1_CORE_PROT 0x5200B8 + +#define mmDMA1_CORE_SECURE_PROPS 0x5200F0 + +#define mmDMA1_CORE_NON_SECURE_PROPS 0x5200F4 + +#define mmDMA1_CORE_RD_MAX_OUTSTAND 0x520100 + +#define mmDMA1_CORE_RD_MAX_SIZE 0x520104 + +#define mmDMA1_CORE_RD_ARCACHE 0x520108 + +#define mmDMA1_CORE_RD_ARUSER_31_11 0x520110 + +#define mmDMA1_CORE_RD_INFLIGHTS 0x520114 + +#define mmDMA1_CORE_WR_MAX_OUTSTAND 0x520120 + +#define mmDMA1_CORE_WR_MAX_AWID 0x520124 + +#define mmDMA1_CORE_WR_AWCACHE 0x520128 + +#define mmDMA1_CORE_WR_AWUSER_31_11 0x520130 + +#define mmDMA1_CORE_WR_INFLIGHTS 0x520134 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_0 0x520150 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_1 0x520154 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_0 0x520158 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_1 0x52015C + +#define mmDMA1_CORE_ERR_CFG 0x520160 + +#define mmDMA1_CORE_ERR_CAUSE 0x520164 + +#define mmDMA1_CORE_ERRMSG_ADDR_LO 0x520170 + +#define mmDMA1_CORE_ERRMSG_ADDR_HI 0x520174 + +#define mmDMA1_CORE_ERRMSG_WDATA 0x520178 + +#define mmDMA1_CORE_STS0 0x520190 + +#define mmDMA1_CORE_STS1 0x520194 + +#define mmDMA1_CORE_RD_DBGMEM_ADD 0x520200 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_WR 0x520204 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_RD 0x520208 + +#define mmDMA1_CORE_RD_DBGMEM_CTRL 0x52020C + +#define mmDMA1_CORE_RD_DBGMEM_RC 0x520210 + +#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT 0x520220 + +#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT 0x520224 + +#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT 0x520228 + +#define mmDMA1_CORE_DBG_DESC_CNT 0x52022C + +#define mmDMA1_CORE_DBG_STS 0x520230 + +#define mmDMA1_CORE_DBG_RD_DESC_ID 0x520234 + +#define mmDMA1_CORE_DBG_WR_DESC_ID 0x520238 + +#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h new file mode 100644 index 000000000..c3ef30084 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_QM_REGS_H_ +#define ASIC_REG_DMA1_QM_REGS_H_ + +/* + ***************************************** + * DMA1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA1_QM_GLBL_CFG0 0x528000 + +#define mmDMA1_QM_GLBL_CFG1 0x528004 + +#define mmDMA1_QM_GLBL_PROT 0x528008 + +#define mmDMA1_QM_GLBL_ERR_CFG 0x52800C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x528010 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x528014 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x528018 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x528020 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x528024 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x528028 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x528030 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x528034 + +#define mmDMA1_QM_GLBL_STS0 0x528038 + +#define mmDMA1_QM_GLBL_STS1_0 0x528040 + +#define mmDMA1_QM_GLBL_STS1_1 0x528044 + +#define mmDMA1_QM_GLBL_STS1_2 0x528048 + +#define mmDMA1_QM_GLBL_STS1_3 0x52804C + +#define mmDMA1_QM_GLBL_STS1_4 0x528050 + +#define mmDMA1_QM_GLBL_MSG_EN_0 0x528054 + +#define mmDMA1_QM_GLBL_MSG_EN_1 0x528058 + +#define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C + +#define mmDMA1_QM_GLBL_MSG_EN_3 0x528060 + +#define mmDMA1_QM_GLBL_MSG_EN_4 0x528068 + +#define mmDMA1_QM_PQ_BASE_LO_0 0x528070 + +#define mmDMA1_QM_PQ_BASE_LO_1 0x528074 + +#define mmDMA1_QM_PQ_BASE_LO_2 0x528078 + +#define mmDMA1_QM_PQ_BASE_LO_3 0x52807C + +#define mmDMA1_QM_PQ_BASE_HI_0 0x528080 + +#define mmDMA1_QM_PQ_BASE_HI_1 0x528084 + +#define mmDMA1_QM_PQ_BASE_HI_2 0x528088 + +#define mmDMA1_QM_PQ_BASE_HI_3 0x52808C + +#define mmDMA1_QM_PQ_SIZE_0 0x528090 + +#define mmDMA1_QM_PQ_SIZE_1 0x528094 + +#define mmDMA1_QM_PQ_SIZE_2 0x528098 + +#define mmDMA1_QM_PQ_SIZE_3 0x52809C + +#define mmDMA1_QM_PQ_PI_0 0x5280A0 + +#define mmDMA1_QM_PQ_PI_1 0x5280A4 + +#define mmDMA1_QM_PQ_PI_2 0x5280A8 + +#define mmDMA1_QM_PQ_PI_3 0x5280AC + +#define mmDMA1_QM_PQ_CI_0 0x5280B0 + +#define mmDMA1_QM_PQ_CI_1 0x5280B4 + +#define mmDMA1_QM_PQ_CI_2 0x5280B8 + +#define mmDMA1_QM_PQ_CI_3 0x5280BC + +#define mmDMA1_QM_PQ_CFG0_0 0x5280C0 + +#define mmDMA1_QM_PQ_CFG0_1 0x5280C4 + +#define mmDMA1_QM_PQ_CFG0_2 0x5280C8 + +#define mmDMA1_QM_PQ_CFG0_3 0x5280CC + +#define mmDMA1_QM_PQ_CFG1_0 0x5280D0 + +#define mmDMA1_QM_PQ_CFG1_1 0x5280D4 + +#define mmDMA1_QM_PQ_CFG1_2 0x5280D8 + +#define mmDMA1_QM_PQ_CFG1_3 0x5280DC + +#define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0 + +#define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4 + +#define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8 + +#define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC + +#define mmDMA1_QM_PQ_STS0_0 0x5280F0 + +#define mmDMA1_QM_PQ_STS0_1 0x5280F4 + +#define mmDMA1_QM_PQ_STS0_2 0x5280F8 + +#define mmDMA1_QM_PQ_STS0_3 0x5280FC + +#define mmDMA1_QM_PQ_STS1_0 0x528100 + +#define mmDMA1_QM_PQ_STS1_1 0x528104 + +#define mmDMA1_QM_PQ_STS1_2 0x528108 + +#define mmDMA1_QM_PQ_STS1_3 0x52810C + +#define mmDMA1_QM_CQ_CFG0_0 0x528110 + +#define mmDMA1_QM_CQ_CFG0_1 0x528114 + +#define mmDMA1_QM_CQ_CFG0_2 0x528118 + +#define mmDMA1_QM_CQ_CFG0_3 0x52811C + +#define mmDMA1_QM_CQ_CFG0_4 0x528120 + +#define mmDMA1_QM_CQ_CFG1_0 0x528124 + +#define mmDMA1_QM_CQ_CFG1_1 0x528128 + +#define mmDMA1_QM_CQ_CFG1_2 0x52812C + +#define mmDMA1_QM_CQ_CFG1_3 0x528130 + +#define mmDMA1_QM_CQ_CFG1_4 0x528134 + +#define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138 + +#define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C + +#define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140 + +#define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144 + +#define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148 + +#define mmDMA1_QM_CQ_STS0_0 0x52814C + +#define mmDMA1_QM_CQ_STS0_1 0x528150 + +#define mmDMA1_QM_CQ_STS0_2 0x528154 + +#define mmDMA1_QM_CQ_STS0_3 0x528158 + +#define mmDMA1_QM_CQ_STS0_4 0x52815C + +#define mmDMA1_QM_CQ_STS1_0 0x528160 + +#define mmDMA1_QM_CQ_STS1_1 0x528164 + +#define mmDMA1_QM_CQ_STS1_2 0x528168 + +#define mmDMA1_QM_CQ_STS1_3 0x52816C + +#define mmDMA1_QM_CQ_STS1_4 0x528170 + +#define mmDMA1_QM_CQ_PTR_LO_0 0x528174 + +#define mmDMA1_QM_CQ_PTR_HI_0 0x528178 + +#define mmDMA1_QM_CQ_TSIZE_0 0x52817C + +#define mmDMA1_QM_CQ_CTL_0 0x528180 + +#define mmDMA1_QM_CQ_PTR_LO_1 0x528184 + +#define mmDMA1_QM_CQ_PTR_HI_1 0x528188 + +#define mmDMA1_QM_CQ_TSIZE_1 0x52818C + +#define mmDMA1_QM_CQ_CTL_1 0x528190 + +#define mmDMA1_QM_CQ_PTR_LO_2 0x528194 + +#define mmDMA1_QM_CQ_PTR_HI_2 0x528198 + +#define mmDMA1_QM_CQ_TSIZE_2 0x52819C + +#define mmDMA1_QM_CQ_CTL_2 0x5281A0 + +#define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4 + +#define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8 + +#define mmDMA1_QM_CQ_TSIZE_3 0x5281AC + +#define mmDMA1_QM_CQ_CTL_3 0x5281B0 + +#define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4 + +#define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8 + +#define mmDMA1_QM_CQ_TSIZE_4 0x5281BC + +#define mmDMA1_QM_CQ_CTL_4 0x5281C0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4 + +#define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8 + +#define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC + +#define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8 + +#define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC + +#define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0 + +#define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8 + +#define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC + +#define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0 + +#define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4 + +#define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8 + +#define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC + +#define mmDMA1_QM_CQ_CTL_STS_0 0x528200 + +#define mmDMA1_QM_CQ_CTL_STS_1 0x528204 + +#define mmDMA1_QM_CQ_CTL_STS_2 0x528208 + +#define mmDMA1_QM_CQ_CTL_STS_3 0x52820C + +#define mmDMA1_QM_CQ_CTL_STS_4 0x528210 + +#define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214 + +#define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218 + +#define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C + +#define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220 + +#define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304 + +#define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308 + +#define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C + +#define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310 + +#define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314 + +#define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318 + +#define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C + +#define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320 + +#define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324 + +#define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328 + +#define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C + +#define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330 + +#define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334 + +#define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338 + +#define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C + +#define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340 + +#define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344 + +#define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348 + +#define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C + +#define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350 + +#define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354 + +#define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358 + +#define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C + +#define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360 + +#define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364 + +#define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368 + +#define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C + +#define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370 + +#define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374 + +#define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378 + +#define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C + +#define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380 + +#define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384 + +#define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388 + +#define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C + +#define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390 + +#define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394 + +#define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398 + +#define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C + +#define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0 + +#define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4 + +#define mmDMA1_QM_CP_STS_0 0x5283A8 + +#define mmDMA1_QM_CP_STS_1 0x5283AC + +#define mmDMA1_QM_CP_STS_2 0x5283B0 + +#define mmDMA1_QM_CP_STS_3 0x5283B4 + +#define mmDMA1_QM_CP_STS_4 0x5283B8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC + +#define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0 + +#define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4 + +#define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8 + +#define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC + +#define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400 + +#define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404 + +#define mmDMA1_QM_CP_DBG_0_0 0x528408 + +#define mmDMA1_QM_CP_DBG_0_1 0x52840C + +#define mmDMA1_QM_CP_DBG_0_2 0x528410 + +#define mmDMA1_QM_CP_DBG_0_3 0x528414 + +#define mmDMA1_QM_CP_DBG_0_4 0x528418 + +#define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C + +#define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420 + +#define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424 + +#define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428 + +#define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C + +#define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430 + +#define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434 + +#define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438 + +#define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C + +#define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440 + +#define mmDMA1_QM_ARB_CFG_0 0x528A00 + +#define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C + +#define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14 + +#define mmDMA1_QM_ARB_CFG_1 0x528A18 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C + +#define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20 + +#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28 + +#define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C + +#define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34 + +#define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38 + +#define mmDMA1_QM_ARB_SLV_ID 0x528B3C + +#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44 + +#define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48 + +#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C + +#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50 + +#define mmDMA1_QM_ARB_BASE_LO 0x528B54 + +#define mmDMA1_QM_ARB_BASE_HI 0x528B58 + +#define mmDMA1_QM_ARB_STATE_STS 0x528B80 + +#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84 + +#define mmDMA1_QM_ARB_MSG_STS 0x528B88 + +#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C + +#define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C + +#define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0 + +#define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC + +#define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC + +#define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC + +#define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC + +#define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC + +#define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00 + +#define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04 + +#define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08 + +#define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C + +#define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10 + +#define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14 + +#define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18 + +#define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C + +#define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20 + +#define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24 + +#define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28 + +#define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C + +#define mmDMA1_QM_CGM_CFG 0x528C70 + +#define mmDMA1_QM_CGM_STS 0x528C74 + +#define mmDMA1_QM_CGM_CFG1 0x528C78 + +#define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80 + +#define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84 + +#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90 + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0 + +#define mmDMA1_QM_GLBL_AXCACHE 0x528CA4 + +#define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0 + +#define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4 + +#define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8 + +#define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC + +#define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0 + +#define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4 + +#define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8 + +#define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00 + +#endif /* ASIC_REG_DMA1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h new file mode 100644 index 000000000..a42862cd5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_CORE_REGS_H_ +#define ASIC_REG_DMA2_CORE_REGS_H_ + +/* + ***************************************** + * DMA2_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA2_CORE_CFG_0 0x540000 + +#define mmDMA2_CORE_CFG_1 0x540004 + +#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008 + +#define mmDMA2_CORE_SRC_BASE_LO 0x540014 + +#define mmDMA2_CORE_SRC_BASE_HI 0x540018 + +#define mmDMA2_CORE_DST_BASE_LO 0x54001C + +#define mmDMA2_CORE_DST_BASE_HI 0x540020 + +#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C + +#define mmDMA2_CORE_SRC_STRIDE_1 0x540030 + +#define mmDMA2_CORE_SRC_TSIZE_2 0x540034 + +#define mmDMA2_CORE_SRC_STRIDE_2 0x540038 + +#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C + +#define mmDMA2_CORE_SRC_STRIDE_3 0x540040 + +#define mmDMA2_CORE_SRC_TSIZE_4 0x540044 + +#define mmDMA2_CORE_SRC_STRIDE_4 0x540048 + +#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C + +#define mmDMA2_CORE_DST_TSIZE_1 0x540054 + +#define mmDMA2_CORE_DST_STRIDE_1 0x540058 + +#define mmDMA2_CORE_DST_TSIZE_2 0x54005C + +#define mmDMA2_CORE_DST_STRIDE_2 0x540060 + +#define mmDMA2_CORE_DST_TSIZE_3 0x540064 + +#define mmDMA2_CORE_DST_STRIDE_3 0x540068 + +#define mmDMA2_CORE_DST_TSIZE_4 0x54006C + +#define mmDMA2_CORE_DST_STRIDE_4 0x540070 + +#define mmDMA2_CORE_DST_TSIZE_0 0x540074 + +#define mmDMA2_CORE_COMMIT 0x540078 + +#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C + +#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080 + +#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084 + +#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088 + +#define mmDMA2_CORE_TE_NUMROWS 0x540094 + +#define mmDMA2_CORE_PROT 0x5400B8 + +#define mmDMA2_CORE_SECURE_PROPS 0x5400F0 + +#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4 + +#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100 + +#define mmDMA2_CORE_RD_MAX_SIZE 0x540104 + +#define mmDMA2_CORE_RD_ARCACHE 0x540108 + +#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110 + +#define mmDMA2_CORE_RD_INFLIGHTS 0x540114 + +#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120 + +#define mmDMA2_CORE_WR_MAX_AWID 0x540124 + +#define mmDMA2_CORE_WR_AWCACHE 0x540128 + +#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130 + +#define mmDMA2_CORE_WR_INFLIGHTS 0x540134 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C + +#define mmDMA2_CORE_ERR_CFG 0x540160 + +#define mmDMA2_CORE_ERR_CAUSE 0x540164 + +#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170 + +#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174 + +#define mmDMA2_CORE_ERRMSG_WDATA 0x540178 + +#define mmDMA2_CORE_STS0 0x540190 + +#define mmDMA2_CORE_STS1 0x540194 + +#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208 + +#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C + +#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210 + +#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220 + +#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224 + +#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228 + +#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C + +#define mmDMA2_CORE_DBG_STS 0x540230 + +#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234 + +#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238 + +#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h new file mode 100644 index 000000000..8c4d4e016 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_QM_REGS_H_ +#define ASIC_REG_DMA2_QM_REGS_H_ + +/* + ***************************************** + * DMA2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA2_QM_GLBL_CFG0 0x548000 + +#define mmDMA2_QM_GLBL_CFG1 0x548004 + +#define mmDMA2_QM_GLBL_PROT 0x548008 + +#define mmDMA2_QM_GLBL_ERR_CFG 0x54800C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x548010 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x548014 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x548018 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x548020 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x548024 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x548028 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x548030 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x548034 + +#define mmDMA2_QM_GLBL_STS0 0x548038 + +#define mmDMA2_QM_GLBL_STS1_0 0x548040 + +#define mmDMA2_QM_GLBL_STS1_1 0x548044 + +#define mmDMA2_QM_GLBL_STS1_2 0x548048 + +#define mmDMA2_QM_GLBL_STS1_3 0x54804C + +#define mmDMA2_QM_GLBL_STS1_4 0x548050 + +#define mmDMA2_QM_GLBL_MSG_EN_0 0x548054 + +#define mmDMA2_QM_GLBL_MSG_EN_1 0x548058 + +#define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C + +#define mmDMA2_QM_GLBL_MSG_EN_3 0x548060 + +#define mmDMA2_QM_GLBL_MSG_EN_4 0x548068 + +#define mmDMA2_QM_PQ_BASE_LO_0 0x548070 + +#define mmDMA2_QM_PQ_BASE_LO_1 0x548074 + +#define mmDMA2_QM_PQ_BASE_LO_2 0x548078 + +#define mmDMA2_QM_PQ_BASE_LO_3 0x54807C + +#define mmDMA2_QM_PQ_BASE_HI_0 0x548080 + +#define mmDMA2_QM_PQ_BASE_HI_1 0x548084 + +#define mmDMA2_QM_PQ_BASE_HI_2 0x548088 + +#define mmDMA2_QM_PQ_BASE_HI_3 0x54808C + +#define mmDMA2_QM_PQ_SIZE_0 0x548090 + +#define mmDMA2_QM_PQ_SIZE_1 0x548094 + +#define mmDMA2_QM_PQ_SIZE_2 0x548098 + +#define mmDMA2_QM_PQ_SIZE_3 0x54809C + +#define mmDMA2_QM_PQ_PI_0 0x5480A0 + +#define mmDMA2_QM_PQ_PI_1 0x5480A4 + +#define mmDMA2_QM_PQ_PI_2 0x5480A8 + +#define mmDMA2_QM_PQ_PI_3 0x5480AC + +#define mmDMA2_QM_PQ_CI_0 0x5480B0 + +#define mmDMA2_QM_PQ_CI_1 0x5480B4 + +#define mmDMA2_QM_PQ_CI_2 0x5480B8 + +#define mmDMA2_QM_PQ_CI_3 0x5480BC + +#define mmDMA2_QM_PQ_CFG0_0 0x5480C0 + +#define mmDMA2_QM_PQ_CFG0_1 0x5480C4 + +#define mmDMA2_QM_PQ_CFG0_2 0x5480C8 + +#define mmDMA2_QM_PQ_CFG0_3 0x5480CC + +#define mmDMA2_QM_PQ_CFG1_0 0x5480D0 + +#define mmDMA2_QM_PQ_CFG1_1 0x5480D4 + +#define mmDMA2_QM_PQ_CFG1_2 0x5480D8 + +#define mmDMA2_QM_PQ_CFG1_3 0x5480DC + +#define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0 + +#define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4 + +#define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8 + +#define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC + +#define mmDMA2_QM_PQ_STS0_0 0x5480F0 + +#define mmDMA2_QM_PQ_STS0_1 0x5480F4 + +#define mmDMA2_QM_PQ_STS0_2 0x5480F8 + +#define mmDMA2_QM_PQ_STS0_3 0x5480FC + +#define mmDMA2_QM_PQ_STS1_0 0x548100 + +#define mmDMA2_QM_PQ_STS1_1 0x548104 + +#define mmDMA2_QM_PQ_STS1_2 0x548108 + +#define mmDMA2_QM_PQ_STS1_3 0x54810C + +#define mmDMA2_QM_CQ_CFG0_0 0x548110 + +#define mmDMA2_QM_CQ_CFG0_1 0x548114 + +#define mmDMA2_QM_CQ_CFG0_2 0x548118 + +#define mmDMA2_QM_CQ_CFG0_3 0x54811C + +#define mmDMA2_QM_CQ_CFG0_4 0x548120 + +#define mmDMA2_QM_CQ_CFG1_0 0x548124 + +#define mmDMA2_QM_CQ_CFG1_1 0x548128 + +#define mmDMA2_QM_CQ_CFG1_2 0x54812C + +#define mmDMA2_QM_CQ_CFG1_3 0x548130 + +#define mmDMA2_QM_CQ_CFG1_4 0x548134 + +#define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138 + +#define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C + +#define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140 + +#define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144 + +#define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148 + +#define mmDMA2_QM_CQ_STS0_0 0x54814C + +#define mmDMA2_QM_CQ_STS0_1 0x548150 + +#define mmDMA2_QM_CQ_STS0_2 0x548154 + +#define mmDMA2_QM_CQ_STS0_3 0x548158 + +#define mmDMA2_QM_CQ_STS0_4 0x54815C + +#define mmDMA2_QM_CQ_STS1_0 0x548160 + +#define mmDMA2_QM_CQ_STS1_1 0x548164 + +#define mmDMA2_QM_CQ_STS1_2 0x548168 + +#define mmDMA2_QM_CQ_STS1_3 0x54816C + +#define mmDMA2_QM_CQ_STS1_4 0x548170 + +#define mmDMA2_QM_CQ_PTR_LO_0 0x548174 + +#define mmDMA2_QM_CQ_PTR_HI_0 0x548178 + +#define mmDMA2_QM_CQ_TSIZE_0 0x54817C + +#define mmDMA2_QM_CQ_CTL_0 0x548180 + +#define mmDMA2_QM_CQ_PTR_LO_1 0x548184 + +#define mmDMA2_QM_CQ_PTR_HI_1 0x548188 + +#define mmDMA2_QM_CQ_TSIZE_1 0x54818C + +#define mmDMA2_QM_CQ_CTL_1 0x548190 + +#define mmDMA2_QM_CQ_PTR_LO_2 0x548194 + +#define mmDMA2_QM_CQ_PTR_HI_2 0x548198 + +#define mmDMA2_QM_CQ_TSIZE_2 0x54819C + +#define mmDMA2_QM_CQ_CTL_2 0x5481A0 + +#define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4 + +#define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8 + +#define mmDMA2_QM_CQ_TSIZE_3 0x5481AC + +#define mmDMA2_QM_CQ_CTL_3 0x5481B0 + +#define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4 + +#define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8 + +#define mmDMA2_QM_CQ_TSIZE_4 0x5481BC + +#define mmDMA2_QM_CQ_CTL_4 0x5481C0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4 + +#define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8 + +#define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC + +#define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8 + +#define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC + +#define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0 + +#define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8 + +#define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC + +#define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0 + +#define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4 + +#define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8 + +#define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC + +#define mmDMA2_QM_CQ_CTL_STS_0 0x548200 + +#define mmDMA2_QM_CQ_CTL_STS_1 0x548204 + +#define mmDMA2_QM_CQ_CTL_STS_2 0x548208 + +#define mmDMA2_QM_CQ_CTL_STS_3 0x54820C + +#define mmDMA2_QM_CQ_CTL_STS_4 0x548210 + +#define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214 + +#define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218 + +#define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C + +#define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220 + +#define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304 + +#define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308 + +#define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C + +#define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310 + +#define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314 + +#define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318 + +#define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C + +#define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320 + +#define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324 + +#define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328 + +#define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C + +#define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330 + +#define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334 + +#define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338 + +#define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C + +#define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340 + +#define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344 + +#define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348 + +#define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C + +#define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350 + +#define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354 + +#define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358 + +#define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C + +#define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360 + +#define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364 + +#define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368 + +#define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C + +#define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370 + +#define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374 + +#define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378 + +#define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C + +#define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380 + +#define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384 + +#define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388 + +#define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C + +#define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390 + +#define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394 + +#define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398 + +#define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C + +#define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0 + +#define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4 + +#define mmDMA2_QM_CP_STS_0 0x5483A8 + +#define mmDMA2_QM_CP_STS_1 0x5483AC + +#define mmDMA2_QM_CP_STS_2 0x5483B0 + +#define mmDMA2_QM_CP_STS_3 0x5483B4 + +#define mmDMA2_QM_CP_STS_4 0x5483B8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC + +#define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0 + +#define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4 + +#define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8 + +#define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC + +#define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400 + +#define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404 + +#define mmDMA2_QM_CP_DBG_0_0 0x548408 + +#define mmDMA2_QM_CP_DBG_0_1 0x54840C + +#define mmDMA2_QM_CP_DBG_0_2 0x548410 + +#define mmDMA2_QM_CP_DBG_0_3 0x548414 + +#define mmDMA2_QM_CP_DBG_0_4 0x548418 + +#define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C + +#define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420 + +#define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424 + +#define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428 + +#define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C + +#define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430 + +#define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434 + +#define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438 + +#define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C + +#define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440 + +#define mmDMA2_QM_ARB_CFG_0 0x548A00 + +#define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C + +#define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14 + +#define mmDMA2_QM_ARB_CFG_1 0x548A18 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C + +#define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20 + +#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28 + +#define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C + +#define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34 + +#define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38 + +#define mmDMA2_QM_ARB_SLV_ID 0x548B3C + +#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44 + +#define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48 + +#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C + +#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50 + +#define mmDMA2_QM_ARB_BASE_LO 0x548B54 + +#define mmDMA2_QM_ARB_BASE_HI 0x548B58 + +#define mmDMA2_QM_ARB_STATE_STS 0x548B80 + +#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84 + +#define mmDMA2_QM_ARB_MSG_STS 0x548B88 + +#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C + +#define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C + +#define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0 + +#define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC + +#define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC + +#define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC + +#define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC + +#define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC + +#define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00 + +#define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04 + +#define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08 + +#define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C + +#define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10 + +#define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14 + +#define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18 + +#define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C + +#define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20 + +#define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24 + +#define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28 + +#define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C + +#define mmDMA2_QM_CGM_CFG 0x548C70 + +#define mmDMA2_QM_CGM_STS 0x548C74 + +#define mmDMA2_QM_CGM_CFG1 0x548C78 + +#define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80 + +#define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84 + +#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90 + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0 + +#define mmDMA2_QM_GLBL_AXCACHE 0x548CA4 + +#define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0 + +#define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4 + +#define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8 + +#define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC + +#define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0 + +#define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4 + +#define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8 + +#define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00 + +#endif /* ASIC_REG_DMA2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h new file mode 100644 index 000000000..fb145f416 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_CORE_REGS_H_ +#define ASIC_REG_DMA3_CORE_REGS_H_ + +/* + ***************************************** + * DMA3_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA3_CORE_CFG_0 0x560000 + +#define mmDMA3_CORE_CFG_1 0x560004 + +#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008 + +#define mmDMA3_CORE_SRC_BASE_LO 0x560014 + +#define mmDMA3_CORE_SRC_BASE_HI 0x560018 + +#define mmDMA3_CORE_DST_BASE_LO 0x56001C + +#define mmDMA3_CORE_DST_BASE_HI 0x560020 + +#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C + +#define mmDMA3_CORE_SRC_STRIDE_1 0x560030 + +#define mmDMA3_CORE_SRC_TSIZE_2 0x560034 + +#define mmDMA3_CORE_SRC_STRIDE_2 0x560038 + +#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C + +#define mmDMA3_CORE_SRC_STRIDE_3 0x560040 + +#define mmDMA3_CORE_SRC_TSIZE_4 0x560044 + +#define mmDMA3_CORE_SRC_STRIDE_4 0x560048 + +#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C + +#define mmDMA3_CORE_DST_TSIZE_1 0x560054 + +#define mmDMA3_CORE_DST_STRIDE_1 0x560058 + +#define mmDMA3_CORE_DST_TSIZE_2 0x56005C + +#define mmDMA3_CORE_DST_STRIDE_2 0x560060 + +#define mmDMA3_CORE_DST_TSIZE_3 0x560064 + +#define mmDMA3_CORE_DST_STRIDE_3 0x560068 + +#define mmDMA3_CORE_DST_TSIZE_4 0x56006C + +#define mmDMA3_CORE_DST_STRIDE_4 0x560070 + +#define mmDMA3_CORE_DST_TSIZE_0 0x560074 + +#define mmDMA3_CORE_COMMIT 0x560078 + +#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C + +#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080 + +#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084 + +#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088 + +#define mmDMA3_CORE_TE_NUMROWS 0x560094 + +#define mmDMA3_CORE_PROT 0x5600B8 + +#define mmDMA3_CORE_SECURE_PROPS 0x5600F0 + +#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4 + +#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100 + +#define mmDMA3_CORE_RD_MAX_SIZE 0x560104 + +#define mmDMA3_CORE_RD_ARCACHE 0x560108 + +#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110 + +#define mmDMA3_CORE_RD_INFLIGHTS 0x560114 + +#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120 + +#define mmDMA3_CORE_WR_MAX_AWID 0x560124 + +#define mmDMA3_CORE_WR_AWCACHE 0x560128 + +#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130 + +#define mmDMA3_CORE_WR_INFLIGHTS 0x560134 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C + +#define mmDMA3_CORE_ERR_CFG 0x560160 + +#define mmDMA3_CORE_ERR_CAUSE 0x560164 + +#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170 + +#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174 + +#define mmDMA3_CORE_ERRMSG_WDATA 0x560178 + +#define mmDMA3_CORE_STS0 0x560190 + +#define mmDMA3_CORE_STS1 0x560194 + +#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208 + +#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C + +#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210 + +#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220 + +#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224 + +#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228 + +#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C + +#define mmDMA3_CORE_DBG_STS 0x560230 + +#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234 + +#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238 + +#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h new file mode 100644 index 000000000..a4b461ca3 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_QM_REGS_H_ +#define ASIC_REG_DMA3_QM_REGS_H_ + +/* + ***************************************** + * DMA3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA3_QM_GLBL_CFG0 0x568000 + +#define mmDMA3_QM_GLBL_CFG1 0x568004 + +#define mmDMA3_QM_GLBL_PROT 0x568008 + +#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034 + +#define mmDMA3_QM_GLBL_STS0 0x568038 + +#define mmDMA3_QM_GLBL_STS1_0 0x568040 + +#define mmDMA3_QM_GLBL_STS1_1 0x568044 + +#define mmDMA3_QM_GLBL_STS1_2 0x568048 + +#define mmDMA3_QM_GLBL_STS1_3 0x56804C + +#define mmDMA3_QM_GLBL_STS1_4 0x568050 + +#define mmDMA3_QM_GLBL_MSG_EN_0 0x568054 + +#define mmDMA3_QM_GLBL_MSG_EN_1 0x568058 + +#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C + +#define mmDMA3_QM_GLBL_MSG_EN_3 0x568060 + +#define mmDMA3_QM_GLBL_MSG_EN_4 0x568068 + +#define mmDMA3_QM_PQ_BASE_LO_0 0x568070 + +#define mmDMA3_QM_PQ_BASE_LO_1 0x568074 + +#define mmDMA3_QM_PQ_BASE_LO_2 0x568078 + +#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C + +#define mmDMA3_QM_PQ_BASE_HI_0 0x568080 + +#define mmDMA3_QM_PQ_BASE_HI_1 0x568084 + +#define mmDMA3_QM_PQ_BASE_HI_2 0x568088 + +#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C + +#define mmDMA3_QM_PQ_SIZE_0 0x568090 + +#define mmDMA3_QM_PQ_SIZE_1 0x568094 + +#define mmDMA3_QM_PQ_SIZE_2 0x568098 + +#define mmDMA3_QM_PQ_SIZE_3 0x56809C + +#define mmDMA3_QM_PQ_PI_0 0x5680A0 + +#define mmDMA3_QM_PQ_PI_1 0x5680A4 + +#define mmDMA3_QM_PQ_PI_2 0x5680A8 + +#define mmDMA3_QM_PQ_PI_3 0x5680AC + +#define mmDMA3_QM_PQ_CI_0 0x5680B0 + +#define mmDMA3_QM_PQ_CI_1 0x5680B4 + +#define mmDMA3_QM_PQ_CI_2 0x5680B8 + +#define mmDMA3_QM_PQ_CI_3 0x5680BC + +#define mmDMA3_QM_PQ_CFG0_0 0x5680C0 + +#define mmDMA3_QM_PQ_CFG0_1 0x5680C4 + +#define mmDMA3_QM_PQ_CFG0_2 0x5680C8 + +#define mmDMA3_QM_PQ_CFG0_3 0x5680CC + +#define mmDMA3_QM_PQ_CFG1_0 0x5680D0 + +#define mmDMA3_QM_PQ_CFG1_1 0x5680D4 + +#define mmDMA3_QM_PQ_CFG1_2 0x5680D8 + +#define mmDMA3_QM_PQ_CFG1_3 0x5680DC + +#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0 + +#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4 + +#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8 + +#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC + +#define mmDMA3_QM_PQ_STS0_0 0x5680F0 + +#define mmDMA3_QM_PQ_STS0_1 0x5680F4 + +#define mmDMA3_QM_PQ_STS0_2 0x5680F8 + +#define mmDMA3_QM_PQ_STS0_3 0x5680FC + +#define mmDMA3_QM_PQ_STS1_0 0x568100 + +#define mmDMA3_QM_PQ_STS1_1 0x568104 + +#define mmDMA3_QM_PQ_STS1_2 0x568108 + +#define mmDMA3_QM_PQ_STS1_3 0x56810C + +#define mmDMA3_QM_CQ_CFG0_0 0x568110 + +#define mmDMA3_QM_CQ_CFG0_1 0x568114 + +#define mmDMA3_QM_CQ_CFG0_2 0x568118 + +#define mmDMA3_QM_CQ_CFG0_3 0x56811C + +#define mmDMA3_QM_CQ_CFG0_4 0x568120 + +#define mmDMA3_QM_CQ_CFG1_0 0x568124 + +#define mmDMA3_QM_CQ_CFG1_1 0x568128 + +#define mmDMA3_QM_CQ_CFG1_2 0x56812C + +#define mmDMA3_QM_CQ_CFG1_3 0x568130 + +#define mmDMA3_QM_CQ_CFG1_4 0x568134 + +#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138 + +#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C + +#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140 + +#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144 + +#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148 + +#define mmDMA3_QM_CQ_STS0_0 0x56814C + +#define mmDMA3_QM_CQ_STS0_1 0x568150 + +#define mmDMA3_QM_CQ_STS0_2 0x568154 + +#define mmDMA3_QM_CQ_STS0_3 0x568158 + +#define mmDMA3_QM_CQ_STS0_4 0x56815C + +#define mmDMA3_QM_CQ_STS1_0 0x568160 + +#define mmDMA3_QM_CQ_STS1_1 0x568164 + +#define mmDMA3_QM_CQ_STS1_2 0x568168 + +#define mmDMA3_QM_CQ_STS1_3 0x56816C + +#define mmDMA3_QM_CQ_STS1_4 0x568170 + +#define mmDMA3_QM_CQ_PTR_LO_0 0x568174 + +#define mmDMA3_QM_CQ_PTR_HI_0 0x568178 + +#define mmDMA3_QM_CQ_TSIZE_0 0x56817C + +#define mmDMA3_QM_CQ_CTL_0 0x568180 + +#define mmDMA3_QM_CQ_PTR_LO_1 0x568184 + +#define mmDMA3_QM_CQ_PTR_HI_1 0x568188 + +#define mmDMA3_QM_CQ_TSIZE_1 0x56818C + +#define mmDMA3_QM_CQ_CTL_1 0x568190 + +#define mmDMA3_QM_CQ_PTR_LO_2 0x568194 + +#define mmDMA3_QM_CQ_PTR_HI_2 0x568198 + +#define mmDMA3_QM_CQ_TSIZE_2 0x56819C + +#define mmDMA3_QM_CQ_CTL_2 0x5681A0 + +#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4 + +#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8 + +#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC + +#define mmDMA3_QM_CQ_CTL_3 0x5681B0 + +#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4 + +#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8 + +#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC + +#define mmDMA3_QM_CQ_CTL_4 0x5681C0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4 + +#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8 + +#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC + +#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8 + +#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC + +#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0 + +#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8 + +#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC + +#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0 + +#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4 + +#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8 + +#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC + +#define mmDMA3_QM_CQ_CTL_STS_0 0x568200 + +#define mmDMA3_QM_CQ_CTL_STS_1 0x568204 + +#define mmDMA3_QM_CQ_CTL_STS_2 0x568208 + +#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C + +#define mmDMA3_QM_CQ_CTL_STS_4 0x568210 + +#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214 + +#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218 + +#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C + +#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220 + +#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304 + +#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308 + +#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C + +#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310 + +#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314 + +#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318 + +#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C + +#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320 + +#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324 + +#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328 + +#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C + +#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330 + +#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334 + +#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338 + +#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C + +#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340 + +#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344 + +#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348 + +#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C + +#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350 + +#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354 + +#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358 + +#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C + +#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360 + +#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364 + +#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368 + +#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C + +#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370 + +#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374 + +#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378 + +#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C + +#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380 + +#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384 + +#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388 + +#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C + +#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390 + +#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394 + +#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398 + +#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C + +#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0 + +#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4 + +#define mmDMA3_QM_CP_STS_0 0x5683A8 + +#define mmDMA3_QM_CP_STS_1 0x5683AC + +#define mmDMA3_QM_CP_STS_2 0x5683B0 + +#define mmDMA3_QM_CP_STS_3 0x5683B4 + +#define mmDMA3_QM_CP_STS_4 0x5683B8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC + +#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0 + +#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4 + +#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8 + +#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC + +#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400 + +#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404 + +#define mmDMA3_QM_CP_DBG_0_0 0x568408 + +#define mmDMA3_QM_CP_DBG_0_1 0x56840C + +#define mmDMA3_QM_CP_DBG_0_2 0x568410 + +#define mmDMA3_QM_CP_DBG_0_3 0x568414 + +#define mmDMA3_QM_CP_DBG_0_4 0x568418 + +#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C + +#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420 + +#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424 + +#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428 + +#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C + +#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430 + +#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434 + +#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438 + +#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C + +#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440 + +#define mmDMA3_QM_ARB_CFG_0 0x568A00 + +#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C + +#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14 + +#define mmDMA3_QM_ARB_CFG_1 0x568A18 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C + +#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20 + +#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28 + +#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C + +#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34 + +#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38 + +#define mmDMA3_QM_ARB_SLV_ID 0x568B3C + +#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44 + +#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48 + +#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C + +#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50 + +#define mmDMA3_QM_ARB_BASE_LO 0x568B54 + +#define mmDMA3_QM_ARB_BASE_HI 0x568B58 + +#define mmDMA3_QM_ARB_STATE_STS 0x568B80 + +#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84 + +#define mmDMA3_QM_ARB_MSG_STS 0x568B88 + +#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C + +#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C + +#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0 + +#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC + +#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC + +#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC + +#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC + +#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC + +#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00 + +#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04 + +#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08 + +#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C + +#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10 + +#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14 + +#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18 + +#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C + +#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20 + +#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24 + +#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28 + +#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C + +#define mmDMA3_QM_CGM_CFG 0x568C70 + +#define mmDMA3_QM_CGM_STS 0x568C74 + +#define mmDMA3_QM_CGM_CFG1 0x568C78 + +#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80 + +#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84 + +#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90 + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0 + +#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4 + +#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0 + +#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4 + +#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8 + +#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC + +#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0 + +#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4 + +#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8 + +#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00 + +#endif /* ASIC_REG_DMA3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h new file mode 100644 index 000000000..192d11404 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_CORE_REGS_H_ +#define ASIC_REG_DMA4_CORE_REGS_H_ + +/* + ***************************************** + * DMA4_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA4_CORE_CFG_0 0x580000 + +#define mmDMA4_CORE_CFG_1 0x580004 + +#define mmDMA4_CORE_LBW_MAX_OUTSTAND 0x580008 + +#define mmDMA4_CORE_SRC_BASE_LO 0x580014 + +#define mmDMA4_CORE_SRC_BASE_HI 0x580018 + +#define mmDMA4_CORE_DST_BASE_LO 0x58001C + +#define mmDMA4_CORE_DST_BASE_HI 0x580020 + +#define mmDMA4_CORE_SRC_TSIZE_1 0x58002C + +#define mmDMA4_CORE_SRC_STRIDE_1 0x580030 + +#define mmDMA4_CORE_SRC_TSIZE_2 0x580034 + +#define mmDMA4_CORE_SRC_STRIDE_2 0x580038 + +#define mmDMA4_CORE_SRC_TSIZE_3 0x58003C + +#define mmDMA4_CORE_SRC_STRIDE_3 0x580040 + +#define mmDMA4_CORE_SRC_TSIZE_4 0x580044 + +#define mmDMA4_CORE_SRC_STRIDE_4 0x580048 + +#define mmDMA4_CORE_SRC_TSIZE_0 0x58004C + +#define mmDMA4_CORE_DST_TSIZE_1 0x580054 + +#define mmDMA4_CORE_DST_STRIDE_1 0x580058 + +#define mmDMA4_CORE_DST_TSIZE_2 0x58005C + +#define mmDMA4_CORE_DST_STRIDE_2 0x580060 + +#define mmDMA4_CORE_DST_TSIZE_3 0x580064 + +#define mmDMA4_CORE_DST_STRIDE_3 0x580068 + +#define mmDMA4_CORE_DST_TSIZE_4 0x58006C + +#define mmDMA4_CORE_DST_STRIDE_4 0x580070 + +#define mmDMA4_CORE_DST_TSIZE_0 0x580074 + +#define mmDMA4_CORE_COMMIT 0x580078 + +#define mmDMA4_CORE_WR_COMP_WDATA 0x58007C + +#define mmDMA4_CORE_WR_COMP_ADDR_LO 0x580080 + +#define mmDMA4_CORE_WR_COMP_ADDR_HI 0x580084 + +#define mmDMA4_CORE_WR_COMP_AWUSER_31_11 0x580088 + +#define mmDMA4_CORE_TE_NUMROWS 0x580094 + +#define mmDMA4_CORE_PROT 0x5800B8 + +#define mmDMA4_CORE_SECURE_PROPS 0x5800F0 + +#define mmDMA4_CORE_NON_SECURE_PROPS 0x5800F4 + +#define mmDMA4_CORE_RD_MAX_OUTSTAND 0x580100 + +#define mmDMA4_CORE_RD_MAX_SIZE 0x580104 + +#define mmDMA4_CORE_RD_ARCACHE 0x580108 + +#define mmDMA4_CORE_RD_ARUSER_31_11 0x580110 + +#define mmDMA4_CORE_RD_INFLIGHTS 0x580114 + +#define mmDMA4_CORE_WR_MAX_OUTSTAND 0x580120 + +#define mmDMA4_CORE_WR_MAX_AWID 0x580124 + +#define mmDMA4_CORE_WR_AWCACHE 0x580128 + +#define mmDMA4_CORE_WR_AWUSER_31_11 0x580130 + +#define mmDMA4_CORE_WR_INFLIGHTS 0x580134 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_0 0x580150 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_1 0x580154 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_0 0x580158 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_1 0x58015C + +#define mmDMA4_CORE_ERR_CFG 0x580160 + +#define mmDMA4_CORE_ERR_CAUSE 0x580164 + +#define mmDMA4_CORE_ERRMSG_ADDR_LO 0x580170 + +#define mmDMA4_CORE_ERRMSG_ADDR_HI 0x580174 + +#define mmDMA4_CORE_ERRMSG_WDATA 0x580178 + +#define mmDMA4_CORE_STS0 0x580190 + +#define mmDMA4_CORE_STS1 0x580194 + +#define mmDMA4_CORE_RD_DBGMEM_ADD 0x580200 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_WR 0x580204 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_RD 0x580208 + +#define mmDMA4_CORE_RD_DBGMEM_CTRL 0x58020C + +#define mmDMA4_CORE_RD_DBGMEM_RC 0x580210 + +#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT 0x580220 + +#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT 0x580224 + +#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT 0x580228 + +#define mmDMA4_CORE_DBG_DESC_CNT 0x58022C + +#define mmDMA4_CORE_DBG_STS 0x580230 + +#define mmDMA4_CORE_DBG_RD_DESC_ID 0x580234 + +#define mmDMA4_CORE_DBG_WR_DESC_ID 0x580238 + +#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h new file mode 100644 index 000000000..f0cbda0d1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_QM_REGS_H_ +#define ASIC_REG_DMA4_QM_REGS_H_ + +/* + ***************************************** + * DMA4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA4_QM_GLBL_CFG0 0x588000 + +#define mmDMA4_QM_GLBL_CFG1 0x588004 + +#define mmDMA4_QM_GLBL_PROT 0x588008 + +#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034 + +#define mmDMA4_QM_GLBL_STS0 0x588038 + +#define mmDMA4_QM_GLBL_STS1_0 0x588040 + +#define mmDMA4_QM_GLBL_STS1_1 0x588044 + +#define mmDMA4_QM_GLBL_STS1_2 0x588048 + +#define mmDMA4_QM_GLBL_STS1_3 0x58804C + +#define mmDMA4_QM_GLBL_STS1_4 0x588050 + +#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054 + +#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058 + +#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C + +#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060 + +#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068 + +#define mmDMA4_QM_PQ_BASE_LO_0 0x588070 + +#define mmDMA4_QM_PQ_BASE_LO_1 0x588074 + +#define mmDMA4_QM_PQ_BASE_LO_2 0x588078 + +#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C + +#define mmDMA4_QM_PQ_BASE_HI_0 0x588080 + +#define mmDMA4_QM_PQ_BASE_HI_1 0x588084 + +#define mmDMA4_QM_PQ_BASE_HI_2 0x588088 + +#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C + +#define mmDMA4_QM_PQ_SIZE_0 0x588090 + +#define mmDMA4_QM_PQ_SIZE_1 0x588094 + +#define mmDMA4_QM_PQ_SIZE_2 0x588098 + +#define mmDMA4_QM_PQ_SIZE_3 0x58809C + +#define mmDMA4_QM_PQ_PI_0 0x5880A0 + +#define mmDMA4_QM_PQ_PI_1 0x5880A4 + +#define mmDMA4_QM_PQ_PI_2 0x5880A8 + +#define mmDMA4_QM_PQ_PI_3 0x5880AC + +#define mmDMA4_QM_PQ_CI_0 0x5880B0 + +#define mmDMA4_QM_PQ_CI_1 0x5880B4 + +#define mmDMA4_QM_PQ_CI_2 0x5880B8 + +#define mmDMA4_QM_PQ_CI_3 0x5880BC + +#define mmDMA4_QM_PQ_CFG0_0 0x5880C0 + +#define mmDMA4_QM_PQ_CFG0_1 0x5880C4 + +#define mmDMA4_QM_PQ_CFG0_2 0x5880C8 + +#define mmDMA4_QM_PQ_CFG0_3 0x5880CC + +#define mmDMA4_QM_PQ_CFG1_0 0x5880D0 + +#define mmDMA4_QM_PQ_CFG1_1 0x5880D4 + +#define mmDMA4_QM_PQ_CFG1_2 0x5880D8 + +#define mmDMA4_QM_PQ_CFG1_3 0x5880DC + +#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0 + +#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4 + +#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8 + +#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC + +#define mmDMA4_QM_PQ_STS0_0 0x5880F0 + +#define mmDMA4_QM_PQ_STS0_1 0x5880F4 + +#define mmDMA4_QM_PQ_STS0_2 0x5880F8 + +#define mmDMA4_QM_PQ_STS0_3 0x5880FC + +#define mmDMA4_QM_PQ_STS1_0 0x588100 + +#define mmDMA4_QM_PQ_STS1_1 0x588104 + +#define mmDMA4_QM_PQ_STS1_2 0x588108 + +#define mmDMA4_QM_PQ_STS1_3 0x58810C + +#define mmDMA4_QM_CQ_CFG0_0 0x588110 + +#define mmDMA4_QM_CQ_CFG0_1 0x588114 + +#define mmDMA4_QM_CQ_CFG0_2 0x588118 + +#define mmDMA4_QM_CQ_CFG0_3 0x58811C + +#define mmDMA4_QM_CQ_CFG0_4 0x588120 + +#define mmDMA4_QM_CQ_CFG1_0 0x588124 + +#define mmDMA4_QM_CQ_CFG1_1 0x588128 + +#define mmDMA4_QM_CQ_CFG1_2 0x58812C + +#define mmDMA4_QM_CQ_CFG1_3 0x588130 + +#define mmDMA4_QM_CQ_CFG1_4 0x588134 + +#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138 + +#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C + +#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140 + +#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144 + +#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148 + +#define mmDMA4_QM_CQ_STS0_0 0x58814C + +#define mmDMA4_QM_CQ_STS0_1 0x588150 + +#define mmDMA4_QM_CQ_STS0_2 0x588154 + +#define mmDMA4_QM_CQ_STS0_3 0x588158 + +#define mmDMA4_QM_CQ_STS0_4 0x58815C + +#define mmDMA4_QM_CQ_STS1_0 0x588160 + +#define mmDMA4_QM_CQ_STS1_1 0x588164 + +#define mmDMA4_QM_CQ_STS1_2 0x588168 + +#define mmDMA4_QM_CQ_STS1_3 0x58816C + +#define mmDMA4_QM_CQ_STS1_4 0x588170 + +#define mmDMA4_QM_CQ_PTR_LO_0 0x588174 + +#define mmDMA4_QM_CQ_PTR_HI_0 0x588178 + +#define mmDMA4_QM_CQ_TSIZE_0 0x58817C + +#define mmDMA4_QM_CQ_CTL_0 0x588180 + +#define mmDMA4_QM_CQ_PTR_LO_1 0x588184 + +#define mmDMA4_QM_CQ_PTR_HI_1 0x588188 + +#define mmDMA4_QM_CQ_TSIZE_1 0x58818C + +#define mmDMA4_QM_CQ_CTL_1 0x588190 + +#define mmDMA4_QM_CQ_PTR_LO_2 0x588194 + +#define mmDMA4_QM_CQ_PTR_HI_2 0x588198 + +#define mmDMA4_QM_CQ_TSIZE_2 0x58819C + +#define mmDMA4_QM_CQ_CTL_2 0x5881A0 + +#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4 + +#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8 + +#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC + +#define mmDMA4_QM_CQ_CTL_3 0x5881B0 + +#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4 + +#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8 + +#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC + +#define mmDMA4_QM_CQ_CTL_4 0x5881C0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4 + +#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8 + +#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC + +#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8 + +#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC + +#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0 + +#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8 + +#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC + +#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0 + +#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4 + +#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8 + +#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC + +#define mmDMA4_QM_CQ_CTL_STS_0 0x588200 + +#define mmDMA4_QM_CQ_CTL_STS_1 0x588204 + +#define mmDMA4_QM_CQ_CTL_STS_2 0x588208 + +#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C + +#define mmDMA4_QM_CQ_CTL_STS_4 0x588210 + +#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214 + +#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218 + +#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C + +#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220 + +#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304 + +#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308 + +#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C + +#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310 + +#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314 + +#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318 + +#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C + +#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320 + +#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324 + +#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328 + +#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C + +#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330 + +#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334 + +#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338 + +#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C + +#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340 + +#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344 + +#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348 + +#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C + +#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350 + +#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354 + +#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358 + +#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C + +#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360 + +#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364 + +#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368 + +#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C + +#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370 + +#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374 + +#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378 + +#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C + +#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380 + +#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384 + +#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388 + +#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C + +#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390 + +#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394 + +#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398 + +#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C + +#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0 + +#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4 + +#define mmDMA4_QM_CP_STS_0 0x5883A8 + +#define mmDMA4_QM_CP_STS_1 0x5883AC + +#define mmDMA4_QM_CP_STS_2 0x5883B0 + +#define mmDMA4_QM_CP_STS_3 0x5883B4 + +#define mmDMA4_QM_CP_STS_4 0x5883B8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC + +#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0 + +#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4 + +#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8 + +#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC + +#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400 + +#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404 + +#define mmDMA4_QM_CP_DBG_0_0 0x588408 + +#define mmDMA4_QM_CP_DBG_0_1 0x58840C + +#define mmDMA4_QM_CP_DBG_0_2 0x588410 + +#define mmDMA4_QM_CP_DBG_0_3 0x588414 + +#define mmDMA4_QM_CP_DBG_0_4 0x588418 + +#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C + +#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420 + +#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424 + +#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428 + +#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C + +#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430 + +#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434 + +#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438 + +#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C + +#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440 + +#define mmDMA4_QM_ARB_CFG_0 0x588A00 + +#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C + +#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14 + +#define mmDMA4_QM_ARB_CFG_1 0x588A18 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C + +#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20 + +#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28 + +#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C + +#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34 + +#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38 + +#define mmDMA4_QM_ARB_SLV_ID 0x588B3C + +#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44 + +#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48 + +#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C + +#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50 + +#define mmDMA4_QM_ARB_BASE_LO 0x588B54 + +#define mmDMA4_QM_ARB_BASE_HI 0x588B58 + +#define mmDMA4_QM_ARB_STATE_STS 0x588B80 + +#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84 + +#define mmDMA4_QM_ARB_MSG_STS 0x588B88 + +#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C + +#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C + +#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0 + +#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC + +#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC + +#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC + +#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC + +#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC + +#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00 + +#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04 + +#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08 + +#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C + +#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10 + +#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14 + +#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18 + +#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C + +#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20 + +#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24 + +#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28 + +#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C + +#define mmDMA4_QM_CGM_CFG 0x588C70 + +#define mmDMA4_QM_CGM_STS 0x588C74 + +#define mmDMA4_QM_CGM_CFG1 0x588C78 + +#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80 + +#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84 + +#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90 + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0 + +#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4 + +#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0 + +#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4 + +#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8 + +#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC + +#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0 + +#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4 + +#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8 + +#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00 + +#endif /* ASIC_REG_DMA4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h new file mode 100644 index 000000000..6e07c6fb6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_CORE_REGS_H_ +#define ASIC_REG_DMA5_CORE_REGS_H_ + +/* + ***************************************** + * DMA5_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA5_CORE_CFG_0 0x5A0000 + +#define mmDMA5_CORE_CFG_1 0x5A0004 + +#define mmDMA5_CORE_LBW_MAX_OUTSTAND 0x5A0008 + +#define mmDMA5_CORE_SRC_BASE_LO 0x5A0014 + +#define mmDMA5_CORE_SRC_BASE_HI 0x5A0018 + +#define mmDMA5_CORE_DST_BASE_LO 0x5A001C + +#define mmDMA5_CORE_DST_BASE_HI 0x5A0020 + +#define mmDMA5_CORE_SRC_TSIZE_1 0x5A002C + +#define mmDMA5_CORE_SRC_STRIDE_1 0x5A0030 + +#define mmDMA5_CORE_SRC_TSIZE_2 0x5A0034 + +#define mmDMA5_CORE_SRC_STRIDE_2 0x5A0038 + +#define mmDMA5_CORE_SRC_TSIZE_3 0x5A003C + +#define mmDMA5_CORE_SRC_STRIDE_3 0x5A0040 + +#define mmDMA5_CORE_SRC_TSIZE_4 0x5A0044 + +#define mmDMA5_CORE_SRC_STRIDE_4 0x5A0048 + +#define mmDMA5_CORE_SRC_TSIZE_0 0x5A004C + +#define mmDMA5_CORE_DST_TSIZE_1 0x5A0054 + +#define mmDMA5_CORE_DST_STRIDE_1 0x5A0058 + +#define mmDMA5_CORE_DST_TSIZE_2 0x5A005C + +#define mmDMA5_CORE_DST_STRIDE_2 0x5A0060 + +#define mmDMA5_CORE_DST_TSIZE_3 0x5A0064 + +#define mmDMA5_CORE_DST_STRIDE_3 0x5A0068 + +#define mmDMA5_CORE_DST_TSIZE_4 0x5A006C + +#define mmDMA5_CORE_DST_STRIDE_4 0x5A0070 + +#define mmDMA5_CORE_DST_TSIZE_0 0x5A0074 + +#define mmDMA5_CORE_COMMIT 0x5A0078 + +#define mmDMA5_CORE_WR_COMP_WDATA 0x5A007C + +#define mmDMA5_CORE_WR_COMP_ADDR_LO 0x5A0080 + +#define mmDMA5_CORE_WR_COMP_ADDR_HI 0x5A0084 + +#define mmDMA5_CORE_WR_COMP_AWUSER_31_11 0x5A0088 + +#define mmDMA5_CORE_TE_NUMROWS 0x5A0094 + +#define mmDMA5_CORE_PROT 0x5A00B8 + +#define mmDMA5_CORE_SECURE_PROPS 0x5A00F0 + +#define mmDMA5_CORE_NON_SECURE_PROPS 0x5A00F4 + +#define mmDMA5_CORE_RD_MAX_OUTSTAND 0x5A0100 + +#define mmDMA5_CORE_RD_MAX_SIZE 0x5A0104 + +#define mmDMA5_CORE_RD_ARCACHE 0x5A0108 + +#define mmDMA5_CORE_RD_ARUSER_31_11 0x5A0110 + +#define mmDMA5_CORE_RD_INFLIGHTS 0x5A0114 + +#define mmDMA5_CORE_WR_MAX_OUTSTAND 0x5A0120 + +#define mmDMA5_CORE_WR_MAX_AWID 0x5A0124 + +#define mmDMA5_CORE_WR_AWCACHE 0x5A0128 + +#define mmDMA5_CORE_WR_AWUSER_31_11 0x5A0130 + +#define mmDMA5_CORE_WR_INFLIGHTS 0x5A0134 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_0 0x5A0150 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_1 0x5A0154 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_0 0x5A0158 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_1 0x5A015C + +#define mmDMA5_CORE_ERR_CFG 0x5A0160 + +#define mmDMA5_CORE_ERR_CAUSE 0x5A0164 + +#define mmDMA5_CORE_ERRMSG_ADDR_LO 0x5A0170 + +#define mmDMA5_CORE_ERRMSG_ADDR_HI 0x5A0174 + +#define mmDMA5_CORE_ERRMSG_WDATA 0x5A0178 + +#define mmDMA5_CORE_STS0 0x5A0190 + +#define mmDMA5_CORE_STS1 0x5A0194 + +#define mmDMA5_CORE_RD_DBGMEM_ADD 0x5A0200 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_WR 0x5A0204 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_RD 0x5A0208 + +#define mmDMA5_CORE_RD_DBGMEM_CTRL 0x5A020C + +#define mmDMA5_CORE_RD_DBGMEM_RC 0x5A0210 + +#define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT 0x5A0220 + +#define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT 0x5A0224 + +#define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT 0x5A0228 + +#define mmDMA5_CORE_DBG_DESC_CNT 0x5A022C + +#define mmDMA5_CORE_DBG_STS 0x5A0230 + +#define mmDMA5_CORE_DBG_RD_DESC_ID 0x5A0234 + +#define mmDMA5_CORE_DBG_WR_DESC_ID 0x5A0238 + +#endif /* ASIC_REG_DMA5_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h new file mode 100644 index 000000000..0faea2175 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_QM_REGS_H_ +#define ASIC_REG_DMA5_QM_REGS_H_ + +/* + ***************************************** + * DMA5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA5_QM_GLBL_CFG0 0x5A8000 + +#define mmDMA5_QM_GLBL_CFG1 0x5A8004 + +#define mmDMA5_QM_GLBL_PROT 0x5A8008 + +#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034 + +#define mmDMA5_QM_GLBL_STS0 0x5A8038 + +#define mmDMA5_QM_GLBL_STS1_0 0x5A8040 + +#define mmDMA5_QM_GLBL_STS1_1 0x5A8044 + +#define mmDMA5_QM_GLBL_STS1_2 0x5A8048 + +#define mmDMA5_QM_GLBL_STS1_3 0x5A804C + +#define mmDMA5_QM_GLBL_STS1_4 0x5A8050 + +#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054 + +#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058 + +#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C + +#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060 + +#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068 + +#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070 + +#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074 + +#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078 + +#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C + +#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080 + +#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084 + +#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088 + +#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C + +#define mmDMA5_QM_PQ_SIZE_0 0x5A8090 + +#define mmDMA5_QM_PQ_SIZE_1 0x5A8094 + +#define mmDMA5_QM_PQ_SIZE_2 0x5A8098 + +#define mmDMA5_QM_PQ_SIZE_3 0x5A809C + +#define mmDMA5_QM_PQ_PI_0 0x5A80A0 + +#define mmDMA5_QM_PQ_PI_1 0x5A80A4 + +#define mmDMA5_QM_PQ_PI_2 0x5A80A8 + +#define mmDMA5_QM_PQ_PI_3 0x5A80AC + +#define mmDMA5_QM_PQ_CI_0 0x5A80B0 + +#define mmDMA5_QM_PQ_CI_1 0x5A80B4 + +#define mmDMA5_QM_PQ_CI_2 0x5A80B8 + +#define mmDMA5_QM_PQ_CI_3 0x5A80BC + +#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0 + +#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4 + +#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8 + +#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC + +#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0 + +#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4 + +#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8 + +#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC + +#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0 + +#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4 + +#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8 + +#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC + +#define mmDMA5_QM_PQ_STS0_0 0x5A80F0 + +#define mmDMA5_QM_PQ_STS0_1 0x5A80F4 + +#define mmDMA5_QM_PQ_STS0_2 0x5A80F8 + +#define mmDMA5_QM_PQ_STS0_3 0x5A80FC + +#define mmDMA5_QM_PQ_STS1_0 0x5A8100 + +#define mmDMA5_QM_PQ_STS1_1 0x5A8104 + +#define mmDMA5_QM_PQ_STS1_2 0x5A8108 + +#define mmDMA5_QM_PQ_STS1_3 0x5A810C + +#define mmDMA5_QM_CQ_CFG0_0 0x5A8110 + +#define mmDMA5_QM_CQ_CFG0_1 0x5A8114 + +#define mmDMA5_QM_CQ_CFG0_2 0x5A8118 + +#define mmDMA5_QM_CQ_CFG0_3 0x5A811C + +#define mmDMA5_QM_CQ_CFG0_4 0x5A8120 + +#define mmDMA5_QM_CQ_CFG1_0 0x5A8124 + +#define mmDMA5_QM_CQ_CFG1_1 0x5A8128 + +#define mmDMA5_QM_CQ_CFG1_2 0x5A812C + +#define mmDMA5_QM_CQ_CFG1_3 0x5A8130 + +#define mmDMA5_QM_CQ_CFG1_4 0x5A8134 + +#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138 + +#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C + +#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140 + +#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144 + +#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148 + +#define mmDMA5_QM_CQ_STS0_0 0x5A814C + +#define mmDMA5_QM_CQ_STS0_1 0x5A8150 + +#define mmDMA5_QM_CQ_STS0_2 0x5A8154 + +#define mmDMA5_QM_CQ_STS0_3 0x5A8158 + +#define mmDMA5_QM_CQ_STS0_4 0x5A815C + +#define mmDMA5_QM_CQ_STS1_0 0x5A8160 + +#define mmDMA5_QM_CQ_STS1_1 0x5A8164 + +#define mmDMA5_QM_CQ_STS1_2 0x5A8168 + +#define mmDMA5_QM_CQ_STS1_3 0x5A816C + +#define mmDMA5_QM_CQ_STS1_4 0x5A8170 + +#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174 + +#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178 + +#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C + +#define mmDMA5_QM_CQ_CTL_0 0x5A8180 + +#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184 + +#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188 + +#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C + +#define mmDMA5_QM_CQ_CTL_1 0x5A8190 + +#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194 + +#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198 + +#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C + +#define mmDMA5_QM_CQ_CTL_2 0x5A81A0 + +#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4 + +#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8 + +#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC + +#define mmDMA5_QM_CQ_CTL_3 0x5A81B0 + +#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4 + +#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8 + +#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC + +#define mmDMA5_QM_CQ_CTL_4 0x5A81C0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4 + +#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8 + +#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC + +#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8 + +#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC + +#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0 + +#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8 + +#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC + +#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0 + +#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4 + +#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8 + +#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC + +#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200 + +#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204 + +#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208 + +#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C + +#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210 + +#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214 + +#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218 + +#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C + +#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220 + +#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304 + +#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308 + +#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C + +#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310 + +#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314 + +#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318 + +#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C + +#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320 + +#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324 + +#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328 + +#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C + +#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330 + +#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334 + +#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338 + +#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C + +#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340 + +#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344 + +#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348 + +#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C + +#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350 + +#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354 + +#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358 + +#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C + +#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360 + +#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364 + +#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368 + +#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C + +#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370 + +#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374 + +#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378 + +#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C + +#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380 + +#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384 + +#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388 + +#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C + +#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390 + +#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394 + +#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398 + +#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C + +#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0 + +#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4 + +#define mmDMA5_QM_CP_STS_0 0x5A83A8 + +#define mmDMA5_QM_CP_STS_1 0x5A83AC + +#define mmDMA5_QM_CP_STS_2 0x5A83B0 + +#define mmDMA5_QM_CP_STS_3 0x5A83B4 + +#define mmDMA5_QM_CP_STS_4 0x5A83B8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC + +#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0 + +#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4 + +#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8 + +#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC + +#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400 + +#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404 + +#define mmDMA5_QM_CP_DBG_0_0 0x5A8408 + +#define mmDMA5_QM_CP_DBG_0_1 0x5A840C + +#define mmDMA5_QM_CP_DBG_0_2 0x5A8410 + +#define mmDMA5_QM_CP_DBG_0_3 0x5A8414 + +#define mmDMA5_QM_CP_DBG_0_4 0x5A8418 + +#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C + +#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420 + +#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424 + +#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428 + +#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C + +#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430 + +#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434 + +#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438 + +#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C + +#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440 + +#define mmDMA5_QM_ARB_CFG_0 0x5A8A00 + +#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C + +#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14 + +#define mmDMA5_QM_ARB_CFG_1 0x5A8A18 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C + +#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20 + +#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28 + +#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C + +#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34 + +#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38 + +#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C + +#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44 + +#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48 + +#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C + +#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50 + +#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54 + +#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58 + +#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80 + +#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84 + +#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88 + +#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C + +#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C + +#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0 + +#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC + +#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC + +#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC + +#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC + +#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC + +#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00 + +#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04 + +#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08 + +#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C + +#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10 + +#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14 + +#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18 + +#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C + +#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20 + +#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24 + +#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28 + +#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C + +#define mmDMA5_QM_CGM_CFG 0x5A8C70 + +#define mmDMA5_QM_CGM_STS 0x5A8C74 + +#define mmDMA5_QM_CGM_CFG1 0x5A8C78 + +#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80 + +#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84 + +#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90 + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0 + +#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4 + +#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0 + +#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4 + +#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8 + +#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC + +#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0 + +#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4 + +#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8 + +#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00 + +#endif /* ASIC_REG_DMA5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h new file mode 100644 index 000000000..4962c13e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_CORE_REGS_H_ +#define ASIC_REG_DMA6_CORE_REGS_H_ + +/* + ***************************************** + * DMA6_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA6_CORE_CFG_0 0x5C0000 + +#define mmDMA6_CORE_CFG_1 0x5C0004 + +#define mmDMA6_CORE_LBW_MAX_OUTSTAND 0x5C0008 + +#define mmDMA6_CORE_SRC_BASE_LO 0x5C0014 + +#define mmDMA6_CORE_SRC_BASE_HI 0x5C0018 + +#define mmDMA6_CORE_DST_BASE_LO 0x5C001C + +#define mmDMA6_CORE_DST_BASE_HI 0x5C0020 + +#define mmDMA6_CORE_SRC_TSIZE_1 0x5C002C + +#define mmDMA6_CORE_SRC_STRIDE_1 0x5C0030 + +#define mmDMA6_CORE_SRC_TSIZE_2 0x5C0034 + +#define mmDMA6_CORE_SRC_STRIDE_2 0x5C0038 + +#define mmDMA6_CORE_SRC_TSIZE_3 0x5C003C + +#define mmDMA6_CORE_SRC_STRIDE_3 0x5C0040 + +#define mmDMA6_CORE_SRC_TSIZE_4 0x5C0044 + +#define mmDMA6_CORE_SRC_STRIDE_4 0x5C0048 + +#define mmDMA6_CORE_SRC_TSIZE_0 0x5C004C + +#define mmDMA6_CORE_DST_TSIZE_1 0x5C0054 + +#define mmDMA6_CORE_DST_STRIDE_1 0x5C0058 + +#define mmDMA6_CORE_DST_TSIZE_2 0x5C005C + +#define mmDMA6_CORE_DST_STRIDE_2 0x5C0060 + +#define mmDMA6_CORE_DST_TSIZE_3 0x5C0064 + +#define mmDMA6_CORE_DST_STRIDE_3 0x5C0068 + +#define mmDMA6_CORE_DST_TSIZE_4 0x5C006C + +#define mmDMA6_CORE_DST_STRIDE_4 0x5C0070 + +#define mmDMA6_CORE_DST_TSIZE_0 0x5C0074 + +#define mmDMA6_CORE_COMMIT 0x5C0078 + +#define mmDMA6_CORE_WR_COMP_WDATA 0x5C007C + +#define mmDMA6_CORE_WR_COMP_ADDR_LO 0x5C0080 + +#define mmDMA6_CORE_WR_COMP_ADDR_HI 0x5C0084 + +#define mmDMA6_CORE_WR_COMP_AWUSER_31_11 0x5C0088 + +#define mmDMA6_CORE_TE_NUMROWS 0x5C0094 + +#define mmDMA6_CORE_PROT 0x5C00B8 + +#define mmDMA6_CORE_SECURE_PROPS 0x5C00F0 + +#define mmDMA6_CORE_NON_SECURE_PROPS 0x5C00F4 + +#define mmDMA6_CORE_RD_MAX_OUTSTAND 0x5C0100 + +#define mmDMA6_CORE_RD_MAX_SIZE 0x5C0104 + +#define mmDMA6_CORE_RD_ARCACHE 0x5C0108 + +#define mmDMA6_CORE_RD_ARUSER_31_11 0x5C0110 + +#define mmDMA6_CORE_RD_INFLIGHTS 0x5C0114 + +#define mmDMA6_CORE_WR_MAX_OUTSTAND 0x5C0120 + +#define mmDMA6_CORE_WR_MAX_AWID 0x5C0124 + +#define mmDMA6_CORE_WR_AWCACHE 0x5C0128 + +#define mmDMA6_CORE_WR_AWUSER_31_11 0x5C0130 + +#define mmDMA6_CORE_WR_INFLIGHTS 0x5C0134 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_0 0x5C0150 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_1 0x5C0154 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_0 0x5C0158 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_1 0x5C015C + +#define mmDMA6_CORE_ERR_CFG 0x5C0160 + +#define mmDMA6_CORE_ERR_CAUSE 0x5C0164 + +#define mmDMA6_CORE_ERRMSG_ADDR_LO 0x5C0170 + +#define mmDMA6_CORE_ERRMSG_ADDR_HI 0x5C0174 + +#define mmDMA6_CORE_ERRMSG_WDATA 0x5C0178 + +#define mmDMA6_CORE_STS0 0x5C0190 + +#define mmDMA6_CORE_STS1 0x5C0194 + +#define mmDMA6_CORE_RD_DBGMEM_ADD 0x5C0200 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_WR 0x5C0204 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_RD 0x5C0208 + +#define mmDMA6_CORE_RD_DBGMEM_CTRL 0x5C020C + +#define mmDMA6_CORE_RD_DBGMEM_RC 0x5C0210 + +#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT 0x5C0220 + +#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT 0x5C0224 + +#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT 0x5C0228 + +#define mmDMA6_CORE_DBG_DESC_CNT 0x5C022C + +#define mmDMA6_CORE_DBG_STS 0x5C0230 + +#define mmDMA6_CORE_DBG_RD_DESC_ID 0x5C0234 + +#define mmDMA6_CORE_DBG_WR_DESC_ID 0x5C0238 + +#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h new file mode 100644 index 000000000..af87adb94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_QM_REGS_H_ +#define ASIC_REG_DMA6_QM_REGS_H_ + +/* + ***************************************** + * DMA6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA6_QM_GLBL_CFG0 0x5C8000 + +#define mmDMA6_QM_GLBL_CFG1 0x5C8004 + +#define mmDMA6_QM_GLBL_PROT 0x5C8008 + +#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034 + +#define mmDMA6_QM_GLBL_STS0 0x5C8038 + +#define mmDMA6_QM_GLBL_STS1_0 0x5C8040 + +#define mmDMA6_QM_GLBL_STS1_1 0x5C8044 + +#define mmDMA6_QM_GLBL_STS1_2 0x5C8048 + +#define mmDMA6_QM_GLBL_STS1_3 0x5C804C + +#define mmDMA6_QM_GLBL_STS1_4 0x5C8050 + +#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054 + +#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058 + +#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C + +#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060 + +#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068 + +#define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070 + +#define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074 + +#define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078 + +#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C + +#define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080 + +#define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084 + +#define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088 + +#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C + +#define mmDMA6_QM_PQ_SIZE_0 0x5C8090 + +#define mmDMA6_QM_PQ_SIZE_1 0x5C8094 + +#define mmDMA6_QM_PQ_SIZE_2 0x5C8098 + +#define mmDMA6_QM_PQ_SIZE_3 0x5C809C + +#define mmDMA6_QM_PQ_PI_0 0x5C80A0 + +#define mmDMA6_QM_PQ_PI_1 0x5C80A4 + +#define mmDMA6_QM_PQ_PI_2 0x5C80A8 + +#define mmDMA6_QM_PQ_PI_3 0x5C80AC + +#define mmDMA6_QM_PQ_CI_0 0x5C80B0 + +#define mmDMA6_QM_PQ_CI_1 0x5C80B4 + +#define mmDMA6_QM_PQ_CI_2 0x5C80B8 + +#define mmDMA6_QM_PQ_CI_3 0x5C80BC + +#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0 + +#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4 + +#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8 + +#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC + +#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0 + +#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4 + +#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8 + +#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC + +#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0 + +#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4 + +#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8 + +#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC + +#define mmDMA6_QM_PQ_STS0_0 0x5C80F0 + +#define mmDMA6_QM_PQ_STS0_1 0x5C80F4 + +#define mmDMA6_QM_PQ_STS0_2 0x5C80F8 + +#define mmDMA6_QM_PQ_STS0_3 0x5C80FC + +#define mmDMA6_QM_PQ_STS1_0 0x5C8100 + +#define mmDMA6_QM_PQ_STS1_1 0x5C8104 + +#define mmDMA6_QM_PQ_STS1_2 0x5C8108 + +#define mmDMA6_QM_PQ_STS1_3 0x5C810C + +#define mmDMA6_QM_CQ_CFG0_0 0x5C8110 + +#define mmDMA6_QM_CQ_CFG0_1 0x5C8114 + +#define mmDMA6_QM_CQ_CFG0_2 0x5C8118 + +#define mmDMA6_QM_CQ_CFG0_3 0x5C811C + +#define mmDMA6_QM_CQ_CFG0_4 0x5C8120 + +#define mmDMA6_QM_CQ_CFG1_0 0x5C8124 + +#define mmDMA6_QM_CQ_CFG1_1 0x5C8128 + +#define mmDMA6_QM_CQ_CFG1_2 0x5C812C + +#define mmDMA6_QM_CQ_CFG1_3 0x5C8130 + +#define mmDMA6_QM_CQ_CFG1_4 0x5C8134 + +#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138 + +#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C + +#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140 + +#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144 + +#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148 + +#define mmDMA6_QM_CQ_STS0_0 0x5C814C + +#define mmDMA6_QM_CQ_STS0_1 0x5C8150 + +#define mmDMA6_QM_CQ_STS0_2 0x5C8154 + +#define mmDMA6_QM_CQ_STS0_3 0x5C8158 + +#define mmDMA6_QM_CQ_STS0_4 0x5C815C + +#define mmDMA6_QM_CQ_STS1_0 0x5C8160 + +#define mmDMA6_QM_CQ_STS1_1 0x5C8164 + +#define mmDMA6_QM_CQ_STS1_2 0x5C8168 + +#define mmDMA6_QM_CQ_STS1_3 0x5C816C + +#define mmDMA6_QM_CQ_STS1_4 0x5C8170 + +#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174 + +#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178 + +#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C + +#define mmDMA6_QM_CQ_CTL_0 0x5C8180 + +#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184 + +#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188 + +#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C + +#define mmDMA6_QM_CQ_CTL_1 0x5C8190 + +#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194 + +#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198 + +#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C + +#define mmDMA6_QM_CQ_CTL_2 0x5C81A0 + +#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4 + +#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8 + +#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC + +#define mmDMA6_QM_CQ_CTL_3 0x5C81B0 + +#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4 + +#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8 + +#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC + +#define mmDMA6_QM_CQ_CTL_4 0x5C81C0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4 + +#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8 + +#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC + +#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8 + +#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC + +#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0 + +#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8 + +#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC + +#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0 + +#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4 + +#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8 + +#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC + +#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200 + +#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204 + +#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208 + +#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C + +#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210 + +#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214 + +#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218 + +#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C + +#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220 + +#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304 + +#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308 + +#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C + +#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310 + +#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314 + +#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318 + +#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C + +#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320 + +#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324 + +#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328 + +#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C + +#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330 + +#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334 + +#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338 + +#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C + +#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340 + +#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344 + +#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348 + +#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C + +#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350 + +#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354 + +#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358 + +#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C + +#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360 + +#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364 + +#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368 + +#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C + +#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370 + +#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374 + +#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378 + +#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C + +#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380 + +#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384 + +#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388 + +#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C + +#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390 + +#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394 + +#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398 + +#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C + +#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0 + +#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4 + +#define mmDMA6_QM_CP_STS_0 0x5C83A8 + +#define mmDMA6_QM_CP_STS_1 0x5C83AC + +#define mmDMA6_QM_CP_STS_2 0x5C83B0 + +#define mmDMA6_QM_CP_STS_3 0x5C83B4 + +#define mmDMA6_QM_CP_STS_4 0x5C83B8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC + +#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0 + +#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4 + +#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8 + +#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC + +#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400 + +#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404 + +#define mmDMA6_QM_CP_DBG_0_0 0x5C8408 + +#define mmDMA6_QM_CP_DBG_0_1 0x5C840C + +#define mmDMA6_QM_CP_DBG_0_2 0x5C8410 + +#define mmDMA6_QM_CP_DBG_0_3 0x5C8414 + +#define mmDMA6_QM_CP_DBG_0_4 0x5C8418 + +#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C + +#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420 + +#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424 + +#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428 + +#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C + +#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430 + +#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434 + +#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438 + +#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C + +#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440 + +#define mmDMA6_QM_ARB_CFG_0 0x5C8A00 + +#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C + +#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14 + +#define mmDMA6_QM_ARB_CFG_1 0x5C8A18 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C + +#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20 + +#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28 + +#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C + +#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34 + +#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38 + +#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C + +#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44 + +#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48 + +#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C + +#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50 + +#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54 + +#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58 + +#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80 + +#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84 + +#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88 + +#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C + +#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C + +#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0 + +#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC + +#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC + +#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC + +#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC + +#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC + +#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00 + +#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04 + +#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08 + +#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C + +#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10 + +#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14 + +#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18 + +#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C + +#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20 + +#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24 + +#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28 + +#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C + +#define mmDMA6_QM_CGM_CFG 0x5C8C70 + +#define mmDMA6_QM_CGM_STS 0x5C8C74 + +#define mmDMA6_QM_CGM_CFG1 0x5C8C78 + +#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80 + +#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84 + +#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90 + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0 + +#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4 + +#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0 + +#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4 + +#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8 + +#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC + +#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0 + +#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4 + +#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8 + +#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00 + +#endif /* ASIC_REG_DMA6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h new file mode 100644 index 000000000..8dd705d20 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_CORE_REGS_H_ +#define ASIC_REG_DMA7_CORE_REGS_H_ + +/* + ***************************************** + * DMA7_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA7_CORE_CFG_0 0x5E0000 + +#define mmDMA7_CORE_CFG_1 0x5E0004 + +#define mmDMA7_CORE_LBW_MAX_OUTSTAND 0x5E0008 + +#define mmDMA7_CORE_SRC_BASE_LO 0x5E0014 + +#define mmDMA7_CORE_SRC_BASE_HI 0x5E0018 + +#define mmDMA7_CORE_DST_BASE_LO 0x5E001C + +#define mmDMA7_CORE_DST_BASE_HI 0x5E0020 + +#define mmDMA7_CORE_SRC_TSIZE_1 0x5E002C + +#define mmDMA7_CORE_SRC_STRIDE_1 0x5E0030 + +#define mmDMA7_CORE_SRC_TSIZE_2 0x5E0034 + +#define mmDMA7_CORE_SRC_STRIDE_2 0x5E0038 + +#define mmDMA7_CORE_SRC_TSIZE_3 0x5E003C + +#define mmDMA7_CORE_SRC_STRIDE_3 0x5E0040 + +#define mmDMA7_CORE_SRC_TSIZE_4 0x5E0044 + +#define mmDMA7_CORE_SRC_STRIDE_4 0x5E0048 + +#define mmDMA7_CORE_SRC_TSIZE_0 0x5E004C + +#define mmDMA7_CORE_DST_TSIZE_1 0x5E0054 + +#define mmDMA7_CORE_DST_STRIDE_1 0x5E0058 + +#define mmDMA7_CORE_DST_TSIZE_2 0x5E005C + +#define mmDMA7_CORE_DST_STRIDE_2 0x5E0060 + +#define mmDMA7_CORE_DST_TSIZE_3 0x5E0064 + +#define mmDMA7_CORE_DST_STRIDE_3 0x5E0068 + +#define mmDMA7_CORE_DST_TSIZE_4 0x5E006C + +#define mmDMA7_CORE_DST_STRIDE_4 0x5E0070 + +#define mmDMA7_CORE_DST_TSIZE_0 0x5E0074 + +#define mmDMA7_CORE_COMMIT 0x5E0078 + +#define mmDMA7_CORE_WR_COMP_WDATA 0x5E007C + +#define mmDMA7_CORE_WR_COMP_ADDR_LO 0x5E0080 + +#define mmDMA7_CORE_WR_COMP_ADDR_HI 0x5E0084 + +#define mmDMA7_CORE_WR_COMP_AWUSER_31_11 0x5E0088 + +#define mmDMA7_CORE_TE_NUMROWS 0x5E0094 + +#define mmDMA7_CORE_PROT 0x5E00B8 + +#define mmDMA7_CORE_SECURE_PROPS 0x5E00F0 + +#define mmDMA7_CORE_NON_SECURE_PROPS 0x5E00F4 + +#define mmDMA7_CORE_RD_MAX_OUTSTAND 0x5E0100 + +#define mmDMA7_CORE_RD_MAX_SIZE 0x5E0104 + +#define mmDMA7_CORE_RD_ARCACHE 0x5E0108 + +#define mmDMA7_CORE_RD_ARUSER_31_11 0x5E0110 + +#define mmDMA7_CORE_RD_INFLIGHTS 0x5E0114 + +#define mmDMA7_CORE_WR_MAX_OUTSTAND 0x5E0120 + +#define mmDMA7_CORE_WR_MAX_AWID 0x5E0124 + +#define mmDMA7_CORE_WR_AWCACHE 0x5E0128 + +#define mmDMA7_CORE_WR_AWUSER_31_11 0x5E0130 + +#define mmDMA7_CORE_WR_INFLIGHTS 0x5E0134 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_0 0x5E0150 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_1 0x5E0154 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_0 0x5E0158 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_1 0x5E015C + +#define mmDMA7_CORE_ERR_CFG 0x5E0160 + +#define mmDMA7_CORE_ERR_CAUSE 0x5E0164 + +#define mmDMA7_CORE_ERRMSG_ADDR_LO 0x5E0170 + +#define mmDMA7_CORE_ERRMSG_ADDR_HI 0x5E0174 + +#define mmDMA7_CORE_ERRMSG_WDATA 0x5E0178 + +#define mmDMA7_CORE_STS0 0x5E0190 + +#define mmDMA7_CORE_STS1 0x5E0194 + +#define mmDMA7_CORE_RD_DBGMEM_ADD 0x5E0200 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_WR 0x5E0204 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_RD 0x5E0208 + +#define mmDMA7_CORE_RD_DBGMEM_CTRL 0x5E020C + +#define mmDMA7_CORE_RD_DBGMEM_RC 0x5E0210 + +#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT 0x5E0220 + +#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT 0x5E0224 + +#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT 0x5E0228 + +#define mmDMA7_CORE_DBG_DESC_CNT 0x5E022C + +#define mmDMA7_CORE_DBG_STS 0x5E0230 + +#define mmDMA7_CORE_DBG_RD_DESC_ID 0x5E0234 + +#define mmDMA7_CORE_DBG_WR_DESC_ID 0x5E0238 + +#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h new file mode 100644 index 000000000..d6c631f63 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_QM_REGS_H_ +#define ASIC_REG_DMA7_QM_REGS_H_ + +/* + ***************************************** + * DMA7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA7_QM_GLBL_CFG0 0x5E8000 + +#define mmDMA7_QM_GLBL_CFG1 0x5E8004 + +#define mmDMA7_QM_GLBL_PROT 0x5E8008 + +#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034 + +#define mmDMA7_QM_GLBL_STS0 0x5E8038 + +#define mmDMA7_QM_GLBL_STS1_0 0x5E8040 + +#define mmDMA7_QM_GLBL_STS1_1 0x5E8044 + +#define mmDMA7_QM_GLBL_STS1_2 0x5E8048 + +#define mmDMA7_QM_GLBL_STS1_3 0x5E804C + +#define mmDMA7_QM_GLBL_STS1_4 0x5E8050 + +#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054 + +#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058 + +#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C + +#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060 + +#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068 + +#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070 + +#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074 + +#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078 + +#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C + +#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080 + +#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084 + +#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088 + +#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C + +#define mmDMA7_QM_PQ_SIZE_0 0x5E8090 + +#define mmDMA7_QM_PQ_SIZE_1 0x5E8094 + +#define mmDMA7_QM_PQ_SIZE_2 0x5E8098 + +#define mmDMA7_QM_PQ_SIZE_3 0x5E809C + +#define mmDMA7_QM_PQ_PI_0 0x5E80A0 + +#define mmDMA7_QM_PQ_PI_1 0x5E80A4 + +#define mmDMA7_QM_PQ_PI_2 0x5E80A8 + +#define mmDMA7_QM_PQ_PI_3 0x5E80AC + +#define mmDMA7_QM_PQ_CI_0 0x5E80B0 + +#define mmDMA7_QM_PQ_CI_1 0x5E80B4 + +#define mmDMA7_QM_PQ_CI_2 0x5E80B8 + +#define mmDMA7_QM_PQ_CI_3 0x5E80BC + +#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0 + +#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4 + +#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8 + +#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC + +#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0 + +#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4 + +#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8 + +#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC + +#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0 + +#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4 + +#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8 + +#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC + +#define mmDMA7_QM_PQ_STS0_0 0x5E80F0 + +#define mmDMA7_QM_PQ_STS0_1 0x5E80F4 + +#define mmDMA7_QM_PQ_STS0_2 0x5E80F8 + +#define mmDMA7_QM_PQ_STS0_3 0x5E80FC + +#define mmDMA7_QM_PQ_STS1_0 0x5E8100 + +#define mmDMA7_QM_PQ_STS1_1 0x5E8104 + +#define mmDMA7_QM_PQ_STS1_2 0x5E8108 + +#define mmDMA7_QM_PQ_STS1_3 0x5E810C + +#define mmDMA7_QM_CQ_CFG0_0 0x5E8110 + +#define mmDMA7_QM_CQ_CFG0_1 0x5E8114 + +#define mmDMA7_QM_CQ_CFG0_2 0x5E8118 + +#define mmDMA7_QM_CQ_CFG0_3 0x5E811C + +#define mmDMA7_QM_CQ_CFG0_4 0x5E8120 + +#define mmDMA7_QM_CQ_CFG1_0 0x5E8124 + +#define mmDMA7_QM_CQ_CFG1_1 0x5E8128 + +#define mmDMA7_QM_CQ_CFG1_2 0x5E812C + +#define mmDMA7_QM_CQ_CFG1_3 0x5E8130 + +#define mmDMA7_QM_CQ_CFG1_4 0x5E8134 + +#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138 + +#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C + +#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140 + +#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144 + +#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148 + +#define mmDMA7_QM_CQ_STS0_0 0x5E814C + +#define mmDMA7_QM_CQ_STS0_1 0x5E8150 + +#define mmDMA7_QM_CQ_STS0_2 0x5E8154 + +#define mmDMA7_QM_CQ_STS0_3 0x5E8158 + +#define mmDMA7_QM_CQ_STS0_4 0x5E815C + +#define mmDMA7_QM_CQ_STS1_0 0x5E8160 + +#define mmDMA7_QM_CQ_STS1_1 0x5E8164 + +#define mmDMA7_QM_CQ_STS1_2 0x5E8168 + +#define mmDMA7_QM_CQ_STS1_3 0x5E816C + +#define mmDMA7_QM_CQ_STS1_4 0x5E8170 + +#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174 + +#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178 + +#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C + +#define mmDMA7_QM_CQ_CTL_0 0x5E8180 + +#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184 + +#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188 + +#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C + +#define mmDMA7_QM_CQ_CTL_1 0x5E8190 + +#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194 + +#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198 + +#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C + +#define mmDMA7_QM_CQ_CTL_2 0x5E81A0 + +#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4 + +#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8 + +#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC + +#define mmDMA7_QM_CQ_CTL_3 0x5E81B0 + +#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4 + +#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8 + +#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC + +#define mmDMA7_QM_CQ_CTL_4 0x5E81C0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4 + +#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8 + +#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC + +#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8 + +#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC + +#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0 + +#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8 + +#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC + +#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0 + +#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4 + +#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8 + +#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC + +#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200 + +#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204 + +#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208 + +#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C + +#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210 + +#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214 + +#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218 + +#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C + +#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220 + +#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304 + +#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308 + +#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C + +#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310 + +#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314 + +#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318 + +#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C + +#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320 + +#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324 + +#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328 + +#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C + +#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330 + +#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334 + +#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338 + +#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C + +#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340 + +#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344 + +#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348 + +#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C + +#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350 + +#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354 + +#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358 + +#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C + +#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360 + +#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364 + +#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368 + +#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C + +#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370 + +#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374 + +#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378 + +#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C + +#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380 + +#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384 + +#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388 + +#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C + +#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390 + +#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394 + +#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398 + +#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C + +#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0 + +#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4 + +#define mmDMA7_QM_CP_STS_0 0x5E83A8 + +#define mmDMA7_QM_CP_STS_1 0x5E83AC + +#define mmDMA7_QM_CP_STS_2 0x5E83B0 + +#define mmDMA7_QM_CP_STS_3 0x5E83B4 + +#define mmDMA7_QM_CP_STS_4 0x5E83B8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC + +#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0 + +#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4 + +#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8 + +#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC + +#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400 + +#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404 + +#define mmDMA7_QM_CP_DBG_0_0 0x5E8408 + +#define mmDMA7_QM_CP_DBG_0_1 0x5E840C + +#define mmDMA7_QM_CP_DBG_0_2 0x5E8410 + +#define mmDMA7_QM_CP_DBG_0_3 0x5E8414 + +#define mmDMA7_QM_CP_DBG_0_4 0x5E8418 + +#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C + +#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420 + +#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424 + +#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428 + +#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C + +#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430 + +#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434 + +#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438 + +#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C + +#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440 + +#define mmDMA7_QM_ARB_CFG_0 0x5E8A00 + +#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C + +#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14 + +#define mmDMA7_QM_ARB_CFG_1 0x5E8A18 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C + +#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20 + +#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28 + +#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C + +#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34 + +#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38 + +#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C + +#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44 + +#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48 + +#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C + +#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50 + +#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54 + +#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58 + +#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80 + +#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84 + +#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88 + +#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C + +#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C + +#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0 + +#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC + +#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC + +#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC + +#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC + +#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC + +#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00 + +#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04 + +#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08 + +#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C + +#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10 + +#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14 + +#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18 + +#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C + +#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20 + +#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24 + +#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28 + +#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C + +#define mmDMA7_QM_CGM_CFG 0x5E8C70 + +#define mmDMA7_QM_CGM_STS 0x5E8C74 + +#define mmDMA7_QM_CGM_CFG1 0x5E8C78 + +#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80 + +#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84 + +#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90 + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0 + +#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4 + +#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0 + +#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4 + +#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8 + +#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC + +#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0 + +#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4 + +#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8 + +#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00 + +#endif /* ASIC_REG_DMA7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h new file mode 100644 index 000000000..8c1c72df4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH0_PERM_SEL 0x4E1108 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_0 0x4E1114 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_1 0x4E1118 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_2 0x4E111C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_3 0x4E1120 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_4 0x4E1124 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_5 0x4E1128 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_6 0x4E112C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_7 0x4E1130 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_8 0x4E1134 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_9 0x4E1138 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_10 0x4E113C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_11 0x4E1140 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_12 0x4E1144 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_13 0x4E1148 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_14 0x4E114C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_15 0x4E1150 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_16 0x4E1154 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_17 0x4E1158 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_18 0x4E115C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_19 0x4E1160 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_20 0x4E1164 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_21 0x4E1168 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_22 0x4E116C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_23 0x4E1170 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_24 0x4E1174 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_25 0x4E1178 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_26 0x4E117C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_27 0x4E1180 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_0 0x4E1184 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_1 0x4E1188 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_2 0x4E118C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_3 0x4E1190 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_4 0x4E1194 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_5 0x4E1198 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_6 0x4E119C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_7 0x4E11A0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_8 0x4E11A4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_9 0x4E11A8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_10 0x4E11AC + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_11 0x4E11B0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_12 0x4E11B4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_13 0x4E11B8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_14 0x4E11BC + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN 0x4E126C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN 0x4E1274 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT 0x4E1278 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST 0x4E127C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4E1280 + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN 0x4E1284 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_EN 0x4E1288 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_SAT 0x4E128C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_RST 0x4E1290 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4E1294 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN 0x4E129C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT 0x4E12A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST 0x4E12A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4E12AC + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RED 0x4E12B4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN 0x4E12EC + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN 0x4E12F0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4E12F4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4E12F8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4E1404 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4E1408 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4E140C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4E1410 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4E1414 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4E1418 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4E141C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4E1420 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4E1424 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4E1428 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4E142C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4E1430 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4E1434 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4E1438 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0 0x4E1450 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1 0x4E1454 + +#define mmDMA_IF_E_N_DOWN_CH0_NON_LIN_EN 0x4E1480 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_0 0x4E1500 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_1 0x4E1504 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_2 0x4E1508 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_3 0x4E150C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_4 0x4E1510 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4E1514 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4E1520 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4E1524 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4E1528 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4E152C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4E1530 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4E1534 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4E1538 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4E153C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4E1540 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4E1550 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4E1554 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4E1558 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4E155C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4E1560 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4E1564 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4E1568 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4E156C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4E1570 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4E1574 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4E1578 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4E157C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4E1580 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4E1584 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4E1588 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4E158C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4E1590 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4E1594 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4E1598 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4E15E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4E15E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4E15EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4E15F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4E15F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4E15F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4E15FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4E1600 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4E1604 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4E1608 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4E160C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4E1610 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4E1614 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4E1618 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4E161C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4E1620 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4E1624 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4E1628 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4E162C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4E1630 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4E1634 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4E1638 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4E163C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4E1640 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4E1644 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4E1648 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4E164C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4E1650 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4E1654 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4E1658 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4E165C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4E1660 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4E1664 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4E1668 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4E166C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4E1670 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4E1674 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4E1678 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4E167C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4E1680 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4E1684 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4E1688 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4E168C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4E1690 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4E1694 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4E1698 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4E169C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4E16A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4E16A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4E16A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4E16AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4E16B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4E16B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4E16B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4E16BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4E16C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4E16C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4E16C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4E16CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4E16D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4E16D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4E16D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4E16DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4E16E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4E16E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4E16E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4E16EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4E16F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4E16F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4E16F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4E16FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4E1700 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4E1704 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4E1708 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4E170C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4E1710 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4E1714 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4E1718 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4E171C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4E1720 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4E1724 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4E1728 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4E172C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4E1730 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4E1734 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4E1738 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4E173C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4E1740 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4E1744 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4E1748 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4E174C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4E1750 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4E1754 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4E1758 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4E175C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4E1760 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4E1764 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4E1768 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4E176C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4E1770 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4E1774 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4E1778 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4E177C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4E1780 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4E1784 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4E1788 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4E178C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4E1790 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4E1794 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4E1798 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4E179C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4E17A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4E17A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4E17A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4E17AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4E17B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4E17B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4E17B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4E17BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4E17C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4E17C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4E17C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4E17CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4E17D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4E17D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4E17D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4E17DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4E17E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4E1824 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4E1828 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4E182C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4E1830 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4E1834 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4E1838 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4E183C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4E1840 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4E1844 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4E1848 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4E184C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4E1850 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4E1854 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4E1858 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4E185C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4E1860 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4E1864 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4E1868 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4E186C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4E1870 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4E1874 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4E1878 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4E187C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4E1880 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4E1884 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4E1888 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4E188C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4E1890 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4E1894 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4E1898 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4E189C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4E18A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4E18A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4E18A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4E18AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4E18B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4E18B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4E18B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4E18BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4E18C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4E18C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4E18C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4E18CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4E18D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4E18D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4E18D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4E18DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4E18E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4E18E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4E18E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4E18EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4E18F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4E18F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4E18F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4E18FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4E1900 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4E1904 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4E1908 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4E190C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4E1910 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4E1914 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4E1918 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4E191C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4E1920 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4E1924 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4E1928 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4E192C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4E1930 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4E1934 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4E1938 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4E193C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4E1940 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4E1944 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4E1948 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4E194C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4E1950 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4E1954 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4E1958 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4E195C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4E1960 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4E1964 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4E1968 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4E196C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4E1970 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4E1974 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4E1978 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4E197C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4E1980 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4E1984 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4E1988 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4E198C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4E1990 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4E1994 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4E1998 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4E199C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4E19A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4E19A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4E19A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4E19AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4E19B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4E19B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4E19B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4E19BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4E19C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4E19C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4E19C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4E19CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4E19D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4E19D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4E19D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4E19DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4E19E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4E19E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4E19E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4E19EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4E19F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4E19F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4E19F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4E19FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4E1A00 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4E1A04 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4E1A08 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4E1A0C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4E1A10 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4E1A14 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4E1A18 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4E1A1C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4E1A20 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4E1A64 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4E1A68 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4E1A6C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4E1A70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_CFG 0x4E1B64 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_SHIFT 0x4E1B68 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4E1B6C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4E1B70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4E1B74 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4E1B78 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4E1B7C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4E1B80 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4E1B84 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4E1B88 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_0 0x4E1BAC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_1 0x4E1BB0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_2 0x4E1BB4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_3 0x4E1BB8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_4 0x4E1BBC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_5 0x4E1BC0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_6 0x4E1BC4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_7 0x4E1BC8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_0 0x4E1BEC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_1 0x4E1BF0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_2 0x4E1BF4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_3 0x4E1BF8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_4 0x4E1BFC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_5 0x4E1C00 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_6 0x4E1C04 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_7 0x4E1C08 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_WDT 0x4E1C2C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E1C30 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E1C34 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E1C38 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E1C3C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E1C40 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E1C44 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E1C48 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E1C4C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4E1C50 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4E1C54 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4E1C58 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4E1C5C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4E1C60 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4E1C64 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4E1C68 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4E1C6C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E1C70 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E1C74 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E1C78 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E1C7C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E1C80 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E1C84 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E1C88 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E1C8C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4E1C90 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4E1C94 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4E1C98 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4E1C9C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4E1CA0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4E1CA4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4E1CA8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4E1CAC + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4E1CB0 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4E1CB4 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4E1CB8 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4E1CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h new file mode 100644 index 000000000..b2b593fce --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL 0x4E2108 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0 0x4E2114 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1 0x4E2118 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2 0x4E211C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3 0x4E2120 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4 0x4E2124 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5 0x4E2128 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6 0x4E212C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7 0x4E2130 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8 0x4E2134 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9 0x4E2138 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10 0x4E213C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11 0x4E2140 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12 0x4E2144 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13 0x4E2148 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14 0x4E214C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15 0x4E2150 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16 0x4E2154 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17 0x4E2158 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18 0x4E215C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19 0x4E2160 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20 0x4E2164 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21 0x4E2168 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22 0x4E216C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23 0x4E2170 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24 0x4E2174 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25 0x4E2178 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26 0x4E217C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27 0x4E2180 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0 0x4E2184 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1 0x4E2188 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2 0x4E218C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3 0x4E2190 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4 0x4E2194 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5 0x4E2198 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6 0x4E219C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7 0x4E21A0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8 0x4E21A4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9 0x4E21A8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10 0x4E21AC + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11 0x4E21B0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12 0x4E21B4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13 0x4E21B8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14 0x4E21BC + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN 0x4E226C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN 0x4E2274 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT 0x4E2278 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST 0x4E227C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4E2280 + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN 0x4E2284 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN 0x4E2288 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT 0x4E228C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST 0x4E2290 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4E2294 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN 0x4E229C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT 0x4E22A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST 0x4E22A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4E22AC + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED 0x4E22B4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN 0x4E22EC + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN 0x4E22F0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4E22F4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4E22F8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4E2404 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4E2408 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4E240C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4E2410 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4E2414 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4E2418 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4E241C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4E2420 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4E2424 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4E2428 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4E242C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4E2430 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4E2434 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4E2438 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0 0x4E2450 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1 0x4E2454 + +#define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN 0x4E2480 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0 0x4E2500 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1 0x4E2504 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2 0x4E2508 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3 0x4E250C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4 0x4E2510 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4E2514 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4E2520 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4E2524 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4E2528 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4E252C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4E2530 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4E2534 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4E2538 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4E253C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4E2540 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4E2550 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4E2554 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4E2558 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4E255C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4E2560 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4E2564 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4E2568 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4E256C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4E2570 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4E2574 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4E2578 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4E257C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4E2580 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4E2584 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4E2588 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4E258C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4E2590 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4E2594 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4E2598 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4E25E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4E25E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4E25EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4E25F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4E25F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4E25F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4E25FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4E2600 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4E2604 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4E2608 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4E260C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4E2610 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4E2614 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4E2618 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4E261C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4E2620 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4E2624 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4E2628 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4E262C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4E2630 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4E2634 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4E2638 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4E263C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4E2640 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4E2644 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4E2648 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4E264C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4E2650 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4E2654 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4E2658 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4E265C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4E2660 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4E2664 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4E2668 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4E266C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4E2670 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4E2674 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4E2678 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4E267C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4E2680 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4E2684 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4E2688 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4E268C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4E2690 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4E2694 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4E2698 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4E269C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4E26A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4E26A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4E26A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4E26AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4E26B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4E26B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4E26B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4E26BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4E26C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4E26C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4E26C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4E26CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4E26D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4E26D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4E26D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4E26DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4E26E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4E26E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4E26E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4E26EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4E26F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4E26F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4E26F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4E26FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4E2700 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4E2704 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4E2708 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4E270C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4E2710 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4E2714 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4E2718 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4E271C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4E2720 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4E2724 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4E2728 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4E272C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4E2730 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4E2734 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4E2738 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4E273C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4E2740 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4E2744 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4E2748 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4E274C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4E2750 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4E2754 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4E2758 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4E275C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4E2760 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4E2764 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4E2768 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4E276C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4E2770 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4E2774 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4E2778 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4E277C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4E2780 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4E2784 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4E2788 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4E278C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4E2790 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4E2794 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4E2798 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4E279C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4E27A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4E27A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4E27A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4E27AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4E27B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4E27B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4E27B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4E27BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4E27C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4E27C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4E27C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4E27CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4E27D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4E27D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4E27D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4E27DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4E27E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4E2824 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4E2828 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4E282C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4E2830 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4E2834 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4E2838 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4E283C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4E2840 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4E2844 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4E2848 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4E284C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4E2850 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4E2854 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4E2858 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4E285C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4E2860 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4E2864 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4E2868 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4E286C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4E2870 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4E2874 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4E2878 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4E287C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4E2880 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4E2884 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4E2888 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4E288C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4E2890 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4E2894 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4E2898 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4E289C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4E28A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4E28A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4E28A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4E28AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4E28B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4E28B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4E28B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4E28BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4E28C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4E28C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4E28C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4E28CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4E28D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4E28D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4E28D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4E28DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4E28E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4E28E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4E28E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4E28EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4E28F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4E28F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4E28F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4E28FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4E2900 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4E2904 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4E2908 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4E290C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4E2910 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4E2914 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4E2918 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4E291C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4E2920 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4E2924 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4E2928 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4E292C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4E2930 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4E2934 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4E2938 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4E293C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4E2940 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4E2944 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4E2948 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4E294C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4E2950 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4E2954 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4E2958 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4E295C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4E2960 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4E2964 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4E2968 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4E296C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4E2970 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4E2974 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4E2978 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4E297C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4E2980 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4E2984 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4E2988 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4E298C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4E2990 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4E2994 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4E2998 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4E299C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4E29A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4E29A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4E29A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4E29AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4E29B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4E29B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4E29B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4E29BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4E29C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4E29C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4E29C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4E29CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4E29D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4E29D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4E29D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4E29DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4E29E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4E29E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4E29E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4E29EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4E29F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4E29F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4E29F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4E29FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4E2A00 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4E2A04 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4E2A08 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4E2A0C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4E2A10 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4E2A14 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4E2A18 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4E2A1C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4E2A20 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4E2A64 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4E2A68 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4E2A6C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4E2A70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG 0x4E2B64 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT 0x4E2B68 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4E2B6C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4E2B70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4E2B74 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4E2B78 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4E2B7C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4E2B80 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4E2B84 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4E2B88 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0 0x4E2BAC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1 0x4E2BB0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2 0x4E2BB4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3 0x4E2BB8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4 0x4E2BBC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5 0x4E2BC0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6 0x4E2BC4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7 0x4E2BC8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0 0x4E2BEC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1 0x4E2BF0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2 0x4E2BF4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3 0x4E2BF8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4 0x4E2BFC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5 0x4E2C00 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6 0x4E2C04 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7 0x4E2C08 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT 0x4E2C2C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E2C30 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E2C34 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E2C38 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E2C3C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E2C40 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E2C44 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E2C48 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E2C4C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4E2C50 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4E2C54 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4E2C58 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4E2C5C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4E2C60 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4E2C64 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4E2C68 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4E2C6C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E2C70 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E2C74 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E2C78 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E2C7C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E2C80 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E2C84 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E2C88 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E2C8C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4E2C90 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4E2C94 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4E2C98 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4E2C9C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4E2CA0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4E2CA4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4E2CA8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4E2CAC + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4E2CB0 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4E2CB4 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4E2CB8 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4E2CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h new file mode 100644 index 000000000..8a10c6a76 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_N_HBM0_WR_CRED_CNT 0x4E0000 + +#define mmDMA_IF_E_N_HBM1_WR_CRED_CNT 0x4E0004 + +#define mmDMA_IF_E_N_HBM0_RD_CRED_CNT 0x4E0008 + +#define mmDMA_IF_E_N_HBM1_RD_CRED_CNT 0x4E000C + +#define mmDMA_IF_E_N_HBM_LIMITER_0 0x4E0030 + +#define mmDMA_IF_E_N_HBM_LIMITER_1 0x4E0034 + +#define mmDMA_IF_E_N_HBM_LIMITER_2 0x4E0038 + +#define mmDMA_IF_E_N_HBM_LIMITER_3 0x4E003C + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_0 0x4E0040 + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_1 0x4E0044 + +#define mmDMA_IF_E_N_HBM_CRED_EN_0 0x4E0050 + +#define mmDMA_IF_E_N_HBM_CRED_EN_1 0x4E0054 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_0 0x4E0100 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_1 0x4E0104 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_2 0x4E0108 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_3 0x4E010C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_4 0x4E0110 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_5 0x4E0114 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_6 0x4E0118 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_7 0x4E011C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_8 0x4E0120 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_9 0x4E0124 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_10 0x4E0128 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_11 0x4E012C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_12 0x4E0130 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_13 0x4E0134 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_14 0x4E0138 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_15 0x4E013C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_0 0x4E0140 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_1 0x4E0144 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_2 0x4E0148 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_3 0x4E014C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_4 0x4E0150 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_5 0x4E0154 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_6 0x4E0158 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_7 0x4E015C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_8 0x4E0160 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_9 0x4E0164 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_10 0x4E0168 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_11 0x4E016C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_12 0x4E0170 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_13 0x4E0174 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_14 0x4E0178 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_15 0x4E017C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_0 0x4E0180 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_1 0x4E0184 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_2 0x4E0188 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_3 0x4E018C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_4 0x4E0190 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_5 0x4E0194 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_6 0x4E0198 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_7 0x4E019C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_8 0x4E01A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_9 0x4E01A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_10 0x4E01A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_11 0x4E01AC + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_12 0x4E01B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_13 0x4E01B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_14 0x4E01B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_15 0x4E01BC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_0 0x4E01C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_1 0x4E01C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_2 0x4E01C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_3 0x4E01CC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_4 0x4E01D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_5 0x4E01D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_6 0x4E01D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_7 0x4E01DC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_8 0x4E01E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_9 0x4E01E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_10 0x4E01E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_11 0x4E01EC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_12 0x4E01F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_13 0x4E01F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_14 0x4E01F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_15 0x4E01FC + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_0 0x4E0200 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_1 0x4E0204 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_2 0x4E0208 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_3 0x4E020C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_4 0x4E0210 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_5 0x4E0214 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_6 0x4E0218 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_7 0x4E021C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_8 0x4E0220 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_9 0x4E0224 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_10 0x4E0228 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_11 0x4E022C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_12 0x4E0230 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_13 0x4E0234 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_14 0x4E0238 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_15 0x4E023C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_0 0x4E0240 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_1 0x4E0244 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_2 0x4E0248 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_3 0x4E024C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_4 0x4E0250 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_5 0x4E0254 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_6 0x4E0258 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_7 0x4E025C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_8 0x4E0260 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_9 0x4E0264 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_10 0x4E0268 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_11 0x4E026C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_12 0x4E0270 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_13 0x4E0274 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_14 0x4E0278 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_15 0x4E027C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_0 0x4E0280 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_1 0x4E0284 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_2 0x4E0288 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_3 0x4E028C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_4 0x4E0290 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_5 0x4E0294 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_6 0x4E0298 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_7 0x4E029C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_8 0x4E02A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_9 0x4E02A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_10 0x4E02A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_11 0x4E02AC + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_12 0x4E02B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_13 0x4E02B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_14 0x4E02B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_15 0x4E02BC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_0 0x4E02C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_1 0x4E02C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_2 0x4E02C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_3 0x4E02CC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_4 0x4E02D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_5 0x4E02D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_6 0x4E02D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_7 0x4E02DC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_8 0x4E02E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_9 0x4E02E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_10 0x4E02E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_11 0x4E02EC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_12 0x4E02F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_13 0x4E02F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_14 0x4E02F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_15 0x4E02FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_0 0x4E0300 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_1 0x4E0304 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_2 0x4E0308 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_3 0x4E030C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_4 0x4E0310 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_5 0x4E0314 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_6 0x4E0318 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_7 0x4E031C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_8 0x4E0320 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_9 0x4E0324 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_10 0x4E0328 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_11 0x4E032C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_12 0x4E0330 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_13 0x4E0334 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_14 0x4E0338 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_15 0x4E033C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_0 0x4E0340 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_1 0x4E0344 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_2 0x4E0348 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_3 0x4E034C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_4 0x4E0350 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_5 0x4E0354 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_6 0x4E0358 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_7 0x4E035C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_8 0x4E0360 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_9 0x4E0364 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_10 0x4E0368 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_11 0x4E036C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_12 0x4E0370 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_13 0x4E0374 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_14 0x4E0378 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_15 0x4E037C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_0 0x4E0380 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_1 0x4E0384 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_2 0x4E0388 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_3 0x4E038C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_4 0x4E0390 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_5 0x4E0394 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_6 0x4E0398 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_7 0x4E039C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_8 0x4E03A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_9 0x4E03A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_10 0x4E03A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_11 0x4E03AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_12 0x4E03B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_13 0x4E03B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_14 0x4E03B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_15 0x4E03BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_0 0x4E03C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_1 0x4E03C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_2 0x4E03C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_3 0x4E03CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_4 0x4E03D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_5 0x4E03D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_6 0x4E03D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_7 0x4E03DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_8 0x4E03E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_9 0x4E03E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_10 0x4E03E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_11 0x4E03EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_12 0x4E03F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_13 0x4E03F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_14 0x4E03F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_15 0x4E03FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_0 0x4E0400 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_1 0x4E0404 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_2 0x4E0408 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_3 0x4E040C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_4 0x4E0410 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_5 0x4E0414 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_6 0x4E0418 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_7 0x4E041C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_8 0x4E0420 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_9 0x4E0424 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_10 0x4E0428 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_11 0x4E042C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_12 0x4E0430 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_13 0x4E0434 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_14 0x4E0438 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_15 0x4E043C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_0 0x4E0440 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_1 0x4E0444 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_2 0x4E0448 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_3 0x4E044C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_4 0x4E0450 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_5 0x4E0454 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_6 0x4E0458 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_7 0x4E045C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_8 0x4E0460 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_9 0x4E0464 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_10 0x4E0468 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_11 0x4E046C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_12 0x4E0470 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_13 0x4E0474 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_14 0x4E0478 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_15 0x4E047C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_0 0x4E0480 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_1 0x4E0484 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_2 0x4E0488 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_3 0x4E048C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_4 0x4E0490 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_5 0x4E0494 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_6 0x4E0498 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_7 0x4E049C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_8 0x4E04A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_9 0x4E04A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_10 0x4E04A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_11 0x4E04AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_12 0x4E04B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_13 0x4E04B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_14 0x4E04B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_15 0x4E04BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_0 0x4E04C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_1 0x4E04C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_2 0x4E04C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_3 0x4E04CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_4 0x4E04D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_5 0x4E04D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_6 0x4E04D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_7 0x4E04DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_8 0x4E04E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_9 0x4E04E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_10 0x4E04E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_11 0x4E04EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_12 0x4E04F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_13 0x4E04F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_14 0x4E04F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_15 0x4E04FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_0 0x4E0500 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_1 0x4E0504 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_2 0x4E0508 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_3 0x4E050C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_4 0x4E0510 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_5 0x4E0514 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_6 0x4E0518 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_7 0x4E051C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_8 0x4E0520 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_9 0x4E0524 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_10 0x4E0528 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_11 0x4E052C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_12 0x4E0530 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_13 0x4E0534 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_14 0x4E0538 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_15 0x4E053C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_0 0x4E0540 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_1 0x4E0544 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_2 0x4E0548 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_3 0x4E054C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_4 0x4E0550 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_5 0x4E0554 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_6 0x4E0558 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_7 0x4E055C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_8 0x4E0560 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_9 0x4E0564 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_10 0x4E0568 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_11 0x4E056C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_12 0x4E0570 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_13 0x4E0574 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_14 0x4E0578 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_15 0x4E057C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_0 0x4E0580 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_1 0x4E0584 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_2 0x4E0588 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_3 0x4E058C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_4 0x4E0590 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_5 0x4E0594 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_6 0x4E0598 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_7 0x4E059C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_8 0x4E05A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_9 0x4E05A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_10 0x4E05A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_11 0x4E05AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_12 0x4E05B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_13 0x4E05B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_14 0x4E05B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_15 0x4E05BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_0 0x4E05C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_1 0x4E05C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_2 0x4E05C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_3 0x4E05CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_4 0x4E05D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_5 0x4E05D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_6 0x4E05D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_7 0x4E05DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_8 0x4E05E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_9 0x4E05E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_10 0x4E05E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_11 0x4E05EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_12 0x4E05F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_13 0x4E05F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_14 0x4E05F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_15 0x4E05FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_0 0x4E0600 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_1 0x4E0604 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_2 0x4E0608 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_3 0x4E060C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_4 0x4E0610 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_5 0x4E0614 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_6 0x4E0618 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_7 0x4E061C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_8 0x4E0620 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_9 0x4E0624 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_10 0x4E0628 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_11 0x4E062C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_12 0x4E0630 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_13 0x4E0634 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_14 0x4E0638 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_15 0x4E063C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_0 0x4E0640 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_1 0x4E0644 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_2 0x4E0648 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_3 0x4E064C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_4 0x4E0650 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_5 0x4E0654 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_6 0x4E0658 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_7 0x4E065C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_8 0x4E0660 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_9 0x4E0664 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_10 0x4E0668 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_11 0x4E066C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_12 0x4E0670 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_13 0x4E0674 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_14 0x4E0678 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_15 0x4E067C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_0 0x4E0680 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_1 0x4E0684 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_2 0x4E0688 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_3 0x4E068C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_4 0x4E0690 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_5 0x4E0694 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_6 0x4E0698 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_7 0x4E069C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_8 0x4E06A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_9 0x4E06A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_10 0x4E06A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_11 0x4E06AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_12 0x4E06B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_13 0x4E06B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_14 0x4E06B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_15 0x4E06BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_0 0x4E06C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_1 0x4E06C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_2 0x4E06C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_3 0x4E06CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_4 0x4E06D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_5 0x4E06D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_6 0x4E06D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_7 0x4E06DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_8 0x4E06E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_9 0x4E06E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_10 0x4E06E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_11 0x4E06EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_12 0x4E06F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_13 0x4E06F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_14 0x4E06F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_15 0x4E06FC + +#define mmDMA_IF_E_N_SOB_HIT_RPROT 0x4E0700 + +#define mmDMA_IF_E_N_SOB_HIT_WPROT 0x4E0704 + +#define mmDMA_IF_E_N_SOB_HIT_RPRIV 0x4E070C + +#define mmDMA_IF_E_N_SOB_HIT_WPRIV 0x4E0710 + +#define mmDMA_IF_E_N_DMA0_HIT_RPROT 0x4E071C + +#define mmDMA_IF_E_N_DMA0_HIT_WPROT 0x4E0720 + +#define mmDMA_IF_E_N_DMA0_HIT_RPRIV 0x4E0724 + +#define mmDMA_IF_E_N_DMA0_HIT_WPRIV 0x4E0728 + +#define mmDMA_IF_E_N_DMA1_HIT_RPROT 0x4E0730 + +#define mmDMA_IF_E_N_DMA1_HIT_WPROT 0x4E0734 + +#define mmDMA_IF_E_N_DMA1_HIT_RPRIV 0x4E0738 + +#define mmDMA_IF_E_N_DMA1_HIT_WPRIV 0x4E073C + +#define mmDMA_IF_E_N_HBM_BIN 0x4E0800 + +#define mmDMA_IF_E_N_MME_BIN 0x4E0804 + +#define mmDMA_IF_E_N_TPC_BIN 0x4E0808 + +#define mmDMA_IF_E_N_DMA_BIN 0x4E080C + +#define mmDMA_IF_E_N_SOB_CG_EN 0x4E0810 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_0 0x4E0820 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_1 0x4E0824 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_2 0x4E0828 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_3 0x4E082C + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_4 0x4E0830 + +#define mmDMA_IF_E_N_HBM_MISC 0x4E0834 + +#endif /* ASIC_REG_DMA_IF_E_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h new file mode 100644 index 000000000..cd61289a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL 0x4A1108 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0 0x4A1114 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1 0x4A1118 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2 0x4A111C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3 0x4A1120 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4 0x4A1124 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5 0x4A1128 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6 0x4A112C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7 0x4A1130 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8 0x4A1134 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9 0x4A1138 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10 0x4A113C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11 0x4A1140 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12 0x4A1144 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13 0x4A1148 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14 0x4A114C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15 0x4A1150 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16 0x4A1154 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17 0x4A1158 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18 0x4A115C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19 0x4A1160 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20 0x4A1164 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21 0x4A1168 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22 0x4A116C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23 0x4A1170 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24 0x4A1174 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25 0x4A1178 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26 0x4A117C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27 0x4A1180 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0 0x4A1184 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1 0x4A1188 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2 0x4A118C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3 0x4A1190 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4 0x4A1194 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5 0x4A1198 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6 0x4A119C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7 0x4A11A0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8 0x4A11A4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9 0x4A11A8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10 0x4A11AC + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11 0x4A11B0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12 0x4A11B4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13 0x4A11B8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14 0x4A11BC + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN 0x4A126C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN 0x4A1274 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT 0x4A1278 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST 0x4A127C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT 0x4A1280 + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN 0x4A1284 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN 0x4A1288 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT 0x4A128C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST 0x4A1290 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT 0x4A1294 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN 0x4A129C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT 0x4A12A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST 0x4A12A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4A12AC + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED 0x4A12B4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN 0x4A12EC + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN 0x4A12F0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4A12F4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4A12F8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4A1404 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4A1408 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4A140C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4A1410 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4A1414 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4A1418 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x4A141C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x4A1420 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4A1424 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4A1428 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4A142C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4A1430 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4A1434 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4A1438 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0 0x4A1450 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1 0x4A1454 + +#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN 0x4A1480 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0 0x4A1500 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1 0x4A1504 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2 0x4A1508 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3 0x4A150C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4 0x4A1510 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x4A1514 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x4A1520 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x4A1524 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x4A1528 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x4A152C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x4A1530 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x4A1534 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x4A1538 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x4A153C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x4A1540 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0 0x4A1550 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1 0x4A1554 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2 0x4A1558 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3 0x4A155C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4 0x4A1560 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5 0x4A1564 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6 0x4A1568 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7 0x4A156C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8 0x4A1570 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9 0x4A1574 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10 0x4A1578 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11 0x4A157C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12 0x4A1580 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13 0x4A1584 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14 0x4A1588 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15 0x4A158C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16 0x4A1590 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17 0x4A1594 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18 0x4A1598 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4A15E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4A15E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4A15EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4A15F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4A15F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4A15F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4A15FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4A1600 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4A1604 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4A1608 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4A160C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4A1610 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4A1614 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4A1618 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4A161C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4A1620 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4A1624 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4A1628 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4A162C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4A1630 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4A1634 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4A1638 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4A163C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4A1640 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4A1644 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4A1648 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4A164C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4A1650 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4A1654 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4A1658 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4A165C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4A1660 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4A1664 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4A1668 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4A166C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4A1670 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4A1674 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4A1678 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4A167C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4A1680 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4A1684 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4A1688 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4A168C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4A1690 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4A1694 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4A1698 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4A169C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4A16A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4A16A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4A16A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4A16AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4A16B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4A16B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4A16B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4A16BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4A16C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4A16C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4A16C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4A16CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4A16D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4A16D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4A16D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4A16DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4A16E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4A16E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4A16E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4A16EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4A16F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4A16F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4A16F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4A16FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4A1700 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4A1704 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4A1708 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4A170C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4A1710 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4A1714 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4A1718 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4A171C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4A1720 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4A1724 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4A1728 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4A172C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4A1730 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4A1734 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4A1738 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4A173C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4A1740 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4A1744 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4A1748 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4A174C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4A1750 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4A1754 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4A1758 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4A175C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4A1760 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4A1764 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4A1768 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4A176C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4A1770 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4A1774 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4A1778 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4A177C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4A1780 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4A1784 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4A1788 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4A178C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4A1790 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4A1794 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4A1798 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4A179C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4A17A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4A17A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4A17A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4A17AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4A17B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4A17B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4A17B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4A17BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4A17C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4A17C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4A17C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4A17CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4A17D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4A17D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4A17D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4A17DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4A17E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4A1824 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4A1828 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4A182C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4A1830 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4A1834 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4A1838 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4A183C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4A1840 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4A1844 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4A1848 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4A184C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4A1850 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4A1854 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4A1858 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4A185C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4A1860 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4A1864 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4A1868 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4A186C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4A1870 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4A1874 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4A1878 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4A187C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4A1880 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4A1884 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4A1888 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4A188C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4A1890 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4A1894 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4A1898 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4A189C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4A18A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4A18A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4A18A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4A18AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4A18B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4A18B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4A18B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4A18BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4A18C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4A18C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4A18C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4A18CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4A18D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4A18D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4A18D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4A18DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4A18E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4A18E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4A18E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4A18EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4A18F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4A18F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4A18F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4A18FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4A1900 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4A1904 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4A1908 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4A190C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4A1910 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4A1914 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4A1918 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4A191C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4A1920 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4A1924 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4A1928 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4A192C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4A1930 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4A1934 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4A1938 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4A193C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4A1940 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4A1944 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4A1948 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4A194C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4A1950 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4A1954 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4A1958 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4A195C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4A1960 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4A1964 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4A1968 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4A196C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4A1970 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4A1974 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4A1978 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4A197C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4A1980 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4A1984 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4A1988 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4A198C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4A1990 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4A1994 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4A1998 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4A199C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4A19A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4A19A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4A19A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4A19AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4A19B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4A19B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4A19B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4A19BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4A19C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4A19C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4A19C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4A19CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4A19D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4A19D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4A19D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4A19DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4A19E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4A19E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4A19E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4A19EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4A19F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4A19F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4A19F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4A19FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4A1A00 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4A1A04 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4A1A08 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4A1A0C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4A1A10 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4A1A14 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4A1A18 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4A1A1C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4A1A20 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x4A1A64 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x4A1A68 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4A1A6C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4A1A70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG 0x4A1B64 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT 0x4A1B68 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4A1B6C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4A1B70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4A1B74 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4A1B78 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4A1B7C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4A1B80 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4A1B84 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4A1B88 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0 0x4A1BAC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1 0x4A1BB0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2 0x4A1BB4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3 0x4A1BB8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4 0x4A1BBC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5 0x4A1BC0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6 0x4A1BC4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7 0x4A1BC8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0 0x4A1BEC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1 0x4A1BF0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2 0x4A1BF4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3 0x4A1BF8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4 0x4A1BFC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5 0x4A1C00 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6 0x4A1C04 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7 0x4A1C08 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT 0x4A1C2C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A1C30 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A1C34 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A1C38 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A1C3C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A1C40 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A1C44 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A1C48 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A1C4C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4A1C50 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4A1C54 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4A1C58 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4A1C5C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4A1C60 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4A1C64 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4A1C68 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4A1C6C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A1C70 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A1C74 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A1C78 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A1C7C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A1C80 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A1C84 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A1C88 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A1C8C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4A1C90 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4A1C94 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4A1C98 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4A1C9C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4A1CA0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4A1CA4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4A1CA8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4A1CAC + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x4A1CB0 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x4A1CB4 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x4A1CB8 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x4A1CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h new file mode 100644 index 000000000..3f32370a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL 0x4A2108 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0 0x4A2114 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1 0x4A2118 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2 0x4A211C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3 0x4A2120 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4 0x4A2124 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5 0x4A2128 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6 0x4A212C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7 0x4A2130 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8 0x4A2134 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9 0x4A2138 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10 0x4A213C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11 0x4A2140 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12 0x4A2144 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13 0x4A2148 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14 0x4A214C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15 0x4A2150 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16 0x4A2154 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17 0x4A2158 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18 0x4A215C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19 0x4A2160 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20 0x4A2164 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21 0x4A2168 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22 0x4A216C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23 0x4A2170 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24 0x4A2174 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25 0x4A2178 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26 0x4A217C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27 0x4A2180 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0 0x4A2184 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1 0x4A2188 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2 0x4A218C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3 0x4A2190 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4 0x4A2194 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5 0x4A2198 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6 0x4A219C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7 0x4A21A0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8 0x4A21A4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9 0x4A21A8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10 0x4A21AC + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11 0x4A21B0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12 0x4A21B4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13 0x4A21B8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14 0x4A21BC + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN 0x4A226C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN 0x4A2274 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT 0x4A2278 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST 0x4A227C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT 0x4A2280 + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN 0x4A2284 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN 0x4A2288 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT 0x4A228C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST 0x4A2290 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT 0x4A2294 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN 0x4A229C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT 0x4A22A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST 0x4A22A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4A22AC + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED 0x4A22B4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN 0x4A22EC + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN 0x4A22F0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4A22F4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4A22F8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4A2404 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4A2408 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4A240C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4A2410 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4A2414 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4A2418 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x4A241C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x4A2420 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4A2424 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4A2428 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4A242C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4A2430 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4A2434 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4A2438 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0 0x4A2450 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1 0x4A2454 + +#define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN 0x4A2480 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0 0x4A2500 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1 0x4A2504 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2 0x4A2508 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3 0x4A250C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4 0x4A2510 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x4A2514 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x4A2520 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x4A2524 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x4A2528 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x4A252C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x4A2530 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x4A2534 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x4A2538 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x4A253C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x4A2540 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0 0x4A2550 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1 0x4A2554 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2 0x4A2558 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3 0x4A255C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4 0x4A2560 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5 0x4A2564 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6 0x4A2568 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7 0x4A256C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8 0x4A2570 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9 0x4A2574 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10 0x4A2578 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11 0x4A257C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12 0x4A2580 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13 0x4A2584 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14 0x4A2588 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15 0x4A258C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16 0x4A2590 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17 0x4A2594 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18 0x4A2598 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4A25E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4A25E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4A25EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4A25F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4A25F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4A25F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4A25FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4A2600 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4A2604 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4A2608 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4A260C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4A2610 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4A2614 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4A2618 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4A261C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4A2620 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4A2624 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4A2628 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4A262C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4A2630 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4A2634 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4A2638 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4A263C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4A2640 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4A2644 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4A2648 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4A264C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4A2650 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4A2654 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4A2658 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4A265C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4A2660 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4A2664 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4A2668 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4A266C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4A2670 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4A2674 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4A2678 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4A267C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4A2680 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4A2684 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4A2688 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4A268C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4A2690 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4A2694 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4A2698 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4A269C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4A26A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4A26A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4A26A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4A26AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4A26B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4A26B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4A26B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4A26BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4A26C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4A26C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4A26C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4A26CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4A26D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4A26D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4A26D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4A26DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4A26E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4A26E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4A26E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4A26EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4A26F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4A26F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4A26F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4A26FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4A2700 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4A2704 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4A2708 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4A270C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4A2710 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4A2714 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4A2718 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4A271C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4A2720 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4A2724 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4A2728 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4A272C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4A2730 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4A2734 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4A2738 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4A273C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4A2740 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4A2744 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4A2748 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4A274C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4A2750 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4A2754 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4A2758 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4A275C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4A2760 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4A2764 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4A2768 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4A276C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4A2770 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4A2774 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4A2778 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4A277C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4A2780 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4A2784 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4A2788 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4A278C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4A2790 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4A2794 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4A2798 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4A279C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4A27A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4A27A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4A27A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4A27AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4A27B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4A27B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4A27B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4A27BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4A27C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4A27C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4A27C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4A27CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4A27D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4A27D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4A27D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4A27DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4A27E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4A2824 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4A2828 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4A282C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4A2830 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4A2834 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4A2838 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4A283C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4A2840 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4A2844 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4A2848 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4A284C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4A2850 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4A2854 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4A2858 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4A285C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4A2860 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4A2864 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4A2868 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4A286C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4A2870 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4A2874 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4A2878 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4A287C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4A2880 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4A2884 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4A2888 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4A288C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4A2890 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4A2894 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4A2898 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4A289C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4A28A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4A28A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4A28A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4A28AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4A28B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4A28B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4A28B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4A28BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4A28C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4A28C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4A28C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4A28CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4A28D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4A28D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4A28D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4A28DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4A28E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4A28E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4A28E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4A28EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4A28F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4A28F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4A28F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4A28FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4A2900 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4A2904 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4A2908 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4A290C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4A2910 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4A2914 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4A2918 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4A291C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4A2920 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4A2924 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4A2928 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4A292C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4A2930 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4A2934 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4A2938 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4A293C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4A2940 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4A2944 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4A2948 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4A294C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4A2950 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4A2954 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4A2958 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4A295C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4A2960 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4A2964 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4A2968 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4A296C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4A2970 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4A2974 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4A2978 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4A297C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4A2980 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4A2984 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4A2988 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4A298C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4A2990 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4A2994 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4A2998 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4A299C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4A29A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4A29A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4A29A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4A29AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4A29B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4A29B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4A29B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4A29BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4A29C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4A29C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4A29C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4A29CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4A29D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4A29D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4A29D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4A29DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4A29E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4A29E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4A29E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4A29EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4A29F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4A29F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4A29F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4A29FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4A2A00 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4A2A04 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4A2A08 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4A2A0C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4A2A10 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4A2A14 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4A2A18 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4A2A1C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4A2A20 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x4A2A64 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x4A2A68 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4A2A6C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4A2A70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG 0x4A2B64 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT 0x4A2B68 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4A2B6C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4A2B70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4A2B74 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4A2B78 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4A2B7C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4A2B80 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4A2B84 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4A2B88 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0 0x4A2BAC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1 0x4A2BB0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2 0x4A2BB4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3 0x4A2BB8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4 0x4A2BBC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5 0x4A2BC0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6 0x4A2BC4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7 0x4A2BC8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0 0x4A2BEC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1 0x4A2BF0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2 0x4A2BF4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3 0x4A2BF8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4 0x4A2BFC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5 0x4A2C00 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6 0x4A2C04 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7 0x4A2C08 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT 0x4A2C2C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A2C30 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A2C34 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A2C38 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A2C3C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A2C40 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A2C44 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A2C48 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A2C4C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4A2C50 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4A2C54 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4A2C58 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4A2C5C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4A2C60 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4A2C64 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4A2C68 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4A2C6C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A2C70 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A2C74 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A2C78 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A2C7C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A2C80 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A2C84 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A2C88 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A2C8C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4A2C90 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4A2C94 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4A2C98 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4A2C9C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4A2CA0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4A2CA4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4A2CA8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4A2CAC + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x4A2CB0 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x4A2CB4 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x4A2CB8 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x4A2CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h new file mode 100644 index 000000000..78c18da71 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_S_HBM0_WR_CRED_CNT 0x4A0000 + +#define mmDMA_IF_E_S_HBM1_WR_CRED_CNT 0x4A0004 + +#define mmDMA_IF_E_S_HBM0_RD_CRED_CNT 0x4A0008 + +#define mmDMA_IF_E_S_HBM1_RD_CRED_CNT 0x4A000C + +#define mmDMA_IF_E_S_HBM_LIMITER_0 0x4A0030 + +#define mmDMA_IF_E_S_HBM_LIMITER_1 0x4A0034 + +#define mmDMA_IF_E_S_HBM_LIMITER_2 0x4A0038 + +#define mmDMA_IF_E_S_HBM_LIMITER_3 0x4A003C + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_0 0x4A0040 + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_1 0x4A0044 + +#define mmDMA_IF_E_S_HBM_CRED_EN_0 0x4A0050 + +#define mmDMA_IF_E_S_HBM_CRED_EN_1 0x4A0054 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_0 0x4A0100 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_1 0x4A0104 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_2 0x4A0108 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_3 0x4A010C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_4 0x4A0110 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_5 0x4A0114 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_6 0x4A0118 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_7 0x4A011C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_8 0x4A0120 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_9 0x4A0124 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_10 0x4A0128 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_11 0x4A012C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_12 0x4A0130 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_13 0x4A0134 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_14 0x4A0138 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_15 0x4A013C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_0 0x4A0140 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_1 0x4A0144 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_2 0x4A0148 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_3 0x4A014C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_4 0x4A0150 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_5 0x4A0154 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_6 0x4A0158 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_7 0x4A015C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_8 0x4A0160 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_9 0x4A0164 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_10 0x4A0168 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_11 0x4A016C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_12 0x4A0170 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_13 0x4A0174 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_14 0x4A0178 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_15 0x4A017C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_0 0x4A0180 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_1 0x4A0184 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_2 0x4A0188 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_3 0x4A018C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_4 0x4A0190 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_5 0x4A0194 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_6 0x4A0198 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_7 0x4A019C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_8 0x4A01A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_9 0x4A01A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_10 0x4A01A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_11 0x4A01AC + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_12 0x4A01B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_13 0x4A01B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_14 0x4A01B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_15 0x4A01BC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_0 0x4A01C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_1 0x4A01C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_2 0x4A01C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_3 0x4A01CC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_4 0x4A01D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_5 0x4A01D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_6 0x4A01D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_7 0x4A01DC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_8 0x4A01E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_9 0x4A01E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_10 0x4A01E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_11 0x4A01EC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_12 0x4A01F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_13 0x4A01F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_14 0x4A01F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_15 0x4A01FC + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_0 0x4A0200 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_1 0x4A0204 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_2 0x4A0208 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_3 0x4A020C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_4 0x4A0210 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_5 0x4A0214 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_6 0x4A0218 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_7 0x4A021C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_8 0x4A0220 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_9 0x4A0224 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_10 0x4A0228 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_11 0x4A022C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_12 0x4A0230 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_13 0x4A0234 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_14 0x4A0238 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_15 0x4A023C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_0 0x4A0240 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_1 0x4A0244 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_2 0x4A0248 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_3 0x4A024C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_4 0x4A0250 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_5 0x4A0254 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_6 0x4A0258 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_7 0x4A025C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_8 0x4A0260 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_9 0x4A0264 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_10 0x4A0268 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_11 0x4A026C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_12 0x4A0270 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_13 0x4A0274 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_14 0x4A0278 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_15 0x4A027C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_0 0x4A0280 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_1 0x4A0284 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_2 0x4A0288 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_3 0x4A028C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_4 0x4A0290 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_5 0x4A0294 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_6 0x4A0298 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_7 0x4A029C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_8 0x4A02A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_9 0x4A02A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_10 0x4A02A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_11 0x4A02AC + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_12 0x4A02B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_13 0x4A02B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_14 0x4A02B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_15 0x4A02BC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_0 0x4A02C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_1 0x4A02C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_2 0x4A02C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_3 0x4A02CC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_4 0x4A02D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_5 0x4A02D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_6 0x4A02D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_7 0x4A02DC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_8 0x4A02E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_9 0x4A02E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_10 0x4A02E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_11 0x4A02EC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_12 0x4A02F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_13 0x4A02F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_14 0x4A02F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_15 0x4A02FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_0 0x4A0300 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_1 0x4A0304 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_2 0x4A0308 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_3 0x4A030C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_4 0x4A0310 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_5 0x4A0314 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_6 0x4A0318 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_7 0x4A031C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_8 0x4A0320 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_9 0x4A0324 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_10 0x4A0328 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_11 0x4A032C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_12 0x4A0330 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_13 0x4A0334 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_14 0x4A0338 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_15 0x4A033C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_0 0x4A0340 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_1 0x4A0344 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_2 0x4A0348 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_3 0x4A034C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_4 0x4A0350 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_5 0x4A0354 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_6 0x4A0358 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_7 0x4A035C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_8 0x4A0360 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_9 0x4A0364 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_10 0x4A0368 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_11 0x4A036C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_12 0x4A0370 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_13 0x4A0374 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_14 0x4A0378 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_15 0x4A037C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_0 0x4A0380 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_1 0x4A0384 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_2 0x4A0388 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_3 0x4A038C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_4 0x4A0390 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_5 0x4A0394 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_6 0x4A0398 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_7 0x4A039C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_8 0x4A03A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_9 0x4A03A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_10 0x4A03A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_11 0x4A03AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_12 0x4A03B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_13 0x4A03B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_14 0x4A03B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_15 0x4A03BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_0 0x4A03C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_1 0x4A03C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_2 0x4A03C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_3 0x4A03CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_4 0x4A03D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_5 0x4A03D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_6 0x4A03D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_7 0x4A03DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_8 0x4A03E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_9 0x4A03E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_10 0x4A03E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_11 0x4A03EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_12 0x4A03F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_13 0x4A03F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_14 0x4A03F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_15 0x4A03FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_0 0x4A0400 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_1 0x4A0404 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_2 0x4A0408 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_3 0x4A040C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_4 0x4A0410 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_5 0x4A0414 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_6 0x4A0418 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_7 0x4A041C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_8 0x4A0420 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_9 0x4A0424 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_10 0x4A0428 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_11 0x4A042C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_12 0x4A0430 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_13 0x4A0434 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_14 0x4A0438 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_15 0x4A043C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_0 0x4A0440 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_1 0x4A0444 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_2 0x4A0448 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_3 0x4A044C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_4 0x4A0450 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_5 0x4A0454 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_6 0x4A0458 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_7 0x4A045C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_8 0x4A0460 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_9 0x4A0464 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_10 0x4A0468 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_11 0x4A046C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_12 0x4A0470 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_13 0x4A0474 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_14 0x4A0478 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_15 0x4A047C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_0 0x4A0480 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_1 0x4A0484 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_2 0x4A0488 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_3 0x4A048C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_4 0x4A0490 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_5 0x4A0494 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_6 0x4A0498 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_7 0x4A049C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_8 0x4A04A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_9 0x4A04A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_10 0x4A04A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_11 0x4A04AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_12 0x4A04B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_13 0x4A04B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_14 0x4A04B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_15 0x4A04BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_0 0x4A04C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_1 0x4A04C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_2 0x4A04C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_3 0x4A04CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_4 0x4A04D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_5 0x4A04D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_6 0x4A04D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_7 0x4A04DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_8 0x4A04E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_9 0x4A04E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_10 0x4A04E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_11 0x4A04EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_12 0x4A04F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_13 0x4A04F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_14 0x4A04F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_15 0x4A04FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_0 0x4A0500 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_1 0x4A0504 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_2 0x4A0508 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_3 0x4A050C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_4 0x4A0510 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_5 0x4A0514 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_6 0x4A0518 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_7 0x4A051C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_8 0x4A0520 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_9 0x4A0524 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_10 0x4A0528 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_11 0x4A052C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_12 0x4A0530 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_13 0x4A0534 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_14 0x4A0538 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_15 0x4A053C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_0 0x4A0540 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_1 0x4A0544 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_2 0x4A0548 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_3 0x4A054C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_4 0x4A0550 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_5 0x4A0554 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_6 0x4A0558 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_7 0x4A055C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_8 0x4A0560 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_9 0x4A0564 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_10 0x4A0568 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_11 0x4A056C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_12 0x4A0570 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_13 0x4A0574 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_14 0x4A0578 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_15 0x4A057C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_0 0x4A0580 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_1 0x4A0584 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_2 0x4A0588 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_3 0x4A058C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_4 0x4A0590 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_5 0x4A0594 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_6 0x4A0598 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_7 0x4A059C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_8 0x4A05A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_9 0x4A05A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_10 0x4A05A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_11 0x4A05AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_12 0x4A05B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_13 0x4A05B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_14 0x4A05B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_15 0x4A05BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_0 0x4A05C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_1 0x4A05C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_2 0x4A05C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_3 0x4A05CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_4 0x4A05D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_5 0x4A05D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_6 0x4A05D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_7 0x4A05DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_8 0x4A05E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_9 0x4A05E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_10 0x4A05E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_11 0x4A05EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_12 0x4A05F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_13 0x4A05F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_14 0x4A05F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_15 0x4A05FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_0 0x4A0600 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_1 0x4A0604 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_2 0x4A0608 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_3 0x4A060C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_4 0x4A0610 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_5 0x4A0614 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_6 0x4A0618 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_7 0x4A061C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_8 0x4A0620 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_9 0x4A0624 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_10 0x4A0628 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_11 0x4A062C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_12 0x4A0630 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_13 0x4A0634 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_14 0x4A0638 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_15 0x4A063C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_0 0x4A0640 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_1 0x4A0644 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_2 0x4A0648 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_3 0x4A064C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_4 0x4A0650 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_5 0x4A0654 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_6 0x4A0658 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_7 0x4A065C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_8 0x4A0660 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_9 0x4A0664 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_10 0x4A0668 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_11 0x4A066C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_12 0x4A0670 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_13 0x4A0674 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_14 0x4A0678 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_15 0x4A067C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_0 0x4A0680 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_1 0x4A0684 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_2 0x4A0688 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_3 0x4A068C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_4 0x4A0690 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_5 0x4A0694 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_6 0x4A0698 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_7 0x4A069C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_8 0x4A06A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_9 0x4A06A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_10 0x4A06A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_11 0x4A06AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_12 0x4A06B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_13 0x4A06B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_14 0x4A06B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_15 0x4A06BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_0 0x4A06C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_1 0x4A06C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_2 0x4A06C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_3 0x4A06CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_4 0x4A06D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_5 0x4A06D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_6 0x4A06D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_7 0x4A06DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_8 0x4A06E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_9 0x4A06E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_10 0x4A06E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_11 0x4A06EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_12 0x4A06F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_13 0x4A06F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_14 0x4A06F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_15 0x4A06FC + +#define mmDMA_IF_E_S_SOB_HIT_RPROT 0x4A0700 + +#define mmDMA_IF_E_S_SOB_HIT_WPROT 0x4A0704 + +#define mmDMA_IF_E_S_SOB_HIT_RPRIV 0x4A070C + +#define mmDMA_IF_E_S_SOB_HIT_WPRIV 0x4A0710 + +#define mmDMA_IF_E_S_DMA0_HIT_RPROT 0x4A071C + +#define mmDMA_IF_E_S_DMA0_HIT_WPROT 0x4A0720 + +#define mmDMA_IF_E_S_DMA0_HIT_RPRIV 0x4A0724 + +#define mmDMA_IF_E_S_DMA0_HIT_WPRIV 0x4A0728 + +#define mmDMA_IF_E_S_DMA1_HIT_RPROT 0x4A0730 + +#define mmDMA_IF_E_S_DMA1_HIT_WPROT 0x4A0734 + +#define mmDMA_IF_E_S_DMA1_HIT_RPRIV 0x4A0738 + +#define mmDMA_IF_E_S_DMA1_HIT_WPRIV 0x4A073C + +#define mmDMA_IF_E_S_HBM_BIN 0x4A0800 + +#define mmDMA_IF_E_S_MME_BIN 0x4A0804 + +#define mmDMA_IF_E_S_TPC_BIN 0x4A0808 + +#define mmDMA_IF_E_S_DMA_BIN 0x4A080C + +#define mmDMA_IF_E_S_SOB_CG_EN 0x4A0810 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_0 0x4A0820 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_1 0x4A0824 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_2 0x4A0828 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_3 0x4A082C + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_4 0x4A0830 + +#define mmDMA_IF_E_S_HBM_MISC 0x4A0834 + +#endif /* ASIC_REG_DMA_IF_E_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h new file mode 100644 index 000000000..4ccaf8712 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL 0x4C1108 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0 0x4C1114 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1 0x4C1118 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2 0x4C111C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3 0x4C1120 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4 0x4C1124 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5 0x4C1128 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6 0x4C112C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7 0x4C1130 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8 0x4C1134 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9 0x4C1138 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10 0x4C113C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11 0x4C1140 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12 0x4C1144 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13 0x4C1148 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14 0x4C114C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15 0x4C1150 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16 0x4C1154 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17 0x4C1158 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18 0x4C115C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19 0x4C1160 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20 0x4C1164 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21 0x4C1168 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22 0x4C116C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23 0x4C1170 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24 0x4C1174 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25 0x4C1178 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26 0x4C117C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27 0x4C1180 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0 0x4C1184 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1 0x4C1188 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2 0x4C118C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3 0x4C1190 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4 0x4C1194 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5 0x4C1198 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6 0x4C119C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7 0x4C11A0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8 0x4C11A4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9 0x4C11A8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10 0x4C11AC + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11 0x4C11B0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_12 0x4C11B4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_13 0x4C11B8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_14 0x4C11BC + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN 0x4C126C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN 0x4C1274 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT 0x4C1278 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST 0x4C127C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4C1280 + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN 0x4C1284 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_EN 0x4C1288 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_SAT 0x4C128C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_RST 0x4C1290 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4C1294 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN 0x4C129C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT 0x4C12A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST 0x4C12A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4C12AC + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RED 0x4C12B4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN 0x4C12EC + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN 0x4C12F0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4C12F4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4C12F8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4C1404 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4C1408 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4C140C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4C1410 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4C1414 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4C1418 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4C141C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4C1420 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4C1424 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4C1428 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4C142C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4C1430 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4C1434 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4C1438 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0 0x4C1450 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1 0x4C1454 + +#define mmDMA_IF_W_N_DOWN_CH0_NON_LIN_EN 0x4C1480 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_0 0x4C1500 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_1 0x4C1504 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_2 0x4C1508 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_3 0x4C150C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_4 0x4C1510 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4C1514 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4C1520 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4C1524 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4C1528 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4C152C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4C1530 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4C1534 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4C1538 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4C153C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4C1540 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4C1550 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4C1554 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4C1558 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4C155C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4C1560 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4C1564 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4C1568 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4C156C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4C1570 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4C1574 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4C1578 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4C157C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4C1580 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4C1584 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4C1588 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4C158C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4C1590 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4C1594 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4C1598 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4C15E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4C15E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4C15EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4C15F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4C15F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4C15F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4C15FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4C1600 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4C1604 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4C1608 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4C160C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4C1610 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4C1614 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4C1618 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4C161C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4C1620 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4C1624 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4C1628 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4C162C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4C1630 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4C1634 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4C1638 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4C163C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4C1640 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4C1644 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4C1648 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4C164C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4C1650 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4C1654 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4C1658 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4C165C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4C1660 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4C1664 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4C1668 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4C166C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4C1670 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4C1674 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4C1678 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4C167C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4C1680 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4C1684 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4C1688 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4C168C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4C1690 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4C1694 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4C1698 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4C169C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4C16A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4C16A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4C16A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4C16AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4C16B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4C16B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4C16B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4C16BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4C16C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4C16C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4C16C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4C16CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4C16D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4C16D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4C16D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4C16DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4C16E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4C16E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4C16E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4C16EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4C16F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4C16F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4C16F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4C16FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4C1700 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4C1704 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4C1708 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4C170C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4C1710 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4C1714 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4C1718 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4C171C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4C1720 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4C1724 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4C1728 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4C172C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4C1730 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4C1734 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4C1738 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4C173C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4C1740 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4C1744 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4C1748 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4C174C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4C1750 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4C1754 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4C1758 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4C175C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4C1760 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4C1764 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4C1768 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4C176C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4C1770 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4C1774 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4C1778 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4C177C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4C1780 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4C1784 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4C1788 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4C178C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4C1790 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4C1794 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4C1798 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4C179C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4C17A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4C17A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4C17A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4C17AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4C17B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4C17B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4C17B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4C17BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4C17C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4C17C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4C17C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4C17CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4C17D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4C17D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4C17D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4C17DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4C17E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4C1824 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4C1828 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4C182C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4C1830 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4C1834 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4C1838 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4C183C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4C1840 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4C1844 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4C1848 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4C184C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4C1850 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4C1854 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4C1858 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4C185C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4C1860 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4C1864 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4C1868 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4C186C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4C1870 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4C1874 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4C1878 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4C187C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4C1880 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4C1884 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4C1888 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4C188C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4C1890 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4C1894 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4C1898 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4C189C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4C18A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4C18A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4C18A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4C18AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4C18B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4C18B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4C18B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4C18BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4C18C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4C18C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4C18C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4C18CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4C18D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4C18D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4C18D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4C18DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4C18E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4C18E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4C18E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4C18EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4C18F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4C18F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4C18F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4C18FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4C1900 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4C1904 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4C1908 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4C190C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4C1910 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4C1914 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4C1918 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4C191C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4C1920 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4C1924 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4C1928 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4C192C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4C1930 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4C1934 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4C1938 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4C193C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4C1940 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4C1944 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4C1948 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4C194C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4C1950 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4C1954 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4C1958 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4C195C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4C1960 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4C1964 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4C1968 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4C196C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4C1970 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4C1974 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4C1978 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4C197C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4C1980 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4C1984 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4C1988 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4C198C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4C1990 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4C1994 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4C1998 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4C199C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4C19A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4C19A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4C19A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4C19AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4C19B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4C19B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4C19B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4C19BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4C19C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4C19C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4C19C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4C19CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4C19D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4C19D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4C19D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4C19DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4C19E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4C19E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4C19E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4C19EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4C19F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4C19F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4C19F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4C19FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4C1A00 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4C1A04 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4C1A08 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4C1A0C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4C1A10 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4C1A14 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4C1A18 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4C1A1C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4C1A20 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4C1A64 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4C1A68 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4C1A6C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4C1A70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_CFG 0x4C1B64 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_SHIFT 0x4C1B68 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4C1B6C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4C1B70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4C1B74 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4C1B78 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4C1B7C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4C1B80 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4C1B84 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4C1B88 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_0 0x4C1BAC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_1 0x4C1BB0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_2 0x4C1BB4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_3 0x4C1BB8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_4 0x4C1BBC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_5 0x4C1BC0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_6 0x4C1BC4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_7 0x4C1BC8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_0 0x4C1BEC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_1 0x4C1BF0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_2 0x4C1BF4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_3 0x4C1BF8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_4 0x4C1BFC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_5 0x4C1C00 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_6 0x4C1C04 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_7 0x4C1C08 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_WDT 0x4C1C2C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C1C30 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C1C34 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C1C38 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C1C3C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C1C40 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C1C44 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C1C48 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C1C4C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4C1C50 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4C1C54 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4C1C58 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4C1C5C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4C1C60 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4C1C64 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4C1C68 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4C1C6C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C1C70 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C1C74 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C1C78 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C1C7C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C1C80 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C1C84 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C1C88 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C1C8C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4C1C90 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4C1C94 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4C1C98 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4C1C9C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4C1CA0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4C1CA4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4C1CA8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4C1CAC + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4C1CB0 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4C1CB4 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4C1CB8 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4C1CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h new file mode 100644 index 000000000..9236f4183 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL 0x4C2108 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0 0x4C2114 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1 0x4C2118 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2 0x4C211C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3 0x4C2120 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4 0x4C2124 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5 0x4C2128 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6 0x4C212C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7 0x4C2130 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8 0x4C2134 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9 0x4C2138 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10 0x4C213C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11 0x4C2140 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12 0x4C2144 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13 0x4C2148 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14 0x4C214C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15 0x4C2150 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16 0x4C2154 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17 0x4C2158 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18 0x4C215C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19 0x4C2160 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20 0x4C2164 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21 0x4C2168 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22 0x4C216C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23 0x4C2170 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24 0x4C2174 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25 0x4C2178 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26 0x4C217C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27 0x4C2180 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0 0x4C2184 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1 0x4C2188 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2 0x4C218C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3 0x4C2190 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4 0x4C2194 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5 0x4C2198 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6 0x4C219C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7 0x4C21A0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8 0x4C21A4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9 0x4C21A8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10 0x4C21AC + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11 0x4C21B0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12 0x4C21B4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13 0x4C21B8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14 0x4C21BC + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN 0x4C226C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN 0x4C2274 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT 0x4C2278 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST 0x4C227C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4C2280 + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN 0x4C2284 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN 0x4C2288 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT 0x4C228C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST 0x4C2290 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4C2294 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN 0x4C229C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT 0x4C22A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST 0x4C22A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4C22AC + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED 0x4C22B4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN 0x4C22EC + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN 0x4C22F0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4C22F4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4C22F8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4C2404 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4C2408 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4C240C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4C2410 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4C2414 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4C2418 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4C241C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4C2420 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4C2424 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4C2428 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4C242C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4C2430 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4C2434 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4C2438 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0 0x4C2450 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1 0x4C2454 + +#define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN 0x4C2480 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0 0x4C2500 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1 0x4C2504 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2 0x4C2508 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3 0x4C250C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4 0x4C2510 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4C2514 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4C2520 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4C2524 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4C2528 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4C252C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4C2530 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4C2534 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4C2538 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4C253C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4C2540 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4C2550 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4C2554 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4C2558 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4C255C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4C2560 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4C2564 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4C2568 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4C256C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4C2570 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4C2574 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4C2578 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4C257C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4C2580 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4C2584 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4C2588 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4C258C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4C2590 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4C2594 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4C2598 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4C25E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4C25E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4C25EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4C25F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4C25F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4C25F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4C25FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4C2600 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4C2604 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4C2608 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4C260C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4C2610 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4C2614 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4C2618 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4C261C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4C2620 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4C2624 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4C2628 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4C262C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4C2630 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4C2634 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4C2638 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4C263C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4C2640 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4C2644 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4C2648 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4C264C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4C2650 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4C2654 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4C2658 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4C265C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4C2660 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4C2664 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4C2668 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4C266C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4C2670 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4C2674 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4C2678 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4C267C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4C2680 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4C2684 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4C2688 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4C268C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4C2690 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4C2694 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4C2698 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4C269C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4C26A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4C26A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4C26A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4C26AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4C26B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4C26B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4C26B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4C26BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4C26C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4C26C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4C26C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4C26CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4C26D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4C26D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4C26D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4C26DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4C26E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4C26E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4C26E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4C26EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4C26F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4C26F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4C26F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4C26FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4C2700 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4C2704 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4C2708 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4C270C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4C2710 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4C2714 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4C2718 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4C271C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4C2720 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4C2724 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4C2728 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4C272C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4C2730 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4C2734 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4C2738 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4C273C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4C2740 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4C2744 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4C2748 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4C274C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4C2750 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4C2754 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4C2758 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4C275C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4C2760 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4C2764 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4C2768 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4C276C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4C2770 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4C2774 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4C2778 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4C277C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4C2780 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4C2784 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4C2788 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4C278C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4C2790 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4C2794 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4C2798 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4C279C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4C27A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4C27A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4C27A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4C27AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4C27B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4C27B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4C27B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4C27BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4C27C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4C27C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4C27C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4C27CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4C27D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4C27D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4C27D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4C27DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4C27E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4C2824 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4C2828 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4C282C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4C2830 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4C2834 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4C2838 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4C283C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4C2840 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4C2844 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4C2848 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4C284C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4C2850 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4C2854 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4C2858 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4C285C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4C2860 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4C2864 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4C2868 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4C286C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4C2870 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4C2874 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4C2878 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4C287C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4C2880 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4C2884 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4C2888 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4C288C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4C2890 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4C2894 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4C2898 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4C289C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4C28A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4C28A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4C28A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4C28AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4C28B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4C28B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4C28B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4C28BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4C28C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4C28C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4C28C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4C28CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4C28D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4C28D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4C28D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4C28DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4C28E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4C28E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4C28E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4C28EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4C28F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4C28F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4C28F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4C28FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4C2900 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4C2904 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4C2908 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4C290C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4C2910 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4C2914 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4C2918 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4C291C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4C2920 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4C2924 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4C2928 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4C292C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4C2930 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4C2934 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4C2938 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4C293C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4C2940 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4C2944 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4C2948 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4C294C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4C2950 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4C2954 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4C2958 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4C295C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4C2960 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4C2964 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4C2968 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4C296C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4C2970 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4C2974 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4C2978 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4C297C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4C2980 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4C2984 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4C2988 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4C298C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4C2990 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4C2994 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4C2998 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4C299C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4C29A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4C29A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4C29A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4C29AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4C29B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4C29B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4C29B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4C29BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4C29C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4C29C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4C29C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4C29CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4C29D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4C29D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4C29D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4C29DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4C29E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4C29E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4C29E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4C29EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4C29F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4C29F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4C29F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4C29FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4C2A00 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4C2A04 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4C2A08 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4C2A0C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4C2A10 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4C2A14 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4C2A18 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4C2A1C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4C2A20 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4C2A64 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4C2A68 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4C2A6C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4C2A70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG 0x4C2B64 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT 0x4C2B68 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4C2B6C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4C2B70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4C2B74 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4C2B78 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4C2B7C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4C2B80 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4C2B84 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4C2B88 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0 0x4C2BAC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1 0x4C2BB0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2 0x4C2BB4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3 0x4C2BB8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4 0x4C2BBC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5 0x4C2BC0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6 0x4C2BC4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7 0x4C2BC8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0 0x4C2BEC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1 0x4C2BF0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2 0x4C2BF4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3 0x4C2BF8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4 0x4C2BFC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5 0x4C2C00 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6 0x4C2C04 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7 0x4C2C08 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT 0x4C2C2C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C2C30 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C2C34 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C2C38 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C2C3C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C2C40 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C2C44 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C2C48 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C2C4C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4C2C50 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4C2C54 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4C2C58 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4C2C5C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4C2C60 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4C2C64 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4C2C68 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4C2C6C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C2C70 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C2C74 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C2C78 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C2C7C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C2C80 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C2C84 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C2C88 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C2C8C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4C2C90 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4C2C94 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4C2C98 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4C2C9C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4C2CA0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4C2CA4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4C2CA8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4C2CAC + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4C2CB0 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4C2CB4 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4C2CB8 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4C2CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h new file mode 100644 index 000000000..da60893a5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_N_HBM0_WR_CRED_CNT 0x4C0000 + +#define mmDMA_IF_W_N_HBM1_WR_CRED_CNT 0x4C0004 + +#define mmDMA_IF_W_N_HBM0_RD_CRED_CNT 0x4C0008 + +#define mmDMA_IF_W_N_HBM1_RD_CRED_CNT 0x4C000C + +#define mmDMA_IF_W_N_HBM_LIMITER_0 0x4C0030 + +#define mmDMA_IF_W_N_HBM_LIMITER_1 0x4C0034 + +#define mmDMA_IF_W_N_HBM_LIMITER_2 0x4C0038 + +#define mmDMA_IF_W_N_HBM_LIMITER_3 0x4C003C + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_0 0x4C0040 + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_1 0x4C0044 + +#define mmDMA_IF_W_N_HBM_CRED_EN_0 0x4C0050 + +#define mmDMA_IF_W_N_HBM_CRED_EN_1 0x4C0054 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_0 0x4C0100 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_1 0x4C0104 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_2 0x4C0108 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_3 0x4C010C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_4 0x4C0110 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_5 0x4C0114 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_6 0x4C0118 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_7 0x4C011C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_8 0x4C0120 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_9 0x4C0124 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_10 0x4C0128 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_11 0x4C012C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_12 0x4C0130 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_13 0x4C0134 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_14 0x4C0138 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_15 0x4C013C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_0 0x4C0140 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_1 0x4C0144 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_2 0x4C0148 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_3 0x4C014C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_4 0x4C0150 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_5 0x4C0154 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_6 0x4C0158 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_7 0x4C015C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_8 0x4C0160 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_9 0x4C0164 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_10 0x4C0168 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_11 0x4C016C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_12 0x4C0170 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_13 0x4C0174 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_14 0x4C0178 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_15 0x4C017C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_0 0x4C0180 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_1 0x4C0184 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_2 0x4C0188 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_3 0x4C018C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_4 0x4C0190 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_5 0x4C0194 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_6 0x4C0198 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_7 0x4C019C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_8 0x4C01A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_9 0x4C01A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_10 0x4C01A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_11 0x4C01AC + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_12 0x4C01B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_13 0x4C01B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_14 0x4C01B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_15 0x4C01BC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_0 0x4C01C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_1 0x4C01C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_2 0x4C01C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_3 0x4C01CC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_4 0x4C01D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_5 0x4C01D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_6 0x4C01D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_7 0x4C01DC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_8 0x4C01E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_9 0x4C01E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_10 0x4C01E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_11 0x4C01EC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_12 0x4C01F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_13 0x4C01F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_14 0x4C01F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_15 0x4C01FC + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_0 0x4C0200 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_1 0x4C0204 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_2 0x4C0208 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_3 0x4C020C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_4 0x4C0210 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_5 0x4C0214 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_6 0x4C0218 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_7 0x4C021C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_8 0x4C0220 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_9 0x4C0224 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_10 0x4C0228 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_11 0x4C022C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_12 0x4C0230 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_13 0x4C0234 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_14 0x4C0238 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_15 0x4C023C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_0 0x4C0240 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_1 0x4C0244 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_2 0x4C0248 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_3 0x4C024C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_4 0x4C0250 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_5 0x4C0254 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_6 0x4C0258 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_7 0x4C025C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_8 0x4C0260 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_9 0x4C0264 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_10 0x4C0268 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_11 0x4C026C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_12 0x4C0270 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_13 0x4C0274 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_14 0x4C0278 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_15 0x4C027C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_0 0x4C0280 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_1 0x4C0284 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_2 0x4C0288 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_3 0x4C028C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_4 0x4C0290 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_5 0x4C0294 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_6 0x4C0298 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_7 0x4C029C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_8 0x4C02A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_9 0x4C02A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_10 0x4C02A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_11 0x4C02AC + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_12 0x4C02B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_13 0x4C02B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_14 0x4C02B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_15 0x4C02BC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_0 0x4C02C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_1 0x4C02C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_2 0x4C02C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_3 0x4C02CC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_4 0x4C02D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_5 0x4C02D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_6 0x4C02D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_7 0x4C02DC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_8 0x4C02E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_9 0x4C02E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_10 0x4C02E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_11 0x4C02EC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_12 0x4C02F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_13 0x4C02F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_14 0x4C02F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_15 0x4C02FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_0 0x4C0300 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_1 0x4C0304 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_2 0x4C0308 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_3 0x4C030C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_4 0x4C0310 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_5 0x4C0314 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_6 0x4C0318 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_7 0x4C031C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_8 0x4C0320 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_9 0x4C0324 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_10 0x4C0328 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_11 0x4C032C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_12 0x4C0330 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_13 0x4C0334 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_14 0x4C0338 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_15 0x4C033C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_0 0x4C0340 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_1 0x4C0344 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_2 0x4C0348 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_3 0x4C034C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_4 0x4C0350 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_5 0x4C0354 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_6 0x4C0358 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_7 0x4C035C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_8 0x4C0360 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_9 0x4C0364 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_10 0x4C0368 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_11 0x4C036C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_12 0x4C0370 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_13 0x4C0374 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_14 0x4C0378 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_15 0x4C037C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_0 0x4C0380 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_1 0x4C0384 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_2 0x4C0388 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_3 0x4C038C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_4 0x4C0390 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_5 0x4C0394 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_6 0x4C0398 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_7 0x4C039C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_8 0x4C03A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_9 0x4C03A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_10 0x4C03A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_11 0x4C03AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_12 0x4C03B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_13 0x4C03B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_14 0x4C03B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_15 0x4C03BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_0 0x4C03C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_1 0x4C03C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_2 0x4C03C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_3 0x4C03CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_4 0x4C03D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_5 0x4C03D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_6 0x4C03D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_7 0x4C03DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_8 0x4C03E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_9 0x4C03E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_10 0x4C03E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_11 0x4C03EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_12 0x4C03F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_13 0x4C03F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_14 0x4C03F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_15 0x4C03FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_0 0x4C0400 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_1 0x4C0404 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_2 0x4C0408 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_3 0x4C040C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_4 0x4C0410 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_5 0x4C0414 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_6 0x4C0418 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_7 0x4C041C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_8 0x4C0420 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_9 0x4C0424 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_10 0x4C0428 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_11 0x4C042C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_12 0x4C0430 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_13 0x4C0434 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_14 0x4C0438 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_15 0x4C043C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_0 0x4C0440 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_1 0x4C0444 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_2 0x4C0448 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_3 0x4C044C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_4 0x4C0450 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_5 0x4C0454 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_6 0x4C0458 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_7 0x4C045C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_8 0x4C0460 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_9 0x4C0464 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_10 0x4C0468 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_11 0x4C046C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_12 0x4C0470 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_13 0x4C0474 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_14 0x4C0478 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_15 0x4C047C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_0 0x4C0480 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_1 0x4C0484 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_2 0x4C0488 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_3 0x4C048C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_4 0x4C0490 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_5 0x4C0494 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_6 0x4C0498 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_7 0x4C049C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_8 0x4C04A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_9 0x4C04A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_10 0x4C04A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_11 0x4C04AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_12 0x4C04B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_13 0x4C04B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_14 0x4C04B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_15 0x4C04BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_0 0x4C04C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_1 0x4C04C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_2 0x4C04C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_3 0x4C04CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_4 0x4C04D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_5 0x4C04D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_6 0x4C04D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_7 0x4C04DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_8 0x4C04E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_9 0x4C04E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_10 0x4C04E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_11 0x4C04EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_12 0x4C04F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_13 0x4C04F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_14 0x4C04F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_15 0x4C04FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_0 0x4C0500 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_1 0x4C0504 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_2 0x4C0508 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_3 0x4C050C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_4 0x4C0510 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_5 0x4C0514 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_6 0x4C0518 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_7 0x4C051C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_8 0x4C0520 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_9 0x4C0524 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_10 0x4C0528 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_11 0x4C052C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_12 0x4C0530 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_13 0x4C0534 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_14 0x4C0538 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_15 0x4C053C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_0 0x4C0540 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_1 0x4C0544 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_2 0x4C0548 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_3 0x4C054C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_4 0x4C0550 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_5 0x4C0554 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_6 0x4C0558 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_7 0x4C055C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_8 0x4C0560 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_9 0x4C0564 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_10 0x4C0568 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_11 0x4C056C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_12 0x4C0570 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_13 0x4C0574 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_14 0x4C0578 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_15 0x4C057C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_0 0x4C0580 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_1 0x4C0584 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_2 0x4C0588 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_3 0x4C058C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_4 0x4C0590 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_5 0x4C0594 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_6 0x4C0598 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_7 0x4C059C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_8 0x4C05A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_9 0x4C05A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_10 0x4C05A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_11 0x4C05AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_12 0x4C05B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_13 0x4C05B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_14 0x4C05B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_15 0x4C05BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_0 0x4C05C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_1 0x4C05C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_2 0x4C05C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_3 0x4C05CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_4 0x4C05D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_5 0x4C05D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_6 0x4C05D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_7 0x4C05DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_8 0x4C05E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_9 0x4C05E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_10 0x4C05E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_11 0x4C05EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_12 0x4C05F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_13 0x4C05F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_14 0x4C05F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_15 0x4C05FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_0 0x4C0600 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_1 0x4C0604 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_2 0x4C0608 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_3 0x4C060C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_4 0x4C0610 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_5 0x4C0614 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_6 0x4C0618 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_7 0x4C061C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_8 0x4C0620 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_9 0x4C0624 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_10 0x4C0628 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_11 0x4C062C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_12 0x4C0630 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_13 0x4C0634 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_14 0x4C0638 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_15 0x4C063C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_0 0x4C0640 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_1 0x4C0644 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_2 0x4C0648 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_3 0x4C064C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_4 0x4C0650 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_5 0x4C0654 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_6 0x4C0658 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_7 0x4C065C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_8 0x4C0660 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_9 0x4C0664 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_10 0x4C0668 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_11 0x4C066C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_12 0x4C0670 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_13 0x4C0674 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_14 0x4C0678 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_15 0x4C067C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_0 0x4C0680 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_1 0x4C0684 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_2 0x4C0688 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_3 0x4C068C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_4 0x4C0690 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_5 0x4C0694 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_6 0x4C0698 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_7 0x4C069C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_8 0x4C06A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_9 0x4C06A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_10 0x4C06A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_11 0x4C06AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_12 0x4C06B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_13 0x4C06B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_14 0x4C06B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_15 0x4C06BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_0 0x4C06C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_1 0x4C06C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_2 0x4C06C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_3 0x4C06CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_4 0x4C06D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_5 0x4C06D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_6 0x4C06D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_7 0x4C06DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_8 0x4C06E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_9 0x4C06E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_10 0x4C06E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_11 0x4C06EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_12 0x4C06F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_13 0x4C06F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_14 0x4C06F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_15 0x4C06FC + +#define mmDMA_IF_W_N_SOB_HIT_RPROT 0x4C0700 + +#define mmDMA_IF_W_N_SOB_HIT_WPROT 0x4C0704 + +#define mmDMA_IF_W_N_SOB_HIT_RPRIV 0x4C070C + +#define mmDMA_IF_W_N_SOB_HIT_WPRIV 0x4C0710 + +#define mmDMA_IF_W_N_DMA0_HIT_RPROT 0x4C071C + +#define mmDMA_IF_W_N_DMA0_HIT_WPROT 0x4C0720 + +#define mmDMA_IF_W_N_DMA0_HIT_RPRIV 0x4C0724 + +#define mmDMA_IF_W_N_DMA0_HIT_WPRIV 0x4C0728 + +#define mmDMA_IF_W_N_DMA1_HIT_RPROT 0x4C0730 + +#define mmDMA_IF_W_N_DMA1_HIT_WPROT 0x4C0734 + +#define mmDMA_IF_W_N_DMA1_HIT_RPRIV 0x4C0738 + +#define mmDMA_IF_W_N_DMA1_HIT_WPRIV 0x4C073C + +#define mmDMA_IF_W_N_HBM_BIN 0x4C0800 + +#define mmDMA_IF_W_N_MME_BIN 0x4C0804 + +#define mmDMA_IF_W_N_TPC_BIN 0x4C0808 + +#define mmDMA_IF_W_N_DMA_BIN 0x4C080C + +#define mmDMA_IF_W_N_SOB_CG_EN 0x4C0810 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_0 0x4C0820 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_1 0x4C0824 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_2 0x4C0828 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_3 0x4C082C + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_4 0x4C0830 + +#define mmDMA_IF_W_N_HBM_MISC 0x4C0834 + +#endif /* ASIC_REG_DMA_IF_W_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h new file mode 100644 index 000000000..56ffc920d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280 + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454 + +#define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h new file mode 100644 index 000000000..cbc642918 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280 + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454 + +#define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h new file mode 100644 index 000000000..2382bc41b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_S_HBM0_WR_CRED_CNT 0x480000 + +#define mmDMA_IF_W_S_HBM1_WR_CRED_CNT 0x480004 + +#define mmDMA_IF_W_S_HBM0_RD_CRED_CNT 0x480008 + +#define mmDMA_IF_W_S_HBM1_RD_CRED_CNT 0x48000C + +#define mmDMA_IF_W_S_HBM_LIMITER_0 0x480030 + +#define mmDMA_IF_W_S_HBM_LIMITER_1 0x480034 + +#define mmDMA_IF_W_S_HBM_LIMITER_2 0x480038 + +#define mmDMA_IF_W_S_HBM_LIMITER_3 0x48003C + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_0 0x480040 + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_1 0x480044 + +#define mmDMA_IF_W_S_HBM_CRED_EN_0 0x480050 + +#define mmDMA_IF_W_S_HBM_CRED_EN_1 0x480054 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_0 0x480100 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_1 0x480104 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_2 0x480108 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_3 0x48010C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_4 0x480110 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_5 0x480114 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_6 0x480118 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_7 0x48011C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_8 0x480120 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_9 0x480124 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_10 0x480128 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_11 0x48012C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_12 0x480130 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_13 0x480134 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_14 0x480138 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_15 0x48013C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_0 0x480140 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_1 0x480144 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_2 0x480148 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_3 0x48014C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_4 0x480150 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_5 0x480154 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_6 0x480158 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_7 0x48015C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_8 0x480160 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_9 0x480164 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_10 0x480168 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_11 0x48016C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_12 0x480170 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_13 0x480174 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_14 0x480178 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_15 0x48017C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_0 0x480180 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_1 0x480184 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_2 0x480188 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_3 0x48018C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_4 0x480190 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_5 0x480194 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_6 0x480198 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_7 0x48019C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_8 0x4801A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_9 0x4801A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_10 0x4801A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_11 0x4801AC + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_12 0x4801B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_13 0x4801B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_14 0x4801B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_15 0x4801BC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_0 0x4801C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_1 0x4801C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_2 0x4801C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_3 0x4801CC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_4 0x4801D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_5 0x4801D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_6 0x4801D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_7 0x4801DC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_8 0x4801E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_9 0x4801E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_10 0x4801E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_11 0x4801EC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_12 0x4801F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_13 0x4801F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_14 0x4801F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_15 0x4801FC + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_0 0x480200 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_1 0x480204 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_2 0x480208 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_3 0x48020C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_4 0x480210 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_5 0x480214 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_6 0x480218 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_7 0x48021C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_8 0x480220 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_9 0x480224 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_10 0x480228 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_11 0x48022C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_12 0x480230 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_13 0x480234 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_14 0x480238 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_15 0x48023C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_0 0x480240 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_1 0x480244 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_2 0x480248 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_3 0x48024C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_4 0x480250 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_5 0x480254 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_6 0x480258 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_7 0x48025C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_8 0x480260 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_9 0x480264 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_10 0x480268 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_11 0x48026C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_12 0x480270 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_13 0x480274 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_14 0x480278 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_15 0x48027C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_0 0x480280 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_1 0x480284 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_2 0x480288 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_3 0x48028C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_4 0x480290 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_5 0x480294 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_6 0x480298 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_7 0x48029C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_8 0x4802A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_9 0x4802A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_10 0x4802A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_11 0x4802AC + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_12 0x4802B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_13 0x4802B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_14 0x4802B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_15 0x4802BC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_0 0x4802C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_1 0x4802C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_2 0x4802C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_3 0x4802CC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_4 0x4802D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_5 0x4802D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_6 0x4802D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_7 0x4802DC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_8 0x4802E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_9 0x4802E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_10 0x4802E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_11 0x4802EC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_12 0x4802F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_13 0x4802F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_14 0x4802F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_15 0x4802FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_0 0x480300 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_1 0x480304 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_2 0x480308 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_3 0x48030C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_4 0x480310 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_5 0x480314 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_6 0x480318 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_7 0x48031C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_8 0x480320 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_9 0x480324 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_10 0x480328 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_11 0x48032C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_12 0x480330 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_13 0x480334 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_14 0x480338 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_15 0x48033C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_0 0x480340 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_1 0x480344 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_2 0x480348 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_3 0x48034C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_4 0x480350 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_5 0x480354 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_6 0x480358 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_7 0x48035C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_8 0x480360 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_9 0x480364 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_10 0x480368 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_11 0x48036C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_12 0x480370 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_13 0x480374 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_14 0x480378 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_15 0x48037C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_0 0x480380 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_1 0x480384 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_2 0x480388 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_3 0x48038C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_4 0x480390 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_5 0x480394 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_6 0x480398 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_7 0x48039C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_8 0x4803A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_9 0x4803A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_10 0x4803A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_11 0x4803AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_12 0x4803B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_13 0x4803B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_14 0x4803B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_15 0x4803BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_0 0x4803C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_1 0x4803C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_2 0x4803C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_3 0x4803CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_4 0x4803D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_5 0x4803D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_6 0x4803D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_7 0x4803DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_8 0x4803E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_9 0x4803E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_10 0x4803E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_11 0x4803EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_12 0x4803F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_13 0x4803F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_14 0x4803F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_15 0x4803FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_0 0x480400 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_1 0x480404 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_2 0x480408 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_3 0x48040C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_4 0x480410 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_5 0x480414 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_6 0x480418 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_7 0x48041C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_8 0x480420 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_9 0x480424 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_10 0x480428 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_11 0x48042C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_12 0x480430 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_13 0x480434 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_14 0x480438 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_15 0x48043C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_0 0x480440 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_1 0x480444 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_2 0x480448 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_3 0x48044C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_4 0x480450 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_5 0x480454 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_6 0x480458 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_7 0x48045C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_8 0x480460 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_9 0x480464 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_10 0x480468 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_11 0x48046C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_12 0x480470 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_13 0x480474 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_14 0x480478 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_15 0x48047C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_0 0x480480 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_1 0x480484 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_2 0x480488 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_3 0x48048C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_4 0x480490 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_5 0x480494 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_6 0x480498 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_7 0x48049C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_8 0x4804A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_9 0x4804A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_10 0x4804A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_11 0x4804AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_12 0x4804B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_13 0x4804B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_14 0x4804B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_15 0x4804BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_0 0x4804C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_1 0x4804C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_2 0x4804C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_3 0x4804CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_4 0x4804D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_5 0x4804D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_6 0x4804D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_7 0x4804DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_8 0x4804E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_9 0x4804E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_10 0x4804E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_11 0x4804EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_12 0x4804F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_13 0x4804F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_14 0x4804F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_15 0x4804FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_0 0x480500 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_1 0x480504 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_2 0x480508 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_3 0x48050C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_4 0x480510 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_5 0x480514 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_6 0x480518 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_7 0x48051C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_8 0x480520 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_9 0x480524 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_10 0x480528 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_11 0x48052C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_12 0x480530 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_13 0x480534 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_14 0x480538 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_15 0x48053C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_0 0x480540 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_1 0x480544 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_2 0x480548 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_3 0x48054C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_4 0x480550 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_5 0x480554 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_6 0x480558 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_7 0x48055C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_8 0x480560 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_9 0x480564 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_10 0x480568 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_11 0x48056C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_12 0x480570 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_13 0x480574 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_14 0x480578 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_15 0x48057C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_0 0x480580 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_1 0x480584 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_2 0x480588 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_3 0x48058C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_4 0x480590 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_5 0x480594 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_6 0x480598 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_7 0x48059C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_8 0x4805A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_9 0x4805A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_10 0x4805A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_11 0x4805AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_12 0x4805B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_13 0x4805B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_14 0x4805B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_15 0x4805BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_0 0x4805C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_1 0x4805C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_2 0x4805C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_3 0x4805CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_4 0x4805D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_5 0x4805D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_6 0x4805D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_7 0x4805DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_8 0x4805E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_9 0x4805E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_10 0x4805E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_11 0x4805EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_12 0x4805F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_13 0x4805F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_14 0x4805F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_15 0x4805FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_0 0x480600 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_1 0x480604 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_2 0x480608 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_3 0x48060C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_4 0x480610 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_5 0x480614 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_6 0x480618 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_7 0x48061C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_8 0x480620 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_9 0x480624 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_10 0x480628 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_11 0x48062C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_12 0x480630 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_13 0x480634 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_14 0x480638 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_15 0x48063C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_0 0x480640 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_1 0x480644 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_2 0x480648 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_3 0x48064C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_4 0x480650 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_5 0x480654 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_6 0x480658 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_7 0x48065C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_8 0x480660 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_9 0x480664 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_10 0x480668 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_11 0x48066C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_12 0x480670 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_13 0x480674 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_14 0x480678 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_15 0x48067C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_0 0x480680 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_1 0x480684 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_2 0x480688 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_3 0x48068C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_4 0x480690 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_5 0x480694 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_6 0x480698 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_7 0x48069C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_8 0x4806A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_9 0x4806A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_10 0x4806A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_11 0x4806AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_12 0x4806B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_13 0x4806B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_14 0x4806B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_15 0x4806BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_0 0x4806C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_1 0x4806C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_2 0x4806C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_3 0x4806CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_4 0x4806D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_5 0x4806D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_6 0x4806D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_7 0x4806DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_8 0x4806E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_9 0x4806E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_10 0x4806E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_11 0x4806EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_12 0x4806F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_13 0x4806F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_14 0x4806F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_15 0x4806FC + +#define mmDMA_IF_W_S_SOB_HIT_RPROT 0x480700 + +#define mmDMA_IF_W_S_SOB_HIT_WPROT 0x480704 + +#define mmDMA_IF_W_S_SOB_HIT_RPRIV 0x48070C + +#define mmDMA_IF_W_S_SOB_HIT_WPRIV 0x480710 + +#define mmDMA_IF_W_S_DMA0_HIT_RPROT 0x48071C + +#define mmDMA_IF_W_S_DMA0_HIT_WPROT 0x480720 + +#define mmDMA_IF_W_S_DMA0_HIT_RPRIV 0x480724 + +#define mmDMA_IF_W_S_DMA0_HIT_WPRIV 0x480728 + +#define mmDMA_IF_W_S_DMA1_HIT_RPROT 0x480730 + +#define mmDMA_IF_W_S_DMA1_HIT_WPROT 0x480734 + +#define mmDMA_IF_W_S_DMA1_HIT_RPRIV 0x480738 + +#define mmDMA_IF_W_S_DMA1_HIT_WPRIV 0x48073C + +#define mmDMA_IF_W_S_HBM_BIN 0x480800 + +#define mmDMA_IF_W_S_MME_BIN 0x480804 + +#define mmDMA_IF_W_S_TPC_BIN 0x480808 + +#define mmDMA_IF_W_S_DMA_BIN 0x48080C + +#define mmDMA_IF_W_S_SOB_CG_EN 0x480810 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_0 0x480820 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_1 0x480824 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_2 0x480828 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_3 0x48082C + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_4 0x480830 + +#define mmDMA_IF_W_S_HBM_MISC 0x480834 + +#endif /* ASIC_REG_DMA_IF_W_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h new file mode 100644 index 000000000..c7596aac7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h @@ -0,0 +1,4974 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI_BLOCKS_H_ +#define GAUDI_BLOCKS_H_ + +#define mmNIC0_PHY0_BASE 0x0ull +#define NIC0_PHY0_MAX_OFFSET 0x9F13 +#define mmMME0_ACC_BASE 0x7FFC020000ull +#define MME0_ACC_MAX_OFFSET 0x5C00 +#define MME0_ACC_SECTION 0x20000 +#define mmMME0_SBAB_BASE 0x7FFC040000ull +#define MME0_SBAB_MAX_OFFSET 0x5800 +#define MME0_SBAB_SECTION 0x1000 +#define mmMME0_PRTN_BASE 0x7FFC041000ull +#define MME0_PRTN_MAX_OFFSET 0x5000 +#define MME0_PRTN_SECTION 0x1F000 +#define mmMME0_CTRL_BASE 0x7FFC060000ull +#define MME0_CTRL_MAX_OFFSET 0xDA80 +#define MME0_CTRL_SECTION 0x8000 +#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull +#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME0_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull +#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull +#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull +#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull +#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull +#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull +#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull +#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull +#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull +#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME0_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull +#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull +#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull +#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull +#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull +#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull +#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull +#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull +#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull +#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull +#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull +#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull +#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull +#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull +#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull +#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull +#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull +#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull +#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull +#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull +#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull +#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull +#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull +#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull +#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC +#define mmMME0_QM_BASE 0x7FFC068000ull +#define MME0_QM_MAX_OFFSET 0xD040 +#define MME0_QM_SECTION 0x38000 +#define mmMME1_ACC_BASE 0x7FFC0A0000ull +#define MME1_ACC_MAX_OFFSET 0x5C00 +#define MME1_ACC_SECTION 0x20000 +#define mmMME1_SBAB_BASE 0x7FFC0C0000ull +#define MME1_SBAB_MAX_OFFSET 0x5800 +#define MME1_SBAB_SECTION 0x1000 +#define mmMME1_PRTN_BASE 0x7FFC0C1000ull +#define MME1_PRTN_MAX_OFFSET 0x5000 +#define MME1_PRTN_SECTION 0x1F000 +#define mmMME1_CTRL_BASE 0x7FFC0E0000ull +#define MME1_CTRL_MAX_OFFSET 0xDA80 +#define MME1_CTRL_SECTION 0x8000 +#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull +#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME1_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull +#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull +#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull +#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull +#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull +#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull +#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull +#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull +#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull +#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME1_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull +#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull +#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull +#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull +#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull +#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull +#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull +#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull +#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull +#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull +#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull +#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull +#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull +#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull +#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull +#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull +#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull +#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull +#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull +#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull +#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull +#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull +#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull +#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull +#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC +#define mmMME1_QM_BASE 0x7FFC0E8000ull +#define MME1_QM_MAX_OFFSET 0xD040 +#define MME1_QM_SECTION 0x38000 +#define mmMME2_ACC_BASE 0x7FFC120000ull +#define MME2_ACC_MAX_OFFSET 0x5C00 +#define MME2_ACC_SECTION 0x20000 +#define mmMME2_SBAB_BASE 0x7FFC140000ull +#define MME2_SBAB_MAX_OFFSET 0x5800 +#define MME2_SBAB_SECTION 0x1000 +#define mmMME2_PRTN_BASE 0x7FFC141000ull +#define MME2_PRTN_MAX_OFFSET 0x5000 +#define MME2_PRTN_SECTION 0x1F000 +#define mmMME2_CTRL_BASE 0x7FFC160000ull +#define MME2_CTRL_MAX_OFFSET 0xDA80 +#define MME2_CTRL_SECTION 0x8000 +#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull +#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME2_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull +#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull +#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull +#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull +#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull +#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull +#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull +#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull +#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull +#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME2_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull +#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull +#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull +#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull +#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull +#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull +#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull +#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull +#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull +#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull +#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull +#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull +#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull +#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull +#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull +#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull +#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull +#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull +#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull +#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull +#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull +#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull +#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull +#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull +#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC +#define mmMME2_QM_BASE 0x7FFC168000ull +#define MME2_QM_MAX_OFFSET 0xD040 +#define MME2_QM_SECTION 0x38000 +#define mmMME3_ACC_BASE 0x7FFC1A0000ull +#define MME3_ACC_MAX_OFFSET 0x5C00 +#define MME3_ACC_SECTION 0x20000 +#define mmMME3_SBAB_BASE 0x7FFC1C0000ull +#define MME3_SBAB_MAX_OFFSET 0x5800 +#define MME3_SBAB_SECTION 0x1000 +#define mmMME3_PRTN_BASE 0x7FFC1C1000ull +#define MME3_PRTN_MAX_OFFSET 0x5000 +#define MME3_PRTN_SECTION 0x1F000 +#define mmMME3_CTRL_BASE 0x7FFC1E0000ull +#define MME3_CTRL_MAX_OFFSET 0xDA80 +#define MME3_CTRL_SECTION 0x8000 +#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull +#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME3_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull +#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull +#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull +#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull +#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull +#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull +#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull +#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull +#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull +#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME3_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull +#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull +#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull +#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull +#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull +#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull +#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull +#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull +#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull +#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull +#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull +#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull +#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull +#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull +#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull +#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull +#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull +#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull +#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull +#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull +#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull +#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull +#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull +#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull +#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC +#define mmMME3_QM_BASE 0x7FFC1E8000ull +#define MME3_QM_MAX_OFFSET 0xD040 +#define MME3_QM_SECTION 0x18000 +#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull +#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull +#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull +#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull +#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull +#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull +#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull +#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull +#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull +#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull +#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull +#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull +#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull +#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull +#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull +#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull +#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull +#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull +#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull +#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull +#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull +#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull +#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull +#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull +#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull +#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull +#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull +#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull +#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull +#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull +#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull +#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull +#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull +#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull +#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull +#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull +#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull +#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull +#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull +#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull +#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull +#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull +#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull +#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull +#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull +#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull +#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull +#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull +#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull +#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull +#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull +#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull +#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull +#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull +#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull +#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull +#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull +#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull +#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull +#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull +#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull +#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull +#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull +#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull +#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X7_RTR_SECTION 0x7000 +#define mmSIF_RTR_0_BASE 0x7FFC300000ull +#define SIF_RTR_0_MAX_OFFSET 0x6500 +#define SIF_RTR_0_SECTION 0x6000 +#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull +#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_0_SECTION 0xA000 +#define mmSIF_RTR_1_BASE 0x7FFC310000ull +#define SIF_RTR_1_MAX_OFFSET 0x6500 +#define SIF_RTR_1_SECTION 0x6000 +#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull +#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_1_SECTION 0xA000 +#define mmSIF_RTR_2_BASE 0x7FFC320000ull +#define SIF_RTR_2_MAX_OFFSET 0x6500 +#define SIF_RTR_2_SECTION 0x6000 +#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull +#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_2_SECTION 0xA000 +#define mmSIF_RTR_3_BASE 0x7FFC330000ull +#define SIF_RTR_3_MAX_OFFSET 0x6500 +#define SIF_RTR_3_SECTION 0x6000 +#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull +#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_3_SECTION 0xA000 +#define mmSIF_RTR_4_BASE 0x7FFC340000ull +#define SIF_RTR_4_MAX_OFFSET 0x6500 +#define SIF_RTR_4_SECTION 0x6000 +#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull +#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_4_SECTION 0xA000 +#define mmSIF_RTR_5_BASE 0x7FFC350000ull +#define SIF_RTR_5_MAX_OFFSET 0x6500 +#define SIF_RTR_5_SECTION 0x6000 +#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull +#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_5_SECTION 0xA000 +#define mmSIF_RTR_6_BASE 0x7FFC360000ull +#define SIF_RTR_6_MAX_OFFSET 0x6500 +#define SIF_RTR_6_SECTION 0x6000 +#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull +#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_6_SECTION 0xA000 +#define mmSIF_RTR_7_BASE 0x7FFC370000ull +#define SIF_RTR_7_MAX_OFFSET 0x6500 +#define SIF_RTR_7_SECTION 0x6000 +#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull +#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_7_SECTION 0xA000 +#define mmNIF_RTR_0_BASE 0x7FFC380000ull +#define NIF_RTR_0_MAX_OFFSET 0x6500 +#define NIF_RTR_0_SECTION 0x6000 +#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull +#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_0_SECTION 0xA000 +#define mmNIF_RTR_1_BASE 0x7FFC390000ull +#define NIF_RTR_1_MAX_OFFSET 0x6500 +#define NIF_RTR_1_SECTION 0x6000 +#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull +#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_1_SECTION 0xA000 +#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull +#define NIF_RTR_2_MAX_OFFSET 0x6500 +#define NIF_RTR_2_SECTION 0x6000 +#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull +#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_2_SECTION 0xA000 +#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull +#define NIF_RTR_3_MAX_OFFSET 0x6500 +#define NIF_RTR_3_SECTION 0x6000 +#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull +#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_3_SECTION 0xA000 +#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull +#define NIF_RTR_4_MAX_OFFSET 0x6500 +#define NIF_RTR_4_SECTION 0x6000 +#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull +#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_4_SECTION 0xA000 +#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull +#define NIF_RTR_5_MAX_OFFSET 0x6500 +#define NIF_RTR_5_SECTION 0x6000 +#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull +#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_5_SECTION 0xA000 +#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull +#define NIF_RTR_6_MAX_OFFSET 0x6500 +#define NIF_RTR_6_SECTION 0x6000 +#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull +#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_6_SECTION 0xA000 +#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull +#define NIF_RTR_7_MAX_OFFSET 0x6500 +#define NIF_RTR_7_SECTION 0x6000 +#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull +#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_7_SECTION 0x4B000 +#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x2180 +#define CPU_CA53_CFG_SECTION 0x1000 +#define mmCPU_IF_BASE 0x7FFC442000ull +#define CPU_IF_MAX_OFFSET 0x43C0 +#define CPU_IF_SECTION 0x2000 +#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x3C000 +#define mmDMA_IF_W_S_BASE 0x7FFC480000ull +#define DMA_IF_W_S_MAX_OFFSET 0x8380 +#define DMA_IF_W_S_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull +#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull +#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 +#define mmDMA_W_PLL_BASE 0x7FFC487000ull +#define DMA_W_PLL_MAX_OFFSET 0x5200 +#define DMA_W_PLL_SECTION 0x1000 +#define mmIF_W_PLL_BASE 0x7FFC488000ull +#define IF_W_PLL_MAX_OFFSET 0x5200 +#define IF_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull +#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull +#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull +#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 +#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull +#define DMA_IF_E_S_MAX_OFFSET 0x8380 +#define DMA_IF_E_S_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull +#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull +#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 +#define mmIF_E_PLL_BASE 0x7FFC4A7000ull +#define IF_E_PLL_MAX_OFFSET 0x5200 +#define IF_E_PLL_SECTION 0x1000 +#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull +#define DMA_E_PLL_MAX_OFFSET 0x5200 +#define DMA_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull +#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull +#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull +#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 +#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull +#define DMA_IF_W_N_MAX_OFFSET 0x8380 +#define DMA_IF_W_N_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull +#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull +#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull +#define MESH_W_PLL_MAX_OFFSET 0x5200 +#define MESH_W_PLL_SECTION 0x1000 +#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull +#define SRAM_W_PLL_MAX_OFFSET 0x5200 +#define SRAM_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull +#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull +#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull +#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 +#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull +#define DMA_IF_E_N_MAX_OFFSET 0x8380 +#define DMA_IF_E_N_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull +#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull +#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull +#define MESH_E_PLL_MAX_OFFSET 0x5200 +#define MESH_E_PLL_SECTION 0x1000 +#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull +#define SRAM_E_PLL_MAX_OFFSET 0x5200 +#define SRAM_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull +#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull +#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull +#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 +#define mmDMA0_CORE_BASE 0x7FFC500000ull +#define DMA0_CORE_MAX_OFFSET 0x23C0 +#define DMA0_CORE_SECTION 0x8000 +#define mmDMA0_QM_BASE 0x7FFC508000ull +#define DMA0_QM_MAX_OFFSET 0xD040 +#define DMA0_QM_SECTION 0x18000 +#define mmDMA1_CORE_BASE 0x7FFC520000ull +#define DMA1_CORE_MAX_OFFSET 0x23C0 +#define DMA1_CORE_SECTION 0x8000 +#define mmDMA1_QM_BASE 0x7FFC528000ull +#define DMA1_QM_MAX_OFFSET 0xD040 +#define DMA1_QM_SECTION 0x18000 +#define mmDMA2_CORE_BASE 0x7FFC540000ull +#define DMA2_CORE_MAX_OFFSET 0x23C0 +#define DMA2_CORE_SECTION 0x8000 +#define mmDMA2_QM_BASE 0x7FFC548000ull +#define DMA2_QM_MAX_OFFSET 0xD040 +#define DMA2_QM_SECTION 0x18000 +#define mmDMA3_CORE_BASE 0x7FFC560000ull +#define DMA3_CORE_MAX_OFFSET 0x23C0 +#define DMA3_CORE_SECTION 0x8000 +#define mmDMA3_QM_BASE 0x7FFC568000ull +#define DMA3_QM_MAX_OFFSET 0xD040 +#define DMA3_QM_SECTION 0x18000 +#define mmDMA4_CORE_BASE 0x7FFC580000ull +#define DMA4_CORE_MAX_OFFSET 0x23C0 +#define DMA4_CORE_SECTION 0x8000 +#define mmDMA4_QM_BASE 0x7FFC588000ull +#define DMA4_QM_MAX_OFFSET 0xD040 +#define DMA4_QM_SECTION 0x18000 +#define mmDMA5_CORE_BASE 0x7FFC5A0000ull +#define DMA5_CORE_MAX_OFFSET 0x23C0 +#define DMA5_CORE_SECTION 0x8000 +#define mmDMA5_QM_BASE 0x7FFC5A8000ull +#define DMA5_QM_MAX_OFFSET 0xD040 +#define DMA5_QM_SECTION 0x18000 +#define mmDMA6_CORE_BASE 0x7FFC5C0000ull +#define DMA6_CORE_MAX_OFFSET 0x23C0 +#define DMA6_CORE_SECTION 0x8000 +#define mmDMA6_QM_BASE 0x7FFC5C8000ull +#define DMA6_QM_MAX_OFFSET 0xD040 +#define DMA6_QM_SECTION 0x18000 +#define mmDMA7_CORE_BASE 0x7FFC5E0000ull +#define DMA7_CORE_MAX_OFFSET 0x23C0 +#define DMA7_CORE_SECTION 0x8000 +#define mmDMA7_QM_BASE 0x7FFC5E8000ull +#define DMA7_QM_MAX_OFFSET 0xD040 +#define DMA7_QM_SECTION 0x18000 +#define mmHBM0_BASE 0x7FFC600000ull +#define HBM0_MAX_OFFSET 0x8F58 +#define HBM0_SECTION 0x80000 +#define mmHBM1_BASE 0x7FFC680000ull +#define HBM1_MAX_OFFSET 0x8F58 +#define HBM1_SECTION 0x80000 +#define mmHBM2_BASE 0x7FFC700000ull +#define HBM2_MAX_OFFSET 0x8F58 +#define HBM2_SECTION 0x80000 +#define mmHBM3_BASE 0x7FFC780000ull +#define HBM3_MAX_OFFSET 0x8F58 +#define HBM3_SECTION 0x80000 +#define mmGIC_BASE 0x7FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x7FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0xDF00 +#define PCIE_WRAP_SECTION 0x1000 +#define mmPCIE_DBI_BASE 0x7FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x7FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x9BC0 +#define PCIE_CORE_SECTION 0x3000 +#define mmPCIE_AUX_BASE 0x7FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x9C40 +#define PCIE_AUX_SECTION 0x9000 +#define mmPCIE_PHY_BASE 0x7FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x9640 +#define PCIE_PHY_SECTION 0x1000 +#define mmMMU_UP_BASE 0x7FFCC11000ull +#define MMU_UP_MAX_OFFSET 0x7000 +#define MMU_UP_SECTION 0x1000 +#define mmSTLB_BASE 0x7FFCC12000ull +#define STLB_MAX_OFFSET 0x8800 +#define STLB_SECTION 0x1000 +#define mmPCIE_MSI_BASE 0x7FFCC13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x2D000 +#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x7FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x2000 +#define mmPSOC_UART_0_BASE 0x7FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x7FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x7FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x7FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_EFUSE_SECTION 0x1000 +#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 +#define PSOC_GLOBAL_CONF_SECTION 0x1000 +#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x7FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1480 +#define PSOC_BTL_SECTION 0x1000 +#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1680 +#define PSOC_CS_TRACE_SECTION 0x1000 +#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x1000 +#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_DFT_EFUSE_SECTION 0x1000 +#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x8800 +#define PSOC_RPM_0_SECTION 0x1000 +#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x8800 +#define PSOC_RPM_1_SECTION 0x1000 +#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull +#define PSOC_RPM_2_MAX_OFFSET 0x8800 +#define PSOC_RPM_2_SECTION 0x1000 +#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull +#define PSOC_RPM_3_MAX_OFFSET 0x8800 +#define PSOC_RPM_3_SECTION 0x19000 +#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull +#define PSOC_CPU_PLL_MAX_OFFSET 0x5200 +#define PSOC_CPU_PLL_SECTION 0x1000 +#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull +#define PSOC_MME_PLL_MAX_OFFSET 0x5200 +#define PSOC_MME_PLL_SECTION 0x1000 +#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull +#define PSOC_PCI_PLL_MAX_OFFSET 0x5200 +#define PSOC_PCI_PLL_SECTION 0x1000 +#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull +#define PSOC_TPC_PLL_MAX_OFFSET 0x5200 +#define PSOC_TPC_PLL_SECTION 0x1000 +#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull +#define PSOC_HBM_PLL_MAX_OFFSET 0x5200 +#define PSOC_HBM_PLL_SECTION 0x1000 +#define mmPSOC_PM_BASE 0x7FFCC75000ull +#define PSOC_PM_MAX_OFFSET 0x1F00 +#define PSOC_PM_SECTION 0x1000 +#define mmPSOC_TS_BASE 0x7FFCC76000ull +#define PSOC_TS_MAX_OFFSET 0xE640 +#define PSOC_TS_SECTION 0x2000 +#define mmPSOC_PWM0_BASE 0x7FFCC78000ull +#define PSOC_PWM0_MAX_OFFSET 0x5800 +#define PSOC_PWM0_SECTION 0x1000 +#define mmPSOC_PWM1_BASE 0x7FFCC79000ull +#define PSOC_PWM1_MAX_OFFSET 0x5800 +#define PSOC_PWM1_SECTION 0x1000 +#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull +#define PSOC_PWM2_MAX_OFFSET 0x5800 +#define PSOC_PWM2_SECTION 0x1000 +#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull +#define PSOC_PWM3_MAX_OFFSET 0x5800 +#define PSOC_PWM3_SECTION 0x1000 +#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 +#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull +#define PSOC_GPIO6_MAX_OFFSET 0x1000 +#define PSOC_GPIO6_SECTION 0x3000 +#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x10003 +#define PCIE_PMA_0_SECTION 0x10000 +#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull +#define PCIE_PMA_1_MAX_OFFSET 0x10003 +#define PCIE_PMA_1_SECTION 0x10000 +#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull +#define PCIE_PMA_2_MAX_OFFSET 0x10003 +#define PCIE_PMA_2_SECTION 0x10000 +#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x10003 +#define PCIE_PMA_3_SECTION 0x10000 +#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull +#define NIC0_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH0_SECTION 0x1000 +#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull +#define NIC0_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH1_SECTION 0x1000 +#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull +#define NIC0_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH2_SECTION 0x1000 +#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull +#define NIC0_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH3_SECTION 0x1000 +#define mmNIC0_STAT_BASE 0x7FFCCC4000ull +#define NIC0_STAT_MAX_OFFSET 0x4D00 +#define NIC0_STAT_SECTION 0x1000 +#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull +#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC0_MAC_XPCS91_SECTION 0x3000 +#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull +#define NIC0_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC0_MAC_CORE_SECTION 0x1000 +#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull +#define NIC0_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC0_MAC_AUX_SECTION 0xF000 +#define mmNIC0_PHY_BASE 0x7FFCCD8000ull +#define NIC0_PHY_MAX_OFFSET 0x3400 +#define NIC0_PHY_SECTION 0x8000 +#define mmNIC0_QM0_BASE 0x7FFCCE0000ull +#define NIC0_QM0_MAX_OFFSET 0xD040 +#define NIC0_QM0_SECTION 0x2000 +#define mmNIC0_QM1_BASE 0x7FFCCE2000ull +#define NIC0_QM1_MAX_OFFSET 0xD040 +#define NIC0_QM1_SECTION 0x2000 +#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull +#define NIC0_QPC0_MAX_OFFSET 0x7140 +#define NIC0_QPC0_SECTION 0x1000 +#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull +#define NIC0_QPC1_MAX_OFFSET 0x7140 +#define NIC0_QPC1_SECTION 0x3000 +#define mmNIC0_RXB_BASE 0x7FFCCE8000ull +#define NIC0_RXB_MAX_OFFSET 0x6040 +#define NIC0_RXB_SECTION 0x1000 +#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull +#define NIC0_RXE0_MAX_OFFSET 0x2FC0 +#define NIC0_RXE0_SECTION 0x1000 +#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull +#define NIC0_RXE1_MAX_OFFSET 0x2FC0 +#define NIC0_RXE1_SECTION 0x1000 +#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull +#define NIC0_RX_GW_MAX_OFFSET 0x4540 +#define NIC0_RX_GW_SECTION 0x5000 +#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull +#define NIC0_TXS0_MAX_OFFSET 0x19C0 +#define NIC0_TXS0_SECTION 0x1000 +#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull +#define NIC0_TXS1_MAX_OFFSET 0x19C0 +#define NIC0_TXS1_SECTION 0x1000 +#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull +#define NIC0_TXE0_MAX_OFFSET 0x2040 +#define NIC0_TXE0_SECTION 0x1000 +#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull +#define NIC0_TXE1_MAX_OFFSET 0x2040 +#define NIC0_TXE1_SECTION 0x1000 +#define mmNIC0_TXB_BASE 0x7FFCCF4000ull +#define NIC0_TXB_MAX_OFFSET 0xD400 +#define NIC0_TXB_SECTION 0x1000 +#define mmNIC0_TMR_BASE 0x7FFCCF5000ull +#define NIC0_TMR_MAX_OFFSET 0x1600 +#define NIC0_TMR_SECTION 0x1000 +#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull +#define NIC0_TX_GW_MAX_OFFSET 0x1400 +#define NIC0_TX_GW_SECTION 0x2000 +#define mmNIC0_TS_BASE 0x7FFCCF8000ull +#define NIC0_TS_MAX_OFFSET 0xE640 +#define NIC0_TS_SECTION 0x1000 +#define mmNIC0_PLL_BASE 0x7FFCCF9000ull +#define NIC0_PLL_MAX_OFFSET 0x5200 +#define NIC0_PLL_SECTION 0x1000 +#define mmNIC0_PM_BASE 0x7FFCCFA000ull +#define NIC0_PM_MAX_OFFSET 0x1F00 +#define NIC0_PM_SECTION 0x6000 +#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull +#define NIC1_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH0_SECTION 0x1000 +#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull +#define NIC1_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH1_SECTION 0x1000 +#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull +#define NIC1_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH2_SECTION 0x1000 +#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull +#define NIC1_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH3_SECTION 0x1000 +#define mmNIC1_STAT_BASE 0x7FFCD04000ull +#define NIC1_STAT_MAX_OFFSET 0x4D00 +#define NIC1_STAT_SECTION 0x1000 +#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull +#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC1_MAC_XPCS91_SECTION 0x3000 +#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull +#define NIC1_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC1_MAC_CORE_SECTION 0x1000 +#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull +#define NIC1_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC1_MAC_AUX_SECTION 0xF000 +#define mmNIC1_PHY_BASE 0x7FFCD18000ull +#define NIC1_PHY_MAX_OFFSET 0x3400 +#define NIC1_PHY_SECTION 0x8000 +#define mmNIC1_QM0_BASE 0x7FFCD20000ull +#define NIC1_QM0_MAX_OFFSET 0xD040 +#define NIC1_QM0_SECTION 0x2000 +#define mmNIC1_QM1_BASE 0x7FFCD22000ull +#define NIC1_QM1_MAX_OFFSET 0xD040 +#define NIC1_QM1_SECTION 0x2000 +#define mmNIC1_QPC0_BASE 0x7FFCD24000ull +#define NIC1_QPC0_MAX_OFFSET 0x7140 +#define NIC1_QPC0_SECTION 0x1000 +#define mmNIC1_QPC1_BASE 0x7FFCD25000ull +#define NIC1_QPC1_MAX_OFFSET 0x7140 +#define NIC1_QPC1_SECTION 0x3000 +#define mmNIC1_RXB_BASE 0x7FFCD28000ull +#define NIC1_RXB_MAX_OFFSET 0x6040 +#define NIC1_RXB_SECTION 0x1000 +#define mmNIC1_RXE0_BASE 0x7FFCD29000ull +#define NIC1_RXE0_MAX_OFFSET 0x2FC0 +#define NIC1_RXE0_SECTION 0x1000 +#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull +#define NIC1_RXE1_MAX_OFFSET 0x2FC0 +#define NIC1_RXE1_SECTION 0x1000 +#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull +#define NIC1_RX_GW_MAX_OFFSET 0x4540 +#define NIC1_RX_GW_SECTION 0x5000 +#define mmNIC1_TXS0_BASE 0x7FFCD30000ull +#define NIC1_TXS0_MAX_OFFSET 0x19C0 +#define NIC1_TXS0_SECTION 0x1000 +#define mmNIC1_TXS1_BASE 0x7FFCD31000ull +#define NIC1_TXS1_MAX_OFFSET 0x19C0 +#define NIC1_TXS1_SECTION 0x1000 +#define mmNIC1_TXE0_BASE 0x7FFCD32000ull +#define NIC1_TXE0_MAX_OFFSET 0x2040 +#define NIC1_TXE0_SECTION 0x1000 +#define mmNIC1_TXE1_BASE 0x7FFCD33000ull +#define NIC1_TXE1_MAX_OFFSET 0x2040 +#define NIC1_TXE1_SECTION 0x1000 +#define mmNIC1_TXB_BASE 0x7FFCD34000ull +#define NIC1_TXB_MAX_OFFSET 0xD400 +#define NIC1_TXB_SECTION 0x1000 +#define mmNIC1_TMR_BASE 0x7FFCD35000ull +#define NIC1_TMR_MAX_OFFSET 0x1600 +#define NIC1_TMR_SECTION 0x1000 +#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull +#define NIC1_TX_GW_MAX_OFFSET 0x1400 +#define NIC1_TX_GW_SECTION 0x2000 +#define mmNIC1_TS_BASE 0x7FFCD38000ull +#define NIC1_TS_MAX_OFFSET 0xE640 +#define NIC1_TS_SECTION 0x1000 +#define mmNIC1_PLL_BASE 0x7FFCD39000ull +#define NIC1_PLL_MAX_OFFSET 0x5200 +#define NIC1_PLL_SECTION 0x1000 +#define mmNIC1_PM_BASE 0x7FFCD3A000ull +#define NIC1_PM_MAX_OFFSET 0x1F00 +#define NIC1_PM_SECTION 0x6000 +#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull +#define NIC2_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH0_SECTION 0x1000 +#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull +#define NIC2_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH1_SECTION 0x1000 +#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull +#define NIC2_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH2_SECTION 0x1000 +#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull +#define NIC2_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH3_SECTION 0x1000 +#define mmNIC2_STAT_BASE 0x7FFCD44000ull +#define NIC2_STAT_MAX_OFFSET 0x4D00 +#define NIC2_STAT_SECTION 0x1000 +#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull +#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC2_MAC_XPCS91_SECTION 0x3000 +#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull +#define NIC2_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC2_MAC_CORE_SECTION 0x1000 +#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull +#define NIC2_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC2_MAC_AUX_SECTION 0xF000 +#define mmNIC2_PHY_BASE 0x7FFCD58000ull +#define NIC2_PHY_MAX_OFFSET 0x3400 +#define NIC2_PHY_SECTION 0x8000 +#define mmNIC2_QM0_BASE 0x7FFCD60000ull +#define NIC2_QM0_MAX_OFFSET 0xD040 +#define NIC2_QM0_SECTION 0x2000 +#define mmNIC2_QM1_BASE 0x7FFCD62000ull +#define NIC2_QM1_MAX_OFFSET 0xD040 +#define NIC2_QM1_SECTION 0x2000 +#define mmNIC2_QPC0_BASE 0x7FFCD64000ull +#define NIC2_QPC0_MAX_OFFSET 0x7140 +#define NIC2_QPC0_SECTION 0x1000 +#define mmNIC2_QPC1_BASE 0x7FFCD65000ull +#define NIC2_QPC1_MAX_OFFSET 0x7140 +#define NIC2_QPC1_SECTION 0x3000 +#define mmNIC2_RXB_BASE 0x7FFCD68000ull +#define NIC2_RXB_MAX_OFFSET 0x6040 +#define NIC2_RXB_SECTION 0x1000 +#define mmNIC2_RXE0_BASE 0x7FFCD69000ull +#define NIC2_RXE0_MAX_OFFSET 0x2FC0 +#define NIC2_RXE0_SECTION 0x1000 +#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull +#define NIC2_RXE1_MAX_OFFSET 0x2FC0 +#define NIC2_RXE1_SECTION 0x1000 +#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull +#define NIC2_RX_GW_MAX_OFFSET 0x4540 +#define NIC2_RX_GW_SECTION 0x5000 +#define mmNIC2_TXS0_BASE 0x7FFCD70000ull +#define NIC2_TXS0_MAX_OFFSET 0x19C0 +#define NIC2_TXS0_SECTION 0x1000 +#define mmNIC2_TXS1_BASE 0x7FFCD71000ull +#define NIC2_TXS1_MAX_OFFSET 0x19C0 +#define NIC2_TXS1_SECTION 0x1000 +#define mmNIC2_TXE0_BASE 0x7FFCD72000ull +#define NIC2_TXE0_MAX_OFFSET 0x2040 +#define NIC2_TXE0_SECTION 0x1000 +#define mmNIC2_TXE1_BASE 0x7FFCD73000ull +#define NIC2_TXE1_MAX_OFFSET 0x2040 +#define NIC2_TXE1_SECTION 0x1000 +#define mmNIC2_TXB_BASE 0x7FFCD74000ull +#define NIC2_TXB_MAX_OFFSET 0xD400 +#define NIC2_TXB_SECTION 0x1000 +#define mmNIC2_TMR_BASE 0x7FFCD75000ull +#define NIC2_TMR_MAX_OFFSET 0x1600 +#define NIC2_TMR_SECTION 0x1000 +#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull +#define NIC2_TX_GW_MAX_OFFSET 0x1400 +#define NIC2_TX_GW_SECTION 0x2000 +#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull +#define NIC2_HBM_PLL_MAX_OFFSET 0x5200 +#define NIC2_HBM_PLL_SECTION 0x1000 +#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull +#define NIC2_MME_PLL_MAX_OFFSET 0x5200 +#define NIC2_MME_PLL_SECTION 0x1000 +#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull +#define NIC2_TPC_PLL_MAX_OFFSET 0x5200 +#define NIC2_TPC_PLL_SECTION 0x6000 +#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull +#define NIC3_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH0_SECTION 0x1000 +#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull +#define NIC3_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH1_SECTION 0x1000 +#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull +#define NIC3_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH2_SECTION 0x1000 +#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull +#define NIC3_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH3_SECTION 0x1000 +#define mmNIC3_STAT_BASE 0x7FFCD84000ull +#define NIC3_STAT_MAX_OFFSET 0x4D00 +#define NIC3_STAT_SECTION 0x1000 +#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull +#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC3_MAC_XPCS91_SECTION 0x3000 +#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull +#define NIC3_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC3_MAC_CORE_SECTION 0x1000 +#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull +#define NIC3_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC3_MAC_AUX_SECTION 0xF000 +#define mmNIC3_PHY_BASE 0x7FFCD98000ull +#define NIC3_PHY_MAX_OFFSET 0x3400 +#define NIC3_PHY_SECTION 0x8000 +#define mmNIC3_QM0_BASE 0x7FFCDA0000ull +#define NIC3_QM0_MAX_OFFSET 0xD040 +#define NIC3_QM0_SECTION 0x2000 +#define mmNIC3_QM1_BASE 0x7FFCDA2000ull +#define NIC3_QM1_MAX_OFFSET 0xD040 +#define NIC3_QM1_SECTION 0x2000 +#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull +#define NIC3_QPC0_MAX_OFFSET 0x7140 +#define NIC3_QPC0_SECTION 0x1000 +#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull +#define NIC3_QPC1_MAX_OFFSET 0x7140 +#define NIC3_QPC1_SECTION 0x3000 +#define mmNIC3_RXB_BASE 0x7FFCDA8000ull +#define NIC3_RXB_MAX_OFFSET 0x6040 +#define NIC3_RXB_SECTION 0x1000 +#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull +#define NIC3_RXE0_MAX_OFFSET 0x2FC0 +#define NIC3_RXE0_SECTION 0x1000 +#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull +#define NIC3_RXE1_MAX_OFFSET 0x2FC0 +#define NIC3_RXE1_SECTION 0x1000 +#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull +#define NIC3_RX_GW_MAX_OFFSET 0x4540 +#define NIC3_RX_GW_SECTION 0x5000 +#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull +#define NIC3_TXS0_MAX_OFFSET 0x19C0 +#define NIC3_TXS0_SECTION 0x1000 +#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull +#define NIC3_TXS1_MAX_OFFSET 0x19C0 +#define NIC3_TXS1_SECTION 0x1000 +#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull +#define NIC3_TXE0_MAX_OFFSET 0x2040 +#define NIC3_TXE0_SECTION 0x1000 +#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull +#define NIC3_TXE1_MAX_OFFSET 0x2040 +#define NIC3_TXE1_SECTION 0x1000 +#define mmNIC3_TXB_BASE 0x7FFCDB4000ull +#define NIC3_TXB_MAX_OFFSET 0xD400 +#define NIC3_TXB_SECTION 0x1000 +#define mmNIC3_TMR_BASE 0x7FFCDB5000ull +#define NIC3_TMR_MAX_OFFSET 0x1600 +#define NIC3_TMR_SECTION 0x1000 +#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull +#define NIC3_TX_GW_MAX_OFFSET 0x1400 +#define NIC3_TX_GW_SECTION 0x2000 +#define mmNIC3_TS_BASE 0x7FFCDB8000ull +#define NIC3_TS_MAX_OFFSET 0xE640 +#define NIC3_TS_SECTION 0x2000 +#define mmNIC3_PM_BASE 0x7FFCDBA000ull +#define NIC3_PM_MAX_OFFSET 0x1F00 +#define NIC3_PM_SECTION 0x6000 +#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull +#define NIC4_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH0_SECTION 0x1000 +#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull +#define NIC4_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH1_SECTION 0x1000 +#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull +#define NIC4_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH2_SECTION 0x1000 +#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull +#define NIC4_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH3_SECTION 0x1000 +#define mmNIC4_STAT_BASE 0x7FFCDC4000ull +#define NIC4_STAT_MAX_OFFSET 0x4D00 +#define NIC4_STAT_SECTION 0x1000 +#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull +#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC4_MAC_XPCS91_SECTION 0x3000 +#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull +#define NIC4_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC4_MAC_CORE_SECTION 0x1000 +#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull +#define NIC4_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC4_MAC_AUX_SECTION 0xF000 +#define mmNIC4_PHY_BASE 0x7FFCDD8000ull +#define NIC4_PHY_MAX_OFFSET 0x3400 +#define NIC4_PHY_SECTION 0x8000 +#define mmNIC4_QM0_BASE 0x7FFCDE0000ull +#define NIC4_QM0_MAX_OFFSET 0xD040 +#define NIC4_QM0_SECTION 0x2000 +#define mmNIC4_QM1_BASE 0x7FFCDE2000ull +#define NIC4_QM1_MAX_OFFSET 0xD040 +#define NIC4_QM1_SECTION 0x2000 +#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull +#define NIC4_QPC0_MAX_OFFSET 0x7140 +#define NIC4_QPC0_SECTION 0x1000 +#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull +#define NIC4_QPC1_MAX_OFFSET 0x7140 +#define NIC4_QPC1_SECTION 0x3000 +#define mmNIC4_RXB_BASE 0x7FFCDE8000ull +#define NIC4_RXB_MAX_OFFSET 0x6040 +#define NIC4_RXB_SECTION 0x1000 +#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull +#define NIC4_RXE0_MAX_OFFSET 0x2FC0 +#define NIC4_RXE0_SECTION 0x1000 +#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull +#define NIC4_RXE1_MAX_OFFSET 0x2FC0 +#define NIC4_RXE1_SECTION 0x1000 +#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull +#define NIC4_RX_GW_MAX_OFFSET 0x4540 +#define NIC4_RX_GW_SECTION 0x5000 +#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull +#define NIC4_TXS0_MAX_OFFSET 0x19C0 +#define NIC4_TXS0_SECTION 0x1000 +#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull +#define NIC4_TXS1_MAX_OFFSET 0x19C0 +#define NIC4_TXS1_SECTION 0x1000 +#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull +#define NIC4_TXE0_MAX_OFFSET 0x2040 +#define NIC4_TXE0_SECTION 0x1000 +#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull +#define NIC4_TXE1_MAX_OFFSET 0x2040 +#define NIC4_TXE1_SECTION 0x1000 +#define mmNIC4_TXB_BASE 0x7FFCDF4000ull +#define NIC4_TXB_MAX_OFFSET 0xD400 +#define NIC4_TXB_SECTION 0x1000 +#define mmNIC4_TMR_BASE 0x7FFCDF5000ull +#define NIC4_TMR_MAX_OFFSET 0x1600 +#define NIC4_TMR_SECTION 0x1000 +#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull +#define NIC4_TX_GW_MAX_OFFSET 0x1400 +#define NIC4_TX_GW_SECTION 0x10000 +#define mmTPC0_CFG_BASE 0x7FFCE06000ull +#define TPC0_CFG_MAX_OFFSET 0xE400 +#define TPC0_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull +#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull +#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull +#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull +#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull +#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull +#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull +#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull +#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull +#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull +#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull +#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull +#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull +#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull +#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull +#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull +#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull +#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull +#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull +#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull +#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull +#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull +#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull +#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull +#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull +#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull +#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull +#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull +#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull +#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull +#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull +#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull +#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull +#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull +#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull +#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull +#define QM_TPC0_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_CFG_SECTION 0x2780 +#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull +#define TPC0_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC0_E2E_CRED_SECTION 0x1000 +#define mmTPC0_QM_BASE 0x7FFCE08000ull +#define TPC0_QM_MAX_OFFSET 0xD040 +#define TPC0_QM_SECTION 0x3E000 +#define mmTPC1_CFG_BASE 0x7FFCE46000ull +#define TPC1_CFG_MAX_OFFSET 0xE400 +#define TPC1_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull +#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull +#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull +#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull +#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull +#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull +#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull +#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull +#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull +#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull +#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull +#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull +#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull +#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull +#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull +#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull +#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull +#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull +#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull +#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull +#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull +#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull +#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull +#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull +#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull +#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull +#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull +#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull +#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull +#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull +#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull +#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull +#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull +#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull +#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull +#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull +#define QM_TPC1_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_CFG_SECTION 0x2780 +#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull +#define TPC1_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC1_E2E_CRED_SECTION 0x1000 +#define mmTPC1_QM_BASE 0x7FFCE48000ull +#define TPC1_QM_MAX_OFFSET 0xD040 +#define TPC1_QM_SECTION 0x3E000 +#define mmTPC2_CFG_BASE 0x7FFCE86000ull +#define TPC2_CFG_MAX_OFFSET 0xE400 +#define TPC2_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull +#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull +#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull +#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull +#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull +#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull +#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull +#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull +#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull +#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull +#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull +#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull +#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull +#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull +#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull +#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull +#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull +#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull +#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull +#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull +#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull +#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull +#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull +#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull +#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull +#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull +#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull +#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull +#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull +#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull +#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull +#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull +#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull +#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull +#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull +#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull +#define QM_TPC2_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_CFG_SECTION 0x2780 +#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull +#define TPC2_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC2_E2E_CRED_SECTION 0x1000 +#define mmTPC2_QM_BASE 0x7FFCE88000ull +#define TPC2_QM_MAX_OFFSET 0xD040 +#define TPC2_QM_SECTION 0x3E000 +#define mmTPC3_CFG_BASE 0x7FFCEC6000ull +#define TPC3_CFG_MAX_OFFSET 0xE400 +#define TPC3_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull +#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull +#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull +#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull +#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull +#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull +#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull +#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull +#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull +#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull +#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull +#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull +#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull +#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull +#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull +#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull +#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull +#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull +#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull +#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull +#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull +#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull +#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull +#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull +#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull +#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull +#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull +#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull +#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull +#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull +#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull +#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull +#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull +#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull +#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull +#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull +#define QM_TPC3_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_CFG_SECTION 0x2780 +#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull +#define TPC3_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC3_E2E_CRED_SECTION 0x1000 +#define mmTPC3_QM_BASE 0x7FFCEC8000ull +#define TPC3_QM_MAX_OFFSET 0xD040 +#define TPC3_QM_SECTION 0x3E000 +#define mmTPC4_CFG_BASE 0x7FFCF06000ull +#define TPC4_CFG_MAX_OFFSET 0xE400 +#define TPC4_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull +#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull +#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull +#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull +#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull +#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull +#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull +#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull +#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull +#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull +#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull +#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull +#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull +#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull +#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull +#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull +#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull +#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull +#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull +#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull +#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull +#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull +#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull +#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull +#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull +#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull +#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull +#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull +#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull +#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull +#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull +#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull +#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull +#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull +#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull +#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull +#define QM_TPC4_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_CFG_SECTION 0x2780 +#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull +#define TPC4_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC4_E2E_CRED_SECTION 0x1000 +#define mmTPC4_QM_BASE 0x7FFCF08000ull +#define TPC4_QM_MAX_OFFSET 0xD040 +#define TPC4_QM_SECTION 0x3E000 +#define mmTPC5_CFG_BASE 0x7FFCF46000ull +#define TPC5_CFG_MAX_OFFSET 0xE400 +#define TPC5_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull +#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull +#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull +#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull +#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull +#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull +#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull +#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull +#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull +#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull +#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull +#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull +#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull +#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull +#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull +#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull +#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull +#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull +#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull +#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull +#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull +#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull +#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull +#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull +#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull +#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull +#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull +#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull +#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull +#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull +#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull +#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull +#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull +#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull +#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull +#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull +#define QM_TPC5_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_CFG_SECTION 0x2780 +#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull +#define TPC5_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC5_E2E_CRED_SECTION 0x1000 +#define mmTPC5_QM_BASE 0x7FFCF48000ull +#define TPC5_QM_MAX_OFFSET 0xD040 +#define TPC5_QM_SECTION 0x3E000 +#define mmTPC6_CFG_BASE 0x7FFCF86000ull +#define TPC6_CFG_MAX_OFFSET 0xE400 +#define TPC6_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull +#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull +#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull +#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull +#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull +#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull +#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull +#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull +#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull +#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull +#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull +#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull +#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull +#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull +#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull +#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull +#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull +#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull +#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull +#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull +#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull +#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull +#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull +#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull +#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull +#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull +#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull +#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull +#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull +#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull +#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull +#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull +#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull +#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull +#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull +#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull +#define QM_TPC6_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_CFG_SECTION 0x2780 +#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull +#define TPC6_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC6_E2E_CRED_SECTION 0x1000 +#define mmTPC6_QM_BASE 0x7FFCF88000ull +#define TPC6_QM_MAX_OFFSET 0xD040 +#define TPC6_QM_SECTION 0x3E000 +#define mmTPC7_CFG_BASE 0x7FFCFC6000ull +#define TPC7_CFG_MAX_OFFSET 0xE400 +#define TPC7_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull +#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull +#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull +#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull +#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull +#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull +#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull +#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull +#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull +#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull +#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull +#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull +#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull +#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull +#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull +#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull +#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull +#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull +#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull +#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull +#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull +#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull +#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull +#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull +#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull +#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull +#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull +#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull +#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull +#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull +#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull +#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull +#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull +#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull +#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull +#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull +#define QM_TPC7_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_CFG_SECTION 0x2780 +#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull +#define TPC7_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC7_E2E_CRED_SECTION 0x1000 +#define mmTPC7_QM_BASE 0x7FFCFC8000ull +#define TPC7_QM_MAX_OFFSET 0xD040 +#define TPC7_QM_SECTION 0x1038000 +#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull +#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_S_ROM_TABLE_SECTION 0x21000 +#define mmMME0_ACC_STM_BASE 0x7FFE021000ull +#define MME0_ACC_STM_MAX_OFFSET 0x1000 +#define MME0_ACC_STM_SECTION 0x1000 +#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull +#define MME0_ACC_CTI_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI_SECTION 0x1000 +#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull +#define MME0_ACC_ETF_MAX_OFFSET 0x1000 +#define MME0_ACC_ETF_SECTION 0x1000 +#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull +#define MME0_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME0_ACC_SPMU_SECTION 0x1000 +#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull +#define MME0_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI0_SECTION 0x1000 +#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull +#define MME0_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI1_SECTION 0x1000 +#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull +#define MME0_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME0_ACC_BMON0_SECTION 0x9000 +#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull +#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME0_ACC_FUNNEL_SECTION 0x11000 +#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull +#define MME0_SBAB_STM_MAX_OFFSET 0x1000 +#define MME0_SBAB_STM_SECTION 0x1000 +#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull +#define MME0_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI_SECTION 0x1000 +#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull +#define MME0_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME0_SBAB_ETF_SECTION 0x1000 +#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull +#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME0_SBAB_SPMU_SECTION 0x1000 +#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull +#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI0_SECTION 0x1000 +#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull +#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI1_SECTION 0x1000 +#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull +#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON0_SECTION 0x1000 +#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull +#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON1_SECTION 0x19000 +#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull +#define MME0_CTRL_STM_MAX_OFFSET 0x1000 +#define MME0_CTRL_STM_SECTION 0x1000 +#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull +#define MME0_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI_SECTION 0x1000 +#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull +#define MME0_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME0_CTRL_ETF_SECTION 0x1000 +#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull +#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME0_CTRL_SPMU_SECTION 0x1000 +#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull +#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI0_SECTION 0x1000 +#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull +#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI1_SECTION 0x1000 +#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull +#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON0_SECTION 0x1000 +#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull +#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON1_SECTION 0x39000 +#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull +#define MME1_ACC_STM_MAX_OFFSET 0x1000 +#define MME1_ACC_STM_SECTION 0x1000 +#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull +#define MME1_ACC_CTI_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI_SECTION 0x1000 +#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull +#define MME1_ACC_ETF_MAX_OFFSET 0x1000 +#define MME1_ACC_ETF_SECTION 0x1000 +#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull +#define MME1_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME1_ACC_SPMU_SECTION 0x1000 +#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull +#define MME1_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI0_SECTION 0x1000 +#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull +#define MME1_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI1_SECTION 0x1000 +#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull +#define MME1_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME1_ACC_BMON0_SECTION 0x9000 +#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull +#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME1_ACC_FUNNEL_SECTION 0x11000 +#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull +#define MME1_SBAB_STM_MAX_OFFSET 0x1000 +#define MME1_SBAB_STM_SECTION 0x1000 +#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull +#define MME1_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI_SECTION 0x1000 +#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull +#define MME1_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME1_SBAB_ETF_SECTION 0x1000 +#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull +#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME1_SBAB_SPMU_SECTION 0x1000 +#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull +#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI0_SECTION 0x1000 +#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull +#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI1_SECTION 0x1000 +#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull +#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON0_SECTION 0x1000 +#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull +#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON1_SECTION 0x19000 +#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull +#define MME1_CTRL_STM_MAX_OFFSET 0x1000 +#define MME1_CTRL_STM_SECTION 0x1000 +#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull +#define MME1_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI_SECTION 0x1000 +#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull +#define MME1_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME1_CTRL_ETF_SECTION 0x1000 +#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull +#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME1_CTRL_SPMU_SECTION 0x1000 +#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull +#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI0_SECTION 0x1000 +#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull +#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI1_SECTION 0x1000 +#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull +#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON0_SECTION 0x1000 +#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull +#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON1_SECTION 0x18000 +#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull +#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_N_ROM_TABLE_SECTION 0x21000 +#define mmMME2_ACC_STM_BASE 0x7FFE121000ull +#define MME2_ACC_STM_MAX_OFFSET 0x1000 +#define MME2_ACC_STM_SECTION 0x1000 +#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull +#define MME2_ACC_CTI_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI_SECTION 0x1000 +#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull +#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 +#define MME2_MME2_ACC_ETF_SECTION 0x1000 +#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull +#define MME2_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME2_ACC_SPMU_SECTION 0x1000 +#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull +#define MME2_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI0_SECTION 0x1000 +#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull +#define MME2_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI1_SECTION 0x1000 +#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull +#define MME2_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME2_ACC_BMON0_SECTION 0x9000 +#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull +#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME2_ACC_FUNNEL_SECTION 0x11000 +#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull +#define MME2_SBAB_STM_MAX_OFFSET 0x1000 +#define MME2_SBAB_STM_SECTION 0x1000 +#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull +#define MME2_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI_SECTION 0x1000 +#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull +#define MME2_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME2_SBAB_ETF_SECTION 0x1000 +#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull +#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME2_SBAB_SPMU_SECTION 0x1000 +#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull +#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI0_SECTION 0x1000 +#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull +#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI1_SECTION 0x1000 +#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull +#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON0_SECTION 0x1000 +#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull +#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON1_SECTION 0x19000 +#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull +#define MME2_CTRL_STM_MAX_OFFSET 0x1000 +#define MME2_CTRL_STM_SECTION 0x1000 +#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull +#define MME2_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI_SECTION 0x1000 +#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull +#define MME2_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME2_CTRL_ETF_SECTION 0x1000 +#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull +#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME2_CTRL_SPMU_SECTION 0x1000 +#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull +#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI0_SECTION 0x1000 +#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull +#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI1_SECTION 0x1000 +#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull +#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON0_SECTION 0x1000 +#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull +#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON1_SECTION 0x39000 +#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull +#define MME3_ACC_STM_MAX_OFFSET 0x1000 +#define MME3_ACC_STM_SECTION 0x1000 +#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull +#define MME3_ACC_CTI_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI_SECTION 0x1000 +#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull +#define MME3_ACC_ETF_MAX_OFFSET 0x1000 +#define MME3_ACC_ETF_SECTION 0x1000 +#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull +#define MME3_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME3_ACC_SPMU_SECTION 0x1000 +#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull +#define MME3_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI0_SECTION 0x1000 +#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull +#define MME3_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI1_SECTION 0x1000 +#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull +#define MME3_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME3_ACC_BMON0_SECTION 0x9000 +#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull +#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME3_ACC_FUNNEL_SECTION 0x11000 +#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull +#define MME3_SBAB_STM_MAX_OFFSET 0x1000 +#define MME3_SBAB_STM_SECTION 0x1000 +#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull +#define MME3_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI_SECTION 0x1000 +#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull +#define MME3_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME3_SBAB_ETF_SECTION 0x1000 +#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull +#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME3_SBAB_SPMU_SECTION 0x1000 +#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull +#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI0_SECTION 0x1000 +#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull +#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI1_SECTION 0x1000 +#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull +#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON0_SECTION 0x1000 +#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull +#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON1_SECTION 0x19000 +#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull +#define MME3_CTRL_STM_MAX_OFFSET 0x1000 +#define MME3_CTRL_STM_SECTION 0x1000 +#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull +#define MME3_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI_SECTION 0x1000 +#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull +#define MME3_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME3_CTRL_ETF_SECTION 0x1000 +#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull +#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME3_CTRL_SPMU_SECTION 0x1000 +#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull +#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI0_SECTION 0x1000 +#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull +#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI1_SECTION 0x1000 +#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull +#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON0_SECTION 0x1000 +#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull +#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON1_SECTION 0x18000 +#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull +#define IC_ROM_TABLE_MAX_OFFSET 0x1000 +#define IC_ROM_TABLE_SECTION 0x1000 +#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull +#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull +#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull +#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull +#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull +#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull +#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull +#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull +#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull +#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull +#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull +#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull +#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull +#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull +#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull +#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull +#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull +#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull +#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull +#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull +#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull +#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull +#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull +#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull +#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull +#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull +#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull +#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull +#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull +#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull +#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull +#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull +#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 +#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull +#define IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define IF_ROM_TABLE_SECTION 0x1000 +#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull +#define SIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_0_SECTION 0x10000 +#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull +#define SIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_1_SECTION 0x10000 +#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull +#define SIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_2_SECTION 0x10000 +#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull +#define SIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_3_SECTION 0x10000 +#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull +#define SIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_4_SECTION 0x10000 +#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull +#define SIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_5_SECTION 0x10000 +#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull +#define SIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_6_SECTION 0x10000 +#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull +#define SIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_7_SECTION 0x10000 +#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull +#define NIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_0_SECTION 0x10000 +#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull +#define NIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_1_SECTION 0x10000 +#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull +#define NIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_2_SECTION 0x10000 +#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull +#define NIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_3_SECTION 0x10000 +#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull +#define NIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_4_SECTION 0x10000 +#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull +#define NIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_5_SECTION 0x10000 +#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull +#define NIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_6_SECTION 0x10000 +#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull +#define NIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_7_SECTION 0xF000 +#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull +#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_IF_ROM_TABLE_SECTION 0x1000 +#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull +#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_STM_SECTION 0x1000 +#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull +#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull +#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_ETF_SECTION 0x2000 +#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull +#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull +#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull +#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull +#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull +#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull +#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull +#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull +#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull +#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_STM_SECTION 0x1000 +#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull +#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull +#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_ETF_SECTION 0x2000 +#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull +#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull +#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull +#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull +#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull +#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull +#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull +#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull +#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull +#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_STM_SECTION 0x1000 +#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull +#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull +#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_ETF_SECTION 0x2000 +#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull +#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull +#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull +#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull +#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull +#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull +#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull +#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull +#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull +#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_STM_SECTION 0x1000 +#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull +#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull +#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_ETF_SECTION 0x2000 +#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull +#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull +#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull +#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull +#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull +#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull +#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull +#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull +#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_FUNNEL_SECTION 0x11000 +#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull +#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 +#define CPU_ROM_TABLE_SECTION 0x1000 +#define mmCPU_ETF_0_BASE 0x7FFE481000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x7FFE482000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x7FFE484000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x7FFE485000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x7FFE486000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x7FFE489000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x76000 +#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull +#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_ROM_TABLE_SECTION 0x1000 +#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull +#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_STM_SECTION 0x1000 +#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull +#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull +#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull +#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull +#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull +#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull +#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_0_SECTION 0x1000 +#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull +#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_1_SECTION 0x19000 +#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull +#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_STM_SECTION 0x1000 +#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull +#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull +#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull +#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull +#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull +#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull +#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_0_SECTION 0x1000 +#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull +#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_1_SECTION 0x19000 +#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull +#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_STM_SECTION 0x1000 +#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull +#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull +#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull +#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull +#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull +#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull +#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_0_SECTION 0x1000 +#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull +#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_1_SECTION 0x19000 +#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull +#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_STM_SECTION 0x1000 +#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull +#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull +#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull +#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull +#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull +#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull +#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_0_SECTION 0x1000 +#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull +#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_1_SECTION 0x19000 +#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull +#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_STM_SECTION 0x1000 +#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull +#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull +#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull +#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull +#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull +#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull +#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_0_SECTION 0x1000 +#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull +#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_1_SECTION 0x19000 +#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull +#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_STM_SECTION 0x1000 +#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull +#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull +#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull +#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull +#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull +#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull +#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_0_SECTION 0x1000 +#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull +#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_1_SECTION 0x19000 +#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull +#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_STM_SECTION 0x1000 +#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull +#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull +#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull +#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull +#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull +#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull +#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_0_SECTION 0x1000 +#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull +#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_1_SECTION 0x19000 +#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull +#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_STM_SECTION 0x1000 +#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull +#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull +#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull +#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull +#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull +#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull +#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_0_SECTION 0x1000 +#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull +#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_1_SECTION 0x18000 +#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull +#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull +#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull +#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull +#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 +#define mmCA53_BASE 0x7FFE800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x7FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x7FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x7FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x1000 +#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull +#define PCIE_FUNNEL_MAX_OFFSET 0x1000 +#define PCIE_FUNNEL_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x7000 +#define mmMMU_CS_STM_BASE 0x7FFEC11000ull +#define MMU_CS_STM_MAX_OFFSET 0x1000 +#define MMU_CS_STM_SECTION 0x1000 +#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull +#define MMU_CS_CTI_MAX_OFFSET 0x1000 +#define MMU_CS_CTI_SECTION 0x1000 +#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull +#define MMU_CS_ETF_MAX_OFFSET 0x1000 +#define MMU_CS_ETF_SECTION 0x1000 +#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull +#define MMU_CS_SPMU_MAX_OFFSET 0x1000 +#define MMU_CS_SPMU_SECTION 0x1000 +#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull +#define MMU_BMON_CTI_MAX_OFFSET 0x1000 +#define MMU_BMON_CTI_SECTION 0x1000 +#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull +#define MMU_USER_CTI_MAX_OFFSET 0x1000 +#define MMU_USER_CTI_SECTION 0x1000 +#define mmMMU_BMON_0_BASE 0x7FFEC17000ull +#define MMU_BMON_0_MAX_OFFSET 0x1000 +#define MMU_BMON_0_SECTION 0x1000 +#define mmMMU_BMON_1_BASE 0x7FFEC18000ull +#define MMU_BMON_1_MAX_OFFSET 0x1000 +#define MMU_BMON_1_SECTION 0x28000 +#define mmPSOC_CTI_BASE 0x7FFEC40000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x7FFEC41000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x7FFEC43000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x7FFEC44000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xB000 +#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x70000 +#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull +#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC0_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull +#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC0_DBG_SECTION 0x1000 +#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull +#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC0_DBG_SECTION 0x1000 +#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull +#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull +#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC0_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull +#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC0_DBG_SECTION 0xB000 +#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull +#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC0_DBG_SECTION 0x1000 +#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull +#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull +#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull +#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull +#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC0_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull +#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull +#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC0_DBG_SECTION 0x1000 +#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull +#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC0_DBG_SECTION 0x1000 +#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull +#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC0_DBG_SECTION 0x1000 +#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull +#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC0_DBG_SECTION 0x1000 +#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull +#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC0_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull +#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC0_DBG_SECTION 0x1F000 +#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull +#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC1_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull +#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC1_DBG_SECTION 0x1000 +#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull +#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC1_DBG_SECTION 0x1000 +#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull +#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull +#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC1_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull +#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC1_DBG_SECTION 0xB000 +#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull +#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC1_DBG_SECTION 0x1000 +#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull +#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull +#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull +#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull +#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC1_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull +#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull +#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC1_DBG_SECTION 0x1000 +#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull +#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC1_DBG_SECTION 0x1000 +#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull +#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC1_DBG_SECTION 0x1000 +#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull +#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC1_DBG_SECTION 0x1000 +#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull +#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC1_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull +#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC1_DBG_SECTION 0x1F000 +#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull +#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC2_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull +#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC2_DBG_SECTION 0x1000 +#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull +#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC2_DBG_SECTION 0x1000 +#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull +#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull +#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC2_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull +#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC2_DBG_SECTION 0xB000 +#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull +#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC2_DBG_SECTION 0x1000 +#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull +#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull +#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull +#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull +#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC2_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull +#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull +#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC2_DBG_SECTION 0x1000 +#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull +#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC2_DBG_SECTION 0x1000 +#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull +#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC2_DBG_SECTION 0x1000 +#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull +#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC2_DBG_SECTION 0x1000 +#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull +#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC2_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull +#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC2_DBG_SECTION 0x1F000 +#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull +#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC3_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull +#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC3_DBG_SECTION 0x1000 +#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull +#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC3_DBG_SECTION 0x1000 +#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull +#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull +#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC3_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull +#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC3_DBG_SECTION 0xB000 +#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull +#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC3_DBG_SECTION 0x1000 +#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull +#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull +#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull +#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull +#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC3_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull +#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull +#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC3_DBG_SECTION 0x1000 +#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull +#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC3_DBG_SECTION 0x1000 +#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull +#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC3_DBG_SECTION 0x1000 +#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull +#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC3_DBG_SECTION 0x1000 +#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull +#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC3_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull +#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC3_DBG_SECTION 0x1F000 +#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull +#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC4_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull +#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC4_DBG_SECTION 0x1000 +#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull +#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC4_DBG_SECTION 0x1000 +#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull +#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull +#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC4_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull +#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC4_DBG_SECTION 0xB000 +#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull +#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC4_DBG_SECTION 0x1000 +#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull +#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull +#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull +#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull +#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC4_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull +#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull +#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC4_DBG_SECTION 0x1000 +#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull +#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC4_DBG_SECTION 0x1000 +#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull +#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC4_DBG_SECTION 0x1000 +#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull +#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC4_DBG_SECTION 0x1000 +#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull +#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC4_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull +#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC4_DBG_SECTION 0x21F000 +#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull +#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC0_ROM_TABLE_SECTION 0x1000 +#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull +#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC0_EML_SPMU_SECTION 0x1000 +#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull +#define TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define TPC0_EML_ETF_SECTION 0x1000 +#define mmTPC0_EML_STM_BASE 0x7FFF003000ull +#define TPC0_EML_STM_MAX_OFFSET 0x1000 +#define TPC0_EML_STM_SECTION 0x2000 +#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull +#define TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define TPC0_EML_CTI_SECTION 0x1000 +#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull +#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull +#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull +#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull +#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull +#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull +#define TPC0_EML_CFG_MAX_OFFSET 0x3380 +#define TPC0_EML_CFG_SECTION 0x1000 +#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull +#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC0_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull +#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull +#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull +#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC0_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull +#define TPC0_EML_CS_MAX_OFFSET 0x1000 +#define TPC0_EML_CS_SECTION 0x1000 +#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull +#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC1_ROM_TABLE_SECTION 0x1000 +#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull +#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC1_EML_SPMU_SECTION 0x1000 +#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull +#define TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define TPC1_EML_ETF_SECTION 0x1000 +#define mmTPC1_EML_STM_BASE 0x7FFF203000ull +#define TPC1_EML_STM_MAX_OFFSET 0x1000 +#define TPC1_EML_STM_SECTION 0x2000 +#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull +#define TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define TPC1_EML_CTI_SECTION 0x1000 +#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull +#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull +#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull +#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull +#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull +#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull +#define TPC1_EML_CFG_MAX_OFFSET 0x3380 +#define TPC1_EML_CFG_SECTION 0x1000 +#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull +#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC1_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull +#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull +#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull +#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC1_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull +#define TPC1_EML_CS_MAX_OFFSET 0x1000 +#define TPC1_EML_CS_SECTION 0x1000 +#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull +#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC2_ROM_TABLE_SECTION 0x1000 +#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull +#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC2_EML_SPMU_SECTION 0x1000 +#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull +#define TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define TPC2_EML_ETF_SECTION 0x1000 +#define mmTPC2_EML_STM_BASE 0x7FFF403000ull +#define TPC2_EML_STM_MAX_OFFSET 0x1000 +#define TPC2_EML_STM_SECTION 0x2000 +#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull +#define TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define TPC2_EML_CTI_SECTION 0x1000 +#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull +#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull +#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull +#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull +#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull +#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull +#define TPC2_EML_CFG_MAX_OFFSET 0x3380 +#define TPC2_EML_CFG_SECTION 0x1000 +#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull +#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC2_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull +#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull +#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull +#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC2_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull +#define TPC2_EML_CS_MAX_OFFSET 0x1000 +#define TPC2_EML_CS_SECTION 0x1000 +#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull +#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC3_ROM_TABLE_SECTION 0x1000 +#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull +#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC3_EML_SPMU_SECTION 0x1000 +#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull +#define TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define TPC3_EML_ETF_SECTION 0x1000 +#define mmTPC3_EML_STM_BASE 0x7FFF603000ull +#define TPC3_EML_STM_MAX_OFFSET 0x1000 +#define TPC3_EML_STM_SECTION 0x2000 +#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull +#define TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define TPC3_EML_CTI_SECTION 0x1000 +#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull +#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull +#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull +#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull +#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull +#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull +#define TPC3_EML_CFG_MAX_OFFSET 0x3380 +#define TPC3_EML_CFG_SECTION 0x1000 +#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull +#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC3_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull +#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull +#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull +#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC3_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull +#define TPC3_EML_CS_MAX_OFFSET 0x1000 +#define TPC3_EML_CS_SECTION 0x1000 +#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull +#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC4_ROM_TABLE_SECTION 0x1000 +#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull +#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC4_EML_SPMU_SECTION 0x1000 +#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull +#define TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define TPC4_EML_ETF_SECTION 0x1000 +#define mmTPC4_EML_STM_BASE 0x7FFF803000ull +#define TPC4_EML_STM_MAX_OFFSET 0x1000 +#define TPC4_EML_STM_SECTION 0x2000 +#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull +#define TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define TPC4_EML_CTI_SECTION 0x1000 +#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull +#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull +#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull +#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull +#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull +#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull +#define TPC4_EML_CFG_MAX_OFFSET 0x3380 +#define TPC4_EML_CFG_SECTION 0x1000 +#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull +#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC4_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull +#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull +#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull +#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC4_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull +#define TPC4_EML_CS_MAX_OFFSET 0x1000 +#define TPC4_EML_CS_SECTION 0x1000 +#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull +#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC5_ROM_TABLE_SECTION 0x1000 +#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull +#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC5_EML_SPMU_SECTION 0x1000 +#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull +#define TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define TPC5_EML_ETF_SECTION 0x1000 +#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull +#define TPC5_EML_STM_MAX_OFFSET 0x1000 +#define TPC5_EML_STM_SECTION 0x2000 +#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull +#define TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define TPC5_EML_CTI_SECTION 0x1000 +#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull +#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull +#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull +#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull +#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull +#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull +#define TPC5_EML_CFG_MAX_OFFSET 0x3380 +#define TPC5_EML_CFG_SECTION 0x1000 +#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull +#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC5_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull +#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull +#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull +#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC5_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull +#define TPC5_EML_CS_MAX_OFFSET 0x1000 +#define TPC5_EML_CS_SECTION 0x1000 +#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull +#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC6_ROM_TABLE_SECTION 0x1000 +#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull +#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC6_EML_SPMU_SECTION 0x1000 +#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull +#define TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define TPC6_EML_ETF_SECTION 0x1000 +#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull +#define TPC6_EML_STM_MAX_OFFSET 0x1000 +#define TPC6_EML_STM_SECTION 0x2000 +#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull +#define TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define TPC6_EML_CTI_SECTION 0x1000 +#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull +#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull +#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull +#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull +#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull +#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull +#define TPC6_EML_CFG_MAX_OFFSET 0x3380 +#define TPC6_EML_CFG_SECTION 0x1000 +#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull +#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC6_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull +#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull +#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull +#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC6_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull +#define TPC6_EML_CS_MAX_OFFSET 0x1000 +#define TPC6_EML_CS_SECTION 0x1000 +#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull +#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC7_ROM_TABLE_SECTION 0x1000 +#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull +#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC7_EML_SPMU_SECTION 0x1000 +#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull +#define TPC7_EML_ETF_MAX_OFFSET 0x1000 +#define TPC7_EML_ETF_SECTION 0x1000 +#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull +#define TPC7_EML_STM_MAX_OFFSET 0x1000 +#define TPC7_EML_STM_SECTION 0x2000 +#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull +#define TPC7_EML_CTI_MAX_OFFSET 0x1000 +#define TPC7_EML_CTI_SECTION 0x1000 +#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull +#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC7_EML_FUNNEL_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull +#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull +#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull +#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull +#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull +#define TPC7_EML_CFG_MAX_OFFSET 0x3380 +#define TPC7_EML_CFG_SECTION 0x1000 +#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull +#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC7_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull +#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull +#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull +#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC7_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull +#define TPC7_EML_CS_MAX_OFFSET 0x1000 + +#endif /* GAUDI_BLOCKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h new file mode 100644 index 000000000..1a6576666 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GAUDI_REGS_H_ +#define ASIC_REG_GAUDI_REGS_H_ + +#include "gaudi_blocks.h" +#include "psoc_global_conf_regs.h" +#include "psoc_timestamp_regs.h" +#include "cpu_if_regs.h" +#include "mmu_up_regs.h" +#include "stlb_regs.h" +#include "dma0_qm_regs.h" +#include "dma1_qm_regs.h" +#include "dma2_qm_regs.h" +#include "dma3_qm_regs.h" +#include "dma4_qm_regs.h" +#include "dma5_qm_regs.h" +#include "dma6_qm_regs.h" +#include "dma7_qm_regs.h" +#include "dma0_core_regs.h" +#include "dma1_core_regs.h" +#include "dma2_core_regs.h" +#include "dma3_core_regs.h" +#include "dma4_core_regs.h" +#include "dma5_core_regs.h" +#include "dma6_core_regs.h" +#include "dma7_core_regs.h" +#include "mme0_ctrl_regs.h" +#include "mme1_ctrl_regs.h" +#include "mme2_ctrl_regs.h" +#include "mme3_ctrl_regs.h" +#include "mme0_qm_regs.h" +#include "mme2_qm_regs.h" +#include "tpc0_cfg_regs.h" +#include "tpc1_cfg_regs.h" +#include "tpc2_cfg_regs.h" +#include "tpc3_cfg_regs.h" +#include "tpc4_cfg_regs.h" +#include "tpc5_cfg_regs.h" +#include "tpc6_cfg_regs.h" +#include "tpc7_cfg_regs.h" +#include "tpc0_qm_regs.h" +#include "tpc1_qm_regs.h" +#include "tpc2_qm_regs.h" +#include "tpc3_qm_regs.h" +#include "tpc4_qm_regs.h" +#include "tpc5_qm_regs.h" +#include "tpc6_qm_regs.h" +#include "tpc7_qm_regs.h" +#include "dma_if_e_n_down_ch0_regs.h" +#include "dma_if_e_n_down_ch1_regs.h" +#include "dma_if_e_s_down_ch0_regs.h" +#include "dma_if_e_s_down_ch1_regs.h" +#include "dma_if_w_n_down_ch0_regs.h" +#include "dma_if_w_n_down_ch1_regs.h" +#include "dma_if_w_s_down_ch0_regs.h" +#include "dma_if_w_s_down_ch1_regs.h" +#include "dma_if_e_n_regs.h" +#include "dma_if_e_s_regs.h" +#include "dma_if_w_n_regs.h" +#include "dma_if_w_s_regs.h" +#include "nif_rtr_ctrl_0_regs.h" +#include "nif_rtr_ctrl_1_regs.h" +#include "nif_rtr_ctrl_2_regs.h" +#include "nif_rtr_ctrl_3_regs.h" +#include "nif_rtr_ctrl_4_regs.h" +#include "nif_rtr_ctrl_5_regs.h" +#include "nif_rtr_ctrl_6_regs.h" +#include "nif_rtr_ctrl_7_regs.h" +#include "sif_rtr_ctrl_0_regs.h" +#include "sif_rtr_ctrl_1_regs.h" +#include "sif_rtr_ctrl_2_regs.h" +#include "sif_rtr_ctrl_3_regs.h" +#include "sif_rtr_ctrl_4_regs.h" +#include "sif_rtr_ctrl_5_regs.h" +#include "sif_rtr_ctrl_6_regs.h" +#include "sif_rtr_ctrl_7_regs.h" +#include "psoc_etr_regs.h" +#include "psoc_cpu_pll_regs.h" + +#include "dma0_qm_masks.h" +#include "mme0_qm_masks.h" +#include "tpc0_qm_masks.h" +#include "dma0_core_masks.h" +#include "tpc0_cfg_masks.h" +#include "psoc_global_conf_masks.h" + +#include "nic0_qm0_regs.h" +#include "nic1_qm0_regs.h" +#include "nic2_qm0_regs.h" +#include "nic3_qm0_regs.h" +#include "nic4_qm0_regs.h" +#include "nic0_qm1_regs.h" +#include "nic1_qm1_regs.h" +#include "nic2_qm1_regs.h" +#include "nic3_qm1_regs.h" +#include "nic4_qm1_regs.h" + +#include "nic0_qm0_masks.h" + +#define GAUDI_ECC_MEM_SEL_OFFSET 0xF18 +#define GAUDI_ECC_ADDRESS_OFFSET 0xF1C +#define GAUDI_ECC_SYNDROME_OFFSET 0xF20 +#define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28 +#define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK BIT(8) +#define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK BIT(9) +#define GAUDI_ECC_SERR0_OFFSET 0xF30 +#define GAUDI_ECC_DERR0_OFFSET 0xF40 + +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x4F4800 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x4F5000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0 0x4F5800 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0 + +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030 +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034 + +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030 +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034 + +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030 +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034 + +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030 +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034 + +#define mmMME1_QM_GLBL_CFG0 0xE8000 +#define mmMME1_QM_GLBL_STS0 0xE8038 + +#define mmMME0_SBAB_SB_STALL 0x4002C +#define mmMME0_SBAB_ARUSER0 0x40034 +#define mmMME0_SBAB_ARUSER1 0x40038 +#define mmMME0_SBAB_PROT 0x40050 + +#define mmMME1_SBAB_SB_STALL 0xC002C +#define mmMME1_SBAB_ARUSER0 0xC0034 +#define mmMME1_SBAB_ARUSER1 0xC0038 +#define mmMME1_SBAB_PROT 0xC0050 + +#define mmMME2_SBAB_SB_STALL 0x14002C +#define mmMME2_SBAB_ARUSER0 0x140034 +#define mmMME2_SBAB_ARUSER1 0x140038 +#define mmMME2_SBAB_PROT 0x140050 + +#define mmMME3_SBAB_SB_STALL 0x1C002C +#define mmMME3_SBAB_ARUSER0 0x1C0034 +#define mmMME3_SBAB_ARUSER1 0x1C0038 +#define mmMME3_SBAB_PROT 0x1C0050 + +#define mmMME0_ACC_ACC_STALL 0x20028 +#define mmMME0_ACC_WBC 0x20038 +#define mmMME0_ACC_PROT 0x20050 + +#define mmMME1_ACC_ACC_STALL 0xA0028 +#define mmMME1_ACC_WBC 0xA0038 +#define mmMME1_ACC_PROT 0xA0050 + +#define mmMME2_ACC_ACC_STALL 0x120028 +#define mmMME2_ACC_WBC 0x120038 +#define mmMME2_ACC_PROT 0x120050 + +#define mmMME3_ACC_ACC_STALL 0x1A0028 +#define mmMME3_ACC_WBC 0x1A0038 +#define mmMME3_ACC_PROT 0x1A0050 + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 + +#define mmPSOC_EFUSE_READ 0xC4A000 +#define mmPSOC_EFUSE_DATA_0 0xC4A080 + +#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 +#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 +#define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54 +#define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C + +#define mmPCIE_MSI_INTR_0 0xC13000 + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 + +#define mmPCIE_AUX_FLR_CTRL 0xC07394 +#define mmPCIE_AUX_DBI 0xC07490 + +#define mmPCIE_CORE_MSI_REQ 0xC04100 + +#define mmPSOC_PCI_PLL_NR 0xC72100 +#define mmSRAM_W_PLL_NR 0x4C8100 +#define mmPSOC_HBM_PLL_NR 0xC74100 +#define mmNIC0_PLL_NR 0xCF9100 +#define mmDMA_W_PLL_NR 0x487100 +#define mmMESH_W_PLL_NR 0x4C7100 +#define mmPSOC_MME_PLL_NR 0xC71100 +#define mmPSOC_TPC_PLL_NR 0xC73100 +#define mmIF_W_PLL_NR 0x488100 + +#endif /* ASIC_REG_GAUDI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h new file mode 100644 index 000000000..083d073a0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_CTRL_REGS_H_ +#define ASIC_REG_MME0_CTRL_REGS_H_ + +/* + ***************************************** + * MME0_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME0_CTRL_ARCH_STATUS 0x60000 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C + +#define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020 + +#define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024 + +#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028 + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x6002C + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x60030 + +#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x60034 + +#define mmMME0_CTRL_ARCH_OUTER_LOOP 0x60038 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x6003C + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x60040 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x60044 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x60048 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x6004C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x60050 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x60054 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x60058 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x6005C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x60060 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x60064 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x60068 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x6006C + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x60070 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x60074 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x60078 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x6007C + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x60080 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60084 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x60088 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x6008C + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x60090 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x60094 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x60098 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0 0x6009C + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1 0x600A0 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2 0x600A4 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_3 0x600A8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x600AC + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x600B0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x600B4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x600B8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x600BC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x600C0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x600C4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x600C8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x600CC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x600D0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x600D4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x600D8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x600DC + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x600E0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x600E4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x600E8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x600EC + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x600F0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x600F4 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x600F8 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x600FC + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60100 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60104 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60108 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x6010C + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x60110 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x60114 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x60118 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6011C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60120 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60124 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60128 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6012C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x60130 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x60134 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x60138 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x6013C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x60140 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x60144 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x60148 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x6014C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x60150 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x60154 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x60158 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x6015C + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x60160 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x60164 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x60168 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x6016C + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x60170 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x60174 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x60178 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x6017C + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x60180 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x60184 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60188 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6018C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60190 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60194 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60198 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6019C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x601A0 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x601A4 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x601A8 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x601AC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x601B0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x601B4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x601B8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x601BC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x601C0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x601C4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x601C8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x601CC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x601D0 + +#define mmMME0_CTRL_ARCH_DESC_SB_REPEAT 0x601D4 + +#define mmMME0_CTRL_ARCH_DESC_RATE_LIMITER 0x601D8 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x601DC + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x601E0 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x601E4 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x601E8 + +#define mmMME0_CTRL_ARCH_DESC_AXI_USER_DATA 0x601EC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_S 0x601F0 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x601F4 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x601F8 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x601FC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x60200 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_S 0x60204 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_L 0x60208 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_S 0x6020C + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x60210 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x60214 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x60218 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x6021C + +#define mmMME0_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x60220 + +#define mmMME0_CTRL_ARCH_DESC_DUMMY 0x60224 + +#define mmMME0_CTRL_CMD 0x60280 + +#define mmMME0_CTRL_STATUS1 0x60284 + +#define mmMME0_CTRL_RESET 0x60288 + +#define mmMME0_CTRL_QM_STALL 0x6028C + +#define mmMME0_CTRL_SYNC_OBJECT_FIFO_TH 0x60290 + +#define mmMME0_CTRL_EUS_ROLLUP_CNT_ADD 0x60294 + +#define mmMME0_CTRL_INTR_CAUSE 0x60298 + +#define mmMME0_CTRL_INTR_MASK 0x6029C + +#define mmMME0_CTRL_LOG_SHADOW 0x602A0 + +#define mmMME0_CTRL_PCU_RL_DESC0 0x602A4 + +#define mmMME0_CTRL_PCU_RL_TOKEN_UPDATE 0x602A8 + +#define mmMME0_CTRL_PCU_RL_TH 0x602AC + +#define mmMME0_CTRL_PCU_RL_MIN 0x602B0 + +#define mmMME0_CTRL_PCU_RL_CTRL_EN 0x602B4 + +#define mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x602B8 + +#define mmMME0_CTRL_PCU_DUMMY_A_BF16 0x602BC + +#define mmMME0_CTRL_PCU_DUMMY_B_BF16 0x602C0 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD 0x602C4 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN 0x602C8 + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD 0x602CC + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN 0x602D0 + +#define mmMME0_CTRL_PROT 0x602D4 + +#define mmMME0_CTRL_EU_POWER_SAVE_DISABLE 0x602D8 + +#define mmMME0_CTRL_CS_DBG_BLOCK_ID 0x602DC + +#define mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT 0x602E0 + +#define mmMME0_CTRL_TE_CLOSE_CGATE 0x602E4 + +#define mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR 0x602E8 + +#define mmMME0_CTRL_AGU_SM_TOTAL_CNTR 0x602EC + +#define mmMME0_CTRL_EZSYNC_OUT_CREDIT 0x602F0 + +#define mmMME0_CTRL_PCU_RL_SAT_SEC 0x602F4 + +#define mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER 0x602F8 + +#define mmMME0_CTRL_QM_SLV_LBW_CLK_EN 0x602FC + +#define mmMME0_CTRL_SHADOW_0_STATUS 0x60400 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x60408 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x6040C + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x60410 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x60414 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x60418 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x6041C + +#define mmMME0_CTRL_SHADOW_0_HEADER_LOW 0x60420 + +#define mmMME0_CTRL_SHADOW_0_HEADER_HIGH 0x60424 + +#define mmMME0_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x60428 + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x6042C + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x60430 + +#define mmMME0_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x60434 + +#define mmMME0_CTRL_SHADOW_0_OUTER_LOOP 0x60438 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x6043C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x60440 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x60444 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x60448 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x6044C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x60450 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x60454 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x60458 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x6045C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x60460 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x60464 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x60468 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x6046C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x60470 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x60474 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x60478 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x6047C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x60480 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60484 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x60488 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x6048C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x60490 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x60494 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x60498 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x6049C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x604A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x604A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x604A8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x604AC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x604B0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x604B4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x604B8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x604BC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x604C0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x604C4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x604C8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x604CC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x604D0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x604D4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x604D8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x604DC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x604E0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x604E4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x604E8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x604EC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x604F0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x604F4 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x604F8 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x604FC + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60500 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60504 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60508 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x6050C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x60510 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x60514 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x60518 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6051C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60520 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60524 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60528 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6052C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x60530 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x60534 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x60538 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x6053C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x60540 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x60544 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x60548 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x6054C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x60550 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x60554 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x60558 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x6055C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x60560 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x60564 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x60568 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x6056C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x60570 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x60574 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x60578 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x6057C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x60580 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x60584 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60588 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6058C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60590 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60594 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60598 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6059C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x605A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x605A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x605A8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x605AC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x605B0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x605B4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x605B8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x605BC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x605C0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x605C4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x605C8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x605CC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x605D0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SB_REPEAT 0x605D4 + +#define mmMME0_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x605D8 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x605DC + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x605E0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x605E4 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x605E8 + +#define mmMME0_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x605EC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x605F0 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x605F4 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x605F8 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x605FC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x60600 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x60604 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x60608 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x6060C + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x60610 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x60614 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x60618 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x6061C + +#define mmMME0_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x60620 + +#define mmMME0_CTRL_SHADOW_0_DESC_DUMMY 0x60624 + +#define mmMME0_CTRL_SHADOW_1_STATUS 0x60680 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x60688 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x6068C + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x60690 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x60694 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x60698 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x6069C + +#define mmMME0_CTRL_SHADOW_1_HEADER_LOW 0x606A0 + +#define mmMME0_CTRL_SHADOW_1_HEADER_HIGH 0x606A4 + +#define mmMME0_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x606A8 + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x606AC + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x606B0 + +#define mmMME0_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x606B4 + +#define mmMME0_CTRL_SHADOW_1_OUTER_LOOP 0x606B8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x606BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x606C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x606C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x606C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x606CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x606D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x606D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x606D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x606DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x606E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x606E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x606E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x606EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x606F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x606F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x606F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x606FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x60700 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60704 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x60708 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x6070C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x60710 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x60714 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x60718 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x6071C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x60720 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x60724 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x60728 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x6072C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x60730 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x60734 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x60738 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x6073C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x60740 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x60744 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x60748 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x6074C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x60750 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x60754 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x60758 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x6075C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x60760 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x60764 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x60768 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x6076C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x60770 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60774 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60778 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x6077C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60780 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60784 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60788 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x6078C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x60790 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x60794 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x60798 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6079C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x607A0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x607A4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x607A8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x607AC + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x607B0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x607B4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x607B8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x607BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x607C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x607C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x607C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x607CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x607D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x607D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x607D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x607DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x607E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x607E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x607E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x607EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x607F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x607F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x607F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x607FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x60800 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x60804 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60808 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6080C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60810 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60814 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60818 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6081C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x60820 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x60824 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x60828 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x6082C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60830 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60834 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60838 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x6083C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60840 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x60844 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x60848 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x6084C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x60850 + +#define mmMME0_CTRL_SHADOW_1_DESC_SB_REPEAT 0x60854 + +#define mmMME0_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x60858 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x6085C + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60860 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x60864 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x60868 + +#define mmMME0_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x6086C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x60870 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x60874 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x60878 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x6087C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x60880 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x60884 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x60888 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x6088C + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x60890 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x60894 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x60898 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x6089C + +#define mmMME0_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x608A0 + +#define mmMME0_CTRL_SHADOW_1_DESC_DUMMY 0x608A4 + +#define mmMME0_CTRL_SHADOW_2_STATUS 0x60900 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x60908 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x6090C + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x60910 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x60914 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x60918 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x6091C + +#define mmMME0_CTRL_SHADOW_2_HEADER_LOW 0x60920 + +#define mmMME0_CTRL_SHADOW_2_HEADER_HIGH 0x60924 + +#define mmMME0_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x60928 + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x6092C + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x60930 + +#define mmMME0_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x60934 + +#define mmMME0_CTRL_SHADOW_2_OUTER_LOOP 0x60938 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x6093C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x60940 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x60944 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x60948 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x6094C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x60950 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x60954 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x60958 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x6095C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x60960 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x60964 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x60968 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x6096C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x60970 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x60974 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x60978 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x6097C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x60980 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60984 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x60988 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x6098C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x60990 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x60994 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x60998 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x6099C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x609A0 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x609A4 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x609A8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x609AC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x609B0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x609B4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x609B8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x609BC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x609C0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x609C4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x609C8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x609CC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x609D0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x609D4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x609D8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x609DC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x609E0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x609E4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x609E8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x609EC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x609F0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x609F4 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x609F8 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x609FC + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60A00 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60A04 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60A08 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x60A0C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x60A10 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x60A14 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x60A18 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60A1C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60A20 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60A24 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60A28 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60A2C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x60A30 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x60A34 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x60A38 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x60A3C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x60A40 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x60A44 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x60A48 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x60A4C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x60A50 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x60A54 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x60A58 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x60A5C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x60A60 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x60A64 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x60A68 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x60A6C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x60A70 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x60A74 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x60A78 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x60A7C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x60A80 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x60A84 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60A88 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60A8C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60A90 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60A94 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60A98 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60A9C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x60AA0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x60AA4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x60AA8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x60AAC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60AB0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60AB4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60AB8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60ABC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60AC0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x60AC4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x60AC8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x60ACC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x60AD0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SB_REPEAT 0x60AD4 + +#define mmMME0_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x60AD8 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60ADC + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60AE0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x60AE4 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x60AE8 + +#define mmMME0_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x60AEC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x60AF0 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x60AF4 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x60AF8 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x60AFC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x60B00 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x60B04 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x60B08 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x60B0C + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x60B10 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x60B14 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x60B18 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x60B1C + +#define mmMME0_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x60B20 + +#define mmMME0_CTRL_SHADOW_2_DESC_DUMMY 0x60B24 + +#define mmMME0_CTRL_SHADOW_3_STATUS 0x60B80 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x60B88 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x60B8C + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x60B90 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x60B94 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x60B98 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x60B9C + +#define mmMME0_CTRL_SHADOW_3_HEADER_LOW 0x60BA0 + +#define mmMME0_CTRL_SHADOW_3_HEADER_HIGH 0x60BA4 + +#define mmMME0_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x60BA8 + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x60BAC + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x60BB0 + +#define mmMME0_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x60BB4 + +#define mmMME0_CTRL_SHADOW_3_OUTER_LOOP 0x60BB8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x60BBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x60BC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x60BC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x60BC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x60BCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x60BD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x60BD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x60BD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x60BDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x60BE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x60BE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x60BE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x60BEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x60BF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x60BF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x60BF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x60BFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x60C00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60C04 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x60C08 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x60C0C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x60C10 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x60C14 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x60C18 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x60C1C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x60C20 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x60C24 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x60C28 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x60C2C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x60C30 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x60C34 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x60C38 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x60C3C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x60C40 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x60C44 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x60C48 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x60C4C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x60C50 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x60C54 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x60C58 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x60C5C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x60C60 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x60C64 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x60C68 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x60C6C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x60C70 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60C74 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60C78 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x60C7C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60C80 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60C84 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60C88 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x60C8C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x60C90 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x60C94 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x60C98 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60C9C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60CA0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60CA4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60CA8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60CAC + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x60CB0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x60CB4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x60CB8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x60CBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x60CC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x60CC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x60CC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x60CCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x60CD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x60CD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x60CD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x60CDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x60CE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x60CE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x60CE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x60CEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x60CF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x60CF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x60CF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x60CFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x60D00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x60D04 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60D08 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60D0C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60D10 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60D14 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60D18 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60D1C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x60D20 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x60D24 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x60D28 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x60D2C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60D30 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60D34 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60D38 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60D3C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60D40 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x60D44 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x60D48 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x60D4C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x60D50 + +#define mmMME0_CTRL_SHADOW_3_DESC_SB_REPEAT 0x60D54 + +#define mmMME0_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x60D58 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60D5C + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60D60 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x60D64 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x60D68 + +#define mmMME0_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x60D6C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x60D70 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x60D74 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x60D78 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x60D7C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x60D80 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x60D84 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x60D88 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x60D8C + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x60D90 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x60D94 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x60D98 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x60D9C + +#define mmMME0_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x60DA0 + +#define mmMME0_CTRL_SHADOW_3_DESC_DUMMY 0x60DA4 + +#endif /* ASIC_REG_MME0_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h new file mode 100644 index 000000000..e6dd30ce0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_MASKS_H_ +#define ASIC_REG_MME0_QM_MASKS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +/* MME0_QM_GLBL_CFG0 */ +#define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define MME0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define MME0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* MME0_QM_GLBL_CFG1 */ +#define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define MME0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define MME0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* MME0_QM_GLBL_PROT */ +#define MME0_QM_GLBL_PROT_PQF_SHIFT 0 +#define MME0_QM_GLBL_PROT_PQF_MASK 0xF +#define MME0_QM_GLBL_PROT_CQF_SHIFT 4 +#define MME0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define MME0_QM_GLBL_PROT_CP_SHIFT 9 +#define MME0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define MME0_QM_GLBL_PROT_ERR_SHIFT 14 +#define MME0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define MME0_QM_GLBL_PROT_ARB_SHIFT 15 +#define MME0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* MME0_QM_GLBL_ERR_CFG */ +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* MME0_QM_GLBL_SECURE_PROPS */ +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_NON_SECURE_PROPS */ +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_STS0 */ +#define MME0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define MME0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define MME0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define MME0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define MME0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* MME0_QM_GLBL_STS1 */ +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_STS1_4 */ +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN */ +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN_4 */ +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_PQ_BASE_LO */ +#define MME0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_BASE_HI */ +#define MME0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_SIZE */ +#define MME0_QM_PQ_SIZE_VAL_SHIFT 0 +#define MME0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_PI */ +#define MME0_QM_PQ_PI_VAL_SHIFT 0 +#define MME0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CI */ +#define MME0_QM_PQ_CI_VAL_SHIFT 0 +#define MME0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CFG0 */ +#define MME0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_PQ_CFG1 */ +#define MME0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_ARUSER_31_11 */ +#define MME0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_PQ_STS0 */ +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_STS1 */ +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define MME0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_CFG0 */ +#define MME0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_CQ_CFG1 */ +#define MME0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_ARUSER_31_11 */ +#define MME0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CQ_STS0 */ +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_STS1 */ +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_PTR_LO_0 */ +#define MME0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_0 */ +#define MME0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_0 */ +#define MME0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_0 */ +#define MME0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_1 */ +#define MME0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_1 */ +#define MME0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_1 */ +#define MME0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_1 */ +#define MME0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_2 */ +#define MME0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_2 */ +#define MME0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_2 */ +#define MME0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_2 */ +#define MME0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_3 */ +#define MME0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_3 */ +#define MME0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_3 */ +#define MME0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_3 */ +#define MME0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_4 */ +#define MME0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_4 */ +#define MME0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_4 */ +#define MME0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_4 */ +#define MME0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_STS */ +#define MME0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_STS */ +#define MME0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_STS */ +#define MME0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_STS */ +#define MME0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_IFIFO_CNT */ +#define MME0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME0_QM_CP_MSG_BASE0_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE0_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_TSIZE_OFFSET */ +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_FENCE0_RDATA */ +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE1_RDATA */ +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE2_RDATA */ +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE3_RDATA */ +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE0_CNT */ +#define MME0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE1_CNT */ +#define MME0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE2_CNT */ +#define MME0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE3_CNT */ +#define MME0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_STS */ +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CP_STS_ERDY_SHIFT 16 +#define MME0_QM_CP_STS_ERDY_MASK 0x10000 +#define MME0_QM_CP_STS_RRDY_SHIFT 17 +#define MME0_QM_CP_STS_RRDY_MASK 0x20000 +#define MME0_QM_CP_STS_MRDY_SHIFT 18 +#define MME0_QM_CP_STS_MRDY_MASK 0x40000 +#define MME0_QM_CP_STS_SW_STOP_SHIFT 19 +#define MME0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define MME0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define MME0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME0_QM_CP_CURRENT_INST_LO */ +#define MME0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_CURRENT_INST_HI */ +#define MME0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_BARRIER_CFG */ +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* MME0_QM_CP_DBG_0 */ +#define MME0_QM_CP_DBG_0_CS_SHIFT 0 +#define MME0_QM_CP_DBG_0_CS_MASK 0xF +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define MME0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define MME0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define MME0_QM_CP_DBG_0_STALL_SHIFT 7 +#define MME0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* MME0_QM_CP_ARUSER_31_11 */ +#define MME0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CP_AWUSER_31_11 */ +#define MME0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_CFG_0 */ +#define MME0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define MME0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define MME0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define MME0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define MME0_QM_ARB_CFG_0_EN_SHIFT 8 +#define MME0_QM_ARB_CFG_0_EN_MASK 0x100 +#define MME0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define MME0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* MME0_QM_ARB_CHOISE_Q_PUSH */ +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* MME0_QM_ARB_WRR_WEIGHT */ +#define MME0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CFG_1 */ +#define MME0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define MME0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* MME0_QM_ARB_MST_AVAIL_CRED */ +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* MME0_QM_ARB_MST_CRED_INC */ +#define MME0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_SLAVE_EN */ +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_QUIET_PER */ +#define MME0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_CHOISE_WDT */ +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_ID */ +#define MME0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* MME0_QM_ARB_MSG_MAX_INFLIGHT */ +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* MME0_QM_ARB_MSG_AWUSER_31_11 */ +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_BASE_LO */ +#define MME0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_BASE_HI */ +#define MME0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_STATE_STS */ +#define MME0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CHOISE_FULLNESS_STS */ +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* MME0_QM_ARB_MSG_STS */ +#define MME0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define MME0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* MME0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* MME0_QM_ARB_ERR_CAUSE */ +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_MSG_EN */ +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_STS_DRP */ +#define MME0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define MME0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* MME0_QM_ARB_MST_CRED_STS */ +#define MME0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* MME0_QM_CGM_CFG */ +#define MME0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define MME0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define MME0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define MME0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define MME0_QM_CGM_CFG_EN_SHIFT 31 +#define MME0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* MME0_QM_CGM_STS */ +#define MME0_QM_CGM_STS_ST_SHIFT 0 +#define MME0_QM_CGM_STS_ST_MASK 0x3 +#define MME0_QM_CGM_STS_CG_SHIFT 4 +#define MME0_QM_CGM_STS_CG_MASK 0x10 +#define MME0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define MME0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define MME0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define MME0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* MME0_QM_CGM_CFG1 */ +#define MME0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define MME0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* MME0_QM_LOCAL_RANGE_BASE */ +#define MME0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* MME0_QM_LOCAL_RANGE_SIZE */ +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* MME0_QM_CSMR_STRICT_PRIO_CFG */ +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_GLBL_AXCACHE */ +#define MME0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define MME0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define MME0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define MME0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* MME0_QM_IND_GW_APB_CFG */ +#define MME0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define MME0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define MME0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define MME0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* MME0_QM_IND_GW_APB_WDATA */ +#define MME0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_RDATA */ +#define MME0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_STATUS */ +#define MME0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define MME0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* MME0_QM_GLBL_ERR_ADDR_LO */ +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_ADDR_HI */ +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_WDATA */ +#define MME0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_MEM_INIT_BUSY */ +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_MME0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h new file mode 100644 index 000000000..4f078b328 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_REGS_H_ +#define ASIC_REG_MME0_QM_REGS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME0_QM_GLBL_CFG0 0x68000 + +#define mmMME0_QM_GLBL_CFG1 0x68004 + +#define mmMME0_QM_GLBL_PROT 0x68008 + +#define mmMME0_QM_GLBL_ERR_CFG 0x6800C + +#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010 + +#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014 + +#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018 + +#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C + +#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034 + +#define mmMME0_QM_GLBL_STS0 0x68038 + +#define mmMME0_QM_GLBL_STS1_0 0x68040 + +#define mmMME0_QM_GLBL_STS1_1 0x68044 + +#define mmMME0_QM_GLBL_STS1_2 0x68048 + +#define mmMME0_QM_GLBL_STS1_3 0x6804C + +#define mmMME0_QM_GLBL_STS1_4 0x68050 + +#define mmMME0_QM_GLBL_MSG_EN_0 0x68054 + +#define mmMME0_QM_GLBL_MSG_EN_1 0x68058 + +#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C + +#define mmMME0_QM_GLBL_MSG_EN_3 0x68060 + +#define mmMME0_QM_GLBL_MSG_EN_4 0x68068 + +#define mmMME0_QM_PQ_BASE_LO_0 0x68070 + +#define mmMME0_QM_PQ_BASE_LO_1 0x68074 + +#define mmMME0_QM_PQ_BASE_LO_2 0x68078 + +#define mmMME0_QM_PQ_BASE_LO_3 0x6807C + +#define mmMME0_QM_PQ_BASE_HI_0 0x68080 + +#define mmMME0_QM_PQ_BASE_HI_1 0x68084 + +#define mmMME0_QM_PQ_BASE_HI_2 0x68088 + +#define mmMME0_QM_PQ_BASE_HI_3 0x6808C + +#define mmMME0_QM_PQ_SIZE_0 0x68090 + +#define mmMME0_QM_PQ_SIZE_1 0x68094 + +#define mmMME0_QM_PQ_SIZE_2 0x68098 + +#define mmMME0_QM_PQ_SIZE_3 0x6809C + +#define mmMME0_QM_PQ_PI_0 0x680A0 + +#define mmMME0_QM_PQ_PI_1 0x680A4 + +#define mmMME0_QM_PQ_PI_2 0x680A8 + +#define mmMME0_QM_PQ_PI_3 0x680AC + +#define mmMME0_QM_PQ_CI_0 0x680B0 + +#define mmMME0_QM_PQ_CI_1 0x680B4 + +#define mmMME0_QM_PQ_CI_2 0x680B8 + +#define mmMME0_QM_PQ_CI_3 0x680BC + +#define mmMME0_QM_PQ_CFG0_0 0x680C0 + +#define mmMME0_QM_PQ_CFG0_1 0x680C4 + +#define mmMME0_QM_PQ_CFG0_2 0x680C8 + +#define mmMME0_QM_PQ_CFG0_3 0x680CC + +#define mmMME0_QM_PQ_CFG1_0 0x680D0 + +#define mmMME0_QM_PQ_CFG1_1 0x680D4 + +#define mmMME0_QM_PQ_CFG1_2 0x680D8 + +#define mmMME0_QM_PQ_CFG1_3 0x680DC + +#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0 + +#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4 + +#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8 + +#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC + +#define mmMME0_QM_PQ_STS0_0 0x680F0 + +#define mmMME0_QM_PQ_STS0_1 0x680F4 + +#define mmMME0_QM_PQ_STS0_2 0x680F8 + +#define mmMME0_QM_PQ_STS0_3 0x680FC + +#define mmMME0_QM_PQ_STS1_0 0x68100 + +#define mmMME0_QM_PQ_STS1_1 0x68104 + +#define mmMME0_QM_PQ_STS1_2 0x68108 + +#define mmMME0_QM_PQ_STS1_3 0x6810C + +#define mmMME0_QM_CQ_CFG0_0 0x68110 + +#define mmMME0_QM_CQ_CFG0_1 0x68114 + +#define mmMME0_QM_CQ_CFG0_2 0x68118 + +#define mmMME0_QM_CQ_CFG0_3 0x6811C + +#define mmMME0_QM_CQ_CFG0_4 0x68120 + +#define mmMME0_QM_CQ_CFG1_0 0x68124 + +#define mmMME0_QM_CQ_CFG1_1 0x68128 + +#define mmMME0_QM_CQ_CFG1_2 0x6812C + +#define mmMME0_QM_CQ_CFG1_3 0x68130 + +#define mmMME0_QM_CQ_CFG1_4 0x68134 + +#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138 + +#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C + +#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140 + +#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144 + +#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148 + +#define mmMME0_QM_CQ_STS0_0 0x6814C + +#define mmMME0_QM_CQ_STS0_1 0x68150 + +#define mmMME0_QM_CQ_STS0_2 0x68154 + +#define mmMME0_QM_CQ_STS0_3 0x68158 + +#define mmMME0_QM_CQ_STS0_4 0x6815C + +#define mmMME0_QM_CQ_STS1_0 0x68160 + +#define mmMME0_QM_CQ_STS1_1 0x68164 + +#define mmMME0_QM_CQ_STS1_2 0x68168 + +#define mmMME0_QM_CQ_STS1_3 0x6816C + +#define mmMME0_QM_CQ_STS1_4 0x68170 + +#define mmMME0_QM_CQ_PTR_LO_0 0x68174 + +#define mmMME0_QM_CQ_PTR_HI_0 0x68178 + +#define mmMME0_QM_CQ_TSIZE_0 0x6817C + +#define mmMME0_QM_CQ_CTL_0 0x68180 + +#define mmMME0_QM_CQ_PTR_LO_1 0x68184 + +#define mmMME0_QM_CQ_PTR_HI_1 0x68188 + +#define mmMME0_QM_CQ_TSIZE_1 0x6818C + +#define mmMME0_QM_CQ_CTL_1 0x68190 + +#define mmMME0_QM_CQ_PTR_LO_2 0x68194 + +#define mmMME0_QM_CQ_PTR_HI_2 0x68198 + +#define mmMME0_QM_CQ_TSIZE_2 0x6819C + +#define mmMME0_QM_CQ_CTL_2 0x681A0 + +#define mmMME0_QM_CQ_PTR_LO_3 0x681A4 + +#define mmMME0_QM_CQ_PTR_HI_3 0x681A8 + +#define mmMME0_QM_CQ_TSIZE_3 0x681AC + +#define mmMME0_QM_CQ_CTL_3 0x681B0 + +#define mmMME0_QM_CQ_PTR_LO_4 0x681B4 + +#define mmMME0_QM_CQ_PTR_HI_4 0x681B8 + +#define mmMME0_QM_CQ_TSIZE_4 0x681BC + +#define mmMME0_QM_CQ_CTL_4 0x681C0 + +#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4 + +#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8 + +#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC + +#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0 + +#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4 + +#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8 + +#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC + +#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0 + +#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4 + +#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8 + +#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC + +#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0 + +#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4 + +#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8 + +#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC + +#define mmMME0_QM_CQ_CTL_STS_0 0x68200 + +#define mmMME0_QM_CQ_CTL_STS_1 0x68204 + +#define mmMME0_QM_CQ_CTL_STS_2 0x68208 + +#define mmMME0_QM_CQ_CTL_STS_3 0x6820C + +#define mmMME0_QM_CQ_CTL_STS_4 0x68210 + +#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214 + +#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218 + +#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C + +#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220 + +#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304 + +#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308 + +#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C + +#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310 + +#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314 + +#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318 + +#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C + +#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320 + +#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324 + +#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328 + +#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C + +#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330 + +#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334 + +#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338 + +#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C + +#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340 + +#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344 + +#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348 + +#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C + +#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350 + +#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354 + +#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358 + +#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C + +#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360 + +#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364 + +#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368 + +#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C + +#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370 + +#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374 + +#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378 + +#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C + +#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380 + +#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384 + +#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388 + +#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C + +#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390 + +#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394 + +#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398 + +#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C + +#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0 + +#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4 + +#define mmMME0_QM_CP_STS_0 0x683A8 + +#define mmMME0_QM_CP_STS_1 0x683AC + +#define mmMME0_QM_CP_STS_2 0x683B0 + +#define mmMME0_QM_CP_STS_3 0x683B4 + +#define mmMME0_QM_CP_STS_4 0x683B8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC + +#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0 + +#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4 + +#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC + +#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0 + +#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4 + +#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8 + +#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC + +#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0 + +#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4 + +#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8 + +#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC + +#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400 + +#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404 + +#define mmMME0_QM_CP_DBG_0_0 0x68408 + +#define mmMME0_QM_CP_DBG_0_1 0x6840C + +#define mmMME0_QM_CP_DBG_0_2 0x68410 + +#define mmMME0_QM_CP_DBG_0_3 0x68414 + +#define mmMME0_QM_CP_DBG_0_4 0x68418 + +#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C + +#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420 + +#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424 + +#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428 + +#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C + +#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430 + +#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434 + +#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438 + +#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C + +#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440 + +#define mmMME0_QM_ARB_CFG_0 0x68A00 + +#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04 + +#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08 + +#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C + +#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10 + +#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14 + +#define mmMME0_QM_ARB_CFG_1 0x68A18 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C + +#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20 + +#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28 + +#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C + +#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34 + +#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38 + +#define mmMME0_QM_ARB_SLV_ID 0x68B3C + +#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44 + +#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48 + +#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C + +#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50 + +#define mmMME0_QM_ARB_BASE_LO 0x68B54 + +#define mmMME0_QM_ARB_BASE_HI 0x68B58 + +#define mmMME0_QM_ARB_STATE_STS 0x68B80 + +#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84 + +#define mmMME0_QM_ARB_MSG_STS 0x68B88 + +#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C + +#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C + +#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0 + +#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8 + +#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0 + +#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4 + +#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8 + +#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC + +#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0 + +#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4 + +#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8 + +#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC + +#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0 + +#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4 + +#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8 + +#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC + +#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0 + +#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4 + +#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8 + +#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC + +#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0 + +#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4 + +#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8 + +#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC + +#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00 + +#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04 + +#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08 + +#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C + +#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10 + +#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14 + +#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18 + +#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C + +#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20 + +#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24 + +#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28 + +#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C + +#define mmMME0_QM_CGM_CFG 0x68C70 + +#define mmMME0_QM_CGM_STS 0x68C74 + +#define mmMME0_QM_CGM_CFG1 0x68C78 + +#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80 + +#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84 + +#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90 + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0 + +#define mmMME0_QM_GLBL_AXCACHE 0x68CA4 + +#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0 + +#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4 + +#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8 + +#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC + +#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0 + +#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4 + +#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8 + +#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00 + +#endif /* ASIC_REG_MME0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h new file mode 100644 index 000000000..6c07f7d45 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_CTRL_REGS_H_ +#define ASIC_REG_MME1_CTRL_REGS_H_ + +/* + ***************************************** + * MME1_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME1_CTRL_ARCH_STATUS 0xE0000 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S 0xE0008 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L 0xE000C + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O 0xE0010 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S 0xE0014 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L 0xE0018 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O 0xE001C + +#define mmMME1_CTRL_ARCH_HEADER_LOW 0xE0020 + +#define mmMME1_CTRL_ARCH_HEADER_HIGH 0xE0024 + +#define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0xE0028 + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0xE002C + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0xE0030 + +#define mmMME1_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0xE0034 + +#define mmMME1_CTRL_ARCH_OUTER_LOOP 0xE0038 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0xE003C + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0xE0040 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0xE0044 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0xE0048 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0xE004C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0xE0050 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0xE0054 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0xE0058 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0xE005C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0xE0060 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0xE0064 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0xE0068 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0xE006C + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0xE0070 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0xE0074 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0xE0078 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0xE007C + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0xE0080 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0084 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0xE0088 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0xE008C + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0xE0090 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0xE0094 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0xE0098 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_0 0xE009C + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_1 0xE00A0 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_2 0xE00A4 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_3 0xE00A8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0xE00AC + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0xE00B0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0xE00B4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0xE00B8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0xE00BC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0xE00C0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0xE00C4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0xE00C8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0xE00CC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0xE00D0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0xE00D4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0xE00D8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0xE00DC + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0xE00E0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0xE00E4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0xE00E8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0xE00EC + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0xE00F0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE00F4 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE00F8 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE00FC + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0100 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0104 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0108 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0xE010C + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0xE0110 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0xE0114 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0xE0118 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE011C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0120 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0124 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0128 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE012C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0xE0130 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0xE0134 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0xE0138 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0xE013C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0xE0140 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0xE0144 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0xE0148 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0xE014C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0xE0150 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0xE0154 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0xE0158 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0xE015C + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0xE0160 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0xE0164 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0xE0168 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0xE016C + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0xE0170 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0xE0174 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0xE0178 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0xE017C + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0xE0180 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0xE0184 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0188 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE018C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0190 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0194 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0198 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE019C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0xE01A0 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0xE01A4 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0xE01A8 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0xE01AC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE01B0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE01B4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE01B8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE01BC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE01C0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0xE01C4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0xE01C8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0xE01CC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0xE01D0 + +#define mmMME1_CTRL_ARCH_DESC_SB_REPEAT 0xE01D4 + +#define mmMME1_CTRL_ARCH_DESC_RATE_LIMITER 0xE01D8 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE01DC + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE01E0 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0xE01E4 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0xE01E8 + +#define mmMME1_CTRL_ARCH_DESC_AXI_USER_DATA 0xE01EC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_S 0xE01F0 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0xE01F4 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0xE01F8 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0xE01FC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0xE0200 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_S 0xE0204 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_L 0xE0208 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_S 0xE020C + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0xE0210 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0xE0214 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0xE0218 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0xE021C + +#define mmMME1_CTRL_ARCH_DESC_PCU_RL_SATURATION 0xE0220 + +#define mmMME1_CTRL_ARCH_DESC_DUMMY 0xE0224 + +#define mmMME1_CTRL_CMD 0xE0280 + +#define mmMME1_CTRL_STATUS1 0xE0284 + +#define mmMME1_CTRL_RESET 0xE0288 + +#define mmMME1_CTRL_QM_STALL 0xE028C + +#define mmMME1_CTRL_SYNC_OBJECT_FIFO_TH 0xE0290 + +#define mmMME1_CTRL_EUS_ROLLUP_CNT_ADD 0xE0294 + +#define mmMME1_CTRL_INTR_CAUSE 0xE0298 + +#define mmMME1_CTRL_INTR_MASK 0xE029C + +#define mmMME1_CTRL_LOG_SHADOW 0xE02A0 + +#define mmMME1_CTRL_PCU_RL_DESC0 0xE02A4 + +#define mmMME1_CTRL_PCU_RL_TOKEN_UPDATE 0xE02A8 + +#define mmMME1_CTRL_PCU_RL_TH 0xE02AC + +#define mmMME1_CTRL_PCU_RL_MIN 0xE02B0 + +#define mmMME1_CTRL_PCU_RL_CTRL_EN 0xE02B4 + +#define mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE 0xE02B8 + +#define mmMME1_CTRL_PCU_DUMMY_A_BF16 0xE02BC + +#define mmMME1_CTRL_PCU_DUMMY_B_BF16 0xE02C0 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD 0xE02C4 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN 0xE02C8 + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD 0xE02CC + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN 0xE02D0 + +#define mmMME1_CTRL_PROT 0xE02D4 + +#define mmMME1_CTRL_EU_POWER_SAVE_DISABLE 0xE02D8 + +#define mmMME1_CTRL_CS_DBG_BLOCK_ID 0xE02DC + +#define mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT 0xE02E0 + +#define mmMME1_CTRL_TE_CLOSE_CGATE 0xE02E4 + +#define mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR 0xE02E8 + +#define mmMME1_CTRL_AGU_SM_TOTAL_CNTR 0xE02EC + +#define mmMME1_CTRL_EZSYNC_OUT_CREDIT 0xE02F0 + +#define mmMME1_CTRL_PCU_RL_SAT_SEC 0xE02F4 + +#define mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER 0xE02F8 + +#define mmMME1_CTRL_QM_SLV_LBW_CLK_EN 0xE02FC + +#define mmMME1_CTRL_SHADOW_0_STATUS 0xE0400 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0xE0408 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0xE040C + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0xE0410 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0xE0414 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0xE0418 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0xE041C + +#define mmMME1_CTRL_SHADOW_0_HEADER_LOW 0xE0420 + +#define mmMME1_CTRL_SHADOW_0_HEADER_HIGH 0xE0424 + +#define mmMME1_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0xE0428 + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0xE042C + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0xE0430 + +#define mmMME1_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0xE0434 + +#define mmMME1_CTRL_SHADOW_0_OUTER_LOOP 0xE0438 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0xE043C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0xE0440 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0xE0444 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0xE0448 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0xE044C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0xE0450 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0xE0454 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0xE0458 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0xE045C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0xE0460 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0xE0464 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0xE0468 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0xE046C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0xE0470 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0xE0474 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0xE0478 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0xE047C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0xE0480 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0484 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0xE0488 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0xE048C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0xE0490 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0xE0494 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0xE0498 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0xE049C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0xE04A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0xE04A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0xE04A8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0xE04AC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0xE04B0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0xE04B4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0xE04B8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0xE04BC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0xE04C0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0xE04C4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0xE04C8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0xE04CC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0xE04D0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0xE04D4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0xE04D8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0xE04DC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0xE04E0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0xE04E4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0xE04E8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0xE04EC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0xE04F0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE04F4 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE04F8 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE04FC + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0500 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0504 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0508 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0xE050C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0xE0510 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0xE0514 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0xE0518 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE051C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0520 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0524 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0528 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE052C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0xE0530 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0xE0534 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0xE0538 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0xE053C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0xE0540 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0xE0544 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0xE0548 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0xE054C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0xE0550 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0xE0554 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0xE0558 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0xE055C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0xE0560 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0xE0564 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0xE0568 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0xE056C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0xE0570 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0xE0574 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0xE0578 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0xE057C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0xE0580 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0xE0584 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0588 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE058C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0590 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0594 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0598 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE059C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0xE05A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0xE05A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0xE05A8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0xE05AC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE05B0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE05B4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE05B8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE05BC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE05C0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0xE05C4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0xE05C8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0xE05CC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0xE05D0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SB_REPEAT 0xE05D4 + +#define mmMME1_CTRL_SHADOW_0_DESC_RATE_LIMITER 0xE05D8 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE05DC + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE05E0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0xE05E4 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0xE05E8 + +#define mmMME1_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0xE05EC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_S 0xE05F0 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0xE05F4 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0xE05F8 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0xE05FC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0xE0600 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0xE0604 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0xE0608 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0xE060C + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0xE0610 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0xE0614 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0xE0618 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0xE061C + +#define mmMME1_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0xE0620 + +#define mmMME1_CTRL_SHADOW_0_DESC_DUMMY 0xE0624 + +#define mmMME1_CTRL_SHADOW_1_STATUS 0xE0680 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0xE0688 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0xE068C + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0xE0690 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0xE0694 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0xE0698 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0xE069C + +#define mmMME1_CTRL_SHADOW_1_HEADER_LOW 0xE06A0 + +#define mmMME1_CTRL_SHADOW_1_HEADER_HIGH 0xE06A4 + +#define mmMME1_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0xE06A8 + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0xE06AC + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0xE06B0 + +#define mmMME1_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0xE06B4 + +#define mmMME1_CTRL_SHADOW_1_OUTER_LOOP 0xE06B8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0xE06BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0xE06C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0xE06C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0xE06C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0xE06CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0xE06D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0xE06D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0xE06D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0xE06DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0xE06E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0xE06E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0xE06E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0xE06EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0xE06F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0xE06F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0xE06F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0xE06FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0xE0700 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0704 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0xE0708 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0xE070C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0xE0710 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0xE0714 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0xE0718 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0xE071C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0xE0720 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0xE0724 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0xE0728 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0xE072C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0xE0730 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0xE0734 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0xE0738 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0xE073C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0xE0740 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0xE0744 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0xE0748 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0xE074C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0xE0750 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0xE0754 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0xE0758 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0xE075C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0xE0760 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0xE0764 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0xE0768 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0xE076C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0xE0770 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0774 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0778 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE077C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0780 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0784 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0788 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0xE078C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0xE0790 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0xE0794 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0xE0798 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE079C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE07A0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE07A4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE07A8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE07AC + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0xE07B0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0xE07B4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0xE07B8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0xE07BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0xE07C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0xE07C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0xE07C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0xE07CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0xE07D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0xE07D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0xE07D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0xE07DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0xE07E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0xE07E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0xE07E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0xE07EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0xE07F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0xE07F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0xE07F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0xE07FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0xE0800 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0xE0804 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0808 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE080C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0810 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0814 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0818 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE081C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0xE0820 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0xE0824 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0xE0828 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0xE082C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0830 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0834 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0838 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE083C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0840 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0xE0844 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0xE0848 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0xE084C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0xE0850 + +#define mmMME1_CTRL_SHADOW_1_DESC_SB_REPEAT 0xE0854 + +#define mmMME1_CTRL_SHADOW_1_DESC_RATE_LIMITER 0xE0858 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE085C + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0860 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0864 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0xE0868 + +#define mmMME1_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0xE086C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_S 0xE0870 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0xE0874 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0xE0878 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0xE087C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0xE0880 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0xE0884 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0xE0888 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0xE088C + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0xE0890 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0xE0894 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0xE0898 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0xE089C + +#define mmMME1_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0xE08A0 + +#define mmMME1_CTRL_SHADOW_1_DESC_DUMMY 0xE08A4 + +#define mmMME1_CTRL_SHADOW_2_STATUS 0xE0900 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0xE0908 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0xE090C + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0xE0910 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0xE0914 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0xE0918 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0xE091C + +#define mmMME1_CTRL_SHADOW_2_HEADER_LOW 0xE0920 + +#define mmMME1_CTRL_SHADOW_2_HEADER_HIGH 0xE0924 + +#define mmMME1_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0xE0928 + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0xE092C + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0xE0930 + +#define mmMME1_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0xE0934 + +#define mmMME1_CTRL_SHADOW_2_OUTER_LOOP 0xE0938 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0xE093C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0xE0940 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0xE0944 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0xE0948 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0xE094C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0xE0950 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0xE0954 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0xE0958 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0xE095C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0xE0960 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0xE0964 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0xE0968 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0xE096C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0xE0970 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0xE0974 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0xE0978 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0xE097C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0xE0980 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0984 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0xE0988 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0xE098C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0xE0990 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0xE0994 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0xE0998 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0xE099C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0xE09A0 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0xE09A4 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0xE09A8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0xE09AC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0xE09B0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0xE09B4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0xE09B8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0xE09BC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0xE09C0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0xE09C4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0xE09C8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0xE09CC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0xE09D0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0xE09D4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0xE09D8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0xE09DC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0xE09E0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0xE09E4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0xE09E8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0xE09EC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0xE09F0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE09F4 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE09F8 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE09FC + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0A00 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0A04 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0A08 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0xE0A0C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0xE0A10 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0xE0A14 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0xE0A18 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0A1C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0A20 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0A24 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0A28 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0A2C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0xE0A30 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0xE0A34 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0xE0A38 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0xE0A3C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0xE0A40 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0xE0A44 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0xE0A48 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0xE0A4C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0xE0A50 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0xE0A54 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0xE0A58 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0xE0A5C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0xE0A60 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0xE0A64 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0xE0A68 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0xE0A6C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0xE0A70 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0xE0A74 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0xE0A78 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0xE0A7C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0xE0A80 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0xE0A84 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0A88 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0A8C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0A90 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0A94 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0A98 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0A9C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0xE0AA0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0xE0AA4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0xE0AA8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0xE0AAC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0AB0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0AB4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0AB8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0ABC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0AC0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0xE0AC4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0xE0AC8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0xE0ACC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0xE0AD0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SB_REPEAT 0xE0AD4 + +#define mmMME1_CTRL_SHADOW_2_DESC_RATE_LIMITER 0xE0AD8 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0ADC + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0AE0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0AE4 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0xE0AE8 + +#define mmMME1_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0xE0AEC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_S 0xE0AF0 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0xE0AF4 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0xE0AF8 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0xE0AFC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0xE0B00 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0xE0B04 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0xE0B08 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0xE0B0C + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0xE0B10 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0xE0B14 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0xE0B18 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0xE0B1C + +#define mmMME1_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0xE0B20 + +#define mmMME1_CTRL_SHADOW_2_DESC_DUMMY 0xE0B24 + +#define mmMME1_CTRL_SHADOW_3_STATUS 0xE0B80 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0xE0B88 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0xE0B8C + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0xE0B90 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0xE0B94 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0xE0B98 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0xE0B9C + +#define mmMME1_CTRL_SHADOW_3_HEADER_LOW 0xE0BA0 + +#define mmMME1_CTRL_SHADOW_3_HEADER_HIGH 0xE0BA4 + +#define mmMME1_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0xE0BA8 + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0xE0BAC + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0xE0BB0 + +#define mmMME1_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0xE0BB4 + +#define mmMME1_CTRL_SHADOW_3_OUTER_LOOP 0xE0BB8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0xE0BBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0xE0BC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0xE0BC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0xE0BC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0xE0BCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0xE0BD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0xE0BD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0xE0BD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0xE0BDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0xE0BE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0xE0BE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0xE0BE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0xE0BEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0xE0BF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0xE0BF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0xE0BF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0xE0BFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0xE0C00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0C04 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0xE0C08 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0xE0C0C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0xE0C10 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0xE0C14 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0xE0C18 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0xE0C1C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0xE0C20 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0xE0C24 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0xE0C28 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0xE0C2C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0xE0C30 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0xE0C34 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0xE0C38 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0xE0C3C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0xE0C40 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0xE0C44 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0xE0C48 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0xE0C4C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0xE0C50 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0xE0C54 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0xE0C58 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0xE0C5C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0xE0C60 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0xE0C64 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0xE0C68 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0xE0C6C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0xE0C70 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0C74 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0C78 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE0C7C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0C80 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0C84 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0C88 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0xE0C8C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0xE0C90 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0xE0C94 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0xE0C98 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0C9C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0CA0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0CA4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0CA8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0CAC + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0xE0CB0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0xE0CB4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0xE0CB8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0xE0CBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0xE0CC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0xE0CC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0xE0CC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0xE0CCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0xE0CD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0xE0CD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0xE0CD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0xE0CDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0xE0CE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0xE0CE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0xE0CE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0xE0CEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0xE0CF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0xE0CF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0xE0CF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0xE0CFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0xE0D00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0xE0D04 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0D08 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0D0C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0D10 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0D14 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0D18 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0D1C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0xE0D20 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0xE0D24 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0xE0D28 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0xE0D2C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0D30 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0D34 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0D38 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0D3C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0D40 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0xE0D44 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0xE0D48 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0xE0D4C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0xE0D50 + +#define mmMME1_CTRL_SHADOW_3_DESC_SB_REPEAT 0xE0D54 + +#define mmMME1_CTRL_SHADOW_3_DESC_RATE_LIMITER 0xE0D58 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0D5C + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0D60 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0D64 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0xE0D68 + +#define mmMME1_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0xE0D6C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_S 0xE0D70 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0xE0D74 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0xE0D78 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0xE0D7C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0xE0D80 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0xE0D84 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0xE0D88 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0xE0D8C + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0xE0D90 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0xE0D94 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0xE0D98 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0xE0D9C + +#define mmMME1_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0xE0DA0 + +#define mmMME1_CTRL_SHADOW_3_DESC_DUMMY 0xE0DA4 + +#endif /* ASIC_REG_MME1_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h new file mode 100644 index 000000000..a1f2eb8b9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_CTRL_REGS_H_ +#define ASIC_REG_MME2_CTRL_REGS_H_ + +/* + ***************************************** + * MME2_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME2_CTRL_ARCH_STATUS 0x160000 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_S 0x160008 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_L 0x16000C + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_O 0x160010 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_S 0x160014 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_L 0x160018 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_O 0x16001C + +#define mmMME2_CTRL_ARCH_HEADER_LOW 0x160020 + +#define mmMME2_CTRL_ARCH_HEADER_HIGH 0x160024 + +#define mmMME2_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x160028 + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x16002C + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x160030 + +#define mmMME2_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x160034 + +#define mmMME2_CTRL_ARCH_OUTER_LOOP 0x160038 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x16003C + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x160040 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x160044 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x160048 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x16004C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x160050 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x160054 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x160058 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x16005C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x160060 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x160064 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x160068 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x16006C + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x160070 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x160074 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x160078 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x16007C + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x160080 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160084 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x160088 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x16008C + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x160090 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x160094 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x160098 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_0 0x16009C + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1600A0 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1600A4 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1600A8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1600AC + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1600B0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1600B4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1600B8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1600BC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1600C0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1600C4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1600C8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1600CC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1600D0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1600D4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1600D8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1600DC + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1600E0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1600E4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1600E8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1600EC + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1600F0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1600F4 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1600F8 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1600FC + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160100 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160104 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160108 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x16010C + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x160110 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x160114 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x160118 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16011C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160120 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160124 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160128 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16012C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x160130 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x160134 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x160138 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x16013C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x160140 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x160144 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x160148 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x16014C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x160150 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x160154 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x160158 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x16015C + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x160160 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x160164 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x160168 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x16016C + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x160170 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x160174 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x160178 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x16017C + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x160180 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x160184 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160188 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16018C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160190 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160194 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160198 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16019C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1601A0 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1601A4 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1601A8 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1601AC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1601B0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1601B4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1601B8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1601BC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1601C0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1601C4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1601C8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1601CC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1601D0 + +#define mmMME2_CTRL_ARCH_DESC_SB_REPEAT 0x1601D4 + +#define mmMME2_CTRL_ARCH_DESC_RATE_LIMITER 0x1601D8 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1601DC + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1601E0 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1601E4 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1601E8 + +#define mmMME2_CTRL_ARCH_DESC_AXI_USER_DATA 0x1601EC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_S 0x1601F0 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1601F4 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1601F8 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1601FC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x160200 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_S 0x160204 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_L 0x160208 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_S 0x16020C + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x160210 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x160214 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x160218 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x16021C + +#define mmMME2_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x160220 + +#define mmMME2_CTRL_ARCH_DESC_DUMMY 0x160224 + +#define mmMME2_CTRL_CMD 0x160280 + +#define mmMME2_CTRL_STATUS1 0x160284 + +#define mmMME2_CTRL_RESET 0x160288 + +#define mmMME2_CTRL_QM_STALL 0x16028C + +#define mmMME2_CTRL_SYNC_OBJECT_FIFO_TH 0x160290 + +#define mmMME2_CTRL_EUS_ROLLUP_CNT_ADD 0x160294 + +#define mmMME2_CTRL_INTR_CAUSE 0x160298 + +#define mmMME2_CTRL_INTR_MASK 0x16029C + +#define mmMME2_CTRL_LOG_SHADOW 0x1602A0 + +#define mmMME2_CTRL_PCU_RL_DESC0 0x1602A4 + +#define mmMME2_CTRL_PCU_RL_TOKEN_UPDATE 0x1602A8 + +#define mmMME2_CTRL_PCU_RL_TH 0x1602AC + +#define mmMME2_CTRL_PCU_RL_MIN 0x1602B0 + +#define mmMME2_CTRL_PCU_RL_CTRL_EN 0x1602B4 + +#define mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1602B8 + +#define mmMME2_CTRL_PCU_DUMMY_A_BF16 0x1602BC + +#define mmMME2_CTRL_PCU_DUMMY_B_BF16 0x1602C0 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD 0x1602C4 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1602C8 + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD 0x1602CC + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1602D0 + +#define mmMME2_CTRL_PROT 0x1602D4 + +#define mmMME2_CTRL_EU_POWER_SAVE_DISABLE 0x1602D8 + +#define mmMME2_CTRL_CS_DBG_BLOCK_ID 0x1602DC + +#define mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT 0x1602E0 + +#define mmMME2_CTRL_TE_CLOSE_CGATE 0x1602E4 + +#define mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR 0x1602E8 + +#define mmMME2_CTRL_AGU_SM_TOTAL_CNTR 0x1602EC + +#define mmMME2_CTRL_EZSYNC_OUT_CREDIT 0x1602F0 + +#define mmMME2_CTRL_PCU_RL_SAT_SEC 0x1602F4 + +#define mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER 0x1602F8 + +#define mmMME2_CTRL_QM_SLV_LBW_CLK_EN 0x1602FC + +#define mmMME2_CTRL_SHADOW_0_STATUS 0x160400 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x160408 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x16040C + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x160410 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x160414 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x160418 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x16041C + +#define mmMME2_CTRL_SHADOW_0_HEADER_LOW 0x160420 + +#define mmMME2_CTRL_SHADOW_0_HEADER_HIGH 0x160424 + +#define mmMME2_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x160428 + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x16042C + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x160430 + +#define mmMME2_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x160434 + +#define mmMME2_CTRL_SHADOW_0_OUTER_LOOP 0x160438 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x16043C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x160440 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x160444 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x160448 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x16044C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x160450 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x160454 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x160458 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x16045C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x160460 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x160464 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x160468 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x16046C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x160470 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x160474 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x160478 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x16047C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x160480 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160484 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x160488 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x16048C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x160490 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x160494 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x160498 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x16049C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1604A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1604A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1604A8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1604AC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1604B0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1604B4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1604B8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1604BC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1604C0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1604C4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1604C8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1604CC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1604D0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1604D4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1604D8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1604DC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1604E0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1604E4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1604E8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1604EC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1604F0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1604F4 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1604F8 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1604FC + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160500 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160504 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160508 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x16050C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x160510 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x160514 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x160518 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16051C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160520 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160524 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160528 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16052C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x160530 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x160534 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x160538 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x16053C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x160540 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x160544 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x160548 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x16054C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x160550 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x160554 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x160558 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x16055C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x160560 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x160564 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x160568 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x16056C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x160570 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x160574 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x160578 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x16057C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x160580 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x160584 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160588 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16058C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160590 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160594 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160598 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16059C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1605A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1605A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1605A8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1605AC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1605B0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1605B4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1605B8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1605BC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1605C0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1605C4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1605C8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1605CC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1605D0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1605D4 + +#define mmMME2_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1605D8 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1605DC + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1605E0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1605E4 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1605E8 + +#define mmMME2_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1605EC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1605F0 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1605F4 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1605F8 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1605FC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x160600 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x160604 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x160608 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x16060C + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x160610 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x160614 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x160618 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x16061C + +#define mmMME2_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x160620 + +#define mmMME2_CTRL_SHADOW_0_DESC_DUMMY 0x160624 + +#define mmMME2_CTRL_SHADOW_1_STATUS 0x160680 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x160688 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x16068C + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x160690 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x160694 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x160698 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x16069C + +#define mmMME2_CTRL_SHADOW_1_HEADER_LOW 0x1606A0 + +#define mmMME2_CTRL_SHADOW_1_HEADER_HIGH 0x1606A4 + +#define mmMME2_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1606A8 + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1606AC + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1606B0 + +#define mmMME2_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1606B4 + +#define mmMME2_CTRL_SHADOW_1_OUTER_LOOP 0x1606B8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1606BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1606C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1606C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1606C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1606CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1606D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1606D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1606D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1606DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1606E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1606E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1606E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1606EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1606F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1606F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1606F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1606FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x160700 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160704 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x160708 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x16070C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x160710 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x160714 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x160718 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x16071C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x160720 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x160724 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x160728 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x16072C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x160730 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x160734 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x160738 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x16073C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x160740 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x160744 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x160748 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x16074C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x160750 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x160754 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x160758 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x16075C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x160760 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x160764 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x160768 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x16076C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x160770 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160774 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160778 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x16077C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160780 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160784 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160788 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x16078C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x160790 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x160794 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x160798 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16079C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1607A0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1607A4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1607A8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1607AC + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1607B0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1607B4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1607B8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1607BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1607C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1607C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1607C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1607CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1607D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1607D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1607D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1607DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1607E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1607E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1607E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1607EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1607F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1607F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1607F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1607FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x160800 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x160804 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160808 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16080C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160810 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160814 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160818 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16081C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x160820 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x160824 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x160828 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x16082C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160830 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160834 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160838 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x16083C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160840 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x160844 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x160848 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x16084C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x160850 + +#define mmMME2_CTRL_SHADOW_1_DESC_SB_REPEAT 0x160854 + +#define mmMME2_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x160858 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x16085C + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160860 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x160864 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x160868 + +#define mmMME2_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x16086C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x160870 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x160874 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x160878 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x16087C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x160880 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x160884 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x160888 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x16088C + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x160890 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x160894 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x160898 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x16089C + +#define mmMME2_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1608A0 + +#define mmMME2_CTRL_SHADOW_1_DESC_DUMMY 0x1608A4 + +#define mmMME2_CTRL_SHADOW_2_STATUS 0x160900 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x160908 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x16090C + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x160910 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x160914 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x160918 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x16091C + +#define mmMME2_CTRL_SHADOW_2_HEADER_LOW 0x160920 + +#define mmMME2_CTRL_SHADOW_2_HEADER_HIGH 0x160924 + +#define mmMME2_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x160928 + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x16092C + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x160930 + +#define mmMME2_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x160934 + +#define mmMME2_CTRL_SHADOW_2_OUTER_LOOP 0x160938 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x16093C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x160940 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x160944 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x160948 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x16094C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x160950 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x160954 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x160958 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x16095C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x160960 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x160964 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x160968 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x16096C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x160970 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x160974 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x160978 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x16097C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x160980 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160984 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x160988 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x16098C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x160990 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x160994 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x160998 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x16099C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1609A0 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1609A4 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1609A8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1609AC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1609B0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1609B4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1609B8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1609BC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1609C0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1609C4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1609C8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1609CC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1609D0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1609D4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1609D8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1609DC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1609E0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1609E4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1609E8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1609EC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1609F0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1609F4 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1609F8 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1609FC + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160A00 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160A04 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160A08 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x160A0C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x160A10 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x160A14 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x160A18 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160A1C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160A20 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160A24 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160A28 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160A2C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x160A30 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x160A34 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x160A38 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x160A3C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x160A40 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x160A44 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x160A48 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x160A4C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x160A50 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x160A54 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x160A58 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x160A5C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x160A60 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x160A64 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x160A68 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x160A6C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x160A70 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x160A74 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x160A78 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x160A7C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x160A80 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x160A84 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160A88 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160A8C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160A90 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160A94 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160A98 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160A9C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x160AA0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x160AA4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x160AA8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x160AAC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160AB0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160AB4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160AB8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160ABC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160AC0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x160AC4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x160AC8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x160ACC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x160AD0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SB_REPEAT 0x160AD4 + +#define mmMME2_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x160AD8 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160ADC + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160AE0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x160AE4 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x160AE8 + +#define mmMME2_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x160AEC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x160AF0 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x160AF4 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x160AF8 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x160AFC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x160B00 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x160B04 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x160B08 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x160B0C + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x160B10 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x160B14 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x160B18 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x160B1C + +#define mmMME2_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x160B20 + +#define mmMME2_CTRL_SHADOW_2_DESC_DUMMY 0x160B24 + +#define mmMME2_CTRL_SHADOW_3_STATUS 0x160B80 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x160B88 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x160B8C + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x160B90 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x160B94 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x160B98 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x160B9C + +#define mmMME2_CTRL_SHADOW_3_HEADER_LOW 0x160BA0 + +#define mmMME2_CTRL_SHADOW_3_HEADER_HIGH 0x160BA4 + +#define mmMME2_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x160BA8 + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x160BAC + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x160BB0 + +#define mmMME2_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x160BB4 + +#define mmMME2_CTRL_SHADOW_3_OUTER_LOOP 0x160BB8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x160BBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x160BC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x160BC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x160BC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x160BCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x160BD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x160BD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x160BD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x160BDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x160BE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x160BE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x160BE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x160BEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x160BF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x160BF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x160BF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x160BFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x160C00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160C04 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x160C08 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x160C0C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x160C10 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x160C14 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x160C18 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x160C1C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x160C20 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x160C24 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x160C28 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x160C2C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x160C30 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x160C34 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x160C38 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x160C3C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x160C40 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x160C44 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x160C48 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x160C4C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x160C50 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x160C54 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x160C58 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x160C5C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x160C60 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x160C64 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x160C68 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x160C6C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x160C70 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160C74 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160C78 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x160C7C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160C80 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160C84 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160C88 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x160C8C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x160C90 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x160C94 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x160C98 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160C9C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160CA0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160CA4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160CA8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160CAC + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x160CB0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x160CB4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x160CB8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x160CBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x160CC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x160CC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x160CC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x160CCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x160CD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x160CD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x160CD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x160CDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x160CE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x160CE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x160CE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x160CEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x160CF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x160CF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x160CF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x160CFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x160D00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x160D04 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160D08 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160D0C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160D10 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160D14 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160D18 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160D1C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x160D20 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x160D24 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x160D28 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x160D2C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160D30 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160D34 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160D38 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160D3C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160D40 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x160D44 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x160D48 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x160D4C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x160D50 + +#define mmMME2_CTRL_SHADOW_3_DESC_SB_REPEAT 0x160D54 + +#define mmMME2_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x160D58 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160D5C + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160D60 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x160D64 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x160D68 + +#define mmMME2_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x160D6C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x160D70 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x160D74 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x160D78 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x160D7C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x160D80 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x160D84 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x160D88 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x160D8C + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x160D90 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x160D94 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x160D98 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x160D9C + +#define mmMME2_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x160DA0 + +#define mmMME2_CTRL_SHADOW_3_DESC_DUMMY 0x160DA4 + +#endif /* ASIC_REG_MME2_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h new file mode 100644 index 000000000..c1ea6a422 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_QM_REGS_H_ +#define ASIC_REG_MME2_QM_REGS_H_ + +/* + ***************************************** + * MME2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME2_QM_GLBL_CFG0 0x168000 + +#define mmMME2_QM_GLBL_CFG1 0x168004 + +#define mmMME2_QM_GLBL_PROT 0x168008 + +#define mmMME2_QM_GLBL_ERR_CFG 0x16800C + +#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010 + +#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014 + +#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018 + +#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C + +#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034 + +#define mmMME2_QM_GLBL_STS0 0x168038 + +#define mmMME2_QM_GLBL_STS1_0 0x168040 + +#define mmMME2_QM_GLBL_STS1_1 0x168044 + +#define mmMME2_QM_GLBL_STS1_2 0x168048 + +#define mmMME2_QM_GLBL_STS1_3 0x16804C + +#define mmMME2_QM_GLBL_STS1_4 0x168050 + +#define mmMME2_QM_GLBL_MSG_EN_0 0x168054 + +#define mmMME2_QM_GLBL_MSG_EN_1 0x168058 + +#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C + +#define mmMME2_QM_GLBL_MSG_EN_3 0x168060 + +#define mmMME2_QM_GLBL_MSG_EN_4 0x168068 + +#define mmMME2_QM_PQ_BASE_LO_0 0x168070 + +#define mmMME2_QM_PQ_BASE_LO_1 0x168074 + +#define mmMME2_QM_PQ_BASE_LO_2 0x168078 + +#define mmMME2_QM_PQ_BASE_LO_3 0x16807C + +#define mmMME2_QM_PQ_BASE_HI_0 0x168080 + +#define mmMME2_QM_PQ_BASE_HI_1 0x168084 + +#define mmMME2_QM_PQ_BASE_HI_2 0x168088 + +#define mmMME2_QM_PQ_BASE_HI_3 0x16808C + +#define mmMME2_QM_PQ_SIZE_0 0x168090 + +#define mmMME2_QM_PQ_SIZE_1 0x168094 + +#define mmMME2_QM_PQ_SIZE_2 0x168098 + +#define mmMME2_QM_PQ_SIZE_3 0x16809C + +#define mmMME2_QM_PQ_PI_0 0x1680A0 + +#define mmMME2_QM_PQ_PI_1 0x1680A4 + +#define mmMME2_QM_PQ_PI_2 0x1680A8 + +#define mmMME2_QM_PQ_PI_3 0x1680AC + +#define mmMME2_QM_PQ_CI_0 0x1680B0 + +#define mmMME2_QM_PQ_CI_1 0x1680B4 + +#define mmMME2_QM_PQ_CI_2 0x1680B8 + +#define mmMME2_QM_PQ_CI_3 0x1680BC + +#define mmMME2_QM_PQ_CFG0_0 0x1680C0 + +#define mmMME2_QM_PQ_CFG0_1 0x1680C4 + +#define mmMME2_QM_PQ_CFG0_2 0x1680C8 + +#define mmMME2_QM_PQ_CFG0_3 0x1680CC + +#define mmMME2_QM_PQ_CFG1_0 0x1680D0 + +#define mmMME2_QM_PQ_CFG1_1 0x1680D4 + +#define mmMME2_QM_PQ_CFG1_2 0x1680D8 + +#define mmMME2_QM_PQ_CFG1_3 0x1680DC + +#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0 + +#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4 + +#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8 + +#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC + +#define mmMME2_QM_PQ_STS0_0 0x1680F0 + +#define mmMME2_QM_PQ_STS0_1 0x1680F4 + +#define mmMME2_QM_PQ_STS0_2 0x1680F8 + +#define mmMME2_QM_PQ_STS0_3 0x1680FC + +#define mmMME2_QM_PQ_STS1_0 0x168100 + +#define mmMME2_QM_PQ_STS1_1 0x168104 + +#define mmMME2_QM_PQ_STS1_2 0x168108 + +#define mmMME2_QM_PQ_STS1_3 0x16810C + +#define mmMME2_QM_CQ_CFG0_0 0x168110 + +#define mmMME2_QM_CQ_CFG0_1 0x168114 + +#define mmMME2_QM_CQ_CFG0_2 0x168118 + +#define mmMME2_QM_CQ_CFG0_3 0x16811C + +#define mmMME2_QM_CQ_CFG0_4 0x168120 + +#define mmMME2_QM_CQ_CFG1_0 0x168124 + +#define mmMME2_QM_CQ_CFG1_1 0x168128 + +#define mmMME2_QM_CQ_CFG1_2 0x16812C + +#define mmMME2_QM_CQ_CFG1_3 0x168130 + +#define mmMME2_QM_CQ_CFG1_4 0x168134 + +#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138 + +#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C + +#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140 + +#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144 + +#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148 + +#define mmMME2_QM_CQ_STS0_0 0x16814C + +#define mmMME2_QM_CQ_STS0_1 0x168150 + +#define mmMME2_QM_CQ_STS0_2 0x168154 + +#define mmMME2_QM_CQ_STS0_3 0x168158 + +#define mmMME2_QM_CQ_STS0_4 0x16815C + +#define mmMME2_QM_CQ_STS1_0 0x168160 + +#define mmMME2_QM_CQ_STS1_1 0x168164 + +#define mmMME2_QM_CQ_STS1_2 0x168168 + +#define mmMME2_QM_CQ_STS1_3 0x16816C + +#define mmMME2_QM_CQ_STS1_4 0x168170 + +#define mmMME2_QM_CQ_PTR_LO_0 0x168174 + +#define mmMME2_QM_CQ_PTR_HI_0 0x168178 + +#define mmMME2_QM_CQ_TSIZE_0 0x16817C + +#define mmMME2_QM_CQ_CTL_0 0x168180 + +#define mmMME2_QM_CQ_PTR_LO_1 0x168184 + +#define mmMME2_QM_CQ_PTR_HI_1 0x168188 + +#define mmMME2_QM_CQ_TSIZE_1 0x16818C + +#define mmMME2_QM_CQ_CTL_1 0x168190 + +#define mmMME2_QM_CQ_PTR_LO_2 0x168194 + +#define mmMME2_QM_CQ_PTR_HI_2 0x168198 + +#define mmMME2_QM_CQ_TSIZE_2 0x16819C + +#define mmMME2_QM_CQ_CTL_2 0x1681A0 + +#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4 + +#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8 + +#define mmMME2_QM_CQ_TSIZE_3 0x1681AC + +#define mmMME2_QM_CQ_CTL_3 0x1681B0 + +#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4 + +#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8 + +#define mmMME2_QM_CQ_TSIZE_4 0x1681BC + +#define mmMME2_QM_CQ_CTL_4 0x1681C0 + +#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4 + +#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8 + +#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC + +#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0 + +#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4 + +#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8 + +#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC + +#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0 + +#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4 + +#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8 + +#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC + +#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0 + +#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4 + +#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8 + +#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC + +#define mmMME2_QM_CQ_CTL_STS_0 0x168200 + +#define mmMME2_QM_CQ_CTL_STS_1 0x168204 + +#define mmMME2_QM_CQ_CTL_STS_2 0x168208 + +#define mmMME2_QM_CQ_CTL_STS_3 0x16820C + +#define mmMME2_QM_CQ_CTL_STS_4 0x168210 + +#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214 + +#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218 + +#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C + +#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220 + +#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304 + +#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308 + +#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C + +#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310 + +#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314 + +#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318 + +#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C + +#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320 + +#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324 + +#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328 + +#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C + +#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330 + +#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334 + +#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338 + +#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C + +#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340 + +#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344 + +#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348 + +#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C + +#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350 + +#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354 + +#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358 + +#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C + +#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360 + +#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364 + +#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368 + +#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C + +#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370 + +#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374 + +#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378 + +#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C + +#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380 + +#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384 + +#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388 + +#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C + +#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390 + +#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394 + +#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398 + +#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C + +#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0 + +#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4 + +#define mmMME2_QM_CP_STS_0 0x1683A8 + +#define mmMME2_QM_CP_STS_1 0x1683AC + +#define mmMME2_QM_CP_STS_2 0x1683B0 + +#define mmMME2_QM_CP_STS_3 0x1683B4 + +#define mmMME2_QM_CP_STS_4 0x1683B8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC + +#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0 + +#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4 + +#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC + +#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0 + +#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4 + +#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8 + +#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC + +#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0 + +#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4 + +#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8 + +#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC + +#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400 + +#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404 + +#define mmMME2_QM_CP_DBG_0_0 0x168408 + +#define mmMME2_QM_CP_DBG_0_1 0x16840C + +#define mmMME2_QM_CP_DBG_0_2 0x168410 + +#define mmMME2_QM_CP_DBG_0_3 0x168414 + +#define mmMME2_QM_CP_DBG_0_4 0x168418 + +#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C + +#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420 + +#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424 + +#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428 + +#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C + +#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430 + +#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434 + +#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438 + +#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C + +#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440 + +#define mmMME2_QM_ARB_CFG_0 0x168A00 + +#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04 + +#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08 + +#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C + +#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10 + +#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14 + +#define mmMME2_QM_ARB_CFG_1 0x168A18 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C + +#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20 + +#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28 + +#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C + +#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34 + +#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38 + +#define mmMME2_QM_ARB_SLV_ID 0x168B3C + +#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44 + +#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48 + +#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C + +#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50 + +#define mmMME2_QM_ARB_BASE_LO 0x168B54 + +#define mmMME2_QM_ARB_BASE_HI 0x168B58 + +#define mmMME2_QM_ARB_STATE_STS 0x168B80 + +#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84 + +#define mmMME2_QM_ARB_MSG_STS 0x168B88 + +#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C + +#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C + +#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0 + +#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8 + +#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0 + +#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4 + +#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8 + +#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC + +#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0 + +#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4 + +#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8 + +#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC + +#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0 + +#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4 + +#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8 + +#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC + +#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0 + +#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4 + +#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8 + +#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC + +#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0 + +#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4 + +#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8 + +#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC + +#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00 + +#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04 + +#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08 + +#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C + +#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10 + +#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14 + +#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18 + +#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C + +#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20 + +#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24 + +#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28 + +#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C + +#define mmMME2_QM_CGM_CFG 0x168C70 + +#define mmMME2_QM_CGM_STS 0x168C74 + +#define mmMME2_QM_CGM_CFG1 0x168C78 + +#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80 + +#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84 + +#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90 + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0 + +#define mmMME2_QM_GLBL_AXCACHE 0x168CA4 + +#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0 + +#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4 + +#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8 + +#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC + +#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0 + +#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4 + +#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8 + +#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00 + +#endif /* ASIC_REG_MME2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h new file mode 100644 index 000000000..36f6edc72 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME3_CTRL_REGS_H_ +#define ASIC_REG_MME3_CTRL_REGS_H_ + +/* + ***************************************** + * MME3_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME3_CTRL_ARCH_STATUS 0x1E0000 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S 0x1E0008 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L 0x1E000C + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O 0x1E0010 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S 0x1E0014 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L 0x1E0018 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O 0x1E001C + +#define mmMME3_CTRL_ARCH_HEADER_LOW 0x1E0020 + +#define mmMME3_CTRL_ARCH_HEADER_HIGH 0x1E0024 + +#define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x1E0028 + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x1E002C + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x1E0030 + +#define mmMME3_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x1E0034 + +#define mmMME3_CTRL_ARCH_OUTER_LOOP 0x1E0038 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x1E003C + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x1E0040 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x1E0044 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x1E0048 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x1E004C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x1E0050 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x1E0054 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x1E0058 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x1E005C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x1E0060 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x1E0064 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x1E0068 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x1E006C + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x1E0070 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x1E0074 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x1E0078 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x1E007C + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x1E0080 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0084 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x1E0088 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x1E008C + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x1E0090 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x1E0094 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x1E0098 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_0 0x1E009C + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1E00A0 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1E00A4 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1E00A8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1E00AC + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1E00B0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1E00B4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1E00B8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1E00BC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1E00C0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1E00C4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1E00C8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1E00CC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1E00D0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1E00D4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1E00D8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1E00DC + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1E00E0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1E00E4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1E00E8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1E00EC + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1E00F0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E00F4 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E00F8 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E00FC + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0100 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0104 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0108 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x1E010C + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x1E0110 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x1E0114 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x1E0118 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E011C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0120 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0124 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0128 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E012C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x1E0130 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x1E0134 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x1E0138 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x1E013C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x1E0140 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x1E0144 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x1E0148 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x1E014C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x1E0150 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x1E0154 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x1E0158 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x1E015C + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x1E0160 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x1E0164 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x1E0168 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x1E016C + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x1E0170 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x1E0174 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x1E0178 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x1E017C + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x1E0180 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x1E0184 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0188 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E018C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0190 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0194 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0198 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E019C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1E01A0 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1E01A4 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1E01A8 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1E01AC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E01B0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E01B4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E01B8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E01BC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E01C0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1E01C4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1E01C8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1E01CC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1E01D0 + +#define mmMME3_CTRL_ARCH_DESC_SB_REPEAT 0x1E01D4 + +#define mmMME3_CTRL_ARCH_DESC_RATE_LIMITER 0x1E01D8 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E01DC + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E01E0 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E01E4 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1E01E8 + +#define mmMME3_CTRL_ARCH_DESC_AXI_USER_DATA 0x1E01EC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_S 0x1E01F0 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1E01F4 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1E01F8 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1E01FC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x1E0200 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_S 0x1E0204 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_L 0x1E0208 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_S 0x1E020C + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x1E0210 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x1E0214 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x1E0218 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x1E021C + +#define mmMME3_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x1E0220 + +#define mmMME3_CTRL_ARCH_DESC_DUMMY 0x1E0224 + +#define mmMME3_CTRL_CMD 0x1E0280 + +#define mmMME3_CTRL_STATUS1 0x1E0284 + +#define mmMME3_CTRL_RESET 0x1E0288 + +#define mmMME3_CTRL_QM_STALL 0x1E028C + +#define mmMME3_CTRL_SYNC_OBJECT_FIFO_TH 0x1E0290 + +#define mmMME3_CTRL_EUS_ROLLUP_CNT_ADD 0x1E0294 + +#define mmMME3_CTRL_INTR_CAUSE 0x1E0298 + +#define mmMME3_CTRL_INTR_MASK 0x1E029C + +#define mmMME3_CTRL_LOG_SHADOW 0x1E02A0 + +#define mmMME3_CTRL_PCU_RL_DESC0 0x1E02A4 + +#define mmMME3_CTRL_PCU_RL_TOKEN_UPDATE 0x1E02A8 + +#define mmMME3_CTRL_PCU_RL_TH 0x1E02AC + +#define mmMME3_CTRL_PCU_RL_MIN 0x1E02B0 + +#define mmMME3_CTRL_PCU_RL_CTRL_EN 0x1E02B4 + +#define mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1E02B8 + +#define mmMME3_CTRL_PCU_DUMMY_A_BF16 0x1E02BC + +#define mmMME3_CTRL_PCU_DUMMY_B_BF16 0x1E02C0 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD 0x1E02C4 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1E02C8 + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD 0x1E02CC + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1E02D0 + +#define mmMME3_CTRL_PROT 0x1E02D4 + +#define mmMME3_CTRL_EU_POWER_SAVE_DISABLE 0x1E02D8 + +#define mmMME3_CTRL_CS_DBG_BLOCK_ID 0x1E02DC + +#define mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT 0x1E02E0 + +#define mmMME3_CTRL_TE_CLOSE_CGATE 0x1E02E4 + +#define mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR 0x1E02E8 + +#define mmMME3_CTRL_AGU_SM_TOTAL_CNTR 0x1E02EC + +#define mmMME3_CTRL_EZSYNC_OUT_CREDIT 0x1E02F0 + +#define mmMME3_CTRL_PCU_RL_SAT_SEC 0x1E02F4 + +#define mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER 0x1E02F8 + +#define mmMME3_CTRL_QM_SLV_LBW_CLK_EN 0x1E02FC + +#define mmMME3_CTRL_SHADOW_0_STATUS 0x1E0400 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x1E0408 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x1E040C + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x1E0410 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x1E0414 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x1E0418 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x1E041C + +#define mmMME3_CTRL_SHADOW_0_HEADER_LOW 0x1E0420 + +#define mmMME3_CTRL_SHADOW_0_HEADER_HIGH 0x1E0424 + +#define mmMME3_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x1E0428 + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x1E042C + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x1E0430 + +#define mmMME3_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x1E0434 + +#define mmMME3_CTRL_SHADOW_0_OUTER_LOOP 0x1E0438 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x1E043C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x1E0440 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x1E0444 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x1E0448 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x1E044C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x1E0450 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x1E0454 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x1E0458 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x1E045C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x1E0460 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x1E0464 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x1E0468 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x1E046C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x1E0470 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x1E0474 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x1E0478 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x1E047C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x1E0480 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0484 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x1E0488 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x1E048C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x1E0490 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x1E0494 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x1E0498 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x1E049C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1E04A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1E04A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1E04A8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1E04AC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1E04B0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1E04B4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1E04B8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1E04BC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1E04C0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1E04C4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1E04C8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1E04CC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1E04D0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1E04D4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1E04D8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1E04DC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1E04E0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1E04E4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1E04E8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1E04EC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1E04F0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E04F4 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E04F8 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E04FC + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0500 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0504 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0508 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x1E050C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x1E0510 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x1E0514 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x1E0518 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E051C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0520 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0524 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0528 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E052C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x1E0530 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x1E0534 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x1E0538 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x1E053C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x1E0540 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x1E0544 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x1E0548 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x1E054C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x1E0550 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x1E0554 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x1E0558 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x1E055C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x1E0560 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x1E0564 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x1E0568 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x1E056C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x1E0570 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x1E0574 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x1E0578 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x1E057C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x1E0580 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x1E0584 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0588 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E058C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0590 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0594 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0598 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E059C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1E05A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1E05A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1E05A8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1E05AC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E05B0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E05B4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E05B8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E05BC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E05C0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1E05C4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1E05C8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1E05CC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1E05D0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1E05D4 + +#define mmMME3_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1E05D8 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E05DC + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E05E0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E05E4 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1E05E8 + +#define mmMME3_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1E05EC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1E05F0 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1E05F4 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1E05F8 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1E05FC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x1E0600 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x1E0604 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x1E0608 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x1E060C + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x1E0610 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x1E0614 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x1E0618 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x1E061C + +#define mmMME3_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x1E0620 + +#define mmMME3_CTRL_SHADOW_0_DESC_DUMMY 0x1E0624 + +#define mmMME3_CTRL_SHADOW_1_STATUS 0x1E0680 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x1E0688 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x1E068C + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x1E0690 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x1E0694 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x1E0698 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x1E069C + +#define mmMME3_CTRL_SHADOW_1_HEADER_LOW 0x1E06A0 + +#define mmMME3_CTRL_SHADOW_1_HEADER_HIGH 0x1E06A4 + +#define mmMME3_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1E06A8 + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1E06AC + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1E06B0 + +#define mmMME3_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1E06B4 + +#define mmMME3_CTRL_SHADOW_1_OUTER_LOOP 0x1E06B8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1E06BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1E06C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1E06C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1E06C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1E06CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1E06D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1E06D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1E06D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1E06DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1E06E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1E06E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1E06E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1E06EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1E06F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1E06F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1E06F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1E06FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x1E0700 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0704 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x1E0708 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x1E070C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x1E0710 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x1E0714 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x1E0718 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x1E071C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x1E0720 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x1E0724 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x1E0728 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x1E072C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x1E0730 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x1E0734 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x1E0738 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x1E073C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x1E0740 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x1E0744 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x1E0748 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x1E074C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x1E0750 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x1E0754 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x1E0758 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x1E075C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x1E0760 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x1E0764 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x1E0768 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x1E076C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x1E0770 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0774 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0778 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E077C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0780 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0784 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0788 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x1E078C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x1E0790 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x1E0794 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x1E0798 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E079C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E07A0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E07A4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E07A8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E07AC + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1E07B0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1E07B4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1E07B8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1E07BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1E07C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1E07C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1E07C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1E07CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1E07D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1E07D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1E07D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1E07DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1E07E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1E07E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1E07E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1E07EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1E07F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1E07F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1E07F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1E07FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x1E0800 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x1E0804 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0808 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E080C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0810 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0814 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0818 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E081C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x1E0820 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x1E0824 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x1E0828 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x1E082C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0830 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0834 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0838 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E083C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0840 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x1E0844 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x1E0848 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x1E084C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x1E0850 + +#define mmMME3_CTRL_SHADOW_1_DESC_SB_REPEAT 0x1E0854 + +#define mmMME3_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x1E0858 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E085C + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0860 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0864 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x1E0868 + +#define mmMME3_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x1E086C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x1E0870 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x1E0874 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x1E0878 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x1E087C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x1E0880 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x1E0884 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x1E0888 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x1E088C + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x1E0890 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x1E0894 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x1E0898 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x1E089C + +#define mmMME3_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1E08A0 + +#define mmMME3_CTRL_SHADOW_1_DESC_DUMMY 0x1E08A4 + +#define mmMME3_CTRL_SHADOW_2_STATUS 0x1E0900 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x1E0908 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x1E090C + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x1E0910 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x1E0914 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x1E0918 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x1E091C + +#define mmMME3_CTRL_SHADOW_2_HEADER_LOW 0x1E0920 + +#define mmMME3_CTRL_SHADOW_2_HEADER_HIGH 0x1E0924 + +#define mmMME3_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x1E0928 + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x1E092C + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x1E0930 + +#define mmMME3_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x1E0934 + +#define mmMME3_CTRL_SHADOW_2_OUTER_LOOP 0x1E0938 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x1E093C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x1E0940 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x1E0944 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x1E0948 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x1E094C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x1E0950 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x1E0954 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x1E0958 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x1E095C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x1E0960 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x1E0964 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x1E0968 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x1E096C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x1E0970 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x1E0974 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x1E0978 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x1E097C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x1E0980 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0984 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x1E0988 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x1E098C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x1E0990 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x1E0994 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x1E0998 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x1E099C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1E09A0 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1E09A4 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1E09A8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1E09AC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1E09B0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1E09B4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1E09B8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1E09BC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1E09C0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1E09C4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1E09C8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1E09CC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1E09D0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1E09D4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1E09D8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1E09DC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1E09E0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1E09E4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1E09E8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1E09EC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1E09F0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E09F4 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E09F8 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E09FC + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0A00 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0A04 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0A08 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x1E0A0C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x1E0A10 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x1E0A14 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x1E0A18 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0A1C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0A20 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0A24 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0A28 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0A2C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x1E0A30 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x1E0A34 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x1E0A38 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x1E0A3C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x1E0A40 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x1E0A44 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x1E0A48 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x1E0A4C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x1E0A50 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x1E0A54 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x1E0A58 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x1E0A5C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x1E0A60 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x1E0A64 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x1E0A68 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x1E0A6C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x1E0A70 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x1E0A74 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x1E0A78 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x1E0A7C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x1E0A80 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x1E0A84 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0A88 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0A8C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0A90 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0A94 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0A98 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0A9C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x1E0AA0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x1E0AA4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x1E0AA8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x1E0AAC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0AB0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0AB4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0AB8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0ABC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0AC0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x1E0AC4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x1E0AC8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x1E0ACC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x1E0AD0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SB_REPEAT 0x1E0AD4 + +#define mmMME3_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x1E0AD8 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0ADC + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0AE0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0AE4 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x1E0AE8 + +#define mmMME3_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x1E0AEC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x1E0AF0 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x1E0AF4 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x1E0AF8 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x1E0AFC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x1E0B00 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x1E0B04 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x1E0B08 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x1E0B0C + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x1E0B10 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x1E0B14 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x1E0B18 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x1E0B1C + +#define mmMME3_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x1E0B20 + +#define mmMME3_CTRL_SHADOW_2_DESC_DUMMY 0x1E0B24 + +#define mmMME3_CTRL_SHADOW_3_STATUS 0x1E0B80 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x1E0B88 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x1E0B8C + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x1E0B90 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x1E0B94 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x1E0B98 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x1E0B9C + +#define mmMME3_CTRL_SHADOW_3_HEADER_LOW 0x1E0BA0 + +#define mmMME3_CTRL_SHADOW_3_HEADER_HIGH 0x1E0BA4 + +#define mmMME3_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x1E0BA8 + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x1E0BAC + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x1E0BB0 + +#define mmMME3_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x1E0BB4 + +#define mmMME3_CTRL_SHADOW_3_OUTER_LOOP 0x1E0BB8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x1E0BBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x1E0BC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x1E0BC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x1E0BC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x1E0BCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x1E0BD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x1E0BD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x1E0BD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x1E0BDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x1E0BE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x1E0BE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x1E0BE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x1E0BEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x1E0BF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x1E0BF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x1E0BF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x1E0BFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x1E0C00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0C04 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x1E0C08 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x1E0C0C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x1E0C10 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x1E0C14 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x1E0C18 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x1E0C1C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x1E0C20 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x1E0C24 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x1E0C28 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x1E0C2C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x1E0C30 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x1E0C34 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x1E0C38 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x1E0C3C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x1E0C40 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x1E0C44 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x1E0C48 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x1E0C4C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x1E0C50 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x1E0C54 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x1E0C58 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x1E0C5C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x1E0C60 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x1E0C64 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x1E0C68 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x1E0C6C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x1E0C70 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0C74 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0C78 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E0C7C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0C80 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0C84 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0C88 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x1E0C8C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x1E0C90 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x1E0C94 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x1E0C98 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0C9C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0CA0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0CA4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0CA8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0CAC + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x1E0CB0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x1E0CB4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x1E0CB8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x1E0CBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x1E0CC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x1E0CC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x1E0CC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x1E0CCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x1E0CD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x1E0CD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x1E0CD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x1E0CDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x1E0CE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x1E0CE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x1E0CE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x1E0CEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x1E0CF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x1E0CF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x1E0CF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x1E0CFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x1E0D00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x1E0D04 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0D08 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0D0C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0D10 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0D14 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0D18 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0D1C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x1E0D20 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x1E0D24 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x1E0D28 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x1E0D2C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0D30 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0D34 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0D38 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0D3C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0D40 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x1E0D44 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x1E0D48 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x1E0D4C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x1E0D50 + +#define mmMME3_CTRL_SHADOW_3_DESC_SB_REPEAT 0x1E0D54 + +#define mmMME3_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x1E0D58 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0D5C + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0D60 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0D64 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x1E0D68 + +#define mmMME3_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x1E0D6C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x1E0D70 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x1E0D74 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x1E0D78 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x1E0D7C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x1E0D80 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x1E0D84 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x1E0D88 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x1E0D8C + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x1E0D90 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x1E0D94 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x1E0D98 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x1E0D9C + +#define mmMME3_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x1E0DA0 + +#define mmMME3_CTRL_SHADOW_3_DESC_DUMMY 0x1E0DA4 + +#endif /* ASIC_REG_MME3_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h new file mode 100644 index 000000000..61465b599 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_UP_REGS_H_ +#define ASIC_REG_MMU_UP_REGS_H_ + +/* + ***************************************** + * MMU_UP (Prototype: MMU) + ***************************************** + */ + +#define mmMMU_UP_MMU_ENABLE 0xC1100C + +#define mmMMU_UP_FORCE_ORDERING 0xC11010 + +#define mmMMU_UP_FEATURE_ENABLE 0xC11014 + +#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 + +#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C + +#define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 + +#define mmMMU_UP_SCRAMBLER 0xC11024 + +#define mmMMU_UP_MEM_INIT_BUSY 0xC11028 + +#define mmMMU_UP_SPI_MASK 0xC1102C + +#define mmMMU_UP_SPI_CAUSE 0xC11030 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 + +#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 + +#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 + +#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C + +#define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 + +#define mmMMU_UP_SLICE_CREDIT 0xC11054 + +#define mmMMU_UP_PIPE_CREDIT 0xC11058 + +#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C + +#define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 + +#define mmMMU_UP_RAZWI_READ_VLD 0xC11064 + +#define mmMMU_UP_RAZWI_READ_ID 0xC11068 + +#define mmMMU_UP_MMU_BYPASS 0xC1106C + +#endif /* ASIC_REG_MMU_UP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h new file mode 100644 index 000000000..bd37b6452 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_MASKS_H_ +#define ASIC_REG_NIC0_QM0_MASKS_H_ + +/* + ***************************************** + * NIC0_QM0 (Prototype: QMAN) + ***************************************** + */ + +/* NIC0_QM0_GLBL_CFG0 */ +#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0 +#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF +#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT 4 +#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT 9 +#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* NIC0_QM0_GLBL_CFG1 */ +#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF +#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT 9 +#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* NIC0_QM0_GLBL_PROT */ +#define NIC0_QM0_GLBL_PROT_PQF_SHIFT 0 +#define NIC0_QM0_GLBL_PROT_PQF_MASK 0xF +#define NIC0_QM0_GLBL_PROT_CQF_SHIFT 4 +#define NIC0_QM0_GLBL_PROT_CQF_MASK 0x1F0 +#define NIC0_QM0_GLBL_PROT_CP_SHIFT 9 +#define NIC0_QM0_GLBL_PROT_CP_MASK 0x3E00 +#define NIC0_QM0_GLBL_PROT_ERR_SHIFT 14 +#define NIC0_QM0_GLBL_PROT_ERR_MASK 0x4000 +#define NIC0_QM0_GLBL_PROT_ARB_SHIFT 15 +#define NIC0_QM0_GLBL_PROT_ARB_MASK 0x8000 + +/* NIC0_QM0_GLBL_ERR_CFG */ +#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* NIC0_QM0_GLBL_SECURE_PROPS */ +#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* NIC0_QM0_GLBL_NON_SECURE_PROPS */ +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* NIC0_QM0_GLBL_STS0 */ +#define NIC0_QM0_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define NIC0_QM0_GLBL_STS0_PQF_IDLE_MASK 0xF +#define NIC0_QM0_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define NIC0_QM0_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define NIC0_QM0_GLBL_STS0_CP_IDLE_SHIFT 9 +#define NIC0_QM0_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* NIC0_QM0_GLBL_STS1 */ +#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* NIC0_QM0_GLBL_STS1_4 */ +#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* NIC0_QM0_GLBL_MSG_EN */ +#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* NIC0_QM0_GLBL_MSG_EN_4 */ +#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* NIC0_QM0_PQ_BASE_LO */ +#define NIC0_QM0_PQ_BASE_LO_VAL_SHIFT 0 +#define NIC0_QM0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_PQ_BASE_HI */ +#define NIC0_QM0_PQ_BASE_HI_VAL_SHIFT 0 +#define NIC0_QM0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_PQ_SIZE */ +#define NIC0_QM0_PQ_SIZE_VAL_SHIFT 0 +#define NIC0_QM0_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_PQ_PI */ +#define NIC0_QM0_PQ_PI_VAL_SHIFT 0 +#define NIC0_QM0_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_PQ_CI */ +#define NIC0_QM0_PQ_CI_VAL_SHIFT 0 +#define NIC0_QM0_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_PQ_CFG0 */ +#define NIC0_QM0_PQ_CFG0_RESERVED_SHIFT 0 +#define NIC0_QM0_PQ_CFG0_RESERVED_MASK 0x1 + +/* NIC0_QM0_PQ_CFG1 */ +#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* NIC0_QM0_PQ_ARUSER_31_11 */ +#define NIC0_QM0_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define NIC0_QM0_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* NIC0_QM0_PQ_STS0 */ +#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* NIC0_QM0_PQ_STS1 */ +#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define NIC0_QM0_PQ_STS1_PQ_BUSY_SHIFT 31 +#define NIC0_QM0_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* NIC0_QM0_CQ_CFG0 */ +#define NIC0_QM0_CQ_CFG0_RESERVED_SHIFT 0 +#define NIC0_QM0_CQ_CFG0_RESERVED_MASK 0x1 + +/* NIC0_QM0_CQ_CFG1 */ +#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_ARUSER_31_11 */ +#define NIC0_QM0_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define NIC0_QM0_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* NIC0_QM0_CQ_STS0 */ +#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_STS1 */ +#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define NIC0_QM0_CQ_STS1_CQ_BUSY_SHIFT 31 +#define NIC0_QM0_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* NIC0_QM0_CQ_PTR_LO_0 */ +#define NIC0_QM0_CQ_PTR_LO_0_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_0 */ +#define NIC0_QM0_CQ_PTR_HI_0_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_0 */ +#define NIC0_QM0_CQ_TSIZE_0_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_0 */ +#define NIC0_QM0_CQ_CTL_0_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_0_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_0_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_PTR_LO_1 */ +#define NIC0_QM0_CQ_PTR_LO_1_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_1 */ +#define NIC0_QM0_CQ_PTR_HI_1_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_1 */ +#define NIC0_QM0_CQ_TSIZE_1_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_1 */ +#define NIC0_QM0_CQ_CTL_1_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_1_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_1_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_PTR_LO_2 */ +#define NIC0_QM0_CQ_PTR_LO_2_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_2 */ +#define NIC0_QM0_CQ_PTR_HI_2_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_2 */ +#define NIC0_QM0_CQ_TSIZE_2_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_2 */ +#define NIC0_QM0_CQ_CTL_2_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_2_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_2_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_PTR_LO_3 */ +#define NIC0_QM0_CQ_PTR_LO_3_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_3 */ +#define NIC0_QM0_CQ_PTR_HI_3_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_3 */ +#define NIC0_QM0_CQ_TSIZE_3_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_3 */ +#define NIC0_QM0_CQ_CTL_3_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_3_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_3_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_PTR_LO_4 */ +#define NIC0_QM0_CQ_PTR_LO_4_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_4 */ +#define NIC0_QM0_CQ_PTR_HI_4_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_4 */ +#define NIC0_QM0_CQ_TSIZE_4_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_4 */ +#define NIC0_QM0_CQ_CTL_4_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_4_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_4_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_PTR_LO_STS */ +#define NIC0_QM0_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_PTR_HI_STS */ +#define NIC0_QM0_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define NIC0_QM0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_TSIZE_STS */ +#define NIC0_QM0_CQ_TSIZE_STS_VAL_SHIFT 0 +#define NIC0_QM0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CQ_CTL_STS */ +#define NIC0_QM0_CQ_CTL_STS_RPT_SHIFT 0 +#define NIC0_QM0_CQ_CTL_STS_RPT_MASK 0xFFFF +#define NIC0_QM0_CQ_CTL_STS_CTL_SHIFT 16 +#define NIC0_QM0_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* NIC0_QM0_CQ_IFIFO_CNT */ +#define NIC0_QM0_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define NIC0_QM0_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* NIC0_QM0_CP_MSG_BASE0_ADDR_LO */ +#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE0_ADDR_HI */ +#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE1_ADDR_LO */ +#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE1_ADDR_HI */ +#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE2_ADDR_LO */ +#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE2_ADDR_HI */ +#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE3_ADDR_LO */ +#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_MSG_BASE3_ADDR_HI */ +#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_LDMA_TSIZE_OFFSET */ +#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET */ +#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_FENCE0_RDATA */ +#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* NIC0_QM0_CP_FENCE1_RDATA */ +#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* NIC0_QM0_CP_FENCE2_RDATA */ +#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* NIC0_QM0_CP_FENCE3_RDATA */ +#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* NIC0_QM0_CP_FENCE0_CNT */ +#define NIC0_QM0_CP_FENCE0_CNT_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* NIC0_QM0_CP_FENCE1_CNT */ +#define NIC0_QM0_CP_FENCE1_CNT_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* NIC0_QM0_CP_FENCE2_CNT */ +#define NIC0_QM0_CP_FENCE2_CNT_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* NIC0_QM0_CP_FENCE3_CNT */ +#define NIC0_QM0_CP_FENCE3_CNT_VAL_SHIFT 0 +#define NIC0_QM0_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* NIC0_QM0_CP_STS */ +#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define NIC0_QM0_CP_STS_ERDY_SHIFT 16 +#define NIC0_QM0_CP_STS_ERDY_MASK 0x10000 +#define NIC0_QM0_CP_STS_RRDY_SHIFT 17 +#define NIC0_QM0_CP_STS_RRDY_MASK 0x20000 +#define NIC0_QM0_CP_STS_MRDY_SHIFT 18 +#define NIC0_QM0_CP_STS_MRDY_MASK 0x40000 +#define NIC0_QM0_CP_STS_SW_STOP_SHIFT 19 +#define NIC0_QM0_CP_STS_SW_STOP_MASK 0x80000 +#define NIC0_QM0_CP_STS_FENCE_ID_SHIFT 20 +#define NIC0_QM0_CP_STS_FENCE_ID_MASK 0x300000 +#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* NIC0_QM0_CP_CURRENT_INST_LO */ +#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_CURRENT_INST_HI */ +#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_CP_BARRIER_CFG */ +#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* NIC0_QM0_CP_DBG_0 */ +#define NIC0_QM0_CP_DBG_0_CS_SHIFT 0 +#define NIC0_QM0_CP_DBG_0_CS_MASK 0xF +#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define NIC0_QM0_CP_DBG_0_MREB_STALL_SHIFT 6 +#define NIC0_QM0_CP_DBG_0_MREB_STALL_MASK 0x40 +#define NIC0_QM0_CP_DBG_0_STALL_SHIFT 7 +#define NIC0_QM0_CP_DBG_0_STALL_MASK 0x80 + +/* NIC0_QM0_CP_ARUSER_31_11 */ +#define NIC0_QM0_CP_ARUSER_31_11_VAL_SHIFT 0 +#define NIC0_QM0_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* NIC0_QM0_CP_AWUSER_31_11 */ +#define NIC0_QM0_CP_AWUSER_31_11_VAL_SHIFT 0 +#define NIC0_QM0_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* NIC0_QM0_ARB_CFG_0 */ +#define NIC0_QM0_ARB_CFG_0_TYPE_SHIFT 0 +#define NIC0_QM0_ARB_CFG_0_TYPE_MASK 0x1 +#define NIC0_QM0_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define NIC0_QM0_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define NIC0_QM0_ARB_CFG_0_EN_SHIFT 8 +#define NIC0_QM0_ARB_CFG_0_EN_MASK 0x100 +#define NIC0_QM0_ARB_CFG_0_MASK_SHIFT 12 +#define NIC0_QM0_ARB_CFG_0_MASK_MASK 0xF000 +#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* NIC0_QM0_ARB_CHOISE_Q_PUSH */ +#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* NIC0_QM0_ARB_WRR_WEIGHT */ +#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_CFG_1 */ +#define NIC0_QM0_ARB_CFG_1_CLR_SHIFT 0 +#define NIC0_QM0_ARB_CFG_1_CLR_MASK 0x1 + +/* NIC0_QM0_ARB_MST_AVAIL_CRED */ +#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* NIC0_QM0_ARB_MST_CRED_INC */ +#define NIC0_QM0_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST */ +#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST */ +#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_MST_SLAVE_EN */ +#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_MST_QUIET_PER */ +#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_SLV_CHOISE_WDT */ +#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_SLV_ID */ +#define NIC0_QM0_ARB_SLV_ID_VAL_SHIFT 0 +#define NIC0_QM0_ARB_SLV_ID_VAL_MASK 0x1F + +/* NIC0_QM0_ARB_MSG_MAX_INFLIGHT */ +#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* NIC0_QM0_ARB_MSG_AWUSER_31_11 */ +#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP */ +#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* NIC0_QM0_ARB_BASE_LO */ +#define NIC0_QM0_ARB_BASE_LO_VAL_SHIFT 0 +#define NIC0_QM0_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_BASE_HI */ +#define NIC0_QM0_ARB_BASE_HI_VAL_SHIFT 0 +#define NIC0_QM0_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_STATE_STS */ +#define NIC0_QM0_ARB_STATE_STS_VAL_SHIFT 0 +#define NIC0_QM0_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_ARB_CHOISE_FULLNESS_STS */ +#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* NIC0_QM0_ARB_MSG_STS */ +#define NIC0_QM0_ARB_MSG_STS_FULL_SHIFT 0 +#define NIC0_QM0_ARB_MSG_STS_FULL_MASK 0x1 +#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD */ +#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* NIC0_QM0_ARB_ERR_CAUSE */ +#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* NIC0_QM0_ARB_ERR_MSG_EN */ +#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* NIC0_QM0_ARB_ERR_STS_DRP */ +#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* NIC0_QM0_ARB_MST_CRED_STS */ +#define NIC0_QM0_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define NIC0_QM0_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* NIC0_QM0_CGM_CFG */ +#define NIC0_QM0_CGM_CFG_IDLE_TH_SHIFT 0 +#define NIC0_QM0_CGM_CFG_IDLE_TH_MASK 0xFFF +#define NIC0_QM0_CGM_CFG_G2F_TH_SHIFT 16 +#define NIC0_QM0_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define NIC0_QM0_CGM_CFG_EN_SHIFT 31 +#define NIC0_QM0_CGM_CFG_EN_MASK 0x80000000 + +/* NIC0_QM0_CGM_STS */ +#define NIC0_QM0_CGM_STS_ST_SHIFT 0 +#define NIC0_QM0_CGM_STS_ST_MASK 0x3 +#define NIC0_QM0_CGM_STS_CG_SHIFT 4 +#define NIC0_QM0_CGM_STS_CG_MASK 0x10 +#define NIC0_QM0_CGM_STS_AGENT_IDLE_SHIFT 8 +#define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK 0x100 +#define NIC0_QM0_CGM_STS_AXI_IDLE_SHIFT 9 +#define NIC0_QM0_CGM_STS_AXI_IDLE_MASK 0x200 +#define NIC0_QM0_CGM_STS_CP_IDLE_SHIFT 10 +#define NIC0_QM0_CGM_STS_CP_IDLE_MASK 0x400 + +/* NIC0_QM0_CGM_CFG1 */ +#define NIC0_QM0_CGM_CFG1_MASK_TH_SHIFT 0 +#define NIC0_QM0_CGM_CFG1_MASK_TH_MASK 0xFF + +/* NIC0_QM0_LOCAL_RANGE_BASE */ +#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* NIC0_QM0_LOCAL_RANGE_SIZE */ +#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* NIC0_QM0_CSMR_STRICT_PRIO_CFG */ +#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_1 */ +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_0 */ +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_1 */ +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_0 */ +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* NIC0_QM0_GLBL_AXCACHE */ +#define NIC0_QM0_GLBL_AXCACHE_AR_SHIFT 0 +#define NIC0_QM0_GLBL_AXCACHE_AR_MASK 0xF +#define NIC0_QM0_GLBL_AXCACHE_AW_SHIFT 16 +#define NIC0_QM0_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* NIC0_QM0_IND_GW_APB_CFG */ +#define NIC0_QM0_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define NIC0_QM0_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define NIC0_QM0_IND_GW_APB_CFG_CMD_SHIFT 31 +#define NIC0_QM0_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* NIC0_QM0_IND_GW_APB_WDATA */ +#define NIC0_QM0_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define NIC0_QM0_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_IND_GW_APB_RDATA */ +#define NIC0_QM0_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define NIC0_QM0_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_IND_GW_APB_STATUS */ +#define NIC0_QM0_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define NIC0_QM0_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define NIC0_QM0_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define NIC0_QM0_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* NIC0_QM0_GLBL_ERR_ADDR_LO */ +#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_GLBL_ERR_ADDR_HI */ +#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_GLBL_ERR_WDATA */ +#define NIC0_QM0_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define NIC0_QM0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* NIC0_QM0_GLBL_MEM_INIT_BUSY */ +#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_NIC0_QM0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h new file mode 100644 index 000000000..7c97f4041 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_REGS_H_ +#define ASIC_REG_NIC0_QM0_REGS_H_ + +/* + ***************************************** + * NIC0_QM0 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC0_QM0_GLBL_CFG0 0xCE0000 + +#define mmNIC0_QM0_GLBL_CFG1 0xCE0004 + +#define mmNIC0_QM0_GLBL_PROT 0xCE0008 + +#define mmNIC0_QM0_GLBL_ERR_CFG 0xCE000C + +#define mmNIC0_QM0_GLBL_SECURE_PROPS_0 0xCE0010 + +#define mmNIC0_QM0_GLBL_SECURE_PROPS_1 0xCE0014 + +#define mmNIC0_QM0_GLBL_SECURE_PROPS_2 0xCE0018 + +#define mmNIC0_QM0_GLBL_SECURE_PROPS_3 0xCE001C + +#define mmNIC0_QM0_GLBL_SECURE_PROPS_4 0xCE0020 + +#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 0xCE0024 + +#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 0xCE0028 + +#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 0xCE002C + +#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 0xCE0030 + +#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 0xCE0034 + +#define mmNIC0_QM0_GLBL_STS0 0xCE0038 + +#define mmNIC0_QM0_GLBL_STS1_0 0xCE0040 + +#define mmNIC0_QM0_GLBL_STS1_1 0xCE0044 + +#define mmNIC0_QM0_GLBL_STS1_2 0xCE0048 + +#define mmNIC0_QM0_GLBL_STS1_3 0xCE004C + +#define mmNIC0_QM0_GLBL_STS1_4 0xCE0050 + +#define mmNIC0_QM0_GLBL_MSG_EN_0 0xCE0054 + +#define mmNIC0_QM0_GLBL_MSG_EN_1 0xCE0058 + +#define mmNIC0_QM0_GLBL_MSG_EN_2 0xCE005C + +#define mmNIC0_QM0_GLBL_MSG_EN_3 0xCE0060 + +#define mmNIC0_QM0_GLBL_MSG_EN_4 0xCE0068 + +#define mmNIC0_QM0_PQ_BASE_LO_0 0xCE0070 + +#define mmNIC0_QM0_PQ_BASE_LO_1 0xCE0074 + +#define mmNIC0_QM0_PQ_BASE_LO_2 0xCE0078 + +#define mmNIC0_QM0_PQ_BASE_LO_3 0xCE007C + +#define mmNIC0_QM0_PQ_BASE_HI_0 0xCE0080 + +#define mmNIC0_QM0_PQ_BASE_HI_1 0xCE0084 + +#define mmNIC0_QM0_PQ_BASE_HI_2 0xCE0088 + +#define mmNIC0_QM0_PQ_BASE_HI_3 0xCE008C + +#define mmNIC0_QM0_PQ_SIZE_0 0xCE0090 + +#define mmNIC0_QM0_PQ_SIZE_1 0xCE0094 + +#define mmNIC0_QM0_PQ_SIZE_2 0xCE0098 + +#define mmNIC0_QM0_PQ_SIZE_3 0xCE009C + +#define mmNIC0_QM0_PQ_PI_0 0xCE00A0 + +#define mmNIC0_QM0_PQ_PI_1 0xCE00A4 + +#define mmNIC0_QM0_PQ_PI_2 0xCE00A8 + +#define mmNIC0_QM0_PQ_PI_3 0xCE00AC + +#define mmNIC0_QM0_PQ_CI_0 0xCE00B0 + +#define mmNIC0_QM0_PQ_CI_1 0xCE00B4 + +#define mmNIC0_QM0_PQ_CI_2 0xCE00B8 + +#define mmNIC0_QM0_PQ_CI_3 0xCE00BC + +#define mmNIC0_QM0_PQ_CFG0_0 0xCE00C0 + +#define mmNIC0_QM0_PQ_CFG0_1 0xCE00C4 + +#define mmNIC0_QM0_PQ_CFG0_2 0xCE00C8 + +#define mmNIC0_QM0_PQ_CFG0_3 0xCE00CC + +#define mmNIC0_QM0_PQ_CFG1_0 0xCE00D0 + +#define mmNIC0_QM0_PQ_CFG1_1 0xCE00D4 + +#define mmNIC0_QM0_PQ_CFG1_2 0xCE00D8 + +#define mmNIC0_QM0_PQ_CFG1_3 0xCE00DC + +#define mmNIC0_QM0_PQ_ARUSER_31_11_0 0xCE00E0 + +#define mmNIC0_QM0_PQ_ARUSER_31_11_1 0xCE00E4 + +#define mmNIC0_QM0_PQ_ARUSER_31_11_2 0xCE00E8 + +#define mmNIC0_QM0_PQ_ARUSER_31_11_3 0xCE00EC + +#define mmNIC0_QM0_PQ_STS0_0 0xCE00F0 + +#define mmNIC0_QM0_PQ_STS0_1 0xCE00F4 + +#define mmNIC0_QM0_PQ_STS0_2 0xCE00F8 + +#define mmNIC0_QM0_PQ_STS0_3 0xCE00FC + +#define mmNIC0_QM0_PQ_STS1_0 0xCE0100 + +#define mmNIC0_QM0_PQ_STS1_1 0xCE0104 + +#define mmNIC0_QM0_PQ_STS1_2 0xCE0108 + +#define mmNIC0_QM0_PQ_STS1_3 0xCE010C + +#define mmNIC0_QM0_CQ_CFG0_0 0xCE0110 + +#define mmNIC0_QM0_CQ_CFG0_1 0xCE0114 + +#define mmNIC0_QM0_CQ_CFG0_2 0xCE0118 + +#define mmNIC0_QM0_CQ_CFG0_3 0xCE011C + +#define mmNIC0_QM0_CQ_CFG0_4 0xCE0120 + +#define mmNIC0_QM0_CQ_CFG1_0 0xCE0124 + +#define mmNIC0_QM0_CQ_CFG1_1 0xCE0128 + +#define mmNIC0_QM0_CQ_CFG1_2 0xCE012C + +#define mmNIC0_QM0_CQ_CFG1_3 0xCE0130 + +#define mmNIC0_QM0_CQ_CFG1_4 0xCE0134 + +#define mmNIC0_QM0_CQ_ARUSER_31_11_0 0xCE0138 + +#define mmNIC0_QM0_CQ_ARUSER_31_11_1 0xCE013C + +#define mmNIC0_QM0_CQ_ARUSER_31_11_2 0xCE0140 + +#define mmNIC0_QM0_CQ_ARUSER_31_11_3 0xCE0144 + +#define mmNIC0_QM0_CQ_ARUSER_31_11_4 0xCE0148 + +#define mmNIC0_QM0_CQ_STS0_0 0xCE014C + +#define mmNIC0_QM0_CQ_STS0_1 0xCE0150 + +#define mmNIC0_QM0_CQ_STS0_2 0xCE0154 + +#define mmNIC0_QM0_CQ_STS0_3 0xCE0158 + +#define mmNIC0_QM0_CQ_STS0_4 0xCE015C + +#define mmNIC0_QM0_CQ_STS1_0 0xCE0160 + +#define mmNIC0_QM0_CQ_STS1_1 0xCE0164 + +#define mmNIC0_QM0_CQ_STS1_2 0xCE0168 + +#define mmNIC0_QM0_CQ_STS1_3 0xCE016C + +#define mmNIC0_QM0_CQ_STS1_4 0xCE0170 + +#define mmNIC0_QM0_CQ_PTR_LO_0 0xCE0174 + +#define mmNIC0_QM0_CQ_PTR_HI_0 0xCE0178 + +#define mmNIC0_QM0_CQ_TSIZE_0 0xCE017C + +#define mmNIC0_QM0_CQ_CTL_0 0xCE0180 + +#define mmNIC0_QM0_CQ_PTR_LO_1 0xCE0184 + +#define mmNIC0_QM0_CQ_PTR_HI_1 0xCE0188 + +#define mmNIC0_QM0_CQ_TSIZE_1 0xCE018C + +#define mmNIC0_QM0_CQ_CTL_1 0xCE0190 + +#define mmNIC0_QM0_CQ_PTR_LO_2 0xCE0194 + +#define mmNIC0_QM0_CQ_PTR_HI_2 0xCE0198 + +#define mmNIC0_QM0_CQ_TSIZE_2 0xCE019C + +#define mmNIC0_QM0_CQ_CTL_2 0xCE01A0 + +#define mmNIC0_QM0_CQ_PTR_LO_3 0xCE01A4 + +#define mmNIC0_QM0_CQ_PTR_HI_3 0xCE01A8 + +#define mmNIC0_QM0_CQ_TSIZE_3 0xCE01AC + +#define mmNIC0_QM0_CQ_CTL_3 0xCE01B0 + +#define mmNIC0_QM0_CQ_PTR_LO_4 0xCE01B4 + +#define mmNIC0_QM0_CQ_PTR_HI_4 0xCE01B8 + +#define mmNIC0_QM0_CQ_TSIZE_4 0xCE01BC + +#define mmNIC0_QM0_CQ_CTL_4 0xCE01C0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0xCE01C4 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0xCE01C8 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0xCE01CC + +#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0xCE01D0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0xCE01D4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0xCE01D8 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0xCE01DC + +#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0xCE01E0 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0xCE01E4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0xCE01E8 + +#define mmNIC0_QM0_CQ_TSIZE_STS_0 0xCE01EC + +#define mmNIC0_QM0_CQ_TSIZE_STS_1 0xCE01F0 + +#define mmNIC0_QM0_CQ_TSIZE_STS_2 0xCE01F4 + +#define mmNIC0_QM0_CQ_TSIZE_STS_3 0xCE01F8 + +#define mmNIC0_QM0_CQ_TSIZE_STS_4 0xCE01FC + +#define mmNIC0_QM0_CQ_CTL_STS_0 0xCE0200 + +#define mmNIC0_QM0_CQ_CTL_STS_1 0xCE0204 + +#define mmNIC0_QM0_CQ_CTL_STS_2 0xCE0208 + +#define mmNIC0_QM0_CQ_CTL_STS_3 0xCE020C + +#define mmNIC0_QM0_CQ_CTL_STS_4 0xCE0210 + +#define mmNIC0_QM0_CQ_IFIFO_CNT_0 0xCE0214 + +#define mmNIC0_QM0_CQ_IFIFO_CNT_1 0xCE0218 + +#define mmNIC0_QM0_CQ_IFIFO_CNT_2 0xCE021C + +#define mmNIC0_QM0_CQ_IFIFO_CNT_3 0xCE0220 + +#define mmNIC0_QM0_CQ_IFIFO_CNT_4 0xCE0224 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0xCE0228 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0xCE022C + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0xCE0230 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0xCE0234 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0xCE0238 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0xCE023C + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0xCE0240 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0xCE0244 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0xCE0248 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0xCE024C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0xCE0250 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0xCE0254 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0xCE0258 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0xCE025C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0xCE0260 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0xCE0264 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0xCE0268 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0xCE026C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0xCE0270 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0xCE0274 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0xCE0278 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0xCE027C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0xCE0280 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0xCE0284 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0xCE0288 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0xCE028C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0xCE0290 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0xCE0294 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0xCE0298 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0xCE029C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0xCE02A0 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0xCE02A4 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0xCE02A8 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0xCE02AC + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0xCE02B0 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0xCE02B4 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0xCE02B8 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0xCE02BC + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0xCE02C0 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0xCE02C4 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 0xCE02C8 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 0xCE02CC + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 0xCE02D0 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 0xCE02D4 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 0xCE02D8 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE02E0 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE02E4 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE02E8 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE02EC + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE02F0 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE02F4 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE02F8 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE02FC + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE0300 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE0304 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0xCE0308 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0xCE030C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0xCE0310 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0xCE0314 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0xCE0318 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0xCE031C + +#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0xCE0320 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0xCE0324 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0xCE0328 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0xCE032C + +#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0xCE0330 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0xCE0334 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0xCE0338 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0xCE033C + +#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0xCE0340 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0xCE0344 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0xCE0348 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0xCE034C + +#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0xCE0350 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0xCE0354 + +#define mmNIC0_QM0_CP_FENCE0_CNT_0 0xCE0358 + +#define mmNIC0_QM0_CP_FENCE0_CNT_1 0xCE035C + +#define mmNIC0_QM0_CP_FENCE0_CNT_2 0xCE0360 + +#define mmNIC0_QM0_CP_FENCE0_CNT_3 0xCE0364 + +#define mmNIC0_QM0_CP_FENCE0_CNT_4 0xCE0368 + +#define mmNIC0_QM0_CP_FENCE1_CNT_0 0xCE036C + +#define mmNIC0_QM0_CP_FENCE1_CNT_1 0xCE0370 + +#define mmNIC0_QM0_CP_FENCE1_CNT_2 0xCE0374 + +#define mmNIC0_QM0_CP_FENCE1_CNT_3 0xCE0378 + +#define mmNIC0_QM0_CP_FENCE1_CNT_4 0xCE037C + +#define mmNIC0_QM0_CP_FENCE2_CNT_0 0xCE0380 + +#define mmNIC0_QM0_CP_FENCE2_CNT_1 0xCE0384 + +#define mmNIC0_QM0_CP_FENCE2_CNT_2 0xCE0388 + +#define mmNIC0_QM0_CP_FENCE2_CNT_3 0xCE038C + +#define mmNIC0_QM0_CP_FENCE2_CNT_4 0xCE0390 + +#define mmNIC0_QM0_CP_FENCE3_CNT_0 0xCE0394 + +#define mmNIC0_QM0_CP_FENCE3_CNT_1 0xCE0398 + +#define mmNIC0_QM0_CP_FENCE3_CNT_2 0xCE039C + +#define mmNIC0_QM0_CP_FENCE3_CNT_3 0xCE03A0 + +#define mmNIC0_QM0_CP_FENCE3_CNT_4 0xCE03A4 + +#define mmNIC0_QM0_CP_STS_0 0xCE03A8 + +#define mmNIC0_QM0_CP_STS_1 0xCE03AC + +#define mmNIC0_QM0_CP_STS_2 0xCE03B0 + +#define mmNIC0_QM0_CP_STS_3 0xCE03B4 + +#define mmNIC0_QM0_CP_STS_4 0xCE03B8 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0xCE03BC + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0xCE03C0 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0xCE03C4 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0xCE03C8 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0xCE03CC + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0xCE03D0 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0xCE03D4 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0xCE03D8 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0xCE03DC + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0xCE03E0 + +#define mmNIC0_QM0_CP_BARRIER_CFG_0 0xCE03F4 + +#define mmNIC0_QM0_CP_BARRIER_CFG_1 0xCE03F8 + +#define mmNIC0_QM0_CP_BARRIER_CFG_2 0xCE03FC + +#define mmNIC0_QM0_CP_BARRIER_CFG_3 0xCE0400 + +#define mmNIC0_QM0_CP_BARRIER_CFG_4 0xCE0404 + +#define mmNIC0_QM0_CP_DBG_0_0 0xCE0408 + +#define mmNIC0_QM0_CP_DBG_0_1 0xCE040C + +#define mmNIC0_QM0_CP_DBG_0_2 0xCE0410 + +#define mmNIC0_QM0_CP_DBG_0_3 0xCE0414 + +#define mmNIC0_QM0_CP_DBG_0_4 0xCE0418 + +#define mmNIC0_QM0_CP_ARUSER_31_11_0 0xCE041C + +#define mmNIC0_QM0_CP_ARUSER_31_11_1 0xCE0420 + +#define mmNIC0_QM0_CP_ARUSER_31_11_2 0xCE0424 + +#define mmNIC0_QM0_CP_ARUSER_31_11_3 0xCE0428 + +#define mmNIC0_QM0_CP_ARUSER_31_11_4 0xCE042C + +#define mmNIC0_QM0_CP_AWUSER_31_11_0 0xCE0430 + +#define mmNIC0_QM0_CP_AWUSER_31_11_1 0xCE0434 + +#define mmNIC0_QM0_CP_AWUSER_31_11_2 0xCE0438 + +#define mmNIC0_QM0_CP_AWUSER_31_11_3 0xCE043C + +#define mmNIC0_QM0_CP_AWUSER_31_11_4 0xCE0440 + +#define mmNIC0_QM0_ARB_CFG_0 0xCE0A00 + +#define mmNIC0_QM0_ARB_CHOISE_Q_PUSH 0xCE0A04 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0xCE0A08 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0xCE0A0C + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0xCE0A10 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0xCE0A14 + +#define mmNIC0_QM0_ARB_CFG_1 0xCE0A18 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0xCE0A20 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0xCE0A24 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0xCE0A28 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0xCE0A2C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0xCE0A30 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0xCE0A34 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0xCE0A38 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0xCE0A3C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0xCE0A40 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0xCE0A44 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0xCE0A48 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0xCE0A4C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0xCE0A50 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0xCE0A54 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0xCE0A58 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0xCE0A5C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0xCE0A60 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0xCE0A64 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0xCE0A68 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0xCE0A6C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0xCE0A70 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0xCE0A74 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0xCE0A78 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0xCE0A7C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0xCE0A80 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0xCE0A84 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0xCE0A88 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0xCE0A8C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0xCE0A90 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0xCE0A94 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0xCE0A98 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0xCE0A9C + +#define mmNIC0_QM0_ARB_MST_CRED_INC 0xCE0AA0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xCE0AA4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xCE0AA8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xCE0AAC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xCE0AB0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xCE0AB4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xCE0AB8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xCE0ABC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xCE0AC0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xCE0AC4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xCE0AC8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xCE0ACC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xCE0AD0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xCE0AD4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xCE0AD8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xCE0ADC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xCE0AE0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xCE0AE4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xCE0AE8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xCE0AEC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xCE0AF0 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xCE0AF4 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xCE0AF8 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xCE0AFC + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xCE0B00 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xCE0B04 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xCE0B08 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xCE0B0C + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xCE0B10 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xCE0B14 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xCE0B18 + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xCE0B1C + +#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xCE0B20 + +#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xCE0B28 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0xCE0B2C + +#define mmNIC0_QM0_ARB_MST_QUIET_PER 0xCE0B34 + +#define mmNIC0_QM0_ARB_SLV_CHOISE_WDT 0xCE0B38 + +#define mmNIC0_QM0_ARB_SLV_ID 0xCE0B3C + +#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0xCE0B44 + +#define mmNIC0_QM0_ARB_MSG_AWUSER_31_11 0xCE0B48 + +#define mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP 0xCE0B4C + +#define mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE0B50 + +#define mmNIC0_QM0_ARB_BASE_LO 0xCE0B54 + +#define mmNIC0_QM0_ARB_BASE_HI 0xCE0B58 + +#define mmNIC0_QM0_ARB_STATE_STS 0xCE0B80 + +#define mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS 0xCE0B84 + +#define mmNIC0_QM0_ARB_MSG_STS 0xCE0B88 + +#define mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD 0xCE0B8C + +#define mmNIC0_QM0_ARB_ERR_CAUSE 0xCE0B9C + +#define mmNIC0_QM0_ARB_ERR_MSG_EN 0xCE0BA0 + +#define mmNIC0_QM0_ARB_ERR_STS_DRP 0xCE0BA8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_0 0xCE0BB0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0xCE0BB4 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_2 0xCE0BB8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_3 0xCE0BBC + +#define mmNIC0_QM0_ARB_MST_CRED_STS_4 0xCE0BC0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_5 0xCE0BC4 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_6 0xCE0BC8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_7 0xCE0BCC + +#define mmNIC0_QM0_ARB_MST_CRED_STS_8 0xCE0BD0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_9 0xCE0BD4 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_10 0xCE0BD8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_11 0xCE0BDC + +#define mmNIC0_QM0_ARB_MST_CRED_STS_12 0xCE0BE0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_13 0xCE0BE4 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_14 0xCE0BE8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_15 0xCE0BEC + +#define mmNIC0_QM0_ARB_MST_CRED_STS_16 0xCE0BF0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_17 0xCE0BF4 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_18 0xCE0BF8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_19 0xCE0BFC + +#define mmNIC0_QM0_ARB_MST_CRED_STS_20 0xCE0C00 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_21 0xCE0C04 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_22 0xCE0C08 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_23 0xCE0C0C + +#define mmNIC0_QM0_ARB_MST_CRED_STS_24 0xCE0C10 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_25 0xCE0C14 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_26 0xCE0C18 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_27 0xCE0C1C + +#define mmNIC0_QM0_ARB_MST_CRED_STS_28 0xCE0C20 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_29 0xCE0C24 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_30 0xCE0C28 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_31 0xCE0C2C + +#define mmNIC0_QM0_CGM_CFG 0xCE0C70 + +#define mmNIC0_QM0_CGM_STS 0xCE0C74 + +#define mmNIC0_QM0_CGM_CFG1 0xCE0C78 + +#define mmNIC0_QM0_LOCAL_RANGE_BASE 0xCE0C80 + +#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0xCE0C84 + +#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0xCE0C90 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0xCE0C94 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0xCE0C98 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0xCE0C9C + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0xCE0CA0 + +#define mmNIC0_QM0_GLBL_AXCACHE 0xCE0CA4 + +#define mmNIC0_QM0_IND_GW_APB_CFG 0xCE0CB0 + +#define mmNIC0_QM0_IND_GW_APB_WDATA 0xCE0CB4 + +#define mmNIC0_QM0_IND_GW_APB_RDATA 0xCE0CB8 + +#define mmNIC0_QM0_IND_GW_APB_STATUS 0xCE0CBC + +#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0xCE0CD0 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0xCE0CD4 + +#define mmNIC0_QM0_GLBL_ERR_WDATA 0xCE0CD8 + +#define mmNIC0_QM0_GLBL_MEM_INIT_BUSY 0xCE0D00 + +#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h new file mode 100644 index 000000000..fe96c575b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM1_REGS_H_ +#define ASIC_REG_NIC0_QM1_REGS_H_ + +/* + ***************************************** + * NIC0_QM1 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC0_QM1_GLBL_CFG0 0xCE2000 + +#define mmNIC0_QM1_GLBL_CFG1 0xCE2004 + +#define mmNIC0_QM1_GLBL_PROT 0xCE2008 + +#define mmNIC0_QM1_GLBL_ERR_CFG 0xCE200C + +#define mmNIC0_QM1_GLBL_SECURE_PROPS_0 0xCE2010 + +#define mmNIC0_QM1_GLBL_SECURE_PROPS_1 0xCE2014 + +#define mmNIC0_QM1_GLBL_SECURE_PROPS_2 0xCE2018 + +#define mmNIC0_QM1_GLBL_SECURE_PROPS_3 0xCE201C + +#define mmNIC0_QM1_GLBL_SECURE_PROPS_4 0xCE2020 + +#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0 0xCE2024 + +#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1 0xCE2028 + +#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2 0xCE202C + +#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3 0xCE2030 + +#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4 0xCE2034 + +#define mmNIC0_QM1_GLBL_STS0 0xCE2038 + +#define mmNIC0_QM1_GLBL_STS1_0 0xCE2040 + +#define mmNIC0_QM1_GLBL_STS1_1 0xCE2044 + +#define mmNIC0_QM1_GLBL_STS1_2 0xCE2048 + +#define mmNIC0_QM1_GLBL_STS1_3 0xCE204C + +#define mmNIC0_QM1_GLBL_STS1_4 0xCE2050 + +#define mmNIC0_QM1_GLBL_MSG_EN_0 0xCE2054 + +#define mmNIC0_QM1_GLBL_MSG_EN_1 0xCE2058 + +#define mmNIC0_QM1_GLBL_MSG_EN_2 0xCE205C + +#define mmNIC0_QM1_GLBL_MSG_EN_3 0xCE2060 + +#define mmNIC0_QM1_GLBL_MSG_EN_4 0xCE2068 + +#define mmNIC0_QM1_PQ_BASE_LO_0 0xCE2070 + +#define mmNIC0_QM1_PQ_BASE_LO_1 0xCE2074 + +#define mmNIC0_QM1_PQ_BASE_LO_2 0xCE2078 + +#define mmNIC0_QM1_PQ_BASE_LO_3 0xCE207C + +#define mmNIC0_QM1_PQ_BASE_HI_0 0xCE2080 + +#define mmNIC0_QM1_PQ_BASE_HI_1 0xCE2084 + +#define mmNIC0_QM1_PQ_BASE_HI_2 0xCE2088 + +#define mmNIC0_QM1_PQ_BASE_HI_3 0xCE208C + +#define mmNIC0_QM1_PQ_SIZE_0 0xCE2090 + +#define mmNIC0_QM1_PQ_SIZE_1 0xCE2094 + +#define mmNIC0_QM1_PQ_SIZE_2 0xCE2098 + +#define mmNIC0_QM1_PQ_SIZE_3 0xCE209C + +#define mmNIC0_QM1_PQ_PI_0 0xCE20A0 + +#define mmNIC0_QM1_PQ_PI_1 0xCE20A4 + +#define mmNIC0_QM1_PQ_PI_2 0xCE20A8 + +#define mmNIC0_QM1_PQ_PI_3 0xCE20AC + +#define mmNIC0_QM1_PQ_CI_0 0xCE20B0 + +#define mmNIC0_QM1_PQ_CI_1 0xCE20B4 + +#define mmNIC0_QM1_PQ_CI_2 0xCE20B8 + +#define mmNIC0_QM1_PQ_CI_3 0xCE20BC + +#define mmNIC0_QM1_PQ_CFG0_0 0xCE20C0 + +#define mmNIC0_QM1_PQ_CFG0_1 0xCE20C4 + +#define mmNIC0_QM1_PQ_CFG0_2 0xCE20C8 + +#define mmNIC0_QM1_PQ_CFG0_3 0xCE20CC + +#define mmNIC0_QM1_PQ_CFG1_0 0xCE20D0 + +#define mmNIC0_QM1_PQ_CFG1_1 0xCE20D4 + +#define mmNIC0_QM1_PQ_CFG1_2 0xCE20D8 + +#define mmNIC0_QM1_PQ_CFG1_3 0xCE20DC + +#define mmNIC0_QM1_PQ_ARUSER_31_11_0 0xCE20E0 + +#define mmNIC0_QM1_PQ_ARUSER_31_11_1 0xCE20E4 + +#define mmNIC0_QM1_PQ_ARUSER_31_11_2 0xCE20E8 + +#define mmNIC0_QM1_PQ_ARUSER_31_11_3 0xCE20EC + +#define mmNIC0_QM1_PQ_STS0_0 0xCE20F0 + +#define mmNIC0_QM1_PQ_STS0_1 0xCE20F4 + +#define mmNIC0_QM1_PQ_STS0_2 0xCE20F8 + +#define mmNIC0_QM1_PQ_STS0_3 0xCE20FC + +#define mmNIC0_QM1_PQ_STS1_0 0xCE2100 + +#define mmNIC0_QM1_PQ_STS1_1 0xCE2104 + +#define mmNIC0_QM1_PQ_STS1_2 0xCE2108 + +#define mmNIC0_QM1_PQ_STS1_3 0xCE210C + +#define mmNIC0_QM1_CQ_CFG0_0 0xCE2110 + +#define mmNIC0_QM1_CQ_CFG0_1 0xCE2114 + +#define mmNIC0_QM1_CQ_CFG0_2 0xCE2118 + +#define mmNIC0_QM1_CQ_CFG0_3 0xCE211C + +#define mmNIC0_QM1_CQ_CFG0_4 0xCE2120 + +#define mmNIC0_QM1_CQ_CFG1_0 0xCE2124 + +#define mmNIC0_QM1_CQ_CFG1_1 0xCE2128 + +#define mmNIC0_QM1_CQ_CFG1_2 0xCE212C + +#define mmNIC0_QM1_CQ_CFG1_3 0xCE2130 + +#define mmNIC0_QM1_CQ_CFG1_4 0xCE2134 + +#define mmNIC0_QM1_CQ_ARUSER_31_11_0 0xCE2138 + +#define mmNIC0_QM1_CQ_ARUSER_31_11_1 0xCE213C + +#define mmNIC0_QM1_CQ_ARUSER_31_11_2 0xCE2140 + +#define mmNIC0_QM1_CQ_ARUSER_31_11_3 0xCE2144 + +#define mmNIC0_QM1_CQ_ARUSER_31_11_4 0xCE2148 + +#define mmNIC0_QM1_CQ_STS0_0 0xCE214C + +#define mmNIC0_QM1_CQ_STS0_1 0xCE2150 + +#define mmNIC0_QM1_CQ_STS0_2 0xCE2154 + +#define mmNIC0_QM1_CQ_STS0_3 0xCE2158 + +#define mmNIC0_QM1_CQ_STS0_4 0xCE215C + +#define mmNIC0_QM1_CQ_STS1_0 0xCE2160 + +#define mmNIC0_QM1_CQ_STS1_1 0xCE2164 + +#define mmNIC0_QM1_CQ_STS1_2 0xCE2168 + +#define mmNIC0_QM1_CQ_STS1_3 0xCE216C + +#define mmNIC0_QM1_CQ_STS1_4 0xCE2170 + +#define mmNIC0_QM1_CQ_PTR_LO_0 0xCE2174 + +#define mmNIC0_QM1_CQ_PTR_HI_0 0xCE2178 + +#define mmNIC0_QM1_CQ_TSIZE_0 0xCE217C + +#define mmNIC0_QM1_CQ_CTL_0 0xCE2180 + +#define mmNIC0_QM1_CQ_PTR_LO_1 0xCE2184 + +#define mmNIC0_QM1_CQ_PTR_HI_1 0xCE2188 + +#define mmNIC0_QM1_CQ_TSIZE_1 0xCE218C + +#define mmNIC0_QM1_CQ_CTL_1 0xCE2190 + +#define mmNIC0_QM1_CQ_PTR_LO_2 0xCE2194 + +#define mmNIC0_QM1_CQ_PTR_HI_2 0xCE2198 + +#define mmNIC0_QM1_CQ_TSIZE_2 0xCE219C + +#define mmNIC0_QM1_CQ_CTL_2 0xCE21A0 + +#define mmNIC0_QM1_CQ_PTR_LO_3 0xCE21A4 + +#define mmNIC0_QM1_CQ_PTR_HI_3 0xCE21A8 + +#define mmNIC0_QM1_CQ_TSIZE_3 0xCE21AC + +#define mmNIC0_QM1_CQ_CTL_3 0xCE21B0 + +#define mmNIC0_QM1_CQ_PTR_LO_4 0xCE21B4 + +#define mmNIC0_QM1_CQ_PTR_HI_4 0xCE21B8 + +#define mmNIC0_QM1_CQ_TSIZE_4 0xCE21BC + +#define mmNIC0_QM1_CQ_CTL_4 0xCE21C0 + +#define mmNIC0_QM1_CQ_PTR_LO_STS_0 0xCE21C4 + +#define mmNIC0_QM1_CQ_PTR_LO_STS_1 0xCE21C8 + +#define mmNIC0_QM1_CQ_PTR_LO_STS_2 0xCE21CC + +#define mmNIC0_QM1_CQ_PTR_LO_STS_3 0xCE21D0 + +#define mmNIC0_QM1_CQ_PTR_LO_STS_4 0xCE21D4 + +#define mmNIC0_QM1_CQ_PTR_HI_STS_0 0xCE21D8 + +#define mmNIC0_QM1_CQ_PTR_HI_STS_1 0xCE21DC + +#define mmNIC0_QM1_CQ_PTR_HI_STS_2 0xCE21E0 + +#define mmNIC0_QM1_CQ_PTR_HI_STS_3 0xCE21E4 + +#define mmNIC0_QM1_CQ_PTR_HI_STS_4 0xCE21E8 + +#define mmNIC0_QM1_CQ_TSIZE_STS_0 0xCE21EC + +#define mmNIC0_QM1_CQ_TSIZE_STS_1 0xCE21F0 + +#define mmNIC0_QM1_CQ_TSIZE_STS_2 0xCE21F4 + +#define mmNIC0_QM1_CQ_TSIZE_STS_3 0xCE21F8 + +#define mmNIC0_QM1_CQ_TSIZE_STS_4 0xCE21FC + +#define mmNIC0_QM1_CQ_CTL_STS_0 0xCE2200 + +#define mmNIC0_QM1_CQ_CTL_STS_1 0xCE2204 + +#define mmNIC0_QM1_CQ_CTL_STS_2 0xCE2208 + +#define mmNIC0_QM1_CQ_CTL_STS_3 0xCE220C + +#define mmNIC0_QM1_CQ_CTL_STS_4 0xCE2210 + +#define mmNIC0_QM1_CQ_IFIFO_CNT_0 0xCE2214 + +#define mmNIC0_QM1_CQ_IFIFO_CNT_1 0xCE2218 + +#define mmNIC0_QM1_CQ_IFIFO_CNT_2 0xCE221C + +#define mmNIC0_QM1_CQ_IFIFO_CNT_3 0xCE2220 + +#define mmNIC0_QM1_CQ_IFIFO_CNT_4 0xCE2224 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0 0xCE2228 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1 0xCE222C + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2 0xCE2230 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3 0xCE2234 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4 0xCE2238 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0 0xCE223C + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1 0xCE2240 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2 0xCE2244 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3 0xCE2248 + +#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4 0xCE224C + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0 0xCE2250 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1 0xCE2254 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2 0xCE2258 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3 0xCE225C + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4 0xCE2260 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0 0xCE2264 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1 0xCE2268 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2 0xCE226C + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3 0xCE2270 + +#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4 0xCE2274 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0 0xCE2278 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1 0xCE227C + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 0xCE2280 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3 0xCE2284 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4 0xCE2288 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0 0xCE228C + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1 0xCE2290 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2 0xCE2294 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3 0xCE2298 + +#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4 0xCE229C + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0 0xCE22A0 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1 0xCE22A4 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2 0xCE22A8 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3 0xCE22AC + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4 0xCE22B0 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0 0xCE22B4 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1 0xCE22B8 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2 0xCE22BC + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3 0xCE22C0 + +#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4 0xCE22C4 + +#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0 0xCE22C8 + +#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1 0xCE22CC + +#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2 0xCE22D0 + +#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3 0xCE22D4 + +#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4 0xCE22D8 + +#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE22E0 + +#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE22E4 + +#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE22E8 + +#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE22EC + +#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE22F0 + +#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE22F4 + +#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE22F8 + +#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE22FC + +#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE2300 + +#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE2304 + +#define mmNIC0_QM1_CP_FENCE0_RDATA_0 0xCE2308 + +#define mmNIC0_QM1_CP_FENCE0_RDATA_1 0xCE230C + +#define mmNIC0_QM1_CP_FENCE0_RDATA_2 0xCE2310 + +#define mmNIC0_QM1_CP_FENCE0_RDATA_3 0xCE2314 + +#define mmNIC0_QM1_CP_FENCE0_RDATA_4 0xCE2318 + +#define mmNIC0_QM1_CP_FENCE1_RDATA_0 0xCE231C + +#define mmNIC0_QM1_CP_FENCE1_RDATA_1 0xCE2320 + +#define mmNIC0_QM1_CP_FENCE1_RDATA_2 0xCE2324 + +#define mmNIC0_QM1_CP_FENCE1_RDATA_3 0xCE2328 + +#define mmNIC0_QM1_CP_FENCE1_RDATA_4 0xCE232C + +#define mmNIC0_QM1_CP_FENCE2_RDATA_0 0xCE2330 + +#define mmNIC0_QM1_CP_FENCE2_RDATA_1 0xCE2334 + +#define mmNIC0_QM1_CP_FENCE2_RDATA_2 0xCE2338 + +#define mmNIC0_QM1_CP_FENCE2_RDATA_3 0xCE233C + +#define mmNIC0_QM1_CP_FENCE2_RDATA_4 0xCE2340 + +#define mmNIC0_QM1_CP_FENCE3_RDATA_0 0xCE2344 + +#define mmNIC0_QM1_CP_FENCE3_RDATA_1 0xCE2348 + +#define mmNIC0_QM1_CP_FENCE3_RDATA_2 0xCE234C + +#define mmNIC0_QM1_CP_FENCE3_RDATA_3 0xCE2350 + +#define mmNIC0_QM1_CP_FENCE3_RDATA_4 0xCE2354 + +#define mmNIC0_QM1_CP_FENCE0_CNT_0 0xCE2358 + +#define mmNIC0_QM1_CP_FENCE0_CNT_1 0xCE235C + +#define mmNIC0_QM1_CP_FENCE0_CNT_2 0xCE2360 + +#define mmNIC0_QM1_CP_FENCE0_CNT_3 0xCE2364 + +#define mmNIC0_QM1_CP_FENCE0_CNT_4 0xCE2368 + +#define mmNIC0_QM1_CP_FENCE1_CNT_0 0xCE236C + +#define mmNIC0_QM1_CP_FENCE1_CNT_1 0xCE2370 + +#define mmNIC0_QM1_CP_FENCE1_CNT_2 0xCE2374 + +#define mmNIC0_QM1_CP_FENCE1_CNT_3 0xCE2378 + +#define mmNIC0_QM1_CP_FENCE1_CNT_4 0xCE237C + +#define mmNIC0_QM1_CP_FENCE2_CNT_0 0xCE2380 + +#define mmNIC0_QM1_CP_FENCE2_CNT_1 0xCE2384 + +#define mmNIC0_QM1_CP_FENCE2_CNT_2 0xCE2388 + +#define mmNIC0_QM1_CP_FENCE2_CNT_3 0xCE238C + +#define mmNIC0_QM1_CP_FENCE2_CNT_4 0xCE2390 + +#define mmNIC0_QM1_CP_FENCE3_CNT_0 0xCE2394 + +#define mmNIC0_QM1_CP_FENCE3_CNT_1 0xCE2398 + +#define mmNIC0_QM1_CP_FENCE3_CNT_2 0xCE239C + +#define mmNIC0_QM1_CP_FENCE3_CNT_3 0xCE23A0 + +#define mmNIC0_QM1_CP_FENCE3_CNT_4 0xCE23A4 + +#define mmNIC0_QM1_CP_STS_0 0xCE23A8 + +#define mmNIC0_QM1_CP_STS_1 0xCE23AC + +#define mmNIC0_QM1_CP_STS_2 0xCE23B0 + +#define mmNIC0_QM1_CP_STS_3 0xCE23B4 + +#define mmNIC0_QM1_CP_STS_4 0xCE23B8 + +#define mmNIC0_QM1_CP_CURRENT_INST_LO_0 0xCE23BC + +#define mmNIC0_QM1_CP_CURRENT_INST_LO_1 0xCE23C0 + +#define mmNIC0_QM1_CP_CURRENT_INST_LO_2 0xCE23C4 + +#define mmNIC0_QM1_CP_CURRENT_INST_LO_3 0xCE23C8 + +#define mmNIC0_QM1_CP_CURRENT_INST_LO_4 0xCE23CC + +#define mmNIC0_QM1_CP_CURRENT_INST_HI_0 0xCE23D0 + +#define mmNIC0_QM1_CP_CURRENT_INST_HI_1 0xCE23D4 + +#define mmNIC0_QM1_CP_CURRENT_INST_HI_2 0xCE23D8 + +#define mmNIC0_QM1_CP_CURRENT_INST_HI_3 0xCE23DC + +#define mmNIC0_QM1_CP_CURRENT_INST_HI_4 0xCE23E0 + +#define mmNIC0_QM1_CP_BARRIER_CFG_0 0xCE23F4 + +#define mmNIC0_QM1_CP_BARRIER_CFG_1 0xCE23F8 + +#define mmNIC0_QM1_CP_BARRIER_CFG_2 0xCE23FC + +#define mmNIC0_QM1_CP_BARRIER_CFG_3 0xCE2400 + +#define mmNIC0_QM1_CP_BARRIER_CFG_4 0xCE2404 + +#define mmNIC0_QM1_CP_DBG_0_0 0xCE2408 + +#define mmNIC0_QM1_CP_DBG_0_1 0xCE240C + +#define mmNIC0_QM1_CP_DBG_0_2 0xCE2410 + +#define mmNIC0_QM1_CP_DBG_0_3 0xCE2414 + +#define mmNIC0_QM1_CP_DBG_0_4 0xCE2418 + +#define mmNIC0_QM1_CP_ARUSER_31_11_0 0xCE241C + +#define mmNIC0_QM1_CP_ARUSER_31_11_1 0xCE2420 + +#define mmNIC0_QM1_CP_ARUSER_31_11_2 0xCE2424 + +#define mmNIC0_QM1_CP_ARUSER_31_11_3 0xCE2428 + +#define mmNIC0_QM1_CP_ARUSER_31_11_4 0xCE242C + +#define mmNIC0_QM1_CP_AWUSER_31_11_0 0xCE2430 + +#define mmNIC0_QM1_CP_AWUSER_31_11_1 0xCE2434 + +#define mmNIC0_QM1_CP_AWUSER_31_11_2 0xCE2438 + +#define mmNIC0_QM1_CP_AWUSER_31_11_3 0xCE243C + +#define mmNIC0_QM1_CP_AWUSER_31_11_4 0xCE2440 + +#define mmNIC0_QM1_ARB_CFG_0 0xCE2A00 + +#define mmNIC0_QM1_ARB_CHOISE_Q_PUSH 0xCE2A04 + +#define mmNIC0_QM1_ARB_WRR_WEIGHT_0 0xCE2A08 + +#define mmNIC0_QM1_ARB_WRR_WEIGHT_1 0xCE2A0C + +#define mmNIC0_QM1_ARB_WRR_WEIGHT_2 0xCE2A10 + +#define mmNIC0_QM1_ARB_WRR_WEIGHT_3 0xCE2A14 + +#define mmNIC0_QM1_ARB_CFG_1 0xCE2A18 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_0 0xCE2A20 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_1 0xCE2A24 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_2 0xCE2A28 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_3 0xCE2A2C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_4 0xCE2A30 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_5 0xCE2A34 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_6 0xCE2A38 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_7 0xCE2A3C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_8 0xCE2A40 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_9 0xCE2A44 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_10 0xCE2A48 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_11 0xCE2A4C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_12 0xCE2A50 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_13 0xCE2A54 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_14 0xCE2A58 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_15 0xCE2A5C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_16 0xCE2A60 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_17 0xCE2A64 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_18 0xCE2A68 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_19 0xCE2A6C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_20 0xCE2A70 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_21 0xCE2A74 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_22 0xCE2A78 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_23 0xCE2A7C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 0xCE2A80 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_25 0xCE2A84 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_26 0xCE2A88 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_27 0xCE2A8C + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_28 0xCE2A90 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_29 0xCE2A94 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_30 0xCE2A98 + +#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_31 0xCE2A9C + +#define mmNIC0_QM1_ARB_MST_CRED_INC 0xCE2AA0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xCE2AA4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xCE2AA8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xCE2AAC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xCE2AB0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xCE2AB4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xCE2AB8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xCE2ABC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xCE2AC0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xCE2AC4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xCE2AC8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xCE2ACC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xCE2AD0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xCE2AD4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xCE2AD8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xCE2ADC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xCE2AE0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xCE2AE4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xCE2AE8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xCE2AEC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xCE2AF0 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xCE2AF4 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xCE2AF8 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xCE2AFC + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xCE2B00 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xCE2B04 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xCE2B08 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xCE2B0C + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xCE2B10 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xCE2B14 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xCE2B18 + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xCE2B1C + +#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xCE2B20 + +#define mmNIC0_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xCE2B28 + +#define mmNIC0_QM1_ARB_MST_SLAVE_EN 0xCE2B2C + +#define mmNIC0_QM1_ARB_MST_QUIET_PER 0xCE2B34 + +#define mmNIC0_QM1_ARB_SLV_CHOISE_WDT 0xCE2B38 + +#define mmNIC0_QM1_ARB_SLV_ID 0xCE2B3C + +#define mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT 0xCE2B44 + +#define mmNIC0_QM1_ARB_MSG_AWUSER_31_11 0xCE2B48 + +#define mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP 0xCE2B4C + +#define mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE2B50 + +#define mmNIC0_QM1_ARB_BASE_LO 0xCE2B54 + +#define mmNIC0_QM1_ARB_BASE_HI 0xCE2B58 + +#define mmNIC0_QM1_ARB_STATE_STS 0xCE2B80 + +#define mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS 0xCE2B84 + +#define mmNIC0_QM1_ARB_MSG_STS 0xCE2B88 + +#define mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD 0xCE2B8C + +#define mmNIC0_QM1_ARB_ERR_CAUSE 0xCE2B9C + +#define mmNIC0_QM1_ARB_ERR_MSG_EN 0xCE2BA0 + +#define mmNIC0_QM1_ARB_ERR_STS_DRP 0xCE2BA8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_0 0xCE2BB0 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_1 0xCE2BB4 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_2 0xCE2BB8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_3 0xCE2BBC + +#define mmNIC0_QM1_ARB_MST_CRED_STS_4 0xCE2BC0 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_5 0xCE2BC4 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_6 0xCE2BC8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_7 0xCE2BCC + +#define mmNIC0_QM1_ARB_MST_CRED_STS_8 0xCE2BD0 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_9 0xCE2BD4 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_10 0xCE2BD8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_11 0xCE2BDC + +#define mmNIC0_QM1_ARB_MST_CRED_STS_12 0xCE2BE0 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_13 0xCE2BE4 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_14 0xCE2BE8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_15 0xCE2BEC + +#define mmNIC0_QM1_ARB_MST_CRED_STS_16 0xCE2BF0 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_17 0xCE2BF4 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_18 0xCE2BF8 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_19 0xCE2BFC + +#define mmNIC0_QM1_ARB_MST_CRED_STS_20 0xCE2C00 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_21 0xCE2C04 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_22 0xCE2C08 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_23 0xCE2C0C + +#define mmNIC0_QM1_ARB_MST_CRED_STS_24 0xCE2C10 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_25 0xCE2C14 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_26 0xCE2C18 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_27 0xCE2C1C + +#define mmNIC0_QM1_ARB_MST_CRED_STS_28 0xCE2C20 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_29 0xCE2C24 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_30 0xCE2C28 + +#define mmNIC0_QM1_ARB_MST_CRED_STS_31 0xCE2C2C + +#define mmNIC0_QM1_CGM_CFG 0xCE2C70 + +#define mmNIC0_QM1_CGM_STS 0xCE2C74 + +#define mmNIC0_QM1_CGM_CFG1 0xCE2C78 + +#define mmNIC0_QM1_LOCAL_RANGE_BASE 0xCE2C80 + +#define mmNIC0_QM1_LOCAL_RANGE_SIZE 0xCE2C84 + +#define mmNIC0_QM1_CSMR_STRICT_PRIO_CFG 0xCE2C90 + +#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1 0xCE2C94 + +#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0 0xCE2C98 + +#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1 0xCE2C9C + +#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0 0xCE2CA0 + +#define mmNIC0_QM1_GLBL_AXCACHE 0xCE2CA4 + +#define mmNIC0_QM1_IND_GW_APB_CFG 0xCE2CB0 + +#define mmNIC0_QM1_IND_GW_APB_WDATA 0xCE2CB4 + +#define mmNIC0_QM1_IND_GW_APB_RDATA 0xCE2CB8 + +#define mmNIC0_QM1_IND_GW_APB_STATUS 0xCE2CBC + +#define mmNIC0_QM1_GLBL_ERR_ADDR_LO 0xCE2CD0 + +#define mmNIC0_QM1_GLBL_ERR_ADDR_HI 0xCE2CD4 + +#define mmNIC0_QM1_GLBL_ERR_WDATA 0xCE2CD8 + +#define mmNIC0_QM1_GLBL_MEM_INIT_BUSY 0xCE2D00 + +#endif /* ASIC_REG_NIC0_QM1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h new file mode 100644 index 000000000..0d1caf057 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC1_QM0_REGS_H_ +#define ASIC_REG_NIC1_QM0_REGS_H_ + +/* + ***************************************** + * NIC1_QM0 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC1_QM0_GLBL_CFG0 0xD20000 + +#define mmNIC1_QM0_GLBL_CFG1 0xD20004 + +#define mmNIC1_QM0_GLBL_PROT 0xD20008 + +#define mmNIC1_QM0_GLBL_ERR_CFG 0xD2000C + +#define mmNIC1_QM0_GLBL_SECURE_PROPS_0 0xD20010 + +#define mmNIC1_QM0_GLBL_SECURE_PROPS_1 0xD20014 + +#define mmNIC1_QM0_GLBL_SECURE_PROPS_2 0xD20018 + +#define mmNIC1_QM0_GLBL_SECURE_PROPS_3 0xD2001C + +#define mmNIC1_QM0_GLBL_SECURE_PROPS_4 0xD20020 + +#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0 0xD20024 + +#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1 0xD20028 + +#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2 0xD2002C + +#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3 0xD20030 + +#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4 0xD20034 + +#define mmNIC1_QM0_GLBL_STS0 0xD20038 + +#define mmNIC1_QM0_GLBL_STS1_0 0xD20040 + +#define mmNIC1_QM0_GLBL_STS1_1 0xD20044 + +#define mmNIC1_QM0_GLBL_STS1_2 0xD20048 + +#define mmNIC1_QM0_GLBL_STS1_3 0xD2004C + +#define mmNIC1_QM0_GLBL_STS1_4 0xD20050 + +#define mmNIC1_QM0_GLBL_MSG_EN_0 0xD20054 + +#define mmNIC1_QM0_GLBL_MSG_EN_1 0xD20058 + +#define mmNIC1_QM0_GLBL_MSG_EN_2 0xD2005C + +#define mmNIC1_QM0_GLBL_MSG_EN_3 0xD20060 + +#define mmNIC1_QM0_GLBL_MSG_EN_4 0xD20068 + +#define mmNIC1_QM0_PQ_BASE_LO_0 0xD20070 + +#define mmNIC1_QM0_PQ_BASE_LO_1 0xD20074 + +#define mmNIC1_QM0_PQ_BASE_LO_2 0xD20078 + +#define mmNIC1_QM0_PQ_BASE_LO_3 0xD2007C + +#define mmNIC1_QM0_PQ_BASE_HI_0 0xD20080 + +#define mmNIC1_QM0_PQ_BASE_HI_1 0xD20084 + +#define mmNIC1_QM0_PQ_BASE_HI_2 0xD20088 + +#define mmNIC1_QM0_PQ_BASE_HI_3 0xD2008C + +#define mmNIC1_QM0_PQ_SIZE_0 0xD20090 + +#define mmNIC1_QM0_PQ_SIZE_1 0xD20094 + +#define mmNIC1_QM0_PQ_SIZE_2 0xD20098 + +#define mmNIC1_QM0_PQ_SIZE_3 0xD2009C + +#define mmNIC1_QM0_PQ_PI_0 0xD200A0 + +#define mmNIC1_QM0_PQ_PI_1 0xD200A4 + +#define mmNIC1_QM0_PQ_PI_2 0xD200A8 + +#define mmNIC1_QM0_PQ_PI_3 0xD200AC + +#define mmNIC1_QM0_PQ_CI_0 0xD200B0 + +#define mmNIC1_QM0_PQ_CI_1 0xD200B4 + +#define mmNIC1_QM0_PQ_CI_2 0xD200B8 + +#define mmNIC1_QM0_PQ_CI_3 0xD200BC + +#define mmNIC1_QM0_PQ_CFG0_0 0xD200C0 + +#define mmNIC1_QM0_PQ_CFG0_1 0xD200C4 + +#define mmNIC1_QM0_PQ_CFG0_2 0xD200C8 + +#define mmNIC1_QM0_PQ_CFG0_3 0xD200CC + +#define mmNIC1_QM0_PQ_CFG1_0 0xD200D0 + +#define mmNIC1_QM0_PQ_CFG1_1 0xD200D4 + +#define mmNIC1_QM0_PQ_CFG1_2 0xD200D8 + +#define mmNIC1_QM0_PQ_CFG1_3 0xD200DC + +#define mmNIC1_QM0_PQ_ARUSER_31_11_0 0xD200E0 + +#define mmNIC1_QM0_PQ_ARUSER_31_11_1 0xD200E4 + +#define mmNIC1_QM0_PQ_ARUSER_31_11_2 0xD200E8 + +#define mmNIC1_QM0_PQ_ARUSER_31_11_3 0xD200EC + +#define mmNIC1_QM0_PQ_STS0_0 0xD200F0 + +#define mmNIC1_QM0_PQ_STS0_1 0xD200F4 + +#define mmNIC1_QM0_PQ_STS0_2 0xD200F8 + +#define mmNIC1_QM0_PQ_STS0_3 0xD200FC + +#define mmNIC1_QM0_PQ_STS1_0 0xD20100 + +#define mmNIC1_QM0_PQ_STS1_1 0xD20104 + +#define mmNIC1_QM0_PQ_STS1_2 0xD20108 + +#define mmNIC1_QM0_PQ_STS1_3 0xD2010C + +#define mmNIC1_QM0_CQ_CFG0_0 0xD20110 + +#define mmNIC1_QM0_CQ_CFG0_1 0xD20114 + +#define mmNIC1_QM0_CQ_CFG0_2 0xD20118 + +#define mmNIC1_QM0_CQ_CFG0_3 0xD2011C + +#define mmNIC1_QM0_CQ_CFG0_4 0xD20120 + +#define mmNIC1_QM0_CQ_CFG1_0 0xD20124 + +#define mmNIC1_QM0_CQ_CFG1_1 0xD20128 + +#define mmNIC1_QM0_CQ_CFG1_2 0xD2012C + +#define mmNIC1_QM0_CQ_CFG1_3 0xD20130 + +#define mmNIC1_QM0_CQ_CFG1_4 0xD20134 + +#define mmNIC1_QM0_CQ_ARUSER_31_11_0 0xD20138 + +#define mmNIC1_QM0_CQ_ARUSER_31_11_1 0xD2013C + +#define mmNIC1_QM0_CQ_ARUSER_31_11_2 0xD20140 + +#define mmNIC1_QM0_CQ_ARUSER_31_11_3 0xD20144 + +#define mmNIC1_QM0_CQ_ARUSER_31_11_4 0xD20148 + +#define mmNIC1_QM0_CQ_STS0_0 0xD2014C + +#define mmNIC1_QM0_CQ_STS0_1 0xD20150 + +#define mmNIC1_QM0_CQ_STS0_2 0xD20154 + +#define mmNIC1_QM0_CQ_STS0_3 0xD20158 + +#define mmNIC1_QM0_CQ_STS0_4 0xD2015C + +#define mmNIC1_QM0_CQ_STS1_0 0xD20160 + +#define mmNIC1_QM0_CQ_STS1_1 0xD20164 + +#define mmNIC1_QM0_CQ_STS1_2 0xD20168 + +#define mmNIC1_QM0_CQ_STS1_3 0xD2016C + +#define mmNIC1_QM0_CQ_STS1_4 0xD20170 + +#define mmNIC1_QM0_CQ_PTR_LO_0 0xD20174 + +#define mmNIC1_QM0_CQ_PTR_HI_0 0xD20178 + +#define mmNIC1_QM0_CQ_TSIZE_0 0xD2017C + +#define mmNIC1_QM0_CQ_CTL_0 0xD20180 + +#define mmNIC1_QM0_CQ_PTR_LO_1 0xD20184 + +#define mmNIC1_QM0_CQ_PTR_HI_1 0xD20188 + +#define mmNIC1_QM0_CQ_TSIZE_1 0xD2018C + +#define mmNIC1_QM0_CQ_CTL_1 0xD20190 + +#define mmNIC1_QM0_CQ_PTR_LO_2 0xD20194 + +#define mmNIC1_QM0_CQ_PTR_HI_2 0xD20198 + +#define mmNIC1_QM0_CQ_TSIZE_2 0xD2019C + +#define mmNIC1_QM0_CQ_CTL_2 0xD201A0 + +#define mmNIC1_QM0_CQ_PTR_LO_3 0xD201A4 + +#define mmNIC1_QM0_CQ_PTR_HI_3 0xD201A8 + +#define mmNIC1_QM0_CQ_TSIZE_3 0xD201AC + +#define mmNIC1_QM0_CQ_CTL_3 0xD201B0 + +#define mmNIC1_QM0_CQ_PTR_LO_4 0xD201B4 + +#define mmNIC1_QM0_CQ_PTR_HI_4 0xD201B8 + +#define mmNIC1_QM0_CQ_TSIZE_4 0xD201BC + +#define mmNIC1_QM0_CQ_CTL_4 0xD201C0 + +#define mmNIC1_QM0_CQ_PTR_LO_STS_0 0xD201C4 + +#define mmNIC1_QM0_CQ_PTR_LO_STS_1 0xD201C8 + +#define mmNIC1_QM0_CQ_PTR_LO_STS_2 0xD201CC + +#define mmNIC1_QM0_CQ_PTR_LO_STS_3 0xD201D0 + +#define mmNIC1_QM0_CQ_PTR_LO_STS_4 0xD201D4 + +#define mmNIC1_QM0_CQ_PTR_HI_STS_0 0xD201D8 + +#define mmNIC1_QM0_CQ_PTR_HI_STS_1 0xD201DC + +#define mmNIC1_QM0_CQ_PTR_HI_STS_2 0xD201E0 + +#define mmNIC1_QM0_CQ_PTR_HI_STS_3 0xD201E4 + +#define mmNIC1_QM0_CQ_PTR_HI_STS_4 0xD201E8 + +#define mmNIC1_QM0_CQ_TSIZE_STS_0 0xD201EC + +#define mmNIC1_QM0_CQ_TSIZE_STS_1 0xD201F0 + +#define mmNIC1_QM0_CQ_TSIZE_STS_2 0xD201F4 + +#define mmNIC1_QM0_CQ_TSIZE_STS_3 0xD201F8 + +#define mmNIC1_QM0_CQ_TSIZE_STS_4 0xD201FC + +#define mmNIC1_QM0_CQ_CTL_STS_0 0xD20200 + +#define mmNIC1_QM0_CQ_CTL_STS_1 0xD20204 + +#define mmNIC1_QM0_CQ_CTL_STS_2 0xD20208 + +#define mmNIC1_QM0_CQ_CTL_STS_3 0xD2020C + +#define mmNIC1_QM0_CQ_CTL_STS_4 0xD20210 + +#define mmNIC1_QM0_CQ_IFIFO_CNT_0 0xD20214 + +#define mmNIC1_QM0_CQ_IFIFO_CNT_1 0xD20218 + +#define mmNIC1_QM0_CQ_IFIFO_CNT_2 0xD2021C + +#define mmNIC1_QM0_CQ_IFIFO_CNT_3 0xD20220 + +#define mmNIC1_QM0_CQ_IFIFO_CNT_4 0xD20224 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD20228 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD2022C + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD20230 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD20234 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD20238 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD2023C + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD20240 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD20244 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD20248 + +#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD2024C + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD20250 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD20254 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD20258 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD2025C + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD20260 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD20264 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD20268 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD2026C + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD20270 + +#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD20274 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD20278 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD2027C + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD20280 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD20284 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD20288 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD2028C + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD20290 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD20294 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD20298 + +#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD2029C + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD202A0 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD202A4 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD202A8 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD202AC + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD202B0 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD202B4 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD202B8 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD202BC + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD202C0 + +#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD202C4 + +#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD202C8 + +#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD202CC + +#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD202D0 + +#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD202D4 + +#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD202D8 + +#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD202E0 + +#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD202E4 + +#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD202E8 + +#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD202EC + +#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD202F0 + +#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD202F4 + +#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD202F8 + +#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD202FC + +#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD20300 + +#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD20304 + +#define mmNIC1_QM0_CP_FENCE0_RDATA_0 0xD20308 + +#define mmNIC1_QM0_CP_FENCE0_RDATA_1 0xD2030C + +#define mmNIC1_QM0_CP_FENCE0_RDATA_2 0xD20310 + +#define mmNIC1_QM0_CP_FENCE0_RDATA_3 0xD20314 + +#define mmNIC1_QM0_CP_FENCE0_RDATA_4 0xD20318 + +#define mmNIC1_QM0_CP_FENCE1_RDATA_0 0xD2031C + +#define mmNIC1_QM0_CP_FENCE1_RDATA_1 0xD20320 + +#define mmNIC1_QM0_CP_FENCE1_RDATA_2 0xD20324 + +#define mmNIC1_QM0_CP_FENCE1_RDATA_3 0xD20328 + +#define mmNIC1_QM0_CP_FENCE1_RDATA_4 0xD2032C + +#define mmNIC1_QM0_CP_FENCE2_RDATA_0 0xD20330 + +#define mmNIC1_QM0_CP_FENCE2_RDATA_1 0xD20334 + +#define mmNIC1_QM0_CP_FENCE2_RDATA_2 0xD20338 + +#define mmNIC1_QM0_CP_FENCE2_RDATA_3 0xD2033C + +#define mmNIC1_QM0_CP_FENCE2_RDATA_4 0xD20340 + +#define mmNIC1_QM0_CP_FENCE3_RDATA_0 0xD20344 + +#define mmNIC1_QM0_CP_FENCE3_RDATA_1 0xD20348 + +#define mmNIC1_QM0_CP_FENCE3_RDATA_2 0xD2034C + +#define mmNIC1_QM0_CP_FENCE3_RDATA_3 0xD20350 + +#define mmNIC1_QM0_CP_FENCE3_RDATA_4 0xD20354 + +#define mmNIC1_QM0_CP_FENCE0_CNT_0 0xD20358 + +#define mmNIC1_QM0_CP_FENCE0_CNT_1 0xD2035C + +#define mmNIC1_QM0_CP_FENCE0_CNT_2 0xD20360 + +#define mmNIC1_QM0_CP_FENCE0_CNT_3 0xD20364 + +#define mmNIC1_QM0_CP_FENCE0_CNT_4 0xD20368 + +#define mmNIC1_QM0_CP_FENCE1_CNT_0 0xD2036C + +#define mmNIC1_QM0_CP_FENCE1_CNT_1 0xD20370 + +#define mmNIC1_QM0_CP_FENCE1_CNT_2 0xD20374 + +#define mmNIC1_QM0_CP_FENCE1_CNT_3 0xD20378 + +#define mmNIC1_QM0_CP_FENCE1_CNT_4 0xD2037C + +#define mmNIC1_QM0_CP_FENCE2_CNT_0 0xD20380 + +#define mmNIC1_QM0_CP_FENCE2_CNT_1 0xD20384 + +#define mmNIC1_QM0_CP_FENCE2_CNT_2 0xD20388 + +#define mmNIC1_QM0_CP_FENCE2_CNT_3 0xD2038C + +#define mmNIC1_QM0_CP_FENCE2_CNT_4 0xD20390 + +#define mmNIC1_QM0_CP_FENCE3_CNT_0 0xD20394 + +#define mmNIC1_QM0_CP_FENCE3_CNT_1 0xD20398 + +#define mmNIC1_QM0_CP_FENCE3_CNT_2 0xD2039C + +#define mmNIC1_QM0_CP_FENCE3_CNT_3 0xD203A0 + +#define mmNIC1_QM0_CP_FENCE3_CNT_4 0xD203A4 + +#define mmNIC1_QM0_CP_STS_0 0xD203A8 + +#define mmNIC1_QM0_CP_STS_1 0xD203AC + +#define mmNIC1_QM0_CP_STS_2 0xD203B0 + +#define mmNIC1_QM0_CP_STS_3 0xD203B4 + +#define mmNIC1_QM0_CP_STS_4 0xD203B8 + +#define mmNIC1_QM0_CP_CURRENT_INST_LO_0 0xD203BC + +#define mmNIC1_QM0_CP_CURRENT_INST_LO_1 0xD203C0 + +#define mmNIC1_QM0_CP_CURRENT_INST_LO_2 0xD203C4 + +#define mmNIC1_QM0_CP_CURRENT_INST_LO_3 0xD203C8 + +#define mmNIC1_QM0_CP_CURRENT_INST_LO_4 0xD203CC + +#define mmNIC1_QM0_CP_CURRENT_INST_HI_0 0xD203D0 + +#define mmNIC1_QM0_CP_CURRENT_INST_HI_1 0xD203D4 + +#define mmNIC1_QM0_CP_CURRENT_INST_HI_2 0xD203D8 + +#define mmNIC1_QM0_CP_CURRENT_INST_HI_3 0xD203DC + +#define mmNIC1_QM0_CP_CURRENT_INST_HI_4 0xD203E0 + +#define mmNIC1_QM0_CP_BARRIER_CFG_0 0xD203F4 + +#define mmNIC1_QM0_CP_BARRIER_CFG_1 0xD203F8 + +#define mmNIC1_QM0_CP_BARRIER_CFG_2 0xD203FC + +#define mmNIC1_QM0_CP_BARRIER_CFG_3 0xD20400 + +#define mmNIC1_QM0_CP_BARRIER_CFG_4 0xD20404 + +#define mmNIC1_QM0_CP_DBG_0_0 0xD20408 + +#define mmNIC1_QM0_CP_DBG_0_1 0xD2040C + +#define mmNIC1_QM0_CP_DBG_0_2 0xD20410 + +#define mmNIC1_QM0_CP_DBG_0_3 0xD20414 + +#define mmNIC1_QM0_CP_DBG_0_4 0xD20418 + +#define mmNIC1_QM0_CP_ARUSER_31_11_0 0xD2041C + +#define mmNIC1_QM0_CP_ARUSER_31_11_1 0xD20420 + +#define mmNIC1_QM0_CP_ARUSER_31_11_2 0xD20424 + +#define mmNIC1_QM0_CP_ARUSER_31_11_3 0xD20428 + +#define mmNIC1_QM0_CP_ARUSER_31_11_4 0xD2042C + +#define mmNIC1_QM0_CP_AWUSER_31_11_0 0xD20430 + +#define mmNIC1_QM0_CP_AWUSER_31_11_1 0xD20434 + +#define mmNIC1_QM0_CP_AWUSER_31_11_2 0xD20438 + +#define mmNIC1_QM0_CP_AWUSER_31_11_3 0xD2043C + +#define mmNIC1_QM0_CP_AWUSER_31_11_4 0xD20440 + +#define mmNIC1_QM0_ARB_CFG_0 0xD20A00 + +#define mmNIC1_QM0_ARB_CHOISE_Q_PUSH 0xD20A04 + +#define mmNIC1_QM0_ARB_WRR_WEIGHT_0 0xD20A08 + +#define mmNIC1_QM0_ARB_WRR_WEIGHT_1 0xD20A0C + +#define mmNIC1_QM0_ARB_WRR_WEIGHT_2 0xD20A10 + +#define mmNIC1_QM0_ARB_WRR_WEIGHT_3 0xD20A14 + +#define mmNIC1_QM0_ARB_CFG_1 0xD20A18 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_0 0xD20A20 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_1 0xD20A24 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_2 0xD20A28 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_3 0xD20A2C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_4 0xD20A30 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_5 0xD20A34 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_6 0xD20A38 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_7 0xD20A3C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_8 0xD20A40 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_9 0xD20A44 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_10 0xD20A48 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_11 0xD20A4C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_12 0xD20A50 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_13 0xD20A54 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_14 0xD20A58 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_15 0xD20A5C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_16 0xD20A60 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_17 0xD20A64 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_18 0xD20A68 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_19 0xD20A6C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_20 0xD20A70 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_21 0xD20A74 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_22 0xD20A78 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_23 0xD20A7C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 0xD20A80 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_25 0xD20A84 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_26 0xD20A88 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_27 0xD20A8C + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_28 0xD20A90 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_29 0xD20A94 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_30 0xD20A98 + +#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_31 0xD20A9C + +#define mmNIC1_QM0_ARB_MST_CRED_INC 0xD20AA0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD20AA4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD20AA8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD20AAC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD20AB0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD20AB4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD20AB8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD20ABC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD20AC0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD20AC4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD20AC8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD20ACC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD20AD0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD20AD4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD20AD8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD20ADC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD20AE0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD20AE4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD20AE8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD20AEC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD20AF0 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD20AF4 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD20AF8 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD20AFC + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD20B00 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD20B04 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD20B08 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD20B0C + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD20B10 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD20B14 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD20B18 + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD20B1C + +#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD20B20 + +#define mmNIC1_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD20B28 + +#define mmNIC1_QM0_ARB_MST_SLAVE_EN 0xD20B2C + +#define mmNIC1_QM0_ARB_MST_QUIET_PER 0xD20B34 + +#define mmNIC1_QM0_ARB_SLV_CHOISE_WDT 0xD20B38 + +#define mmNIC1_QM0_ARB_SLV_ID 0xD20B3C + +#define mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT 0xD20B44 + +#define mmNIC1_QM0_ARB_MSG_AWUSER_31_11 0xD20B48 + +#define mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD20B4C + +#define mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD20B50 + +#define mmNIC1_QM0_ARB_BASE_LO 0xD20B54 + +#define mmNIC1_QM0_ARB_BASE_HI 0xD20B58 + +#define mmNIC1_QM0_ARB_STATE_STS 0xD20B80 + +#define mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS 0xD20B84 + +#define mmNIC1_QM0_ARB_MSG_STS 0xD20B88 + +#define mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD20B8C + +#define mmNIC1_QM0_ARB_ERR_CAUSE 0xD20B9C + +#define mmNIC1_QM0_ARB_ERR_MSG_EN 0xD20BA0 + +#define mmNIC1_QM0_ARB_ERR_STS_DRP 0xD20BA8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_0 0xD20BB0 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_1 0xD20BB4 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_2 0xD20BB8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_3 0xD20BBC + +#define mmNIC1_QM0_ARB_MST_CRED_STS_4 0xD20BC0 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_5 0xD20BC4 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_6 0xD20BC8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_7 0xD20BCC + +#define mmNIC1_QM0_ARB_MST_CRED_STS_8 0xD20BD0 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_9 0xD20BD4 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_10 0xD20BD8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_11 0xD20BDC + +#define mmNIC1_QM0_ARB_MST_CRED_STS_12 0xD20BE0 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_13 0xD20BE4 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_14 0xD20BE8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_15 0xD20BEC + +#define mmNIC1_QM0_ARB_MST_CRED_STS_16 0xD20BF0 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_17 0xD20BF4 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_18 0xD20BF8 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_19 0xD20BFC + +#define mmNIC1_QM0_ARB_MST_CRED_STS_20 0xD20C00 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_21 0xD20C04 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_22 0xD20C08 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_23 0xD20C0C + +#define mmNIC1_QM0_ARB_MST_CRED_STS_24 0xD20C10 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_25 0xD20C14 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_26 0xD20C18 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_27 0xD20C1C + +#define mmNIC1_QM0_ARB_MST_CRED_STS_28 0xD20C20 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_29 0xD20C24 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_30 0xD20C28 + +#define mmNIC1_QM0_ARB_MST_CRED_STS_31 0xD20C2C + +#define mmNIC1_QM0_CGM_CFG 0xD20C70 + +#define mmNIC1_QM0_CGM_STS 0xD20C74 + +#define mmNIC1_QM0_CGM_CFG1 0xD20C78 + +#define mmNIC1_QM0_LOCAL_RANGE_BASE 0xD20C80 + +#define mmNIC1_QM0_LOCAL_RANGE_SIZE 0xD20C84 + +#define mmNIC1_QM0_CSMR_STRICT_PRIO_CFG 0xD20C90 + +#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1 0xD20C94 + +#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0 0xD20C98 + +#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1 0xD20C9C + +#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0 0xD20CA0 + +#define mmNIC1_QM0_GLBL_AXCACHE 0xD20CA4 + +#define mmNIC1_QM0_IND_GW_APB_CFG 0xD20CB0 + +#define mmNIC1_QM0_IND_GW_APB_WDATA 0xD20CB4 + +#define mmNIC1_QM0_IND_GW_APB_RDATA 0xD20CB8 + +#define mmNIC1_QM0_IND_GW_APB_STATUS 0xD20CBC + +#define mmNIC1_QM0_GLBL_ERR_ADDR_LO 0xD20CD0 + +#define mmNIC1_QM0_GLBL_ERR_ADDR_HI 0xD20CD4 + +#define mmNIC1_QM0_GLBL_ERR_WDATA 0xD20CD8 + +#define mmNIC1_QM0_GLBL_MEM_INIT_BUSY 0xD20D00 + +#endif /* ASIC_REG_NIC1_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h new file mode 100644 index 000000000..1b115ee6d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC1_QM1_REGS_H_ +#define ASIC_REG_NIC1_QM1_REGS_H_ + +/* + ***************************************** + * NIC1_QM1 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC1_QM1_GLBL_CFG0 0xD22000 + +#define mmNIC1_QM1_GLBL_CFG1 0xD22004 + +#define mmNIC1_QM1_GLBL_PROT 0xD22008 + +#define mmNIC1_QM1_GLBL_ERR_CFG 0xD2200C + +#define mmNIC1_QM1_GLBL_SECURE_PROPS_0 0xD22010 + +#define mmNIC1_QM1_GLBL_SECURE_PROPS_1 0xD22014 + +#define mmNIC1_QM1_GLBL_SECURE_PROPS_2 0xD22018 + +#define mmNIC1_QM1_GLBL_SECURE_PROPS_3 0xD2201C + +#define mmNIC1_QM1_GLBL_SECURE_PROPS_4 0xD22020 + +#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 0xD22024 + +#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 0xD22028 + +#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 0xD2202C + +#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 0xD22030 + +#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 0xD22034 + +#define mmNIC1_QM1_GLBL_STS0 0xD22038 + +#define mmNIC1_QM1_GLBL_STS1_0 0xD22040 + +#define mmNIC1_QM1_GLBL_STS1_1 0xD22044 + +#define mmNIC1_QM1_GLBL_STS1_2 0xD22048 + +#define mmNIC1_QM1_GLBL_STS1_3 0xD2204C + +#define mmNIC1_QM1_GLBL_STS1_4 0xD22050 + +#define mmNIC1_QM1_GLBL_MSG_EN_0 0xD22054 + +#define mmNIC1_QM1_GLBL_MSG_EN_1 0xD22058 + +#define mmNIC1_QM1_GLBL_MSG_EN_2 0xD2205C + +#define mmNIC1_QM1_GLBL_MSG_EN_3 0xD22060 + +#define mmNIC1_QM1_GLBL_MSG_EN_4 0xD22068 + +#define mmNIC1_QM1_PQ_BASE_LO_0 0xD22070 + +#define mmNIC1_QM1_PQ_BASE_LO_1 0xD22074 + +#define mmNIC1_QM1_PQ_BASE_LO_2 0xD22078 + +#define mmNIC1_QM1_PQ_BASE_LO_3 0xD2207C + +#define mmNIC1_QM1_PQ_BASE_HI_0 0xD22080 + +#define mmNIC1_QM1_PQ_BASE_HI_1 0xD22084 + +#define mmNIC1_QM1_PQ_BASE_HI_2 0xD22088 + +#define mmNIC1_QM1_PQ_BASE_HI_3 0xD2208C + +#define mmNIC1_QM1_PQ_SIZE_0 0xD22090 + +#define mmNIC1_QM1_PQ_SIZE_1 0xD22094 + +#define mmNIC1_QM1_PQ_SIZE_2 0xD22098 + +#define mmNIC1_QM1_PQ_SIZE_3 0xD2209C + +#define mmNIC1_QM1_PQ_PI_0 0xD220A0 + +#define mmNIC1_QM1_PQ_PI_1 0xD220A4 + +#define mmNIC1_QM1_PQ_PI_2 0xD220A8 + +#define mmNIC1_QM1_PQ_PI_3 0xD220AC + +#define mmNIC1_QM1_PQ_CI_0 0xD220B0 + +#define mmNIC1_QM1_PQ_CI_1 0xD220B4 + +#define mmNIC1_QM1_PQ_CI_2 0xD220B8 + +#define mmNIC1_QM1_PQ_CI_3 0xD220BC + +#define mmNIC1_QM1_PQ_CFG0_0 0xD220C0 + +#define mmNIC1_QM1_PQ_CFG0_1 0xD220C4 + +#define mmNIC1_QM1_PQ_CFG0_2 0xD220C8 + +#define mmNIC1_QM1_PQ_CFG0_3 0xD220CC + +#define mmNIC1_QM1_PQ_CFG1_0 0xD220D0 + +#define mmNIC1_QM1_PQ_CFG1_1 0xD220D4 + +#define mmNIC1_QM1_PQ_CFG1_2 0xD220D8 + +#define mmNIC1_QM1_PQ_CFG1_3 0xD220DC + +#define mmNIC1_QM1_PQ_ARUSER_31_11_0 0xD220E0 + +#define mmNIC1_QM1_PQ_ARUSER_31_11_1 0xD220E4 + +#define mmNIC1_QM1_PQ_ARUSER_31_11_2 0xD220E8 + +#define mmNIC1_QM1_PQ_ARUSER_31_11_3 0xD220EC + +#define mmNIC1_QM1_PQ_STS0_0 0xD220F0 + +#define mmNIC1_QM1_PQ_STS0_1 0xD220F4 + +#define mmNIC1_QM1_PQ_STS0_2 0xD220F8 + +#define mmNIC1_QM1_PQ_STS0_3 0xD220FC + +#define mmNIC1_QM1_PQ_STS1_0 0xD22100 + +#define mmNIC1_QM1_PQ_STS1_1 0xD22104 + +#define mmNIC1_QM1_PQ_STS1_2 0xD22108 + +#define mmNIC1_QM1_PQ_STS1_3 0xD2210C + +#define mmNIC1_QM1_CQ_CFG0_0 0xD22110 + +#define mmNIC1_QM1_CQ_CFG0_1 0xD22114 + +#define mmNIC1_QM1_CQ_CFG0_2 0xD22118 + +#define mmNIC1_QM1_CQ_CFG0_3 0xD2211C + +#define mmNIC1_QM1_CQ_CFG0_4 0xD22120 + +#define mmNIC1_QM1_CQ_CFG1_0 0xD22124 + +#define mmNIC1_QM1_CQ_CFG1_1 0xD22128 + +#define mmNIC1_QM1_CQ_CFG1_2 0xD2212C + +#define mmNIC1_QM1_CQ_CFG1_3 0xD22130 + +#define mmNIC1_QM1_CQ_CFG1_4 0xD22134 + +#define mmNIC1_QM1_CQ_ARUSER_31_11_0 0xD22138 + +#define mmNIC1_QM1_CQ_ARUSER_31_11_1 0xD2213C + +#define mmNIC1_QM1_CQ_ARUSER_31_11_2 0xD22140 + +#define mmNIC1_QM1_CQ_ARUSER_31_11_3 0xD22144 + +#define mmNIC1_QM1_CQ_ARUSER_31_11_4 0xD22148 + +#define mmNIC1_QM1_CQ_STS0_0 0xD2214C + +#define mmNIC1_QM1_CQ_STS0_1 0xD22150 + +#define mmNIC1_QM1_CQ_STS0_2 0xD22154 + +#define mmNIC1_QM1_CQ_STS0_3 0xD22158 + +#define mmNIC1_QM1_CQ_STS0_4 0xD2215C + +#define mmNIC1_QM1_CQ_STS1_0 0xD22160 + +#define mmNIC1_QM1_CQ_STS1_1 0xD22164 + +#define mmNIC1_QM1_CQ_STS1_2 0xD22168 + +#define mmNIC1_QM1_CQ_STS1_3 0xD2216C + +#define mmNIC1_QM1_CQ_STS1_4 0xD22170 + +#define mmNIC1_QM1_CQ_PTR_LO_0 0xD22174 + +#define mmNIC1_QM1_CQ_PTR_HI_0 0xD22178 + +#define mmNIC1_QM1_CQ_TSIZE_0 0xD2217C + +#define mmNIC1_QM1_CQ_CTL_0 0xD22180 + +#define mmNIC1_QM1_CQ_PTR_LO_1 0xD22184 + +#define mmNIC1_QM1_CQ_PTR_HI_1 0xD22188 + +#define mmNIC1_QM1_CQ_TSIZE_1 0xD2218C + +#define mmNIC1_QM1_CQ_CTL_1 0xD22190 + +#define mmNIC1_QM1_CQ_PTR_LO_2 0xD22194 + +#define mmNIC1_QM1_CQ_PTR_HI_2 0xD22198 + +#define mmNIC1_QM1_CQ_TSIZE_2 0xD2219C + +#define mmNIC1_QM1_CQ_CTL_2 0xD221A0 + +#define mmNIC1_QM1_CQ_PTR_LO_3 0xD221A4 + +#define mmNIC1_QM1_CQ_PTR_HI_3 0xD221A8 + +#define mmNIC1_QM1_CQ_TSIZE_3 0xD221AC + +#define mmNIC1_QM1_CQ_CTL_3 0xD221B0 + +#define mmNIC1_QM1_CQ_PTR_LO_4 0xD221B4 + +#define mmNIC1_QM1_CQ_PTR_HI_4 0xD221B8 + +#define mmNIC1_QM1_CQ_TSIZE_4 0xD221BC + +#define mmNIC1_QM1_CQ_CTL_4 0xD221C0 + +#define mmNIC1_QM1_CQ_PTR_LO_STS_0 0xD221C4 + +#define mmNIC1_QM1_CQ_PTR_LO_STS_1 0xD221C8 + +#define mmNIC1_QM1_CQ_PTR_LO_STS_2 0xD221CC + +#define mmNIC1_QM1_CQ_PTR_LO_STS_3 0xD221D0 + +#define mmNIC1_QM1_CQ_PTR_LO_STS_4 0xD221D4 + +#define mmNIC1_QM1_CQ_PTR_HI_STS_0 0xD221D8 + +#define mmNIC1_QM1_CQ_PTR_HI_STS_1 0xD221DC + +#define mmNIC1_QM1_CQ_PTR_HI_STS_2 0xD221E0 + +#define mmNIC1_QM1_CQ_PTR_HI_STS_3 0xD221E4 + +#define mmNIC1_QM1_CQ_PTR_HI_STS_4 0xD221E8 + +#define mmNIC1_QM1_CQ_TSIZE_STS_0 0xD221EC + +#define mmNIC1_QM1_CQ_TSIZE_STS_1 0xD221F0 + +#define mmNIC1_QM1_CQ_TSIZE_STS_2 0xD221F4 + +#define mmNIC1_QM1_CQ_TSIZE_STS_3 0xD221F8 + +#define mmNIC1_QM1_CQ_TSIZE_STS_4 0xD221FC + +#define mmNIC1_QM1_CQ_CTL_STS_0 0xD22200 + +#define mmNIC1_QM1_CQ_CTL_STS_1 0xD22204 + +#define mmNIC1_QM1_CQ_CTL_STS_2 0xD22208 + +#define mmNIC1_QM1_CQ_CTL_STS_3 0xD2220C + +#define mmNIC1_QM1_CQ_CTL_STS_4 0xD22210 + +#define mmNIC1_QM1_CQ_IFIFO_CNT_0 0xD22214 + +#define mmNIC1_QM1_CQ_IFIFO_CNT_1 0xD22218 + +#define mmNIC1_QM1_CQ_IFIFO_CNT_2 0xD2221C + +#define mmNIC1_QM1_CQ_IFIFO_CNT_3 0xD22220 + +#define mmNIC1_QM1_CQ_IFIFO_CNT_4 0xD22224 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD22228 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD2222C + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD22230 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD22234 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD22238 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD2223C + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD22240 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD22244 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD22248 + +#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD2224C + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD22250 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD22254 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD22258 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD2225C + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD22260 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD22264 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD22268 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD2226C + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD22270 + +#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD22274 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD22278 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD2227C + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD22280 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD22284 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD22288 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD2228C + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD22290 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD22294 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD22298 + +#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD2229C + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD222A0 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD222A4 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD222A8 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD222AC + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD222B0 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD222B4 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD222B8 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD222BC + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD222C0 + +#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD222C4 + +#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD222C8 + +#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD222CC + +#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD222D0 + +#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD222D4 + +#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD222D8 + +#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD222E0 + +#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD222E4 + +#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD222E8 + +#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD222EC + +#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD222F0 + +#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD222F4 + +#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD222F8 + +#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD222FC + +#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD22300 + +#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD22304 + +#define mmNIC1_QM1_CP_FENCE0_RDATA_0 0xD22308 + +#define mmNIC1_QM1_CP_FENCE0_RDATA_1 0xD2230C + +#define mmNIC1_QM1_CP_FENCE0_RDATA_2 0xD22310 + +#define mmNIC1_QM1_CP_FENCE0_RDATA_3 0xD22314 + +#define mmNIC1_QM1_CP_FENCE0_RDATA_4 0xD22318 + +#define mmNIC1_QM1_CP_FENCE1_RDATA_0 0xD2231C + +#define mmNIC1_QM1_CP_FENCE1_RDATA_1 0xD22320 + +#define mmNIC1_QM1_CP_FENCE1_RDATA_2 0xD22324 + +#define mmNIC1_QM1_CP_FENCE1_RDATA_3 0xD22328 + +#define mmNIC1_QM1_CP_FENCE1_RDATA_4 0xD2232C + +#define mmNIC1_QM1_CP_FENCE2_RDATA_0 0xD22330 + +#define mmNIC1_QM1_CP_FENCE2_RDATA_1 0xD22334 + +#define mmNIC1_QM1_CP_FENCE2_RDATA_2 0xD22338 + +#define mmNIC1_QM1_CP_FENCE2_RDATA_3 0xD2233C + +#define mmNIC1_QM1_CP_FENCE2_RDATA_4 0xD22340 + +#define mmNIC1_QM1_CP_FENCE3_RDATA_0 0xD22344 + +#define mmNIC1_QM1_CP_FENCE3_RDATA_1 0xD22348 + +#define mmNIC1_QM1_CP_FENCE3_RDATA_2 0xD2234C + +#define mmNIC1_QM1_CP_FENCE3_RDATA_3 0xD22350 + +#define mmNIC1_QM1_CP_FENCE3_RDATA_4 0xD22354 + +#define mmNIC1_QM1_CP_FENCE0_CNT_0 0xD22358 + +#define mmNIC1_QM1_CP_FENCE0_CNT_1 0xD2235C + +#define mmNIC1_QM1_CP_FENCE0_CNT_2 0xD22360 + +#define mmNIC1_QM1_CP_FENCE0_CNT_3 0xD22364 + +#define mmNIC1_QM1_CP_FENCE0_CNT_4 0xD22368 + +#define mmNIC1_QM1_CP_FENCE1_CNT_0 0xD2236C + +#define mmNIC1_QM1_CP_FENCE1_CNT_1 0xD22370 + +#define mmNIC1_QM1_CP_FENCE1_CNT_2 0xD22374 + +#define mmNIC1_QM1_CP_FENCE1_CNT_3 0xD22378 + +#define mmNIC1_QM1_CP_FENCE1_CNT_4 0xD2237C + +#define mmNIC1_QM1_CP_FENCE2_CNT_0 0xD22380 + +#define mmNIC1_QM1_CP_FENCE2_CNT_1 0xD22384 + +#define mmNIC1_QM1_CP_FENCE2_CNT_2 0xD22388 + +#define mmNIC1_QM1_CP_FENCE2_CNT_3 0xD2238C + +#define mmNIC1_QM1_CP_FENCE2_CNT_4 0xD22390 + +#define mmNIC1_QM1_CP_FENCE3_CNT_0 0xD22394 + +#define mmNIC1_QM1_CP_FENCE3_CNT_1 0xD22398 + +#define mmNIC1_QM1_CP_FENCE3_CNT_2 0xD2239C + +#define mmNIC1_QM1_CP_FENCE3_CNT_3 0xD223A0 + +#define mmNIC1_QM1_CP_FENCE3_CNT_4 0xD223A4 + +#define mmNIC1_QM1_CP_STS_0 0xD223A8 + +#define mmNIC1_QM1_CP_STS_1 0xD223AC + +#define mmNIC1_QM1_CP_STS_2 0xD223B0 + +#define mmNIC1_QM1_CP_STS_3 0xD223B4 + +#define mmNIC1_QM1_CP_STS_4 0xD223B8 + +#define mmNIC1_QM1_CP_CURRENT_INST_LO_0 0xD223BC + +#define mmNIC1_QM1_CP_CURRENT_INST_LO_1 0xD223C0 + +#define mmNIC1_QM1_CP_CURRENT_INST_LO_2 0xD223C4 + +#define mmNIC1_QM1_CP_CURRENT_INST_LO_3 0xD223C8 + +#define mmNIC1_QM1_CP_CURRENT_INST_LO_4 0xD223CC + +#define mmNIC1_QM1_CP_CURRENT_INST_HI_0 0xD223D0 + +#define mmNIC1_QM1_CP_CURRENT_INST_HI_1 0xD223D4 + +#define mmNIC1_QM1_CP_CURRENT_INST_HI_2 0xD223D8 + +#define mmNIC1_QM1_CP_CURRENT_INST_HI_3 0xD223DC + +#define mmNIC1_QM1_CP_CURRENT_INST_HI_4 0xD223E0 + +#define mmNIC1_QM1_CP_BARRIER_CFG_0 0xD223F4 + +#define mmNIC1_QM1_CP_BARRIER_CFG_1 0xD223F8 + +#define mmNIC1_QM1_CP_BARRIER_CFG_2 0xD223FC + +#define mmNIC1_QM1_CP_BARRIER_CFG_3 0xD22400 + +#define mmNIC1_QM1_CP_BARRIER_CFG_4 0xD22404 + +#define mmNIC1_QM1_CP_DBG_0_0 0xD22408 + +#define mmNIC1_QM1_CP_DBG_0_1 0xD2240C + +#define mmNIC1_QM1_CP_DBG_0_2 0xD22410 + +#define mmNIC1_QM1_CP_DBG_0_3 0xD22414 + +#define mmNIC1_QM1_CP_DBG_0_4 0xD22418 + +#define mmNIC1_QM1_CP_ARUSER_31_11_0 0xD2241C + +#define mmNIC1_QM1_CP_ARUSER_31_11_1 0xD22420 + +#define mmNIC1_QM1_CP_ARUSER_31_11_2 0xD22424 + +#define mmNIC1_QM1_CP_ARUSER_31_11_3 0xD22428 + +#define mmNIC1_QM1_CP_ARUSER_31_11_4 0xD2242C + +#define mmNIC1_QM1_CP_AWUSER_31_11_0 0xD22430 + +#define mmNIC1_QM1_CP_AWUSER_31_11_1 0xD22434 + +#define mmNIC1_QM1_CP_AWUSER_31_11_2 0xD22438 + +#define mmNIC1_QM1_CP_AWUSER_31_11_3 0xD2243C + +#define mmNIC1_QM1_CP_AWUSER_31_11_4 0xD22440 + +#define mmNIC1_QM1_ARB_CFG_0 0xD22A00 + +#define mmNIC1_QM1_ARB_CHOISE_Q_PUSH 0xD22A04 + +#define mmNIC1_QM1_ARB_WRR_WEIGHT_0 0xD22A08 + +#define mmNIC1_QM1_ARB_WRR_WEIGHT_1 0xD22A0C + +#define mmNIC1_QM1_ARB_WRR_WEIGHT_2 0xD22A10 + +#define mmNIC1_QM1_ARB_WRR_WEIGHT_3 0xD22A14 + +#define mmNIC1_QM1_ARB_CFG_1 0xD22A18 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 0xD22A20 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 0xD22A24 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 0xD22A28 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 0xD22A2C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 0xD22A30 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 0xD22A34 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 0xD22A38 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 0xD22A3C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 0xD22A40 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 0xD22A44 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 0xD22A48 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 0xD22A4C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 0xD22A50 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 0xD22A54 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 0xD22A58 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 0xD22A5C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 0xD22A60 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 0xD22A64 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 0xD22A68 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 0xD22A6C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 0xD22A70 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 0xD22A74 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 0xD22A78 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 0xD22A7C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 0xD22A80 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 0xD22A84 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 0xD22A88 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 0xD22A8C + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 0xD22A90 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 0xD22A94 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 0xD22A98 + +#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 0xD22A9C + +#define mmNIC1_QM1_ARB_MST_CRED_INC 0xD22AA0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD22AA4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD22AA8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD22AAC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD22AB0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD22AB4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD22AB8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD22ABC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD22AC0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD22AC4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD22AC8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD22ACC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD22AD0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD22AD4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD22AD8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD22ADC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD22AE0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD22AE4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD22AE8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD22AEC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD22AF0 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD22AF4 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD22AF8 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD22AFC + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD22B00 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD22B04 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD22B08 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD22B0C + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD22B10 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD22B14 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD22B18 + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD22B1C + +#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD22B20 + +#define mmNIC1_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD22B28 + +#define mmNIC1_QM1_ARB_MST_SLAVE_EN 0xD22B2C + +#define mmNIC1_QM1_ARB_MST_QUIET_PER 0xD22B34 + +#define mmNIC1_QM1_ARB_SLV_CHOISE_WDT 0xD22B38 + +#define mmNIC1_QM1_ARB_SLV_ID 0xD22B3C + +#define mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT 0xD22B44 + +#define mmNIC1_QM1_ARB_MSG_AWUSER_31_11 0xD22B48 + +#define mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD22B4C + +#define mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD22B50 + +#define mmNIC1_QM1_ARB_BASE_LO 0xD22B54 + +#define mmNIC1_QM1_ARB_BASE_HI 0xD22B58 + +#define mmNIC1_QM1_ARB_STATE_STS 0xD22B80 + +#define mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS 0xD22B84 + +#define mmNIC1_QM1_ARB_MSG_STS 0xD22B88 + +#define mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD22B8C + +#define mmNIC1_QM1_ARB_ERR_CAUSE 0xD22B9C + +#define mmNIC1_QM1_ARB_ERR_MSG_EN 0xD22BA0 + +#define mmNIC1_QM1_ARB_ERR_STS_DRP 0xD22BA8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_0 0xD22BB0 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_1 0xD22BB4 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_2 0xD22BB8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_3 0xD22BBC + +#define mmNIC1_QM1_ARB_MST_CRED_STS_4 0xD22BC0 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_5 0xD22BC4 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_6 0xD22BC8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_7 0xD22BCC + +#define mmNIC1_QM1_ARB_MST_CRED_STS_8 0xD22BD0 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_9 0xD22BD4 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_10 0xD22BD8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_11 0xD22BDC + +#define mmNIC1_QM1_ARB_MST_CRED_STS_12 0xD22BE0 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_13 0xD22BE4 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_14 0xD22BE8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_15 0xD22BEC + +#define mmNIC1_QM1_ARB_MST_CRED_STS_16 0xD22BF0 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_17 0xD22BF4 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_18 0xD22BF8 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_19 0xD22BFC + +#define mmNIC1_QM1_ARB_MST_CRED_STS_20 0xD22C00 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_21 0xD22C04 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_22 0xD22C08 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_23 0xD22C0C + +#define mmNIC1_QM1_ARB_MST_CRED_STS_24 0xD22C10 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_25 0xD22C14 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_26 0xD22C18 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_27 0xD22C1C + +#define mmNIC1_QM1_ARB_MST_CRED_STS_28 0xD22C20 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_29 0xD22C24 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_30 0xD22C28 + +#define mmNIC1_QM1_ARB_MST_CRED_STS_31 0xD22C2C + +#define mmNIC1_QM1_CGM_CFG 0xD22C70 + +#define mmNIC1_QM1_CGM_STS 0xD22C74 + +#define mmNIC1_QM1_CGM_CFG1 0xD22C78 + +#define mmNIC1_QM1_LOCAL_RANGE_BASE 0xD22C80 + +#define mmNIC1_QM1_LOCAL_RANGE_SIZE 0xD22C84 + +#define mmNIC1_QM1_CSMR_STRICT_PRIO_CFG 0xD22C90 + +#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 0xD22C94 + +#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 0xD22C98 + +#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 0xD22C9C + +#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 0xD22CA0 + +#define mmNIC1_QM1_GLBL_AXCACHE 0xD22CA4 + +#define mmNIC1_QM1_IND_GW_APB_CFG 0xD22CB0 + +#define mmNIC1_QM1_IND_GW_APB_WDATA 0xD22CB4 + +#define mmNIC1_QM1_IND_GW_APB_RDATA 0xD22CB8 + +#define mmNIC1_QM1_IND_GW_APB_STATUS 0xD22CBC + +#define mmNIC1_QM1_GLBL_ERR_ADDR_LO 0xD22CD0 + +#define mmNIC1_QM1_GLBL_ERR_ADDR_HI 0xD22CD4 + +#define mmNIC1_QM1_GLBL_ERR_WDATA 0xD22CD8 + +#define mmNIC1_QM1_GLBL_MEM_INIT_BUSY 0xD22D00 + +#endif /* ASIC_REG_NIC1_QM1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h new file mode 100644 index 000000000..a89116a45 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC2_QM0_REGS_H_ +#define ASIC_REG_NIC2_QM0_REGS_H_ + +/* + ***************************************** + * NIC2_QM0 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC2_QM0_GLBL_CFG0 0xD60000 + +#define mmNIC2_QM0_GLBL_CFG1 0xD60004 + +#define mmNIC2_QM0_GLBL_PROT 0xD60008 + +#define mmNIC2_QM0_GLBL_ERR_CFG 0xD6000C + +#define mmNIC2_QM0_GLBL_SECURE_PROPS_0 0xD60010 + +#define mmNIC2_QM0_GLBL_SECURE_PROPS_1 0xD60014 + +#define mmNIC2_QM0_GLBL_SECURE_PROPS_2 0xD60018 + +#define mmNIC2_QM0_GLBL_SECURE_PROPS_3 0xD6001C + +#define mmNIC2_QM0_GLBL_SECURE_PROPS_4 0xD60020 + +#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 0xD60024 + +#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 0xD60028 + +#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 0xD6002C + +#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 0xD60030 + +#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 0xD60034 + +#define mmNIC2_QM0_GLBL_STS0 0xD60038 + +#define mmNIC2_QM0_GLBL_STS1_0 0xD60040 + +#define mmNIC2_QM0_GLBL_STS1_1 0xD60044 + +#define mmNIC2_QM0_GLBL_STS1_2 0xD60048 + +#define mmNIC2_QM0_GLBL_STS1_3 0xD6004C + +#define mmNIC2_QM0_GLBL_STS1_4 0xD60050 + +#define mmNIC2_QM0_GLBL_MSG_EN_0 0xD60054 + +#define mmNIC2_QM0_GLBL_MSG_EN_1 0xD60058 + +#define mmNIC2_QM0_GLBL_MSG_EN_2 0xD6005C + +#define mmNIC2_QM0_GLBL_MSG_EN_3 0xD60060 + +#define mmNIC2_QM0_GLBL_MSG_EN_4 0xD60068 + +#define mmNIC2_QM0_PQ_BASE_LO_0 0xD60070 + +#define mmNIC2_QM0_PQ_BASE_LO_1 0xD60074 + +#define mmNIC2_QM0_PQ_BASE_LO_2 0xD60078 + +#define mmNIC2_QM0_PQ_BASE_LO_3 0xD6007C + +#define mmNIC2_QM0_PQ_BASE_HI_0 0xD60080 + +#define mmNIC2_QM0_PQ_BASE_HI_1 0xD60084 + +#define mmNIC2_QM0_PQ_BASE_HI_2 0xD60088 + +#define mmNIC2_QM0_PQ_BASE_HI_3 0xD6008C + +#define mmNIC2_QM0_PQ_SIZE_0 0xD60090 + +#define mmNIC2_QM0_PQ_SIZE_1 0xD60094 + +#define mmNIC2_QM0_PQ_SIZE_2 0xD60098 + +#define mmNIC2_QM0_PQ_SIZE_3 0xD6009C + +#define mmNIC2_QM0_PQ_PI_0 0xD600A0 + +#define mmNIC2_QM0_PQ_PI_1 0xD600A4 + +#define mmNIC2_QM0_PQ_PI_2 0xD600A8 + +#define mmNIC2_QM0_PQ_PI_3 0xD600AC + +#define mmNIC2_QM0_PQ_CI_0 0xD600B0 + +#define mmNIC2_QM0_PQ_CI_1 0xD600B4 + +#define mmNIC2_QM0_PQ_CI_2 0xD600B8 + +#define mmNIC2_QM0_PQ_CI_3 0xD600BC + +#define mmNIC2_QM0_PQ_CFG0_0 0xD600C0 + +#define mmNIC2_QM0_PQ_CFG0_1 0xD600C4 + +#define mmNIC2_QM0_PQ_CFG0_2 0xD600C8 + +#define mmNIC2_QM0_PQ_CFG0_3 0xD600CC + +#define mmNIC2_QM0_PQ_CFG1_0 0xD600D0 + +#define mmNIC2_QM0_PQ_CFG1_1 0xD600D4 + +#define mmNIC2_QM0_PQ_CFG1_2 0xD600D8 + +#define mmNIC2_QM0_PQ_CFG1_3 0xD600DC + +#define mmNIC2_QM0_PQ_ARUSER_31_11_0 0xD600E0 + +#define mmNIC2_QM0_PQ_ARUSER_31_11_1 0xD600E4 + +#define mmNIC2_QM0_PQ_ARUSER_31_11_2 0xD600E8 + +#define mmNIC2_QM0_PQ_ARUSER_31_11_3 0xD600EC + +#define mmNIC2_QM0_PQ_STS0_0 0xD600F0 + +#define mmNIC2_QM0_PQ_STS0_1 0xD600F4 + +#define mmNIC2_QM0_PQ_STS0_2 0xD600F8 + +#define mmNIC2_QM0_PQ_STS0_3 0xD600FC + +#define mmNIC2_QM0_PQ_STS1_0 0xD60100 + +#define mmNIC2_QM0_PQ_STS1_1 0xD60104 + +#define mmNIC2_QM0_PQ_STS1_2 0xD60108 + +#define mmNIC2_QM0_PQ_STS1_3 0xD6010C + +#define mmNIC2_QM0_CQ_CFG0_0 0xD60110 + +#define mmNIC2_QM0_CQ_CFG0_1 0xD60114 + +#define mmNIC2_QM0_CQ_CFG0_2 0xD60118 + +#define mmNIC2_QM0_CQ_CFG0_3 0xD6011C + +#define mmNIC2_QM0_CQ_CFG0_4 0xD60120 + +#define mmNIC2_QM0_CQ_CFG1_0 0xD60124 + +#define mmNIC2_QM0_CQ_CFG1_1 0xD60128 + +#define mmNIC2_QM0_CQ_CFG1_2 0xD6012C + +#define mmNIC2_QM0_CQ_CFG1_3 0xD60130 + +#define mmNIC2_QM0_CQ_CFG1_4 0xD60134 + +#define mmNIC2_QM0_CQ_ARUSER_31_11_0 0xD60138 + +#define mmNIC2_QM0_CQ_ARUSER_31_11_1 0xD6013C + +#define mmNIC2_QM0_CQ_ARUSER_31_11_2 0xD60140 + +#define mmNIC2_QM0_CQ_ARUSER_31_11_3 0xD60144 + +#define mmNIC2_QM0_CQ_ARUSER_31_11_4 0xD60148 + +#define mmNIC2_QM0_CQ_STS0_0 0xD6014C + +#define mmNIC2_QM0_CQ_STS0_1 0xD60150 + +#define mmNIC2_QM0_CQ_STS0_2 0xD60154 + +#define mmNIC2_QM0_CQ_STS0_3 0xD60158 + +#define mmNIC2_QM0_CQ_STS0_4 0xD6015C + +#define mmNIC2_QM0_CQ_STS1_0 0xD60160 + +#define mmNIC2_QM0_CQ_STS1_1 0xD60164 + +#define mmNIC2_QM0_CQ_STS1_2 0xD60168 + +#define mmNIC2_QM0_CQ_STS1_3 0xD6016C + +#define mmNIC2_QM0_CQ_STS1_4 0xD60170 + +#define mmNIC2_QM0_CQ_PTR_LO_0 0xD60174 + +#define mmNIC2_QM0_CQ_PTR_HI_0 0xD60178 + +#define mmNIC2_QM0_CQ_TSIZE_0 0xD6017C + +#define mmNIC2_QM0_CQ_CTL_0 0xD60180 + +#define mmNIC2_QM0_CQ_PTR_LO_1 0xD60184 + +#define mmNIC2_QM0_CQ_PTR_HI_1 0xD60188 + +#define mmNIC2_QM0_CQ_TSIZE_1 0xD6018C + +#define mmNIC2_QM0_CQ_CTL_1 0xD60190 + +#define mmNIC2_QM0_CQ_PTR_LO_2 0xD60194 + +#define mmNIC2_QM0_CQ_PTR_HI_2 0xD60198 + +#define mmNIC2_QM0_CQ_TSIZE_2 0xD6019C + +#define mmNIC2_QM0_CQ_CTL_2 0xD601A0 + +#define mmNIC2_QM0_CQ_PTR_LO_3 0xD601A4 + +#define mmNIC2_QM0_CQ_PTR_HI_3 0xD601A8 + +#define mmNIC2_QM0_CQ_TSIZE_3 0xD601AC + +#define mmNIC2_QM0_CQ_CTL_3 0xD601B0 + +#define mmNIC2_QM0_CQ_PTR_LO_4 0xD601B4 + +#define mmNIC2_QM0_CQ_PTR_HI_4 0xD601B8 + +#define mmNIC2_QM0_CQ_TSIZE_4 0xD601BC + +#define mmNIC2_QM0_CQ_CTL_4 0xD601C0 + +#define mmNIC2_QM0_CQ_PTR_LO_STS_0 0xD601C4 + +#define mmNIC2_QM0_CQ_PTR_LO_STS_1 0xD601C8 + +#define mmNIC2_QM0_CQ_PTR_LO_STS_2 0xD601CC + +#define mmNIC2_QM0_CQ_PTR_LO_STS_3 0xD601D0 + +#define mmNIC2_QM0_CQ_PTR_LO_STS_4 0xD601D4 + +#define mmNIC2_QM0_CQ_PTR_HI_STS_0 0xD601D8 + +#define mmNIC2_QM0_CQ_PTR_HI_STS_1 0xD601DC + +#define mmNIC2_QM0_CQ_PTR_HI_STS_2 0xD601E0 + +#define mmNIC2_QM0_CQ_PTR_HI_STS_3 0xD601E4 + +#define mmNIC2_QM0_CQ_PTR_HI_STS_4 0xD601E8 + +#define mmNIC2_QM0_CQ_TSIZE_STS_0 0xD601EC + +#define mmNIC2_QM0_CQ_TSIZE_STS_1 0xD601F0 + +#define mmNIC2_QM0_CQ_TSIZE_STS_2 0xD601F4 + +#define mmNIC2_QM0_CQ_TSIZE_STS_3 0xD601F8 + +#define mmNIC2_QM0_CQ_TSIZE_STS_4 0xD601FC + +#define mmNIC2_QM0_CQ_CTL_STS_0 0xD60200 + +#define mmNIC2_QM0_CQ_CTL_STS_1 0xD60204 + +#define mmNIC2_QM0_CQ_CTL_STS_2 0xD60208 + +#define mmNIC2_QM0_CQ_CTL_STS_3 0xD6020C + +#define mmNIC2_QM0_CQ_CTL_STS_4 0xD60210 + +#define mmNIC2_QM0_CQ_IFIFO_CNT_0 0xD60214 + +#define mmNIC2_QM0_CQ_IFIFO_CNT_1 0xD60218 + +#define mmNIC2_QM0_CQ_IFIFO_CNT_2 0xD6021C + +#define mmNIC2_QM0_CQ_IFIFO_CNT_3 0xD60220 + +#define mmNIC2_QM0_CQ_IFIFO_CNT_4 0xD60224 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD60228 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD6022C + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD60230 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD60234 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD60238 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD6023C + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD60240 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD60244 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD60248 + +#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD6024C + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD60250 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD60254 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD60258 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD6025C + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD60260 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD60264 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD60268 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD6026C + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD60270 + +#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD60274 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD60278 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD6027C + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD60280 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD60284 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD60288 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD6028C + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD60290 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD60294 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD60298 + +#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD6029C + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD602A0 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD602A4 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD602A8 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD602AC + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD602B0 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD602B4 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD602B8 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD602BC + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD602C0 + +#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD602C4 + +#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD602C8 + +#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD602CC + +#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD602D0 + +#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD602D4 + +#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD602D8 + +#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD602E0 + +#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD602E4 + +#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD602E8 + +#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD602EC + +#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD602F0 + +#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD602F4 + +#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD602F8 + +#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD602FC + +#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD60300 + +#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD60304 + +#define mmNIC2_QM0_CP_FENCE0_RDATA_0 0xD60308 + +#define mmNIC2_QM0_CP_FENCE0_RDATA_1 0xD6030C + +#define mmNIC2_QM0_CP_FENCE0_RDATA_2 0xD60310 + +#define mmNIC2_QM0_CP_FENCE0_RDATA_3 0xD60314 + +#define mmNIC2_QM0_CP_FENCE0_RDATA_4 0xD60318 + +#define mmNIC2_QM0_CP_FENCE1_RDATA_0 0xD6031C + +#define mmNIC2_QM0_CP_FENCE1_RDATA_1 0xD60320 + +#define mmNIC2_QM0_CP_FENCE1_RDATA_2 0xD60324 + +#define mmNIC2_QM0_CP_FENCE1_RDATA_3 0xD60328 + +#define mmNIC2_QM0_CP_FENCE1_RDATA_4 0xD6032C + +#define mmNIC2_QM0_CP_FENCE2_RDATA_0 0xD60330 + +#define mmNIC2_QM0_CP_FENCE2_RDATA_1 0xD60334 + +#define mmNIC2_QM0_CP_FENCE2_RDATA_2 0xD60338 + +#define mmNIC2_QM0_CP_FENCE2_RDATA_3 0xD6033C + +#define mmNIC2_QM0_CP_FENCE2_RDATA_4 0xD60340 + +#define mmNIC2_QM0_CP_FENCE3_RDATA_0 0xD60344 + +#define mmNIC2_QM0_CP_FENCE3_RDATA_1 0xD60348 + +#define mmNIC2_QM0_CP_FENCE3_RDATA_2 0xD6034C + +#define mmNIC2_QM0_CP_FENCE3_RDATA_3 0xD60350 + +#define mmNIC2_QM0_CP_FENCE3_RDATA_4 0xD60354 + +#define mmNIC2_QM0_CP_FENCE0_CNT_0 0xD60358 + +#define mmNIC2_QM0_CP_FENCE0_CNT_1 0xD6035C + +#define mmNIC2_QM0_CP_FENCE0_CNT_2 0xD60360 + +#define mmNIC2_QM0_CP_FENCE0_CNT_3 0xD60364 + +#define mmNIC2_QM0_CP_FENCE0_CNT_4 0xD60368 + +#define mmNIC2_QM0_CP_FENCE1_CNT_0 0xD6036C + +#define mmNIC2_QM0_CP_FENCE1_CNT_1 0xD60370 + +#define mmNIC2_QM0_CP_FENCE1_CNT_2 0xD60374 + +#define mmNIC2_QM0_CP_FENCE1_CNT_3 0xD60378 + +#define mmNIC2_QM0_CP_FENCE1_CNT_4 0xD6037C + +#define mmNIC2_QM0_CP_FENCE2_CNT_0 0xD60380 + +#define mmNIC2_QM0_CP_FENCE2_CNT_1 0xD60384 + +#define mmNIC2_QM0_CP_FENCE2_CNT_2 0xD60388 + +#define mmNIC2_QM0_CP_FENCE2_CNT_3 0xD6038C + +#define mmNIC2_QM0_CP_FENCE2_CNT_4 0xD60390 + +#define mmNIC2_QM0_CP_FENCE3_CNT_0 0xD60394 + +#define mmNIC2_QM0_CP_FENCE3_CNT_1 0xD60398 + +#define mmNIC2_QM0_CP_FENCE3_CNT_2 0xD6039C + +#define mmNIC2_QM0_CP_FENCE3_CNT_3 0xD603A0 + +#define mmNIC2_QM0_CP_FENCE3_CNT_4 0xD603A4 + +#define mmNIC2_QM0_CP_STS_0 0xD603A8 + +#define mmNIC2_QM0_CP_STS_1 0xD603AC + +#define mmNIC2_QM0_CP_STS_2 0xD603B0 + +#define mmNIC2_QM0_CP_STS_3 0xD603B4 + +#define mmNIC2_QM0_CP_STS_4 0xD603B8 + +#define mmNIC2_QM0_CP_CURRENT_INST_LO_0 0xD603BC + +#define mmNIC2_QM0_CP_CURRENT_INST_LO_1 0xD603C0 + +#define mmNIC2_QM0_CP_CURRENT_INST_LO_2 0xD603C4 + +#define mmNIC2_QM0_CP_CURRENT_INST_LO_3 0xD603C8 + +#define mmNIC2_QM0_CP_CURRENT_INST_LO_4 0xD603CC + +#define mmNIC2_QM0_CP_CURRENT_INST_HI_0 0xD603D0 + +#define mmNIC2_QM0_CP_CURRENT_INST_HI_1 0xD603D4 + +#define mmNIC2_QM0_CP_CURRENT_INST_HI_2 0xD603D8 + +#define mmNIC2_QM0_CP_CURRENT_INST_HI_3 0xD603DC + +#define mmNIC2_QM0_CP_CURRENT_INST_HI_4 0xD603E0 + +#define mmNIC2_QM0_CP_BARRIER_CFG_0 0xD603F4 + +#define mmNIC2_QM0_CP_BARRIER_CFG_1 0xD603F8 + +#define mmNIC2_QM0_CP_BARRIER_CFG_2 0xD603FC + +#define mmNIC2_QM0_CP_BARRIER_CFG_3 0xD60400 + +#define mmNIC2_QM0_CP_BARRIER_CFG_4 0xD60404 + +#define mmNIC2_QM0_CP_DBG_0_0 0xD60408 + +#define mmNIC2_QM0_CP_DBG_0_1 0xD6040C + +#define mmNIC2_QM0_CP_DBG_0_2 0xD60410 + +#define mmNIC2_QM0_CP_DBG_0_3 0xD60414 + +#define mmNIC2_QM0_CP_DBG_0_4 0xD60418 + +#define mmNIC2_QM0_CP_ARUSER_31_11_0 0xD6041C + +#define mmNIC2_QM0_CP_ARUSER_31_11_1 0xD60420 + +#define mmNIC2_QM0_CP_ARUSER_31_11_2 0xD60424 + +#define mmNIC2_QM0_CP_ARUSER_31_11_3 0xD60428 + +#define mmNIC2_QM0_CP_ARUSER_31_11_4 0xD6042C + +#define mmNIC2_QM0_CP_AWUSER_31_11_0 0xD60430 + +#define mmNIC2_QM0_CP_AWUSER_31_11_1 0xD60434 + +#define mmNIC2_QM0_CP_AWUSER_31_11_2 0xD60438 + +#define mmNIC2_QM0_CP_AWUSER_31_11_3 0xD6043C + +#define mmNIC2_QM0_CP_AWUSER_31_11_4 0xD60440 + +#define mmNIC2_QM0_ARB_CFG_0 0xD60A00 + +#define mmNIC2_QM0_ARB_CHOISE_Q_PUSH 0xD60A04 + +#define mmNIC2_QM0_ARB_WRR_WEIGHT_0 0xD60A08 + +#define mmNIC2_QM0_ARB_WRR_WEIGHT_1 0xD60A0C + +#define mmNIC2_QM0_ARB_WRR_WEIGHT_2 0xD60A10 + +#define mmNIC2_QM0_ARB_WRR_WEIGHT_3 0xD60A14 + +#define mmNIC2_QM0_ARB_CFG_1 0xD60A18 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 0xD60A20 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 0xD60A24 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 0xD60A28 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 0xD60A2C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 0xD60A30 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 0xD60A34 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 0xD60A38 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 0xD60A3C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 0xD60A40 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 0xD60A44 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 0xD60A48 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 0xD60A4C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 0xD60A50 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 0xD60A54 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 0xD60A58 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 0xD60A5C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 0xD60A60 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 0xD60A64 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 0xD60A68 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 0xD60A6C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 0xD60A70 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 0xD60A74 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 0xD60A78 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 0xD60A7C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 0xD60A80 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 0xD60A84 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 0xD60A88 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 0xD60A8C + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 0xD60A90 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 0xD60A94 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 0xD60A98 + +#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 0xD60A9C + +#define mmNIC2_QM0_ARB_MST_CRED_INC 0xD60AA0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD60AA4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD60AA8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD60AAC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD60AB0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD60AB4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD60AB8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD60ABC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD60AC0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD60AC4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD60AC8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD60ACC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD60AD0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD60AD4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD60AD8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD60ADC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD60AE0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD60AE4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD60AE8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD60AEC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD60AF0 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD60AF4 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD60AF8 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD60AFC + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD60B00 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD60B04 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD60B08 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD60B0C + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD60B10 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD60B14 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD60B18 + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD60B1C + +#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD60B20 + +#define mmNIC2_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD60B28 + +#define mmNIC2_QM0_ARB_MST_SLAVE_EN 0xD60B2C + +#define mmNIC2_QM0_ARB_MST_QUIET_PER 0xD60B34 + +#define mmNIC2_QM0_ARB_SLV_CHOISE_WDT 0xD60B38 + +#define mmNIC2_QM0_ARB_SLV_ID 0xD60B3C + +#define mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT 0xD60B44 + +#define mmNIC2_QM0_ARB_MSG_AWUSER_31_11 0xD60B48 + +#define mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD60B4C + +#define mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD60B50 + +#define mmNIC2_QM0_ARB_BASE_LO 0xD60B54 + +#define mmNIC2_QM0_ARB_BASE_HI 0xD60B58 + +#define mmNIC2_QM0_ARB_STATE_STS 0xD60B80 + +#define mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS 0xD60B84 + +#define mmNIC2_QM0_ARB_MSG_STS 0xD60B88 + +#define mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD60B8C + +#define mmNIC2_QM0_ARB_ERR_CAUSE 0xD60B9C + +#define mmNIC2_QM0_ARB_ERR_MSG_EN 0xD60BA0 + +#define mmNIC2_QM0_ARB_ERR_STS_DRP 0xD60BA8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_0 0xD60BB0 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_1 0xD60BB4 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_2 0xD60BB8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_3 0xD60BBC + +#define mmNIC2_QM0_ARB_MST_CRED_STS_4 0xD60BC0 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_5 0xD60BC4 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_6 0xD60BC8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_7 0xD60BCC + +#define mmNIC2_QM0_ARB_MST_CRED_STS_8 0xD60BD0 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_9 0xD60BD4 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_10 0xD60BD8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_11 0xD60BDC + +#define mmNIC2_QM0_ARB_MST_CRED_STS_12 0xD60BE0 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_13 0xD60BE4 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_14 0xD60BE8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_15 0xD60BEC + +#define mmNIC2_QM0_ARB_MST_CRED_STS_16 0xD60BF0 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_17 0xD60BF4 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_18 0xD60BF8 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_19 0xD60BFC + +#define mmNIC2_QM0_ARB_MST_CRED_STS_20 0xD60C00 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_21 0xD60C04 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_22 0xD60C08 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_23 0xD60C0C + +#define mmNIC2_QM0_ARB_MST_CRED_STS_24 0xD60C10 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_25 0xD60C14 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_26 0xD60C18 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_27 0xD60C1C + +#define mmNIC2_QM0_ARB_MST_CRED_STS_28 0xD60C20 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_29 0xD60C24 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_30 0xD60C28 + +#define mmNIC2_QM0_ARB_MST_CRED_STS_31 0xD60C2C + +#define mmNIC2_QM0_CGM_CFG 0xD60C70 + +#define mmNIC2_QM0_CGM_STS 0xD60C74 + +#define mmNIC2_QM0_CGM_CFG1 0xD60C78 + +#define mmNIC2_QM0_LOCAL_RANGE_BASE 0xD60C80 + +#define mmNIC2_QM0_LOCAL_RANGE_SIZE 0xD60C84 + +#define mmNIC2_QM0_CSMR_STRICT_PRIO_CFG 0xD60C90 + +#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 0xD60C94 + +#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 0xD60C98 + +#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 0xD60C9C + +#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 0xD60CA0 + +#define mmNIC2_QM0_GLBL_AXCACHE 0xD60CA4 + +#define mmNIC2_QM0_IND_GW_APB_CFG 0xD60CB0 + +#define mmNIC2_QM0_IND_GW_APB_WDATA 0xD60CB4 + +#define mmNIC2_QM0_IND_GW_APB_RDATA 0xD60CB8 + +#define mmNIC2_QM0_IND_GW_APB_STATUS 0xD60CBC + +#define mmNIC2_QM0_GLBL_ERR_ADDR_LO 0xD60CD0 + +#define mmNIC2_QM0_GLBL_ERR_ADDR_HI 0xD60CD4 + +#define mmNIC2_QM0_GLBL_ERR_WDATA 0xD60CD8 + +#define mmNIC2_QM0_GLBL_MEM_INIT_BUSY 0xD60D00 + +#endif /* ASIC_REG_NIC2_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h new file mode 100644 index 000000000..b7f091ddc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC2_QM1_REGS_H_ +#define ASIC_REG_NIC2_QM1_REGS_H_ + +/* + ***************************************** + * NIC2_QM1 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC2_QM1_GLBL_CFG0 0xD62000 + +#define mmNIC2_QM1_GLBL_CFG1 0xD62004 + +#define mmNIC2_QM1_GLBL_PROT 0xD62008 + +#define mmNIC2_QM1_GLBL_ERR_CFG 0xD6200C + +#define mmNIC2_QM1_GLBL_SECURE_PROPS_0 0xD62010 + +#define mmNIC2_QM1_GLBL_SECURE_PROPS_1 0xD62014 + +#define mmNIC2_QM1_GLBL_SECURE_PROPS_2 0xD62018 + +#define mmNIC2_QM1_GLBL_SECURE_PROPS_3 0xD6201C + +#define mmNIC2_QM1_GLBL_SECURE_PROPS_4 0xD62020 + +#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0 0xD62024 + +#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1 0xD62028 + +#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2 0xD6202C + +#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3 0xD62030 + +#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4 0xD62034 + +#define mmNIC2_QM1_GLBL_STS0 0xD62038 + +#define mmNIC2_QM1_GLBL_STS1_0 0xD62040 + +#define mmNIC2_QM1_GLBL_STS1_1 0xD62044 + +#define mmNIC2_QM1_GLBL_STS1_2 0xD62048 + +#define mmNIC2_QM1_GLBL_STS1_3 0xD6204C + +#define mmNIC2_QM1_GLBL_STS1_4 0xD62050 + +#define mmNIC2_QM1_GLBL_MSG_EN_0 0xD62054 + +#define mmNIC2_QM1_GLBL_MSG_EN_1 0xD62058 + +#define mmNIC2_QM1_GLBL_MSG_EN_2 0xD6205C + +#define mmNIC2_QM1_GLBL_MSG_EN_3 0xD62060 + +#define mmNIC2_QM1_GLBL_MSG_EN_4 0xD62068 + +#define mmNIC2_QM1_PQ_BASE_LO_0 0xD62070 + +#define mmNIC2_QM1_PQ_BASE_LO_1 0xD62074 + +#define mmNIC2_QM1_PQ_BASE_LO_2 0xD62078 + +#define mmNIC2_QM1_PQ_BASE_LO_3 0xD6207C + +#define mmNIC2_QM1_PQ_BASE_HI_0 0xD62080 + +#define mmNIC2_QM1_PQ_BASE_HI_1 0xD62084 + +#define mmNIC2_QM1_PQ_BASE_HI_2 0xD62088 + +#define mmNIC2_QM1_PQ_BASE_HI_3 0xD6208C + +#define mmNIC2_QM1_PQ_SIZE_0 0xD62090 + +#define mmNIC2_QM1_PQ_SIZE_1 0xD62094 + +#define mmNIC2_QM1_PQ_SIZE_2 0xD62098 + +#define mmNIC2_QM1_PQ_SIZE_3 0xD6209C + +#define mmNIC2_QM1_PQ_PI_0 0xD620A0 + +#define mmNIC2_QM1_PQ_PI_1 0xD620A4 + +#define mmNIC2_QM1_PQ_PI_2 0xD620A8 + +#define mmNIC2_QM1_PQ_PI_3 0xD620AC + +#define mmNIC2_QM1_PQ_CI_0 0xD620B0 + +#define mmNIC2_QM1_PQ_CI_1 0xD620B4 + +#define mmNIC2_QM1_PQ_CI_2 0xD620B8 + +#define mmNIC2_QM1_PQ_CI_3 0xD620BC + +#define mmNIC2_QM1_PQ_CFG0_0 0xD620C0 + +#define mmNIC2_QM1_PQ_CFG0_1 0xD620C4 + +#define mmNIC2_QM1_PQ_CFG0_2 0xD620C8 + +#define mmNIC2_QM1_PQ_CFG0_3 0xD620CC + +#define mmNIC2_QM1_PQ_CFG1_0 0xD620D0 + +#define mmNIC2_QM1_PQ_CFG1_1 0xD620D4 + +#define mmNIC2_QM1_PQ_CFG1_2 0xD620D8 + +#define mmNIC2_QM1_PQ_CFG1_3 0xD620DC + +#define mmNIC2_QM1_PQ_ARUSER_31_11_0 0xD620E0 + +#define mmNIC2_QM1_PQ_ARUSER_31_11_1 0xD620E4 + +#define mmNIC2_QM1_PQ_ARUSER_31_11_2 0xD620E8 + +#define mmNIC2_QM1_PQ_ARUSER_31_11_3 0xD620EC + +#define mmNIC2_QM1_PQ_STS0_0 0xD620F0 + +#define mmNIC2_QM1_PQ_STS0_1 0xD620F4 + +#define mmNIC2_QM1_PQ_STS0_2 0xD620F8 + +#define mmNIC2_QM1_PQ_STS0_3 0xD620FC + +#define mmNIC2_QM1_PQ_STS1_0 0xD62100 + +#define mmNIC2_QM1_PQ_STS1_1 0xD62104 + +#define mmNIC2_QM1_PQ_STS1_2 0xD62108 + +#define mmNIC2_QM1_PQ_STS1_3 0xD6210C + +#define mmNIC2_QM1_CQ_CFG0_0 0xD62110 + +#define mmNIC2_QM1_CQ_CFG0_1 0xD62114 + +#define mmNIC2_QM1_CQ_CFG0_2 0xD62118 + +#define mmNIC2_QM1_CQ_CFG0_3 0xD6211C + +#define mmNIC2_QM1_CQ_CFG0_4 0xD62120 + +#define mmNIC2_QM1_CQ_CFG1_0 0xD62124 + +#define mmNIC2_QM1_CQ_CFG1_1 0xD62128 + +#define mmNIC2_QM1_CQ_CFG1_2 0xD6212C + +#define mmNIC2_QM1_CQ_CFG1_3 0xD62130 + +#define mmNIC2_QM1_CQ_CFG1_4 0xD62134 + +#define mmNIC2_QM1_CQ_ARUSER_31_11_0 0xD62138 + +#define mmNIC2_QM1_CQ_ARUSER_31_11_1 0xD6213C + +#define mmNIC2_QM1_CQ_ARUSER_31_11_2 0xD62140 + +#define mmNIC2_QM1_CQ_ARUSER_31_11_3 0xD62144 + +#define mmNIC2_QM1_CQ_ARUSER_31_11_4 0xD62148 + +#define mmNIC2_QM1_CQ_STS0_0 0xD6214C + +#define mmNIC2_QM1_CQ_STS0_1 0xD62150 + +#define mmNIC2_QM1_CQ_STS0_2 0xD62154 + +#define mmNIC2_QM1_CQ_STS0_3 0xD62158 + +#define mmNIC2_QM1_CQ_STS0_4 0xD6215C + +#define mmNIC2_QM1_CQ_STS1_0 0xD62160 + +#define mmNIC2_QM1_CQ_STS1_1 0xD62164 + +#define mmNIC2_QM1_CQ_STS1_2 0xD62168 + +#define mmNIC2_QM1_CQ_STS1_3 0xD6216C + +#define mmNIC2_QM1_CQ_STS1_4 0xD62170 + +#define mmNIC2_QM1_CQ_PTR_LO_0 0xD62174 + +#define mmNIC2_QM1_CQ_PTR_HI_0 0xD62178 + +#define mmNIC2_QM1_CQ_TSIZE_0 0xD6217C + +#define mmNIC2_QM1_CQ_CTL_0 0xD62180 + +#define mmNIC2_QM1_CQ_PTR_LO_1 0xD62184 + +#define mmNIC2_QM1_CQ_PTR_HI_1 0xD62188 + +#define mmNIC2_QM1_CQ_TSIZE_1 0xD6218C + +#define mmNIC2_QM1_CQ_CTL_1 0xD62190 + +#define mmNIC2_QM1_CQ_PTR_LO_2 0xD62194 + +#define mmNIC2_QM1_CQ_PTR_HI_2 0xD62198 + +#define mmNIC2_QM1_CQ_TSIZE_2 0xD6219C + +#define mmNIC2_QM1_CQ_CTL_2 0xD621A0 + +#define mmNIC2_QM1_CQ_PTR_LO_3 0xD621A4 + +#define mmNIC2_QM1_CQ_PTR_HI_3 0xD621A8 + +#define mmNIC2_QM1_CQ_TSIZE_3 0xD621AC + +#define mmNIC2_QM1_CQ_CTL_3 0xD621B0 + +#define mmNIC2_QM1_CQ_PTR_LO_4 0xD621B4 + +#define mmNIC2_QM1_CQ_PTR_HI_4 0xD621B8 + +#define mmNIC2_QM1_CQ_TSIZE_4 0xD621BC + +#define mmNIC2_QM1_CQ_CTL_4 0xD621C0 + +#define mmNIC2_QM1_CQ_PTR_LO_STS_0 0xD621C4 + +#define mmNIC2_QM1_CQ_PTR_LO_STS_1 0xD621C8 + +#define mmNIC2_QM1_CQ_PTR_LO_STS_2 0xD621CC + +#define mmNIC2_QM1_CQ_PTR_LO_STS_3 0xD621D0 + +#define mmNIC2_QM1_CQ_PTR_LO_STS_4 0xD621D4 + +#define mmNIC2_QM1_CQ_PTR_HI_STS_0 0xD621D8 + +#define mmNIC2_QM1_CQ_PTR_HI_STS_1 0xD621DC + +#define mmNIC2_QM1_CQ_PTR_HI_STS_2 0xD621E0 + +#define mmNIC2_QM1_CQ_PTR_HI_STS_3 0xD621E4 + +#define mmNIC2_QM1_CQ_PTR_HI_STS_4 0xD621E8 + +#define mmNIC2_QM1_CQ_TSIZE_STS_0 0xD621EC + +#define mmNIC2_QM1_CQ_TSIZE_STS_1 0xD621F0 + +#define mmNIC2_QM1_CQ_TSIZE_STS_2 0xD621F4 + +#define mmNIC2_QM1_CQ_TSIZE_STS_3 0xD621F8 + +#define mmNIC2_QM1_CQ_TSIZE_STS_4 0xD621FC + +#define mmNIC2_QM1_CQ_CTL_STS_0 0xD62200 + +#define mmNIC2_QM1_CQ_CTL_STS_1 0xD62204 + +#define mmNIC2_QM1_CQ_CTL_STS_2 0xD62208 + +#define mmNIC2_QM1_CQ_CTL_STS_3 0xD6220C + +#define mmNIC2_QM1_CQ_CTL_STS_4 0xD62210 + +#define mmNIC2_QM1_CQ_IFIFO_CNT_0 0xD62214 + +#define mmNIC2_QM1_CQ_IFIFO_CNT_1 0xD62218 + +#define mmNIC2_QM1_CQ_IFIFO_CNT_2 0xD6221C + +#define mmNIC2_QM1_CQ_IFIFO_CNT_3 0xD62220 + +#define mmNIC2_QM1_CQ_IFIFO_CNT_4 0xD62224 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD62228 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD6222C + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD62230 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD62234 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD62238 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD6223C + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD62240 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD62244 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD62248 + +#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD6224C + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD62250 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD62254 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD62258 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD6225C + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD62260 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD62264 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD62268 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD6226C + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD62270 + +#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD62274 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD62278 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD6227C + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD62280 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD62284 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD62288 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD6228C + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD62290 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD62294 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD62298 + +#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD6229C + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD622A0 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD622A4 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD622A8 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD622AC + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD622B0 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD622B4 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD622B8 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD622BC + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD622C0 + +#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD622C4 + +#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD622C8 + +#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD622CC + +#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD622D0 + +#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD622D4 + +#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD622D8 + +#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD622E0 + +#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD622E4 + +#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD622E8 + +#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD622EC + +#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD622F0 + +#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD622F4 + +#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD622F8 + +#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD622FC + +#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD62300 + +#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD62304 + +#define mmNIC2_QM1_CP_FENCE0_RDATA_0 0xD62308 + +#define mmNIC2_QM1_CP_FENCE0_RDATA_1 0xD6230C + +#define mmNIC2_QM1_CP_FENCE0_RDATA_2 0xD62310 + +#define mmNIC2_QM1_CP_FENCE0_RDATA_3 0xD62314 + +#define mmNIC2_QM1_CP_FENCE0_RDATA_4 0xD62318 + +#define mmNIC2_QM1_CP_FENCE1_RDATA_0 0xD6231C + +#define mmNIC2_QM1_CP_FENCE1_RDATA_1 0xD62320 + +#define mmNIC2_QM1_CP_FENCE1_RDATA_2 0xD62324 + +#define mmNIC2_QM1_CP_FENCE1_RDATA_3 0xD62328 + +#define mmNIC2_QM1_CP_FENCE1_RDATA_4 0xD6232C + +#define mmNIC2_QM1_CP_FENCE2_RDATA_0 0xD62330 + +#define mmNIC2_QM1_CP_FENCE2_RDATA_1 0xD62334 + +#define mmNIC2_QM1_CP_FENCE2_RDATA_2 0xD62338 + +#define mmNIC2_QM1_CP_FENCE2_RDATA_3 0xD6233C + +#define mmNIC2_QM1_CP_FENCE2_RDATA_4 0xD62340 + +#define mmNIC2_QM1_CP_FENCE3_RDATA_0 0xD62344 + +#define mmNIC2_QM1_CP_FENCE3_RDATA_1 0xD62348 + +#define mmNIC2_QM1_CP_FENCE3_RDATA_2 0xD6234C + +#define mmNIC2_QM1_CP_FENCE3_RDATA_3 0xD62350 + +#define mmNIC2_QM1_CP_FENCE3_RDATA_4 0xD62354 + +#define mmNIC2_QM1_CP_FENCE0_CNT_0 0xD62358 + +#define mmNIC2_QM1_CP_FENCE0_CNT_1 0xD6235C + +#define mmNIC2_QM1_CP_FENCE0_CNT_2 0xD62360 + +#define mmNIC2_QM1_CP_FENCE0_CNT_3 0xD62364 + +#define mmNIC2_QM1_CP_FENCE0_CNT_4 0xD62368 + +#define mmNIC2_QM1_CP_FENCE1_CNT_0 0xD6236C + +#define mmNIC2_QM1_CP_FENCE1_CNT_1 0xD62370 + +#define mmNIC2_QM1_CP_FENCE1_CNT_2 0xD62374 + +#define mmNIC2_QM1_CP_FENCE1_CNT_3 0xD62378 + +#define mmNIC2_QM1_CP_FENCE1_CNT_4 0xD6237C + +#define mmNIC2_QM1_CP_FENCE2_CNT_0 0xD62380 + +#define mmNIC2_QM1_CP_FENCE2_CNT_1 0xD62384 + +#define mmNIC2_QM1_CP_FENCE2_CNT_2 0xD62388 + +#define mmNIC2_QM1_CP_FENCE2_CNT_3 0xD6238C + +#define mmNIC2_QM1_CP_FENCE2_CNT_4 0xD62390 + +#define mmNIC2_QM1_CP_FENCE3_CNT_0 0xD62394 + +#define mmNIC2_QM1_CP_FENCE3_CNT_1 0xD62398 + +#define mmNIC2_QM1_CP_FENCE3_CNT_2 0xD6239C + +#define mmNIC2_QM1_CP_FENCE3_CNT_3 0xD623A0 + +#define mmNIC2_QM1_CP_FENCE3_CNT_4 0xD623A4 + +#define mmNIC2_QM1_CP_STS_0 0xD623A8 + +#define mmNIC2_QM1_CP_STS_1 0xD623AC + +#define mmNIC2_QM1_CP_STS_2 0xD623B0 + +#define mmNIC2_QM1_CP_STS_3 0xD623B4 + +#define mmNIC2_QM1_CP_STS_4 0xD623B8 + +#define mmNIC2_QM1_CP_CURRENT_INST_LO_0 0xD623BC + +#define mmNIC2_QM1_CP_CURRENT_INST_LO_1 0xD623C0 + +#define mmNIC2_QM1_CP_CURRENT_INST_LO_2 0xD623C4 + +#define mmNIC2_QM1_CP_CURRENT_INST_LO_3 0xD623C8 + +#define mmNIC2_QM1_CP_CURRENT_INST_LO_4 0xD623CC + +#define mmNIC2_QM1_CP_CURRENT_INST_HI_0 0xD623D0 + +#define mmNIC2_QM1_CP_CURRENT_INST_HI_1 0xD623D4 + +#define mmNIC2_QM1_CP_CURRENT_INST_HI_2 0xD623D8 + +#define mmNIC2_QM1_CP_CURRENT_INST_HI_3 0xD623DC + +#define mmNIC2_QM1_CP_CURRENT_INST_HI_4 0xD623E0 + +#define mmNIC2_QM1_CP_BARRIER_CFG_0 0xD623F4 + +#define mmNIC2_QM1_CP_BARRIER_CFG_1 0xD623F8 + +#define mmNIC2_QM1_CP_BARRIER_CFG_2 0xD623FC + +#define mmNIC2_QM1_CP_BARRIER_CFG_3 0xD62400 + +#define mmNIC2_QM1_CP_BARRIER_CFG_4 0xD62404 + +#define mmNIC2_QM1_CP_DBG_0_0 0xD62408 + +#define mmNIC2_QM1_CP_DBG_0_1 0xD6240C + +#define mmNIC2_QM1_CP_DBG_0_2 0xD62410 + +#define mmNIC2_QM1_CP_DBG_0_3 0xD62414 + +#define mmNIC2_QM1_CP_DBG_0_4 0xD62418 + +#define mmNIC2_QM1_CP_ARUSER_31_11_0 0xD6241C + +#define mmNIC2_QM1_CP_ARUSER_31_11_1 0xD62420 + +#define mmNIC2_QM1_CP_ARUSER_31_11_2 0xD62424 + +#define mmNIC2_QM1_CP_ARUSER_31_11_3 0xD62428 + +#define mmNIC2_QM1_CP_ARUSER_31_11_4 0xD6242C + +#define mmNIC2_QM1_CP_AWUSER_31_11_0 0xD62430 + +#define mmNIC2_QM1_CP_AWUSER_31_11_1 0xD62434 + +#define mmNIC2_QM1_CP_AWUSER_31_11_2 0xD62438 + +#define mmNIC2_QM1_CP_AWUSER_31_11_3 0xD6243C + +#define mmNIC2_QM1_CP_AWUSER_31_11_4 0xD62440 + +#define mmNIC2_QM1_ARB_CFG_0 0xD62A00 + +#define mmNIC2_QM1_ARB_CHOISE_Q_PUSH 0xD62A04 + +#define mmNIC2_QM1_ARB_WRR_WEIGHT_0 0xD62A08 + +#define mmNIC2_QM1_ARB_WRR_WEIGHT_1 0xD62A0C + +#define mmNIC2_QM1_ARB_WRR_WEIGHT_2 0xD62A10 + +#define mmNIC2_QM1_ARB_WRR_WEIGHT_3 0xD62A14 + +#define mmNIC2_QM1_ARB_CFG_1 0xD62A18 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_0 0xD62A20 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_1 0xD62A24 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_2 0xD62A28 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_3 0xD62A2C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_4 0xD62A30 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_5 0xD62A34 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_6 0xD62A38 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_7 0xD62A3C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_8 0xD62A40 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_9 0xD62A44 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_10 0xD62A48 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_11 0xD62A4C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_12 0xD62A50 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_13 0xD62A54 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_14 0xD62A58 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_15 0xD62A5C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_16 0xD62A60 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_17 0xD62A64 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_18 0xD62A68 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_19 0xD62A6C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_20 0xD62A70 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_21 0xD62A74 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_22 0xD62A78 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_23 0xD62A7C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 0xD62A80 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_25 0xD62A84 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_26 0xD62A88 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_27 0xD62A8C + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_28 0xD62A90 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_29 0xD62A94 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_30 0xD62A98 + +#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_31 0xD62A9C + +#define mmNIC2_QM1_ARB_MST_CRED_INC 0xD62AA0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD62AA4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD62AA8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD62AAC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD62AB0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD62AB4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD62AB8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD62ABC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD62AC0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD62AC4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD62AC8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD62ACC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD62AD0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD62AD4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD62AD8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD62ADC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD62AE0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD62AE4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD62AE8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD62AEC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD62AF0 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD62AF4 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD62AF8 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD62AFC + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD62B00 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD62B04 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD62B08 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD62B0C + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD62B10 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD62B14 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD62B18 + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD62B1C + +#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD62B20 + +#define mmNIC2_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD62B28 + +#define mmNIC2_QM1_ARB_MST_SLAVE_EN 0xD62B2C + +#define mmNIC2_QM1_ARB_MST_QUIET_PER 0xD62B34 + +#define mmNIC2_QM1_ARB_SLV_CHOISE_WDT 0xD62B38 + +#define mmNIC2_QM1_ARB_SLV_ID 0xD62B3C + +#define mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT 0xD62B44 + +#define mmNIC2_QM1_ARB_MSG_AWUSER_31_11 0xD62B48 + +#define mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD62B4C + +#define mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD62B50 + +#define mmNIC2_QM1_ARB_BASE_LO 0xD62B54 + +#define mmNIC2_QM1_ARB_BASE_HI 0xD62B58 + +#define mmNIC2_QM1_ARB_STATE_STS 0xD62B80 + +#define mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS 0xD62B84 + +#define mmNIC2_QM1_ARB_MSG_STS 0xD62B88 + +#define mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD62B8C + +#define mmNIC2_QM1_ARB_ERR_CAUSE 0xD62B9C + +#define mmNIC2_QM1_ARB_ERR_MSG_EN 0xD62BA0 + +#define mmNIC2_QM1_ARB_ERR_STS_DRP 0xD62BA8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_0 0xD62BB0 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_1 0xD62BB4 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_2 0xD62BB8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_3 0xD62BBC + +#define mmNIC2_QM1_ARB_MST_CRED_STS_4 0xD62BC0 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_5 0xD62BC4 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_6 0xD62BC8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_7 0xD62BCC + +#define mmNIC2_QM1_ARB_MST_CRED_STS_8 0xD62BD0 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_9 0xD62BD4 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_10 0xD62BD8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_11 0xD62BDC + +#define mmNIC2_QM1_ARB_MST_CRED_STS_12 0xD62BE0 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_13 0xD62BE4 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_14 0xD62BE8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_15 0xD62BEC + +#define mmNIC2_QM1_ARB_MST_CRED_STS_16 0xD62BF0 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_17 0xD62BF4 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_18 0xD62BF8 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_19 0xD62BFC + +#define mmNIC2_QM1_ARB_MST_CRED_STS_20 0xD62C00 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_21 0xD62C04 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_22 0xD62C08 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_23 0xD62C0C + +#define mmNIC2_QM1_ARB_MST_CRED_STS_24 0xD62C10 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_25 0xD62C14 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_26 0xD62C18 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_27 0xD62C1C + +#define mmNIC2_QM1_ARB_MST_CRED_STS_28 0xD62C20 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_29 0xD62C24 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_30 0xD62C28 + +#define mmNIC2_QM1_ARB_MST_CRED_STS_31 0xD62C2C + +#define mmNIC2_QM1_CGM_CFG 0xD62C70 + +#define mmNIC2_QM1_CGM_STS 0xD62C74 + +#define mmNIC2_QM1_CGM_CFG1 0xD62C78 + +#define mmNIC2_QM1_LOCAL_RANGE_BASE 0xD62C80 + +#define mmNIC2_QM1_LOCAL_RANGE_SIZE 0xD62C84 + +#define mmNIC2_QM1_CSMR_STRICT_PRIO_CFG 0xD62C90 + +#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1 0xD62C94 + +#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0 0xD62C98 + +#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1 0xD62C9C + +#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0 0xD62CA0 + +#define mmNIC2_QM1_GLBL_AXCACHE 0xD62CA4 + +#define mmNIC2_QM1_IND_GW_APB_CFG 0xD62CB0 + +#define mmNIC2_QM1_IND_GW_APB_WDATA 0xD62CB4 + +#define mmNIC2_QM1_IND_GW_APB_RDATA 0xD62CB8 + +#define mmNIC2_QM1_IND_GW_APB_STATUS 0xD62CBC + +#define mmNIC2_QM1_GLBL_ERR_ADDR_LO 0xD62CD0 + +#define mmNIC2_QM1_GLBL_ERR_ADDR_HI 0xD62CD4 + +#define mmNIC2_QM1_GLBL_ERR_WDATA 0xD62CD8 + +#define mmNIC2_QM1_GLBL_MEM_INIT_BUSY 0xD62D00 + +#endif /* ASIC_REG_NIC2_QM1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h new file mode 100644 index 000000000..4712cc62b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC3_QM0_REGS_H_ +#define ASIC_REG_NIC3_QM0_REGS_H_ + +/* + ***************************************** + * NIC3_QM0 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC3_QM0_GLBL_CFG0 0xDA0000 + +#define mmNIC3_QM0_GLBL_CFG1 0xDA0004 + +#define mmNIC3_QM0_GLBL_PROT 0xDA0008 + +#define mmNIC3_QM0_GLBL_ERR_CFG 0xDA000C + +#define mmNIC3_QM0_GLBL_SECURE_PROPS_0 0xDA0010 + +#define mmNIC3_QM0_GLBL_SECURE_PROPS_1 0xDA0014 + +#define mmNIC3_QM0_GLBL_SECURE_PROPS_2 0xDA0018 + +#define mmNIC3_QM0_GLBL_SECURE_PROPS_3 0xDA001C + +#define mmNIC3_QM0_GLBL_SECURE_PROPS_4 0xDA0020 + +#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0 0xDA0024 + +#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1 0xDA0028 + +#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2 0xDA002C + +#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3 0xDA0030 + +#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4 0xDA0034 + +#define mmNIC3_QM0_GLBL_STS0 0xDA0038 + +#define mmNIC3_QM0_GLBL_STS1_0 0xDA0040 + +#define mmNIC3_QM0_GLBL_STS1_1 0xDA0044 + +#define mmNIC3_QM0_GLBL_STS1_2 0xDA0048 + +#define mmNIC3_QM0_GLBL_STS1_3 0xDA004C + +#define mmNIC3_QM0_GLBL_STS1_4 0xDA0050 + +#define mmNIC3_QM0_GLBL_MSG_EN_0 0xDA0054 + +#define mmNIC3_QM0_GLBL_MSG_EN_1 0xDA0058 + +#define mmNIC3_QM0_GLBL_MSG_EN_2 0xDA005C + +#define mmNIC3_QM0_GLBL_MSG_EN_3 0xDA0060 + +#define mmNIC3_QM0_GLBL_MSG_EN_4 0xDA0068 + +#define mmNIC3_QM0_PQ_BASE_LO_0 0xDA0070 + +#define mmNIC3_QM0_PQ_BASE_LO_1 0xDA0074 + +#define mmNIC3_QM0_PQ_BASE_LO_2 0xDA0078 + +#define mmNIC3_QM0_PQ_BASE_LO_3 0xDA007C + +#define mmNIC3_QM0_PQ_BASE_HI_0 0xDA0080 + +#define mmNIC3_QM0_PQ_BASE_HI_1 0xDA0084 + +#define mmNIC3_QM0_PQ_BASE_HI_2 0xDA0088 + +#define mmNIC3_QM0_PQ_BASE_HI_3 0xDA008C + +#define mmNIC3_QM0_PQ_SIZE_0 0xDA0090 + +#define mmNIC3_QM0_PQ_SIZE_1 0xDA0094 + +#define mmNIC3_QM0_PQ_SIZE_2 0xDA0098 + +#define mmNIC3_QM0_PQ_SIZE_3 0xDA009C + +#define mmNIC3_QM0_PQ_PI_0 0xDA00A0 + +#define mmNIC3_QM0_PQ_PI_1 0xDA00A4 + +#define mmNIC3_QM0_PQ_PI_2 0xDA00A8 + +#define mmNIC3_QM0_PQ_PI_3 0xDA00AC + +#define mmNIC3_QM0_PQ_CI_0 0xDA00B0 + +#define mmNIC3_QM0_PQ_CI_1 0xDA00B4 + +#define mmNIC3_QM0_PQ_CI_2 0xDA00B8 + +#define mmNIC3_QM0_PQ_CI_3 0xDA00BC + +#define mmNIC3_QM0_PQ_CFG0_0 0xDA00C0 + +#define mmNIC3_QM0_PQ_CFG0_1 0xDA00C4 + +#define mmNIC3_QM0_PQ_CFG0_2 0xDA00C8 + +#define mmNIC3_QM0_PQ_CFG0_3 0xDA00CC + +#define mmNIC3_QM0_PQ_CFG1_0 0xDA00D0 + +#define mmNIC3_QM0_PQ_CFG1_1 0xDA00D4 + +#define mmNIC3_QM0_PQ_CFG1_2 0xDA00D8 + +#define mmNIC3_QM0_PQ_CFG1_3 0xDA00DC + +#define mmNIC3_QM0_PQ_ARUSER_31_11_0 0xDA00E0 + +#define mmNIC3_QM0_PQ_ARUSER_31_11_1 0xDA00E4 + +#define mmNIC3_QM0_PQ_ARUSER_31_11_2 0xDA00E8 + +#define mmNIC3_QM0_PQ_ARUSER_31_11_3 0xDA00EC + +#define mmNIC3_QM0_PQ_STS0_0 0xDA00F0 + +#define mmNIC3_QM0_PQ_STS0_1 0xDA00F4 + +#define mmNIC3_QM0_PQ_STS0_2 0xDA00F8 + +#define mmNIC3_QM0_PQ_STS0_3 0xDA00FC + +#define mmNIC3_QM0_PQ_STS1_0 0xDA0100 + +#define mmNIC3_QM0_PQ_STS1_1 0xDA0104 + +#define mmNIC3_QM0_PQ_STS1_2 0xDA0108 + +#define mmNIC3_QM0_PQ_STS1_3 0xDA010C + +#define mmNIC3_QM0_CQ_CFG0_0 0xDA0110 + +#define mmNIC3_QM0_CQ_CFG0_1 0xDA0114 + +#define mmNIC3_QM0_CQ_CFG0_2 0xDA0118 + +#define mmNIC3_QM0_CQ_CFG0_3 0xDA011C + +#define mmNIC3_QM0_CQ_CFG0_4 0xDA0120 + +#define mmNIC3_QM0_CQ_CFG1_0 0xDA0124 + +#define mmNIC3_QM0_CQ_CFG1_1 0xDA0128 + +#define mmNIC3_QM0_CQ_CFG1_2 0xDA012C + +#define mmNIC3_QM0_CQ_CFG1_3 0xDA0130 + +#define mmNIC3_QM0_CQ_CFG1_4 0xDA0134 + +#define mmNIC3_QM0_CQ_ARUSER_31_11_0 0xDA0138 + +#define mmNIC3_QM0_CQ_ARUSER_31_11_1 0xDA013C + +#define mmNIC3_QM0_CQ_ARUSER_31_11_2 0xDA0140 + +#define mmNIC3_QM0_CQ_ARUSER_31_11_3 0xDA0144 + +#define mmNIC3_QM0_CQ_ARUSER_31_11_4 0xDA0148 + +#define mmNIC3_QM0_CQ_STS0_0 0xDA014C + +#define mmNIC3_QM0_CQ_STS0_1 0xDA0150 + +#define mmNIC3_QM0_CQ_STS0_2 0xDA0154 + +#define mmNIC3_QM0_CQ_STS0_3 0xDA0158 + +#define mmNIC3_QM0_CQ_STS0_4 0xDA015C + +#define mmNIC3_QM0_CQ_STS1_0 0xDA0160 + +#define mmNIC3_QM0_CQ_STS1_1 0xDA0164 + +#define mmNIC3_QM0_CQ_STS1_2 0xDA0168 + +#define mmNIC3_QM0_CQ_STS1_3 0xDA016C + +#define mmNIC3_QM0_CQ_STS1_4 0xDA0170 + +#define mmNIC3_QM0_CQ_PTR_LO_0 0xDA0174 + +#define mmNIC3_QM0_CQ_PTR_HI_0 0xDA0178 + +#define mmNIC3_QM0_CQ_TSIZE_0 0xDA017C + +#define mmNIC3_QM0_CQ_CTL_0 0xDA0180 + +#define mmNIC3_QM0_CQ_PTR_LO_1 0xDA0184 + +#define mmNIC3_QM0_CQ_PTR_HI_1 0xDA0188 + +#define mmNIC3_QM0_CQ_TSIZE_1 0xDA018C + +#define mmNIC3_QM0_CQ_CTL_1 0xDA0190 + +#define mmNIC3_QM0_CQ_PTR_LO_2 0xDA0194 + +#define mmNIC3_QM0_CQ_PTR_HI_2 0xDA0198 + +#define mmNIC3_QM0_CQ_TSIZE_2 0xDA019C + +#define mmNIC3_QM0_CQ_CTL_2 0xDA01A0 + +#define mmNIC3_QM0_CQ_PTR_LO_3 0xDA01A4 + +#define mmNIC3_QM0_CQ_PTR_HI_3 0xDA01A8 + +#define mmNIC3_QM0_CQ_TSIZE_3 0xDA01AC + +#define mmNIC3_QM0_CQ_CTL_3 0xDA01B0 + +#define mmNIC3_QM0_CQ_PTR_LO_4 0xDA01B4 + +#define mmNIC3_QM0_CQ_PTR_HI_4 0xDA01B8 + +#define mmNIC3_QM0_CQ_TSIZE_4 0xDA01BC + +#define mmNIC3_QM0_CQ_CTL_4 0xDA01C0 + +#define mmNIC3_QM0_CQ_PTR_LO_STS_0 0xDA01C4 + +#define mmNIC3_QM0_CQ_PTR_LO_STS_1 0xDA01C8 + +#define mmNIC3_QM0_CQ_PTR_LO_STS_2 0xDA01CC + +#define mmNIC3_QM0_CQ_PTR_LO_STS_3 0xDA01D0 + +#define mmNIC3_QM0_CQ_PTR_LO_STS_4 0xDA01D4 + +#define mmNIC3_QM0_CQ_PTR_HI_STS_0 0xDA01D8 + +#define mmNIC3_QM0_CQ_PTR_HI_STS_1 0xDA01DC + +#define mmNIC3_QM0_CQ_PTR_HI_STS_2 0xDA01E0 + +#define mmNIC3_QM0_CQ_PTR_HI_STS_3 0xDA01E4 + +#define mmNIC3_QM0_CQ_PTR_HI_STS_4 0xDA01E8 + +#define mmNIC3_QM0_CQ_TSIZE_STS_0 0xDA01EC + +#define mmNIC3_QM0_CQ_TSIZE_STS_1 0xDA01F0 + +#define mmNIC3_QM0_CQ_TSIZE_STS_2 0xDA01F4 + +#define mmNIC3_QM0_CQ_TSIZE_STS_3 0xDA01F8 + +#define mmNIC3_QM0_CQ_TSIZE_STS_4 0xDA01FC + +#define mmNIC3_QM0_CQ_CTL_STS_0 0xDA0200 + +#define mmNIC3_QM0_CQ_CTL_STS_1 0xDA0204 + +#define mmNIC3_QM0_CQ_CTL_STS_2 0xDA0208 + +#define mmNIC3_QM0_CQ_CTL_STS_3 0xDA020C + +#define mmNIC3_QM0_CQ_CTL_STS_4 0xDA0210 + +#define mmNIC3_QM0_CQ_IFIFO_CNT_0 0xDA0214 + +#define mmNIC3_QM0_CQ_IFIFO_CNT_1 0xDA0218 + +#define mmNIC3_QM0_CQ_IFIFO_CNT_2 0xDA021C + +#define mmNIC3_QM0_CQ_IFIFO_CNT_3 0xDA0220 + +#define mmNIC3_QM0_CQ_IFIFO_CNT_4 0xDA0224 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDA0228 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDA022C + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDA0230 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDA0234 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDA0238 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDA023C + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDA0240 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDA0244 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDA0248 + +#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDA024C + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDA0250 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDA0254 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDA0258 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDA025C + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDA0260 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDA0264 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDA0268 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDA026C + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDA0270 + +#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDA0274 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDA0278 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDA027C + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDA0280 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDA0284 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDA0288 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDA028C + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDA0290 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDA0294 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDA0298 + +#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDA029C + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDA02A0 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDA02A4 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDA02A8 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDA02AC + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDA02B0 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDA02B4 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDA02B8 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDA02BC + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDA02C0 + +#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDA02C4 + +#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDA02C8 + +#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDA02CC + +#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDA02D0 + +#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDA02D4 + +#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDA02D8 + +#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA02E0 + +#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA02E4 + +#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA02E8 + +#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA02EC + +#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA02F0 + +#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA02F4 + +#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA02F8 + +#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA02FC + +#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA0300 + +#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA0304 + +#define mmNIC3_QM0_CP_FENCE0_RDATA_0 0xDA0308 + +#define mmNIC3_QM0_CP_FENCE0_RDATA_1 0xDA030C + +#define mmNIC3_QM0_CP_FENCE0_RDATA_2 0xDA0310 + +#define mmNIC3_QM0_CP_FENCE0_RDATA_3 0xDA0314 + +#define mmNIC3_QM0_CP_FENCE0_RDATA_4 0xDA0318 + +#define mmNIC3_QM0_CP_FENCE1_RDATA_0 0xDA031C + +#define mmNIC3_QM0_CP_FENCE1_RDATA_1 0xDA0320 + +#define mmNIC3_QM0_CP_FENCE1_RDATA_2 0xDA0324 + +#define mmNIC3_QM0_CP_FENCE1_RDATA_3 0xDA0328 + +#define mmNIC3_QM0_CP_FENCE1_RDATA_4 0xDA032C + +#define mmNIC3_QM0_CP_FENCE2_RDATA_0 0xDA0330 + +#define mmNIC3_QM0_CP_FENCE2_RDATA_1 0xDA0334 + +#define mmNIC3_QM0_CP_FENCE2_RDATA_2 0xDA0338 + +#define mmNIC3_QM0_CP_FENCE2_RDATA_3 0xDA033C + +#define mmNIC3_QM0_CP_FENCE2_RDATA_4 0xDA0340 + +#define mmNIC3_QM0_CP_FENCE3_RDATA_0 0xDA0344 + +#define mmNIC3_QM0_CP_FENCE3_RDATA_1 0xDA0348 + +#define mmNIC3_QM0_CP_FENCE3_RDATA_2 0xDA034C + +#define mmNIC3_QM0_CP_FENCE3_RDATA_3 0xDA0350 + +#define mmNIC3_QM0_CP_FENCE3_RDATA_4 0xDA0354 + +#define mmNIC3_QM0_CP_FENCE0_CNT_0 0xDA0358 + +#define mmNIC3_QM0_CP_FENCE0_CNT_1 0xDA035C + +#define mmNIC3_QM0_CP_FENCE0_CNT_2 0xDA0360 + +#define mmNIC3_QM0_CP_FENCE0_CNT_3 0xDA0364 + +#define mmNIC3_QM0_CP_FENCE0_CNT_4 0xDA0368 + +#define mmNIC3_QM0_CP_FENCE1_CNT_0 0xDA036C + +#define mmNIC3_QM0_CP_FENCE1_CNT_1 0xDA0370 + +#define mmNIC3_QM0_CP_FENCE1_CNT_2 0xDA0374 + +#define mmNIC3_QM0_CP_FENCE1_CNT_3 0xDA0378 + +#define mmNIC3_QM0_CP_FENCE1_CNT_4 0xDA037C + +#define mmNIC3_QM0_CP_FENCE2_CNT_0 0xDA0380 + +#define mmNIC3_QM0_CP_FENCE2_CNT_1 0xDA0384 + +#define mmNIC3_QM0_CP_FENCE2_CNT_2 0xDA0388 + +#define mmNIC3_QM0_CP_FENCE2_CNT_3 0xDA038C + +#define mmNIC3_QM0_CP_FENCE2_CNT_4 0xDA0390 + +#define mmNIC3_QM0_CP_FENCE3_CNT_0 0xDA0394 + +#define mmNIC3_QM0_CP_FENCE3_CNT_1 0xDA0398 + +#define mmNIC3_QM0_CP_FENCE3_CNT_2 0xDA039C + +#define mmNIC3_QM0_CP_FENCE3_CNT_3 0xDA03A0 + +#define mmNIC3_QM0_CP_FENCE3_CNT_4 0xDA03A4 + +#define mmNIC3_QM0_CP_STS_0 0xDA03A8 + +#define mmNIC3_QM0_CP_STS_1 0xDA03AC + +#define mmNIC3_QM0_CP_STS_2 0xDA03B0 + +#define mmNIC3_QM0_CP_STS_3 0xDA03B4 + +#define mmNIC3_QM0_CP_STS_4 0xDA03B8 + +#define mmNIC3_QM0_CP_CURRENT_INST_LO_0 0xDA03BC + +#define mmNIC3_QM0_CP_CURRENT_INST_LO_1 0xDA03C0 + +#define mmNIC3_QM0_CP_CURRENT_INST_LO_2 0xDA03C4 + +#define mmNIC3_QM0_CP_CURRENT_INST_LO_3 0xDA03C8 + +#define mmNIC3_QM0_CP_CURRENT_INST_LO_4 0xDA03CC + +#define mmNIC3_QM0_CP_CURRENT_INST_HI_0 0xDA03D0 + +#define mmNIC3_QM0_CP_CURRENT_INST_HI_1 0xDA03D4 + +#define mmNIC3_QM0_CP_CURRENT_INST_HI_2 0xDA03D8 + +#define mmNIC3_QM0_CP_CURRENT_INST_HI_3 0xDA03DC + +#define mmNIC3_QM0_CP_CURRENT_INST_HI_4 0xDA03E0 + +#define mmNIC3_QM0_CP_BARRIER_CFG_0 0xDA03F4 + +#define mmNIC3_QM0_CP_BARRIER_CFG_1 0xDA03F8 + +#define mmNIC3_QM0_CP_BARRIER_CFG_2 0xDA03FC + +#define mmNIC3_QM0_CP_BARRIER_CFG_3 0xDA0400 + +#define mmNIC3_QM0_CP_BARRIER_CFG_4 0xDA0404 + +#define mmNIC3_QM0_CP_DBG_0_0 0xDA0408 + +#define mmNIC3_QM0_CP_DBG_0_1 0xDA040C + +#define mmNIC3_QM0_CP_DBG_0_2 0xDA0410 + +#define mmNIC3_QM0_CP_DBG_0_3 0xDA0414 + +#define mmNIC3_QM0_CP_DBG_0_4 0xDA0418 + +#define mmNIC3_QM0_CP_ARUSER_31_11_0 0xDA041C + +#define mmNIC3_QM0_CP_ARUSER_31_11_1 0xDA0420 + +#define mmNIC3_QM0_CP_ARUSER_31_11_2 0xDA0424 + +#define mmNIC3_QM0_CP_ARUSER_31_11_3 0xDA0428 + +#define mmNIC3_QM0_CP_ARUSER_31_11_4 0xDA042C + +#define mmNIC3_QM0_CP_AWUSER_31_11_0 0xDA0430 + +#define mmNIC3_QM0_CP_AWUSER_31_11_1 0xDA0434 + +#define mmNIC3_QM0_CP_AWUSER_31_11_2 0xDA0438 + +#define mmNIC3_QM0_CP_AWUSER_31_11_3 0xDA043C + +#define mmNIC3_QM0_CP_AWUSER_31_11_4 0xDA0440 + +#define mmNIC3_QM0_ARB_CFG_0 0xDA0A00 + +#define mmNIC3_QM0_ARB_CHOISE_Q_PUSH 0xDA0A04 + +#define mmNIC3_QM0_ARB_WRR_WEIGHT_0 0xDA0A08 + +#define mmNIC3_QM0_ARB_WRR_WEIGHT_1 0xDA0A0C + +#define mmNIC3_QM0_ARB_WRR_WEIGHT_2 0xDA0A10 + +#define mmNIC3_QM0_ARB_WRR_WEIGHT_3 0xDA0A14 + +#define mmNIC3_QM0_ARB_CFG_1 0xDA0A18 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_0 0xDA0A20 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_1 0xDA0A24 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_2 0xDA0A28 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_3 0xDA0A2C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_4 0xDA0A30 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_5 0xDA0A34 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_6 0xDA0A38 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_7 0xDA0A3C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_8 0xDA0A40 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_9 0xDA0A44 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_10 0xDA0A48 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_11 0xDA0A4C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_12 0xDA0A50 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_13 0xDA0A54 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_14 0xDA0A58 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_15 0xDA0A5C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_16 0xDA0A60 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_17 0xDA0A64 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_18 0xDA0A68 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_19 0xDA0A6C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_20 0xDA0A70 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_21 0xDA0A74 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_22 0xDA0A78 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_23 0xDA0A7C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 0xDA0A80 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_25 0xDA0A84 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_26 0xDA0A88 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_27 0xDA0A8C + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_28 0xDA0A90 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_29 0xDA0A94 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_30 0xDA0A98 + +#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_31 0xDA0A9C + +#define mmNIC3_QM0_ARB_MST_CRED_INC 0xDA0AA0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDA0AA4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDA0AA8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDA0AAC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDA0AB0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDA0AB4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDA0AB8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDA0ABC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDA0AC0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDA0AC4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDA0AC8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDA0ACC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDA0AD0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDA0AD4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDA0AD8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDA0ADC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDA0AE0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDA0AE4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDA0AE8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDA0AEC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDA0AF0 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDA0AF4 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDA0AF8 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDA0AFC + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDA0B00 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDA0B04 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDA0B08 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDA0B0C + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDA0B10 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDA0B14 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDA0B18 + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDA0B1C + +#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDA0B20 + +#define mmNIC3_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDA0B28 + +#define mmNIC3_QM0_ARB_MST_SLAVE_EN 0xDA0B2C + +#define mmNIC3_QM0_ARB_MST_QUIET_PER 0xDA0B34 + +#define mmNIC3_QM0_ARB_SLV_CHOISE_WDT 0xDA0B38 + +#define mmNIC3_QM0_ARB_SLV_ID 0xDA0B3C + +#define mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT 0xDA0B44 + +#define mmNIC3_QM0_ARB_MSG_AWUSER_31_11 0xDA0B48 + +#define mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDA0B4C + +#define mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA0B50 + +#define mmNIC3_QM0_ARB_BASE_LO 0xDA0B54 + +#define mmNIC3_QM0_ARB_BASE_HI 0xDA0B58 + +#define mmNIC3_QM0_ARB_STATE_STS 0xDA0B80 + +#define mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS 0xDA0B84 + +#define mmNIC3_QM0_ARB_MSG_STS 0xDA0B88 + +#define mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDA0B8C + +#define mmNIC3_QM0_ARB_ERR_CAUSE 0xDA0B9C + +#define mmNIC3_QM0_ARB_ERR_MSG_EN 0xDA0BA0 + +#define mmNIC3_QM0_ARB_ERR_STS_DRP 0xDA0BA8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_0 0xDA0BB0 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_1 0xDA0BB4 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_2 0xDA0BB8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_3 0xDA0BBC + +#define mmNIC3_QM0_ARB_MST_CRED_STS_4 0xDA0BC0 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_5 0xDA0BC4 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_6 0xDA0BC8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_7 0xDA0BCC + +#define mmNIC3_QM0_ARB_MST_CRED_STS_8 0xDA0BD0 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_9 0xDA0BD4 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_10 0xDA0BD8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_11 0xDA0BDC + +#define mmNIC3_QM0_ARB_MST_CRED_STS_12 0xDA0BE0 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_13 0xDA0BE4 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_14 0xDA0BE8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_15 0xDA0BEC + +#define mmNIC3_QM0_ARB_MST_CRED_STS_16 0xDA0BF0 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_17 0xDA0BF4 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_18 0xDA0BF8 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_19 0xDA0BFC + +#define mmNIC3_QM0_ARB_MST_CRED_STS_20 0xDA0C00 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_21 0xDA0C04 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_22 0xDA0C08 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_23 0xDA0C0C + +#define mmNIC3_QM0_ARB_MST_CRED_STS_24 0xDA0C10 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_25 0xDA0C14 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_26 0xDA0C18 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_27 0xDA0C1C + +#define mmNIC3_QM0_ARB_MST_CRED_STS_28 0xDA0C20 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_29 0xDA0C24 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_30 0xDA0C28 + +#define mmNIC3_QM0_ARB_MST_CRED_STS_31 0xDA0C2C + +#define mmNIC3_QM0_CGM_CFG 0xDA0C70 + +#define mmNIC3_QM0_CGM_STS 0xDA0C74 + +#define mmNIC3_QM0_CGM_CFG1 0xDA0C78 + +#define mmNIC3_QM0_LOCAL_RANGE_BASE 0xDA0C80 + +#define mmNIC3_QM0_LOCAL_RANGE_SIZE 0xDA0C84 + +#define mmNIC3_QM0_CSMR_STRICT_PRIO_CFG 0xDA0C90 + +#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1 0xDA0C94 + +#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0 0xDA0C98 + +#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1 0xDA0C9C + +#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0 0xDA0CA0 + +#define mmNIC3_QM0_GLBL_AXCACHE 0xDA0CA4 + +#define mmNIC3_QM0_IND_GW_APB_CFG 0xDA0CB0 + +#define mmNIC3_QM0_IND_GW_APB_WDATA 0xDA0CB4 + +#define mmNIC3_QM0_IND_GW_APB_RDATA 0xDA0CB8 + +#define mmNIC3_QM0_IND_GW_APB_STATUS 0xDA0CBC + +#define mmNIC3_QM0_GLBL_ERR_ADDR_LO 0xDA0CD0 + +#define mmNIC3_QM0_GLBL_ERR_ADDR_HI 0xDA0CD4 + +#define mmNIC3_QM0_GLBL_ERR_WDATA 0xDA0CD8 + +#define mmNIC3_QM0_GLBL_MEM_INIT_BUSY 0xDA0D00 + +#endif /* ASIC_REG_NIC3_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h new file mode 100644 index 000000000..7fa040f65 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC3_QM1_REGS_H_ +#define ASIC_REG_NIC3_QM1_REGS_H_ + +/* + ***************************************** + * NIC3_QM1 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC3_QM1_GLBL_CFG0 0xDA2000 + +#define mmNIC3_QM1_GLBL_CFG1 0xDA2004 + +#define mmNIC3_QM1_GLBL_PROT 0xDA2008 + +#define mmNIC3_QM1_GLBL_ERR_CFG 0xDA200C + +#define mmNIC3_QM1_GLBL_SECURE_PROPS_0 0xDA2010 + +#define mmNIC3_QM1_GLBL_SECURE_PROPS_1 0xDA2014 + +#define mmNIC3_QM1_GLBL_SECURE_PROPS_2 0xDA2018 + +#define mmNIC3_QM1_GLBL_SECURE_PROPS_3 0xDA201C + +#define mmNIC3_QM1_GLBL_SECURE_PROPS_4 0xDA2020 + +#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 0xDA2024 + +#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 0xDA2028 + +#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 0xDA202C + +#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 0xDA2030 + +#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 0xDA2034 + +#define mmNIC3_QM1_GLBL_STS0 0xDA2038 + +#define mmNIC3_QM1_GLBL_STS1_0 0xDA2040 + +#define mmNIC3_QM1_GLBL_STS1_1 0xDA2044 + +#define mmNIC3_QM1_GLBL_STS1_2 0xDA2048 + +#define mmNIC3_QM1_GLBL_STS1_3 0xDA204C + +#define mmNIC3_QM1_GLBL_STS1_4 0xDA2050 + +#define mmNIC3_QM1_GLBL_MSG_EN_0 0xDA2054 + +#define mmNIC3_QM1_GLBL_MSG_EN_1 0xDA2058 + +#define mmNIC3_QM1_GLBL_MSG_EN_2 0xDA205C + +#define mmNIC3_QM1_GLBL_MSG_EN_3 0xDA2060 + +#define mmNIC3_QM1_GLBL_MSG_EN_4 0xDA2068 + +#define mmNIC3_QM1_PQ_BASE_LO_0 0xDA2070 + +#define mmNIC3_QM1_PQ_BASE_LO_1 0xDA2074 + +#define mmNIC3_QM1_PQ_BASE_LO_2 0xDA2078 + +#define mmNIC3_QM1_PQ_BASE_LO_3 0xDA207C + +#define mmNIC3_QM1_PQ_BASE_HI_0 0xDA2080 + +#define mmNIC3_QM1_PQ_BASE_HI_1 0xDA2084 + +#define mmNIC3_QM1_PQ_BASE_HI_2 0xDA2088 + +#define mmNIC3_QM1_PQ_BASE_HI_3 0xDA208C + +#define mmNIC3_QM1_PQ_SIZE_0 0xDA2090 + +#define mmNIC3_QM1_PQ_SIZE_1 0xDA2094 + +#define mmNIC3_QM1_PQ_SIZE_2 0xDA2098 + +#define mmNIC3_QM1_PQ_SIZE_3 0xDA209C + +#define mmNIC3_QM1_PQ_PI_0 0xDA20A0 + +#define mmNIC3_QM1_PQ_PI_1 0xDA20A4 + +#define mmNIC3_QM1_PQ_PI_2 0xDA20A8 + +#define mmNIC3_QM1_PQ_PI_3 0xDA20AC + +#define mmNIC3_QM1_PQ_CI_0 0xDA20B0 + +#define mmNIC3_QM1_PQ_CI_1 0xDA20B4 + +#define mmNIC3_QM1_PQ_CI_2 0xDA20B8 + +#define mmNIC3_QM1_PQ_CI_3 0xDA20BC + +#define mmNIC3_QM1_PQ_CFG0_0 0xDA20C0 + +#define mmNIC3_QM1_PQ_CFG0_1 0xDA20C4 + +#define mmNIC3_QM1_PQ_CFG0_2 0xDA20C8 + +#define mmNIC3_QM1_PQ_CFG0_3 0xDA20CC + +#define mmNIC3_QM1_PQ_CFG1_0 0xDA20D0 + +#define mmNIC3_QM1_PQ_CFG1_1 0xDA20D4 + +#define mmNIC3_QM1_PQ_CFG1_2 0xDA20D8 + +#define mmNIC3_QM1_PQ_CFG1_3 0xDA20DC + +#define mmNIC3_QM1_PQ_ARUSER_31_11_0 0xDA20E0 + +#define mmNIC3_QM1_PQ_ARUSER_31_11_1 0xDA20E4 + +#define mmNIC3_QM1_PQ_ARUSER_31_11_2 0xDA20E8 + +#define mmNIC3_QM1_PQ_ARUSER_31_11_3 0xDA20EC + +#define mmNIC3_QM1_PQ_STS0_0 0xDA20F0 + +#define mmNIC3_QM1_PQ_STS0_1 0xDA20F4 + +#define mmNIC3_QM1_PQ_STS0_2 0xDA20F8 + +#define mmNIC3_QM1_PQ_STS0_3 0xDA20FC + +#define mmNIC3_QM1_PQ_STS1_0 0xDA2100 + +#define mmNIC3_QM1_PQ_STS1_1 0xDA2104 + +#define mmNIC3_QM1_PQ_STS1_2 0xDA2108 + +#define mmNIC3_QM1_PQ_STS1_3 0xDA210C + +#define mmNIC3_QM1_CQ_CFG0_0 0xDA2110 + +#define mmNIC3_QM1_CQ_CFG0_1 0xDA2114 + +#define mmNIC3_QM1_CQ_CFG0_2 0xDA2118 + +#define mmNIC3_QM1_CQ_CFG0_3 0xDA211C + +#define mmNIC3_QM1_CQ_CFG0_4 0xDA2120 + +#define mmNIC3_QM1_CQ_CFG1_0 0xDA2124 + +#define mmNIC3_QM1_CQ_CFG1_1 0xDA2128 + +#define mmNIC3_QM1_CQ_CFG1_2 0xDA212C + +#define mmNIC3_QM1_CQ_CFG1_3 0xDA2130 + +#define mmNIC3_QM1_CQ_CFG1_4 0xDA2134 + +#define mmNIC3_QM1_CQ_ARUSER_31_11_0 0xDA2138 + +#define mmNIC3_QM1_CQ_ARUSER_31_11_1 0xDA213C + +#define mmNIC3_QM1_CQ_ARUSER_31_11_2 0xDA2140 + +#define mmNIC3_QM1_CQ_ARUSER_31_11_3 0xDA2144 + +#define mmNIC3_QM1_CQ_ARUSER_31_11_4 0xDA2148 + +#define mmNIC3_QM1_CQ_STS0_0 0xDA214C + +#define mmNIC3_QM1_CQ_STS0_1 0xDA2150 + +#define mmNIC3_QM1_CQ_STS0_2 0xDA2154 + +#define mmNIC3_QM1_CQ_STS0_3 0xDA2158 + +#define mmNIC3_QM1_CQ_STS0_4 0xDA215C + +#define mmNIC3_QM1_CQ_STS1_0 0xDA2160 + +#define mmNIC3_QM1_CQ_STS1_1 0xDA2164 + +#define mmNIC3_QM1_CQ_STS1_2 0xDA2168 + +#define mmNIC3_QM1_CQ_STS1_3 0xDA216C + +#define mmNIC3_QM1_CQ_STS1_4 0xDA2170 + +#define mmNIC3_QM1_CQ_PTR_LO_0 0xDA2174 + +#define mmNIC3_QM1_CQ_PTR_HI_0 0xDA2178 + +#define mmNIC3_QM1_CQ_TSIZE_0 0xDA217C + +#define mmNIC3_QM1_CQ_CTL_0 0xDA2180 + +#define mmNIC3_QM1_CQ_PTR_LO_1 0xDA2184 + +#define mmNIC3_QM1_CQ_PTR_HI_1 0xDA2188 + +#define mmNIC3_QM1_CQ_TSIZE_1 0xDA218C + +#define mmNIC3_QM1_CQ_CTL_1 0xDA2190 + +#define mmNIC3_QM1_CQ_PTR_LO_2 0xDA2194 + +#define mmNIC3_QM1_CQ_PTR_HI_2 0xDA2198 + +#define mmNIC3_QM1_CQ_TSIZE_2 0xDA219C + +#define mmNIC3_QM1_CQ_CTL_2 0xDA21A0 + +#define mmNIC3_QM1_CQ_PTR_LO_3 0xDA21A4 + +#define mmNIC3_QM1_CQ_PTR_HI_3 0xDA21A8 + +#define mmNIC3_QM1_CQ_TSIZE_3 0xDA21AC + +#define mmNIC3_QM1_CQ_CTL_3 0xDA21B0 + +#define mmNIC3_QM1_CQ_PTR_LO_4 0xDA21B4 + +#define mmNIC3_QM1_CQ_PTR_HI_4 0xDA21B8 + +#define mmNIC3_QM1_CQ_TSIZE_4 0xDA21BC + +#define mmNIC3_QM1_CQ_CTL_4 0xDA21C0 + +#define mmNIC3_QM1_CQ_PTR_LO_STS_0 0xDA21C4 + +#define mmNIC3_QM1_CQ_PTR_LO_STS_1 0xDA21C8 + +#define mmNIC3_QM1_CQ_PTR_LO_STS_2 0xDA21CC + +#define mmNIC3_QM1_CQ_PTR_LO_STS_3 0xDA21D0 + +#define mmNIC3_QM1_CQ_PTR_LO_STS_4 0xDA21D4 + +#define mmNIC3_QM1_CQ_PTR_HI_STS_0 0xDA21D8 + +#define mmNIC3_QM1_CQ_PTR_HI_STS_1 0xDA21DC + +#define mmNIC3_QM1_CQ_PTR_HI_STS_2 0xDA21E0 + +#define mmNIC3_QM1_CQ_PTR_HI_STS_3 0xDA21E4 + +#define mmNIC3_QM1_CQ_PTR_HI_STS_4 0xDA21E8 + +#define mmNIC3_QM1_CQ_TSIZE_STS_0 0xDA21EC + +#define mmNIC3_QM1_CQ_TSIZE_STS_1 0xDA21F0 + +#define mmNIC3_QM1_CQ_TSIZE_STS_2 0xDA21F4 + +#define mmNIC3_QM1_CQ_TSIZE_STS_3 0xDA21F8 + +#define mmNIC3_QM1_CQ_TSIZE_STS_4 0xDA21FC + +#define mmNIC3_QM1_CQ_CTL_STS_0 0xDA2200 + +#define mmNIC3_QM1_CQ_CTL_STS_1 0xDA2204 + +#define mmNIC3_QM1_CQ_CTL_STS_2 0xDA2208 + +#define mmNIC3_QM1_CQ_CTL_STS_3 0xDA220C + +#define mmNIC3_QM1_CQ_CTL_STS_4 0xDA2210 + +#define mmNIC3_QM1_CQ_IFIFO_CNT_0 0xDA2214 + +#define mmNIC3_QM1_CQ_IFIFO_CNT_1 0xDA2218 + +#define mmNIC3_QM1_CQ_IFIFO_CNT_2 0xDA221C + +#define mmNIC3_QM1_CQ_IFIFO_CNT_3 0xDA2220 + +#define mmNIC3_QM1_CQ_IFIFO_CNT_4 0xDA2224 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDA2228 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDA222C + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDA2230 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDA2234 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDA2238 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDA223C + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDA2240 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDA2244 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDA2248 + +#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDA224C + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDA2250 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDA2254 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDA2258 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDA225C + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDA2260 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDA2264 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDA2268 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDA226C + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDA2270 + +#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDA2274 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDA2278 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDA227C + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDA2280 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDA2284 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDA2288 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDA228C + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDA2290 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDA2294 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDA2298 + +#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDA229C + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDA22A0 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDA22A4 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDA22A8 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDA22AC + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDA22B0 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDA22B4 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDA22B8 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDA22BC + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDA22C0 + +#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDA22C4 + +#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDA22C8 + +#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDA22CC + +#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDA22D0 + +#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDA22D4 + +#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDA22D8 + +#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA22E0 + +#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA22E4 + +#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA22E8 + +#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA22EC + +#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA22F0 + +#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA22F4 + +#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA22F8 + +#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA22FC + +#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA2300 + +#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA2304 + +#define mmNIC3_QM1_CP_FENCE0_RDATA_0 0xDA2308 + +#define mmNIC3_QM1_CP_FENCE0_RDATA_1 0xDA230C + +#define mmNIC3_QM1_CP_FENCE0_RDATA_2 0xDA2310 + +#define mmNIC3_QM1_CP_FENCE0_RDATA_3 0xDA2314 + +#define mmNIC3_QM1_CP_FENCE0_RDATA_4 0xDA2318 + +#define mmNIC3_QM1_CP_FENCE1_RDATA_0 0xDA231C + +#define mmNIC3_QM1_CP_FENCE1_RDATA_1 0xDA2320 + +#define mmNIC3_QM1_CP_FENCE1_RDATA_2 0xDA2324 + +#define mmNIC3_QM1_CP_FENCE1_RDATA_3 0xDA2328 + +#define mmNIC3_QM1_CP_FENCE1_RDATA_4 0xDA232C + +#define mmNIC3_QM1_CP_FENCE2_RDATA_0 0xDA2330 + +#define mmNIC3_QM1_CP_FENCE2_RDATA_1 0xDA2334 + +#define mmNIC3_QM1_CP_FENCE2_RDATA_2 0xDA2338 + +#define mmNIC3_QM1_CP_FENCE2_RDATA_3 0xDA233C + +#define mmNIC3_QM1_CP_FENCE2_RDATA_4 0xDA2340 + +#define mmNIC3_QM1_CP_FENCE3_RDATA_0 0xDA2344 + +#define mmNIC3_QM1_CP_FENCE3_RDATA_1 0xDA2348 + +#define mmNIC3_QM1_CP_FENCE3_RDATA_2 0xDA234C + +#define mmNIC3_QM1_CP_FENCE3_RDATA_3 0xDA2350 + +#define mmNIC3_QM1_CP_FENCE3_RDATA_4 0xDA2354 + +#define mmNIC3_QM1_CP_FENCE0_CNT_0 0xDA2358 + +#define mmNIC3_QM1_CP_FENCE0_CNT_1 0xDA235C + +#define mmNIC3_QM1_CP_FENCE0_CNT_2 0xDA2360 + +#define mmNIC3_QM1_CP_FENCE0_CNT_3 0xDA2364 + +#define mmNIC3_QM1_CP_FENCE0_CNT_4 0xDA2368 + +#define mmNIC3_QM1_CP_FENCE1_CNT_0 0xDA236C + +#define mmNIC3_QM1_CP_FENCE1_CNT_1 0xDA2370 + +#define mmNIC3_QM1_CP_FENCE1_CNT_2 0xDA2374 + +#define mmNIC3_QM1_CP_FENCE1_CNT_3 0xDA2378 + +#define mmNIC3_QM1_CP_FENCE1_CNT_4 0xDA237C + +#define mmNIC3_QM1_CP_FENCE2_CNT_0 0xDA2380 + +#define mmNIC3_QM1_CP_FENCE2_CNT_1 0xDA2384 + +#define mmNIC3_QM1_CP_FENCE2_CNT_2 0xDA2388 + +#define mmNIC3_QM1_CP_FENCE2_CNT_3 0xDA238C + +#define mmNIC3_QM1_CP_FENCE2_CNT_4 0xDA2390 + +#define mmNIC3_QM1_CP_FENCE3_CNT_0 0xDA2394 + +#define mmNIC3_QM1_CP_FENCE3_CNT_1 0xDA2398 + +#define mmNIC3_QM1_CP_FENCE3_CNT_2 0xDA239C + +#define mmNIC3_QM1_CP_FENCE3_CNT_3 0xDA23A0 + +#define mmNIC3_QM1_CP_FENCE3_CNT_4 0xDA23A4 + +#define mmNIC3_QM1_CP_STS_0 0xDA23A8 + +#define mmNIC3_QM1_CP_STS_1 0xDA23AC + +#define mmNIC3_QM1_CP_STS_2 0xDA23B0 + +#define mmNIC3_QM1_CP_STS_3 0xDA23B4 + +#define mmNIC3_QM1_CP_STS_4 0xDA23B8 + +#define mmNIC3_QM1_CP_CURRENT_INST_LO_0 0xDA23BC + +#define mmNIC3_QM1_CP_CURRENT_INST_LO_1 0xDA23C0 + +#define mmNIC3_QM1_CP_CURRENT_INST_LO_2 0xDA23C4 + +#define mmNIC3_QM1_CP_CURRENT_INST_LO_3 0xDA23C8 + +#define mmNIC3_QM1_CP_CURRENT_INST_LO_4 0xDA23CC + +#define mmNIC3_QM1_CP_CURRENT_INST_HI_0 0xDA23D0 + +#define mmNIC3_QM1_CP_CURRENT_INST_HI_1 0xDA23D4 + +#define mmNIC3_QM1_CP_CURRENT_INST_HI_2 0xDA23D8 + +#define mmNIC3_QM1_CP_CURRENT_INST_HI_3 0xDA23DC + +#define mmNIC3_QM1_CP_CURRENT_INST_HI_4 0xDA23E0 + +#define mmNIC3_QM1_CP_BARRIER_CFG_0 0xDA23F4 + +#define mmNIC3_QM1_CP_BARRIER_CFG_1 0xDA23F8 + +#define mmNIC3_QM1_CP_BARRIER_CFG_2 0xDA23FC + +#define mmNIC3_QM1_CP_BARRIER_CFG_3 0xDA2400 + +#define mmNIC3_QM1_CP_BARRIER_CFG_4 0xDA2404 + +#define mmNIC3_QM1_CP_DBG_0_0 0xDA2408 + +#define mmNIC3_QM1_CP_DBG_0_1 0xDA240C + +#define mmNIC3_QM1_CP_DBG_0_2 0xDA2410 + +#define mmNIC3_QM1_CP_DBG_0_3 0xDA2414 + +#define mmNIC3_QM1_CP_DBG_0_4 0xDA2418 + +#define mmNIC3_QM1_CP_ARUSER_31_11_0 0xDA241C + +#define mmNIC3_QM1_CP_ARUSER_31_11_1 0xDA2420 + +#define mmNIC3_QM1_CP_ARUSER_31_11_2 0xDA2424 + +#define mmNIC3_QM1_CP_ARUSER_31_11_3 0xDA2428 + +#define mmNIC3_QM1_CP_ARUSER_31_11_4 0xDA242C + +#define mmNIC3_QM1_CP_AWUSER_31_11_0 0xDA2430 + +#define mmNIC3_QM1_CP_AWUSER_31_11_1 0xDA2434 + +#define mmNIC3_QM1_CP_AWUSER_31_11_2 0xDA2438 + +#define mmNIC3_QM1_CP_AWUSER_31_11_3 0xDA243C + +#define mmNIC3_QM1_CP_AWUSER_31_11_4 0xDA2440 + +#define mmNIC3_QM1_ARB_CFG_0 0xDA2A00 + +#define mmNIC3_QM1_ARB_CHOISE_Q_PUSH 0xDA2A04 + +#define mmNIC3_QM1_ARB_WRR_WEIGHT_0 0xDA2A08 + +#define mmNIC3_QM1_ARB_WRR_WEIGHT_1 0xDA2A0C + +#define mmNIC3_QM1_ARB_WRR_WEIGHT_2 0xDA2A10 + +#define mmNIC3_QM1_ARB_WRR_WEIGHT_3 0xDA2A14 + +#define mmNIC3_QM1_ARB_CFG_1 0xDA2A18 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 0xDA2A20 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 0xDA2A24 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 0xDA2A28 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 0xDA2A2C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 0xDA2A30 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 0xDA2A34 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 0xDA2A38 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 0xDA2A3C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 0xDA2A40 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 0xDA2A44 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 0xDA2A48 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 0xDA2A4C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 0xDA2A50 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 0xDA2A54 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 0xDA2A58 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 0xDA2A5C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 0xDA2A60 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 0xDA2A64 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 0xDA2A68 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 0xDA2A6C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 0xDA2A70 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 0xDA2A74 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 0xDA2A78 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 0xDA2A7C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 0xDA2A80 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 0xDA2A84 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 0xDA2A88 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 0xDA2A8C + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 0xDA2A90 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 0xDA2A94 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 0xDA2A98 + +#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 0xDA2A9C + +#define mmNIC3_QM1_ARB_MST_CRED_INC 0xDA2AA0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDA2AA4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDA2AA8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDA2AAC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDA2AB0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDA2AB4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDA2AB8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDA2ABC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDA2AC0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDA2AC4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDA2AC8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDA2ACC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDA2AD0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDA2AD4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDA2AD8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDA2ADC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDA2AE0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDA2AE4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDA2AE8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDA2AEC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDA2AF0 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDA2AF4 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDA2AF8 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDA2AFC + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDA2B00 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDA2B04 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDA2B08 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDA2B0C + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDA2B10 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDA2B14 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDA2B18 + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDA2B1C + +#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDA2B20 + +#define mmNIC3_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDA2B28 + +#define mmNIC3_QM1_ARB_MST_SLAVE_EN 0xDA2B2C + +#define mmNIC3_QM1_ARB_MST_QUIET_PER 0xDA2B34 + +#define mmNIC3_QM1_ARB_SLV_CHOISE_WDT 0xDA2B38 + +#define mmNIC3_QM1_ARB_SLV_ID 0xDA2B3C + +#define mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT 0xDA2B44 + +#define mmNIC3_QM1_ARB_MSG_AWUSER_31_11 0xDA2B48 + +#define mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDA2B4C + +#define mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA2B50 + +#define mmNIC3_QM1_ARB_BASE_LO 0xDA2B54 + +#define mmNIC3_QM1_ARB_BASE_HI 0xDA2B58 + +#define mmNIC3_QM1_ARB_STATE_STS 0xDA2B80 + +#define mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS 0xDA2B84 + +#define mmNIC3_QM1_ARB_MSG_STS 0xDA2B88 + +#define mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDA2B8C + +#define mmNIC3_QM1_ARB_ERR_CAUSE 0xDA2B9C + +#define mmNIC3_QM1_ARB_ERR_MSG_EN 0xDA2BA0 + +#define mmNIC3_QM1_ARB_ERR_STS_DRP 0xDA2BA8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_0 0xDA2BB0 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_1 0xDA2BB4 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_2 0xDA2BB8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_3 0xDA2BBC + +#define mmNIC3_QM1_ARB_MST_CRED_STS_4 0xDA2BC0 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_5 0xDA2BC4 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_6 0xDA2BC8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_7 0xDA2BCC + +#define mmNIC3_QM1_ARB_MST_CRED_STS_8 0xDA2BD0 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_9 0xDA2BD4 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_10 0xDA2BD8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_11 0xDA2BDC + +#define mmNIC3_QM1_ARB_MST_CRED_STS_12 0xDA2BE0 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_13 0xDA2BE4 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_14 0xDA2BE8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_15 0xDA2BEC + +#define mmNIC3_QM1_ARB_MST_CRED_STS_16 0xDA2BF0 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_17 0xDA2BF4 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_18 0xDA2BF8 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_19 0xDA2BFC + +#define mmNIC3_QM1_ARB_MST_CRED_STS_20 0xDA2C00 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_21 0xDA2C04 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_22 0xDA2C08 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_23 0xDA2C0C + +#define mmNIC3_QM1_ARB_MST_CRED_STS_24 0xDA2C10 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_25 0xDA2C14 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_26 0xDA2C18 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_27 0xDA2C1C + +#define mmNIC3_QM1_ARB_MST_CRED_STS_28 0xDA2C20 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_29 0xDA2C24 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_30 0xDA2C28 + +#define mmNIC3_QM1_ARB_MST_CRED_STS_31 0xDA2C2C + +#define mmNIC3_QM1_CGM_CFG 0xDA2C70 + +#define mmNIC3_QM1_CGM_STS 0xDA2C74 + +#define mmNIC3_QM1_CGM_CFG1 0xDA2C78 + +#define mmNIC3_QM1_LOCAL_RANGE_BASE 0xDA2C80 + +#define mmNIC3_QM1_LOCAL_RANGE_SIZE 0xDA2C84 + +#define mmNIC3_QM1_CSMR_STRICT_PRIO_CFG 0xDA2C90 + +#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 0xDA2C94 + +#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 0xDA2C98 + +#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 0xDA2C9C + +#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 0xDA2CA0 + +#define mmNIC3_QM1_GLBL_AXCACHE 0xDA2CA4 + +#define mmNIC3_QM1_IND_GW_APB_CFG 0xDA2CB0 + +#define mmNIC3_QM1_IND_GW_APB_WDATA 0xDA2CB4 + +#define mmNIC3_QM1_IND_GW_APB_RDATA 0xDA2CB8 + +#define mmNIC3_QM1_IND_GW_APB_STATUS 0xDA2CBC + +#define mmNIC3_QM1_GLBL_ERR_ADDR_LO 0xDA2CD0 + +#define mmNIC3_QM1_GLBL_ERR_ADDR_HI 0xDA2CD4 + +#define mmNIC3_QM1_GLBL_ERR_WDATA 0xDA2CD8 + +#define mmNIC3_QM1_GLBL_MEM_INIT_BUSY 0xDA2D00 + +#endif /* ASIC_REG_NIC3_QM1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h new file mode 100644 index 000000000..99d531967 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC4_QM0_REGS_H_ +#define ASIC_REG_NIC4_QM0_REGS_H_ + +/* + ***************************************** + * NIC4_QM0 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC4_QM0_GLBL_CFG0 0xDE0000 + +#define mmNIC4_QM0_GLBL_CFG1 0xDE0004 + +#define mmNIC4_QM0_GLBL_PROT 0xDE0008 + +#define mmNIC4_QM0_GLBL_ERR_CFG 0xDE000C + +#define mmNIC4_QM0_GLBL_SECURE_PROPS_0 0xDE0010 + +#define mmNIC4_QM0_GLBL_SECURE_PROPS_1 0xDE0014 + +#define mmNIC4_QM0_GLBL_SECURE_PROPS_2 0xDE0018 + +#define mmNIC4_QM0_GLBL_SECURE_PROPS_3 0xDE001C + +#define mmNIC4_QM0_GLBL_SECURE_PROPS_4 0xDE0020 + +#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0 0xDE0024 + +#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1 0xDE0028 + +#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2 0xDE002C + +#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3 0xDE0030 + +#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4 0xDE0034 + +#define mmNIC4_QM0_GLBL_STS0 0xDE0038 + +#define mmNIC4_QM0_GLBL_STS1_0 0xDE0040 + +#define mmNIC4_QM0_GLBL_STS1_1 0xDE0044 + +#define mmNIC4_QM0_GLBL_STS1_2 0xDE0048 + +#define mmNIC4_QM0_GLBL_STS1_3 0xDE004C + +#define mmNIC4_QM0_GLBL_STS1_4 0xDE0050 + +#define mmNIC4_QM0_GLBL_MSG_EN_0 0xDE0054 + +#define mmNIC4_QM0_GLBL_MSG_EN_1 0xDE0058 + +#define mmNIC4_QM0_GLBL_MSG_EN_2 0xDE005C + +#define mmNIC4_QM0_GLBL_MSG_EN_3 0xDE0060 + +#define mmNIC4_QM0_GLBL_MSG_EN_4 0xDE0068 + +#define mmNIC4_QM0_PQ_BASE_LO_0 0xDE0070 + +#define mmNIC4_QM0_PQ_BASE_LO_1 0xDE0074 + +#define mmNIC4_QM0_PQ_BASE_LO_2 0xDE0078 + +#define mmNIC4_QM0_PQ_BASE_LO_3 0xDE007C + +#define mmNIC4_QM0_PQ_BASE_HI_0 0xDE0080 + +#define mmNIC4_QM0_PQ_BASE_HI_1 0xDE0084 + +#define mmNIC4_QM0_PQ_BASE_HI_2 0xDE0088 + +#define mmNIC4_QM0_PQ_BASE_HI_3 0xDE008C + +#define mmNIC4_QM0_PQ_SIZE_0 0xDE0090 + +#define mmNIC4_QM0_PQ_SIZE_1 0xDE0094 + +#define mmNIC4_QM0_PQ_SIZE_2 0xDE0098 + +#define mmNIC4_QM0_PQ_SIZE_3 0xDE009C + +#define mmNIC4_QM0_PQ_PI_0 0xDE00A0 + +#define mmNIC4_QM0_PQ_PI_1 0xDE00A4 + +#define mmNIC4_QM0_PQ_PI_2 0xDE00A8 + +#define mmNIC4_QM0_PQ_PI_3 0xDE00AC + +#define mmNIC4_QM0_PQ_CI_0 0xDE00B0 + +#define mmNIC4_QM0_PQ_CI_1 0xDE00B4 + +#define mmNIC4_QM0_PQ_CI_2 0xDE00B8 + +#define mmNIC4_QM0_PQ_CI_3 0xDE00BC + +#define mmNIC4_QM0_PQ_CFG0_0 0xDE00C0 + +#define mmNIC4_QM0_PQ_CFG0_1 0xDE00C4 + +#define mmNIC4_QM0_PQ_CFG0_2 0xDE00C8 + +#define mmNIC4_QM0_PQ_CFG0_3 0xDE00CC + +#define mmNIC4_QM0_PQ_CFG1_0 0xDE00D0 + +#define mmNIC4_QM0_PQ_CFG1_1 0xDE00D4 + +#define mmNIC4_QM0_PQ_CFG1_2 0xDE00D8 + +#define mmNIC4_QM0_PQ_CFG1_3 0xDE00DC + +#define mmNIC4_QM0_PQ_ARUSER_31_11_0 0xDE00E0 + +#define mmNIC4_QM0_PQ_ARUSER_31_11_1 0xDE00E4 + +#define mmNIC4_QM0_PQ_ARUSER_31_11_2 0xDE00E8 + +#define mmNIC4_QM0_PQ_ARUSER_31_11_3 0xDE00EC + +#define mmNIC4_QM0_PQ_STS0_0 0xDE00F0 + +#define mmNIC4_QM0_PQ_STS0_1 0xDE00F4 + +#define mmNIC4_QM0_PQ_STS0_2 0xDE00F8 + +#define mmNIC4_QM0_PQ_STS0_3 0xDE00FC + +#define mmNIC4_QM0_PQ_STS1_0 0xDE0100 + +#define mmNIC4_QM0_PQ_STS1_1 0xDE0104 + +#define mmNIC4_QM0_PQ_STS1_2 0xDE0108 + +#define mmNIC4_QM0_PQ_STS1_3 0xDE010C + +#define mmNIC4_QM0_CQ_CFG0_0 0xDE0110 + +#define mmNIC4_QM0_CQ_CFG0_1 0xDE0114 + +#define mmNIC4_QM0_CQ_CFG0_2 0xDE0118 + +#define mmNIC4_QM0_CQ_CFG0_3 0xDE011C + +#define mmNIC4_QM0_CQ_CFG0_4 0xDE0120 + +#define mmNIC4_QM0_CQ_CFG1_0 0xDE0124 + +#define mmNIC4_QM0_CQ_CFG1_1 0xDE0128 + +#define mmNIC4_QM0_CQ_CFG1_2 0xDE012C + +#define mmNIC4_QM0_CQ_CFG1_3 0xDE0130 + +#define mmNIC4_QM0_CQ_CFG1_4 0xDE0134 + +#define mmNIC4_QM0_CQ_ARUSER_31_11_0 0xDE0138 + +#define mmNIC4_QM0_CQ_ARUSER_31_11_1 0xDE013C + +#define mmNIC4_QM0_CQ_ARUSER_31_11_2 0xDE0140 + +#define mmNIC4_QM0_CQ_ARUSER_31_11_3 0xDE0144 + +#define mmNIC4_QM0_CQ_ARUSER_31_11_4 0xDE0148 + +#define mmNIC4_QM0_CQ_STS0_0 0xDE014C + +#define mmNIC4_QM0_CQ_STS0_1 0xDE0150 + +#define mmNIC4_QM0_CQ_STS0_2 0xDE0154 + +#define mmNIC4_QM0_CQ_STS0_3 0xDE0158 + +#define mmNIC4_QM0_CQ_STS0_4 0xDE015C + +#define mmNIC4_QM0_CQ_STS1_0 0xDE0160 + +#define mmNIC4_QM0_CQ_STS1_1 0xDE0164 + +#define mmNIC4_QM0_CQ_STS1_2 0xDE0168 + +#define mmNIC4_QM0_CQ_STS1_3 0xDE016C + +#define mmNIC4_QM0_CQ_STS1_4 0xDE0170 + +#define mmNIC4_QM0_CQ_PTR_LO_0 0xDE0174 + +#define mmNIC4_QM0_CQ_PTR_HI_0 0xDE0178 + +#define mmNIC4_QM0_CQ_TSIZE_0 0xDE017C + +#define mmNIC4_QM0_CQ_CTL_0 0xDE0180 + +#define mmNIC4_QM0_CQ_PTR_LO_1 0xDE0184 + +#define mmNIC4_QM0_CQ_PTR_HI_1 0xDE0188 + +#define mmNIC4_QM0_CQ_TSIZE_1 0xDE018C + +#define mmNIC4_QM0_CQ_CTL_1 0xDE0190 + +#define mmNIC4_QM0_CQ_PTR_LO_2 0xDE0194 + +#define mmNIC4_QM0_CQ_PTR_HI_2 0xDE0198 + +#define mmNIC4_QM0_CQ_TSIZE_2 0xDE019C + +#define mmNIC4_QM0_CQ_CTL_2 0xDE01A0 + +#define mmNIC4_QM0_CQ_PTR_LO_3 0xDE01A4 + +#define mmNIC4_QM0_CQ_PTR_HI_3 0xDE01A8 + +#define mmNIC4_QM0_CQ_TSIZE_3 0xDE01AC + +#define mmNIC4_QM0_CQ_CTL_3 0xDE01B0 + +#define mmNIC4_QM0_CQ_PTR_LO_4 0xDE01B4 + +#define mmNIC4_QM0_CQ_PTR_HI_4 0xDE01B8 + +#define mmNIC4_QM0_CQ_TSIZE_4 0xDE01BC + +#define mmNIC4_QM0_CQ_CTL_4 0xDE01C0 + +#define mmNIC4_QM0_CQ_PTR_LO_STS_0 0xDE01C4 + +#define mmNIC4_QM0_CQ_PTR_LO_STS_1 0xDE01C8 + +#define mmNIC4_QM0_CQ_PTR_LO_STS_2 0xDE01CC + +#define mmNIC4_QM0_CQ_PTR_LO_STS_3 0xDE01D0 + +#define mmNIC4_QM0_CQ_PTR_LO_STS_4 0xDE01D4 + +#define mmNIC4_QM0_CQ_PTR_HI_STS_0 0xDE01D8 + +#define mmNIC4_QM0_CQ_PTR_HI_STS_1 0xDE01DC + +#define mmNIC4_QM0_CQ_PTR_HI_STS_2 0xDE01E0 + +#define mmNIC4_QM0_CQ_PTR_HI_STS_3 0xDE01E4 + +#define mmNIC4_QM0_CQ_PTR_HI_STS_4 0xDE01E8 + +#define mmNIC4_QM0_CQ_TSIZE_STS_0 0xDE01EC + +#define mmNIC4_QM0_CQ_TSIZE_STS_1 0xDE01F0 + +#define mmNIC4_QM0_CQ_TSIZE_STS_2 0xDE01F4 + +#define mmNIC4_QM0_CQ_TSIZE_STS_3 0xDE01F8 + +#define mmNIC4_QM0_CQ_TSIZE_STS_4 0xDE01FC + +#define mmNIC4_QM0_CQ_CTL_STS_0 0xDE0200 + +#define mmNIC4_QM0_CQ_CTL_STS_1 0xDE0204 + +#define mmNIC4_QM0_CQ_CTL_STS_2 0xDE0208 + +#define mmNIC4_QM0_CQ_CTL_STS_3 0xDE020C + +#define mmNIC4_QM0_CQ_CTL_STS_4 0xDE0210 + +#define mmNIC4_QM0_CQ_IFIFO_CNT_0 0xDE0214 + +#define mmNIC4_QM0_CQ_IFIFO_CNT_1 0xDE0218 + +#define mmNIC4_QM0_CQ_IFIFO_CNT_2 0xDE021C + +#define mmNIC4_QM0_CQ_IFIFO_CNT_3 0xDE0220 + +#define mmNIC4_QM0_CQ_IFIFO_CNT_4 0xDE0224 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDE0228 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDE022C + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDE0230 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDE0234 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDE0238 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDE023C + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDE0240 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDE0244 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDE0248 + +#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDE024C + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDE0250 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDE0254 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDE0258 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDE025C + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDE0260 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDE0264 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDE0268 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDE026C + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDE0270 + +#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDE0274 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDE0278 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDE027C + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDE0280 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDE0284 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDE0288 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDE028C + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDE0290 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDE0294 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDE0298 + +#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDE029C + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDE02A0 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDE02A4 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDE02A8 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDE02AC + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDE02B0 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDE02B4 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDE02B8 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDE02BC + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDE02C0 + +#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDE02C4 + +#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDE02C8 + +#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDE02CC + +#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDE02D0 + +#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDE02D4 + +#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDE02D8 + +#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE02E0 + +#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE02E4 + +#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE02E8 + +#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE02EC + +#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE02F0 + +#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE02F4 + +#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE02F8 + +#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE02FC + +#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE0300 + +#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE0304 + +#define mmNIC4_QM0_CP_FENCE0_RDATA_0 0xDE0308 + +#define mmNIC4_QM0_CP_FENCE0_RDATA_1 0xDE030C + +#define mmNIC4_QM0_CP_FENCE0_RDATA_2 0xDE0310 + +#define mmNIC4_QM0_CP_FENCE0_RDATA_3 0xDE0314 + +#define mmNIC4_QM0_CP_FENCE0_RDATA_4 0xDE0318 + +#define mmNIC4_QM0_CP_FENCE1_RDATA_0 0xDE031C + +#define mmNIC4_QM0_CP_FENCE1_RDATA_1 0xDE0320 + +#define mmNIC4_QM0_CP_FENCE1_RDATA_2 0xDE0324 + +#define mmNIC4_QM0_CP_FENCE1_RDATA_3 0xDE0328 + +#define mmNIC4_QM0_CP_FENCE1_RDATA_4 0xDE032C + +#define mmNIC4_QM0_CP_FENCE2_RDATA_0 0xDE0330 + +#define mmNIC4_QM0_CP_FENCE2_RDATA_1 0xDE0334 + +#define mmNIC4_QM0_CP_FENCE2_RDATA_2 0xDE0338 + +#define mmNIC4_QM0_CP_FENCE2_RDATA_3 0xDE033C + +#define mmNIC4_QM0_CP_FENCE2_RDATA_4 0xDE0340 + +#define mmNIC4_QM0_CP_FENCE3_RDATA_0 0xDE0344 + +#define mmNIC4_QM0_CP_FENCE3_RDATA_1 0xDE0348 + +#define mmNIC4_QM0_CP_FENCE3_RDATA_2 0xDE034C + +#define mmNIC4_QM0_CP_FENCE3_RDATA_3 0xDE0350 + +#define mmNIC4_QM0_CP_FENCE3_RDATA_4 0xDE0354 + +#define mmNIC4_QM0_CP_FENCE0_CNT_0 0xDE0358 + +#define mmNIC4_QM0_CP_FENCE0_CNT_1 0xDE035C + +#define mmNIC4_QM0_CP_FENCE0_CNT_2 0xDE0360 + +#define mmNIC4_QM0_CP_FENCE0_CNT_3 0xDE0364 + +#define mmNIC4_QM0_CP_FENCE0_CNT_4 0xDE0368 + +#define mmNIC4_QM0_CP_FENCE1_CNT_0 0xDE036C + +#define mmNIC4_QM0_CP_FENCE1_CNT_1 0xDE0370 + +#define mmNIC4_QM0_CP_FENCE1_CNT_2 0xDE0374 + +#define mmNIC4_QM0_CP_FENCE1_CNT_3 0xDE0378 + +#define mmNIC4_QM0_CP_FENCE1_CNT_4 0xDE037C + +#define mmNIC4_QM0_CP_FENCE2_CNT_0 0xDE0380 + +#define mmNIC4_QM0_CP_FENCE2_CNT_1 0xDE0384 + +#define mmNIC4_QM0_CP_FENCE2_CNT_2 0xDE0388 + +#define mmNIC4_QM0_CP_FENCE2_CNT_3 0xDE038C + +#define mmNIC4_QM0_CP_FENCE2_CNT_4 0xDE0390 + +#define mmNIC4_QM0_CP_FENCE3_CNT_0 0xDE0394 + +#define mmNIC4_QM0_CP_FENCE3_CNT_1 0xDE0398 + +#define mmNIC4_QM0_CP_FENCE3_CNT_2 0xDE039C + +#define mmNIC4_QM0_CP_FENCE3_CNT_3 0xDE03A0 + +#define mmNIC4_QM0_CP_FENCE3_CNT_4 0xDE03A4 + +#define mmNIC4_QM0_CP_STS_0 0xDE03A8 + +#define mmNIC4_QM0_CP_STS_1 0xDE03AC + +#define mmNIC4_QM0_CP_STS_2 0xDE03B0 + +#define mmNIC4_QM0_CP_STS_3 0xDE03B4 + +#define mmNIC4_QM0_CP_STS_4 0xDE03B8 + +#define mmNIC4_QM0_CP_CURRENT_INST_LO_0 0xDE03BC + +#define mmNIC4_QM0_CP_CURRENT_INST_LO_1 0xDE03C0 + +#define mmNIC4_QM0_CP_CURRENT_INST_LO_2 0xDE03C4 + +#define mmNIC4_QM0_CP_CURRENT_INST_LO_3 0xDE03C8 + +#define mmNIC4_QM0_CP_CURRENT_INST_LO_4 0xDE03CC + +#define mmNIC4_QM0_CP_CURRENT_INST_HI_0 0xDE03D0 + +#define mmNIC4_QM0_CP_CURRENT_INST_HI_1 0xDE03D4 + +#define mmNIC4_QM0_CP_CURRENT_INST_HI_2 0xDE03D8 + +#define mmNIC4_QM0_CP_CURRENT_INST_HI_3 0xDE03DC + +#define mmNIC4_QM0_CP_CURRENT_INST_HI_4 0xDE03E0 + +#define mmNIC4_QM0_CP_BARRIER_CFG_0 0xDE03F4 + +#define mmNIC4_QM0_CP_BARRIER_CFG_1 0xDE03F8 + +#define mmNIC4_QM0_CP_BARRIER_CFG_2 0xDE03FC + +#define mmNIC4_QM0_CP_BARRIER_CFG_3 0xDE0400 + +#define mmNIC4_QM0_CP_BARRIER_CFG_4 0xDE0404 + +#define mmNIC4_QM0_CP_DBG_0_0 0xDE0408 + +#define mmNIC4_QM0_CP_DBG_0_1 0xDE040C + +#define mmNIC4_QM0_CP_DBG_0_2 0xDE0410 + +#define mmNIC4_QM0_CP_DBG_0_3 0xDE0414 + +#define mmNIC4_QM0_CP_DBG_0_4 0xDE0418 + +#define mmNIC4_QM0_CP_ARUSER_31_11_0 0xDE041C + +#define mmNIC4_QM0_CP_ARUSER_31_11_1 0xDE0420 + +#define mmNIC4_QM0_CP_ARUSER_31_11_2 0xDE0424 + +#define mmNIC4_QM0_CP_ARUSER_31_11_3 0xDE0428 + +#define mmNIC4_QM0_CP_ARUSER_31_11_4 0xDE042C + +#define mmNIC4_QM0_CP_AWUSER_31_11_0 0xDE0430 + +#define mmNIC4_QM0_CP_AWUSER_31_11_1 0xDE0434 + +#define mmNIC4_QM0_CP_AWUSER_31_11_2 0xDE0438 + +#define mmNIC4_QM0_CP_AWUSER_31_11_3 0xDE043C + +#define mmNIC4_QM0_CP_AWUSER_31_11_4 0xDE0440 + +#define mmNIC4_QM0_ARB_CFG_0 0xDE0A00 + +#define mmNIC4_QM0_ARB_CHOISE_Q_PUSH 0xDE0A04 + +#define mmNIC4_QM0_ARB_WRR_WEIGHT_0 0xDE0A08 + +#define mmNIC4_QM0_ARB_WRR_WEIGHT_1 0xDE0A0C + +#define mmNIC4_QM0_ARB_WRR_WEIGHT_2 0xDE0A10 + +#define mmNIC4_QM0_ARB_WRR_WEIGHT_3 0xDE0A14 + +#define mmNIC4_QM0_ARB_CFG_1 0xDE0A18 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_0 0xDE0A20 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_1 0xDE0A24 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_2 0xDE0A28 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_3 0xDE0A2C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_4 0xDE0A30 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_5 0xDE0A34 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_6 0xDE0A38 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_7 0xDE0A3C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_8 0xDE0A40 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_9 0xDE0A44 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_10 0xDE0A48 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_11 0xDE0A4C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_12 0xDE0A50 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_13 0xDE0A54 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_14 0xDE0A58 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_15 0xDE0A5C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_16 0xDE0A60 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_17 0xDE0A64 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_18 0xDE0A68 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_19 0xDE0A6C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_20 0xDE0A70 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_21 0xDE0A74 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_22 0xDE0A78 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_23 0xDE0A7C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 0xDE0A80 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_25 0xDE0A84 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_26 0xDE0A88 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_27 0xDE0A8C + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_28 0xDE0A90 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_29 0xDE0A94 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_30 0xDE0A98 + +#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_31 0xDE0A9C + +#define mmNIC4_QM0_ARB_MST_CRED_INC 0xDE0AA0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDE0AA4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDE0AA8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDE0AAC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDE0AB0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDE0AB4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDE0AB8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDE0ABC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDE0AC0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDE0AC4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDE0AC8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDE0ACC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDE0AD0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDE0AD4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDE0AD8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDE0ADC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDE0AE0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDE0AE4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDE0AE8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDE0AEC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDE0AF0 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDE0AF4 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDE0AF8 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDE0AFC + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDE0B00 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDE0B04 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDE0B08 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDE0B0C + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDE0B10 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDE0B14 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDE0B18 + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDE0B1C + +#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDE0B20 + +#define mmNIC4_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDE0B28 + +#define mmNIC4_QM0_ARB_MST_SLAVE_EN 0xDE0B2C + +#define mmNIC4_QM0_ARB_MST_QUIET_PER 0xDE0B34 + +#define mmNIC4_QM0_ARB_SLV_CHOISE_WDT 0xDE0B38 + +#define mmNIC4_QM0_ARB_SLV_ID 0xDE0B3C + +#define mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT 0xDE0B44 + +#define mmNIC4_QM0_ARB_MSG_AWUSER_31_11 0xDE0B48 + +#define mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDE0B4C + +#define mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE0B50 + +#define mmNIC4_QM0_ARB_BASE_LO 0xDE0B54 + +#define mmNIC4_QM0_ARB_BASE_HI 0xDE0B58 + +#define mmNIC4_QM0_ARB_STATE_STS 0xDE0B80 + +#define mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS 0xDE0B84 + +#define mmNIC4_QM0_ARB_MSG_STS 0xDE0B88 + +#define mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDE0B8C + +#define mmNIC4_QM0_ARB_ERR_CAUSE 0xDE0B9C + +#define mmNIC4_QM0_ARB_ERR_MSG_EN 0xDE0BA0 + +#define mmNIC4_QM0_ARB_ERR_STS_DRP 0xDE0BA8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_0 0xDE0BB0 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_1 0xDE0BB4 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_2 0xDE0BB8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_3 0xDE0BBC + +#define mmNIC4_QM0_ARB_MST_CRED_STS_4 0xDE0BC0 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_5 0xDE0BC4 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_6 0xDE0BC8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_7 0xDE0BCC + +#define mmNIC4_QM0_ARB_MST_CRED_STS_8 0xDE0BD0 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_9 0xDE0BD4 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_10 0xDE0BD8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_11 0xDE0BDC + +#define mmNIC4_QM0_ARB_MST_CRED_STS_12 0xDE0BE0 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_13 0xDE0BE4 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_14 0xDE0BE8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_15 0xDE0BEC + +#define mmNIC4_QM0_ARB_MST_CRED_STS_16 0xDE0BF0 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_17 0xDE0BF4 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_18 0xDE0BF8 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_19 0xDE0BFC + +#define mmNIC4_QM0_ARB_MST_CRED_STS_20 0xDE0C00 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_21 0xDE0C04 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_22 0xDE0C08 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_23 0xDE0C0C + +#define mmNIC4_QM0_ARB_MST_CRED_STS_24 0xDE0C10 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_25 0xDE0C14 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_26 0xDE0C18 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_27 0xDE0C1C + +#define mmNIC4_QM0_ARB_MST_CRED_STS_28 0xDE0C20 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_29 0xDE0C24 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_30 0xDE0C28 + +#define mmNIC4_QM0_ARB_MST_CRED_STS_31 0xDE0C2C + +#define mmNIC4_QM0_CGM_CFG 0xDE0C70 + +#define mmNIC4_QM0_CGM_STS 0xDE0C74 + +#define mmNIC4_QM0_CGM_CFG1 0xDE0C78 + +#define mmNIC4_QM0_LOCAL_RANGE_BASE 0xDE0C80 + +#define mmNIC4_QM0_LOCAL_RANGE_SIZE 0xDE0C84 + +#define mmNIC4_QM0_CSMR_STRICT_PRIO_CFG 0xDE0C90 + +#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1 0xDE0C94 + +#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0 0xDE0C98 + +#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1 0xDE0C9C + +#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0 0xDE0CA0 + +#define mmNIC4_QM0_GLBL_AXCACHE 0xDE0CA4 + +#define mmNIC4_QM0_IND_GW_APB_CFG 0xDE0CB0 + +#define mmNIC4_QM0_IND_GW_APB_WDATA 0xDE0CB4 + +#define mmNIC4_QM0_IND_GW_APB_RDATA 0xDE0CB8 + +#define mmNIC4_QM0_IND_GW_APB_STATUS 0xDE0CBC + +#define mmNIC4_QM0_GLBL_ERR_ADDR_LO 0xDE0CD0 + +#define mmNIC4_QM0_GLBL_ERR_ADDR_HI 0xDE0CD4 + +#define mmNIC4_QM0_GLBL_ERR_WDATA 0xDE0CD8 + +#define mmNIC4_QM0_GLBL_MEM_INIT_BUSY 0xDE0D00 + +#endif /* ASIC_REG_NIC4_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h new file mode 100644 index 000000000..34b21b21d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC4_QM1_REGS_H_ +#define ASIC_REG_NIC4_QM1_REGS_H_ + +/* + ***************************************** + * NIC4_QM1 (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC4_QM1_GLBL_CFG0 0xDE2000 + +#define mmNIC4_QM1_GLBL_CFG1 0xDE2004 + +#define mmNIC4_QM1_GLBL_PROT 0xDE2008 + +#define mmNIC4_QM1_GLBL_ERR_CFG 0xDE200C + +#define mmNIC4_QM1_GLBL_SECURE_PROPS_0 0xDE2010 + +#define mmNIC4_QM1_GLBL_SECURE_PROPS_1 0xDE2014 + +#define mmNIC4_QM1_GLBL_SECURE_PROPS_2 0xDE2018 + +#define mmNIC4_QM1_GLBL_SECURE_PROPS_3 0xDE201C + +#define mmNIC4_QM1_GLBL_SECURE_PROPS_4 0xDE2020 + +#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 0xDE2024 + +#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 0xDE2028 + +#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 0xDE202C + +#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 0xDE2030 + +#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 0xDE2034 + +#define mmNIC4_QM1_GLBL_STS0 0xDE2038 + +#define mmNIC4_QM1_GLBL_STS1_0 0xDE2040 + +#define mmNIC4_QM1_GLBL_STS1_1 0xDE2044 + +#define mmNIC4_QM1_GLBL_STS1_2 0xDE2048 + +#define mmNIC4_QM1_GLBL_STS1_3 0xDE204C + +#define mmNIC4_QM1_GLBL_STS1_4 0xDE2050 + +#define mmNIC4_QM1_GLBL_MSG_EN_0 0xDE2054 + +#define mmNIC4_QM1_GLBL_MSG_EN_1 0xDE2058 + +#define mmNIC4_QM1_GLBL_MSG_EN_2 0xDE205C + +#define mmNIC4_QM1_GLBL_MSG_EN_3 0xDE2060 + +#define mmNIC4_QM1_GLBL_MSG_EN_4 0xDE2068 + +#define mmNIC4_QM1_PQ_BASE_LO_0 0xDE2070 + +#define mmNIC4_QM1_PQ_BASE_LO_1 0xDE2074 + +#define mmNIC4_QM1_PQ_BASE_LO_2 0xDE2078 + +#define mmNIC4_QM1_PQ_BASE_LO_3 0xDE207C + +#define mmNIC4_QM1_PQ_BASE_HI_0 0xDE2080 + +#define mmNIC4_QM1_PQ_BASE_HI_1 0xDE2084 + +#define mmNIC4_QM1_PQ_BASE_HI_2 0xDE2088 + +#define mmNIC4_QM1_PQ_BASE_HI_3 0xDE208C + +#define mmNIC4_QM1_PQ_SIZE_0 0xDE2090 + +#define mmNIC4_QM1_PQ_SIZE_1 0xDE2094 + +#define mmNIC4_QM1_PQ_SIZE_2 0xDE2098 + +#define mmNIC4_QM1_PQ_SIZE_3 0xDE209C + +#define mmNIC4_QM1_PQ_PI_0 0xDE20A0 + +#define mmNIC4_QM1_PQ_PI_1 0xDE20A4 + +#define mmNIC4_QM1_PQ_PI_2 0xDE20A8 + +#define mmNIC4_QM1_PQ_PI_3 0xDE20AC + +#define mmNIC4_QM1_PQ_CI_0 0xDE20B0 + +#define mmNIC4_QM1_PQ_CI_1 0xDE20B4 + +#define mmNIC4_QM1_PQ_CI_2 0xDE20B8 + +#define mmNIC4_QM1_PQ_CI_3 0xDE20BC + +#define mmNIC4_QM1_PQ_CFG0_0 0xDE20C0 + +#define mmNIC4_QM1_PQ_CFG0_1 0xDE20C4 + +#define mmNIC4_QM1_PQ_CFG0_2 0xDE20C8 + +#define mmNIC4_QM1_PQ_CFG0_3 0xDE20CC + +#define mmNIC4_QM1_PQ_CFG1_0 0xDE20D0 + +#define mmNIC4_QM1_PQ_CFG1_1 0xDE20D4 + +#define mmNIC4_QM1_PQ_CFG1_2 0xDE20D8 + +#define mmNIC4_QM1_PQ_CFG1_3 0xDE20DC + +#define mmNIC4_QM1_PQ_ARUSER_31_11_0 0xDE20E0 + +#define mmNIC4_QM1_PQ_ARUSER_31_11_1 0xDE20E4 + +#define mmNIC4_QM1_PQ_ARUSER_31_11_2 0xDE20E8 + +#define mmNIC4_QM1_PQ_ARUSER_31_11_3 0xDE20EC + +#define mmNIC4_QM1_PQ_STS0_0 0xDE20F0 + +#define mmNIC4_QM1_PQ_STS0_1 0xDE20F4 + +#define mmNIC4_QM1_PQ_STS0_2 0xDE20F8 + +#define mmNIC4_QM1_PQ_STS0_3 0xDE20FC + +#define mmNIC4_QM1_PQ_STS1_0 0xDE2100 + +#define mmNIC4_QM1_PQ_STS1_1 0xDE2104 + +#define mmNIC4_QM1_PQ_STS1_2 0xDE2108 + +#define mmNIC4_QM1_PQ_STS1_3 0xDE210C + +#define mmNIC4_QM1_CQ_CFG0_0 0xDE2110 + +#define mmNIC4_QM1_CQ_CFG0_1 0xDE2114 + +#define mmNIC4_QM1_CQ_CFG0_2 0xDE2118 + +#define mmNIC4_QM1_CQ_CFG0_3 0xDE211C + +#define mmNIC4_QM1_CQ_CFG0_4 0xDE2120 + +#define mmNIC4_QM1_CQ_CFG1_0 0xDE2124 + +#define mmNIC4_QM1_CQ_CFG1_1 0xDE2128 + +#define mmNIC4_QM1_CQ_CFG1_2 0xDE212C + +#define mmNIC4_QM1_CQ_CFG1_3 0xDE2130 + +#define mmNIC4_QM1_CQ_CFG1_4 0xDE2134 + +#define mmNIC4_QM1_CQ_ARUSER_31_11_0 0xDE2138 + +#define mmNIC4_QM1_CQ_ARUSER_31_11_1 0xDE213C + +#define mmNIC4_QM1_CQ_ARUSER_31_11_2 0xDE2140 + +#define mmNIC4_QM1_CQ_ARUSER_31_11_3 0xDE2144 + +#define mmNIC4_QM1_CQ_ARUSER_31_11_4 0xDE2148 + +#define mmNIC4_QM1_CQ_STS0_0 0xDE214C + +#define mmNIC4_QM1_CQ_STS0_1 0xDE2150 + +#define mmNIC4_QM1_CQ_STS0_2 0xDE2154 + +#define mmNIC4_QM1_CQ_STS0_3 0xDE2158 + +#define mmNIC4_QM1_CQ_STS0_4 0xDE215C + +#define mmNIC4_QM1_CQ_STS1_0 0xDE2160 + +#define mmNIC4_QM1_CQ_STS1_1 0xDE2164 + +#define mmNIC4_QM1_CQ_STS1_2 0xDE2168 + +#define mmNIC4_QM1_CQ_STS1_3 0xDE216C + +#define mmNIC4_QM1_CQ_STS1_4 0xDE2170 + +#define mmNIC4_QM1_CQ_PTR_LO_0 0xDE2174 + +#define mmNIC4_QM1_CQ_PTR_HI_0 0xDE2178 + +#define mmNIC4_QM1_CQ_TSIZE_0 0xDE217C + +#define mmNIC4_QM1_CQ_CTL_0 0xDE2180 + +#define mmNIC4_QM1_CQ_PTR_LO_1 0xDE2184 + +#define mmNIC4_QM1_CQ_PTR_HI_1 0xDE2188 + +#define mmNIC4_QM1_CQ_TSIZE_1 0xDE218C + +#define mmNIC4_QM1_CQ_CTL_1 0xDE2190 + +#define mmNIC4_QM1_CQ_PTR_LO_2 0xDE2194 + +#define mmNIC4_QM1_CQ_PTR_HI_2 0xDE2198 + +#define mmNIC4_QM1_CQ_TSIZE_2 0xDE219C + +#define mmNIC4_QM1_CQ_CTL_2 0xDE21A0 + +#define mmNIC4_QM1_CQ_PTR_LO_3 0xDE21A4 + +#define mmNIC4_QM1_CQ_PTR_HI_3 0xDE21A8 + +#define mmNIC4_QM1_CQ_TSIZE_3 0xDE21AC + +#define mmNIC4_QM1_CQ_CTL_3 0xDE21B0 + +#define mmNIC4_QM1_CQ_PTR_LO_4 0xDE21B4 + +#define mmNIC4_QM1_CQ_PTR_HI_4 0xDE21B8 + +#define mmNIC4_QM1_CQ_TSIZE_4 0xDE21BC + +#define mmNIC4_QM1_CQ_CTL_4 0xDE21C0 + +#define mmNIC4_QM1_CQ_PTR_LO_STS_0 0xDE21C4 + +#define mmNIC4_QM1_CQ_PTR_LO_STS_1 0xDE21C8 + +#define mmNIC4_QM1_CQ_PTR_LO_STS_2 0xDE21CC + +#define mmNIC4_QM1_CQ_PTR_LO_STS_3 0xDE21D0 + +#define mmNIC4_QM1_CQ_PTR_LO_STS_4 0xDE21D4 + +#define mmNIC4_QM1_CQ_PTR_HI_STS_0 0xDE21D8 + +#define mmNIC4_QM1_CQ_PTR_HI_STS_1 0xDE21DC + +#define mmNIC4_QM1_CQ_PTR_HI_STS_2 0xDE21E0 + +#define mmNIC4_QM1_CQ_PTR_HI_STS_3 0xDE21E4 + +#define mmNIC4_QM1_CQ_PTR_HI_STS_4 0xDE21E8 + +#define mmNIC4_QM1_CQ_TSIZE_STS_0 0xDE21EC + +#define mmNIC4_QM1_CQ_TSIZE_STS_1 0xDE21F0 + +#define mmNIC4_QM1_CQ_TSIZE_STS_2 0xDE21F4 + +#define mmNIC4_QM1_CQ_TSIZE_STS_3 0xDE21F8 + +#define mmNIC4_QM1_CQ_TSIZE_STS_4 0xDE21FC + +#define mmNIC4_QM1_CQ_CTL_STS_0 0xDE2200 + +#define mmNIC4_QM1_CQ_CTL_STS_1 0xDE2204 + +#define mmNIC4_QM1_CQ_CTL_STS_2 0xDE2208 + +#define mmNIC4_QM1_CQ_CTL_STS_3 0xDE220C + +#define mmNIC4_QM1_CQ_CTL_STS_4 0xDE2210 + +#define mmNIC4_QM1_CQ_IFIFO_CNT_0 0xDE2214 + +#define mmNIC4_QM1_CQ_IFIFO_CNT_1 0xDE2218 + +#define mmNIC4_QM1_CQ_IFIFO_CNT_2 0xDE221C + +#define mmNIC4_QM1_CQ_IFIFO_CNT_3 0xDE2220 + +#define mmNIC4_QM1_CQ_IFIFO_CNT_4 0xDE2224 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDE2228 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDE222C + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDE2230 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDE2234 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDE2238 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDE223C + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDE2240 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDE2244 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDE2248 + +#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDE224C + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDE2250 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDE2254 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDE2258 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDE225C + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDE2260 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDE2264 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDE2268 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDE226C + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDE2270 + +#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDE2274 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDE2278 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDE227C + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDE2280 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDE2284 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDE2288 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDE228C + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDE2290 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDE2294 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDE2298 + +#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDE229C + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDE22A0 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDE22A4 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDE22A8 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDE22AC + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDE22B0 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDE22B4 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDE22B8 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDE22BC + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDE22C0 + +#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDE22C4 + +#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDE22C8 + +#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDE22CC + +#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDE22D0 + +#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDE22D4 + +#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDE22D8 + +#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE22E0 + +#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE22E4 + +#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE22E8 + +#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE22EC + +#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE22F0 + +#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE22F4 + +#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE22F8 + +#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE22FC + +#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE2300 + +#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE2304 + +#define mmNIC4_QM1_CP_FENCE0_RDATA_0 0xDE2308 + +#define mmNIC4_QM1_CP_FENCE0_RDATA_1 0xDE230C + +#define mmNIC4_QM1_CP_FENCE0_RDATA_2 0xDE2310 + +#define mmNIC4_QM1_CP_FENCE0_RDATA_3 0xDE2314 + +#define mmNIC4_QM1_CP_FENCE0_RDATA_4 0xDE2318 + +#define mmNIC4_QM1_CP_FENCE1_RDATA_0 0xDE231C + +#define mmNIC4_QM1_CP_FENCE1_RDATA_1 0xDE2320 + +#define mmNIC4_QM1_CP_FENCE1_RDATA_2 0xDE2324 + +#define mmNIC4_QM1_CP_FENCE1_RDATA_3 0xDE2328 + +#define mmNIC4_QM1_CP_FENCE1_RDATA_4 0xDE232C + +#define mmNIC4_QM1_CP_FENCE2_RDATA_0 0xDE2330 + +#define mmNIC4_QM1_CP_FENCE2_RDATA_1 0xDE2334 + +#define mmNIC4_QM1_CP_FENCE2_RDATA_2 0xDE2338 + +#define mmNIC4_QM1_CP_FENCE2_RDATA_3 0xDE233C + +#define mmNIC4_QM1_CP_FENCE2_RDATA_4 0xDE2340 + +#define mmNIC4_QM1_CP_FENCE3_RDATA_0 0xDE2344 + +#define mmNIC4_QM1_CP_FENCE3_RDATA_1 0xDE2348 + +#define mmNIC4_QM1_CP_FENCE3_RDATA_2 0xDE234C + +#define mmNIC4_QM1_CP_FENCE3_RDATA_3 0xDE2350 + +#define mmNIC4_QM1_CP_FENCE3_RDATA_4 0xDE2354 + +#define mmNIC4_QM1_CP_FENCE0_CNT_0 0xDE2358 + +#define mmNIC4_QM1_CP_FENCE0_CNT_1 0xDE235C + +#define mmNIC4_QM1_CP_FENCE0_CNT_2 0xDE2360 + +#define mmNIC4_QM1_CP_FENCE0_CNT_3 0xDE2364 + +#define mmNIC4_QM1_CP_FENCE0_CNT_4 0xDE2368 + +#define mmNIC4_QM1_CP_FENCE1_CNT_0 0xDE236C + +#define mmNIC4_QM1_CP_FENCE1_CNT_1 0xDE2370 + +#define mmNIC4_QM1_CP_FENCE1_CNT_2 0xDE2374 + +#define mmNIC4_QM1_CP_FENCE1_CNT_3 0xDE2378 + +#define mmNIC4_QM1_CP_FENCE1_CNT_4 0xDE237C + +#define mmNIC4_QM1_CP_FENCE2_CNT_0 0xDE2380 + +#define mmNIC4_QM1_CP_FENCE2_CNT_1 0xDE2384 + +#define mmNIC4_QM1_CP_FENCE2_CNT_2 0xDE2388 + +#define mmNIC4_QM1_CP_FENCE2_CNT_3 0xDE238C + +#define mmNIC4_QM1_CP_FENCE2_CNT_4 0xDE2390 + +#define mmNIC4_QM1_CP_FENCE3_CNT_0 0xDE2394 + +#define mmNIC4_QM1_CP_FENCE3_CNT_1 0xDE2398 + +#define mmNIC4_QM1_CP_FENCE3_CNT_2 0xDE239C + +#define mmNIC4_QM1_CP_FENCE3_CNT_3 0xDE23A0 + +#define mmNIC4_QM1_CP_FENCE3_CNT_4 0xDE23A4 + +#define mmNIC4_QM1_CP_STS_0 0xDE23A8 + +#define mmNIC4_QM1_CP_STS_1 0xDE23AC + +#define mmNIC4_QM1_CP_STS_2 0xDE23B0 + +#define mmNIC4_QM1_CP_STS_3 0xDE23B4 + +#define mmNIC4_QM1_CP_STS_4 0xDE23B8 + +#define mmNIC4_QM1_CP_CURRENT_INST_LO_0 0xDE23BC + +#define mmNIC4_QM1_CP_CURRENT_INST_LO_1 0xDE23C0 + +#define mmNIC4_QM1_CP_CURRENT_INST_LO_2 0xDE23C4 + +#define mmNIC4_QM1_CP_CURRENT_INST_LO_3 0xDE23C8 + +#define mmNIC4_QM1_CP_CURRENT_INST_LO_4 0xDE23CC + +#define mmNIC4_QM1_CP_CURRENT_INST_HI_0 0xDE23D0 + +#define mmNIC4_QM1_CP_CURRENT_INST_HI_1 0xDE23D4 + +#define mmNIC4_QM1_CP_CURRENT_INST_HI_2 0xDE23D8 + +#define mmNIC4_QM1_CP_CURRENT_INST_HI_3 0xDE23DC + +#define mmNIC4_QM1_CP_CURRENT_INST_HI_4 0xDE23E0 + +#define mmNIC4_QM1_CP_BARRIER_CFG_0 0xDE23F4 + +#define mmNIC4_QM1_CP_BARRIER_CFG_1 0xDE23F8 + +#define mmNIC4_QM1_CP_BARRIER_CFG_2 0xDE23FC + +#define mmNIC4_QM1_CP_BARRIER_CFG_3 0xDE2400 + +#define mmNIC4_QM1_CP_BARRIER_CFG_4 0xDE2404 + +#define mmNIC4_QM1_CP_DBG_0_0 0xDE2408 + +#define mmNIC4_QM1_CP_DBG_0_1 0xDE240C + +#define mmNIC4_QM1_CP_DBG_0_2 0xDE2410 + +#define mmNIC4_QM1_CP_DBG_0_3 0xDE2414 + +#define mmNIC4_QM1_CP_DBG_0_4 0xDE2418 + +#define mmNIC4_QM1_CP_ARUSER_31_11_0 0xDE241C + +#define mmNIC4_QM1_CP_ARUSER_31_11_1 0xDE2420 + +#define mmNIC4_QM1_CP_ARUSER_31_11_2 0xDE2424 + +#define mmNIC4_QM1_CP_ARUSER_31_11_3 0xDE2428 + +#define mmNIC4_QM1_CP_ARUSER_31_11_4 0xDE242C + +#define mmNIC4_QM1_CP_AWUSER_31_11_0 0xDE2430 + +#define mmNIC4_QM1_CP_AWUSER_31_11_1 0xDE2434 + +#define mmNIC4_QM1_CP_AWUSER_31_11_2 0xDE2438 + +#define mmNIC4_QM1_CP_AWUSER_31_11_3 0xDE243C + +#define mmNIC4_QM1_CP_AWUSER_31_11_4 0xDE2440 + +#define mmNIC4_QM1_ARB_CFG_0 0xDE2A00 + +#define mmNIC4_QM1_ARB_CHOISE_Q_PUSH 0xDE2A04 + +#define mmNIC4_QM1_ARB_WRR_WEIGHT_0 0xDE2A08 + +#define mmNIC4_QM1_ARB_WRR_WEIGHT_1 0xDE2A0C + +#define mmNIC4_QM1_ARB_WRR_WEIGHT_2 0xDE2A10 + +#define mmNIC4_QM1_ARB_WRR_WEIGHT_3 0xDE2A14 + +#define mmNIC4_QM1_ARB_CFG_1 0xDE2A18 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 0xDE2A20 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 0xDE2A24 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 0xDE2A28 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 0xDE2A2C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 0xDE2A30 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 0xDE2A34 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 0xDE2A38 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 0xDE2A3C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 0xDE2A40 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 0xDE2A44 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 0xDE2A48 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 0xDE2A4C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 0xDE2A50 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 0xDE2A54 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 0xDE2A58 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 0xDE2A5C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 0xDE2A60 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 0xDE2A64 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 0xDE2A68 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 0xDE2A6C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 0xDE2A70 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 0xDE2A74 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 0xDE2A78 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 0xDE2A7C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 0xDE2A80 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 0xDE2A84 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 0xDE2A88 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 0xDE2A8C + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 0xDE2A90 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 0xDE2A94 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 0xDE2A98 + +#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 0xDE2A9C + +#define mmNIC4_QM1_ARB_MST_CRED_INC 0xDE2AA0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDE2AA4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDE2AA8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDE2AAC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDE2AB0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDE2AB4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDE2AB8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDE2ABC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDE2AC0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDE2AC4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDE2AC8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDE2ACC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDE2AD0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDE2AD4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDE2AD8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDE2ADC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDE2AE0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDE2AE4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDE2AE8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDE2AEC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDE2AF0 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDE2AF4 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDE2AF8 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDE2AFC + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDE2B00 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDE2B04 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDE2B08 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDE2B0C + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDE2B10 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDE2B14 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDE2B18 + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDE2B1C + +#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDE2B20 + +#define mmNIC4_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDE2B28 + +#define mmNIC4_QM1_ARB_MST_SLAVE_EN 0xDE2B2C + +#define mmNIC4_QM1_ARB_MST_QUIET_PER 0xDE2B34 + +#define mmNIC4_QM1_ARB_SLV_CHOISE_WDT 0xDE2B38 + +#define mmNIC4_QM1_ARB_SLV_ID 0xDE2B3C + +#define mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT 0xDE2B44 + +#define mmNIC4_QM1_ARB_MSG_AWUSER_31_11 0xDE2B48 + +#define mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDE2B4C + +#define mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE2B50 + +#define mmNIC4_QM1_ARB_BASE_LO 0xDE2B54 + +#define mmNIC4_QM1_ARB_BASE_HI 0xDE2B58 + +#define mmNIC4_QM1_ARB_STATE_STS 0xDE2B80 + +#define mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS 0xDE2B84 + +#define mmNIC4_QM1_ARB_MSG_STS 0xDE2B88 + +#define mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDE2B8C + +#define mmNIC4_QM1_ARB_ERR_CAUSE 0xDE2B9C + +#define mmNIC4_QM1_ARB_ERR_MSG_EN 0xDE2BA0 + +#define mmNIC4_QM1_ARB_ERR_STS_DRP 0xDE2BA8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_0 0xDE2BB0 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_1 0xDE2BB4 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_2 0xDE2BB8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_3 0xDE2BBC + +#define mmNIC4_QM1_ARB_MST_CRED_STS_4 0xDE2BC0 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_5 0xDE2BC4 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_6 0xDE2BC8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_7 0xDE2BCC + +#define mmNIC4_QM1_ARB_MST_CRED_STS_8 0xDE2BD0 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_9 0xDE2BD4 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_10 0xDE2BD8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_11 0xDE2BDC + +#define mmNIC4_QM1_ARB_MST_CRED_STS_12 0xDE2BE0 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_13 0xDE2BE4 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_14 0xDE2BE8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_15 0xDE2BEC + +#define mmNIC4_QM1_ARB_MST_CRED_STS_16 0xDE2BF0 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_17 0xDE2BF4 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_18 0xDE2BF8 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_19 0xDE2BFC + +#define mmNIC4_QM1_ARB_MST_CRED_STS_20 0xDE2C00 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_21 0xDE2C04 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_22 0xDE2C08 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_23 0xDE2C0C + +#define mmNIC4_QM1_ARB_MST_CRED_STS_24 0xDE2C10 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_25 0xDE2C14 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_26 0xDE2C18 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_27 0xDE2C1C + +#define mmNIC4_QM1_ARB_MST_CRED_STS_28 0xDE2C20 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_29 0xDE2C24 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_30 0xDE2C28 + +#define mmNIC4_QM1_ARB_MST_CRED_STS_31 0xDE2C2C + +#define mmNIC4_QM1_CGM_CFG 0xDE2C70 + +#define mmNIC4_QM1_CGM_STS 0xDE2C74 + +#define mmNIC4_QM1_CGM_CFG1 0xDE2C78 + +#define mmNIC4_QM1_LOCAL_RANGE_BASE 0xDE2C80 + +#define mmNIC4_QM1_LOCAL_RANGE_SIZE 0xDE2C84 + +#define mmNIC4_QM1_CSMR_STRICT_PRIO_CFG 0xDE2C90 + +#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 0xDE2C94 + +#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 0xDE2C98 + +#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 0xDE2C9C + +#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 0xDE2CA0 + +#define mmNIC4_QM1_GLBL_AXCACHE 0xDE2CA4 + +#define mmNIC4_QM1_IND_GW_APB_CFG 0xDE2CB0 + +#define mmNIC4_QM1_IND_GW_APB_WDATA 0xDE2CB4 + +#define mmNIC4_QM1_IND_GW_APB_RDATA 0xDE2CB8 + +#define mmNIC4_QM1_IND_GW_APB_STATUS 0xDE2CBC + +#define mmNIC4_QM1_GLBL_ERR_ADDR_LO 0xDE2CD0 + +#define mmNIC4_QM1_GLBL_ERR_ADDR_HI 0xDE2CD4 + +#define mmNIC4_QM1_GLBL_ERR_WDATA 0xDE2CD8 + +#define mmNIC4_QM1_GLBL_MEM_INIT_BUSY 0xDE2D00 + +#endif /* ASIC_REG_NIC4_QM1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000..2efa2a54d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_0_PERM_SEL 0x386108 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_0 0x386114 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_1 0x386118 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_2 0x38611C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_3 0x386120 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_4 0x386124 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_5 0x386128 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_6 0x38612C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_7 0x386130 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_8 0x386134 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_9 0x386138 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_10 0x38613C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_11 0x386140 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_12 0x386144 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_13 0x386148 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_14 0x38614C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_15 0x386150 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_16 0x386154 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_17 0x386158 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_18 0x38615C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_19 0x386160 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_20 0x386164 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_21 0x386168 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_22 0x38616C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_23 0x386170 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_24 0x386174 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_25 0x386178 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_26 0x38617C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_27 0x386180 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x386184 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x386188 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x38618C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x386190 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x386194 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x386198 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x38619C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3861A0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3861A4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3861A8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3861AC + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3861B0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3861B4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3861B8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3861BC + +#define mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x38626C + +#define mmNIF_RTR_CTRL_0_RL_HBM_EN 0x386274 + +#define mmNIF_RTR_CTRL_0_RL_HBM_SAT 0x386278 + +#define mmNIF_RTR_CTRL_0_RL_HBM_RST 0x38627C + +#define mmNIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x386280 + +#define mmNIF_RTR_CTRL_0_SCRAM_HBM_EN 0x386284 + +#define mmNIF_RTR_CTRL_0_RL_PCI_EN 0x386288 + +#define mmNIF_RTR_CTRL_0_RL_PCI_SAT 0x38628C + +#define mmNIF_RTR_CTRL_0_RL_PCI_RST 0x386290 + +#define mmNIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x386294 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_EN 0x38629C + +#define mmNIF_RTR_CTRL_0_RL_SRAM_SAT 0x3862A0 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RST 0x3862A4 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3862AC + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RED 0x3862B4 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_EN 0x3862EC + +#define mmNIF_RTR_CTRL_0_E2E_PCI_EN 0x3862F0 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3862F4 + +#define mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3862F8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x386404 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x386408 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x38640C + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x386410 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x386414 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x386418 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x38641C + +#define mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x386420 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x386424 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x386428 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x38642C + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x386430 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x386434 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x386438 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_0 0x386450 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_1 0x386454 + +#define mmNIF_RTR_CTRL_0_NON_LIN_EN 0x386480 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x386500 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x386504 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x386508 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x38650C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x386510 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x386514 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x386520 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x386524 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x386528 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x38652C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x386530 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x386534 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x386538 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x38653C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x386540 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x386550 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x386554 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x386558 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x38655C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x386560 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x386564 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x386568 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x38656C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x386570 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x386574 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x386578 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x38657C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x386580 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x386584 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x386588 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x38658C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x386590 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x386594 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x386598 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3865E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3865E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3865EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3865F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3865F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3865F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3865FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x386600 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x386604 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x386608 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x38660C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x386610 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x386614 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x386618 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x38661C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x386620 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x386624 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x386628 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x38662C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x386630 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x386634 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x386638 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x38663C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x386640 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x386644 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x386648 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x38664C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x386650 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x386654 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x386658 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x38665C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x386660 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x386664 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x386668 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x38666C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x386670 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x386674 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x386678 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x38667C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x386680 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x386684 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x386688 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x38668C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x386690 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x386694 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x386698 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x38669C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3866A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3866A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3866A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3866AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3866B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3866B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3866B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3866BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3866C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3866C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3866C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3866CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3866D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3866D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3866D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3866DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3866E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3866E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3866E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3866EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3866F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3866F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3866F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3866FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x386700 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x386704 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x386708 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x38670C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x386710 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x386714 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x386718 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x38671C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x386720 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x386724 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x386728 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x38672C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x386730 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x386734 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x386738 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x38673C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x386740 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x386744 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x386748 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x38674C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x386750 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x386754 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x386758 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x38675C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x386760 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x386764 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x386768 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x38676C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x386770 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x386774 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x386778 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x38677C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x386780 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x386784 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x386788 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x38678C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x386790 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x386794 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x386798 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x38679C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3867A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3867A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3867A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3867AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3867B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3867B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3867B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3867BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3867C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3867C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3867C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3867CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3867D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3867D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3867D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3867DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3867E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x386824 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x386828 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x38682C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x386830 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x386834 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x386838 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x38683C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x386840 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x386844 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x386848 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x38684C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x386850 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x386854 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x386858 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x38685C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x386860 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x386864 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x386868 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x38686C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x386870 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x386874 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x386878 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x38687C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x386880 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x386884 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x386888 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x38688C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x386890 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x386894 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x386898 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x38689C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3868A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3868A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3868A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3868AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3868B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3868B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3868B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3868BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3868C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3868C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3868C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3868CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3868D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3868D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3868D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3868DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3868E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3868E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3868E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3868EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3868F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3868F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3868F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3868FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x386900 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x386904 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x386908 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x38690C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x386910 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x386914 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x386918 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x38691C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x386920 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x386924 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x386928 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x38692C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x386930 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x386934 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x386938 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x38693C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x386940 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x386944 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x386948 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x38694C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x386950 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x386954 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x386958 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x38695C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x386960 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x386964 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x386968 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x38696C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x386970 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x386974 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x386978 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x38697C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x386980 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x386984 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x386988 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x38698C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x386990 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x386994 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x386998 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x38699C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3869A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3869A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3869A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3869AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3869B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3869B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3869B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3869BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3869C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3869C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3869C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3869CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3869D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3869D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3869D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3869DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3869E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3869E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3869E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3869EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3869F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3869F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3869F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3869FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x386A00 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x386A04 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x386A08 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x386A0C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x386A10 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x386A14 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x386A18 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x386A1C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x386A20 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x386A64 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x386A68 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x386A6C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x386A70 + +#define mmNIF_RTR_CTRL_0_RGL_CFG 0x386B64 + +#define mmNIF_RTR_CTRL_0_RGL_SHIFT 0x386B68 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x386B6C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x386B70 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x386B74 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x386B78 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x386B7C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x386B80 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x386B84 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x386B88 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_0 0x386BAC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_1 0x386BB0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_2 0x386BB4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_3 0x386BB8 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_4 0x386BBC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_5 0x386BC0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_6 0x386BC4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_7 0x386BC8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_0 0x386BEC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_1 0x386BF0 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_2 0x386BF4 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_3 0x386BF8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_4 0x386BFC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_5 0x386C00 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_6 0x386C04 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_7 0x386C08 + +#define mmNIF_RTR_CTRL_0_RGL_WDT 0x386C2C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x386C30 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x386C34 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x386C38 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x386C3C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x386C40 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x386C44 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x386C48 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x386C4C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x386C50 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x386C54 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x386C58 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x386C5C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x386C60 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x386C64 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x386C68 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x386C6C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x386C70 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x386C74 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x386C78 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x386C7C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x386C80 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x386C84 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x386C88 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x386C8C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x386C90 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x386C94 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x386C98 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x386C9C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x386CA0 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x386CA4 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x386CA8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x386CAC + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x386CB0 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x386CB4 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x386CB8 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x386CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000..a6047d4e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_1_PERM_SEL 0x396108 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_0 0x396114 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_1 0x396118 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_2 0x39611C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_3 0x396120 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_4 0x396124 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_5 0x396128 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_6 0x39612C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_7 0x396130 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_8 0x396134 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_9 0x396138 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_10 0x39613C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_11 0x396140 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_12 0x396144 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_13 0x396148 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_14 0x39614C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_15 0x396150 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_16 0x396154 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_17 0x396158 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_18 0x39615C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_19 0x396160 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_20 0x396164 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_21 0x396168 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_22 0x39616C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_23 0x396170 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_24 0x396174 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_25 0x396178 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_26 0x39617C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_27 0x396180 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x396184 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x396188 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x39618C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x396190 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x396194 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x396198 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x39619C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3961A0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3961A4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3961A8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3961AC + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3961B0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3961B4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3961B8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3961BC + +#define mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x39626C + +#define mmNIF_RTR_CTRL_1_RL_HBM_EN 0x396274 + +#define mmNIF_RTR_CTRL_1_RL_HBM_SAT 0x396278 + +#define mmNIF_RTR_CTRL_1_RL_HBM_RST 0x39627C + +#define mmNIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x396280 + +#define mmNIF_RTR_CTRL_1_SCRAM_HBM_EN 0x396284 + +#define mmNIF_RTR_CTRL_1_RL_PCI_EN 0x396288 + +#define mmNIF_RTR_CTRL_1_RL_PCI_SAT 0x39628C + +#define mmNIF_RTR_CTRL_1_RL_PCI_RST 0x396290 + +#define mmNIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x396294 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_EN 0x39629C + +#define mmNIF_RTR_CTRL_1_RL_SRAM_SAT 0x3962A0 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RST 0x3962A4 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3962AC + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RED 0x3962B4 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_EN 0x3962EC + +#define mmNIF_RTR_CTRL_1_E2E_PCI_EN 0x3962F0 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3962F4 + +#define mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3962F8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x396404 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x396408 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x39640C + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x396410 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x396414 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x396418 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x39641C + +#define mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x396420 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x396424 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x396428 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x39642C + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x396430 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x396434 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x396438 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_0 0x396450 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_1 0x396454 + +#define mmNIF_RTR_CTRL_1_NON_LIN_EN 0x396480 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x396500 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x396504 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x396508 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x39650C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x396510 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x396514 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x396520 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x396524 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x396528 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x39652C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x396530 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x396534 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x396538 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x39653C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x396540 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x396550 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x396554 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x396558 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x39655C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x396560 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x396564 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x396568 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x39656C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x396570 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x396574 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x396578 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x39657C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x396580 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x396584 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x396588 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x39658C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x396590 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x396594 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x396598 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3965E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3965E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3965EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3965F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3965F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3965F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3965FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x396600 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x396604 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x396608 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x39660C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x396610 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x396614 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x396618 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x39661C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x396620 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x396624 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x396628 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x39662C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x396630 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x396634 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x396638 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x39663C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x396640 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x396644 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x396648 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x39664C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x396650 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x396654 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x396658 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x39665C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x396660 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x396664 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x396668 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x39666C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x396670 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x396674 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x396678 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x39667C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x396680 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x396684 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x396688 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x39668C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x396690 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x396694 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x396698 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x39669C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3966A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3966A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3966A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3966AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3966B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3966B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3966B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3966BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3966C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3966C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3966C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3966CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3966D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3966D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3966D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3966DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3966E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3966E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3966E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3966EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3966F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3966F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3966F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3966FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x396700 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x396704 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x396708 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x39670C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x396710 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x396714 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x396718 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x39671C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x396720 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x396724 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x396728 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x39672C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x396730 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x396734 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x396738 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x39673C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x396740 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x396744 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x396748 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x39674C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x396750 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x396754 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x396758 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x39675C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x396760 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x396764 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x396768 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x39676C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x396770 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x396774 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x396778 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x39677C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x396780 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x396784 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x396788 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x39678C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x396790 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x396794 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x396798 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x39679C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3967A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3967A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3967A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3967AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3967B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3967B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3967B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3967BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3967C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3967C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3967C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3967CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3967D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3967D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3967D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3967DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3967E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x396824 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x396828 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x39682C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x396830 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x396834 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x396838 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x39683C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x396840 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x396844 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x396848 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x39684C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x396850 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x396854 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x396858 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x39685C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x396860 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x396864 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x396868 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x39686C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x396870 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x396874 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x396878 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x39687C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x396880 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x396884 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x396888 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x39688C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x396890 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x396894 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x396898 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x39689C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3968A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3968A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3968A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3968AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3968B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3968B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3968B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3968BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3968C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3968C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3968C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3968CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3968D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3968D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3968D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3968DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3968E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3968E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3968E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3968EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3968F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3968F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3968F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3968FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x396900 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x396904 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x396908 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x39690C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x396910 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x396914 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x396918 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x39691C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x396920 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x396924 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x396928 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x39692C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x396930 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x396934 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x396938 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x39693C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x396940 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x396944 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x396948 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x39694C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x396950 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x396954 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x396958 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x39695C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x396960 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x396964 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x396968 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x39696C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x396970 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x396974 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x396978 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x39697C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x396980 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x396984 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x396988 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x39698C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x396990 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x396994 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x396998 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x39699C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3969A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3969A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3969A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3969AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3969B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3969B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3969B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3969BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3969C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3969C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3969C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3969CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3969D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3969D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3969D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3969DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3969E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3969E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3969E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3969EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3969F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3969F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3969F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3969FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x396A00 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x396A04 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x396A08 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x396A0C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x396A10 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x396A14 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x396A18 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x396A1C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x396A20 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x396A64 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x396A68 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x396A6C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x396A70 + +#define mmNIF_RTR_CTRL_1_RGL_CFG 0x396B64 + +#define mmNIF_RTR_CTRL_1_RGL_SHIFT 0x396B68 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x396B6C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x396B70 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x396B74 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x396B78 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x396B7C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x396B80 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x396B84 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x396B88 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_0 0x396BAC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_1 0x396BB0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_2 0x396BB4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_3 0x396BB8 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_4 0x396BBC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_5 0x396BC0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_6 0x396BC4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_7 0x396BC8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_0 0x396BEC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_1 0x396BF0 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_2 0x396BF4 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_3 0x396BF8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_4 0x396BFC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_5 0x396C00 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_6 0x396C04 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_7 0x396C08 + +#define mmNIF_RTR_CTRL_1_RGL_WDT 0x396C2C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x396C30 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x396C34 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x396C38 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x396C3C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x396C40 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x396C44 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x396C48 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x396C4C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x396C50 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x396C54 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x396C58 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x396C5C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x396C60 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x396C64 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x396C68 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x396C6C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x396C70 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x396C74 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x396C78 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x396C7C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x396C80 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x396C84 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x396C88 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x396C8C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x396C90 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x396C94 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x396C98 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x396C9C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x396CA0 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x396CA4 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x396CA8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x396CAC + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x396CB0 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x396CB4 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x396CB8 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x396CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000..9de8442f9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_2_PERM_SEL 0x3A6108 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0 0x3A6114 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1 0x3A6118 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2 0x3A611C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3 0x3A6120 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4 0x3A6124 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5 0x3A6128 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6 0x3A612C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7 0x3A6130 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8 0x3A6134 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9 0x3A6138 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10 0x3A613C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11 0x3A6140 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12 0x3A6144 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13 0x3A6148 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14 0x3A614C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15 0x3A6150 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16 0x3A6154 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17 0x3A6158 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18 0x3A615C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19 0x3A6160 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20 0x3A6164 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21 0x3A6168 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22 0x3A616C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23 0x3A6170 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24 0x3A6174 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25 0x3A6178 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26 0x3A617C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27 0x3A6180 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x3A6184 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x3A6188 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x3A618C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x3A6190 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x3A6194 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x3A6198 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x3A619C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3A61A0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3A61A4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3A61A8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3A61AC + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3A61B0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3A61B4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3A61B8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3A61BC + +#define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x3A626C + +#define mmNIF_RTR_CTRL_2_RL_HBM_EN 0x3A6274 + +#define mmNIF_RTR_CTRL_2_RL_HBM_SAT 0x3A6278 + +#define mmNIF_RTR_CTRL_2_RL_HBM_RST 0x3A627C + +#define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x3A6280 + +#define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN 0x3A6284 + +#define mmNIF_RTR_CTRL_2_RL_PCI_EN 0x3A6288 + +#define mmNIF_RTR_CTRL_2_RL_PCI_SAT 0x3A628C + +#define mmNIF_RTR_CTRL_2_RL_PCI_RST 0x3A6290 + +#define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x3A6294 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_EN 0x3A629C + +#define mmNIF_RTR_CTRL_2_RL_SRAM_SAT 0x3A62A0 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RST 0x3A62A4 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3A62AC + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RED 0x3A62B4 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_EN 0x3A62EC + +#define mmNIF_RTR_CTRL_2_E2E_PCI_EN 0x3A62F0 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3A62F4 + +#define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3A62F8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x3A6404 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x3A6408 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x3A640C + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x3A6410 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x3A6414 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x3A6418 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x3A641C + +#define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x3A6420 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x3A6424 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x3A6428 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x3A642C + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x3A6430 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x3A6434 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x3A6438 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0 0x3A6450 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1 0x3A6454 + +#define mmNIF_RTR_CTRL_2_NON_LIN_EN 0x3A6480 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x3A6500 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x3A6504 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x3A6508 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x3A650C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x3A6510 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x3A6514 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x3A6520 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x3A6524 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x3A6528 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x3A652C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x3A6530 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x3A6534 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x3A6538 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x3A653C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x3A6540 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x3A6550 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x3A6554 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x3A6558 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x3A655C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x3A6560 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x3A6564 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x3A6568 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x3A656C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x3A6570 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x3A6574 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x3A6578 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x3A657C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x3A6580 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x3A6584 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x3A6588 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x3A658C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x3A6590 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x3A6594 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x3A6598 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3A65E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3A65E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3A65EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3A65F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3A65F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3A65F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3A65FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x3A6600 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x3A6604 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x3A6608 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x3A660C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x3A6610 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x3A6614 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x3A6618 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x3A661C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x3A6620 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x3A6624 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x3A6628 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x3A662C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x3A6630 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x3A6634 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x3A6638 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x3A663C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x3A6640 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x3A6644 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x3A6648 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x3A664C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x3A6650 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x3A6654 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x3A6658 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x3A665C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x3A6660 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x3A6664 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x3A6668 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x3A666C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x3A6670 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x3A6674 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x3A6678 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x3A667C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x3A6680 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x3A6684 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x3A6688 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x3A668C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x3A6690 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x3A6694 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x3A6698 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x3A669C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3A66A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3A66A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3A66A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3A66AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3A66B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3A66B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3A66B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3A66BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3A66C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3A66C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3A66C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3A66CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3A66D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3A66D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3A66D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3A66DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3A66E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3A66E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3A66E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3A66EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3A66F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3A66F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3A66F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3A66FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x3A6700 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x3A6704 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x3A6708 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x3A670C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x3A6710 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x3A6714 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x3A6718 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x3A671C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x3A6720 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x3A6724 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x3A6728 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x3A672C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x3A6730 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x3A6734 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x3A6738 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x3A673C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x3A6740 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x3A6744 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x3A6748 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x3A674C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x3A6750 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x3A6754 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x3A6758 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x3A675C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x3A6760 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x3A6764 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x3A6768 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x3A676C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x3A6770 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x3A6774 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x3A6778 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x3A677C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x3A6780 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x3A6784 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x3A6788 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x3A678C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x3A6790 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x3A6794 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x3A6798 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x3A679C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3A67A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3A67A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3A67A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3A67AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3A67B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3A67B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3A67B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3A67BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3A67C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3A67C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3A67C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3A67CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3A67D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3A67D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3A67D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3A67DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3A67E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x3A6824 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x3A6828 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x3A682C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x3A6830 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x3A6834 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x3A6838 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x3A683C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x3A6840 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x3A6844 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x3A6848 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x3A684C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x3A6850 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x3A6854 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x3A6858 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x3A685C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x3A6860 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x3A6864 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x3A6868 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x3A686C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x3A6870 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x3A6874 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x3A6878 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x3A687C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x3A6880 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x3A6884 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x3A6888 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x3A688C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x3A6890 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x3A6894 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x3A6898 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x3A689C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3A68A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3A68A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3A68A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3A68AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3A68B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3A68B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3A68B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3A68BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3A68C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3A68C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3A68C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3A68CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3A68D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3A68D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3A68D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3A68DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3A68E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3A68E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3A68E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3A68EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3A68F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3A68F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3A68F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3A68FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x3A6900 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x3A6904 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x3A6908 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x3A690C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x3A6910 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x3A6914 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x3A6918 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x3A691C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x3A6920 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x3A6924 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x3A6928 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x3A692C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x3A6930 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x3A6934 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x3A6938 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x3A693C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x3A6940 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x3A6944 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x3A6948 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x3A694C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x3A6950 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x3A6954 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x3A6958 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x3A695C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x3A6960 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x3A6964 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x3A6968 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x3A696C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x3A6970 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x3A6974 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x3A6978 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x3A697C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x3A6980 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x3A6984 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x3A6988 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x3A698C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x3A6990 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x3A6994 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x3A6998 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x3A699C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3A69A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3A69A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3A69A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3A69AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3A69B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3A69B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3A69B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3A69BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3A69C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3A69C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3A69C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3A69CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3A69D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3A69D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3A69D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3A69DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3A69E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3A69E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3A69E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3A69EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3A69F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3A69F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3A69F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3A69FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x3A6A00 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x3A6A04 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x3A6A08 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x3A6A0C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x3A6A10 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x3A6A14 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x3A6A18 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x3A6A1C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x3A6A20 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x3A6A64 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x3A6A68 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x3A6A6C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x3A6A70 + +#define mmNIF_RTR_CTRL_2_RGL_CFG 0x3A6B64 + +#define mmNIF_RTR_CTRL_2_RGL_SHIFT 0x3A6B68 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x3A6B6C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x3A6B70 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x3A6B74 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x3A6B78 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x3A6B7C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x3A6B80 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x3A6B84 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x3A6B88 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_0 0x3A6BAC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_1 0x3A6BB0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_2 0x3A6BB4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_3 0x3A6BB8 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_4 0x3A6BBC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_5 0x3A6BC0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_6 0x3A6BC4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_7 0x3A6BC8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0 0x3A6BEC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1 0x3A6BF0 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2 0x3A6BF4 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3 0x3A6BF8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4 0x3A6BFC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5 0x3A6C00 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6 0x3A6C04 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7 0x3A6C08 + +#define mmNIF_RTR_CTRL_2_RGL_WDT 0x3A6C2C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x3A6C30 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x3A6C34 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x3A6C38 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x3A6C3C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x3A6C40 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x3A6C44 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x3A6C48 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x3A6C4C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x3A6C50 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x3A6C54 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x3A6C58 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x3A6C5C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x3A6C60 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x3A6C64 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x3A6C68 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x3A6C6C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x3A6C70 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x3A6C74 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x3A6C78 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x3A6C7C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x3A6C80 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x3A6C84 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x3A6C88 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x3A6C8C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x3A6C90 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x3A6C94 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x3A6C98 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x3A6C9C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x3A6CA0 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x3A6CA4 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x3A6CA8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x3A6CAC + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x3A6CB0 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x3A6CB4 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x3A6CB8 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x3A6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000..34fd47685 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_3_PERM_SEL 0x3B6108 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_0 0x3B6114 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_1 0x3B6118 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_2 0x3B611C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_3 0x3B6120 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_4 0x3B6124 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_5 0x3B6128 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_6 0x3B612C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_7 0x3B6130 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_8 0x3B6134 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_9 0x3B6138 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_10 0x3B613C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_11 0x3B6140 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_12 0x3B6144 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_13 0x3B6148 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_14 0x3B614C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_15 0x3B6150 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_16 0x3B6154 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_17 0x3B6158 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_18 0x3B615C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_19 0x3B6160 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_20 0x3B6164 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_21 0x3B6168 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_22 0x3B616C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_23 0x3B6170 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_24 0x3B6174 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_25 0x3B6178 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_26 0x3B617C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_27 0x3B6180 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x3B6184 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x3B6188 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x3B618C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x3B6190 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x3B6194 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x3B6198 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x3B619C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3B61A0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3B61A4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3B61A8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3B61AC + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3B61B0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3B61B4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3B61B8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3B61BC + +#define mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x3B626C + +#define mmNIF_RTR_CTRL_3_RL_HBM_EN 0x3B6274 + +#define mmNIF_RTR_CTRL_3_RL_HBM_SAT 0x3B6278 + +#define mmNIF_RTR_CTRL_3_RL_HBM_RST 0x3B627C + +#define mmNIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x3B6280 + +#define mmNIF_RTR_CTRL_3_SCRAM_HBM_EN 0x3B6284 + +#define mmNIF_RTR_CTRL_3_RL_PCI_EN 0x3B6288 + +#define mmNIF_RTR_CTRL_3_RL_PCI_SAT 0x3B628C + +#define mmNIF_RTR_CTRL_3_RL_PCI_RST 0x3B6290 + +#define mmNIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x3B6294 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_EN 0x3B629C + +#define mmNIF_RTR_CTRL_3_RL_SRAM_SAT 0x3B62A0 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RST 0x3B62A4 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3B62AC + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RED 0x3B62B4 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_EN 0x3B62EC + +#define mmNIF_RTR_CTRL_3_E2E_PCI_EN 0x3B62F0 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3B62F4 + +#define mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3B62F8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x3B6404 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x3B6408 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x3B640C + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x3B6410 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x3B6414 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x3B6418 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x3B641C + +#define mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x3B6420 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x3B6424 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x3B6428 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x3B642C + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x3B6430 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x3B6434 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x3B6438 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_0 0x3B6450 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_1 0x3B6454 + +#define mmNIF_RTR_CTRL_3_NON_LIN_EN 0x3B6480 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x3B6500 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x3B6504 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x3B6508 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x3B650C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x3B6510 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x3B6514 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x3B6520 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x3B6524 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x3B6528 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x3B652C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x3B6530 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x3B6534 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x3B6538 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x3B653C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x3B6540 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x3B6550 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x3B6554 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x3B6558 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x3B655C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x3B6560 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x3B6564 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x3B6568 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x3B656C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x3B6570 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x3B6574 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x3B6578 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x3B657C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x3B6580 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x3B6584 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x3B6588 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x3B658C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x3B6590 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x3B6594 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x3B6598 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3B65E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3B65E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3B65EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3B65F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3B65F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3B65F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3B65FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x3B6600 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x3B6604 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x3B6608 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x3B660C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x3B6610 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x3B6614 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x3B6618 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x3B661C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x3B6620 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x3B6624 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x3B6628 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x3B662C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x3B6630 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x3B6634 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x3B6638 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x3B663C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x3B6640 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x3B6644 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x3B6648 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x3B664C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x3B6650 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x3B6654 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x3B6658 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x3B665C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x3B6660 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x3B6664 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x3B6668 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x3B666C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x3B6670 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x3B6674 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x3B6678 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x3B667C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x3B6680 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x3B6684 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x3B6688 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x3B668C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x3B6690 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x3B6694 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x3B6698 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x3B669C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3B66A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3B66A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3B66A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3B66AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3B66B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3B66B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3B66B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3B66BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3B66C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3B66C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3B66C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3B66CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3B66D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3B66D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3B66D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3B66DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3B66E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3B66E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3B66E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3B66EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3B66F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3B66F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3B66F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3B66FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x3B6700 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x3B6704 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x3B6708 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x3B670C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x3B6710 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x3B6714 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x3B6718 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x3B671C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x3B6720 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x3B6724 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x3B6728 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x3B672C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x3B6730 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x3B6734 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x3B6738 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x3B673C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x3B6740 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x3B6744 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x3B6748 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x3B674C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x3B6750 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x3B6754 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x3B6758 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x3B675C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x3B6760 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x3B6764 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x3B6768 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x3B676C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x3B6770 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x3B6774 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x3B6778 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x3B677C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x3B6780 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x3B6784 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x3B6788 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x3B678C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x3B6790 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x3B6794 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x3B6798 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x3B679C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3B67A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3B67A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3B67A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3B67AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3B67B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3B67B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3B67B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3B67BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3B67C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3B67C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3B67C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3B67CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3B67D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3B67D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3B67D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3B67DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3B67E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x3B6824 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x3B6828 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x3B682C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x3B6830 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x3B6834 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x3B6838 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x3B683C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x3B6840 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x3B6844 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x3B6848 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x3B684C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x3B6850 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x3B6854 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x3B6858 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x3B685C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x3B6860 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x3B6864 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x3B6868 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x3B686C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x3B6870 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x3B6874 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x3B6878 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x3B687C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x3B6880 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x3B6884 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x3B6888 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x3B688C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x3B6890 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x3B6894 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x3B6898 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x3B689C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3B68A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3B68A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3B68A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3B68AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3B68B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3B68B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3B68B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3B68BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3B68C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3B68C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3B68C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3B68CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3B68D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3B68D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3B68D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3B68DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3B68E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3B68E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3B68E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3B68EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3B68F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3B68F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3B68F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3B68FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x3B6900 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x3B6904 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x3B6908 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x3B690C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x3B6910 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x3B6914 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x3B6918 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x3B691C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x3B6920 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x3B6924 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x3B6928 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x3B692C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x3B6930 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x3B6934 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x3B6938 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x3B693C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x3B6940 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x3B6944 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x3B6948 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x3B694C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x3B6950 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x3B6954 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x3B6958 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x3B695C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x3B6960 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x3B6964 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x3B6968 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x3B696C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x3B6970 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x3B6974 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x3B6978 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x3B697C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x3B6980 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x3B6984 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x3B6988 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x3B698C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x3B6990 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x3B6994 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x3B6998 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x3B699C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3B69A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3B69A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3B69A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3B69AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3B69B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3B69B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3B69B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3B69BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3B69C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3B69C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3B69C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3B69CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3B69D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3B69D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3B69D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3B69DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3B69E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3B69E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3B69E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3B69EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3B69F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3B69F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3B69F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3B69FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x3B6A00 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x3B6A04 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x3B6A08 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x3B6A0C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x3B6A10 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x3B6A14 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x3B6A18 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x3B6A1C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x3B6A20 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x3B6A64 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x3B6A68 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x3B6A6C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x3B6A70 + +#define mmNIF_RTR_CTRL_3_RGL_CFG 0x3B6B64 + +#define mmNIF_RTR_CTRL_3_RGL_SHIFT 0x3B6B68 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x3B6B6C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x3B6B70 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x3B6B74 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x3B6B78 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x3B6B7C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x3B6B80 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x3B6B84 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x3B6B88 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_0 0x3B6BAC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_1 0x3B6BB0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_2 0x3B6BB4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_3 0x3B6BB8 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_4 0x3B6BBC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_5 0x3B6BC0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_6 0x3B6BC4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_7 0x3B6BC8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_0 0x3B6BEC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_1 0x3B6BF0 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_2 0x3B6BF4 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_3 0x3B6BF8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_4 0x3B6BFC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_5 0x3B6C00 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_6 0x3B6C04 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_7 0x3B6C08 + +#define mmNIF_RTR_CTRL_3_RGL_WDT 0x3B6C2C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x3B6C30 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x3B6C34 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x3B6C38 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x3B6C3C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x3B6C40 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x3B6C44 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x3B6C48 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x3B6C4C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x3B6C50 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x3B6C54 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x3B6C58 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x3B6C5C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x3B6C60 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x3B6C64 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x3B6C68 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x3B6C6C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x3B6C70 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x3B6C74 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x3B6C78 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x3B6C7C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x3B6C80 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x3B6C84 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x3B6C88 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x3B6C8C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x3B6C90 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x3B6C94 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x3B6C98 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x3B6C9C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x3B6CA0 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x3B6CA4 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x3B6CA8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x3B6CAC + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x3B6CB0 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x3B6CB4 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x3B6CB8 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x3B6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000..543a98f81 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_4_PERM_SEL 0x3C6108 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_0 0x3C6114 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_1 0x3C6118 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_2 0x3C611C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_3 0x3C6120 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_4 0x3C6124 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_5 0x3C6128 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_6 0x3C612C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_7 0x3C6130 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_8 0x3C6134 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_9 0x3C6138 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_10 0x3C613C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_11 0x3C6140 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_12 0x3C6144 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_13 0x3C6148 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_14 0x3C614C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_15 0x3C6150 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_16 0x3C6154 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_17 0x3C6158 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_18 0x3C615C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_19 0x3C6160 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_20 0x3C6164 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_21 0x3C6168 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_22 0x3C616C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_23 0x3C6170 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_24 0x3C6174 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_25 0x3C6178 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_26 0x3C617C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_27 0x3C6180 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x3C6184 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x3C6188 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x3C618C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x3C6190 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x3C6194 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x3C6198 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x3C619C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3C61A0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3C61A4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3C61A8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3C61AC + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3C61B0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3C61B4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3C61B8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3C61BC + +#define mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x3C626C + +#define mmNIF_RTR_CTRL_4_RL_HBM_EN 0x3C6274 + +#define mmNIF_RTR_CTRL_4_RL_HBM_SAT 0x3C6278 + +#define mmNIF_RTR_CTRL_4_RL_HBM_RST 0x3C627C + +#define mmNIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x3C6280 + +#define mmNIF_RTR_CTRL_4_SCRAM_HBM_EN 0x3C6284 + +#define mmNIF_RTR_CTRL_4_RL_PCI_EN 0x3C6288 + +#define mmNIF_RTR_CTRL_4_RL_PCI_SAT 0x3C628C + +#define mmNIF_RTR_CTRL_4_RL_PCI_RST 0x3C6290 + +#define mmNIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x3C6294 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_EN 0x3C629C + +#define mmNIF_RTR_CTRL_4_RL_SRAM_SAT 0x3C62A0 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RST 0x3C62A4 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3C62AC + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RED 0x3C62B4 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_EN 0x3C62EC + +#define mmNIF_RTR_CTRL_4_E2E_PCI_EN 0x3C62F0 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3C62F4 + +#define mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3C62F8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x3C6404 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x3C6408 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x3C640C + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x3C6410 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x3C6414 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x3C6418 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x3C641C + +#define mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x3C6420 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x3C6424 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x3C6428 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x3C642C + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x3C6430 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x3C6434 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x3C6438 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_0 0x3C6450 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_1 0x3C6454 + +#define mmNIF_RTR_CTRL_4_NON_LIN_EN 0x3C6480 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x3C6500 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x3C6504 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x3C6508 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x3C650C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x3C6510 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x3C6514 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x3C6520 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x3C6524 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x3C6528 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x3C652C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x3C6530 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x3C6534 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x3C6538 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x3C653C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x3C6540 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x3C6550 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x3C6554 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x3C6558 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x3C655C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x3C6560 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x3C6564 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x3C6568 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x3C656C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x3C6570 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x3C6574 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x3C6578 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x3C657C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x3C6580 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x3C6584 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x3C6588 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x3C658C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x3C6590 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x3C6594 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x3C6598 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3C65E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3C65E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3C65EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3C65F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3C65F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3C65F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3C65FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x3C6600 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x3C6604 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x3C6608 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x3C660C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x3C6610 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x3C6614 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x3C6618 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x3C661C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x3C6620 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x3C6624 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x3C6628 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x3C662C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x3C6630 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x3C6634 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x3C6638 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x3C663C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x3C6640 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x3C6644 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x3C6648 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x3C664C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x3C6650 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x3C6654 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x3C6658 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x3C665C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x3C6660 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x3C6664 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x3C6668 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x3C666C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x3C6670 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x3C6674 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x3C6678 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x3C667C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x3C6680 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x3C6684 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x3C6688 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x3C668C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x3C6690 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x3C6694 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x3C6698 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x3C669C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3C66A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3C66A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3C66A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3C66AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3C66B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3C66B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3C66B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3C66BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3C66C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3C66C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3C66C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3C66CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3C66D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3C66D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3C66D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3C66DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3C66E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3C66E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3C66E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3C66EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3C66F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3C66F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3C66F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3C66FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x3C6700 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x3C6704 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x3C6708 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x3C670C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x3C6710 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x3C6714 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x3C6718 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x3C671C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x3C6720 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x3C6724 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x3C6728 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x3C672C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x3C6730 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x3C6734 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x3C6738 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x3C673C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x3C6740 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x3C6744 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x3C6748 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x3C674C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x3C6750 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x3C6754 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x3C6758 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x3C675C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x3C6760 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x3C6764 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x3C6768 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x3C676C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x3C6770 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x3C6774 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x3C6778 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x3C677C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x3C6780 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x3C6784 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x3C6788 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x3C678C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x3C6790 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x3C6794 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x3C6798 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x3C679C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3C67A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3C67A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3C67A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3C67AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3C67B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3C67B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3C67B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3C67BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3C67C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3C67C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3C67C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3C67CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3C67D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3C67D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3C67D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3C67DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3C67E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x3C6824 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x3C6828 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x3C682C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x3C6830 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x3C6834 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x3C6838 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x3C683C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x3C6840 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x3C6844 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x3C6848 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x3C684C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x3C6850 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x3C6854 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x3C6858 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x3C685C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x3C6860 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x3C6864 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x3C6868 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x3C686C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x3C6870 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x3C6874 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x3C6878 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x3C687C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x3C6880 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x3C6884 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x3C6888 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x3C688C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x3C6890 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x3C6894 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x3C6898 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x3C689C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3C68A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3C68A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3C68A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3C68AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3C68B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3C68B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3C68B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3C68BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3C68C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3C68C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3C68C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3C68CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3C68D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3C68D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3C68D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3C68DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3C68E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3C68E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3C68E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3C68EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3C68F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3C68F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3C68F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3C68FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x3C6900 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x3C6904 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x3C6908 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x3C690C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x3C6910 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x3C6914 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x3C6918 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x3C691C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x3C6920 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x3C6924 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x3C6928 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x3C692C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x3C6930 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x3C6934 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x3C6938 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x3C693C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x3C6940 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x3C6944 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x3C6948 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x3C694C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x3C6950 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x3C6954 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x3C6958 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x3C695C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x3C6960 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x3C6964 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x3C6968 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x3C696C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x3C6970 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x3C6974 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x3C6978 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x3C697C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x3C6980 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x3C6984 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x3C6988 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x3C698C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x3C6990 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x3C6994 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x3C6998 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x3C699C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3C69A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3C69A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3C69A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3C69AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3C69B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3C69B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3C69B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3C69BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3C69C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3C69C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3C69C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3C69CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3C69D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3C69D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3C69D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3C69DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3C69E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3C69E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3C69E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3C69EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3C69F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3C69F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3C69F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3C69FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x3C6A00 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x3C6A04 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x3C6A08 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x3C6A0C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x3C6A10 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x3C6A14 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x3C6A18 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x3C6A1C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x3C6A20 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x3C6A64 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x3C6A68 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x3C6A6C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x3C6A70 + +#define mmNIF_RTR_CTRL_4_RGL_CFG 0x3C6B64 + +#define mmNIF_RTR_CTRL_4_RGL_SHIFT 0x3C6B68 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x3C6B6C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x3C6B70 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x3C6B74 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x3C6B78 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x3C6B7C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x3C6B80 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x3C6B84 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x3C6B88 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_0 0x3C6BAC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_1 0x3C6BB0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_2 0x3C6BB4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_3 0x3C6BB8 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_4 0x3C6BBC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_5 0x3C6BC0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_6 0x3C6BC4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_7 0x3C6BC8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_0 0x3C6BEC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_1 0x3C6BF0 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_2 0x3C6BF4 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_3 0x3C6BF8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_4 0x3C6BFC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_5 0x3C6C00 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_6 0x3C6C04 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_7 0x3C6C08 + +#define mmNIF_RTR_CTRL_4_RGL_WDT 0x3C6C2C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x3C6C30 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x3C6C34 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x3C6C38 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x3C6C3C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x3C6C40 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x3C6C44 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x3C6C48 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x3C6C4C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x3C6C50 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x3C6C54 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x3C6C58 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x3C6C5C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x3C6C60 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x3C6C64 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x3C6C68 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x3C6C6C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x3C6C70 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x3C6C74 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x3C6C78 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x3C6C7C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x3C6C80 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x3C6C84 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x3C6C88 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x3C6C8C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x3C6C90 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x3C6C94 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x3C6C98 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x3C6C9C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x3C6CA0 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x3C6CA4 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x3C6CA8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x3C6CAC + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x3C6CB0 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x3C6CB4 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x3C6CB8 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x3C6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000..95486b7dd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_5_PERM_SEL 0x3D6108 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_0 0x3D6114 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_1 0x3D6118 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_2 0x3D611C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_3 0x3D6120 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_4 0x3D6124 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_5 0x3D6128 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_6 0x3D612C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_7 0x3D6130 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_8 0x3D6134 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_9 0x3D6138 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_10 0x3D613C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_11 0x3D6140 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_12 0x3D6144 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_13 0x3D6148 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_14 0x3D614C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_15 0x3D6150 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_16 0x3D6154 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_17 0x3D6158 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_18 0x3D615C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_19 0x3D6160 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_20 0x3D6164 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_21 0x3D6168 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_22 0x3D616C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_23 0x3D6170 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_24 0x3D6174 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_25 0x3D6178 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_26 0x3D617C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_27 0x3D6180 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x3D6184 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x3D6188 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x3D618C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x3D6190 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x3D6194 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x3D6198 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x3D619C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3D61A0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3D61A4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3D61A8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3D61AC + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3D61B0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3D61B4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3D61B8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3D61BC + +#define mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x3D626C + +#define mmNIF_RTR_CTRL_5_RL_HBM_EN 0x3D6274 + +#define mmNIF_RTR_CTRL_5_RL_HBM_SAT 0x3D6278 + +#define mmNIF_RTR_CTRL_5_RL_HBM_RST 0x3D627C + +#define mmNIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x3D6280 + +#define mmNIF_RTR_CTRL_5_SCRAM_HBM_EN 0x3D6284 + +#define mmNIF_RTR_CTRL_5_RL_PCI_EN 0x3D6288 + +#define mmNIF_RTR_CTRL_5_RL_PCI_SAT 0x3D628C + +#define mmNIF_RTR_CTRL_5_RL_PCI_RST 0x3D6290 + +#define mmNIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x3D6294 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_EN 0x3D629C + +#define mmNIF_RTR_CTRL_5_RL_SRAM_SAT 0x3D62A0 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RST 0x3D62A4 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3D62AC + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RED 0x3D62B4 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_EN 0x3D62EC + +#define mmNIF_RTR_CTRL_5_E2E_PCI_EN 0x3D62F0 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3D62F4 + +#define mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3D62F8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x3D6404 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x3D6408 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x3D640C + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x3D6410 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x3D6414 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x3D6418 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x3D641C + +#define mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x3D6420 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x3D6424 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x3D6428 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x3D642C + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x3D6430 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x3D6434 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x3D6438 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_0 0x3D6450 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_1 0x3D6454 + +#define mmNIF_RTR_CTRL_5_NON_LIN_EN 0x3D6480 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x3D6500 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x3D6504 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x3D6508 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x3D650C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x3D6510 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x3D6514 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x3D6520 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x3D6524 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x3D6528 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x3D652C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x3D6530 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x3D6534 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x3D6538 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x3D653C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x3D6540 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x3D6550 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x3D6554 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x3D6558 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x3D655C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x3D6560 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x3D6564 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x3D6568 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x3D656C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x3D6570 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x3D6574 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x3D6578 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x3D657C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x3D6580 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x3D6584 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x3D6588 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x3D658C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x3D6590 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x3D6594 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x3D6598 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3D65E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3D65E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3D65EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3D65F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3D65F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3D65F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3D65FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x3D6600 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x3D6604 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x3D6608 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x3D660C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x3D6610 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x3D6614 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x3D6618 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x3D661C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x3D6620 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x3D6624 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x3D6628 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x3D662C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x3D6630 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x3D6634 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x3D6638 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x3D663C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x3D6640 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x3D6644 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x3D6648 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x3D664C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x3D6650 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x3D6654 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x3D6658 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x3D665C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x3D6660 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x3D6664 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x3D6668 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x3D666C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x3D6670 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x3D6674 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x3D6678 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x3D667C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x3D6680 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x3D6684 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x3D6688 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x3D668C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x3D6690 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x3D6694 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x3D6698 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x3D669C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3D66A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3D66A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3D66A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3D66AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3D66B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3D66B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3D66B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3D66BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3D66C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3D66C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3D66C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3D66CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3D66D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3D66D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3D66D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3D66DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3D66E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3D66E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3D66E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3D66EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3D66F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3D66F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3D66F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3D66FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x3D6700 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x3D6704 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x3D6708 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x3D670C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x3D6710 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x3D6714 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x3D6718 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x3D671C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x3D6720 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x3D6724 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x3D6728 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x3D672C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x3D6730 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x3D6734 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x3D6738 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x3D673C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x3D6740 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x3D6744 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x3D6748 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x3D674C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x3D6750 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x3D6754 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x3D6758 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x3D675C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x3D6760 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x3D6764 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x3D6768 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x3D676C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x3D6770 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x3D6774 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x3D6778 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x3D677C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x3D6780 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x3D6784 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x3D6788 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x3D678C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x3D6790 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x3D6794 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x3D6798 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x3D679C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3D67A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3D67A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3D67A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3D67AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3D67B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3D67B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3D67B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3D67BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3D67C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3D67C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3D67C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3D67CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3D67D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3D67D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3D67D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3D67DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3D67E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x3D6824 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x3D6828 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x3D682C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x3D6830 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x3D6834 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x3D6838 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x3D683C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x3D6840 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x3D6844 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x3D6848 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x3D684C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x3D6850 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x3D6854 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x3D6858 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x3D685C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x3D6860 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x3D6864 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x3D6868 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x3D686C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x3D6870 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x3D6874 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x3D6878 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x3D687C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x3D6880 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x3D6884 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x3D6888 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x3D688C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x3D6890 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x3D6894 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x3D6898 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x3D689C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3D68A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3D68A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3D68A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3D68AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3D68B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3D68B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3D68B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3D68BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3D68C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3D68C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3D68C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3D68CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3D68D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3D68D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3D68D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3D68DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3D68E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3D68E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3D68E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3D68EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3D68F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3D68F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3D68F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3D68FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x3D6900 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x3D6904 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x3D6908 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x3D690C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x3D6910 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x3D6914 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x3D6918 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x3D691C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x3D6920 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x3D6924 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x3D6928 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x3D692C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x3D6930 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x3D6934 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x3D6938 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x3D693C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x3D6940 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x3D6944 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x3D6948 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x3D694C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x3D6950 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x3D6954 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x3D6958 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x3D695C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x3D6960 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x3D6964 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x3D6968 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x3D696C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x3D6970 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x3D6974 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x3D6978 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x3D697C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x3D6980 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x3D6984 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x3D6988 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x3D698C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x3D6990 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x3D6994 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x3D6998 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x3D699C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3D69A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3D69A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3D69A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3D69AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3D69B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3D69B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3D69B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3D69BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3D69C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3D69C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3D69C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3D69CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3D69D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3D69D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3D69D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3D69DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3D69E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3D69E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3D69E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3D69EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3D69F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3D69F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3D69F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3D69FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x3D6A00 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x3D6A04 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x3D6A08 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x3D6A0C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x3D6A10 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x3D6A14 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x3D6A18 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x3D6A1C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x3D6A20 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x3D6A64 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x3D6A68 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x3D6A6C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x3D6A70 + +#define mmNIF_RTR_CTRL_5_RGL_CFG 0x3D6B64 + +#define mmNIF_RTR_CTRL_5_RGL_SHIFT 0x3D6B68 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x3D6B6C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x3D6B70 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x3D6B74 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x3D6B78 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x3D6B7C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x3D6B80 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x3D6B84 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x3D6B88 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_0 0x3D6BAC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_1 0x3D6BB0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_2 0x3D6BB4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_3 0x3D6BB8 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_4 0x3D6BBC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_5 0x3D6BC0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_6 0x3D6BC4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_7 0x3D6BC8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_0 0x3D6BEC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_1 0x3D6BF0 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_2 0x3D6BF4 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_3 0x3D6BF8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_4 0x3D6BFC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_5 0x3D6C00 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_6 0x3D6C04 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_7 0x3D6C08 + +#define mmNIF_RTR_CTRL_5_RGL_WDT 0x3D6C2C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x3D6C30 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x3D6C34 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x3D6C38 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x3D6C3C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x3D6C40 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x3D6C44 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x3D6C48 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x3D6C4C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x3D6C50 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x3D6C54 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x3D6C58 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x3D6C5C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x3D6C60 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x3D6C64 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x3D6C68 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x3D6C6C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x3D6C70 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x3D6C74 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x3D6C78 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x3D6C7C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x3D6C80 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x3D6C84 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x3D6C88 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x3D6C8C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x3D6C90 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x3D6C94 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x3D6C98 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x3D6C9C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x3D6CA0 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x3D6CA4 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x3D6CA8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x3D6CAC + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x3D6CB0 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x3D6CB4 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x3D6CB8 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x3D6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000..b79c59887 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_6_PERM_SEL 0x3E6108 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_0 0x3E6114 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_1 0x3E6118 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_2 0x3E611C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_3 0x3E6120 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_4 0x3E6124 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_5 0x3E6128 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_6 0x3E612C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_7 0x3E6130 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_8 0x3E6134 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_9 0x3E6138 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_10 0x3E613C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_11 0x3E6140 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_12 0x3E6144 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_13 0x3E6148 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_14 0x3E614C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_15 0x3E6150 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_16 0x3E6154 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_17 0x3E6158 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_18 0x3E615C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_19 0x3E6160 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_20 0x3E6164 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_21 0x3E6168 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_22 0x3E616C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_23 0x3E6170 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_24 0x3E6174 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_25 0x3E6178 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_26 0x3E617C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_27 0x3E6180 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x3E6184 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x3E6188 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x3E618C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x3E6190 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x3E6194 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x3E6198 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x3E619C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3E61A0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3E61A4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3E61A8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3E61AC + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3E61B0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3E61B4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3E61B8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3E61BC + +#define mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x3E626C + +#define mmNIF_RTR_CTRL_6_RL_HBM_EN 0x3E6274 + +#define mmNIF_RTR_CTRL_6_RL_HBM_SAT 0x3E6278 + +#define mmNIF_RTR_CTRL_6_RL_HBM_RST 0x3E627C + +#define mmNIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x3E6280 + +#define mmNIF_RTR_CTRL_6_SCRAM_HBM_EN 0x3E6284 + +#define mmNIF_RTR_CTRL_6_RL_PCI_EN 0x3E6288 + +#define mmNIF_RTR_CTRL_6_RL_PCI_SAT 0x3E628C + +#define mmNIF_RTR_CTRL_6_RL_PCI_RST 0x3E6290 + +#define mmNIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x3E6294 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_EN 0x3E629C + +#define mmNIF_RTR_CTRL_6_RL_SRAM_SAT 0x3E62A0 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RST 0x3E62A4 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3E62AC + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RED 0x3E62B4 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_EN 0x3E62EC + +#define mmNIF_RTR_CTRL_6_E2E_PCI_EN 0x3E62F0 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3E62F4 + +#define mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3E62F8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x3E6404 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x3E6408 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x3E640C + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x3E6410 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x3E6414 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x3E6418 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x3E641C + +#define mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x3E6420 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x3E6424 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x3E6428 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x3E642C + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x3E6430 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x3E6434 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x3E6438 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_0 0x3E6450 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_1 0x3E6454 + +#define mmNIF_RTR_CTRL_6_NON_LIN_EN 0x3E6480 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x3E6500 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x3E6504 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x3E6508 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x3E650C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x3E6510 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x3E6514 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x3E6520 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x3E6524 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x3E6528 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x3E652C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x3E6530 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x3E6534 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x3E6538 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x3E653C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x3E6540 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x3E6550 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x3E6554 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x3E6558 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x3E655C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x3E6560 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x3E6564 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x3E6568 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x3E656C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x3E6570 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x3E6574 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x3E6578 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x3E657C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x3E6580 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x3E6584 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x3E6588 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x3E658C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x3E6590 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x3E6594 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x3E6598 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3E65E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3E65E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3E65EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3E65F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3E65F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3E65F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3E65FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x3E6600 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x3E6604 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x3E6608 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x3E660C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x3E6610 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x3E6614 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x3E6618 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x3E661C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x3E6620 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x3E6624 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x3E6628 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x3E662C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x3E6630 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x3E6634 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x3E6638 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x3E663C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x3E6640 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x3E6644 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x3E6648 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x3E664C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x3E6650 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x3E6654 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x3E6658 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x3E665C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x3E6660 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x3E6664 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x3E6668 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x3E666C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x3E6670 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x3E6674 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x3E6678 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x3E667C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x3E6680 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x3E6684 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x3E6688 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x3E668C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x3E6690 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x3E6694 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x3E6698 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x3E669C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3E66A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3E66A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3E66A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3E66AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3E66B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3E66B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3E66B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3E66BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3E66C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3E66C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3E66C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3E66CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3E66D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3E66D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3E66D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3E66DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3E66E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3E66E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3E66E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3E66EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3E66F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3E66F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3E66F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3E66FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x3E6700 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x3E6704 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x3E6708 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x3E670C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x3E6710 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x3E6714 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x3E6718 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x3E671C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x3E6720 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x3E6724 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x3E6728 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x3E672C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x3E6730 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x3E6734 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x3E6738 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x3E673C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x3E6740 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x3E6744 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x3E6748 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x3E674C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x3E6750 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x3E6754 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x3E6758 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x3E675C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x3E6760 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x3E6764 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x3E6768 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x3E676C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x3E6770 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x3E6774 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x3E6778 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x3E677C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x3E6780 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x3E6784 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x3E6788 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x3E678C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x3E6790 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x3E6794 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x3E6798 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x3E679C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3E67A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3E67A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3E67A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3E67AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3E67B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3E67B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3E67B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3E67BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3E67C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3E67C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3E67C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3E67CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3E67D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3E67D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3E67D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3E67DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3E67E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x3E6824 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x3E6828 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x3E682C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x3E6830 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x3E6834 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x3E6838 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x3E683C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x3E6840 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x3E6844 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x3E6848 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x3E684C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x3E6850 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x3E6854 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x3E6858 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x3E685C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x3E6860 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x3E6864 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x3E6868 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x3E686C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x3E6870 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x3E6874 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x3E6878 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x3E687C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x3E6880 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x3E6884 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x3E6888 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x3E688C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x3E6890 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x3E6894 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x3E6898 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x3E689C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3E68A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3E68A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3E68A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3E68AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3E68B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3E68B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3E68B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3E68BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3E68C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3E68C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3E68C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3E68CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3E68D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3E68D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3E68D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3E68DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3E68E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3E68E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3E68E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3E68EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3E68F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3E68F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3E68F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3E68FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x3E6900 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x3E6904 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x3E6908 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x3E690C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x3E6910 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x3E6914 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x3E6918 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x3E691C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x3E6920 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x3E6924 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x3E6928 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x3E692C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x3E6930 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x3E6934 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x3E6938 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x3E693C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x3E6940 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x3E6944 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x3E6948 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x3E694C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x3E6950 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x3E6954 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x3E6958 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x3E695C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x3E6960 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x3E6964 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x3E6968 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x3E696C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x3E6970 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x3E6974 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x3E6978 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x3E697C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x3E6980 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x3E6984 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x3E6988 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x3E698C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x3E6990 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x3E6994 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x3E6998 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x3E699C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3E69A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3E69A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3E69A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3E69AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3E69B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3E69B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3E69B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3E69BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3E69C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3E69C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3E69C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3E69CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3E69D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3E69D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3E69D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3E69DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3E69E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3E69E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3E69E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3E69EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3E69F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3E69F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3E69F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3E69FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x3E6A00 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x3E6A04 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x3E6A08 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x3E6A0C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x3E6A10 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x3E6A14 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x3E6A18 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x3E6A1C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x3E6A20 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x3E6A64 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x3E6A68 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x3E6A6C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x3E6A70 + +#define mmNIF_RTR_CTRL_6_RGL_CFG 0x3E6B64 + +#define mmNIF_RTR_CTRL_6_RGL_SHIFT 0x3E6B68 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x3E6B6C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x3E6B70 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x3E6B74 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x3E6B78 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x3E6B7C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x3E6B80 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x3E6B84 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x3E6B88 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_0 0x3E6BAC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_1 0x3E6BB0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_2 0x3E6BB4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_3 0x3E6BB8 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_4 0x3E6BBC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_5 0x3E6BC0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_6 0x3E6BC4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_7 0x3E6BC8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_0 0x3E6BEC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_1 0x3E6BF0 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_2 0x3E6BF4 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_3 0x3E6BF8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_4 0x3E6BFC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_5 0x3E6C00 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_6 0x3E6C04 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_7 0x3E6C08 + +#define mmNIF_RTR_CTRL_6_RGL_WDT 0x3E6C2C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x3E6C30 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x3E6C34 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x3E6C38 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x3E6C3C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x3E6C40 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x3E6C44 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x3E6C48 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x3E6C4C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x3E6C50 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x3E6C54 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x3E6C58 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x3E6C5C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x3E6C60 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x3E6C64 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x3E6C68 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x3E6C6C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x3E6C70 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x3E6C74 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x3E6C78 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x3E6C7C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x3E6C80 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x3E6C84 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x3E6C88 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x3E6C8C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x3E6C90 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x3E6C94 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x3E6C98 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x3E6C9C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x3E6CA0 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x3E6CA4 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x3E6CA8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x3E6CAC + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x3E6CB0 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x3E6CB4 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x3E6CB8 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x3E6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000..3a6a34ba2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_7_PERM_SEL 0x3F6108 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_0 0x3F6114 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_1 0x3F6118 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_2 0x3F611C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_3 0x3F6120 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_4 0x3F6124 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_5 0x3F6128 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_6 0x3F612C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_7 0x3F6130 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_8 0x3F6134 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_9 0x3F6138 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_10 0x3F613C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_11 0x3F6140 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_12 0x3F6144 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_13 0x3F6148 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_14 0x3F614C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_15 0x3F6150 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_16 0x3F6154 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_17 0x3F6158 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_18 0x3F615C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_19 0x3F6160 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_20 0x3F6164 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_21 0x3F6168 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_22 0x3F616C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_23 0x3F6170 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_24 0x3F6174 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_25 0x3F6178 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_26 0x3F617C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_27 0x3F6180 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x3F6184 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x3F6188 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x3F618C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x3F6190 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x3F6194 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x3F6198 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x3F619C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3F61A0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3F61A4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3F61A8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3F61AC + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3F61B0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3F61B4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3F61B8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3F61BC + +#define mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x3F626C + +#define mmNIF_RTR_CTRL_7_RL_HBM_EN 0x3F6274 + +#define mmNIF_RTR_CTRL_7_RL_HBM_SAT 0x3F6278 + +#define mmNIF_RTR_CTRL_7_RL_HBM_RST 0x3F627C + +#define mmNIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x3F6280 + +#define mmNIF_RTR_CTRL_7_SCRAM_HBM_EN 0x3F6284 + +#define mmNIF_RTR_CTRL_7_RL_PCI_EN 0x3F6288 + +#define mmNIF_RTR_CTRL_7_RL_PCI_SAT 0x3F628C + +#define mmNIF_RTR_CTRL_7_RL_PCI_RST 0x3F6290 + +#define mmNIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x3F6294 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_EN 0x3F629C + +#define mmNIF_RTR_CTRL_7_RL_SRAM_SAT 0x3F62A0 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RST 0x3F62A4 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3F62AC + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RED 0x3F62B4 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_EN 0x3F62EC + +#define mmNIF_RTR_CTRL_7_E2E_PCI_EN 0x3F62F0 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3F62F4 + +#define mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3F62F8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x3F6404 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x3F6408 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x3F640C + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x3F6410 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x3F6414 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x3F6418 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x3F641C + +#define mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x3F6420 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x3F6424 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x3F6428 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x3F642C + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x3F6430 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x3F6434 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x3F6438 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_0 0x3F6450 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_1 0x3F6454 + +#define mmNIF_RTR_CTRL_7_NON_LIN_EN 0x3F6480 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x3F6500 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x3F6504 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x3F6508 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x3F650C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x3F6510 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x3F6514 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x3F6520 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x3F6524 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x3F6528 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x3F652C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x3F6530 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x3F6534 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x3F6538 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x3F653C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x3F6540 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x3F6550 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x3F6554 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x3F6558 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x3F655C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x3F6560 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x3F6564 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x3F6568 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x3F656C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x3F6570 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x3F6574 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x3F6578 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x3F657C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x3F6580 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x3F6584 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x3F6588 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x3F658C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x3F6590 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x3F6594 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x3F6598 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3F65E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3F65E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3F65EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3F65F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3F65F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3F65F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3F65FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x3F6600 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x3F6604 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x3F6608 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x3F660C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x3F6610 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x3F6614 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x3F6618 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x3F661C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x3F6620 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x3F6624 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x3F6628 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x3F662C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x3F6630 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x3F6634 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x3F6638 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x3F663C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x3F6640 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x3F6644 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x3F6648 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x3F664C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x3F6650 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x3F6654 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x3F6658 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x3F665C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x3F6660 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x3F6664 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x3F6668 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x3F666C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x3F6670 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x3F6674 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x3F6678 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x3F667C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x3F6680 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x3F6684 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x3F6688 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x3F668C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x3F6690 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x3F6694 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x3F6698 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x3F669C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3F66A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3F66A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3F66A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3F66AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3F66B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3F66B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3F66B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3F66BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3F66C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3F66C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3F66C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3F66CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3F66D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3F66D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3F66D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3F66DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3F66E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3F66E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3F66E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3F66EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3F66F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3F66F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3F66F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3F66FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x3F6700 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x3F6704 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x3F6708 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x3F670C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x3F6710 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x3F6714 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x3F6718 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x3F671C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x3F6720 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x3F6724 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x3F6728 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x3F672C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x3F6730 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x3F6734 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x3F6738 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x3F673C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x3F6740 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x3F6744 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x3F6748 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x3F674C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x3F6750 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x3F6754 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x3F6758 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x3F675C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x3F6760 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x3F6764 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x3F6768 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x3F676C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x3F6770 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x3F6774 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x3F6778 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x3F677C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x3F6780 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x3F6784 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x3F6788 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x3F678C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x3F6790 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x3F6794 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x3F6798 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x3F679C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3F67A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3F67A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3F67A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3F67AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3F67B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3F67B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3F67B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3F67BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3F67C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3F67C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3F67C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3F67CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3F67D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3F67D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3F67D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3F67DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3F67E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x3F6824 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x3F6828 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x3F682C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x3F6830 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x3F6834 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x3F6838 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x3F683C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x3F6840 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x3F6844 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x3F6848 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x3F684C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x3F6850 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x3F6854 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x3F6858 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x3F685C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x3F6860 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x3F6864 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x3F6868 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x3F686C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x3F6870 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x3F6874 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x3F6878 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x3F687C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x3F6880 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x3F6884 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x3F6888 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x3F688C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x3F6890 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x3F6894 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x3F6898 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x3F689C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3F68A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3F68A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3F68A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3F68AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3F68B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3F68B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3F68B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3F68BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3F68C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3F68C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3F68C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3F68CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3F68D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3F68D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3F68D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3F68DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3F68E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3F68E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3F68E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3F68EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3F68F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3F68F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3F68F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3F68FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x3F6900 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x3F6904 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x3F6908 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x3F690C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x3F6910 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x3F6914 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x3F6918 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x3F691C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x3F6920 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x3F6924 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x3F6928 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x3F692C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x3F6930 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x3F6934 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x3F6938 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x3F693C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x3F6940 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x3F6944 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x3F6948 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x3F694C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x3F6950 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x3F6954 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x3F6958 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x3F695C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x3F6960 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x3F6964 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x3F6968 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x3F696C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x3F6970 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x3F6974 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x3F6978 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x3F697C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x3F6980 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x3F6984 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x3F6988 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x3F698C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x3F6990 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x3F6994 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x3F6998 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x3F699C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3F69A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3F69A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3F69A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3F69AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3F69B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3F69B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3F69B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3F69BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3F69C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3F69C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3F69C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3F69CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3F69D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3F69D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3F69D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3F69DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3F69E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3F69E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3F69E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3F69EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3F69F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3F69F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3F69F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3F69FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x3F6A00 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x3F6A04 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x3F6A08 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x3F6A0C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x3F6A10 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x3F6A14 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x3F6A18 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x3F6A1C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x3F6A20 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x3F6A64 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x3F6A68 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x3F6A6C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x3F6A70 + +#define mmNIF_RTR_CTRL_7_RGL_CFG 0x3F6B64 + +#define mmNIF_RTR_CTRL_7_RGL_SHIFT 0x3F6B68 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x3F6B6C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x3F6B70 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x3F6B74 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x3F6B78 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x3F6B7C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x3F6B80 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x3F6B84 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x3F6B88 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_0 0x3F6BAC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_1 0x3F6BB0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_2 0x3F6BB4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_3 0x3F6BB8 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_4 0x3F6BBC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_5 0x3F6BC0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_6 0x3F6BC4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_7 0x3F6BC8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_0 0x3F6BEC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_1 0x3F6BF0 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_2 0x3F6BF4 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_3 0x3F6BF8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_4 0x3F6BFC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_5 0x3F6C00 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_6 0x3F6C04 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_7 0x3F6C08 + +#define mmNIF_RTR_CTRL_7_RGL_WDT 0x3F6C2C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x3F6C30 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x3F6C34 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x3F6C38 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x3F6C3C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x3F6C40 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x3F6C44 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x3F6C48 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x3F6C4C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x3F6C50 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x3F6C54 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x3F6C58 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x3F6C5C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x3F6C60 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x3F6C64 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x3F6C68 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x3F6C6C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x3F6C70 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x3F6C74 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x3F6C78 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x3F6C7C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x3F6C80 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x3F6C84 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x3F6C88 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x3F6C8C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x3F6C90 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x3F6C94 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x3F6C98 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x3F6C9C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x3F6CA0 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x3F6CA4 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x3F6CA8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x3F6CAC + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x3F6CB0 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x3F6CB4 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x3F6CB8 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x3F6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h new file mode 100644 index 000000000..2585c70f5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_ +#define ASIC_REG_PSOC_CPU_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_CPU_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_CPU_PLL_NR 0xC70100 + +#define mmPSOC_CPU_PLL_NF 0xC70104 + +#define mmPSOC_CPU_PLL_OD 0xC70108 + +#define mmPSOC_CPU_PLL_NB 0xC7010C + +#define mmPSOC_CPU_PLL_CFG 0xC70110 + +#define mmPSOC_CPU_PLL_LOSE_MASK 0xC70120 + +#define mmPSOC_CPU_PLL_LOCK_INTR 0xC70128 + +#define mmPSOC_CPU_PLL_LOCK_BYPASS 0xC7012C + +#define mmPSOC_CPU_PLL_DATA_CHNG 0xC70130 + +#define mmPSOC_CPU_PLL_RST 0xC70134 + +#define mmPSOC_CPU_PLL_SLIP_WD_CNTR 0xC70150 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_0 0xC70200 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_1 0xC70204 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_2 0xC70208 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_3 0xC7020C + +#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0 0xC70220 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1 0xC70224 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2 0xC70228 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3 0xC7022C + +#define mmPSOC_CPU_PLL_DIV_SEL_0 0xC70280 + +#define mmPSOC_CPU_PLL_DIV_SEL_1 0xC70284 + +#define mmPSOC_CPU_PLL_DIV_SEL_2 0xC70288 + +#define mmPSOC_CPU_PLL_DIV_SEL_3 0xC7028C + +#define mmPSOC_CPU_PLL_DIV_EN_0 0xC702A0 + +#define mmPSOC_CPU_PLL_DIV_EN_1 0xC702A4 + +#define mmPSOC_CPU_PLL_DIV_EN_2 0xC702A8 + +#define mmPSOC_CPU_PLL_DIV_EN_3 0xC702AC + +#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0 0xC702C0 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1 0xC702C4 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2 0xC702C8 + +#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3 0xC702CC + +#define mmPSOC_CPU_PLL_CLK_GATER 0xC70300 + +#define mmPSOC_CPU_PLL_CLK_RLX_0 0xC70310 + +#define mmPSOC_CPU_PLL_CLK_RLX_1 0xC70314 + +#define mmPSOC_CPU_PLL_CLK_RLX_2 0xC70318 + +#define mmPSOC_CPU_PLL_CLK_RLX_3 0xC7031C + +#define mmPSOC_CPU_PLL_REF_CNTR_PERIOD 0xC70400 + +#define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD 0xC70410 + +#define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD 0xC70420 + +#define mmPSOC_CPU_PLL_PLL_NOT_STABLE 0xC70430 + +#define mmPSOC_CPU_PLL_FREQ_CALC_EN 0xC70440 + +#define mmPSOC_CPU_PLL_RLX_BITMAP_CFG 0xC70500 + +#define mmPSOC_CPU_PLL_RLX_BITMAP_0 0xC70510 + +#define mmPSOC_CPU_PLL_RLX_BITMAP_1 0xC70514 + +#define mmPSOC_CPU_PLL_RLX_BITMAP_2 0xC70518 + +#define mmPSOC_CPU_PLL_RLX_BITMAP_3 0xC7051C + +#endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000..b7c33e025 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x2C43004 + +#define mmPSOC_ETR_STS 0x2C4300C + +#define mmPSOC_ETR_RRD 0x2C43010 + +#define mmPSOC_ETR_RRP 0x2C43014 + +#define mmPSOC_ETR_RWP 0x2C43018 + +#define mmPSOC_ETR_TRG 0x2C4301C + +#define mmPSOC_ETR_CTL 0x2C43020 + +#define mmPSOC_ETR_RWD 0x2C43024 + +#define mmPSOC_ETR_MODE 0x2C43028 + +#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C + +#define mmPSOC_ETR_CBUFLEVEL 0x2C43030 + +#define mmPSOC_ETR_BUFWM 0x2C43034 + +#define mmPSOC_ETR_RRPHI 0x2C43038 + +#define mmPSOC_ETR_RWPHI 0x2C4303C + +#define mmPSOC_ETR_AXICTL 0x2C43110 + +#define mmPSOC_ETR_DBALO 0x2C43118 + +#define mmPSOC_ETR_DBAHI 0x2C4311C + +#define mmPSOC_ETR_FFSR 0x2C43300 + +#define mmPSOC_ETR_FFCR 0x2C43304 + +#define mmPSOC_ETR_PSCR 0x2C43308 + +#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC + +#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8 + +#define mmPSOC_ETR_ITCTRL 0x2C43F00 + +#define mmPSOC_ETR_CLAIMSET 0x2C43FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4 + +#define mmPSOC_ETR_LAR 0x2C43FB0 + +#define mmPSOC_ETR_LSR 0x2C43FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8 + +#define mmPSOC_ETR_DEVID 0x2C43FC8 + +#define mmPSOC_ETR_DEVTYPE 0x2C43FCC + +#define mmPSOC_ETR_PERIPHID4 0x2C43FD0 + +#define mmPSOC_ETR_PERIPHID5 0x2C43FD4 + +#define mmPSOC_ETR_PERIPHID6 0x2C43FD8 + +#define mmPSOC_ETR_PERIPHID7 0x2C43FDC + +#define mmPSOC_ETR_PERIPHID0 0x2C43FE0 + +#define mmPSOC_ETR_PERIPHID1 0x2C43FE4 + +#define mmPSOC_ETR_PERIPHID2 0x2C43FE8 + +#define mmPSOC_ETR_PERIPHID3 0x2C43FEC + +#define mmPSOC_ETR_COMPID0 0x2C43FF0 + +#define mmPSOC_ETR_COMPID1 0x2C43FF4 + +#define mmPSOC_ETR_COMPID2 0x2C43FF8 + +#define mmPSOC_ETR_COMPID3 0x2C43FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000..6703e678e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,502 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PHY_STABLE */ +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_OVR */ +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ETR_FLUSH */ +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RAZWI */ +#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_PROT */ +#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_ADC */ +#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TRACE_ADDR */ +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0x3FF + +/* PSOC_GLOBAL_CONF_ARUSER */ +#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AWUSER */ +#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK 0xC +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK 0x1FFF00 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK 0x400000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT 23 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK 0x800000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT 24 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK 0x1F000000 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST */ +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_L */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_H */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_BTL_IMG */ +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_STATE */ +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */ +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_RST_CTRL */ +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK 0xFF + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000..1b5cfcc1d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,1062 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 + +#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0xC4B04C + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0xC4B058 + +#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0xC4B060 + +#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0xC4B064 + +#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0xC4B068 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0xC4B070 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0xC4B074 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0xC4B078 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0xC4B07C + +#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0xC4B080 + +#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0xC4B084 + +#define mmPSOC_GLOBAL_CONF_RAZWI 0xC4B088 + +#define mmPSOC_GLOBAL_CONF_PROT 0xC4B090 + +#define mmPSOC_GLOBAL_CONF_ADC 0xC4B094 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0xC4B098 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C + +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0xC4B300 + +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0xC4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 + +#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0xC4B320 + +#define mmPSOC_GLOBAL_CONF_ARUSER 0xC4B330 + +#define mmPSOC_GLOBAL_CONF_AWUSER 0xC4B334 + +#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0xC4B338 + +#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0xC4B33C + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0xC4B44C + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_L 0xC4B460 + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_H 0xC4B464 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_L 0xC4B470 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_H 0xC4B474 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_L 0xC4B480 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_H 0xC4B484 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L 0xC4B490 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H 0xC4B494 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST 0xC4B498 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST 0xC4B4A0 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L 0xC4B4A4 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H 0xC4B4A8 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B4B0 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_L 0xC4B4B4 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_H 0xC4B4B8 + +#define mmPSOC_GLOBAL_CONF_BTL_IMG 0xC4B4E0 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B4E4 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B4E8 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B4F0 + +#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0xC4B4F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0xC4B614 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0xC4B618 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0xC4B61C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0xC4B620 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0xC4B624 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0xC4B628 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0xC4B62C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0xC4B630 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0xC4B634 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0xC4B638 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0xC4B63C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0xC4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0xC4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0xC4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0xC4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0xC4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0xC4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0xC4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0xC4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0xC4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0xC4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B694 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B698 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B69C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B6A0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B6A4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B6A8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B6AC + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B6B0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B6B4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B6B8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B6BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B6C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B6C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B6C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B6CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B6D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B6D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_6 0xC4B6D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_7 0xC4B6DC + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B710 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ 0xC4B720 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START 0xC4B724 + +#define mmPSOC_GLOBAL_CONF_ADC_DATA_SAMPLES 0xC4B728 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS 0xC4B72C + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB 0xC4B730 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES 0xC4B734 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE 0xC4B738 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA 0xC4B73C + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO 0xC4B740 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK 0xC4B744 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B848 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B84C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B850 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B854 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B858 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B85C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B860 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B864 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B868 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B86C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B870 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B874 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B878 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B87C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B880 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B884 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B888 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B88C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B890 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B894 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B898 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B89C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B8A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B8A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B8A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B8AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B8B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B8B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B8B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B8BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B8C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B8C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B8C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B8CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B8D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B8D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B8D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B8DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B8E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B8E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B8E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B8EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B8F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B8F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B8F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B8FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0xC4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0xC4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0xC4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0xC4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0xC4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0xC4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0xC4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0xC4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0xC4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0xC4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0xC4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0xC4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0xC4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0xC4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_96 0xC4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_97 0xC4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_98 0xC4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_99 0xC4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_100 0xC4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_101 0xC4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_102 0xC4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4BA44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4BA48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4BA4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4BA50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4BA54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4BA58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4BA5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4BA60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4BA64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4BA68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4BA6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4BA70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4BA74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4BA78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4BA7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4BA80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4BA84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4BA88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4BA8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4BA90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4BA94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4BA98 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4BA9C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4BAA0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4BAA4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4BAA8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4BAAC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4BAB0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4BAB4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4BAB8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4BABC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4BAC0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4BAC4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4BAC8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4BACC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4BAD0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4BAD4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4BAD8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4BADC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4BAE0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4BAE4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4BAE8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4BAEC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4BAF0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4BAF4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4BAF8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4BAFC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BB00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BB04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BB08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BB0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BB10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BB14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BB18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BB1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BB20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BB24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BB28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BB2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BB30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BB34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BB38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BB3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BB40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BB44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0xC4BB48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0xC4BB4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0xC4BB50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0xC4BB54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0xC4BB58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0xC4BB5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0xC4BB60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0xC4BB64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0xC4BB68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0xC4BB6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0xC4BB70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0xC4BB74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0xC4BB78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0xC4BB7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_96 0xC4BB80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_97 0xC4BB84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_98 0xC4BB88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_99 0xC4BB8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_100 0xC4BB90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_101 0xC4BB94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_102 0xC4BB98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_0 0xC4BC00 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_1 0xC4BC04 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_2 0xC4BC08 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_3 0xC4BC0C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_4 0xC4BC10 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_5 0xC4BC14 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_6 0xC4BC18 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_7 0xC4BC1C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_8 0xC4BC20 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_9 0xC4BC24 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_10 0xC4BC28 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_11 0xC4BC2C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_12 0xC4BC30 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_13 0xC4BC34 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_14 0xC4BC38 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_15 0xC4BC3C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_16 0xC4BC40 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_17 0xC4BC44 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_18 0xC4BC48 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_19 0xC4BC4C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_20 0xC4BC50 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_21 0xC4BC54 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_22 0xC4BC58 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_23 0xC4BC5C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_24 0xC4BC60 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_25 0xC4BC64 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_26 0xC4BC68 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_27 0xC4BC6C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_28 0xC4BC70 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_29 0xC4BC74 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_30 0xC4BC78 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_31 0xC4BC7C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_32 0xC4BC80 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_33 0xC4BC84 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_34 0xC4BC88 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_35 0xC4BC8C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_36 0xC4BC90 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_37 0xC4BC94 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_38 0xC4BC98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_39 0xC4BC9C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_40 0xC4BCA0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_41 0xC4BCA4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_42 0xC4BCA8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_43 0xC4BCAC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_44 0xC4BCB0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_45 0xC4BCB4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_46 0xC4BCB8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_47 0xC4BCBC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_48 0xC4BCC0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_49 0xC4BCC4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_50 0xC4BCC8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_51 0xC4BCCC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_52 0xC4BCD0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_53 0xC4BCD4 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000..9ce24597d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000..ddf824392 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_0_PERM_SEL 0x306108 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0 0x306114 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1 0x306118 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2 0x30611C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3 0x306120 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4 0x306124 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5 0x306128 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6 0x30612C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7 0x306130 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8 0x306134 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9 0x306138 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10 0x30613C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11 0x306140 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12 0x306144 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13 0x306148 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14 0x30614C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15 0x306150 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16 0x306154 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17 0x306158 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18 0x30615C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19 0x306160 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20 0x306164 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21 0x306168 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22 0x30616C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23 0x306170 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24 0x306174 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25 0x306178 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26 0x30617C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27 0x306180 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x306184 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x306188 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x30618C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x306190 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x306194 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x306198 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x30619C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3061A0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3061A4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3061A8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3061AC + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3061B0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3061B4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3061B8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3061BC + +#define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x30626C + +#define mmSIF_RTR_CTRL_0_RL_HBM_EN 0x306274 + +#define mmSIF_RTR_CTRL_0_RL_HBM_SAT 0x306278 + +#define mmSIF_RTR_CTRL_0_RL_HBM_RST 0x30627C + +#define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x306280 + +#define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN 0x306284 + +#define mmSIF_RTR_CTRL_0_RL_PCI_EN 0x306288 + +#define mmSIF_RTR_CTRL_0_RL_PCI_SAT 0x30628C + +#define mmSIF_RTR_CTRL_0_RL_PCI_RST 0x306290 + +#define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x306294 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_EN 0x30629C + +#define mmSIF_RTR_CTRL_0_RL_SRAM_SAT 0x3062A0 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RST 0x3062A4 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3062AC + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RED 0x3062B4 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_EN 0x3062EC + +#define mmSIF_RTR_CTRL_0_E2E_PCI_EN 0x3062F0 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3062F4 + +#define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3062F8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x306404 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x306408 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x30640C + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x306410 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x306414 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x306418 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x30641C + +#define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x306420 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x306424 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x306428 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x30642C + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x306430 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x306434 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x306438 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0 0x306450 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1 0x306454 + +#define mmSIF_RTR_CTRL_0_NON_LIN_EN 0x306480 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x306500 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x306504 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x306508 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x30650C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x306510 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x306514 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x306520 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x306524 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x306528 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x30652C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x306530 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x306534 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x306538 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x30653C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x306540 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x306550 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x306554 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x306558 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x30655C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x306560 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x306564 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x306568 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x30656C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x306570 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x306574 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x306578 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x30657C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x306580 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x306584 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x306588 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x30658C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x306590 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x306594 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x306598 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3065E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3065E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3065EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3065F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3065F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3065F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3065FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x306600 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x306604 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x306608 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x30660C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x306610 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x306614 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x306618 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x30661C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x306620 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x306624 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x306628 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x30662C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x306630 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x306634 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x306638 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x30663C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x306640 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x306644 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x306648 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x30664C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x306650 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x306654 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x306658 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x30665C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x306660 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x306664 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x306668 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x30666C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x306670 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x306674 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x306678 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x30667C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x306680 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x306684 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x306688 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x30668C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x306690 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x306694 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x306698 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x30669C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3066A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3066A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3066A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3066AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3066B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3066B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3066B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3066BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3066C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3066C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3066C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3066CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3066D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3066D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3066D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3066DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3066E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3066E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3066E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3066EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3066F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3066F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3066F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3066FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x306700 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x306704 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x306708 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x30670C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x306710 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x306714 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x306718 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x30671C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x306720 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x306724 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x306728 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x30672C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x306730 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x306734 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x306738 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x30673C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x306740 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x306744 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x306748 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x30674C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x306750 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x306754 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x306758 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x30675C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x306760 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x306764 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x306768 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x30676C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x306770 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x306774 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x306778 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x30677C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x306780 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x306784 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x306788 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x30678C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x306790 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x306794 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x306798 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x30679C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3067A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3067A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3067A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3067AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3067B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3067B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3067B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3067BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3067C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3067C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3067C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3067CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3067D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3067D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3067D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3067DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3067E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x306824 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x306828 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x30682C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x306830 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x306834 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x306838 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x30683C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x306840 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x306844 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x306848 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x30684C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x306850 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x306854 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x306858 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x30685C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x306860 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x306864 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x306868 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x30686C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x306870 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x306874 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x306878 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x30687C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x306880 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x306884 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x306888 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x30688C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x306890 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x306894 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x306898 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x30689C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3068A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3068A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3068A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3068AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3068B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3068B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3068B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3068BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3068C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3068C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3068C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3068CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3068D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3068D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3068D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3068DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3068E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3068E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3068E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3068EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3068F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3068F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3068F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3068FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x306900 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x306904 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x306908 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x30690C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x306910 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x306914 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x306918 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x30691C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x306920 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x306924 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x306928 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x30692C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x306930 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x306934 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x306938 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x30693C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x306940 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x306944 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x306948 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x30694C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x306950 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x306954 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x306958 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x30695C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x306960 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x306964 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x306968 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x30696C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x306970 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x306974 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x306978 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x30697C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x306980 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x306984 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x306988 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x30698C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x306990 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x306994 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x306998 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x30699C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3069A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3069A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3069A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3069AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3069B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3069B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3069B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3069BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3069C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3069C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3069C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3069CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3069D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3069D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3069D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3069DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3069E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3069E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3069E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3069EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3069F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3069F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3069F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3069FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x306A00 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x306A04 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x306A08 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x306A0C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x306A10 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x306A14 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x306A18 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x306A1C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x306A20 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x306A64 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x306A68 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x306A6C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x306A70 + +#define mmSIF_RTR_CTRL_0_RGL_CFG 0x306B64 + +#define mmSIF_RTR_CTRL_0_RGL_SHIFT 0x306B68 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x306B6C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x306B70 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x306B74 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x306B78 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x306B7C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x306B80 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x306B84 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x306B88 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_0 0x306BAC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_1 0x306BB0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_2 0x306BB4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_3 0x306BB8 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_4 0x306BBC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_5 0x306BC0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_6 0x306BC4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_7 0x306BC8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0 0x306BEC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1 0x306BF0 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2 0x306BF4 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3 0x306BF8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4 0x306BFC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5 0x306C00 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6 0x306C04 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7 0x306C08 + +#define mmSIF_RTR_CTRL_0_RGL_WDT 0x306C2C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x306C30 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x306C34 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x306C38 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x306C3C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x306C40 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x306C44 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x306C48 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x306C4C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x306C50 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x306C54 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x306C58 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x306C5C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x306C60 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x306C64 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x306C68 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x306C6C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x306C70 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x306C74 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x306C78 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x306C7C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x306C80 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x306C84 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x306C88 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x306C8C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x306C90 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x306C94 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x306C98 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x306C9C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x306CA0 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x306CA4 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x306CA8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x306CAC + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x306CB0 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x306CB4 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x306CB8 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x306CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000..c6d517dbb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_1_PERM_SEL 0x316108 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_0 0x316114 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_1 0x316118 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_2 0x31611C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_3 0x316120 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_4 0x316124 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_5 0x316128 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_6 0x31612C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_7 0x316130 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_8 0x316134 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_9 0x316138 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_10 0x31613C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_11 0x316140 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_12 0x316144 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_13 0x316148 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_14 0x31614C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_15 0x316150 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_16 0x316154 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_17 0x316158 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_18 0x31615C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_19 0x316160 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_20 0x316164 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_21 0x316168 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_22 0x31616C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_23 0x316170 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_24 0x316174 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_25 0x316178 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_26 0x31617C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_27 0x316180 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x316184 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x316188 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x31618C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x316190 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x316194 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x316198 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x31619C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3161A0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3161A4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3161A8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3161AC + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3161B0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3161B4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3161B8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3161BC + +#define mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x31626C + +#define mmSIF_RTR_CTRL_1_RL_HBM_EN 0x316274 + +#define mmSIF_RTR_CTRL_1_RL_HBM_SAT 0x316278 + +#define mmSIF_RTR_CTRL_1_RL_HBM_RST 0x31627C + +#define mmSIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x316280 + +#define mmSIF_RTR_CTRL_1_SCRAM_HBM_EN 0x316284 + +#define mmSIF_RTR_CTRL_1_RL_PCI_EN 0x316288 + +#define mmSIF_RTR_CTRL_1_RL_PCI_SAT 0x31628C + +#define mmSIF_RTR_CTRL_1_RL_PCI_RST 0x316290 + +#define mmSIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x316294 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_EN 0x31629C + +#define mmSIF_RTR_CTRL_1_RL_SRAM_SAT 0x3162A0 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RST 0x3162A4 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3162AC + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RED 0x3162B4 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_EN 0x3162EC + +#define mmSIF_RTR_CTRL_1_E2E_PCI_EN 0x3162F0 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3162F4 + +#define mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3162F8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x316404 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x316408 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x31640C + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x316410 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x316414 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x316418 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x31641C + +#define mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x316420 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x316424 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x316428 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x31642C + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x316430 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x316434 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x316438 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_0 0x316450 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_1 0x316454 + +#define mmSIF_RTR_CTRL_1_NON_LIN_EN 0x316480 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x316500 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x316504 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x316508 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x31650C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x316510 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x316514 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x316520 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x316524 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x316528 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x31652C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x316530 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x316534 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x316538 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x31653C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x316540 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x316550 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x316554 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x316558 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x31655C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x316560 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x316564 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x316568 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x31656C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x316570 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x316574 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x316578 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x31657C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x316580 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x316584 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x316588 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x31658C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x316590 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x316594 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x316598 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3165E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3165E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3165EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3165F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3165F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3165F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3165FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x316600 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x316604 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x316608 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x31660C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x316610 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x316614 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x316618 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x31661C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x316620 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x316624 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x316628 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x31662C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x316630 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x316634 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x316638 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x31663C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x316640 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x316644 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x316648 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x31664C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x316650 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x316654 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x316658 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x31665C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x316660 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x316664 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x316668 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x31666C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x316670 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x316674 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x316678 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x31667C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x316680 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x316684 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x316688 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x31668C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x316690 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x316694 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x316698 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x31669C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3166A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3166A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3166A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3166AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3166B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3166B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3166B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3166BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3166C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3166C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3166C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3166CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3166D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3166D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3166D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3166DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3166E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3166E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3166E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3166EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3166F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3166F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3166F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3166FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x316700 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x316704 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x316708 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x31670C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x316710 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x316714 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x316718 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x31671C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x316720 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x316724 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x316728 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x31672C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x316730 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x316734 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x316738 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x31673C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x316740 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x316744 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x316748 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x31674C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x316750 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x316754 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x316758 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x31675C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x316760 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x316764 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x316768 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x31676C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x316770 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x316774 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x316778 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x31677C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x316780 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x316784 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x316788 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x31678C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x316790 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x316794 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x316798 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x31679C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3167A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3167A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3167A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3167AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3167B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3167B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3167B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3167BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3167C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3167C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3167C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3167CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3167D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3167D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3167D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3167DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3167E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x316824 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x316828 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x31682C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x316830 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x316834 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x316838 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x31683C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x316840 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x316844 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x316848 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x31684C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x316850 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x316854 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x316858 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x31685C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x316860 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x316864 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x316868 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x31686C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x316870 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x316874 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x316878 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x31687C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x316880 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x316884 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x316888 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x31688C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x316890 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x316894 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x316898 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x31689C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3168A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3168A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3168A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3168AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3168B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3168B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3168B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3168BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3168C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3168C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3168C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3168CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3168D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3168D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3168D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3168DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3168E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3168E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3168E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3168EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3168F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3168F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3168F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3168FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x316900 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x316904 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x316908 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x31690C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x316910 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x316914 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x316918 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x31691C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x316920 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x316924 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x316928 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x31692C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x316930 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x316934 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x316938 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x31693C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x316940 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x316944 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x316948 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x31694C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x316950 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x316954 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x316958 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x31695C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x316960 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x316964 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x316968 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x31696C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x316970 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x316974 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x316978 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x31697C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x316980 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x316984 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x316988 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x31698C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x316990 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x316994 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x316998 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x31699C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3169A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3169A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3169A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3169AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3169B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3169B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3169B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3169BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3169C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3169C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3169C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3169CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3169D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3169D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3169D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3169DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3169E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3169E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3169E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3169EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3169F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3169F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3169F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3169FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x316A00 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x316A04 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x316A08 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x316A0C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x316A10 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x316A14 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x316A18 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x316A1C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x316A20 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x316A64 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x316A68 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x316A6C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x316A70 + +#define mmSIF_RTR_CTRL_1_RGL_CFG 0x316B64 + +#define mmSIF_RTR_CTRL_1_RGL_SHIFT 0x316B68 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x316B6C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x316B70 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x316B74 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x316B78 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x316B7C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x316B80 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x316B84 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x316B88 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_0 0x316BAC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_1 0x316BB0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_2 0x316BB4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_3 0x316BB8 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_4 0x316BBC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_5 0x316BC0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_6 0x316BC4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_7 0x316BC8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_0 0x316BEC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_1 0x316BF0 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_2 0x316BF4 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_3 0x316BF8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_4 0x316BFC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_5 0x316C00 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_6 0x316C04 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_7 0x316C08 + +#define mmSIF_RTR_CTRL_1_RGL_WDT 0x316C2C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x316C30 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x316C34 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x316C38 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x316C3C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x316C40 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x316C44 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x316C48 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x316C4C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x316C50 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x316C54 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x316C58 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x316C5C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x316C60 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x316C64 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x316C68 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x316C6C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x316C70 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x316C74 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x316C78 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x316C7C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x316C80 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x316C84 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x316C88 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x316C8C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x316C90 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x316C94 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x316C98 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x316C9C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x316CA0 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x316CA4 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x316CA8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x316CAC + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x316CB0 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x316CB4 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x316CB8 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x316CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000..330e5b42d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_2_PERM_SEL 0x326108 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_0 0x326114 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_1 0x326118 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_2 0x32611C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_3 0x326120 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_4 0x326124 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_5 0x326128 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_6 0x32612C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_7 0x326130 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_8 0x326134 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_9 0x326138 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_10 0x32613C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_11 0x326140 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_12 0x326144 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_13 0x326148 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_14 0x32614C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_15 0x326150 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_16 0x326154 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_17 0x326158 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_18 0x32615C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_19 0x326160 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_20 0x326164 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_21 0x326168 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_22 0x32616C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_23 0x326170 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_24 0x326174 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_25 0x326178 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_26 0x32617C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_27 0x326180 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x326184 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x326188 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x32618C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x326190 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x326194 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x326198 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x32619C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3261A0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3261A4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3261A8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3261AC + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3261B0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3261B4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3261B8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3261BC + +#define mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x32626C + +#define mmSIF_RTR_CTRL_2_RL_HBM_EN 0x326274 + +#define mmSIF_RTR_CTRL_2_RL_HBM_SAT 0x326278 + +#define mmSIF_RTR_CTRL_2_RL_HBM_RST 0x32627C + +#define mmSIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x326280 + +#define mmSIF_RTR_CTRL_2_SCRAM_HBM_EN 0x326284 + +#define mmSIF_RTR_CTRL_2_RL_PCI_EN 0x326288 + +#define mmSIF_RTR_CTRL_2_RL_PCI_SAT 0x32628C + +#define mmSIF_RTR_CTRL_2_RL_PCI_RST 0x326290 + +#define mmSIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x326294 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_EN 0x32629C + +#define mmSIF_RTR_CTRL_2_RL_SRAM_SAT 0x3262A0 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RST 0x3262A4 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3262AC + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RED 0x3262B4 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_EN 0x3262EC + +#define mmSIF_RTR_CTRL_2_E2E_PCI_EN 0x3262F0 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3262F4 + +#define mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3262F8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x326404 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x326408 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x32640C + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x326410 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x326414 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x326418 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x32641C + +#define mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x326420 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x326424 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x326428 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x32642C + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x326430 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x326434 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x326438 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_0 0x326450 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_1 0x326454 + +#define mmSIF_RTR_CTRL_2_NON_LIN_EN 0x326480 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x326500 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x326504 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x326508 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x32650C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x326510 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x326514 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x326520 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x326524 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x326528 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x32652C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x326530 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x326534 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x326538 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x32653C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x326540 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x326550 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x326554 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x326558 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x32655C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x326560 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x326564 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x326568 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x32656C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x326570 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x326574 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x326578 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x32657C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x326580 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x326584 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x326588 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x32658C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x326590 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x326594 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x326598 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3265E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3265E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3265EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3265F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3265F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3265F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3265FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x326600 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x326604 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x326608 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x32660C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x326610 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x326614 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x326618 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x32661C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x326620 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x326624 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x326628 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x32662C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x326630 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x326634 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x326638 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x32663C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x326640 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x326644 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x326648 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x32664C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x326650 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x326654 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x326658 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x32665C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x326660 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x326664 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x326668 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x32666C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x326670 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x326674 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x326678 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x32667C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x326680 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x326684 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x326688 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x32668C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x326690 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x326694 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x326698 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x32669C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3266A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3266A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3266A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3266AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3266B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3266B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3266B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3266BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3266C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3266C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3266C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3266CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3266D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3266D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3266D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3266DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3266E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3266E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3266E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3266EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3266F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3266F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3266F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3266FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x326700 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x326704 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x326708 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x32670C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x326710 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x326714 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x326718 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x32671C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x326720 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x326724 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x326728 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x32672C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x326730 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x326734 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x326738 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x32673C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x326740 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x326744 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x326748 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x32674C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x326750 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x326754 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x326758 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x32675C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x326760 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x326764 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x326768 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x32676C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x326770 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x326774 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x326778 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x32677C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x326780 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x326784 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x326788 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x32678C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x326790 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x326794 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x326798 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x32679C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3267A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3267A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3267A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3267AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3267B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3267B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3267B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3267BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3267C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3267C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3267C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3267CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3267D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3267D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3267D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3267DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3267E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x326824 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x326828 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x32682C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x326830 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x326834 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x326838 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x32683C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x326840 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x326844 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x326848 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x32684C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x326850 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x326854 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x326858 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x32685C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x326860 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x326864 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x326868 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x32686C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x326870 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x326874 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x326878 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x32687C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x326880 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x326884 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x326888 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x32688C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x326890 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x326894 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x326898 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x32689C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3268A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3268A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3268A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3268AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3268B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3268B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3268B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3268BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3268C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3268C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3268C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3268CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3268D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3268D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3268D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3268DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3268E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3268E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3268E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3268EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3268F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3268F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3268F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3268FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x326900 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x326904 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x326908 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x32690C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x326910 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x326914 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x326918 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x32691C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x326920 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x326924 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x326928 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x32692C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x326930 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x326934 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x326938 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x32693C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x326940 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x326944 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x326948 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x32694C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x326950 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x326954 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x326958 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x32695C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x326960 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x326964 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x326968 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x32696C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x326970 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x326974 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x326978 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x32697C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x326980 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x326984 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x326988 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x32698C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x326990 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x326994 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x326998 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x32699C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3269A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3269A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3269A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3269AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3269B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3269B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3269B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3269BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3269C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3269C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3269C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3269CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3269D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3269D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3269D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3269DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3269E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3269E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3269E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3269EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3269F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3269F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3269F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3269FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x326A00 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x326A04 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x326A08 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x326A0C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x326A10 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x326A14 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x326A18 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x326A1C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x326A20 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x326A64 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x326A68 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x326A6C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x326A70 + +#define mmSIF_RTR_CTRL_2_RGL_CFG 0x326B64 + +#define mmSIF_RTR_CTRL_2_RGL_SHIFT 0x326B68 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x326B6C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x326B70 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x326B74 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x326B78 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x326B7C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x326B80 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x326B84 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x326B88 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_0 0x326BAC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_1 0x326BB0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_2 0x326BB4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_3 0x326BB8 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_4 0x326BBC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_5 0x326BC0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_6 0x326BC4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_7 0x326BC8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_0 0x326BEC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_1 0x326BF0 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_2 0x326BF4 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_3 0x326BF8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_4 0x326BFC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_5 0x326C00 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_6 0x326C04 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_7 0x326C08 + +#define mmSIF_RTR_CTRL_2_RGL_WDT 0x326C2C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x326C30 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x326C34 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x326C38 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x326C3C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x326C40 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x326C44 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x326C48 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x326C4C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x326C50 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x326C54 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x326C58 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x326C5C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x326C60 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x326C64 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x326C68 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x326C6C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x326C70 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x326C74 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x326C78 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x326C7C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x326C80 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x326C84 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x326C88 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x326C8C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x326C90 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x326C94 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x326C98 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x326C9C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x326CA0 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x326CA4 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x326CA8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x326CAC + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x326CB0 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x326CB4 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x326CB8 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x326CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000..d749f1968 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_3_PERM_SEL 0x336108 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_0 0x336114 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_1 0x336118 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_2 0x33611C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_3 0x336120 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_4 0x336124 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_5 0x336128 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_6 0x33612C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_7 0x336130 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_8 0x336134 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_9 0x336138 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_10 0x33613C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_11 0x336140 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_12 0x336144 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_13 0x336148 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_14 0x33614C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_15 0x336150 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_16 0x336154 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_17 0x336158 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_18 0x33615C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_19 0x336160 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_20 0x336164 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_21 0x336168 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_22 0x33616C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_23 0x336170 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_24 0x336174 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_25 0x336178 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_26 0x33617C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_27 0x336180 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x336184 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x336188 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x33618C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x336190 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x336194 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x336198 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x33619C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3361A0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3361A4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3361A8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3361AC + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3361B0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3361B4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3361B8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3361BC + +#define mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x33626C + +#define mmSIF_RTR_CTRL_3_RL_HBM_EN 0x336274 + +#define mmSIF_RTR_CTRL_3_RL_HBM_SAT 0x336278 + +#define mmSIF_RTR_CTRL_3_RL_HBM_RST 0x33627C + +#define mmSIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x336280 + +#define mmSIF_RTR_CTRL_3_SCRAM_HBM_EN 0x336284 + +#define mmSIF_RTR_CTRL_3_RL_PCI_EN 0x336288 + +#define mmSIF_RTR_CTRL_3_RL_PCI_SAT 0x33628C + +#define mmSIF_RTR_CTRL_3_RL_PCI_RST 0x336290 + +#define mmSIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x336294 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_EN 0x33629C + +#define mmSIF_RTR_CTRL_3_RL_SRAM_SAT 0x3362A0 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RST 0x3362A4 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3362AC + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RED 0x3362B4 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_EN 0x3362EC + +#define mmSIF_RTR_CTRL_3_E2E_PCI_EN 0x3362F0 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3362F4 + +#define mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3362F8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x336404 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x336408 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x33640C + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x336410 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x336414 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x336418 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x33641C + +#define mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x336420 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x336424 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x336428 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x33642C + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x336430 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x336434 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x336438 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_0 0x336450 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_1 0x336454 + +#define mmSIF_RTR_CTRL_3_NON_LIN_EN 0x336480 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x336500 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x336504 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x336508 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x33650C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x336510 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x336514 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x336520 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x336524 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x336528 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x33652C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x336530 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x336534 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x336538 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x33653C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x336540 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x336550 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x336554 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x336558 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x33655C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x336560 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x336564 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x336568 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x33656C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x336570 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x336574 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x336578 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x33657C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x336580 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x336584 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x336588 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x33658C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x336590 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x336594 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x336598 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3365E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3365E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3365EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3365F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3365F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3365F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3365FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x336600 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x336604 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x336608 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x33660C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x336610 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x336614 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x336618 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x33661C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x336620 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x336624 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x336628 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x33662C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x336630 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x336634 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x336638 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x33663C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x336640 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x336644 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x336648 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x33664C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x336650 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x336654 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x336658 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x33665C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x336660 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x336664 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x336668 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x33666C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x336670 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x336674 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x336678 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x33667C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x336680 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x336684 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x336688 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x33668C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x336690 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x336694 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x336698 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x33669C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3366A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3366A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3366A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3366AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3366B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3366B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3366B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3366BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3366C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3366C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3366C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3366CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3366D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3366D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3366D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3366DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3366E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3366E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3366E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3366EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3366F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3366F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3366F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3366FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x336700 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x336704 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x336708 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x33670C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x336710 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x336714 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x336718 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x33671C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x336720 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x336724 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x336728 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x33672C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x336730 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x336734 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x336738 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x33673C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x336740 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x336744 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x336748 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x33674C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x336750 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x336754 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x336758 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x33675C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x336760 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x336764 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x336768 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x33676C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x336770 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x336774 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x336778 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x33677C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x336780 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x336784 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x336788 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x33678C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x336790 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x336794 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x336798 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x33679C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3367A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3367A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3367A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3367AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3367B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3367B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3367B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3367BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3367C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3367C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3367C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3367CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3367D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3367D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3367D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3367DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3367E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x336824 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x336828 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x33682C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x336830 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x336834 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x336838 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x33683C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x336840 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x336844 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x336848 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x33684C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x336850 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x336854 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x336858 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x33685C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x336860 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x336864 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x336868 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x33686C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x336870 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x336874 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x336878 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x33687C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x336880 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x336884 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x336888 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x33688C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x336890 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x336894 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x336898 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x33689C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3368A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3368A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3368A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3368AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3368B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3368B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3368B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3368BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3368C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3368C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3368C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3368CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3368D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3368D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3368D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3368DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3368E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3368E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3368E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3368EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3368F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3368F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3368F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3368FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x336900 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x336904 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x336908 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x33690C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x336910 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x336914 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x336918 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x33691C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x336920 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x336924 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x336928 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x33692C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x336930 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x336934 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x336938 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x33693C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x336940 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x336944 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x336948 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x33694C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x336950 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x336954 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x336958 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x33695C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x336960 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x336964 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x336968 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x33696C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x336970 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x336974 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x336978 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x33697C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x336980 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x336984 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x336988 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x33698C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x336990 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x336994 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x336998 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x33699C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3369A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3369A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3369A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3369AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3369B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3369B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3369B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3369BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3369C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3369C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3369C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3369CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3369D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3369D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3369D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3369DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3369E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3369E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3369E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3369EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3369F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3369F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3369F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3369FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x336A00 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x336A04 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x336A08 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x336A0C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x336A10 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x336A14 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x336A18 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x336A1C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x336A20 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x336A64 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x336A68 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x336A6C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x336A70 + +#define mmSIF_RTR_CTRL_3_RGL_CFG 0x336B64 + +#define mmSIF_RTR_CTRL_3_RGL_SHIFT 0x336B68 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x336B6C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x336B70 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x336B74 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x336B78 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x336B7C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x336B80 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x336B84 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x336B88 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_0 0x336BAC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_1 0x336BB0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_2 0x336BB4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_3 0x336BB8 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_4 0x336BBC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_5 0x336BC0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_6 0x336BC4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_7 0x336BC8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_0 0x336BEC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_1 0x336BF0 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_2 0x336BF4 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_3 0x336BF8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_4 0x336BFC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_5 0x336C00 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_6 0x336C04 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_7 0x336C08 + +#define mmSIF_RTR_CTRL_3_RGL_WDT 0x336C2C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x336C30 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x336C34 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x336C38 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x336C3C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x336C40 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x336C44 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x336C48 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x336C4C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x336C50 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x336C54 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x336C58 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x336C5C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x336C60 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x336C64 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x336C68 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x336C6C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x336C70 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x336C74 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x336C78 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x336C7C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x336C80 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x336C84 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x336C88 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x336C8C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x336C90 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x336C94 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x336C98 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x336C9C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x336CA0 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x336CA4 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x336CA8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x336CAC + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x336CB0 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x336CB4 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x336CB8 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x336CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000..ad48773c4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_4_PERM_SEL 0x346108 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_0 0x346114 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_1 0x346118 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_2 0x34611C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_3 0x346120 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_4 0x346124 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_5 0x346128 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_6 0x34612C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_7 0x346130 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_8 0x346134 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_9 0x346138 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_10 0x34613C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_11 0x346140 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_12 0x346144 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_13 0x346148 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_14 0x34614C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_15 0x346150 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_16 0x346154 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_17 0x346158 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_18 0x34615C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_19 0x346160 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_20 0x346164 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_21 0x346168 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_22 0x34616C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_23 0x346170 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_24 0x346174 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_25 0x346178 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_26 0x34617C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_27 0x346180 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x346184 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x346188 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x34618C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x346190 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x346194 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x346198 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x34619C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3461A0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3461A4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3461A8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3461AC + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3461B0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3461B4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3461B8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3461BC + +#define mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x34626C + +#define mmSIF_RTR_CTRL_4_RL_HBM_EN 0x346274 + +#define mmSIF_RTR_CTRL_4_RL_HBM_SAT 0x346278 + +#define mmSIF_RTR_CTRL_4_RL_HBM_RST 0x34627C + +#define mmSIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x346280 + +#define mmSIF_RTR_CTRL_4_SCRAM_HBM_EN 0x346284 + +#define mmSIF_RTR_CTRL_4_RL_PCI_EN 0x346288 + +#define mmSIF_RTR_CTRL_4_RL_PCI_SAT 0x34628C + +#define mmSIF_RTR_CTRL_4_RL_PCI_RST 0x346290 + +#define mmSIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x346294 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_EN 0x34629C + +#define mmSIF_RTR_CTRL_4_RL_SRAM_SAT 0x3462A0 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RST 0x3462A4 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3462AC + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RED 0x3462B4 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_EN 0x3462EC + +#define mmSIF_RTR_CTRL_4_E2E_PCI_EN 0x3462F0 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3462F4 + +#define mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3462F8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x346404 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x346408 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x34640C + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x346410 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x346414 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x346418 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x34641C + +#define mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x346420 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x346424 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x346428 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x34642C + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x346430 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x346434 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x346438 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_0 0x346450 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_1 0x346454 + +#define mmSIF_RTR_CTRL_4_NON_LIN_EN 0x346480 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x346500 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x346504 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x346508 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x34650C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x346510 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x346514 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x346520 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x346524 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x346528 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x34652C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x346530 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x346534 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x346538 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x34653C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x346540 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x346550 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x346554 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x346558 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x34655C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x346560 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x346564 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x346568 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x34656C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x346570 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x346574 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x346578 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x34657C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x346580 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x346584 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x346588 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x34658C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x346590 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x346594 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x346598 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3465E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3465E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3465EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3465F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3465F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3465F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3465FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x346600 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x346604 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x346608 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x34660C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x346610 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x346614 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x346618 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x34661C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x346620 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x346624 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x346628 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x34662C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x346630 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x346634 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x346638 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x34663C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x346640 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x346644 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x346648 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x34664C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x346650 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x346654 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x346658 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x34665C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x346660 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x346664 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x346668 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x34666C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x346670 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x346674 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x346678 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x34667C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x346680 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x346684 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x346688 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x34668C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x346690 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x346694 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x346698 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x34669C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3466A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3466A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3466A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3466AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3466B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3466B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3466B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3466BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3466C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3466C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3466C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3466CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3466D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3466D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3466D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3466DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3466E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3466E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3466E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3466EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3466F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3466F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3466F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3466FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x346700 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x346704 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x346708 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x34670C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x346710 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x346714 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x346718 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x34671C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x346720 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x346724 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x346728 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x34672C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x346730 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x346734 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x346738 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x34673C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x346740 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x346744 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x346748 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x34674C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x346750 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x346754 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x346758 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x34675C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x346760 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x346764 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x346768 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x34676C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x346770 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x346774 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x346778 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x34677C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x346780 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x346784 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x346788 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x34678C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x346790 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x346794 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x346798 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x34679C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3467A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3467A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3467A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3467AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3467B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3467B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3467B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3467BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3467C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3467C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3467C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3467CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3467D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3467D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3467D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3467DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3467E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x346824 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x346828 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x34682C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x346830 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x346834 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x346838 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x34683C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x346840 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x346844 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x346848 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x34684C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x346850 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x346854 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x346858 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x34685C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x346860 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x346864 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x346868 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x34686C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x346870 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x346874 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x346878 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x34687C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x346880 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x346884 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x346888 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x34688C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x346890 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x346894 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x346898 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x34689C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3468A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3468A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3468A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3468AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3468B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3468B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3468B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3468BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3468C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3468C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3468C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3468CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3468D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3468D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3468D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3468DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3468E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3468E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3468E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3468EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3468F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3468F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3468F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3468FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x346900 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x346904 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x346908 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x34690C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x346910 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x346914 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x346918 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x34691C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x346920 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x346924 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x346928 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x34692C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x346930 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x346934 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x346938 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x34693C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x346940 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x346944 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x346948 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x34694C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x346950 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x346954 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x346958 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x34695C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x346960 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x346964 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x346968 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x34696C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x346970 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x346974 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x346978 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x34697C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x346980 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x346984 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x346988 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x34698C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x346990 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x346994 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x346998 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x34699C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3469A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3469A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3469A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3469AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3469B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3469B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3469B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3469BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3469C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3469C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3469C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3469CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3469D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3469D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3469D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3469DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3469E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3469E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3469E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3469EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3469F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3469F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3469F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3469FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x346A00 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x346A04 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x346A08 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x346A0C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x346A10 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x346A14 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x346A18 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x346A1C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x346A20 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x346A64 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x346A68 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x346A6C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x346A70 + +#define mmSIF_RTR_CTRL_4_RGL_CFG 0x346B64 + +#define mmSIF_RTR_CTRL_4_RGL_SHIFT 0x346B68 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x346B6C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x346B70 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x346B74 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x346B78 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x346B7C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x346B80 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x346B84 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x346B88 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_0 0x346BAC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_1 0x346BB0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_2 0x346BB4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_3 0x346BB8 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_4 0x346BBC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_5 0x346BC0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_6 0x346BC4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_7 0x346BC8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_0 0x346BEC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_1 0x346BF0 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_2 0x346BF4 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_3 0x346BF8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_4 0x346BFC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_5 0x346C00 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_6 0x346C04 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_7 0x346C08 + +#define mmSIF_RTR_CTRL_4_RGL_WDT 0x346C2C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x346C30 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x346C34 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x346C38 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x346C3C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x346C40 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x346C44 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x346C48 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x346C4C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x346C50 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x346C54 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x346C58 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x346C5C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x346C60 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x346C64 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x346C68 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x346C6C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x346C70 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x346C74 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x346C78 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x346C7C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x346C80 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x346C84 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x346C88 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x346C8C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x346C90 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x346C94 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x346C98 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x346C9C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x346CA0 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x346CA4 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x346CA8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x346CAC + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x346CB0 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x346CB4 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x346CB8 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x346CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000..6c27850ca --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_5_PERM_SEL 0x356108 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0 0x356114 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1 0x356118 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2 0x35611C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3 0x356120 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4 0x356124 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5 0x356128 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6 0x35612C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7 0x356130 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8 0x356134 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9 0x356138 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10 0x35613C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11 0x356140 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12 0x356144 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13 0x356148 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14 0x35614C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15 0x356150 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16 0x356154 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17 0x356158 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18 0x35615C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19 0x356160 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20 0x356164 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21 0x356168 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22 0x35616C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23 0x356170 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24 0x356174 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25 0x356178 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26 0x35617C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27 0x356180 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x356184 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x356188 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x35618C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x356190 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x356194 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x356198 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x35619C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3561A0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3561A4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3561A8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3561AC + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3561B0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3561B4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3561B8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3561BC + +#define mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x35626C + +#define mmSIF_RTR_CTRL_5_RL_HBM_EN 0x356274 + +#define mmSIF_RTR_CTRL_5_RL_HBM_SAT 0x356278 + +#define mmSIF_RTR_CTRL_5_RL_HBM_RST 0x35627C + +#define mmSIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x356280 + +#define mmSIF_RTR_CTRL_5_SCRAM_HBM_EN 0x356284 + +#define mmSIF_RTR_CTRL_5_RL_PCI_EN 0x356288 + +#define mmSIF_RTR_CTRL_5_RL_PCI_SAT 0x35628C + +#define mmSIF_RTR_CTRL_5_RL_PCI_RST 0x356290 + +#define mmSIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x356294 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_EN 0x35629C + +#define mmSIF_RTR_CTRL_5_RL_SRAM_SAT 0x3562A0 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RST 0x3562A4 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3562AC + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RED 0x3562B4 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_EN 0x3562EC + +#define mmSIF_RTR_CTRL_5_E2E_PCI_EN 0x3562F0 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3562F4 + +#define mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3562F8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x356404 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x356408 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x35640C + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x356410 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x356414 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x356418 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x35641C + +#define mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x356420 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x356424 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x356428 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x35642C + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x356430 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x356434 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x356438 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_0 0x356450 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_1 0x356454 + +#define mmSIF_RTR_CTRL_5_NON_LIN_EN 0x356480 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x356500 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x356504 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x356508 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x35650C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x356510 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x356514 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x356520 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x356524 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x356528 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x35652C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x356530 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x356534 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x356538 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x35653C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x356540 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x356550 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x356554 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x356558 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x35655C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x356560 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x356564 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x356568 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x35656C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x356570 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x356574 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x356578 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x35657C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x356580 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x356584 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x356588 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x35658C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x356590 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x356594 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x356598 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3565E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3565E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3565EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3565F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3565F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3565F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3565FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x356600 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x356604 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x356608 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x35660C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x356610 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x356614 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x356618 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x35661C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x356620 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x356624 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x356628 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x35662C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x356630 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x356634 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x356638 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x35663C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x356640 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x356644 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x356648 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x35664C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x356650 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x356654 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x356658 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x35665C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x356660 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x356664 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x356668 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x35666C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x356670 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x356674 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x356678 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x35667C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x356680 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x356684 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x356688 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x35668C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x356690 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x356694 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x356698 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x35669C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3566A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3566A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3566A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3566AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3566B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3566B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3566B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3566BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3566C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3566C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3566C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3566CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3566D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3566D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3566D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3566DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3566E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3566E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3566E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3566EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3566F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3566F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3566F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3566FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x356700 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x356704 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x356708 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x35670C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x356710 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x356714 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x356718 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x35671C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x356720 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x356724 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x356728 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x35672C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x356730 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x356734 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x356738 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x35673C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x356740 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x356744 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x356748 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x35674C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x356750 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x356754 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x356758 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x35675C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x356760 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x356764 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x356768 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x35676C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x356770 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x356774 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x356778 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x35677C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x356780 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x356784 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x356788 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x35678C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x356790 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x356794 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x356798 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x35679C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3567A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3567A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3567A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3567AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3567B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3567B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3567B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3567BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3567C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3567C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3567C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3567CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3567D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3567D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3567D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3567DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3567E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x356824 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x356828 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x35682C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x356830 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x356834 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x356838 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x35683C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x356840 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x356844 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x356848 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x35684C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x356850 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x356854 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x356858 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x35685C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x356860 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x356864 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x356868 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x35686C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x356870 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x356874 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x356878 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x35687C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x356880 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x356884 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x356888 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x35688C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x356890 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x356894 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x356898 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x35689C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3568A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3568A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3568A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3568AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3568B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3568B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3568B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3568BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3568C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3568C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3568C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3568CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3568D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3568D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3568D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3568DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3568E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3568E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3568E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3568EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3568F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3568F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3568F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3568FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x356900 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x356904 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x356908 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x35690C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x356910 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x356914 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x356918 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x35691C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x356920 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x356924 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x356928 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x35692C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x356930 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x356934 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x356938 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x35693C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x356940 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x356944 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x356948 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x35694C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x356950 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x356954 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x356958 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x35695C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x356960 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x356964 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x356968 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x35696C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x356970 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x356974 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x356978 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x35697C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x356980 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x356984 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x356988 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x35698C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x356990 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x356994 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x356998 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x35699C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3569A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3569A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3569A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3569AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3569B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3569B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3569B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3569BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3569C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3569C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3569C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3569CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3569D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3569D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3569D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3569DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3569E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3569E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3569E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3569EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3569F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3569F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3569F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3569FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x356A00 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x356A04 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x356A08 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x356A0C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x356A10 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x356A14 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x356A18 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x356A1C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x356A20 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x356A64 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x356A68 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x356A6C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x356A70 + +#define mmSIF_RTR_CTRL_5_RGL_CFG 0x356B64 + +#define mmSIF_RTR_CTRL_5_RGL_SHIFT 0x356B68 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x356B6C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x356B70 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x356B74 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x356B78 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x356B7C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x356B80 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x356B84 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x356B88 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_0 0x356BAC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_1 0x356BB0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_2 0x356BB4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_3 0x356BB8 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_4 0x356BBC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_5 0x356BC0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_6 0x356BC4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_7 0x356BC8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_0 0x356BEC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_1 0x356BF0 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_2 0x356BF4 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_3 0x356BF8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_4 0x356BFC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_5 0x356C00 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_6 0x356C04 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_7 0x356C08 + +#define mmSIF_RTR_CTRL_5_RGL_WDT 0x356C2C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x356C30 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x356C34 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x356C38 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x356C3C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x356C40 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x356C44 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x356C48 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x356C4C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x356C50 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x356C54 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x356C58 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x356C5C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x356C60 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x356C64 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x356C68 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x356C6C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x356C70 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x356C74 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x356C78 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x356C7C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x356C80 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x356C84 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x356C88 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x356C8C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x356C90 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x356C94 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x356C98 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x356C9C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x356CA0 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x356CA4 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x356CA8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x356CAC + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x356CB0 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x356CB4 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x356CB8 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x356CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000..a9ea89aa6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_6_PERM_SEL 0x366108 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_0 0x366114 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_1 0x366118 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_2 0x36611C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_3 0x366120 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_4 0x366124 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_5 0x366128 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_6 0x36612C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_7 0x366130 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_8 0x366134 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_9 0x366138 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_10 0x36613C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_11 0x366140 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_12 0x366144 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_13 0x366148 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_14 0x36614C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_15 0x366150 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_16 0x366154 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_17 0x366158 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_18 0x36615C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_19 0x366160 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_20 0x366164 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_21 0x366168 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_22 0x36616C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_23 0x366170 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_24 0x366174 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_25 0x366178 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_26 0x36617C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_27 0x366180 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x366184 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x366188 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x36618C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x366190 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x366194 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x366198 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x36619C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3661A0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3661A4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3661A8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3661AC + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3661B0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3661B4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3661B8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3661BC + +#define mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x36626C + +#define mmSIF_RTR_CTRL_6_RL_HBM_EN 0x366274 + +#define mmSIF_RTR_CTRL_6_RL_HBM_SAT 0x366278 + +#define mmSIF_RTR_CTRL_6_RL_HBM_RST 0x36627C + +#define mmSIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x366280 + +#define mmSIF_RTR_CTRL_6_SCRAM_HBM_EN 0x366284 + +#define mmSIF_RTR_CTRL_6_RL_PCI_EN 0x366288 + +#define mmSIF_RTR_CTRL_6_RL_PCI_SAT 0x36628C + +#define mmSIF_RTR_CTRL_6_RL_PCI_RST 0x366290 + +#define mmSIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x366294 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_EN 0x36629C + +#define mmSIF_RTR_CTRL_6_RL_SRAM_SAT 0x3662A0 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RST 0x3662A4 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3662AC + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RED 0x3662B4 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_EN 0x3662EC + +#define mmSIF_RTR_CTRL_6_E2E_PCI_EN 0x3662F0 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3662F4 + +#define mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3662F8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x366404 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x366408 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x36640C + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x366410 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x366414 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x366418 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x36641C + +#define mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x366420 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x366424 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x366428 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x36642C + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x366430 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x366434 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x366438 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_0 0x366450 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_1 0x366454 + +#define mmSIF_RTR_CTRL_6_NON_LIN_EN 0x366480 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x366500 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x366504 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x366508 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x36650C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x366510 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x366514 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x366520 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x366524 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x366528 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x36652C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x366530 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x366534 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x366538 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x36653C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x366540 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x366550 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x366554 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x366558 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x36655C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x366560 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x366564 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x366568 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x36656C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x366570 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x366574 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x366578 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x36657C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x366580 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x366584 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x366588 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x36658C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x366590 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x366594 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x366598 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3665E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3665E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3665EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3665F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3665F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3665F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3665FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x366600 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x366604 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x366608 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x36660C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x366610 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x366614 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x366618 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x36661C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x366620 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x366624 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x366628 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x36662C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x366630 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x366634 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x366638 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x36663C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x366640 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x366644 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x366648 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x36664C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x366650 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x366654 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x366658 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x36665C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x366660 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x366664 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x366668 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x36666C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x366670 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x366674 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x366678 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x36667C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x366680 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x366684 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x366688 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x36668C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x366690 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x366694 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x366698 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x36669C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3666A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3666A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3666A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3666AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3666B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3666B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3666B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3666BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3666C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3666C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3666C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3666CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3666D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3666D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3666D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3666DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3666E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3666E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3666E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3666EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3666F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3666F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3666F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3666FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x366700 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x366704 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x366708 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x36670C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x366710 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x366714 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x366718 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x36671C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x366720 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x366724 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x366728 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x36672C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x366730 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x366734 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x366738 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x36673C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x366740 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x366744 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x366748 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x36674C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x366750 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x366754 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x366758 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x36675C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x366760 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x366764 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x366768 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x36676C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x366770 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x366774 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x366778 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x36677C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x366780 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x366784 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x366788 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x36678C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x366790 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x366794 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x366798 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x36679C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3667A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3667A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3667A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3667AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3667B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3667B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3667B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3667BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3667C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3667C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3667C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3667CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3667D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3667D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3667D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3667DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3667E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x366824 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x366828 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x36682C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x366830 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x366834 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x366838 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x36683C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x366840 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x366844 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x366848 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x36684C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x366850 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x366854 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x366858 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x36685C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x366860 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x366864 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x366868 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x36686C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x366870 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x366874 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x366878 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x36687C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x366880 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x366884 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x366888 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x36688C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x366890 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x366894 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x366898 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x36689C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3668A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3668A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3668A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3668AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3668B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3668B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3668B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3668BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3668C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3668C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3668C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3668CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3668D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3668D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3668D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3668DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3668E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3668E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3668E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3668EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3668F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3668F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3668F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3668FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x366900 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x366904 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x366908 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x36690C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x366910 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x366914 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x366918 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x36691C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x366920 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x366924 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x366928 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x36692C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x366930 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x366934 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x366938 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x36693C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x366940 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x366944 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x366948 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x36694C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x366950 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x366954 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x366958 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x36695C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x366960 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x366964 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x366968 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x36696C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x366970 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x366974 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x366978 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x36697C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x366980 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x366984 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x366988 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x36698C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x366990 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x366994 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x366998 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x36699C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3669A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3669A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3669A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3669AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3669B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3669B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3669B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3669BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3669C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3669C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3669C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3669CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3669D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3669D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3669D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3669DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3669E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3669E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3669E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3669EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3669F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3669F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3669F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3669FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x366A00 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x366A04 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x366A08 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x366A0C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x366A10 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x366A14 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x366A18 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x366A1C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x366A20 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x366A64 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x366A68 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x366A6C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x366A70 + +#define mmSIF_RTR_CTRL_6_RGL_CFG 0x366B64 + +#define mmSIF_RTR_CTRL_6_RGL_SHIFT 0x366B68 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x366B6C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x366B70 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x366B74 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x366B78 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x366B7C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x366B80 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x366B84 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x366B88 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_0 0x366BAC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_1 0x366BB0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_2 0x366BB4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_3 0x366BB8 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_4 0x366BBC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_5 0x366BC0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_6 0x366BC4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_7 0x366BC8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_0 0x366BEC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_1 0x366BF0 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_2 0x366BF4 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_3 0x366BF8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_4 0x366BFC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_5 0x366C00 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_6 0x366C04 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_7 0x366C08 + +#define mmSIF_RTR_CTRL_6_RGL_WDT 0x366C2C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x366C30 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x366C34 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x366C38 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x366C3C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x366C40 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x366C44 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x366C48 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x366C4C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x366C50 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x366C54 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x366C58 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x366C5C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x366C60 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x366C64 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x366C68 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x366C6C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x366C70 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x366C74 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x366C78 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x366C7C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x366C80 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x366C84 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x366C88 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x366C8C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x366C90 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x366C94 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x366C98 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x366C9C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x366CA0 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x366CA4 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x366CA8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x366CAC + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x366CB0 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x366CB4 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x366CB8 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x366CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000..a37772c53 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_7_PERM_SEL 0x376108 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_0 0x376114 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_1 0x376118 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_2 0x37611C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_3 0x376120 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_4 0x376124 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_5 0x376128 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_6 0x37612C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_7 0x376130 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_8 0x376134 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_9 0x376138 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_10 0x37613C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_11 0x376140 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_12 0x376144 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_13 0x376148 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_14 0x37614C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_15 0x376150 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_16 0x376154 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_17 0x376158 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_18 0x37615C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_19 0x376160 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_20 0x376164 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_21 0x376168 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_22 0x37616C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_23 0x376170 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_24 0x376174 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_25 0x376178 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_26 0x37617C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_27 0x376180 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x376184 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x376188 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x37618C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x376190 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x376194 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x376198 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x37619C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3761A0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3761A4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3761A8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3761AC + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3761B0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3761B4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3761B8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3761BC + +#define mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x37626C + +#define mmSIF_RTR_CTRL_7_RL_HBM_EN 0x376274 + +#define mmSIF_RTR_CTRL_7_RL_HBM_SAT 0x376278 + +#define mmSIF_RTR_CTRL_7_RL_HBM_RST 0x37627C + +#define mmSIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x376280 + +#define mmSIF_RTR_CTRL_7_SCRAM_HBM_EN 0x376284 + +#define mmSIF_RTR_CTRL_7_RL_PCI_EN 0x376288 + +#define mmSIF_RTR_CTRL_7_RL_PCI_SAT 0x37628C + +#define mmSIF_RTR_CTRL_7_RL_PCI_RST 0x376290 + +#define mmSIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x376294 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_EN 0x37629C + +#define mmSIF_RTR_CTRL_7_RL_SRAM_SAT 0x3762A0 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RST 0x3762A4 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3762AC + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RED 0x3762B4 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_EN 0x3762EC + +#define mmSIF_RTR_CTRL_7_E2E_PCI_EN 0x3762F0 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3762F4 + +#define mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3762F8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x376404 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x376408 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x37640C + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x376410 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x376414 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x376418 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x37641C + +#define mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x376420 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x376424 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x376428 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x37642C + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x376430 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x376434 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x376438 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_0 0x376450 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_1 0x376454 + +#define mmSIF_RTR_CTRL_7_NON_LIN_EN 0x376480 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x376500 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x376504 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x376508 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x37650C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x376510 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x376514 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x376520 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x376524 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x376528 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x37652C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x376530 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x376534 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x376538 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x37653C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x376540 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x376550 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x376554 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x376558 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x37655C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x376560 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x376564 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x376568 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x37656C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x376570 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x376574 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x376578 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x37657C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x376580 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x376584 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x376588 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x37658C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x376590 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x376594 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x376598 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3765E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3765E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3765EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3765F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3765F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3765F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3765FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x376600 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x376604 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x376608 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x37660C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x376610 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x376614 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x376618 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x37661C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x376620 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x376624 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x376628 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x37662C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x376630 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x376634 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x376638 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x37663C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x376640 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x376644 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x376648 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x37664C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x376650 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x376654 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x376658 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x37665C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x376660 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x376664 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x376668 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x37666C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x376670 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x376674 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x376678 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x37667C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x376680 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x376684 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x376688 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x37668C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x376690 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x376694 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x376698 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x37669C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3766A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3766A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3766A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3766AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3766B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3766B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3766B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3766BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3766C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3766C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3766C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3766CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3766D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3766D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3766D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3766DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3766E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3766E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3766E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3766EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3766F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3766F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3766F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3766FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x376700 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x376704 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x376708 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x37670C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x376710 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x376714 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x376718 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x37671C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x376720 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x376724 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x376728 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x37672C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x376730 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x376734 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x376738 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x37673C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x376740 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x376744 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x376748 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x37674C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x376750 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x376754 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x376758 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x37675C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x376760 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x376764 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x376768 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x37676C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x376770 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x376774 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x376778 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x37677C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x376780 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x376784 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x376788 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x37678C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x376790 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x376794 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x376798 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x37679C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3767A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3767A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3767A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3767AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3767B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3767B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3767B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3767BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3767C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3767C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3767C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3767CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3767D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3767D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3767D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3767DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3767E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x376824 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x376828 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x37682C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x376830 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x376834 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x376838 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x37683C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x376840 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x376844 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x376848 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x37684C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x376850 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x376854 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x376858 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x37685C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x376860 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x376864 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x376868 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x37686C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x376870 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x376874 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x376878 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x37687C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x376880 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x376884 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x376888 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x37688C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x376890 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x376894 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x376898 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x37689C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3768A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3768A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3768A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3768AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3768B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3768B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3768B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3768BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3768C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3768C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3768C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3768CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3768D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3768D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3768D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3768DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3768E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3768E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3768E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3768EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3768F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3768F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3768F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3768FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x376900 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x376904 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x376908 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x37690C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x376910 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x376914 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x376918 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x37691C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x376920 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x376924 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x376928 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x37692C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x376930 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x376934 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x376938 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x37693C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x376940 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x376944 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x376948 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x37694C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x376950 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x376954 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x376958 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x37695C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x376960 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x376964 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x376968 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x37696C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x376970 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x376974 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x376978 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x37697C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x376980 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x376984 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x376988 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x37698C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x376990 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x376994 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x376998 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x37699C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3769A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3769A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3769A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3769AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3769B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3769B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3769B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3769BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3769C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3769C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3769C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3769CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3769D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3769D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3769D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3769DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3769E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3769E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3769E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3769EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3769F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3769F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3769F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3769FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x376A00 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x376A04 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x376A08 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x376A0C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x376A10 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x376A14 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x376A18 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x376A1C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x376A20 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x376A64 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x376A68 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x376A6C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x376A70 + +#define mmSIF_RTR_CTRL_7_RGL_CFG 0x376B64 + +#define mmSIF_RTR_CTRL_7_RGL_SHIFT 0x376B68 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x376B6C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x376B70 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x376B74 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x376B78 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x376B7C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x376B80 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x376B84 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x376B88 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_0 0x376BAC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_1 0x376BB0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_2 0x376BB4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_3 0x376BB8 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_4 0x376BBC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_5 0x376BC0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_6 0x376BC4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_7 0x376BC8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_0 0x376BEC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_1 0x376BF0 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_2 0x376BF4 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_3 0x376BF8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_4 0x376BFC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_5 0x376C00 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_6 0x376C04 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_7 0x376C08 + +#define mmSIF_RTR_CTRL_7_RGL_WDT 0x376C2C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x376C30 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x376C34 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x376C38 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x376C3C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x376C40 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x376C44 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x376C48 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x376C4C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x376C50 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x376C54 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x376C58 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x376C5C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x376C60 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x376C64 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x376C68 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x376C6C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x376C70 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x376C74 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x376C78 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x376C7C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x376C80 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x376C84 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x376C88 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x376C8C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x376C90 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x376C94 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x376C98 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x376C9C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x376CA0 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x376CA4 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x376CA8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x376CAC + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x376CB0 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x376CB4 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x376CB8 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x376CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h new file mode 100644 index 000000000..07d2a9000 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0xC12010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0xC12014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0xC12018 + +#define mmSTLB_STLB_FEATURE_EN 0xC1201C + +#define mmSTLB_STLB_AXI_CACHE 0xC12020 + +#define mmSTLB_HOP_CONFIGURATION 0xC12024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0xC12028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0xC1202C + +#define mmSTLB_LINK_LIST 0xC12030 + +#define mmSTLB_INV_ALL_START 0xC12034 + +#define mmSTLB_INV_ALL_SET 0xC12038 + +#define mmSTLB_INV_PS 0xC1203C + +#define mmSTLB_INV_CONSUMER_INDEX 0xC12040 + +#define mmSTLB_INV_HIT_COUNT 0xC12044 + +#define mmSTLB_INV_SET 0xC12048 + +#define mmSTLB_SRAM_INIT 0xC1204C + +#define mmSTLB_MEM_CACHE_INVALIDATION 0xC12050 + +#define mmSTLB_MEM_CACHE_INV_STATUS 0xC12054 + +#define mmSTLB_MEM_CACHE_BASE_38_7 0xC12058 + +#define mmSTLB_MEM_CACHE_BASE_49_39 0xC1205C + +#define mmSTLB_MEM_CACHE_CONFIG 0xC12060 + +#define mmSTLB_SET_THRESHOLD_HOP4 0xC12064 + +#define mmSTLB_SET_THRESHOLD_HOP3 0xC12068 + +#define mmSTLB_SET_THRESHOLD_HOP2 0xC1206C + +#define mmSTLB_SET_THRESHOLD_HOP1 0xC12070 + +#define mmSTLB_SET_THRESHOLD_HOP0 0xC12074 + +#define mmSTLB_MULTI_HIT_INTERRUPT_CLR 0xC12078 + +#define mmSTLB_MULTI_HIT_INTERRUPT_MASK 0xC1207C + +#define mmSTLB_MEM_L0_CACHE_CFG 0xC12080 + +#define mmSTLB_MEM_READ_ARPROT 0xC12084 + +#endif /* ASIC_REG_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h new file mode 100644 index 000000000..8f67c11c8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h @@ -0,0 +1,2578 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_MASKS_H_ +#define ASIC_REG_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_CONFIG */ +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_KERNEL_KERNEL_ID */ +#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_KERNEL_SRF */ +#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ROUND_CSR */ +#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* TPC0_CFG_PROT */ +#define TPC0_CFG_PROT_AWPROT_SHIFT 0 +#define TPC0_CFG_PROT_AWPROT_MASK 0x7 +#define TPC0_CFG_PROT_ARPROT_SHIFT 3 +#define TPC0_CFG_PROT_ARPROT_MASK 0x38 + +/* TPC0_CFG_SEMAPHORE */ +#define TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_VFLAGS */ +#define TPC0_CFG_VFLAGS_V_SHIFT 0 +#define TPC0_CFG_VFLAGS_V_MASK 0xF + +/* TPC0_CFG_SFLAGS */ +#define TPC0_CFG_SFLAGS_V_SHIFT 0 +#define TPC0_CFG_SFLAGS_V_MASK 0xF + +/* TPC0_CFG_LFSR_POLYNOM */ +#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_STATUS */ +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_CMD */ +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* TPC0_CFG_TPC_EXECUTE */ +#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* TPC0_CFG_TPC_STALL */ +#define TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_RD_RATE_LIMIT */ +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_WR_RATE_LIMIT */ +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_MSS_CONFIG */ +#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* TPC0_CFG_TPC_INTR_CAUSE */ +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF + +/* TPC0_CFG_TPC_INTR_MASK */ +#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF + +/* TPC0_CFG_WQ_CREDITS */ +#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* TPC0_CFG_ARUSER_LO */ +#define TPC0_CFG_ARUSER_LO_V_SHIFT 0 +#define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_ARUSER_HI */ +#define TPC0_CFG_ARUSER_HI_V_SHIFT 11 +#define TPC0_CFG_ARUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_AWUSER_LO */ +#define TPC0_CFG_AWUSER_LO_V_SHIFT 0 +#define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_AWUSER_HI */ +#define TPC0_CFG_AWUSER_HI_V_SHIFT 11 +#define TPC0_CFG_AWUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_OPCODE_EXEC */ +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* TPC0_CFG_TSB_CFG */ +#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 0 +#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x1 +#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE + +/* TPC0_CFG_DBGMEM_ADD */ +#define TPC0_CFG_DBGMEM_ADD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_WR */ +#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_RD */ +#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_CTRL */ +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* TPC0_CFG_DBGMEM_RC */ +#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 0 +#define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x1 + +/* TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF0000 + +/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_FUNC_MBIST_CNTRL */ +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 + +/* TPC0_CFG_FUNC_MBIST_PAT */ +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 + +/* TPC0_CFG_FUNC_MBIST_MEM */ +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_0 */ +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_0 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_1 */ +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_1 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_2 */ +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_2 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_3 */ +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_3 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_4 */ +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_4 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_CONFIG */ +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_QM_KERNEL_ID */ +#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_QM_SRF */ +#define TPC0_CFG_QM_SRF_V_SHIFT 0 +#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h new file mode 100644 index 000000000..b82a90626 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_REGS_H_ +#define ASIC_REG_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC + +#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780 + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4 + +#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8 + +#define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC + +#define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0 + +#define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4 + +#define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8 + +#define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC + +#define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0 + +#define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4 + +#define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8 + +#define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC + +#define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0 + +#define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4 + +#define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8 + +#define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC + +#define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0 + +#define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4 + +#define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8 + +#define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC + +#define mmTPC0_CFG_KERNEL_SRF_16 0xE06800 + +#define mmTPC0_CFG_KERNEL_SRF_17 0xE06804 + +#define mmTPC0_CFG_KERNEL_SRF_18 0xE06808 + +#define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C + +#define mmTPC0_CFG_KERNEL_SRF_20 0xE06810 + +#define mmTPC0_CFG_KERNEL_SRF_21 0xE06814 + +#define mmTPC0_CFG_KERNEL_SRF_22 0xE06818 + +#define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C + +#define mmTPC0_CFG_KERNEL_SRF_24 0xE06820 + +#define mmTPC0_CFG_KERNEL_SRF_25 0xE06824 + +#define mmTPC0_CFG_KERNEL_SRF_26 0xE06828 + +#define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C + +#define mmTPC0_CFG_KERNEL_SRF_28 0xE06830 + +#define mmTPC0_CFG_KERNEL_SRF_29 0xE06834 + +#define mmTPC0_CFG_KERNEL_SRF_30 0xE06838 + +#define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C + +#define mmTPC0_CFG_ROUND_CSR 0xE068FC + +#define mmTPC0_CFG_PROT 0xE06900 + +#define mmTPC0_CFG_SEMAPHORE 0xE06908 + +#define mmTPC0_CFG_VFLAGS 0xE0690C + +#define mmTPC0_CFG_SFLAGS 0xE06910 + +#define mmTPC0_CFG_LFSR_POLYNOM 0xE06918 + +#define mmTPC0_CFG_STATUS 0xE0691C + +#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920 + +#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C + +#define mmTPC0_CFG_TPC_CMD 0xE06930 + +#define mmTPC0_CFG_TPC_EXECUTE 0xE06938 + +#define mmTPC0_CFG_TPC_STALL 0xE0693C + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940 + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944 + +#define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948 + +#define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950 + +#define mmTPC0_CFG_MSS_CONFIG 0xE06954 + +#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958 + +#define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C + +#define mmTPC0_CFG_WQ_CREDITS 0xE06960 + +#define mmTPC0_CFG_ARUSER_LO 0xE06964 + +#define mmTPC0_CFG_ARUSER_HI 0xE06968 + +#define mmTPC0_CFG_AWUSER_LO 0xE0696C + +#define mmTPC0_CFG_AWUSER_HI 0xE06970 + +#define mmTPC0_CFG_OPCODE_EXEC 0xE06974 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980 + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990 + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994 + +#define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998 + +#define mmTPC0_CFG_TSB_CFG 0xE0699C + +#define mmTPC0_CFG_DBGMEM_ADD 0xE069A0 + +#define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4 + +#define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8 + +#define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC + +#define mmTPC0_CFG_DBGMEM_RC 0xE069B0 + +#define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4 + +#define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8 + +#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC + +#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0 + +#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4 + +#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0 + +#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 + +#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 + +#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C + +#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40 + +#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74 + +#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78 + +#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC + +#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0 + +#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0 + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4 + +#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8 + +#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C + +#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20 + +#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54 + +#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58 + +#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C + +#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90 + +#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0 + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4 + +#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8 + +#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC + +#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00 + +#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30 + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34 + +#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38 + +#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C + +#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70 + +#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0 + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4 + +#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8 + +#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC + +#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0 + +#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10 + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14 + +#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18 + +#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C + +#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50 + +#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C + +#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80 + +#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC + +#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4 + +#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8 + +#define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC + +#define mmTPC0_CFG_QM_SRF_0 0xE06DC0 + +#define mmTPC0_CFG_QM_SRF_1 0xE06DC4 + +#define mmTPC0_CFG_QM_SRF_2 0xE06DC8 + +#define mmTPC0_CFG_QM_SRF_3 0xE06DCC + +#define mmTPC0_CFG_QM_SRF_4 0xE06DD0 + +#define mmTPC0_CFG_QM_SRF_5 0xE06DD4 + +#define mmTPC0_CFG_QM_SRF_6 0xE06DD8 + +#define mmTPC0_CFG_QM_SRF_7 0xE06DDC + +#define mmTPC0_CFG_QM_SRF_8 0xE06DE0 + +#define mmTPC0_CFG_QM_SRF_9 0xE06DE4 + +#define mmTPC0_CFG_QM_SRF_10 0xE06DE8 + +#define mmTPC0_CFG_QM_SRF_11 0xE06DEC + +#define mmTPC0_CFG_QM_SRF_12 0xE06DF0 + +#define mmTPC0_CFG_QM_SRF_13 0xE06DF4 + +#define mmTPC0_CFG_QM_SRF_14 0xE06DF8 + +#define mmTPC0_CFG_QM_SRF_15 0xE06DFC + +#define mmTPC0_CFG_QM_SRF_16 0xE06E00 + +#define mmTPC0_CFG_QM_SRF_17 0xE06E04 + +#define mmTPC0_CFG_QM_SRF_18 0xE06E08 + +#define mmTPC0_CFG_QM_SRF_19 0xE06E0C + +#define mmTPC0_CFG_QM_SRF_20 0xE06E10 + +#define mmTPC0_CFG_QM_SRF_21 0xE06E14 + +#define mmTPC0_CFG_QM_SRF_22 0xE06E18 + +#define mmTPC0_CFG_QM_SRF_23 0xE06E1C + +#define mmTPC0_CFG_QM_SRF_24 0xE06E20 + +#define mmTPC0_CFG_QM_SRF_25 0xE06E24 + +#define mmTPC0_CFG_QM_SRF_26 0xE06E28 + +#define mmTPC0_CFG_QM_SRF_27 0xE06E2C + +#define mmTPC0_CFG_QM_SRF_28 0xE06E30 + +#define mmTPC0_CFG_QM_SRF_29 0xE06E34 + +#define mmTPC0_CFG_QM_SRF_30 0xE06E38 + +#define mmTPC0_CFG_QM_SRF_31 0xE06E3C + +#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h new file mode 100644 index 000000000..8e71532c6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_MASKS_H_ +#define ASIC_REG_TPC0_QM_MASKS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +/* TPC0_QM_GLBL_CFG0 */ +#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* TPC0_QM_GLBL_CFG1 */ +#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* TPC0_QM_GLBL_PROT */ +#define TPC0_QM_GLBL_PROT_PQF_SHIFT 0 +#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF +#define TPC0_QM_GLBL_PROT_CQF_SHIFT 4 +#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define TPC0_QM_GLBL_PROT_CP_SHIFT 9 +#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define TPC0_QM_GLBL_PROT_ERR_SHIFT 14 +#define TPC0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_PROT_ARB_SHIFT 15 +#define TPC0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* TPC0_QM_GLBL_ERR_CFG */ +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* TPC0_QM_GLBL_SECURE_PROPS */ +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_NON_SECURE_PROPS */ +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_STS0 */ +#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* TPC0_QM_GLBL_STS1 */ +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_STS1_4 */ +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN */ +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN_4 */ +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_PQ_BASE_LO */ +#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BASE_HI */ +#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_SIZE */ +#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 +#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PI */ +#define TPC0_QM_PQ_PI_VAL_SHIFT 0 +#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CI */ +#define TPC0_QM_PQ_CI_VAL_SHIFT 0 +#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CFG0 */ +#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_PQ_CFG1 */ +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_ARUSER_31_11 */ +#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_PQ_STS0 */ +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS1 */ +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_CFG0 */ +#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_CQ_CFG1 */ +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_ARUSER_31_11 */ +#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CQ_STS0 */ +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS1 */ +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_PTR_LO_0 */ +#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_0 */ +#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_0 */ +#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_0 */ +#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_1 */ +#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_1 */ +#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_1 */ +#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_1 */ +#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_2 */ +#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_2 */ +#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_2 */ +#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_2 */ +#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_3 */ +#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_3 */ +#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_3 */ +#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_3 */ +#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_4 */ +#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_4 */ +#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_4 */ +#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_4 */ +#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_STS */ +#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_STS */ +#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_STS */ +#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_STS */ +#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_IFIFO_CNT */ +#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_FENCE0_RDATA */ +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE1_RDATA */ +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE2_RDATA */ +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE3_RDATA */ +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE0_CNT */ +#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE1_CNT */ +#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE2_CNT */ +#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE3_CNT */ +#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_STS */ +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CP_STS_ERDY_SHIFT 16 +#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 +#define TPC0_QM_CP_STS_RRDY_SHIFT 17 +#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 +#define TPC0_QM_CP_STS_MRDY_SHIFT 18 +#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 +#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_QM_CP_CURRENT_INST_LO */ +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_CURRENT_INST_HI */ +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_BARRIER_CFG */ +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* TPC0_QM_CP_DBG_0 */ +#define TPC0_QM_CP_DBG_0_CS_SHIFT 0 +#define TPC0_QM_CP_DBG_0_CS_MASK 0xF +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7 +#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* TPC0_QM_CP_ARUSER_31_11 */ +#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CP_AWUSER_31_11 */ +#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_CFG_0 */ +#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8 +#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100 +#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* TPC0_QM_ARB_CHOISE_Q_PUSH */ +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* TPC0_QM_ARB_WRR_WEIGHT */ +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CFG_1 */ +#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* TPC0_QM_ARB_MST_AVAIL_CRED */ +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MST_CRED_INC */ +#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_SLAVE_EN */ +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_QUIET_PER */ +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_CHOISE_WDT */ +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_ID */ +#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */ +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* TPC0_QM_ARB_MSG_AWUSER_31_11 */ +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_BASE_LO */ +#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_BASE_HI */ +#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_STATE_STS */ +#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */ +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MSG_STS */ +#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* TPC0_QM_ARB_ERR_CAUSE */ +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_MSG_EN */ +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_STS_DRP */ +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* TPC0_QM_ARB_MST_CRED_STS */ +#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* TPC0_QM_CGM_CFG */ +#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define TPC0_QM_CGM_CFG_EN_SHIFT 31 +#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* TPC0_QM_CGM_STS */ +#define TPC0_QM_CGM_STS_ST_SHIFT 0 +#define TPC0_QM_CGM_STS_ST_MASK 0x3 +#define TPC0_QM_CGM_STS_CG_SHIFT 4 +#define TPC0_QM_CGM_STS_CG_MASK 0x10 +#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* TPC0_QM_CGM_CFG1 */ +#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* TPC0_QM_LOCAL_RANGE_BASE */ +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* TPC0_QM_LOCAL_RANGE_SIZE */ +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* TPC0_QM_CSMR_STRICT_PRIO_CFG */ +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_GLBL_AXCACHE */ +#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* TPC0_QM_IND_GW_APB_CFG */ +#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* TPC0_QM_IND_GW_APB_WDATA */ +#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_RDATA */ +#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_STATUS */ +#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* TPC0_QM_GLBL_ERR_ADDR_LO */ +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_ADDR_HI */ +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_WDATA */ +#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_MEM_INIT_BUSY */ +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000..f9e310ab6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034 + +#define mmTPC0_QM_GLBL_STS0 0xE08038 + +#define mmTPC0_QM_GLBL_STS1_0 0xE08040 + +#define mmTPC0_QM_GLBL_STS1_1 0xE08044 + +#define mmTPC0_QM_GLBL_STS1_2 0xE08048 + +#define mmTPC0_QM_GLBL_STS1_3 0xE0804C + +#define mmTPC0_QM_GLBL_STS1_4 0xE08050 + +#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054 + +#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058 + +#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C + +#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060 + +#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068 + +#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070 + +#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074 + +#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078 + +#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C + +#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080 + +#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084 + +#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088 + +#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C + +#define mmTPC0_QM_PQ_SIZE_0 0xE08090 + +#define mmTPC0_QM_PQ_SIZE_1 0xE08094 + +#define mmTPC0_QM_PQ_SIZE_2 0xE08098 + +#define mmTPC0_QM_PQ_SIZE_3 0xE0809C + +#define mmTPC0_QM_PQ_PI_0 0xE080A0 + +#define mmTPC0_QM_PQ_PI_1 0xE080A4 + +#define mmTPC0_QM_PQ_PI_2 0xE080A8 + +#define mmTPC0_QM_PQ_PI_3 0xE080AC + +#define mmTPC0_QM_PQ_CI_0 0xE080B0 + +#define mmTPC0_QM_PQ_CI_1 0xE080B4 + +#define mmTPC0_QM_PQ_CI_2 0xE080B8 + +#define mmTPC0_QM_PQ_CI_3 0xE080BC + +#define mmTPC0_QM_PQ_CFG0_0 0xE080C0 + +#define mmTPC0_QM_PQ_CFG0_1 0xE080C4 + +#define mmTPC0_QM_PQ_CFG0_2 0xE080C8 + +#define mmTPC0_QM_PQ_CFG0_3 0xE080CC + +#define mmTPC0_QM_PQ_CFG1_0 0xE080D0 + +#define mmTPC0_QM_PQ_CFG1_1 0xE080D4 + +#define mmTPC0_QM_PQ_CFG1_2 0xE080D8 + +#define mmTPC0_QM_PQ_CFG1_3 0xE080DC + +#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0 + +#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4 + +#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8 + +#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC + +#define mmTPC0_QM_PQ_STS0_0 0xE080F0 + +#define mmTPC0_QM_PQ_STS0_1 0xE080F4 + +#define mmTPC0_QM_PQ_STS0_2 0xE080F8 + +#define mmTPC0_QM_PQ_STS0_3 0xE080FC + +#define mmTPC0_QM_PQ_STS1_0 0xE08100 + +#define mmTPC0_QM_PQ_STS1_1 0xE08104 + +#define mmTPC0_QM_PQ_STS1_2 0xE08108 + +#define mmTPC0_QM_PQ_STS1_3 0xE0810C + +#define mmTPC0_QM_CQ_CFG0_0 0xE08110 + +#define mmTPC0_QM_CQ_CFG0_1 0xE08114 + +#define mmTPC0_QM_CQ_CFG0_2 0xE08118 + +#define mmTPC0_QM_CQ_CFG0_3 0xE0811C + +#define mmTPC0_QM_CQ_CFG0_4 0xE08120 + +#define mmTPC0_QM_CQ_CFG1_0 0xE08124 + +#define mmTPC0_QM_CQ_CFG1_1 0xE08128 + +#define mmTPC0_QM_CQ_CFG1_2 0xE0812C + +#define mmTPC0_QM_CQ_CFG1_3 0xE08130 + +#define mmTPC0_QM_CQ_CFG1_4 0xE08134 + +#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138 + +#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C + +#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140 + +#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144 + +#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148 + +#define mmTPC0_QM_CQ_STS0_0 0xE0814C + +#define mmTPC0_QM_CQ_STS0_1 0xE08150 + +#define mmTPC0_QM_CQ_STS0_2 0xE08154 + +#define mmTPC0_QM_CQ_STS0_3 0xE08158 + +#define mmTPC0_QM_CQ_STS0_4 0xE0815C + +#define mmTPC0_QM_CQ_STS1_0 0xE08160 + +#define mmTPC0_QM_CQ_STS1_1 0xE08164 + +#define mmTPC0_QM_CQ_STS1_2 0xE08168 + +#define mmTPC0_QM_CQ_STS1_3 0xE0816C + +#define mmTPC0_QM_CQ_STS1_4 0xE08170 + +#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174 + +#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178 + +#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C + +#define mmTPC0_QM_CQ_CTL_0 0xE08180 + +#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184 + +#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188 + +#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C + +#define mmTPC0_QM_CQ_CTL_1 0xE08190 + +#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194 + +#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198 + +#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C + +#define mmTPC0_QM_CQ_CTL_2 0xE081A0 + +#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4 + +#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8 + +#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC + +#define mmTPC0_QM_CQ_CTL_3 0xE081B0 + +#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4 + +#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8 + +#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC + +#define mmTPC0_QM_CQ_CTL_4 0xE081C0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4 + +#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8 + +#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC + +#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8 + +#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC + +#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0 + +#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8 + +#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC + +#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0 + +#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4 + +#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8 + +#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC + +#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200 + +#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204 + +#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208 + +#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C + +#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210 + +#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214 + +#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218 + +#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C + +#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220 + +#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304 + +#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308 + +#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C + +#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310 + +#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314 + +#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318 + +#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C + +#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320 + +#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324 + +#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328 + +#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C + +#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330 + +#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334 + +#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338 + +#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C + +#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340 + +#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344 + +#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348 + +#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C + +#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350 + +#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354 + +#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358 + +#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C + +#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360 + +#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364 + +#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368 + +#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C + +#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370 + +#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374 + +#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378 + +#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C + +#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380 + +#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384 + +#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388 + +#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C + +#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390 + +#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394 + +#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398 + +#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C + +#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0 + +#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4 + +#define mmTPC0_QM_CP_STS_0 0xE083A8 + +#define mmTPC0_QM_CP_STS_1 0xE083AC + +#define mmTPC0_QM_CP_STS_2 0xE083B0 + +#define mmTPC0_QM_CP_STS_3 0xE083B4 + +#define mmTPC0_QM_CP_STS_4 0xE083B8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC + +#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0 + +#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4 + +#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8 + +#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC + +#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400 + +#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404 + +#define mmTPC0_QM_CP_DBG_0_0 0xE08408 + +#define mmTPC0_QM_CP_DBG_0_1 0xE0840C + +#define mmTPC0_QM_CP_DBG_0_2 0xE08410 + +#define mmTPC0_QM_CP_DBG_0_3 0xE08414 + +#define mmTPC0_QM_CP_DBG_0_4 0xE08418 + +#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C + +#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420 + +#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424 + +#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428 + +#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C + +#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430 + +#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434 + +#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438 + +#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C + +#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440 + +#define mmTPC0_QM_ARB_CFG_0 0xE08A00 + +#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C + +#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14 + +#define mmTPC0_QM_ARB_CFG_1 0xE08A18 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C + +#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20 + +#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28 + +#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C + +#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34 + +#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38 + +#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C + +#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44 + +#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48 + +#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C + +#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50 + +#define mmTPC0_QM_ARB_BASE_LO 0xE08B54 + +#define mmTPC0_QM_ARB_BASE_HI 0xE08B58 + +#define mmTPC0_QM_ARB_STATE_STS 0xE08B80 + +#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84 + +#define mmTPC0_QM_ARB_MSG_STS 0xE08B88 + +#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C + +#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C + +#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0 + +#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC + +#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC + +#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC + +#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC + +#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC + +#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00 + +#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04 + +#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08 + +#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C + +#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10 + +#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14 + +#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18 + +#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C + +#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20 + +#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24 + +#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28 + +#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C + +#define mmTPC0_QM_CGM_CFG 0xE08C70 + +#define mmTPC0_QM_CGM_STS 0xE08C74 + +#define mmTPC0_QM_CGM_CFG1 0xE08C78 + +#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80 + +#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84 + +#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90 + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0 + +#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4 + +#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0 + +#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4 + +#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8 + +#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8 + +#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00 + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h new file mode 100644 index 000000000..6736c476d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CFG_REGS_H_ +#define ASIC_REG_TPC1_CFG_REGS_H_ + +/* + ***************************************** + * TPC1_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE46418 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46420 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE46424 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46428 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46430 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46434 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE46438 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46440 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46444 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE46448 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46450 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE46454 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46458 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46460 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46464 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE46468 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46470 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE46474 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE46478 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE46480 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE46484 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE46488 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE46490 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE46494 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE46498 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC + +#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780 + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4 + +#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8 + +#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC + +#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0 + +#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4 + +#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8 + +#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC + +#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0 + +#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4 + +#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8 + +#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC + +#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0 + +#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4 + +#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8 + +#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC + +#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0 + +#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4 + +#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8 + +#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC + +#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800 + +#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804 + +#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808 + +#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C + +#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810 + +#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814 + +#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818 + +#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C + +#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820 + +#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824 + +#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828 + +#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C + +#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830 + +#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834 + +#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838 + +#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C + +#define mmTPC1_CFG_ROUND_CSR 0xE468FC + +#define mmTPC1_CFG_PROT 0xE46900 + +#define mmTPC1_CFG_SEMAPHORE 0xE46908 + +#define mmTPC1_CFG_VFLAGS 0xE4690C + +#define mmTPC1_CFG_SFLAGS 0xE46910 + +#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918 + +#define mmTPC1_CFG_STATUS 0xE4691C + +#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920 + +#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C + +#define mmTPC1_CFG_TPC_CMD 0xE46930 + +#define mmTPC1_CFG_TPC_EXECUTE 0xE46938 + +#define mmTPC1_CFG_TPC_STALL 0xE4693C + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940 + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944 + +#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948 + +#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950 + +#define mmTPC1_CFG_MSS_CONFIG 0xE46954 + +#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958 + +#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C + +#define mmTPC1_CFG_WQ_CREDITS 0xE46960 + +#define mmTPC1_CFG_ARUSER_LO 0xE46964 + +#define mmTPC1_CFG_ARUSER_HI 0xE46968 + +#define mmTPC1_CFG_AWUSER_LO 0xE4696C + +#define mmTPC1_CFG_AWUSER_HI 0xE46970 + +#define mmTPC1_CFG_OPCODE_EXEC 0xE46974 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980 + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990 + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994 + +#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998 + +#define mmTPC1_CFG_TSB_CFG 0xE4699C + +#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0 + +#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4 + +#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8 + +#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC + +#define mmTPC1_CFG_DBGMEM_RC 0xE469B0 + +#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4 + +#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8 + +#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC + +#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0 + +#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4 + +#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0 + +#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 + +#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 + +#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C + +#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40 + +#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74 + +#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78 + +#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC + +#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0 + +#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0 + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4 + +#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8 + +#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C + +#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20 + +#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54 + +#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58 + +#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C + +#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90 + +#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0 + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4 + +#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8 + +#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC + +#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00 + +#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30 + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34 + +#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38 + +#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C + +#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70 + +#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C80 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C84 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C88 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C90 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C94 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C98 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA0 + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA4 + +#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA8 + +#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD4 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD8 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC + +#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE0 + +#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF0 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D00 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D04 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D08 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D10 + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D14 + +#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D18 + +#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D20 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D24 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D28 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D30 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D34 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D38 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D40 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D44 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D48 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C + +#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D50 + +#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D54 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D58 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D60 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D64 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D68 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D70 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D74 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D78 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C + +#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D80 + +#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D84 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D88 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D90 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D94 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D98 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA4 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA8 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC + +#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB4 + +#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB8 + +#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC + +#define mmTPC1_CFG_QM_SRF_0 0xE46DC0 + +#define mmTPC1_CFG_QM_SRF_1 0xE46DC4 + +#define mmTPC1_CFG_QM_SRF_2 0xE46DC8 + +#define mmTPC1_CFG_QM_SRF_3 0xE46DCC + +#define mmTPC1_CFG_QM_SRF_4 0xE46DD0 + +#define mmTPC1_CFG_QM_SRF_5 0xE46DD4 + +#define mmTPC1_CFG_QM_SRF_6 0xE46DD8 + +#define mmTPC1_CFG_QM_SRF_7 0xE46DDC + +#define mmTPC1_CFG_QM_SRF_8 0xE46DE0 + +#define mmTPC1_CFG_QM_SRF_9 0xE46DE4 + +#define mmTPC1_CFG_QM_SRF_10 0xE46DE8 + +#define mmTPC1_CFG_QM_SRF_11 0xE46DEC + +#define mmTPC1_CFG_QM_SRF_12 0xE46DF0 + +#define mmTPC1_CFG_QM_SRF_13 0xE46DF4 + +#define mmTPC1_CFG_QM_SRF_14 0xE46DF8 + +#define mmTPC1_CFG_QM_SRF_15 0xE46DFC + +#define mmTPC1_CFG_QM_SRF_16 0xE46E00 + +#define mmTPC1_CFG_QM_SRF_17 0xE46E04 + +#define mmTPC1_CFG_QM_SRF_18 0xE46E08 + +#define mmTPC1_CFG_QM_SRF_19 0xE46E0C + +#define mmTPC1_CFG_QM_SRF_20 0xE46E10 + +#define mmTPC1_CFG_QM_SRF_21 0xE46E14 + +#define mmTPC1_CFG_QM_SRF_22 0xE46E18 + +#define mmTPC1_CFG_QM_SRF_23 0xE46E1C + +#define mmTPC1_CFG_QM_SRF_24 0xE46E20 + +#define mmTPC1_CFG_QM_SRF_25 0xE46E24 + +#define mmTPC1_CFG_QM_SRF_26 0xE46E28 + +#define mmTPC1_CFG_QM_SRF_27 0xE46E2C + +#define mmTPC1_CFG_QM_SRF_28 0xE46E30 + +#define mmTPC1_CFG_QM_SRF_29 0xE46E34 + +#define mmTPC1_CFG_QM_SRF_30 0xE46E38 + +#define mmTPC1_CFG_QM_SRF_31 0xE46E3C + +#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000..af10ef7a8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034 + +#define mmTPC1_QM_GLBL_STS0 0xE48038 + +#define mmTPC1_QM_GLBL_STS1_0 0xE48040 + +#define mmTPC1_QM_GLBL_STS1_1 0xE48044 + +#define mmTPC1_QM_GLBL_STS1_2 0xE48048 + +#define mmTPC1_QM_GLBL_STS1_3 0xE4804C + +#define mmTPC1_QM_GLBL_STS1_4 0xE48050 + +#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054 + +#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058 + +#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C + +#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060 + +#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068 + +#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070 + +#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074 + +#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078 + +#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C + +#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080 + +#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084 + +#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088 + +#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C + +#define mmTPC1_QM_PQ_SIZE_0 0xE48090 + +#define mmTPC1_QM_PQ_SIZE_1 0xE48094 + +#define mmTPC1_QM_PQ_SIZE_2 0xE48098 + +#define mmTPC1_QM_PQ_SIZE_3 0xE4809C + +#define mmTPC1_QM_PQ_PI_0 0xE480A0 + +#define mmTPC1_QM_PQ_PI_1 0xE480A4 + +#define mmTPC1_QM_PQ_PI_2 0xE480A8 + +#define mmTPC1_QM_PQ_PI_3 0xE480AC + +#define mmTPC1_QM_PQ_CI_0 0xE480B0 + +#define mmTPC1_QM_PQ_CI_1 0xE480B4 + +#define mmTPC1_QM_PQ_CI_2 0xE480B8 + +#define mmTPC1_QM_PQ_CI_3 0xE480BC + +#define mmTPC1_QM_PQ_CFG0_0 0xE480C0 + +#define mmTPC1_QM_PQ_CFG0_1 0xE480C4 + +#define mmTPC1_QM_PQ_CFG0_2 0xE480C8 + +#define mmTPC1_QM_PQ_CFG0_3 0xE480CC + +#define mmTPC1_QM_PQ_CFG1_0 0xE480D0 + +#define mmTPC1_QM_PQ_CFG1_1 0xE480D4 + +#define mmTPC1_QM_PQ_CFG1_2 0xE480D8 + +#define mmTPC1_QM_PQ_CFG1_3 0xE480DC + +#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0 + +#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4 + +#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8 + +#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC + +#define mmTPC1_QM_PQ_STS0_0 0xE480F0 + +#define mmTPC1_QM_PQ_STS0_1 0xE480F4 + +#define mmTPC1_QM_PQ_STS0_2 0xE480F8 + +#define mmTPC1_QM_PQ_STS0_3 0xE480FC + +#define mmTPC1_QM_PQ_STS1_0 0xE48100 + +#define mmTPC1_QM_PQ_STS1_1 0xE48104 + +#define mmTPC1_QM_PQ_STS1_2 0xE48108 + +#define mmTPC1_QM_PQ_STS1_3 0xE4810C + +#define mmTPC1_QM_CQ_CFG0_0 0xE48110 + +#define mmTPC1_QM_CQ_CFG0_1 0xE48114 + +#define mmTPC1_QM_CQ_CFG0_2 0xE48118 + +#define mmTPC1_QM_CQ_CFG0_3 0xE4811C + +#define mmTPC1_QM_CQ_CFG0_4 0xE48120 + +#define mmTPC1_QM_CQ_CFG1_0 0xE48124 + +#define mmTPC1_QM_CQ_CFG1_1 0xE48128 + +#define mmTPC1_QM_CQ_CFG1_2 0xE4812C + +#define mmTPC1_QM_CQ_CFG1_3 0xE48130 + +#define mmTPC1_QM_CQ_CFG1_4 0xE48134 + +#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138 + +#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C + +#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140 + +#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144 + +#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148 + +#define mmTPC1_QM_CQ_STS0_0 0xE4814C + +#define mmTPC1_QM_CQ_STS0_1 0xE48150 + +#define mmTPC1_QM_CQ_STS0_2 0xE48154 + +#define mmTPC1_QM_CQ_STS0_3 0xE48158 + +#define mmTPC1_QM_CQ_STS0_4 0xE4815C + +#define mmTPC1_QM_CQ_STS1_0 0xE48160 + +#define mmTPC1_QM_CQ_STS1_1 0xE48164 + +#define mmTPC1_QM_CQ_STS1_2 0xE48168 + +#define mmTPC1_QM_CQ_STS1_3 0xE4816C + +#define mmTPC1_QM_CQ_STS1_4 0xE48170 + +#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174 + +#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178 + +#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C + +#define mmTPC1_QM_CQ_CTL_0 0xE48180 + +#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184 + +#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188 + +#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C + +#define mmTPC1_QM_CQ_CTL_1 0xE48190 + +#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194 + +#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198 + +#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C + +#define mmTPC1_QM_CQ_CTL_2 0xE481A0 + +#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4 + +#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8 + +#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC + +#define mmTPC1_QM_CQ_CTL_3 0xE481B0 + +#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4 + +#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8 + +#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC + +#define mmTPC1_QM_CQ_CTL_4 0xE481C0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4 + +#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8 + +#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC + +#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8 + +#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC + +#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0 + +#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8 + +#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC + +#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0 + +#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4 + +#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8 + +#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC + +#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200 + +#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204 + +#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208 + +#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C + +#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210 + +#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214 + +#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218 + +#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C + +#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220 + +#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304 + +#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308 + +#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C + +#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310 + +#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314 + +#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318 + +#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C + +#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320 + +#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324 + +#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328 + +#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C + +#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330 + +#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334 + +#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338 + +#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C + +#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340 + +#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344 + +#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348 + +#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C + +#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350 + +#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354 + +#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358 + +#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C + +#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360 + +#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364 + +#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368 + +#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C + +#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370 + +#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374 + +#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378 + +#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C + +#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380 + +#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384 + +#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388 + +#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C + +#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390 + +#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394 + +#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398 + +#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C + +#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0 + +#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4 + +#define mmTPC1_QM_CP_STS_0 0xE483A8 + +#define mmTPC1_QM_CP_STS_1 0xE483AC + +#define mmTPC1_QM_CP_STS_2 0xE483B0 + +#define mmTPC1_QM_CP_STS_3 0xE483B4 + +#define mmTPC1_QM_CP_STS_4 0xE483B8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC + +#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0 + +#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4 + +#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8 + +#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC + +#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400 + +#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404 + +#define mmTPC1_QM_CP_DBG_0_0 0xE48408 + +#define mmTPC1_QM_CP_DBG_0_1 0xE4840C + +#define mmTPC1_QM_CP_DBG_0_2 0xE48410 + +#define mmTPC1_QM_CP_DBG_0_3 0xE48414 + +#define mmTPC1_QM_CP_DBG_0_4 0xE48418 + +#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C + +#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420 + +#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424 + +#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428 + +#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C + +#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430 + +#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434 + +#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438 + +#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C + +#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440 + +#define mmTPC1_QM_ARB_CFG_0 0xE48A00 + +#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C + +#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14 + +#define mmTPC1_QM_ARB_CFG_1 0xE48A18 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C + +#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20 + +#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28 + +#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C + +#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34 + +#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38 + +#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C + +#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44 + +#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48 + +#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C + +#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50 + +#define mmTPC1_QM_ARB_BASE_LO 0xE48B54 + +#define mmTPC1_QM_ARB_BASE_HI 0xE48B58 + +#define mmTPC1_QM_ARB_STATE_STS 0xE48B80 + +#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84 + +#define mmTPC1_QM_ARB_MSG_STS 0xE48B88 + +#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C + +#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C + +#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0 + +#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC + +#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC + +#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC + +#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC + +#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC + +#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00 + +#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04 + +#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08 + +#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C + +#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10 + +#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14 + +#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18 + +#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C + +#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20 + +#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24 + +#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28 + +#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C + +#define mmTPC1_QM_CGM_CFG 0xE48C70 + +#define mmTPC1_QM_CGM_STS 0xE48C74 + +#define mmTPC1_QM_CGM_CFG1 0xE48C78 + +#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80 + +#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84 + +#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90 + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0 + +#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4 + +#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0 + +#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4 + +#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8 + +#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8 + +#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00 + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000..3e77c3795 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4 + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8 + +#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C + +#define mmTPC2_CFG_ROUND_CSR 0xE868FC + +#define mmTPC2_CFG_PROT 0xE86900 + +#define mmTPC2_CFG_SEMAPHORE 0xE86908 + +#define mmTPC2_CFG_VFLAGS 0xE8690C + +#define mmTPC2_CFG_SFLAGS 0xE86910 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918 + +#define mmTPC2_CFG_STATUS 0xE8691C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C + +#define mmTPC2_CFG_TPC_CMD 0xE86930 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86938 + +#define mmTPC2_CFG_TPC_STALL 0xE8693C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944 + +#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948 + +#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86954 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C + +#define mmTPC2_CFG_WQ_CREDITS 0xE86960 + +#define mmTPC2_CFG_ARUSER_LO 0xE86964 + +#define mmTPC2_CFG_ARUSER_HI 0xE86968 + +#define mmTPC2_CFG_AWUSER_LO 0xE8696C + +#define mmTPC2_CFG_AWUSER_HI 0xE86970 + +#define mmTPC2_CFG_OPCODE_EXEC 0xE86974 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980 + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990 + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994 + +#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998 + +#define mmTPC2_CFG_TSB_CFG 0xE8699C + +#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0 + +#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4 + +#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8 + +#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC + +#define mmTPC2_CFG_DBGMEM_RC 0xE869B0 + +#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4 + +#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8 + +#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC + +#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0 + +#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4 + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C + +#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70 + +#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0 + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4 + +#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8 + +#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC + +#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0 + +#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10 + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14 + +#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18 + +#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C + +#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50 + +#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4 + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8 + +#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC + +#define mmTPC2_CFG_QM_SRF_0 0xE86DC0 + +#define mmTPC2_CFG_QM_SRF_1 0xE86DC4 + +#define mmTPC2_CFG_QM_SRF_2 0xE86DC8 + +#define mmTPC2_CFG_QM_SRF_3 0xE86DCC + +#define mmTPC2_CFG_QM_SRF_4 0xE86DD0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86DD4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86DD8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86DDC + +#define mmTPC2_CFG_QM_SRF_8 0xE86DE0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86DE4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86DE8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86DEC + +#define mmTPC2_CFG_QM_SRF_12 0xE86DF0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86DF4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86DF8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86DFC + +#define mmTPC2_CFG_QM_SRF_16 0xE86E00 + +#define mmTPC2_CFG_QM_SRF_17 0xE86E04 + +#define mmTPC2_CFG_QM_SRF_18 0xE86E08 + +#define mmTPC2_CFG_QM_SRF_19 0xE86E0C + +#define mmTPC2_CFG_QM_SRF_20 0xE86E10 + +#define mmTPC2_CFG_QM_SRF_21 0xE86E14 + +#define mmTPC2_CFG_QM_SRF_22 0xE86E18 + +#define mmTPC2_CFG_QM_SRF_23 0xE86E1C + +#define mmTPC2_CFG_QM_SRF_24 0xE86E20 + +#define mmTPC2_CFG_QM_SRF_25 0xE86E24 + +#define mmTPC2_CFG_QM_SRF_26 0xE86E28 + +#define mmTPC2_CFG_QM_SRF_27 0xE86E2C + +#define mmTPC2_CFG_QM_SRF_28 0xE86E30 + +#define mmTPC2_CFG_QM_SRF_29 0xE86E34 + +#define mmTPC2_CFG_QM_SRF_30 0xE86E38 + +#define mmTPC2_CFG_QM_SRF_31 0xE86E3C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h new file mode 100644 index 000000000..2919e2fa5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_QM_REGS_H_ +#define ASIC_REG_TPC2_QM_REGS_H_ + +/* + ***************************************** + * TPC2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC2_QM_GLBL_CFG0 0xE88000 + +#define mmTPC2_QM_GLBL_CFG1 0xE88004 + +#define mmTPC2_QM_GLBL_PROT 0xE88008 + +#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034 + +#define mmTPC2_QM_GLBL_STS0 0xE88038 + +#define mmTPC2_QM_GLBL_STS1_0 0xE88040 + +#define mmTPC2_QM_GLBL_STS1_1 0xE88044 + +#define mmTPC2_QM_GLBL_STS1_2 0xE88048 + +#define mmTPC2_QM_GLBL_STS1_3 0xE8804C + +#define mmTPC2_QM_GLBL_STS1_4 0xE88050 + +#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054 + +#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058 + +#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C + +#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060 + +#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068 + +#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070 + +#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074 + +#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078 + +#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C + +#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080 + +#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084 + +#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088 + +#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C + +#define mmTPC2_QM_PQ_SIZE_0 0xE88090 + +#define mmTPC2_QM_PQ_SIZE_1 0xE88094 + +#define mmTPC2_QM_PQ_SIZE_2 0xE88098 + +#define mmTPC2_QM_PQ_SIZE_3 0xE8809C + +#define mmTPC2_QM_PQ_PI_0 0xE880A0 + +#define mmTPC2_QM_PQ_PI_1 0xE880A4 + +#define mmTPC2_QM_PQ_PI_2 0xE880A8 + +#define mmTPC2_QM_PQ_PI_3 0xE880AC + +#define mmTPC2_QM_PQ_CI_0 0xE880B0 + +#define mmTPC2_QM_PQ_CI_1 0xE880B4 + +#define mmTPC2_QM_PQ_CI_2 0xE880B8 + +#define mmTPC2_QM_PQ_CI_3 0xE880BC + +#define mmTPC2_QM_PQ_CFG0_0 0xE880C0 + +#define mmTPC2_QM_PQ_CFG0_1 0xE880C4 + +#define mmTPC2_QM_PQ_CFG0_2 0xE880C8 + +#define mmTPC2_QM_PQ_CFG0_3 0xE880CC + +#define mmTPC2_QM_PQ_CFG1_0 0xE880D0 + +#define mmTPC2_QM_PQ_CFG1_1 0xE880D4 + +#define mmTPC2_QM_PQ_CFG1_2 0xE880D8 + +#define mmTPC2_QM_PQ_CFG1_3 0xE880DC + +#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0 + +#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4 + +#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8 + +#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC + +#define mmTPC2_QM_PQ_STS0_0 0xE880F0 + +#define mmTPC2_QM_PQ_STS0_1 0xE880F4 + +#define mmTPC2_QM_PQ_STS0_2 0xE880F8 + +#define mmTPC2_QM_PQ_STS0_3 0xE880FC + +#define mmTPC2_QM_PQ_STS1_0 0xE88100 + +#define mmTPC2_QM_PQ_STS1_1 0xE88104 + +#define mmTPC2_QM_PQ_STS1_2 0xE88108 + +#define mmTPC2_QM_PQ_STS1_3 0xE8810C + +#define mmTPC2_QM_CQ_CFG0_0 0xE88110 + +#define mmTPC2_QM_CQ_CFG0_1 0xE88114 + +#define mmTPC2_QM_CQ_CFG0_2 0xE88118 + +#define mmTPC2_QM_CQ_CFG0_3 0xE8811C + +#define mmTPC2_QM_CQ_CFG0_4 0xE88120 + +#define mmTPC2_QM_CQ_CFG1_0 0xE88124 + +#define mmTPC2_QM_CQ_CFG1_1 0xE88128 + +#define mmTPC2_QM_CQ_CFG1_2 0xE8812C + +#define mmTPC2_QM_CQ_CFG1_3 0xE88130 + +#define mmTPC2_QM_CQ_CFG1_4 0xE88134 + +#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138 + +#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C + +#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140 + +#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144 + +#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148 + +#define mmTPC2_QM_CQ_STS0_0 0xE8814C + +#define mmTPC2_QM_CQ_STS0_1 0xE88150 + +#define mmTPC2_QM_CQ_STS0_2 0xE88154 + +#define mmTPC2_QM_CQ_STS0_3 0xE88158 + +#define mmTPC2_QM_CQ_STS0_4 0xE8815C + +#define mmTPC2_QM_CQ_STS1_0 0xE88160 + +#define mmTPC2_QM_CQ_STS1_1 0xE88164 + +#define mmTPC2_QM_CQ_STS1_2 0xE88168 + +#define mmTPC2_QM_CQ_STS1_3 0xE8816C + +#define mmTPC2_QM_CQ_STS1_4 0xE88170 + +#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174 + +#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178 + +#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C + +#define mmTPC2_QM_CQ_CTL_0 0xE88180 + +#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184 + +#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188 + +#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C + +#define mmTPC2_QM_CQ_CTL_1 0xE88190 + +#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194 + +#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198 + +#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C + +#define mmTPC2_QM_CQ_CTL_2 0xE881A0 + +#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4 + +#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8 + +#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC + +#define mmTPC2_QM_CQ_CTL_3 0xE881B0 + +#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4 + +#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8 + +#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC + +#define mmTPC2_QM_CQ_CTL_4 0xE881C0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4 + +#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8 + +#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC + +#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8 + +#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC + +#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0 + +#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8 + +#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC + +#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0 + +#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4 + +#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8 + +#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC + +#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200 + +#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204 + +#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208 + +#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C + +#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210 + +#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214 + +#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218 + +#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C + +#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220 + +#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304 + +#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308 + +#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C + +#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310 + +#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314 + +#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318 + +#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C + +#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320 + +#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324 + +#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328 + +#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C + +#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330 + +#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334 + +#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338 + +#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C + +#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340 + +#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344 + +#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348 + +#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C + +#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350 + +#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354 + +#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358 + +#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C + +#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360 + +#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364 + +#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368 + +#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C + +#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370 + +#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374 + +#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378 + +#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C + +#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380 + +#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384 + +#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388 + +#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C + +#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390 + +#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394 + +#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398 + +#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C + +#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0 + +#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4 + +#define mmTPC2_QM_CP_STS_0 0xE883A8 + +#define mmTPC2_QM_CP_STS_1 0xE883AC + +#define mmTPC2_QM_CP_STS_2 0xE883B0 + +#define mmTPC2_QM_CP_STS_3 0xE883B4 + +#define mmTPC2_QM_CP_STS_4 0xE883B8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC + +#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0 + +#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4 + +#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8 + +#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC + +#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400 + +#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404 + +#define mmTPC2_QM_CP_DBG_0_0 0xE88408 + +#define mmTPC2_QM_CP_DBG_0_1 0xE8840C + +#define mmTPC2_QM_CP_DBG_0_2 0xE88410 + +#define mmTPC2_QM_CP_DBG_0_3 0xE88414 + +#define mmTPC2_QM_CP_DBG_0_4 0xE88418 + +#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C + +#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420 + +#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424 + +#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428 + +#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C + +#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430 + +#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434 + +#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438 + +#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C + +#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440 + +#define mmTPC2_QM_ARB_CFG_0 0xE88A00 + +#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C + +#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14 + +#define mmTPC2_QM_ARB_CFG_1 0xE88A18 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C + +#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20 + +#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28 + +#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C + +#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34 + +#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38 + +#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C + +#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44 + +#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48 + +#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C + +#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50 + +#define mmTPC2_QM_ARB_BASE_LO 0xE88B54 + +#define mmTPC2_QM_ARB_BASE_HI 0xE88B58 + +#define mmTPC2_QM_ARB_STATE_STS 0xE88B80 + +#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84 + +#define mmTPC2_QM_ARB_MSG_STS 0xE88B88 + +#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C + +#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C + +#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0 + +#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC + +#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC + +#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC + +#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC + +#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC + +#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00 + +#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04 + +#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08 + +#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C + +#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10 + +#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14 + +#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18 + +#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C + +#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20 + +#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24 + +#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28 + +#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C + +#define mmTPC2_QM_CGM_CFG 0xE88C70 + +#define mmTPC2_QM_CGM_STS 0xE88C74 + +#define mmTPC2_QM_CGM_CFG1 0xE88C78 + +#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80 + +#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84 + +#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90 + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0 + +#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4 + +#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0 + +#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4 + +#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8 + +#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC + +#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0 + +#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4 + +#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8 + +#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00 + +#endif /* ASIC_REG_TPC2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h new file mode 100644 index 000000000..6d4246965 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CFG_REGS_H_ +#define ASIC_REG_TPC3_CFG_REGS_H_ + +/* + ***************************************** + * TPC3_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC + +#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780 + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4 + +#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8 + +#define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC + +#define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0 + +#define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4 + +#define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8 + +#define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC + +#define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0 + +#define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4 + +#define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8 + +#define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC + +#define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0 + +#define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4 + +#define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8 + +#define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC + +#define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0 + +#define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4 + +#define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8 + +#define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC + +#define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800 + +#define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804 + +#define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808 + +#define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C + +#define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810 + +#define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814 + +#define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818 + +#define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C + +#define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820 + +#define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824 + +#define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828 + +#define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C + +#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830 + +#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834 + +#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838 + +#define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C + +#define mmTPC3_CFG_ROUND_CSR 0xEC68FC + +#define mmTPC3_CFG_PROT 0xEC6900 + +#define mmTPC3_CFG_SEMAPHORE 0xEC6908 + +#define mmTPC3_CFG_VFLAGS 0xEC690C + +#define mmTPC3_CFG_SFLAGS 0xEC6910 + +#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918 + +#define mmTPC3_CFG_STATUS 0xEC691C + +#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920 + +#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C + +#define mmTPC3_CFG_TPC_CMD 0xEC6930 + +#define mmTPC3_CFG_TPC_EXECUTE 0xEC6938 + +#define mmTPC3_CFG_TPC_STALL 0xEC693C + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940 + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944 + +#define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948 + +#define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950 + +#define mmTPC3_CFG_MSS_CONFIG 0xEC6954 + +#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958 + +#define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C + +#define mmTPC3_CFG_WQ_CREDITS 0xEC6960 + +#define mmTPC3_CFG_ARUSER_LO 0xEC6964 + +#define mmTPC3_CFG_ARUSER_HI 0xEC6968 + +#define mmTPC3_CFG_AWUSER_LO 0xEC696C + +#define mmTPC3_CFG_AWUSER_HI 0xEC6970 + +#define mmTPC3_CFG_OPCODE_EXEC 0xEC6974 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980 + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990 + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994 + +#define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998 + +#define mmTPC3_CFG_TSB_CFG 0xEC699C + +#define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0 + +#define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4 + +#define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8 + +#define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC + +#define mmTPC3_CFG_DBGMEM_RC 0xEC69B0 + +#define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4 + +#define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8 + +#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC + +#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0 + +#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4 + +#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0 + +#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 + +#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 + +#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C + +#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40 + +#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74 + +#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78 + +#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC + +#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0 + +#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0 + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4 + +#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8 + +#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C + +#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20 + +#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54 + +#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58 + +#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C + +#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90 + +#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0 + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4 + +#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8 + +#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC + +#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00 + +#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30 + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34 + +#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38 + +#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C + +#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70 + +#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0 + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4 + +#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8 + +#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC + +#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0 + +#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10 + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14 + +#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18 + +#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C + +#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50 + +#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C + +#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80 + +#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC + +#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4 + +#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8 + +#define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC + +#define mmTPC3_CFG_QM_SRF_0 0xEC6DC0 + +#define mmTPC3_CFG_QM_SRF_1 0xEC6DC4 + +#define mmTPC3_CFG_QM_SRF_2 0xEC6DC8 + +#define mmTPC3_CFG_QM_SRF_3 0xEC6DCC + +#define mmTPC3_CFG_QM_SRF_4 0xEC6DD0 + +#define mmTPC3_CFG_QM_SRF_5 0xEC6DD4 + +#define mmTPC3_CFG_QM_SRF_6 0xEC6DD8 + +#define mmTPC3_CFG_QM_SRF_7 0xEC6DDC + +#define mmTPC3_CFG_QM_SRF_8 0xEC6DE0 + +#define mmTPC3_CFG_QM_SRF_9 0xEC6DE4 + +#define mmTPC3_CFG_QM_SRF_10 0xEC6DE8 + +#define mmTPC3_CFG_QM_SRF_11 0xEC6DEC + +#define mmTPC3_CFG_QM_SRF_12 0xEC6DF0 + +#define mmTPC3_CFG_QM_SRF_13 0xEC6DF4 + +#define mmTPC3_CFG_QM_SRF_14 0xEC6DF8 + +#define mmTPC3_CFG_QM_SRF_15 0xEC6DFC + +#define mmTPC3_CFG_QM_SRF_16 0xEC6E00 + +#define mmTPC3_CFG_QM_SRF_17 0xEC6E04 + +#define mmTPC3_CFG_QM_SRF_18 0xEC6E08 + +#define mmTPC3_CFG_QM_SRF_19 0xEC6E0C + +#define mmTPC3_CFG_QM_SRF_20 0xEC6E10 + +#define mmTPC3_CFG_QM_SRF_21 0xEC6E14 + +#define mmTPC3_CFG_QM_SRF_22 0xEC6E18 + +#define mmTPC3_CFG_QM_SRF_23 0xEC6E1C + +#define mmTPC3_CFG_QM_SRF_24 0xEC6E20 + +#define mmTPC3_CFG_QM_SRF_25 0xEC6E24 + +#define mmTPC3_CFG_QM_SRF_26 0xEC6E28 + +#define mmTPC3_CFG_QM_SRF_27 0xEC6E2C + +#define mmTPC3_CFG_QM_SRF_28 0xEC6E30 + +#define mmTPC3_CFG_QM_SRF_29 0xEC6E34 + +#define mmTPC3_CFG_QM_SRF_30 0xEC6E38 + +#define mmTPC3_CFG_QM_SRF_31 0xEC6E3C + +#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h new file mode 100644 index 000000000..5f2a0fd86 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_QM_REGS_H_ +#define ASIC_REG_TPC3_QM_REGS_H_ + +/* + ***************************************** + * TPC3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC3_QM_GLBL_CFG0 0xEC8000 + +#define mmTPC3_QM_GLBL_CFG1 0xEC8004 + +#define mmTPC3_QM_GLBL_PROT 0xEC8008 + +#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034 + +#define mmTPC3_QM_GLBL_STS0 0xEC8038 + +#define mmTPC3_QM_GLBL_STS1_0 0xEC8040 + +#define mmTPC3_QM_GLBL_STS1_1 0xEC8044 + +#define mmTPC3_QM_GLBL_STS1_2 0xEC8048 + +#define mmTPC3_QM_GLBL_STS1_3 0xEC804C + +#define mmTPC3_QM_GLBL_STS1_4 0xEC8050 + +#define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054 + +#define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058 + +#define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C + +#define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060 + +#define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068 + +#define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070 + +#define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074 + +#define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078 + +#define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C + +#define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080 + +#define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084 + +#define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088 + +#define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C + +#define mmTPC3_QM_PQ_SIZE_0 0xEC8090 + +#define mmTPC3_QM_PQ_SIZE_1 0xEC8094 + +#define mmTPC3_QM_PQ_SIZE_2 0xEC8098 + +#define mmTPC3_QM_PQ_SIZE_3 0xEC809C + +#define mmTPC3_QM_PQ_PI_0 0xEC80A0 + +#define mmTPC3_QM_PQ_PI_1 0xEC80A4 + +#define mmTPC3_QM_PQ_PI_2 0xEC80A8 + +#define mmTPC3_QM_PQ_PI_3 0xEC80AC + +#define mmTPC3_QM_PQ_CI_0 0xEC80B0 + +#define mmTPC3_QM_PQ_CI_1 0xEC80B4 + +#define mmTPC3_QM_PQ_CI_2 0xEC80B8 + +#define mmTPC3_QM_PQ_CI_3 0xEC80BC + +#define mmTPC3_QM_PQ_CFG0_0 0xEC80C0 + +#define mmTPC3_QM_PQ_CFG0_1 0xEC80C4 + +#define mmTPC3_QM_PQ_CFG0_2 0xEC80C8 + +#define mmTPC3_QM_PQ_CFG0_3 0xEC80CC + +#define mmTPC3_QM_PQ_CFG1_0 0xEC80D0 + +#define mmTPC3_QM_PQ_CFG1_1 0xEC80D4 + +#define mmTPC3_QM_PQ_CFG1_2 0xEC80D8 + +#define mmTPC3_QM_PQ_CFG1_3 0xEC80DC + +#define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0 + +#define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4 + +#define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8 + +#define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC + +#define mmTPC3_QM_PQ_STS0_0 0xEC80F0 + +#define mmTPC3_QM_PQ_STS0_1 0xEC80F4 + +#define mmTPC3_QM_PQ_STS0_2 0xEC80F8 + +#define mmTPC3_QM_PQ_STS0_3 0xEC80FC + +#define mmTPC3_QM_PQ_STS1_0 0xEC8100 + +#define mmTPC3_QM_PQ_STS1_1 0xEC8104 + +#define mmTPC3_QM_PQ_STS1_2 0xEC8108 + +#define mmTPC3_QM_PQ_STS1_3 0xEC810C + +#define mmTPC3_QM_CQ_CFG0_0 0xEC8110 + +#define mmTPC3_QM_CQ_CFG0_1 0xEC8114 + +#define mmTPC3_QM_CQ_CFG0_2 0xEC8118 + +#define mmTPC3_QM_CQ_CFG0_3 0xEC811C + +#define mmTPC3_QM_CQ_CFG0_4 0xEC8120 + +#define mmTPC3_QM_CQ_CFG1_0 0xEC8124 + +#define mmTPC3_QM_CQ_CFG1_1 0xEC8128 + +#define mmTPC3_QM_CQ_CFG1_2 0xEC812C + +#define mmTPC3_QM_CQ_CFG1_3 0xEC8130 + +#define mmTPC3_QM_CQ_CFG1_4 0xEC8134 + +#define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138 + +#define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C + +#define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140 + +#define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144 + +#define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148 + +#define mmTPC3_QM_CQ_STS0_0 0xEC814C + +#define mmTPC3_QM_CQ_STS0_1 0xEC8150 + +#define mmTPC3_QM_CQ_STS0_2 0xEC8154 + +#define mmTPC3_QM_CQ_STS0_3 0xEC8158 + +#define mmTPC3_QM_CQ_STS0_4 0xEC815C + +#define mmTPC3_QM_CQ_STS1_0 0xEC8160 + +#define mmTPC3_QM_CQ_STS1_1 0xEC8164 + +#define mmTPC3_QM_CQ_STS1_2 0xEC8168 + +#define mmTPC3_QM_CQ_STS1_3 0xEC816C + +#define mmTPC3_QM_CQ_STS1_4 0xEC8170 + +#define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174 + +#define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178 + +#define mmTPC3_QM_CQ_TSIZE_0 0xEC817C + +#define mmTPC3_QM_CQ_CTL_0 0xEC8180 + +#define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184 + +#define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188 + +#define mmTPC3_QM_CQ_TSIZE_1 0xEC818C + +#define mmTPC3_QM_CQ_CTL_1 0xEC8190 + +#define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194 + +#define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198 + +#define mmTPC3_QM_CQ_TSIZE_2 0xEC819C + +#define mmTPC3_QM_CQ_CTL_2 0xEC81A0 + +#define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4 + +#define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8 + +#define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC + +#define mmTPC3_QM_CQ_CTL_3 0xEC81B0 + +#define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4 + +#define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8 + +#define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC + +#define mmTPC3_QM_CQ_CTL_4 0xEC81C0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4 + +#define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8 + +#define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC + +#define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8 + +#define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC + +#define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0 + +#define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8 + +#define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC + +#define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0 + +#define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4 + +#define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8 + +#define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC + +#define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200 + +#define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204 + +#define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208 + +#define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C + +#define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210 + +#define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214 + +#define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218 + +#define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C + +#define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220 + +#define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304 + +#define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308 + +#define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C + +#define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310 + +#define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314 + +#define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318 + +#define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C + +#define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320 + +#define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324 + +#define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328 + +#define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C + +#define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330 + +#define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334 + +#define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338 + +#define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C + +#define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340 + +#define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344 + +#define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348 + +#define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C + +#define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350 + +#define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354 + +#define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358 + +#define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C + +#define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360 + +#define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364 + +#define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368 + +#define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C + +#define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370 + +#define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374 + +#define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378 + +#define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C + +#define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380 + +#define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384 + +#define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388 + +#define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C + +#define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390 + +#define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394 + +#define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398 + +#define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C + +#define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0 + +#define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4 + +#define mmTPC3_QM_CP_STS_0 0xEC83A8 + +#define mmTPC3_QM_CP_STS_1 0xEC83AC + +#define mmTPC3_QM_CP_STS_2 0xEC83B0 + +#define mmTPC3_QM_CP_STS_3 0xEC83B4 + +#define mmTPC3_QM_CP_STS_4 0xEC83B8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC + +#define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0 + +#define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4 + +#define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8 + +#define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC + +#define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400 + +#define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404 + +#define mmTPC3_QM_CP_DBG_0_0 0xEC8408 + +#define mmTPC3_QM_CP_DBG_0_1 0xEC840C + +#define mmTPC3_QM_CP_DBG_0_2 0xEC8410 + +#define mmTPC3_QM_CP_DBG_0_3 0xEC8414 + +#define mmTPC3_QM_CP_DBG_0_4 0xEC8418 + +#define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C + +#define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420 + +#define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424 + +#define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428 + +#define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C + +#define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430 + +#define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434 + +#define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438 + +#define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C + +#define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440 + +#define mmTPC3_QM_ARB_CFG_0 0xEC8A00 + +#define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C + +#define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14 + +#define mmTPC3_QM_ARB_CFG_1 0xEC8A18 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C + +#define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20 + +#define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28 + +#define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C + +#define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34 + +#define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38 + +#define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C + +#define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44 + +#define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48 + +#define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C + +#define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50 + +#define mmTPC3_QM_ARB_BASE_LO 0xEC8B54 + +#define mmTPC3_QM_ARB_BASE_HI 0xEC8B58 + +#define mmTPC3_QM_ARB_STATE_STS 0xEC8B80 + +#define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84 + +#define mmTPC3_QM_ARB_MSG_STS 0xEC8B88 + +#define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C + +#define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C + +#define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0 + +#define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC + +#define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC + +#define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC + +#define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC + +#define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC + +#define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00 + +#define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04 + +#define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08 + +#define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C + +#define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10 + +#define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14 + +#define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18 + +#define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C + +#define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20 + +#define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24 + +#define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28 + +#define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C + +#define mmTPC3_QM_CGM_CFG 0xEC8C70 + +#define mmTPC3_QM_CGM_STS 0xEC8C74 + +#define mmTPC3_QM_CGM_CFG1 0xEC8C78 + +#define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80 + +#define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84 + +#define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90 + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0 + +#define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4 + +#define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0 + +#define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4 + +#define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8 + +#define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC + +#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0 + +#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4 + +#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8 + +#define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00 + +#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h new file mode 100644 index 000000000..7a9447f39 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CFG_REGS_H_ +#define ASIC_REG_TPC4_CFG_REGS_H_ + +/* + ***************************************** + * TPC4_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF06418 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06420 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF06424 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06428 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06430 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06434 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF06438 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06440 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06444 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF06448 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06450 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF06454 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06458 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06460 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06464 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF06468 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06470 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF06474 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF06478 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF06480 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF06484 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF06488 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF06490 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF06494 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF06498 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC + +#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780 + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4 + +#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8 + +#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC + +#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0 + +#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4 + +#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8 + +#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC + +#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0 + +#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4 + +#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8 + +#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC + +#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0 + +#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4 + +#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8 + +#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC + +#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0 + +#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4 + +#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8 + +#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC + +#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800 + +#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804 + +#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808 + +#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C + +#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810 + +#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814 + +#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818 + +#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C + +#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820 + +#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824 + +#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828 + +#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C + +#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830 + +#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834 + +#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838 + +#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C + +#define mmTPC4_CFG_ROUND_CSR 0xF068FC + +#define mmTPC4_CFG_PROT 0xF06900 + +#define mmTPC4_CFG_SEMAPHORE 0xF06908 + +#define mmTPC4_CFG_VFLAGS 0xF0690C + +#define mmTPC4_CFG_SFLAGS 0xF06910 + +#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918 + +#define mmTPC4_CFG_STATUS 0xF0691C + +#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920 + +#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C + +#define mmTPC4_CFG_TPC_CMD 0xF06930 + +#define mmTPC4_CFG_TPC_EXECUTE 0xF06938 + +#define mmTPC4_CFG_TPC_STALL 0xF0693C + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940 + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944 + +#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948 + +#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950 + +#define mmTPC4_CFG_MSS_CONFIG 0xF06954 + +#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958 + +#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C + +#define mmTPC4_CFG_WQ_CREDITS 0xF06960 + +#define mmTPC4_CFG_ARUSER_LO 0xF06964 + +#define mmTPC4_CFG_ARUSER_HI 0xF06968 + +#define mmTPC4_CFG_AWUSER_LO 0xF0696C + +#define mmTPC4_CFG_AWUSER_HI 0xF06970 + +#define mmTPC4_CFG_OPCODE_EXEC 0xF06974 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980 + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990 + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994 + +#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998 + +#define mmTPC4_CFG_TSB_CFG 0xF0699C + +#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0 + +#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4 + +#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8 + +#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC + +#define mmTPC4_CFG_DBGMEM_RC 0xF069B0 + +#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4 + +#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8 + +#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC + +#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0 + +#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4 + +#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0 + +#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 + +#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 + +#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C + +#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40 + +#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74 + +#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78 + +#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC + +#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0 + +#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0 + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4 + +#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8 + +#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C + +#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20 + +#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54 + +#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58 + +#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C + +#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90 + +#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0 + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4 + +#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8 + +#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC + +#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00 + +#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30 + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34 + +#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38 + +#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C + +#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70 + +#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C80 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C84 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C88 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C90 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C94 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C98 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA0 + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA4 + +#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA8 + +#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD4 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD8 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC + +#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE0 + +#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF0 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D00 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D04 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D08 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D10 + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D14 + +#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D18 + +#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D20 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D24 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D28 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D30 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D34 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D38 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D40 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D44 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D48 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C + +#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D50 + +#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D54 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D58 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D60 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D64 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D68 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D70 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D74 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D78 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C + +#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D80 + +#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D84 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D88 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D90 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D94 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D98 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA4 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA8 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC + +#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB4 + +#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB8 + +#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC + +#define mmTPC4_CFG_QM_SRF_0 0xF06DC0 + +#define mmTPC4_CFG_QM_SRF_1 0xF06DC4 + +#define mmTPC4_CFG_QM_SRF_2 0xF06DC8 + +#define mmTPC4_CFG_QM_SRF_3 0xF06DCC + +#define mmTPC4_CFG_QM_SRF_4 0xF06DD0 + +#define mmTPC4_CFG_QM_SRF_5 0xF06DD4 + +#define mmTPC4_CFG_QM_SRF_6 0xF06DD8 + +#define mmTPC4_CFG_QM_SRF_7 0xF06DDC + +#define mmTPC4_CFG_QM_SRF_8 0xF06DE0 + +#define mmTPC4_CFG_QM_SRF_9 0xF06DE4 + +#define mmTPC4_CFG_QM_SRF_10 0xF06DE8 + +#define mmTPC4_CFG_QM_SRF_11 0xF06DEC + +#define mmTPC4_CFG_QM_SRF_12 0xF06DF0 + +#define mmTPC4_CFG_QM_SRF_13 0xF06DF4 + +#define mmTPC4_CFG_QM_SRF_14 0xF06DF8 + +#define mmTPC4_CFG_QM_SRF_15 0xF06DFC + +#define mmTPC4_CFG_QM_SRF_16 0xF06E00 + +#define mmTPC4_CFG_QM_SRF_17 0xF06E04 + +#define mmTPC4_CFG_QM_SRF_18 0xF06E08 + +#define mmTPC4_CFG_QM_SRF_19 0xF06E0C + +#define mmTPC4_CFG_QM_SRF_20 0xF06E10 + +#define mmTPC4_CFG_QM_SRF_21 0xF06E14 + +#define mmTPC4_CFG_QM_SRF_22 0xF06E18 + +#define mmTPC4_CFG_QM_SRF_23 0xF06E1C + +#define mmTPC4_CFG_QM_SRF_24 0xF06E20 + +#define mmTPC4_CFG_QM_SRF_25 0xF06E24 + +#define mmTPC4_CFG_QM_SRF_26 0xF06E28 + +#define mmTPC4_CFG_QM_SRF_27 0xF06E2C + +#define mmTPC4_CFG_QM_SRF_28 0xF06E30 + +#define mmTPC4_CFG_QM_SRF_29 0xF06E34 + +#define mmTPC4_CFG_QM_SRF_30 0xF06E38 + +#define mmTPC4_CFG_QM_SRF_31 0xF06E3C + +#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h new file mode 100644 index 000000000..80e63402f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_QM_REGS_H_ +#define ASIC_REG_TPC4_QM_REGS_H_ + +/* + ***************************************** + * TPC4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC4_QM_GLBL_CFG0 0xF08000 + +#define mmTPC4_QM_GLBL_CFG1 0xF08004 + +#define mmTPC4_QM_GLBL_PROT 0xF08008 + +#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034 + +#define mmTPC4_QM_GLBL_STS0 0xF08038 + +#define mmTPC4_QM_GLBL_STS1_0 0xF08040 + +#define mmTPC4_QM_GLBL_STS1_1 0xF08044 + +#define mmTPC4_QM_GLBL_STS1_2 0xF08048 + +#define mmTPC4_QM_GLBL_STS1_3 0xF0804C + +#define mmTPC4_QM_GLBL_STS1_4 0xF08050 + +#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054 + +#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058 + +#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C + +#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060 + +#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068 + +#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070 + +#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074 + +#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078 + +#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C + +#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080 + +#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084 + +#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088 + +#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C + +#define mmTPC4_QM_PQ_SIZE_0 0xF08090 + +#define mmTPC4_QM_PQ_SIZE_1 0xF08094 + +#define mmTPC4_QM_PQ_SIZE_2 0xF08098 + +#define mmTPC4_QM_PQ_SIZE_3 0xF0809C + +#define mmTPC4_QM_PQ_PI_0 0xF080A0 + +#define mmTPC4_QM_PQ_PI_1 0xF080A4 + +#define mmTPC4_QM_PQ_PI_2 0xF080A8 + +#define mmTPC4_QM_PQ_PI_3 0xF080AC + +#define mmTPC4_QM_PQ_CI_0 0xF080B0 + +#define mmTPC4_QM_PQ_CI_1 0xF080B4 + +#define mmTPC4_QM_PQ_CI_2 0xF080B8 + +#define mmTPC4_QM_PQ_CI_3 0xF080BC + +#define mmTPC4_QM_PQ_CFG0_0 0xF080C0 + +#define mmTPC4_QM_PQ_CFG0_1 0xF080C4 + +#define mmTPC4_QM_PQ_CFG0_2 0xF080C8 + +#define mmTPC4_QM_PQ_CFG0_3 0xF080CC + +#define mmTPC4_QM_PQ_CFG1_0 0xF080D0 + +#define mmTPC4_QM_PQ_CFG1_1 0xF080D4 + +#define mmTPC4_QM_PQ_CFG1_2 0xF080D8 + +#define mmTPC4_QM_PQ_CFG1_3 0xF080DC + +#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0 + +#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4 + +#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8 + +#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC + +#define mmTPC4_QM_PQ_STS0_0 0xF080F0 + +#define mmTPC4_QM_PQ_STS0_1 0xF080F4 + +#define mmTPC4_QM_PQ_STS0_2 0xF080F8 + +#define mmTPC4_QM_PQ_STS0_3 0xF080FC + +#define mmTPC4_QM_PQ_STS1_0 0xF08100 + +#define mmTPC4_QM_PQ_STS1_1 0xF08104 + +#define mmTPC4_QM_PQ_STS1_2 0xF08108 + +#define mmTPC4_QM_PQ_STS1_3 0xF0810C + +#define mmTPC4_QM_CQ_CFG0_0 0xF08110 + +#define mmTPC4_QM_CQ_CFG0_1 0xF08114 + +#define mmTPC4_QM_CQ_CFG0_2 0xF08118 + +#define mmTPC4_QM_CQ_CFG0_3 0xF0811C + +#define mmTPC4_QM_CQ_CFG0_4 0xF08120 + +#define mmTPC4_QM_CQ_CFG1_0 0xF08124 + +#define mmTPC4_QM_CQ_CFG1_1 0xF08128 + +#define mmTPC4_QM_CQ_CFG1_2 0xF0812C + +#define mmTPC4_QM_CQ_CFG1_3 0xF08130 + +#define mmTPC4_QM_CQ_CFG1_4 0xF08134 + +#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138 + +#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C + +#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140 + +#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144 + +#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148 + +#define mmTPC4_QM_CQ_STS0_0 0xF0814C + +#define mmTPC4_QM_CQ_STS0_1 0xF08150 + +#define mmTPC4_QM_CQ_STS0_2 0xF08154 + +#define mmTPC4_QM_CQ_STS0_3 0xF08158 + +#define mmTPC4_QM_CQ_STS0_4 0xF0815C + +#define mmTPC4_QM_CQ_STS1_0 0xF08160 + +#define mmTPC4_QM_CQ_STS1_1 0xF08164 + +#define mmTPC4_QM_CQ_STS1_2 0xF08168 + +#define mmTPC4_QM_CQ_STS1_3 0xF0816C + +#define mmTPC4_QM_CQ_STS1_4 0xF08170 + +#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174 + +#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178 + +#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C + +#define mmTPC4_QM_CQ_CTL_0 0xF08180 + +#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184 + +#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188 + +#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C + +#define mmTPC4_QM_CQ_CTL_1 0xF08190 + +#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194 + +#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198 + +#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C + +#define mmTPC4_QM_CQ_CTL_2 0xF081A0 + +#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4 + +#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8 + +#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC + +#define mmTPC4_QM_CQ_CTL_3 0xF081B0 + +#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4 + +#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8 + +#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC + +#define mmTPC4_QM_CQ_CTL_4 0xF081C0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4 + +#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8 + +#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC + +#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8 + +#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC + +#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0 + +#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8 + +#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC + +#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0 + +#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4 + +#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8 + +#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC + +#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200 + +#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204 + +#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208 + +#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C + +#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210 + +#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214 + +#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218 + +#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C + +#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220 + +#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304 + +#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308 + +#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C + +#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310 + +#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314 + +#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318 + +#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C + +#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320 + +#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324 + +#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328 + +#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C + +#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330 + +#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334 + +#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338 + +#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C + +#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340 + +#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344 + +#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348 + +#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C + +#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350 + +#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354 + +#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358 + +#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C + +#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360 + +#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364 + +#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368 + +#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C + +#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370 + +#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374 + +#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378 + +#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C + +#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380 + +#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384 + +#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388 + +#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C + +#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390 + +#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394 + +#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398 + +#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C + +#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0 + +#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4 + +#define mmTPC4_QM_CP_STS_0 0xF083A8 + +#define mmTPC4_QM_CP_STS_1 0xF083AC + +#define mmTPC4_QM_CP_STS_2 0xF083B0 + +#define mmTPC4_QM_CP_STS_3 0xF083B4 + +#define mmTPC4_QM_CP_STS_4 0xF083B8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC + +#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0 + +#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4 + +#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8 + +#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC + +#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400 + +#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404 + +#define mmTPC4_QM_CP_DBG_0_0 0xF08408 + +#define mmTPC4_QM_CP_DBG_0_1 0xF0840C + +#define mmTPC4_QM_CP_DBG_0_2 0xF08410 + +#define mmTPC4_QM_CP_DBG_0_3 0xF08414 + +#define mmTPC4_QM_CP_DBG_0_4 0xF08418 + +#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C + +#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420 + +#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424 + +#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428 + +#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C + +#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430 + +#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434 + +#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438 + +#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C + +#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440 + +#define mmTPC4_QM_ARB_CFG_0 0xF08A00 + +#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C + +#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14 + +#define mmTPC4_QM_ARB_CFG_1 0xF08A18 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C + +#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20 + +#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28 + +#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C + +#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34 + +#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38 + +#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C + +#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44 + +#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48 + +#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C + +#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50 + +#define mmTPC4_QM_ARB_BASE_LO 0xF08B54 + +#define mmTPC4_QM_ARB_BASE_HI 0xF08B58 + +#define mmTPC4_QM_ARB_STATE_STS 0xF08B80 + +#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84 + +#define mmTPC4_QM_ARB_MSG_STS 0xF08B88 + +#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C + +#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C + +#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0 + +#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC + +#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC + +#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC + +#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC + +#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC + +#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00 + +#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04 + +#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08 + +#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C + +#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10 + +#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14 + +#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18 + +#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C + +#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20 + +#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24 + +#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28 + +#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C + +#define mmTPC4_QM_CGM_CFG 0xF08C70 + +#define mmTPC4_QM_CGM_STS 0xF08C74 + +#define mmTPC4_QM_CGM_CFG1 0xF08C78 + +#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80 + +#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84 + +#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90 + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0 + +#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4 + +#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0 + +#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4 + +#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8 + +#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC + +#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0 + +#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4 + +#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8 + +#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00 + +#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h new file mode 100644 index 000000000..f428f8919 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CFG_REGS_H_ +#define ASIC_REG_TPC5_CFG_REGS_H_ + +/* + ***************************************** + * TPC5_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC + +#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780 + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4 + +#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8 + +#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC + +#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0 + +#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4 + +#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8 + +#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC + +#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0 + +#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4 + +#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8 + +#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC + +#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0 + +#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4 + +#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8 + +#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC + +#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0 + +#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4 + +#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8 + +#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC + +#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800 + +#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804 + +#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808 + +#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C + +#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810 + +#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814 + +#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818 + +#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C + +#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820 + +#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824 + +#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828 + +#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C + +#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830 + +#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834 + +#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838 + +#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C + +#define mmTPC5_CFG_ROUND_CSR 0xF468FC + +#define mmTPC5_CFG_PROT 0xF46900 + +#define mmTPC5_CFG_SEMAPHORE 0xF46908 + +#define mmTPC5_CFG_VFLAGS 0xF4690C + +#define mmTPC5_CFG_SFLAGS 0xF46910 + +#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918 + +#define mmTPC5_CFG_STATUS 0xF4691C + +#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920 + +#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C + +#define mmTPC5_CFG_TPC_CMD 0xF46930 + +#define mmTPC5_CFG_TPC_EXECUTE 0xF46938 + +#define mmTPC5_CFG_TPC_STALL 0xF4693C + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940 + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944 + +#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948 + +#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950 + +#define mmTPC5_CFG_MSS_CONFIG 0xF46954 + +#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958 + +#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C + +#define mmTPC5_CFG_WQ_CREDITS 0xF46960 + +#define mmTPC5_CFG_ARUSER_LO 0xF46964 + +#define mmTPC5_CFG_ARUSER_HI 0xF46968 + +#define mmTPC5_CFG_AWUSER_LO 0xF4696C + +#define mmTPC5_CFG_AWUSER_HI 0xF46970 + +#define mmTPC5_CFG_OPCODE_EXEC 0xF46974 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980 + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990 + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994 + +#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998 + +#define mmTPC5_CFG_TSB_CFG 0xF4699C + +#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0 + +#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4 + +#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8 + +#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC + +#define mmTPC5_CFG_DBGMEM_RC 0xF469B0 + +#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4 + +#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8 + +#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC + +#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0 + +#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4 + +#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0 + +#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 + +#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 + +#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C + +#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40 + +#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74 + +#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78 + +#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC + +#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0 + +#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0 + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4 + +#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8 + +#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C + +#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20 + +#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54 + +#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58 + +#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C + +#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90 + +#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0 + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4 + +#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8 + +#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC + +#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00 + +#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30 + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34 + +#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38 + +#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C + +#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70 + +#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0 + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4 + +#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8 + +#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC + +#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0 + +#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10 + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14 + +#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18 + +#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C + +#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50 + +#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C + +#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80 + +#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC + +#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4 + +#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8 + +#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC + +#define mmTPC5_CFG_QM_SRF_0 0xF46DC0 + +#define mmTPC5_CFG_QM_SRF_1 0xF46DC4 + +#define mmTPC5_CFG_QM_SRF_2 0xF46DC8 + +#define mmTPC5_CFG_QM_SRF_3 0xF46DCC + +#define mmTPC5_CFG_QM_SRF_4 0xF46DD0 + +#define mmTPC5_CFG_QM_SRF_5 0xF46DD4 + +#define mmTPC5_CFG_QM_SRF_6 0xF46DD8 + +#define mmTPC5_CFG_QM_SRF_7 0xF46DDC + +#define mmTPC5_CFG_QM_SRF_8 0xF46DE0 + +#define mmTPC5_CFG_QM_SRF_9 0xF46DE4 + +#define mmTPC5_CFG_QM_SRF_10 0xF46DE8 + +#define mmTPC5_CFG_QM_SRF_11 0xF46DEC + +#define mmTPC5_CFG_QM_SRF_12 0xF46DF0 + +#define mmTPC5_CFG_QM_SRF_13 0xF46DF4 + +#define mmTPC5_CFG_QM_SRF_14 0xF46DF8 + +#define mmTPC5_CFG_QM_SRF_15 0xF46DFC + +#define mmTPC5_CFG_QM_SRF_16 0xF46E00 + +#define mmTPC5_CFG_QM_SRF_17 0xF46E04 + +#define mmTPC5_CFG_QM_SRF_18 0xF46E08 + +#define mmTPC5_CFG_QM_SRF_19 0xF46E0C + +#define mmTPC5_CFG_QM_SRF_20 0xF46E10 + +#define mmTPC5_CFG_QM_SRF_21 0xF46E14 + +#define mmTPC5_CFG_QM_SRF_22 0xF46E18 + +#define mmTPC5_CFG_QM_SRF_23 0xF46E1C + +#define mmTPC5_CFG_QM_SRF_24 0xF46E20 + +#define mmTPC5_CFG_QM_SRF_25 0xF46E24 + +#define mmTPC5_CFG_QM_SRF_26 0xF46E28 + +#define mmTPC5_CFG_QM_SRF_27 0xF46E2C + +#define mmTPC5_CFG_QM_SRF_28 0xF46E30 + +#define mmTPC5_CFG_QM_SRF_29 0xF46E34 + +#define mmTPC5_CFG_QM_SRF_30 0xF46E38 + +#define mmTPC5_CFG_QM_SRF_31 0xF46E3C + +#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h new file mode 100644 index 000000000..cd3a810ff --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_QM_REGS_H_ +#define ASIC_REG_TPC5_QM_REGS_H_ + +/* + ***************************************** + * TPC5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC5_QM_GLBL_CFG0 0xF48000 + +#define mmTPC5_QM_GLBL_CFG1 0xF48004 + +#define mmTPC5_QM_GLBL_PROT 0xF48008 + +#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034 + +#define mmTPC5_QM_GLBL_STS0 0xF48038 + +#define mmTPC5_QM_GLBL_STS1_0 0xF48040 + +#define mmTPC5_QM_GLBL_STS1_1 0xF48044 + +#define mmTPC5_QM_GLBL_STS1_2 0xF48048 + +#define mmTPC5_QM_GLBL_STS1_3 0xF4804C + +#define mmTPC5_QM_GLBL_STS1_4 0xF48050 + +#define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054 + +#define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058 + +#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C + +#define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060 + +#define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068 + +#define mmTPC5_QM_PQ_BASE_LO_0 0xF48070 + +#define mmTPC5_QM_PQ_BASE_LO_1 0xF48074 + +#define mmTPC5_QM_PQ_BASE_LO_2 0xF48078 + +#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C + +#define mmTPC5_QM_PQ_BASE_HI_0 0xF48080 + +#define mmTPC5_QM_PQ_BASE_HI_1 0xF48084 + +#define mmTPC5_QM_PQ_BASE_HI_2 0xF48088 + +#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C + +#define mmTPC5_QM_PQ_SIZE_0 0xF48090 + +#define mmTPC5_QM_PQ_SIZE_1 0xF48094 + +#define mmTPC5_QM_PQ_SIZE_2 0xF48098 + +#define mmTPC5_QM_PQ_SIZE_3 0xF4809C + +#define mmTPC5_QM_PQ_PI_0 0xF480A0 + +#define mmTPC5_QM_PQ_PI_1 0xF480A4 + +#define mmTPC5_QM_PQ_PI_2 0xF480A8 + +#define mmTPC5_QM_PQ_PI_3 0xF480AC + +#define mmTPC5_QM_PQ_CI_0 0xF480B0 + +#define mmTPC5_QM_PQ_CI_1 0xF480B4 + +#define mmTPC5_QM_PQ_CI_2 0xF480B8 + +#define mmTPC5_QM_PQ_CI_3 0xF480BC + +#define mmTPC5_QM_PQ_CFG0_0 0xF480C0 + +#define mmTPC5_QM_PQ_CFG0_1 0xF480C4 + +#define mmTPC5_QM_PQ_CFG0_2 0xF480C8 + +#define mmTPC5_QM_PQ_CFG0_3 0xF480CC + +#define mmTPC5_QM_PQ_CFG1_0 0xF480D0 + +#define mmTPC5_QM_PQ_CFG1_1 0xF480D4 + +#define mmTPC5_QM_PQ_CFG1_2 0xF480D8 + +#define mmTPC5_QM_PQ_CFG1_3 0xF480DC + +#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0 + +#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4 + +#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8 + +#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC + +#define mmTPC5_QM_PQ_STS0_0 0xF480F0 + +#define mmTPC5_QM_PQ_STS0_1 0xF480F4 + +#define mmTPC5_QM_PQ_STS0_2 0xF480F8 + +#define mmTPC5_QM_PQ_STS0_3 0xF480FC + +#define mmTPC5_QM_PQ_STS1_0 0xF48100 + +#define mmTPC5_QM_PQ_STS1_1 0xF48104 + +#define mmTPC5_QM_PQ_STS1_2 0xF48108 + +#define mmTPC5_QM_PQ_STS1_3 0xF4810C + +#define mmTPC5_QM_CQ_CFG0_0 0xF48110 + +#define mmTPC5_QM_CQ_CFG0_1 0xF48114 + +#define mmTPC5_QM_CQ_CFG0_2 0xF48118 + +#define mmTPC5_QM_CQ_CFG0_3 0xF4811C + +#define mmTPC5_QM_CQ_CFG0_4 0xF48120 + +#define mmTPC5_QM_CQ_CFG1_0 0xF48124 + +#define mmTPC5_QM_CQ_CFG1_1 0xF48128 + +#define mmTPC5_QM_CQ_CFG1_2 0xF4812C + +#define mmTPC5_QM_CQ_CFG1_3 0xF48130 + +#define mmTPC5_QM_CQ_CFG1_4 0xF48134 + +#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138 + +#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C + +#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140 + +#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144 + +#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148 + +#define mmTPC5_QM_CQ_STS0_0 0xF4814C + +#define mmTPC5_QM_CQ_STS0_1 0xF48150 + +#define mmTPC5_QM_CQ_STS0_2 0xF48154 + +#define mmTPC5_QM_CQ_STS0_3 0xF48158 + +#define mmTPC5_QM_CQ_STS0_4 0xF4815C + +#define mmTPC5_QM_CQ_STS1_0 0xF48160 + +#define mmTPC5_QM_CQ_STS1_1 0xF48164 + +#define mmTPC5_QM_CQ_STS1_2 0xF48168 + +#define mmTPC5_QM_CQ_STS1_3 0xF4816C + +#define mmTPC5_QM_CQ_STS1_4 0xF48170 + +#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174 + +#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178 + +#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C + +#define mmTPC5_QM_CQ_CTL_0 0xF48180 + +#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184 + +#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188 + +#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C + +#define mmTPC5_QM_CQ_CTL_1 0xF48190 + +#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194 + +#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198 + +#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C + +#define mmTPC5_QM_CQ_CTL_2 0xF481A0 + +#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4 + +#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8 + +#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC + +#define mmTPC5_QM_CQ_CTL_3 0xF481B0 + +#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4 + +#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8 + +#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC + +#define mmTPC5_QM_CQ_CTL_4 0xF481C0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4 + +#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8 + +#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC + +#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8 + +#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC + +#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0 + +#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8 + +#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC + +#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0 + +#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4 + +#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8 + +#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC + +#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200 + +#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204 + +#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208 + +#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C + +#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210 + +#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214 + +#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218 + +#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C + +#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220 + +#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304 + +#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308 + +#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C + +#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310 + +#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314 + +#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318 + +#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C + +#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320 + +#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324 + +#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328 + +#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C + +#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330 + +#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334 + +#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338 + +#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C + +#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340 + +#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344 + +#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348 + +#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C + +#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350 + +#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354 + +#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358 + +#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C + +#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360 + +#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364 + +#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368 + +#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C + +#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370 + +#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374 + +#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378 + +#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C + +#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380 + +#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384 + +#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388 + +#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C + +#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390 + +#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394 + +#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398 + +#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C + +#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0 + +#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4 + +#define mmTPC5_QM_CP_STS_0 0xF483A8 + +#define mmTPC5_QM_CP_STS_1 0xF483AC + +#define mmTPC5_QM_CP_STS_2 0xF483B0 + +#define mmTPC5_QM_CP_STS_3 0xF483B4 + +#define mmTPC5_QM_CP_STS_4 0xF483B8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC + +#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0 + +#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4 + +#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8 + +#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC + +#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400 + +#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404 + +#define mmTPC5_QM_CP_DBG_0_0 0xF48408 + +#define mmTPC5_QM_CP_DBG_0_1 0xF4840C + +#define mmTPC5_QM_CP_DBG_0_2 0xF48410 + +#define mmTPC5_QM_CP_DBG_0_3 0xF48414 + +#define mmTPC5_QM_CP_DBG_0_4 0xF48418 + +#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C + +#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420 + +#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424 + +#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428 + +#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C + +#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430 + +#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434 + +#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438 + +#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C + +#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440 + +#define mmTPC5_QM_ARB_CFG_0 0xF48A00 + +#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C + +#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14 + +#define mmTPC5_QM_ARB_CFG_1 0xF48A18 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C + +#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20 + +#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28 + +#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C + +#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34 + +#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38 + +#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C + +#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44 + +#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48 + +#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C + +#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50 + +#define mmTPC5_QM_ARB_BASE_LO 0xF48B54 + +#define mmTPC5_QM_ARB_BASE_HI 0xF48B58 + +#define mmTPC5_QM_ARB_STATE_STS 0xF48B80 + +#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84 + +#define mmTPC5_QM_ARB_MSG_STS 0xF48B88 + +#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C + +#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C + +#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0 + +#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC + +#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC + +#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC + +#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC + +#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC + +#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00 + +#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04 + +#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08 + +#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C + +#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10 + +#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14 + +#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18 + +#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C + +#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20 + +#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24 + +#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28 + +#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C + +#define mmTPC5_QM_CGM_CFG 0xF48C70 + +#define mmTPC5_QM_CGM_STS 0xF48C74 + +#define mmTPC5_QM_CGM_CFG1 0xF48C78 + +#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80 + +#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84 + +#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90 + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0 + +#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4 + +#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0 + +#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4 + +#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8 + +#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC + +#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0 + +#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4 + +#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8 + +#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00 + +#endif /* ASIC_REG_TPC5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h new file mode 100644 index 000000000..eb251e728 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CFG_REGS_H_ +#define ASIC_REG_TPC6_CFG_REGS_H_ + +/* + ***************************************** + * TPC6_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF86418 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86420 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF86424 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86428 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86430 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86434 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF86438 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86440 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86444 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF86448 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86450 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF86454 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86458 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86460 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86464 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF86468 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86470 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF86474 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF86478 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF86480 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF86484 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF86488 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF86490 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF86494 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF86498 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC + +#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780 + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4 + +#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8 + +#define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC + +#define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0 + +#define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4 + +#define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8 + +#define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC + +#define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0 + +#define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4 + +#define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8 + +#define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC + +#define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0 + +#define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4 + +#define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8 + +#define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC + +#define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0 + +#define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4 + +#define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8 + +#define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC + +#define mmTPC6_CFG_KERNEL_SRF_16 0xF86800 + +#define mmTPC6_CFG_KERNEL_SRF_17 0xF86804 + +#define mmTPC6_CFG_KERNEL_SRF_18 0xF86808 + +#define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C + +#define mmTPC6_CFG_KERNEL_SRF_20 0xF86810 + +#define mmTPC6_CFG_KERNEL_SRF_21 0xF86814 + +#define mmTPC6_CFG_KERNEL_SRF_22 0xF86818 + +#define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C + +#define mmTPC6_CFG_KERNEL_SRF_24 0xF86820 + +#define mmTPC6_CFG_KERNEL_SRF_25 0xF86824 + +#define mmTPC6_CFG_KERNEL_SRF_26 0xF86828 + +#define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C + +#define mmTPC6_CFG_KERNEL_SRF_28 0xF86830 + +#define mmTPC6_CFG_KERNEL_SRF_29 0xF86834 + +#define mmTPC6_CFG_KERNEL_SRF_30 0xF86838 + +#define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C + +#define mmTPC6_CFG_ROUND_CSR 0xF868FC + +#define mmTPC6_CFG_PROT 0xF86900 + +#define mmTPC6_CFG_SEMAPHORE 0xF86908 + +#define mmTPC6_CFG_VFLAGS 0xF8690C + +#define mmTPC6_CFG_SFLAGS 0xF86910 + +#define mmTPC6_CFG_LFSR_POLYNOM 0xF86918 + +#define mmTPC6_CFG_STATUS 0xF8691C + +#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920 + +#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C + +#define mmTPC6_CFG_TPC_CMD 0xF86930 + +#define mmTPC6_CFG_TPC_EXECUTE 0xF86938 + +#define mmTPC6_CFG_TPC_STALL 0xF8693C + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940 + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944 + +#define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948 + +#define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950 + +#define mmTPC6_CFG_MSS_CONFIG 0xF86954 + +#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958 + +#define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C + +#define mmTPC6_CFG_WQ_CREDITS 0xF86960 + +#define mmTPC6_CFG_ARUSER_LO 0xF86964 + +#define mmTPC6_CFG_ARUSER_HI 0xF86968 + +#define mmTPC6_CFG_AWUSER_LO 0xF8696C + +#define mmTPC6_CFG_AWUSER_HI 0xF86970 + +#define mmTPC6_CFG_OPCODE_EXEC 0xF86974 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980 + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990 + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994 + +#define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998 + +#define mmTPC6_CFG_TSB_CFG 0xF8699C + +#define mmTPC6_CFG_DBGMEM_ADD 0xF869A0 + +#define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4 + +#define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8 + +#define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC + +#define mmTPC6_CFG_DBGMEM_RC 0xF869B0 + +#define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4 + +#define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8 + +#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC + +#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0 + +#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4 + +#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0 + +#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 + +#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 + +#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C + +#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40 + +#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74 + +#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78 + +#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC + +#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0 + +#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0 + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4 + +#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8 + +#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C + +#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20 + +#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54 + +#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58 + +#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C + +#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90 + +#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0 + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4 + +#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8 + +#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC + +#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00 + +#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30 + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34 + +#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38 + +#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C + +#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70 + +#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C80 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C84 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C88 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C90 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C94 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C98 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA0 + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA4 + +#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA8 + +#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD4 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD8 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC + +#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE0 + +#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF0 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D00 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D04 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D08 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D10 + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D14 + +#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D18 + +#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D20 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D24 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D28 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D30 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D34 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D38 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D40 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D44 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D48 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C + +#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D50 + +#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D54 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D58 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D60 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D64 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D68 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D70 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D74 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D78 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C + +#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D80 + +#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D84 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D88 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D90 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D94 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D98 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA4 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA8 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC + +#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB4 + +#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB8 + +#define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC + +#define mmTPC6_CFG_QM_SRF_0 0xF86DC0 + +#define mmTPC6_CFG_QM_SRF_1 0xF86DC4 + +#define mmTPC6_CFG_QM_SRF_2 0xF86DC8 + +#define mmTPC6_CFG_QM_SRF_3 0xF86DCC + +#define mmTPC6_CFG_QM_SRF_4 0xF86DD0 + +#define mmTPC6_CFG_QM_SRF_5 0xF86DD4 + +#define mmTPC6_CFG_QM_SRF_6 0xF86DD8 + +#define mmTPC6_CFG_QM_SRF_7 0xF86DDC + +#define mmTPC6_CFG_QM_SRF_8 0xF86DE0 + +#define mmTPC6_CFG_QM_SRF_9 0xF86DE4 + +#define mmTPC6_CFG_QM_SRF_10 0xF86DE8 + +#define mmTPC6_CFG_QM_SRF_11 0xF86DEC + +#define mmTPC6_CFG_QM_SRF_12 0xF86DF0 + +#define mmTPC6_CFG_QM_SRF_13 0xF86DF4 + +#define mmTPC6_CFG_QM_SRF_14 0xF86DF8 + +#define mmTPC6_CFG_QM_SRF_15 0xF86DFC + +#define mmTPC6_CFG_QM_SRF_16 0xF86E00 + +#define mmTPC6_CFG_QM_SRF_17 0xF86E04 + +#define mmTPC6_CFG_QM_SRF_18 0xF86E08 + +#define mmTPC6_CFG_QM_SRF_19 0xF86E0C + +#define mmTPC6_CFG_QM_SRF_20 0xF86E10 + +#define mmTPC6_CFG_QM_SRF_21 0xF86E14 + +#define mmTPC6_CFG_QM_SRF_22 0xF86E18 + +#define mmTPC6_CFG_QM_SRF_23 0xF86E1C + +#define mmTPC6_CFG_QM_SRF_24 0xF86E20 + +#define mmTPC6_CFG_QM_SRF_25 0xF86E24 + +#define mmTPC6_CFG_QM_SRF_26 0xF86E28 + +#define mmTPC6_CFG_QM_SRF_27 0xF86E2C + +#define mmTPC6_CFG_QM_SRF_28 0xF86E30 + +#define mmTPC6_CFG_QM_SRF_29 0xF86E34 + +#define mmTPC6_CFG_QM_SRF_30 0xF86E38 + +#define mmTPC6_CFG_QM_SRF_31 0xF86E3C + +#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h new file mode 100644 index 000000000..e35ef7fd8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_QM_REGS_H_ +#define ASIC_REG_TPC6_QM_REGS_H_ + +/* + ***************************************** + * TPC6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC6_QM_GLBL_CFG0 0xF88000 + +#define mmTPC6_QM_GLBL_CFG1 0xF88004 + +#define mmTPC6_QM_GLBL_PROT 0xF88008 + +#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_0 0xF88010 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_1 0xF88014 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_2 0xF88018 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_3 0xF8801C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_4 0xF88020 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 0xF88024 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 0xF88028 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 0xF8802C + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 0xF88030 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 0xF88034 + +#define mmTPC6_QM_GLBL_STS0 0xF88038 + +#define mmTPC6_QM_GLBL_STS1_0 0xF88040 + +#define mmTPC6_QM_GLBL_STS1_1 0xF88044 + +#define mmTPC6_QM_GLBL_STS1_2 0xF88048 + +#define mmTPC6_QM_GLBL_STS1_3 0xF8804C + +#define mmTPC6_QM_GLBL_STS1_4 0xF88050 + +#define mmTPC6_QM_GLBL_MSG_EN_0 0xF88054 + +#define mmTPC6_QM_GLBL_MSG_EN_1 0xF88058 + +#define mmTPC6_QM_GLBL_MSG_EN_2 0xF8805C + +#define mmTPC6_QM_GLBL_MSG_EN_3 0xF88060 + +#define mmTPC6_QM_GLBL_MSG_EN_4 0xF88068 + +#define mmTPC6_QM_PQ_BASE_LO_0 0xF88070 + +#define mmTPC6_QM_PQ_BASE_LO_1 0xF88074 + +#define mmTPC6_QM_PQ_BASE_LO_2 0xF88078 + +#define mmTPC6_QM_PQ_BASE_LO_3 0xF8807C + +#define mmTPC6_QM_PQ_BASE_HI_0 0xF88080 + +#define mmTPC6_QM_PQ_BASE_HI_1 0xF88084 + +#define mmTPC6_QM_PQ_BASE_HI_2 0xF88088 + +#define mmTPC6_QM_PQ_BASE_HI_3 0xF8808C + +#define mmTPC6_QM_PQ_SIZE_0 0xF88090 + +#define mmTPC6_QM_PQ_SIZE_1 0xF88094 + +#define mmTPC6_QM_PQ_SIZE_2 0xF88098 + +#define mmTPC6_QM_PQ_SIZE_3 0xF8809C + +#define mmTPC6_QM_PQ_PI_0 0xF880A0 + +#define mmTPC6_QM_PQ_PI_1 0xF880A4 + +#define mmTPC6_QM_PQ_PI_2 0xF880A8 + +#define mmTPC6_QM_PQ_PI_3 0xF880AC + +#define mmTPC6_QM_PQ_CI_0 0xF880B0 + +#define mmTPC6_QM_PQ_CI_1 0xF880B4 + +#define mmTPC6_QM_PQ_CI_2 0xF880B8 + +#define mmTPC6_QM_PQ_CI_3 0xF880BC + +#define mmTPC6_QM_PQ_CFG0_0 0xF880C0 + +#define mmTPC6_QM_PQ_CFG0_1 0xF880C4 + +#define mmTPC6_QM_PQ_CFG0_2 0xF880C8 + +#define mmTPC6_QM_PQ_CFG0_3 0xF880CC + +#define mmTPC6_QM_PQ_CFG1_0 0xF880D0 + +#define mmTPC6_QM_PQ_CFG1_1 0xF880D4 + +#define mmTPC6_QM_PQ_CFG1_2 0xF880D8 + +#define mmTPC6_QM_PQ_CFG1_3 0xF880DC + +#define mmTPC6_QM_PQ_ARUSER_31_11_0 0xF880E0 + +#define mmTPC6_QM_PQ_ARUSER_31_11_1 0xF880E4 + +#define mmTPC6_QM_PQ_ARUSER_31_11_2 0xF880E8 + +#define mmTPC6_QM_PQ_ARUSER_31_11_3 0xF880EC + +#define mmTPC6_QM_PQ_STS0_0 0xF880F0 + +#define mmTPC6_QM_PQ_STS0_1 0xF880F4 + +#define mmTPC6_QM_PQ_STS0_2 0xF880F8 + +#define mmTPC6_QM_PQ_STS0_3 0xF880FC + +#define mmTPC6_QM_PQ_STS1_0 0xF88100 + +#define mmTPC6_QM_PQ_STS1_1 0xF88104 + +#define mmTPC6_QM_PQ_STS1_2 0xF88108 + +#define mmTPC6_QM_PQ_STS1_3 0xF8810C + +#define mmTPC6_QM_CQ_CFG0_0 0xF88110 + +#define mmTPC6_QM_CQ_CFG0_1 0xF88114 + +#define mmTPC6_QM_CQ_CFG0_2 0xF88118 + +#define mmTPC6_QM_CQ_CFG0_3 0xF8811C + +#define mmTPC6_QM_CQ_CFG0_4 0xF88120 + +#define mmTPC6_QM_CQ_CFG1_0 0xF88124 + +#define mmTPC6_QM_CQ_CFG1_1 0xF88128 + +#define mmTPC6_QM_CQ_CFG1_2 0xF8812C + +#define mmTPC6_QM_CQ_CFG1_3 0xF88130 + +#define mmTPC6_QM_CQ_CFG1_4 0xF88134 + +#define mmTPC6_QM_CQ_ARUSER_31_11_0 0xF88138 + +#define mmTPC6_QM_CQ_ARUSER_31_11_1 0xF8813C + +#define mmTPC6_QM_CQ_ARUSER_31_11_2 0xF88140 + +#define mmTPC6_QM_CQ_ARUSER_31_11_3 0xF88144 + +#define mmTPC6_QM_CQ_ARUSER_31_11_4 0xF88148 + +#define mmTPC6_QM_CQ_STS0_0 0xF8814C + +#define mmTPC6_QM_CQ_STS0_1 0xF88150 + +#define mmTPC6_QM_CQ_STS0_2 0xF88154 + +#define mmTPC6_QM_CQ_STS0_3 0xF88158 + +#define mmTPC6_QM_CQ_STS0_4 0xF8815C + +#define mmTPC6_QM_CQ_STS1_0 0xF88160 + +#define mmTPC6_QM_CQ_STS1_1 0xF88164 + +#define mmTPC6_QM_CQ_STS1_2 0xF88168 + +#define mmTPC6_QM_CQ_STS1_3 0xF8816C + +#define mmTPC6_QM_CQ_STS1_4 0xF88170 + +#define mmTPC6_QM_CQ_PTR_LO_0 0xF88174 + +#define mmTPC6_QM_CQ_PTR_HI_0 0xF88178 + +#define mmTPC6_QM_CQ_TSIZE_0 0xF8817C + +#define mmTPC6_QM_CQ_CTL_0 0xF88180 + +#define mmTPC6_QM_CQ_PTR_LO_1 0xF88184 + +#define mmTPC6_QM_CQ_PTR_HI_1 0xF88188 + +#define mmTPC6_QM_CQ_TSIZE_1 0xF8818C + +#define mmTPC6_QM_CQ_CTL_1 0xF88190 + +#define mmTPC6_QM_CQ_PTR_LO_2 0xF88194 + +#define mmTPC6_QM_CQ_PTR_HI_2 0xF88198 + +#define mmTPC6_QM_CQ_TSIZE_2 0xF8819C + +#define mmTPC6_QM_CQ_CTL_2 0xF881A0 + +#define mmTPC6_QM_CQ_PTR_LO_3 0xF881A4 + +#define mmTPC6_QM_CQ_PTR_HI_3 0xF881A8 + +#define mmTPC6_QM_CQ_TSIZE_3 0xF881AC + +#define mmTPC6_QM_CQ_CTL_3 0xF881B0 + +#define mmTPC6_QM_CQ_PTR_LO_4 0xF881B4 + +#define mmTPC6_QM_CQ_PTR_HI_4 0xF881B8 + +#define mmTPC6_QM_CQ_TSIZE_4 0xF881BC + +#define mmTPC6_QM_CQ_CTL_4 0xF881C0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_0 0xF881C4 + +#define mmTPC6_QM_CQ_PTR_LO_STS_1 0xF881C8 + +#define mmTPC6_QM_CQ_PTR_LO_STS_2 0xF881CC + +#define mmTPC6_QM_CQ_PTR_LO_STS_3 0xF881D0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_4 0xF881D4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_0 0xF881D8 + +#define mmTPC6_QM_CQ_PTR_HI_STS_1 0xF881DC + +#define mmTPC6_QM_CQ_PTR_HI_STS_2 0xF881E0 + +#define mmTPC6_QM_CQ_PTR_HI_STS_3 0xF881E4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_4 0xF881E8 + +#define mmTPC6_QM_CQ_TSIZE_STS_0 0xF881EC + +#define mmTPC6_QM_CQ_TSIZE_STS_1 0xF881F0 + +#define mmTPC6_QM_CQ_TSIZE_STS_2 0xF881F4 + +#define mmTPC6_QM_CQ_TSIZE_STS_3 0xF881F8 + +#define mmTPC6_QM_CQ_TSIZE_STS_4 0xF881FC + +#define mmTPC6_QM_CQ_CTL_STS_0 0xF88200 + +#define mmTPC6_QM_CQ_CTL_STS_1 0xF88204 + +#define mmTPC6_QM_CQ_CTL_STS_2 0xF88208 + +#define mmTPC6_QM_CQ_CTL_STS_3 0xF8820C + +#define mmTPC6_QM_CQ_CTL_STS_4 0xF88210 + +#define mmTPC6_QM_CQ_IFIFO_CNT_0 0xF88214 + +#define mmTPC6_QM_CQ_IFIFO_CNT_1 0xF88218 + +#define mmTPC6_QM_CQ_IFIFO_CNT_2 0xF8821C + +#define mmTPC6_QM_CQ_IFIFO_CNT_3 0xF88220 + +#define mmTPC6_QM_CQ_IFIFO_CNT_4 0xF88224 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 0xF88228 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 0xF8822C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 0xF88230 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 0xF88234 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 0xF88238 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 0xF8823C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 0xF88240 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 0xF88244 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 0xF88248 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 0xF8824C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 0xF88250 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 0xF88254 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 0xF88258 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 0xF8825C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 0xF88260 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 0xF88264 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 0xF88268 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 0xF8826C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 0xF88270 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 0xF88274 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 0xF88278 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 0xF8827C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 0xF88280 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 0xF88284 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 0xF88288 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 0xF8828C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 0xF88290 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 0xF88294 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 0xF88298 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 0xF8829C + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 0xF882A0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 0xF882A4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 0xF882A8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 0xF882AC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 0xF882B0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 0xF882B4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 0xF882B8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 0xF882BC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 0xF882C0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 0xF882C4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 0xF882C8 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 0xF882CC + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 0xF882D0 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 0xF882D4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 0xF882D8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF882E0 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF882E4 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF882E8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF882EC + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF882F0 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF882F4 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF882F8 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF882FC + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF88300 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF88304 + +#define mmTPC6_QM_CP_FENCE0_RDATA_0 0xF88308 + +#define mmTPC6_QM_CP_FENCE0_RDATA_1 0xF8830C + +#define mmTPC6_QM_CP_FENCE0_RDATA_2 0xF88310 + +#define mmTPC6_QM_CP_FENCE0_RDATA_3 0xF88314 + +#define mmTPC6_QM_CP_FENCE0_RDATA_4 0xF88318 + +#define mmTPC6_QM_CP_FENCE1_RDATA_0 0xF8831C + +#define mmTPC6_QM_CP_FENCE1_RDATA_1 0xF88320 + +#define mmTPC6_QM_CP_FENCE1_RDATA_2 0xF88324 + +#define mmTPC6_QM_CP_FENCE1_RDATA_3 0xF88328 + +#define mmTPC6_QM_CP_FENCE1_RDATA_4 0xF8832C + +#define mmTPC6_QM_CP_FENCE2_RDATA_0 0xF88330 + +#define mmTPC6_QM_CP_FENCE2_RDATA_1 0xF88334 + +#define mmTPC6_QM_CP_FENCE2_RDATA_2 0xF88338 + +#define mmTPC6_QM_CP_FENCE2_RDATA_3 0xF8833C + +#define mmTPC6_QM_CP_FENCE2_RDATA_4 0xF88340 + +#define mmTPC6_QM_CP_FENCE3_RDATA_0 0xF88344 + +#define mmTPC6_QM_CP_FENCE3_RDATA_1 0xF88348 + +#define mmTPC6_QM_CP_FENCE3_RDATA_2 0xF8834C + +#define mmTPC6_QM_CP_FENCE3_RDATA_3 0xF88350 + +#define mmTPC6_QM_CP_FENCE3_RDATA_4 0xF88354 + +#define mmTPC6_QM_CP_FENCE0_CNT_0 0xF88358 + +#define mmTPC6_QM_CP_FENCE0_CNT_1 0xF8835C + +#define mmTPC6_QM_CP_FENCE0_CNT_2 0xF88360 + +#define mmTPC6_QM_CP_FENCE0_CNT_3 0xF88364 + +#define mmTPC6_QM_CP_FENCE0_CNT_4 0xF88368 + +#define mmTPC6_QM_CP_FENCE1_CNT_0 0xF8836C + +#define mmTPC6_QM_CP_FENCE1_CNT_1 0xF88370 + +#define mmTPC6_QM_CP_FENCE1_CNT_2 0xF88374 + +#define mmTPC6_QM_CP_FENCE1_CNT_3 0xF88378 + +#define mmTPC6_QM_CP_FENCE1_CNT_4 0xF8837C + +#define mmTPC6_QM_CP_FENCE2_CNT_0 0xF88380 + +#define mmTPC6_QM_CP_FENCE2_CNT_1 0xF88384 + +#define mmTPC6_QM_CP_FENCE2_CNT_2 0xF88388 + +#define mmTPC6_QM_CP_FENCE2_CNT_3 0xF8838C + +#define mmTPC6_QM_CP_FENCE2_CNT_4 0xF88390 + +#define mmTPC6_QM_CP_FENCE3_CNT_0 0xF88394 + +#define mmTPC6_QM_CP_FENCE3_CNT_1 0xF88398 + +#define mmTPC6_QM_CP_FENCE3_CNT_2 0xF8839C + +#define mmTPC6_QM_CP_FENCE3_CNT_3 0xF883A0 + +#define mmTPC6_QM_CP_FENCE3_CNT_4 0xF883A4 + +#define mmTPC6_QM_CP_STS_0 0xF883A8 + +#define mmTPC6_QM_CP_STS_1 0xF883AC + +#define mmTPC6_QM_CP_STS_2 0xF883B0 + +#define mmTPC6_QM_CP_STS_3 0xF883B4 + +#define mmTPC6_QM_CP_STS_4 0xF883B8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_0 0xF883BC + +#define mmTPC6_QM_CP_CURRENT_INST_LO_1 0xF883C0 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_2 0xF883C4 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_3 0xF883C8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_4 0xF883CC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_0 0xF883D0 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_1 0xF883D4 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_2 0xF883D8 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_3 0xF883DC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_4 0xF883E0 + +#define mmTPC6_QM_CP_BARRIER_CFG_0 0xF883F4 + +#define mmTPC6_QM_CP_BARRIER_CFG_1 0xF883F8 + +#define mmTPC6_QM_CP_BARRIER_CFG_2 0xF883FC + +#define mmTPC6_QM_CP_BARRIER_CFG_3 0xF88400 + +#define mmTPC6_QM_CP_BARRIER_CFG_4 0xF88404 + +#define mmTPC6_QM_CP_DBG_0_0 0xF88408 + +#define mmTPC6_QM_CP_DBG_0_1 0xF8840C + +#define mmTPC6_QM_CP_DBG_0_2 0xF88410 + +#define mmTPC6_QM_CP_DBG_0_3 0xF88414 + +#define mmTPC6_QM_CP_DBG_0_4 0xF88418 + +#define mmTPC6_QM_CP_ARUSER_31_11_0 0xF8841C + +#define mmTPC6_QM_CP_ARUSER_31_11_1 0xF88420 + +#define mmTPC6_QM_CP_ARUSER_31_11_2 0xF88424 + +#define mmTPC6_QM_CP_ARUSER_31_11_3 0xF88428 + +#define mmTPC6_QM_CP_ARUSER_31_11_4 0xF8842C + +#define mmTPC6_QM_CP_AWUSER_31_11_0 0xF88430 + +#define mmTPC6_QM_CP_AWUSER_31_11_1 0xF88434 + +#define mmTPC6_QM_CP_AWUSER_31_11_2 0xF88438 + +#define mmTPC6_QM_CP_AWUSER_31_11_3 0xF8843C + +#define mmTPC6_QM_CP_AWUSER_31_11_4 0xF88440 + +#define mmTPC6_QM_ARB_CFG_0 0xF88A00 + +#define mmTPC6_QM_ARB_CHOISE_Q_PUSH 0xF88A04 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_0 0xF88A08 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_1 0xF88A0C + +#define mmTPC6_QM_ARB_WRR_WEIGHT_2 0xF88A10 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_3 0xF88A14 + +#define mmTPC6_QM_ARB_CFG_1 0xF88A18 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_0 0xF88A20 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_1 0xF88A24 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_2 0xF88A28 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_3 0xF88A2C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_4 0xF88A30 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_5 0xF88A34 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_6 0xF88A38 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_7 0xF88A3C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_8 0xF88A40 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_9 0xF88A44 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_10 0xF88A48 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_11 0xF88A4C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_12 0xF88A50 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_13 0xF88A54 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_14 0xF88A58 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_15 0xF88A5C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_16 0xF88A60 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_17 0xF88A64 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_18 0xF88A68 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_19 0xF88A6C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_20 0xF88A70 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_21 0xF88A74 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_22 0xF88A78 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_23 0xF88A7C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_24 0xF88A80 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_25 0xF88A84 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_26 0xF88A88 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_27 0xF88A8C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_28 0xF88A90 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_29 0xF88A94 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_30 0xF88A98 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_31 0xF88A9C + +#define mmTPC6_QM_ARB_MST_CRED_INC 0xF88AA0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF88AA4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF88AA8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF88AAC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF88AB0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF88AB4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF88AB8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF88ABC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF88AC0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF88AC4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF88AC8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF88ACC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF88AD0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF88AD4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF88AD8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF88ADC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF88AE0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF88AE4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF88AE8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF88AEC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF88AF0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF88AF4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF88AF8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF88AFC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF88B00 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF88B04 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF88B08 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF88B0C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF88B10 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF88B14 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF88B18 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF88B1C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF88B20 + +#define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF88B28 + +#define mmTPC6_QM_ARB_MST_SLAVE_EN 0xF88B2C + +#define mmTPC6_QM_ARB_MST_QUIET_PER 0xF88B34 + +#define mmTPC6_QM_ARB_SLV_CHOISE_WDT 0xF88B38 + +#define mmTPC6_QM_ARB_SLV_ID 0xF88B3C + +#define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT 0xF88B44 + +#define mmTPC6_QM_ARB_MSG_AWUSER_31_11 0xF88B48 + +#define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP 0xF88B4C + +#define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF88B50 + +#define mmTPC6_QM_ARB_BASE_LO 0xF88B54 + +#define mmTPC6_QM_ARB_BASE_HI 0xF88B58 + +#define mmTPC6_QM_ARB_STATE_STS 0xF88B80 + +#define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS 0xF88B84 + +#define mmTPC6_QM_ARB_MSG_STS 0xF88B88 + +#define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD 0xF88B8C + +#define mmTPC6_QM_ARB_ERR_CAUSE 0xF88B9C + +#define mmTPC6_QM_ARB_ERR_MSG_EN 0xF88BA0 + +#define mmTPC6_QM_ARB_ERR_STS_DRP 0xF88BA8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_0 0xF88BB0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_1 0xF88BB4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_2 0xF88BB8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_3 0xF88BBC + +#define mmTPC6_QM_ARB_MST_CRED_STS_4 0xF88BC0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_5 0xF88BC4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_6 0xF88BC8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_7 0xF88BCC + +#define mmTPC6_QM_ARB_MST_CRED_STS_8 0xF88BD0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_9 0xF88BD4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_10 0xF88BD8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_11 0xF88BDC + +#define mmTPC6_QM_ARB_MST_CRED_STS_12 0xF88BE0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_13 0xF88BE4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_14 0xF88BE8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_15 0xF88BEC + +#define mmTPC6_QM_ARB_MST_CRED_STS_16 0xF88BF0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_17 0xF88BF4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_18 0xF88BF8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_19 0xF88BFC + +#define mmTPC6_QM_ARB_MST_CRED_STS_20 0xF88C00 + +#define mmTPC6_QM_ARB_MST_CRED_STS_21 0xF88C04 + +#define mmTPC6_QM_ARB_MST_CRED_STS_22 0xF88C08 + +#define mmTPC6_QM_ARB_MST_CRED_STS_23 0xF88C0C + +#define mmTPC6_QM_ARB_MST_CRED_STS_24 0xF88C10 + +#define mmTPC6_QM_ARB_MST_CRED_STS_25 0xF88C14 + +#define mmTPC6_QM_ARB_MST_CRED_STS_26 0xF88C18 + +#define mmTPC6_QM_ARB_MST_CRED_STS_27 0xF88C1C + +#define mmTPC6_QM_ARB_MST_CRED_STS_28 0xF88C20 + +#define mmTPC6_QM_ARB_MST_CRED_STS_29 0xF88C24 + +#define mmTPC6_QM_ARB_MST_CRED_STS_30 0xF88C28 + +#define mmTPC6_QM_ARB_MST_CRED_STS_31 0xF88C2C + +#define mmTPC6_QM_CGM_CFG 0xF88C70 + +#define mmTPC6_QM_CGM_STS 0xF88C74 + +#define mmTPC6_QM_CGM_CFG1 0xF88C78 + +#define mmTPC6_QM_LOCAL_RANGE_BASE 0xF88C80 + +#define mmTPC6_QM_LOCAL_RANGE_SIZE 0xF88C84 + +#define mmTPC6_QM_CSMR_STRICT_PRIO_CFG 0xF88C90 + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 0xF88C94 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 0xF88C98 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 0xF88C9C + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 0xF88CA0 + +#define mmTPC6_QM_GLBL_AXCACHE 0xF88CA4 + +#define mmTPC6_QM_IND_GW_APB_CFG 0xF88CB0 + +#define mmTPC6_QM_IND_GW_APB_WDATA 0xF88CB4 + +#define mmTPC6_QM_IND_GW_APB_RDATA 0xF88CB8 + +#define mmTPC6_QM_IND_GW_APB_STATUS 0xF88CBC + +#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88CD0 + +#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88CD4 + +#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88CD8 + +#define mmTPC6_QM_GLBL_MEM_INIT_BUSY 0xF88D00 + +#endif /* ASIC_REG_TPC6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h new file mode 100644 index 000000000..1887b10e5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CFG_REGS_H_ +#define ASIC_REG_TPC7_CFG_REGS_H_ + +/* + ***************************************** + * TPC7_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC6418 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC641C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6420 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC6424 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6428 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC642C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6430 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6434 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC6438 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC643C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6440 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6444 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC6448 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC644C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6450 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC6454 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6458 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC645C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6460 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6464 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC6468 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC646C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6470 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC6474 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC6478 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC647C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC6480 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC6484 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC6488 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC648C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC6490 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC6494 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC6498 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC649C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64AC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64BC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC64C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC64C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC64C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC64CC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC64D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC64D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC64D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC64DC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC64E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC64E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC64E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC64EC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC64F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC64F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC64F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC64FC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6500 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC6504 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6508 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC650C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6510 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6514 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC6518 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC651C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6520 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6524 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC6528 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC652C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6530 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC6534 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC6538 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC653C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC6540 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC6544 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC6548 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC654C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC6550 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC6554 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC6558 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC655C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC6560 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC6564 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC6568 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC656C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC6570 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC6574 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC6578 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC657C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6580 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC6584 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6588 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC658C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC6590 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6594 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6598 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC659C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC65A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC65A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC65A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC65AC + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC65B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC65B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC65B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC65BC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xFC65C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xFC65C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xFC65C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xFC65CC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xFC65D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xFC65D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xFC65D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xFC65DC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xFC65E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xFC65E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xFC65E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xFC65EC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xFC65F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xFC65F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xFC65F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xFC65FC + +#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xFC6600 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xFC6604 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xFC6608 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xFC660C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xFC6610 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xFC6614 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xFC6618 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xFC661C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xFC6620 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xFC6624 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xFC6628 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xFC662C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xFC6630 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xFC6634 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xFC6638 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xFC663C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xFC6640 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xFC6644 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xFC6648 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xFC664C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xFC6650 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xFC6654 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xFC6658 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xFC665C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xFC6660 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xFC6664 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xFC6668 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xFC666C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xFC6670 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xFC6674 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xFC6678 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xFC667C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xFC6680 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xFC6684 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xFC6688 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xFC668C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xFC6690 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xFC6694 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xFC6698 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xFC669C + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xFC66A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xFC66A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xFC66A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xFC66AC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xFC66B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xFC66B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xFC66B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xFC66BC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xFC66C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xFC66C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xFC66C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xFC66CC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xFC66D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xFC66D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xFC66D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xFC66DC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xFC66E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xFC66E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xFC66E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xFC66EC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xFC66F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xFC66F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xFC66F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xFC66FC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xFC6700 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xFC6704 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xFC6708 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xFC670C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xFC6710 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xFC6714 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xFC6718 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xFC671C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xFC6720 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xFC6724 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xFC6728 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xFC672C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xFC6730 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xFC6734 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xFC6738 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xFC673C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xFC6740 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xFC6744 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xFC6748 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xFC674C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xFC6750 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xFC6754 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xFC6758 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xFC675C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xFC6760 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xFC6764 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xFC6768 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xFC676C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xFC6770 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xFC6774 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xFC6778 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xFC677C + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6780 + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR 0xFC6784 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6788 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC678C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6790 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC6794 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6798 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC679C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC67A0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC67A4 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC67A8 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC67AC + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC67B0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC67B4 + +#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC67B8 + +#define mmTPC7_CFG_KERNEL_KERNEL_ID 0xFC67BC + +#define mmTPC7_CFG_KERNEL_SRF_0 0xFC67C0 + +#define mmTPC7_CFG_KERNEL_SRF_1 0xFC67C4 + +#define mmTPC7_CFG_KERNEL_SRF_2 0xFC67C8 + +#define mmTPC7_CFG_KERNEL_SRF_3 0xFC67CC + +#define mmTPC7_CFG_KERNEL_SRF_4 0xFC67D0 + +#define mmTPC7_CFG_KERNEL_SRF_5 0xFC67D4 + +#define mmTPC7_CFG_KERNEL_SRF_6 0xFC67D8 + +#define mmTPC7_CFG_KERNEL_SRF_7 0xFC67DC + +#define mmTPC7_CFG_KERNEL_SRF_8 0xFC67E0 + +#define mmTPC7_CFG_KERNEL_SRF_9 0xFC67E4 + +#define mmTPC7_CFG_KERNEL_SRF_10 0xFC67E8 + +#define mmTPC7_CFG_KERNEL_SRF_11 0xFC67EC + +#define mmTPC7_CFG_KERNEL_SRF_12 0xFC67F0 + +#define mmTPC7_CFG_KERNEL_SRF_13 0xFC67F4 + +#define mmTPC7_CFG_KERNEL_SRF_14 0xFC67F8 + +#define mmTPC7_CFG_KERNEL_SRF_15 0xFC67FC + +#define mmTPC7_CFG_KERNEL_SRF_16 0xFC6800 + +#define mmTPC7_CFG_KERNEL_SRF_17 0xFC6804 + +#define mmTPC7_CFG_KERNEL_SRF_18 0xFC6808 + +#define mmTPC7_CFG_KERNEL_SRF_19 0xFC680C + +#define mmTPC7_CFG_KERNEL_SRF_20 0xFC6810 + +#define mmTPC7_CFG_KERNEL_SRF_21 0xFC6814 + +#define mmTPC7_CFG_KERNEL_SRF_22 0xFC6818 + +#define mmTPC7_CFG_KERNEL_SRF_23 0xFC681C + +#define mmTPC7_CFG_KERNEL_SRF_24 0xFC6820 + +#define mmTPC7_CFG_KERNEL_SRF_25 0xFC6824 + +#define mmTPC7_CFG_KERNEL_SRF_26 0xFC6828 + +#define mmTPC7_CFG_KERNEL_SRF_27 0xFC682C + +#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6830 + +#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6834 + +#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6838 + +#define mmTPC7_CFG_KERNEL_SRF_31 0xFC683C + +#define mmTPC7_CFG_ROUND_CSR 0xFC68FC + +#define mmTPC7_CFG_PROT 0xFC6900 + +#define mmTPC7_CFG_SEMAPHORE 0xFC6908 + +#define mmTPC7_CFG_VFLAGS 0xFC690C + +#define mmTPC7_CFG_SFLAGS 0xFC6910 + +#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6918 + +#define mmTPC7_CFG_STATUS 0xFC691C + +#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6920 + +#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6924 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC692C + +#define mmTPC7_CFG_TPC_CMD 0xFC6930 + +#define mmTPC7_CFG_TPC_EXECUTE 0xFC6938 + +#define mmTPC7_CFG_TPC_STALL 0xFC693C + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6940 + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6944 + +#define mmTPC7_CFG_RD_RATE_LIMIT 0xFC6948 + +#define mmTPC7_CFG_WR_RATE_LIMIT 0xFC6950 + +#define mmTPC7_CFG_MSS_CONFIG 0xFC6954 + +#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6958 + +#define mmTPC7_CFG_TPC_INTR_MASK 0xFC695C + +#define mmTPC7_CFG_WQ_CREDITS 0xFC6960 + +#define mmTPC7_CFG_ARUSER_LO 0xFC6964 + +#define mmTPC7_CFG_ARUSER_HI 0xFC6968 + +#define mmTPC7_CFG_AWUSER_LO 0xFC696C + +#define mmTPC7_CFG_AWUSER_HI 0xFC6970 + +#define mmTPC7_CFG_OPCODE_EXEC 0xFC6974 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO 0xFC6978 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI 0xFC697C + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO 0xFC6980 + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI 0xFC6984 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO 0xFC6988 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI 0xFC698C + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO 0xFC6990 + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI 0xFC6994 + +#define mmTPC7_CFG_TSB_CFG_MAX_SIZE 0xFC6998 + +#define mmTPC7_CFG_TSB_CFG 0xFC699C + +#define mmTPC7_CFG_DBGMEM_ADD 0xFC69A0 + +#define mmTPC7_CFG_DBGMEM_DATA_WR 0xFC69A4 + +#define mmTPC7_CFG_DBGMEM_DATA_RD 0xFC69A8 + +#define mmTPC7_CFG_DBGMEM_CTRL 0xFC69AC + +#define mmTPC7_CFG_DBGMEM_RC 0xFC69B0 + +#define mmTPC7_CFG_TSB_INFLIGHT_CNTR 0xFC69B4 + +#define mmTPC7_CFG_WQ_INFLIGHT_CNTR 0xFC69B8 + +#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR 0xFC69BC + +#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR 0xFC69C0 + +#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR 0xFC69C4 + +#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC69D0 + +#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC69D4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC69D8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC69DC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC69E0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC69E4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC69E8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC69EC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC69F0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC69F4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC69F8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC69FC + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04 + +#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08 + +#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A18 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A1C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A20 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A24 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A28 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A2C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A30 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A34 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A38 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A3C + +#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A40 + +#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A44 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A48 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A4C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A50 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A54 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A58 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A5C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A60 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A64 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A68 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A6C + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A70 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A74 + +#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6A78 + +#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6A7C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6A80 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6A84 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6A88 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6A8C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6A90 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6A94 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6A98 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6A9C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AA0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6AA4 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AA8 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AAC + +#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AB0 + +#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AB4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AB8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6ABC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6AC0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6AC4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6AC8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6ACC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6AD0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6AD4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6AD8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6ADC + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6AE0 + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6AE4 + +#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6AE8 + +#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6AEC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6AF0 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6AF4 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6AF8 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6AFC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B00 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B04 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B08 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B0C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B10 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B14 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B18 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B1C + +#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B20 + +#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B24 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B28 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B2C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B30 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B34 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6B38 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6B3C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6B40 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6B44 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6B48 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6B4C + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6B50 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6B54 + +#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6B58 + +#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6B5C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6B60 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6B64 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6B68 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6B6C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6B70 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6B74 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6B78 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6B7C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6B80 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6B84 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6B88 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6B8C + +#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6B90 + +#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6B94 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6B98 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6B9C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6BA0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6BA4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6BA8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6BAC + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6BB0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6BB4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6BB8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6BBC + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xFC6BC0 + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xFC6BC4 + +#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE 0xFC6BC8 + +#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xFC6BCC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE 0xFC6BD0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xFC6BD4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE 0xFC6BD8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xFC6BDC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE 0xFC6BE0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xFC6BE4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE 0xFC6BE8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xFC6BEC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE 0xFC6BF0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xFC6BF4 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xFC6BF8 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xFC6BFC + +#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE 0xFC6C00 + +#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xFC6C04 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE 0xFC6C08 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xFC6C0C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE 0xFC6C10 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xFC6C14 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE 0xFC6C18 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xFC6C1C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE 0xFC6C20 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xFC6C24 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE 0xFC6C28 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xFC6C2C + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xFC6C30 + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xFC6C34 + +#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE 0xFC6C38 + +#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xFC6C3C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE 0xFC6C40 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xFC6C44 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE 0xFC6C48 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xFC6C4C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE 0xFC6C50 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xFC6C54 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE 0xFC6C58 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xFC6C5C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE 0xFC6C60 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xFC6C64 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xFC6C68 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xFC6C6C + +#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE 0xFC6C70 + +#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xFC6C74 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE 0xFC6C78 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xFC6C7C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE 0xFC6C80 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xFC6C84 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE 0xFC6C88 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xFC6C8C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE 0xFC6C90 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xFC6C94 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE 0xFC6C98 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xFC6C9C + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xFC6CA0 + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xFC6CA4 + +#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE 0xFC6CA8 + +#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xFC6CAC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE 0xFC6CB0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xFC6CB4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE 0xFC6CB8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xFC6CBC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE 0xFC6CC0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xFC6CC4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE 0xFC6CC8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xFC6CCC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE 0xFC6CD0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xFC6CD4 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xFC6CD8 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xFC6CDC + +#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE 0xFC6CE0 + +#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xFC6CE4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE 0xFC6CE8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xFC6CEC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE 0xFC6CF0 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xFC6CF4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE 0xFC6CF8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xFC6CFC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE 0xFC6D00 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xFC6D04 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE 0xFC6D08 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xFC6D0C + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xFC6D10 + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xFC6D14 + +#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE 0xFC6D18 + +#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xFC6D1C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE 0xFC6D20 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xFC6D24 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE 0xFC6D28 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xFC6D2C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE 0xFC6D30 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xFC6D34 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE 0xFC6D38 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xFC6D3C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE 0xFC6D40 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xFC6D44 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xFC6D48 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xFC6D4C + +#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE 0xFC6D50 + +#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xFC6D54 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE 0xFC6D58 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xFC6D5C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE 0xFC6D60 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xFC6D64 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE 0xFC6D68 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xFC6D6C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE 0xFC6D70 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xFC6D74 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE 0xFC6D78 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xFC6D7C + +#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D80 + +#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR 0xFC6D84 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6D88 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6D8C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6D90 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6D94 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6D98 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6D9C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6DA0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6DA4 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6DA8 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6DAC + +#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6DB0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6DB4 + +#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6DB8 + +#define mmTPC7_CFG_QM_KERNEL_ID 0xFC6DBC + +#define mmTPC7_CFG_QM_SRF_0 0xFC6DC0 + +#define mmTPC7_CFG_QM_SRF_1 0xFC6DC4 + +#define mmTPC7_CFG_QM_SRF_2 0xFC6DC8 + +#define mmTPC7_CFG_QM_SRF_3 0xFC6DCC + +#define mmTPC7_CFG_QM_SRF_4 0xFC6DD0 + +#define mmTPC7_CFG_QM_SRF_5 0xFC6DD4 + +#define mmTPC7_CFG_QM_SRF_6 0xFC6DD8 + +#define mmTPC7_CFG_QM_SRF_7 0xFC6DDC + +#define mmTPC7_CFG_QM_SRF_8 0xFC6DE0 + +#define mmTPC7_CFG_QM_SRF_9 0xFC6DE4 + +#define mmTPC7_CFG_QM_SRF_10 0xFC6DE8 + +#define mmTPC7_CFG_QM_SRF_11 0xFC6DEC + +#define mmTPC7_CFG_QM_SRF_12 0xFC6DF0 + +#define mmTPC7_CFG_QM_SRF_13 0xFC6DF4 + +#define mmTPC7_CFG_QM_SRF_14 0xFC6DF8 + +#define mmTPC7_CFG_QM_SRF_15 0xFC6DFC + +#define mmTPC7_CFG_QM_SRF_16 0xFC6E00 + +#define mmTPC7_CFG_QM_SRF_17 0xFC6E04 + +#define mmTPC7_CFG_QM_SRF_18 0xFC6E08 + +#define mmTPC7_CFG_QM_SRF_19 0xFC6E0C + +#define mmTPC7_CFG_QM_SRF_20 0xFC6E10 + +#define mmTPC7_CFG_QM_SRF_21 0xFC6E14 + +#define mmTPC7_CFG_QM_SRF_22 0xFC6E18 + +#define mmTPC7_CFG_QM_SRF_23 0xFC6E1C + +#define mmTPC7_CFG_QM_SRF_24 0xFC6E20 + +#define mmTPC7_CFG_QM_SRF_25 0xFC6E24 + +#define mmTPC7_CFG_QM_SRF_26 0xFC6E28 + +#define mmTPC7_CFG_QM_SRF_27 0xFC6E2C + +#define mmTPC7_CFG_QM_SRF_28 0xFC6E30 + +#define mmTPC7_CFG_QM_SRF_29 0xFC6E34 + +#define mmTPC7_CFG_QM_SRF_30 0xFC6E38 + +#define mmTPC7_CFG_QM_SRF_31 0xFC6E3C + +#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h new file mode 100644 index 000000000..5c36c972c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_QM_REGS_H_ +#define ASIC_REG_TPC7_QM_REGS_H_ + +/* + ***************************************** + * TPC7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC7_QM_GLBL_CFG0 0xFC8000 + +#define mmTPC7_QM_GLBL_CFG1 0xFC8004 + +#define mmTPC7_QM_GLBL_PROT 0xFC8008 + +#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_0 0xFC8010 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_1 0xFC8014 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_2 0xFC8018 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_3 0xFC801C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_4 0xFC8020 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 0xFC8024 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 0xFC8028 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 0xFC802C + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 0xFC8030 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 0xFC8034 + +#define mmTPC7_QM_GLBL_STS0 0xFC8038 + +#define mmTPC7_QM_GLBL_STS1_0 0xFC8040 + +#define mmTPC7_QM_GLBL_STS1_1 0xFC8044 + +#define mmTPC7_QM_GLBL_STS1_2 0xFC8048 + +#define mmTPC7_QM_GLBL_STS1_3 0xFC804C + +#define mmTPC7_QM_GLBL_STS1_4 0xFC8050 + +#define mmTPC7_QM_GLBL_MSG_EN_0 0xFC8054 + +#define mmTPC7_QM_GLBL_MSG_EN_1 0xFC8058 + +#define mmTPC7_QM_GLBL_MSG_EN_2 0xFC805C + +#define mmTPC7_QM_GLBL_MSG_EN_3 0xFC8060 + +#define mmTPC7_QM_GLBL_MSG_EN_4 0xFC8068 + +#define mmTPC7_QM_PQ_BASE_LO_0 0xFC8070 + +#define mmTPC7_QM_PQ_BASE_LO_1 0xFC8074 + +#define mmTPC7_QM_PQ_BASE_LO_2 0xFC8078 + +#define mmTPC7_QM_PQ_BASE_LO_3 0xFC807C + +#define mmTPC7_QM_PQ_BASE_HI_0 0xFC8080 + +#define mmTPC7_QM_PQ_BASE_HI_1 0xFC8084 + +#define mmTPC7_QM_PQ_BASE_HI_2 0xFC8088 + +#define mmTPC7_QM_PQ_BASE_HI_3 0xFC808C + +#define mmTPC7_QM_PQ_SIZE_0 0xFC8090 + +#define mmTPC7_QM_PQ_SIZE_1 0xFC8094 + +#define mmTPC7_QM_PQ_SIZE_2 0xFC8098 + +#define mmTPC7_QM_PQ_SIZE_3 0xFC809C + +#define mmTPC7_QM_PQ_PI_0 0xFC80A0 + +#define mmTPC7_QM_PQ_PI_1 0xFC80A4 + +#define mmTPC7_QM_PQ_PI_2 0xFC80A8 + +#define mmTPC7_QM_PQ_PI_3 0xFC80AC + +#define mmTPC7_QM_PQ_CI_0 0xFC80B0 + +#define mmTPC7_QM_PQ_CI_1 0xFC80B4 + +#define mmTPC7_QM_PQ_CI_2 0xFC80B8 + +#define mmTPC7_QM_PQ_CI_3 0xFC80BC + +#define mmTPC7_QM_PQ_CFG0_0 0xFC80C0 + +#define mmTPC7_QM_PQ_CFG0_1 0xFC80C4 + +#define mmTPC7_QM_PQ_CFG0_2 0xFC80C8 + +#define mmTPC7_QM_PQ_CFG0_3 0xFC80CC + +#define mmTPC7_QM_PQ_CFG1_0 0xFC80D0 + +#define mmTPC7_QM_PQ_CFG1_1 0xFC80D4 + +#define mmTPC7_QM_PQ_CFG1_2 0xFC80D8 + +#define mmTPC7_QM_PQ_CFG1_3 0xFC80DC + +#define mmTPC7_QM_PQ_ARUSER_31_11_0 0xFC80E0 + +#define mmTPC7_QM_PQ_ARUSER_31_11_1 0xFC80E4 + +#define mmTPC7_QM_PQ_ARUSER_31_11_2 0xFC80E8 + +#define mmTPC7_QM_PQ_ARUSER_31_11_3 0xFC80EC + +#define mmTPC7_QM_PQ_STS0_0 0xFC80F0 + +#define mmTPC7_QM_PQ_STS0_1 0xFC80F4 + +#define mmTPC7_QM_PQ_STS0_2 0xFC80F8 + +#define mmTPC7_QM_PQ_STS0_3 0xFC80FC + +#define mmTPC7_QM_PQ_STS1_0 0xFC8100 + +#define mmTPC7_QM_PQ_STS1_1 0xFC8104 + +#define mmTPC7_QM_PQ_STS1_2 0xFC8108 + +#define mmTPC7_QM_PQ_STS1_3 0xFC810C + +#define mmTPC7_QM_CQ_CFG0_0 0xFC8110 + +#define mmTPC7_QM_CQ_CFG0_1 0xFC8114 + +#define mmTPC7_QM_CQ_CFG0_2 0xFC8118 + +#define mmTPC7_QM_CQ_CFG0_3 0xFC811C + +#define mmTPC7_QM_CQ_CFG0_4 0xFC8120 + +#define mmTPC7_QM_CQ_CFG1_0 0xFC8124 + +#define mmTPC7_QM_CQ_CFG1_1 0xFC8128 + +#define mmTPC7_QM_CQ_CFG1_2 0xFC812C + +#define mmTPC7_QM_CQ_CFG1_3 0xFC8130 + +#define mmTPC7_QM_CQ_CFG1_4 0xFC8134 + +#define mmTPC7_QM_CQ_ARUSER_31_11_0 0xFC8138 + +#define mmTPC7_QM_CQ_ARUSER_31_11_1 0xFC813C + +#define mmTPC7_QM_CQ_ARUSER_31_11_2 0xFC8140 + +#define mmTPC7_QM_CQ_ARUSER_31_11_3 0xFC8144 + +#define mmTPC7_QM_CQ_ARUSER_31_11_4 0xFC8148 + +#define mmTPC7_QM_CQ_STS0_0 0xFC814C + +#define mmTPC7_QM_CQ_STS0_1 0xFC8150 + +#define mmTPC7_QM_CQ_STS0_2 0xFC8154 + +#define mmTPC7_QM_CQ_STS0_3 0xFC8158 + +#define mmTPC7_QM_CQ_STS0_4 0xFC815C + +#define mmTPC7_QM_CQ_STS1_0 0xFC8160 + +#define mmTPC7_QM_CQ_STS1_1 0xFC8164 + +#define mmTPC7_QM_CQ_STS1_2 0xFC8168 + +#define mmTPC7_QM_CQ_STS1_3 0xFC816C + +#define mmTPC7_QM_CQ_STS1_4 0xFC8170 + +#define mmTPC7_QM_CQ_PTR_LO_0 0xFC8174 + +#define mmTPC7_QM_CQ_PTR_HI_0 0xFC8178 + +#define mmTPC7_QM_CQ_TSIZE_0 0xFC817C + +#define mmTPC7_QM_CQ_CTL_0 0xFC8180 + +#define mmTPC7_QM_CQ_PTR_LO_1 0xFC8184 + +#define mmTPC7_QM_CQ_PTR_HI_1 0xFC8188 + +#define mmTPC7_QM_CQ_TSIZE_1 0xFC818C + +#define mmTPC7_QM_CQ_CTL_1 0xFC8190 + +#define mmTPC7_QM_CQ_PTR_LO_2 0xFC8194 + +#define mmTPC7_QM_CQ_PTR_HI_2 0xFC8198 + +#define mmTPC7_QM_CQ_TSIZE_2 0xFC819C + +#define mmTPC7_QM_CQ_CTL_2 0xFC81A0 + +#define mmTPC7_QM_CQ_PTR_LO_3 0xFC81A4 + +#define mmTPC7_QM_CQ_PTR_HI_3 0xFC81A8 + +#define mmTPC7_QM_CQ_TSIZE_3 0xFC81AC + +#define mmTPC7_QM_CQ_CTL_3 0xFC81B0 + +#define mmTPC7_QM_CQ_PTR_LO_4 0xFC81B4 + +#define mmTPC7_QM_CQ_PTR_HI_4 0xFC81B8 + +#define mmTPC7_QM_CQ_TSIZE_4 0xFC81BC + +#define mmTPC7_QM_CQ_CTL_4 0xFC81C0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_0 0xFC81C4 + +#define mmTPC7_QM_CQ_PTR_LO_STS_1 0xFC81C8 + +#define mmTPC7_QM_CQ_PTR_LO_STS_2 0xFC81CC + +#define mmTPC7_QM_CQ_PTR_LO_STS_3 0xFC81D0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_4 0xFC81D4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_0 0xFC81D8 + +#define mmTPC7_QM_CQ_PTR_HI_STS_1 0xFC81DC + +#define mmTPC7_QM_CQ_PTR_HI_STS_2 0xFC81E0 + +#define mmTPC7_QM_CQ_PTR_HI_STS_3 0xFC81E4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_4 0xFC81E8 + +#define mmTPC7_QM_CQ_TSIZE_STS_0 0xFC81EC + +#define mmTPC7_QM_CQ_TSIZE_STS_1 0xFC81F0 + +#define mmTPC7_QM_CQ_TSIZE_STS_2 0xFC81F4 + +#define mmTPC7_QM_CQ_TSIZE_STS_3 0xFC81F8 + +#define mmTPC7_QM_CQ_TSIZE_STS_4 0xFC81FC + +#define mmTPC7_QM_CQ_CTL_STS_0 0xFC8200 + +#define mmTPC7_QM_CQ_CTL_STS_1 0xFC8204 + +#define mmTPC7_QM_CQ_CTL_STS_2 0xFC8208 + +#define mmTPC7_QM_CQ_CTL_STS_3 0xFC820C + +#define mmTPC7_QM_CQ_CTL_STS_4 0xFC8210 + +#define mmTPC7_QM_CQ_IFIFO_CNT_0 0xFC8214 + +#define mmTPC7_QM_CQ_IFIFO_CNT_1 0xFC8218 + +#define mmTPC7_QM_CQ_IFIFO_CNT_2 0xFC821C + +#define mmTPC7_QM_CQ_IFIFO_CNT_3 0xFC8220 + +#define mmTPC7_QM_CQ_IFIFO_CNT_4 0xFC8224 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 0xFC8228 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 0xFC822C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 0xFC8230 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 0xFC8234 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 0xFC8238 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 0xFC823C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 0xFC8240 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 0xFC8244 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 0xFC8248 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 0xFC824C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 0xFC8250 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 0xFC8254 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 0xFC8258 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 0xFC825C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 0xFC8260 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 0xFC8264 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 0xFC8268 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 0xFC826C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 0xFC8270 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 0xFC8274 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 0xFC8278 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 0xFC827C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 0xFC8280 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 0xFC8284 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 0xFC8288 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 0xFC828C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 0xFC8290 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 0xFC8294 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 0xFC8298 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 0xFC829C + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 0xFC82A0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 0xFC82A4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 0xFC82A8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 0xFC82AC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 0xFC82B0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 0xFC82B4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 0xFC82B8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 0xFC82BC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 0xFC82C0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 0xFC82C4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 0xFC82C8 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 0xFC82CC + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 0xFC82D0 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 0xFC82D4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 0xFC82D8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xFC82E0 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xFC82E4 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xFC82E8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xFC82EC + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xFC82F0 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xFC82F4 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xFC82F8 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xFC82FC + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xFC8300 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xFC8304 + +#define mmTPC7_QM_CP_FENCE0_RDATA_0 0xFC8308 + +#define mmTPC7_QM_CP_FENCE0_RDATA_1 0xFC830C + +#define mmTPC7_QM_CP_FENCE0_RDATA_2 0xFC8310 + +#define mmTPC7_QM_CP_FENCE0_RDATA_3 0xFC8314 + +#define mmTPC7_QM_CP_FENCE0_RDATA_4 0xFC8318 + +#define mmTPC7_QM_CP_FENCE1_RDATA_0 0xFC831C + +#define mmTPC7_QM_CP_FENCE1_RDATA_1 0xFC8320 + +#define mmTPC7_QM_CP_FENCE1_RDATA_2 0xFC8324 + +#define mmTPC7_QM_CP_FENCE1_RDATA_3 0xFC8328 + +#define mmTPC7_QM_CP_FENCE1_RDATA_4 0xFC832C + +#define mmTPC7_QM_CP_FENCE2_RDATA_0 0xFC8330 + +#define mmTPC7_QM_CP_FENCE2_RDATA_1 0xFC8334 + +#define mmTPC7_QM_CP_FENCE2_RDATA_2 0xFC8338 + +#define mmTPC7_QM_CP_FENCE2_RDATA_3 0xFC833C + +#define mmTPC7_QM_CP_FENCE2_RDATA_4 0xFC8340 + +#define mmTPC7_QM_CP_FENCE3_RDATA_0 0xFC8344 + +#define mmTPC7_QM_CP_FENCE3_RDATA_1 0xFC8348 + +#define mmTPC7_QM_CP_FENCE3_RDATA_2 0xFC834C + +#define mmTPC7_QM_CP_FENCE3_RDATA_3 0xFC8350 + +#define mmTPC7_QM_CP_FENCE3_RDATA_4 0xFC8354 + +#define mmTPC7_QM_CP_FENCE0_CNT_0 0xFC8358 + +#define mmTPC7_QM_CP_FENCE0_CNT_1 0xFC835C + +#define mmTPC7_QM_CP_FENCE0_CNT_2 0xFC8360 + +#define mmTPC7_QM_CP_FENCE0_CNT_3 0xFC8364 + +#define mmTPC7_QM_CP_FENCE0_CNT_4 0xFC8368 + +#define mmTPC7_QM_CP_FENCE1_CNT_0 0xFC836C + +#define mmTPC7_QM_CP_FENCE1_CNT_1 0xFC8370 + +#define mmTPC7_QM_CP_FENCE1_CNT_2 0xFC8374 + +#define mmTPC7_QM_CP_FENCE1_CNT_3 0xFC8378 + +#define mmTPC7_QM_CP_FENCE1_CNT_4 0xFC837C + +#define mmTPC7_QM_CP_FENCE2_CNT_0 0xFC8380 + +#define mmTPC7_QM_CP_FENCE2_CNT_1 0xFC8384 + +#define mmTPC7_QM_CP_FENCE2_CNT_2 0xFC8388 + +#define mmTPC7_QM_CP_FENCE2_CNT_3 0xFC838C + +#define mmTPC7_QM_CP_FENCE2_CNT_4 0xFC8390 + +#define mmTPC7_QM_CP_FENCE3_CNT_0 0xFC8394 + +#define mmTPC7_QM_CP_FENCE3_CNT_1 0xFC8398 + +#define mmTPC7_QM_CP_FENCE3_CNT_2 0xFC839C + +#define mmTPC7_QM_CP_FENCE3_CNT_3 0xFC83A0 + +#define mmTPC7_QM_CP_FENCE3_CNT_4 0xFC83A4 + +#define mmTPC7_QM_CP_STS_0 0xFC83A8 + +#define mmTPC7_QM_CP_STS_1 0xFC83AC + +#define mmTPC7_QM_CP_STS_2 0xFC83B0 + +#define mmTPC7_QM_CP_STS_3 0xFC83B4 + +#define mmTPC7_QM_CP_STS_4 0xFC83B8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_0 0xFC83BC + +#define mmTPC7_QM_CP_CURRENT_INST_LO_1 0xFC83C0 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_2 0xFC83C4 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_3 0xFC83C8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_4 0xFC83CC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_0 0xFC83D0 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_1 0xFC83D4 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_2 0xFC83D8 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_3 0xFC83DC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_4 0xFC83E0 + +#define mmTPC7_QM_CP_BARRIER_CFG_0 0xFC83F4 + +#define mmTPC7_QM_CP_BARRIER_CFG_1 0xFC83F8 + +#define mmTPC7_QM_CP_BARRIER_CFG_2 0xFC83FC + +#define mmTPC7_QM_CP_BARRIER_CFG_3 0xFC8400 + +#define mmTPC7_QM_CP_BARRIER_CFG_4 0xFC8404 + +#define mmTPC7_QM_CP_DBG_0_0 0xFC8408 + +#define mmTPC7_QM_CP_DBG_0_1 0xFC840C + +#define mmTPC7_QM_CP_DBG_0_2 0xFC8410 + +#define mmTPC7_QM_CP_DBG_0_3 0xFC8414 + +#define mmTPC7_QM_CP_DBG_0_4 0xFC8418 + +#define mmTPC7_QM_CP_ARUSER_31_11_0 0xFC841C + +#define mmTPC7_QM_CP_ARUSER_31_11_1 0xFC8420 + +#define mmTPC7_QM_CP_ARUSER_31_11_2 0xFC8424 + +#define mmTPC7_QM_CP_ARUSER_31_11_3 0xFC8428 + +#define mmTPC7_QM_CP_ARUSER_31_11_4 0xFC842C + +#define mmTPC7_QM_CP_AWUSER_31_11_0 0xFC8430 + +#define mmTPC7_QM_CP_AWUSER_31_11_1 0xFC8434 + +#define mmTPC7_QM_CP_AWUSER_31_11_2 0xFC8438 + +#define mmTPC7_QM_CP_AWUSER_31_11_3 0xFC843C + +#define mmTPC7_QM_CP_AWUSER_31_11_4 0xFC8440 + +#define mmTPC7_QM_ARB_CFG_0 0xFC8A00 + +#define mmTPC7_QM_ARB_CHOISE_Q_PUSH 0xFC8A04 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_0 0xFC8A08 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_1 0xFC8A0C + +#define mmTPC7_QM_ARB_WRR_WEIGHT_2 0xFC8A10 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_3 0xFC8A14 + +#define mmTPC7_QM_ARB_CFG_1 0xFC8A18 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0 0xFC8A20 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1 0xFC8A24 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2 0xFC8A28 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3 0xFC8A2C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4 0xFC8A30 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5 0xFC8A34 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6 0xFC8A38 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7 0xFC8A3C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8 0xFC8A40 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9 0xFC8A44 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10 0xFC8A48 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11 0xFC8A4C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12 0xFC8A50 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13 0xFC8A54 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14 0xFC8A58 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15 0xFC8A5C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16 0xFC8A60 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17 0xFC8A64 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18 0xFC8A68 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19 0xFC8A6C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20 0xFC8A70 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21 0xFC8A74 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22 0xFC8A78 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23 0xFC8A7C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24 0xFC8A80 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25 0xFC8A84 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26 0xFC8A88 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27 0xFC8A8C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28 0xFC8A90 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29 0xFC8A94 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30 0xFC8A98 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31 0xFC8A9C + +#define mmTPC7_QM_ARB_MST_CRED_INC 0xFC8AA0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xFC8AA4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xFC8AA8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xFC8AAC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xFC8AB0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xFC8AB4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xFC8AB8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xFC8ABC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xFC8AC0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xFC8AC4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xFC8AC8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xFC8ACC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xFC8AD0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xFC8AD4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xFC8AD8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xFC8ADC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xFC8AE0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xFC8AE4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xFC8AE8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xFC8AEC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xFC8AF0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xFC8AF4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xFC8AF8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xFC8AFC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xFC8B00 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xFC8B04 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xFC8B08 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xFC8B0C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xFC8B10 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xFC8B14 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xFC8B18 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xFC8B1C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xFC8B20 + +#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xFC8B28 + +#define mmTPC7_QM_ARB_MST_SLAVE_EN 0xFC8B2C + +#define mmTPC7_QM_ARB_MST_QUIET_PER 0xFC8B34 + +#define mmTPC7_QM_ARB_SLV_CHOISE_WDT 0xFC8B38 + +#define mmTPC7_QM_ARB_SLV_ID 0xFC8B3C + +#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT 0xFC8B44 + +#define mmTPC7_QM_ARB_MSG_AWUSER_31_11 0xFC8B48 + +#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP 0xFC8B4C + +#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xFC8B50 + +#define mmTPC7_QM_ARB_BASE_LO 0xFC8B54 + +#define mmTPC7_QM_ARB_BASE_HI 0xFC8B58 + +#define mmTPC7_QM_ARB_STATE_STS 0xFC8B80 + +#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS 0xFC8B84 + +#define mmTPC7_QM_ARB_MSG_STS 0xFC8B88 + +#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD 0xFC8B8C + +#define mmTPC7_QM_ARB_ERR_CAUSE 0xFC8B9C + +#define mmTPC7_QM_ARB_ERR_MSG_EN 0xFC8BA0 + +#define mmTPC7_QM_ARB_ERR_STS_DRP 0xFC8BA8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_0 0xFC8BB0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_1 0xFC8BB4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_2 0xFC8BB8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_3 0xFC8BBC + +#define mmTPC7_QM_ARB_MST_CRED_STS_4 0xFC8BC0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_5 0xFC8BC4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_6 0xFC8BC8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_7 0xFC8BCC + +#define mmTPC7_QM_ARB_MST_CRED_STS_8 0xFC8BD0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_9 0xFC8BD4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_10 0xFC8BD8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_11 0xFC8BDC + +#define mmTPC7_QM_ARB_MST_CRED_STS_12 0xFC8BE0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_13 0xFC8BE4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_14 0xFC8BE8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_15 0xFC8BEC + +#define mmTPC7_QM_ARB_MST_CRED_STS_16 0xFC8BF0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_17 0xFC8BF4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_18 0xFC8BF8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_19 0xFC8BFC + +#define mmTPC7_QM_ARB_MST_CRED_STS_20 0xFC8C00 + +#define mmTPC7_QM_ARB_MST_CRED_STS_21 0xFC8C04 + +#define mmTPC7_QM_ARB_MST_CRED_STS_22 0xFC8C08 + +#define mmTPC7_QM_ARB_MST_CRED_STS_23 0xFC8C0C + +#define mmTPC7_QM_ARB_MST_CRED_STS_24 0xFC8C10 + +#define mmTPC7_QM_ARB_MST_CRED_STS_25 0xFC8C14 + +#define mmTPC7_QM_ARB_MST_CRED_STS_26 0xFC8C18 + +#define mmTPC7_QM_ARB_MST_CRED_STS_27 0xFC8C1C + +#define mmTPC7_QM_ARB_MST_CRED_STS_28 0xFC8C20 + +#define mmTPC7_QM_ARB_MST_CRED_STS_29 0xFC8C24 + +#define mmTPC7_QM_ARB_MST_CRED_STS_30 0xFC8C28 + +#define mmTPC7_QM_ARB_MST_CRED_STS_31 0xFC8C2C + +#define mmTPC7_QM_CGM_CFG 0xFC8C70 + +#define mmTPC7_QM_CGM_STS 0xFC8C74 + +#define mmTPC7_QM_CGM_CFG1 0xFC8C78 + +#define mmTPC7_QM_LOCAL_RANGE_BASE 0xFC8C80 + +#define mmTPC7_QM_LOCAL_RANGE_SIZE 0xFC8C84 + +#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG 0xFC8C90 + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 0xFC8C94 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 0xFC8C98 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 0xFC8C9C + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 0xFC8CA0 + +#define mmTPC7_QM_GLBL_AXCACHE 0xFC8CA4 + +#define mmTPC7_QM_IND_GW_APB_CFG 0xFC8CB0 + +#define mmTPC7_QM_IND_GW_APB_WDATA 0xFC8CB4 + +#define mmTPC7_QM_IND_GW_APB_RDATA 0xFC8CB8 + +#define mmTPC7_QM_IND_GW_APB_STATUS 0xFC8CBC + +#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8CD0 + +#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8CD4 + +#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8CD8 + +#define mmTPC7_QM_GLBL_MEM_INIT_BUSY 0xFC8D00 + +#endif /* ASIC_REG_TPC7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi.h b/drivers/misc/habanalabs/include/gaudi/gaudi.h new file mode 100644 index 000000000..ffae107b1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_H +#define GAUDI_H + +#define SRAM_BAR_ID 0 +#define CFG_BAR_ID 2 +#define HBM_BAR_ID 4 + +#define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ +#define CFG_BAR_SIZE 0x8000000ull /* 128MB */ + +#define CFG_BASE 0x7FFC000000ull +#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ + +#define SRAM_BASE_ADDR 0x7FF0000000ull +#define SRAM_SIZE 0x1400000 /* 20MB */ + +#define SPI_FLASH_BASE_ADDR 0x7FF8000000ull + +#define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull +#define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ + +#define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull +#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ + +#define DRAM_PHYS_BASE 0x0ull + +#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ +#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ + +#define GAUDI_MSI_ENTRIES 32 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 2 + +#define PROT_BITS_OFFS 0xF80 + +#define MME_NUMBER_OF_MASTER_ENGINES 2 + +#define MME_NUMBER_OF_SLAVE_ENGINES 2 + +#define TPC_NUMBER_OF_ENGINES 8 + +#define DMA_NUMBER_OF_CHANNELS 8 + +#define NIC_NUMBER_OF_MACROS 5 + +#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) + +#define NUMBER_OF_IF 8 + +#define DEVICE_CACHE_LINE_SIZE 128 + +#endif /* GAUDI_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h new file mode 100644 index 000000000..c07ed4ed3 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_EVENTS_H_ +#define __GAUDI_ASYNC_EVENTS_H_ + +enum gaudi_async_event_id { + GAUDI_EVENT_PCIE_CORE_SERR = 32, + GAUDI_EVENT_PCIE_CORE_DERR = 33, + GAUDI_EVENT_PCIE_IF_SERR = 34, + GAUDI_EVENT_PCIE_IF_DERR = 35, + GAUDI_EVENT_PCIE_PHY_SERR = 36, + GAUDI_EVENT_PCIE_PHY_DERR = 37, + GAUDI_EVENT_TPC0_SERR = 38, + GAUDI_EVENT_TPC1_SERR = 39, + GAUDI_EVENT_TPC2_SERR = 40, + GAUDI_EVENT_TPC3_SERR = 41, + GAUDI_EVENT_TPC4_SERR = 42, + GAUDI_EVENT_TPC5_SERR = 43, + GAUDI_EVENT_TPC6_SERR = 44, + GAUDI_EVENT_TPC7_SERR = 45, + GAUDI_EVENT_TPC0_DERR = 46, + GAUDI_EVENT_TPC1_DERR = 47, + GAUDI_EVENT_TPC2_DERR = 48, + GAUDI_EVENT_TPC3_DERR = 49, + GAUDI_EVENT_TPC4_DERR = 50, + GAUDI_EVENT_TPC5_DERR = 51, + GAUDI_EVENT_TPC6_DERR = 52, + GAUDI_EVENT_TPC7_DERR = 53, + GAUDI_EVENT_MME0_ACC_SERR = 54, + GAUDI_EVENT_MME0_ACC_DERR = 55, + GAUDI_EVENT_MME0_SBAB_SERR = 56, + GAUDI_EVENT_MME0_SBAB_DERR = 57, + GAUDI_EVENT_MME1_ACC_SERR = 58, + GAUDI_EVENT_MME1_ACC_DERR = 59, + GAUDI_EVENT_MME1_SBAB_SERR = 60, + GAUDI_EVENT_MME1_SBAB_DERR = 61, + GAUDI_EVENT_MME2_ACC_SERR = 62, + GAUDI_EVENT_MME2_ACC_DERR = 63, + GAUDI_EVENT_MME2_SBAB_SERR = 64, + GAUDI_EVENT_MME2_SBAB_DERR = 65, + GAUDI_EVENT_MME3_ACC_SERR = 66, + GAUDI_EVENT_MME3_ACC_DERR = 67, + GAUDI_EVENT_MME3_SBAB_SERR = 68, + GAUDI_EVENT_MME3_SBAB_DERR = 69, + GAUDI_EVENT_DMA0_SERR_ECC = 70, + GAUDI_EVENT_DMA1_SERR_ECC = 71, + GAUDI_EVENT_DMA2_SERR_ECC = 72, + GAUDI_EVENT_DMA3_SERR_ECC = 73, + GAUDI_EVENT_DMA4_SERR_ECC = 74, + GAUDI_EVENT_DMA5_SERR_ECC = 75, + GAUDI_EVENT_DMA6_SERR_ECC = 76, + GAUDI_EVENT_DMA7_SERR_ECC = 77, + GAUDI_EVENT_DMA0_DERR_ECC = 78, + GAUDI_EVENT_DMA1_DERR_ECC = 79, + GAUDI_EVENT_DMA2_DERR_ECC = 80, + GAUDI_EVENT_DMA3_DERR_ECC = 81, + GAUDI_EVENT_DMA4_DERR_ECC = 82, + GAUDI_EVENT_DMA5_DERR_ECC = 83, + GAUDI_EVENT_DMA6_DERR_ECC = 84, + GAUDI_EVENT_DMA7_DERR_ECC = 85, + GAUDI_EVENT_CPU_IF_ECC_SERR = 86, + GAUDI_EVENT_CPU_IF_ECC_DERR = 87, + GAUDI_EVENT_PSOC_MEM_SERR = 88, + GAUDI_EVENT_PSOC_CORESIGHT_SERR = 89, + GAUDI_EVENT_PSOC_MEM_DERR = 90, + GAUDI_EVENT_PSOC_CORESIGHT_DERR = 91, + GAUDI_EVENT_SRAM0_SERR = 92, + GAUDI_EVENT_SRAM1_SERR = 93, + GAUDI_EVENT_SRAM2_SERR = 94, + GAUDI_EVENT_SRAM3_SERR = 95, + GAUDI_EVENT_SRAM7_SERR = 96, + GAUDI_EVENT_SRAM6_SERR = 97, + GAUDI_EVENT_SRAM5_SERR = 98, + GAUDI_EVENT_SRAM4_SERR = 99, + GAUDI_EVENT_SRAM8_SERR = 100, + GAUDI_EVENT_SRAM9_SERR = 101, + GAUDI_EVENT_SRAM10_SERR = 102, + GAUDI_EVENT_SRAM11_SERR = 103, + GAUDI_EVENT_SRAM15_SERR = 104, + GAUDI_EVENT_SRAM14_SERR = 105, + GAUDI_EVENT_SRAM13_SERR = 106, + GAUDI_EVENT_SRAM12_SERR = 107, + GAUDI_EVENT_SRAM16_SERR = 108, + GAUDI_EVENT_SRAM17_SERR = 109, + GAUDI_EVENT_SRAM18_SERR = 110, + GAUDI_EVENT_SRAM19_SERR = 111, + GAUDI_EVENT_SRAM23_SERR = 112, + GAUDI_EVENT_SRAM22_SERR = 113, + GAUDI_EVENT_SRAM21_SERR = 114, + GAUDI_EVENT_SRAM20_SERR = 115, + GAUDI_EVENT_SRAM24_SERR = 116, + GAUDI_EVENT_SRAM25_SERR = 117, + GAUDI_EVENT_SRAM26_SERR = 118, + GAUDI_EVENT_SRAM27_SERR = 119, + GAUDI_EVENT_SRAM31_SERR = 120, + GAUDI_EVENT_SRAM30_SERR = 121, + GAUDI_EVENT_SRAM29_SERR = 122, + GAUDI_EVENT_SRAM28_SERR = 123, + GAUDI_EVENT_SRAM0_DERR = 124, + GAUDI_EVENT_SRAM1_DERR = 125, + GAUDI_EVENT_SRAM2_DERR = 126, + GAUDI_EVENT_SRAM3_DERR = 127, + GAUDI_EVENT_SRAM7_DERR = 128, + GAUDI_EVENT_SRAM6_DERR = 129, + GAUDI_EVENT_SRAM5_DERR = 130, + GAUDI_EVENT_SRAM4_DERR = 131, + GAUDI_EVENT_SRAM8_DERR = 132, + GAUDI_EVENT_SRAM9_DERR = 133, + GAUDI_EVENT_SRAM10_DERR = 134, + GAUDI_EVENT_SRAM11_DERR = 135, + GAUDI_EVENT_SRAM15_DERR = 136, + GAUDI_EVENT_SRAM14_DERR = 137, + GAUDI_EVENT_SRAM13_DERR = 138, + GAUDI_EVENT_SRAM12_DERR = 139, + GAUDI_EVENT_SRAM16_DERR = 140, + GAUDI_EVENT_SRAM17_DERR = 141, + GAUDI_EVENT_SRAM18_DERR = 142, + GAUDI_EVENT_SRAM19_DERR = 143, + GAUDI_EVENT_SRAM23_DERR = 144, + GAUDI_EVENT_SRAM22_DERR = 145, + GAUDI_EVENT_SRAM21_DERR = 146, + GAUDI_EVENT_SRAM20_DERR = 147, + GAUDI_EVENT_SRAM24_DERR = 148, + GAUDI_EVENT_SRAM25_DERR = 149, + GAUDI_EVENT_SRAM26_DERR = 150, + GAUDI_EVENT_SRAM27_DERR = 151, + GAUDI_EVENT_SRAM31_DERR = 152, + GAUDI_EVENT_SRAM30_DERR = 153, + GAUDI_EVENT_SRAM29_DERR = 154, + GAUDI_EVENT_SRAM28_DERR = 155, + GAUDI_EVENT_NIC0_SERR = 156, + GAUDI_EVENT_NIC1_SERR = 157, + GAUDI_EVENT_NIC2_SERR = 158, + GAUDI_EVENT_NIC3_SERR = 159, + GAUDI_EVENT_NIC4_SERR = 160, + GAUDI_EVENT_NIC0_DERR = 166, + GAUDI_EVENT_NIC1_DERR = 167, + GAUDI_EVENT_NIC2_DERR = 168, + GAUDI_EVENT_NIC3_DERR = 169, + GAUDI_EVENT_NIC4_DERR = 170, + GAUDI_EVENT_DMA_IF0_SERR = 176, + GAUDI_EVENT_DMA_IF1_SERR = 177, + GAUDI_EVENT_DMA_IF2_SERR = 178, + GAUDI_EVENT_DMA_IF3_SERR = 179, + GAUDI_EVENT_DMA_IF0_DERR = 180, + GAUDI_EVENT_DMA_IF1_DERR = 181, + GAUDI_EVENT_DMA_IF2_DERR = 182, + GAUDI_EVENT_DMA_IF3_DERR = 183, + GAUDI_EVENT_GIC500 = 184, + GAUDI_EVENT_HBM_0_SERR = 185, + GAUDI_EVENT_HBM_1_SERR = 186, + GAUDI_EVENT_HBM_2_SERR = 187, + GAUDI_EVENT_HBM_3_SERR = 188, + GAUDI_EVENT_HBM_0_DERR = 189, + GAUDI_EVENT_HBM_1_DERR = 190, + GAUDI_EVENT_HBM_2_DERR = 191, + GAUDI_EVENT_HBM_3_DERR = 192, + GAUDI_EVENT_MMU_SERR = 193, + GAUDI_EVENT_MMU_DERR = 194, + GAUDI_EVENT_PCIE_DEC = 200, + GAUDI_EVENT_TPC0_DEC = 201, + GAUDI_EVENT_TPC1_DEC = 203, + GAUDI_EVENT_TPC2_DEC = 205, + GAUDI_EVENT_TPC3_DEC = 207, + GAUDI_EVENT_TPC4_DEC = 209, + GAUDI_EVENT_TPC5_DEC = 211, + GAUDI_EVENT_TPC6_DEC = 213, + GAUDI_EVENT_TPC7_DEC = 215, + GAUDI_EVENT_AXI_ECC = 217, + GAUDI_EVENT_L2_RAM_ECC = 218, + GAUDI_EVENT_MME0_WBC_RSP = 219, + GAUDI_EVENT_MME0_SBAB0_RSP = 220, + GAUDI_EVENT_MME1_WBC_RSP = 224, + GAUDI_EVENT_MME1_SBAB0_RSP = 225, + GAUDI_EVENT_MME2_WBC_RSP = 229, + GAUDI_EVENT_MME2_SBAB0_RSP = 230, + GAUDI_EVENT_MME3_WBC_RSP = 234, + GAUDI_EVENT_MME3_SBAB0_RSP = 235, + GAUDI_EVENT_PLL0 = 239, + GAUDI_EVENT_PLL1 = 240, + GAUDI_EVENT_PLL2 = 241, + GAUDI_EVENT_PLL3 = 242, + GAUDI_EVENT_PLL4 = 243, + GAUDI_EVENT_PLL5 = 244, + GAUDI_EVENT_PLL6 = 245, + GAUDI_EVENT_PLL7 = 246, + GAUDI_EVENT_PLL8 = 247, + GAUDI_EVENT_PLL9 = 248, + GAUDI_EVENT_PLL10 = 249, + GAUDI_EVENT_PLL11 = 250, + GAUDI_EVENT_PLL12 = 251, + GAUDI_EVENT_PLL13 = 252, + GAUDI_EVENT_PLL14 = 253, + GAUDI_EVENT_PLL15 = 254, + GAUDI_EVENT_PLL16 = 255, + GAUDI_EVENT_PLL17 = 256, + GAUDI_EVENT_CPU_AXI_SPLITTER = 257, + GAUDI_EVENT_PSOC_AXI_DEC = 262, + GAUDI_EVENT_PSOC_PRSTN_FALL = 263, + GAUDI_EVENT_NIC_SEI_0 = 264, + GAUDI_EVENT_NIC_SEI_1 = 265, + GAUDI_EVENT_NIC_SEI_2 = 266, + GAUDI_EVENT_NIC_SEI_3 = 267, + GAUDI_EVENT_NIC_SEI_4 = 268, + GAUDI_EVENT_DMA_IF_SEI_0 = 277, + GAUDI_EVENT_DMA_IF_SEI_1 = 278, + GAUDI_EVENT_DMA_IF_SEI_2 = 279, + GAUDI_EVENT_DMA_IF_SEI_3 = 280, + GAUDI_EVENT_PCIE_FLR = 290, + GAUDI_EVENT_TPC0_BMON_SPMU = 300, + GAUDI_EVENT_TPC0_KRN_ERR = 301, + GAUDI_EVENT_TPC1_BMON_SPMU = 306, + GAUDI_EVENT_TPC1_KRN_ERR = 307, + GAUDI_EVENT_TPC2_BMON_SPMU = 312, + GAUDI_EVENT_TPC2_KRN_ERR = 313, + GAUDI_EVENT_TPC3_BMON_SPMU = 318, + GAUDI_EVENT_TPC3_KRN_ERR = 319, + GAUDI_EVENT_TPC4_BMON_SPMU = 324, + GAUDI_EVENT_TPC4_KRN_ERR = 325, + GAUDI_EVENT_TPC5_BMON_SPMU = 330, + GAUDI_EVENT_TPC5_KRN_ERR = 331, + GAUDI_EVENT_TPC6_BMON_SPMU = 336, + GAUDI_EVENT_TPC6_KRN_ERR = 337, + GAUDI_EVENT_TPC7_BMON_SPMU = 342, + GAUDI_EVENT_TPC7_KRN_ERR = 343, + GAUDI_EVENT_MMU_PAGE_FAULT = 380, + GAUDI_EVENT_MMU_WR_PERM = 381, + GAUDI_EVENT_DMA_BM_CH0 = 383, + GAUDI_EVENT_DMA_BM_CH1 = 384, + GAUDI_EVENT_DMA_BM_CH2 = 385, + GAUDI_EVENT_DMA_BM_CH3 = 386, + GAUDI_EVENT_DMA_BM_CH4 = 387, + GAUDI_EVENT_DMA_BM_CH5 = 388, + GAUDI_EVENT_DMA_BM_CH6 = 389, + GAUDI_EVENT_DMA_BM_CH7 = 390, + GAUDI_EVENT_HBM0_SPI_0 = 395, + GAUDI_EVENT_HBM0_SPI_1 = 396, + GAUDI_EVENT_HBM1_SPI_0 = 399, + GAUDI_EVENT_HBM1_SPI_1 = 400, + GAUDI_EVENT_HBM2_SPI_0 = 403, + GAUDI_EVENT_HBM2_SPI_1 = 404, + GAUDI_EVENT_HBM3_SPI_0 = 407, + GAUDI_EVENT_HBM3_SPI_1 = 408, + GAUDI_EVENT_PSOC_GPIO_U16_0 = 421, + GAUDI_EVENT_NIC0_CS_DBG_DERR = 483, + GAUDI_EVENT_NIC1_CS_DBG_DERR = 487, + GAUDI_EVENT_NIC2_CS_DBG_DERR = 491, + GAUDI_EVENT_NIC3_CS_DBG_DERR = 495, + GAUDI_EVENT_NIC4_CS_DBG_DERR = 499, + GAUDI_EVENT_RAZWI_OR_ADC = 548, + GAUDI_EVENT_TPC0_QM = 572, + GAUDI_EVENT_TPC1_QM = 573, + GAUDI_EVENT_TPC2_QM = 574, + GAUDI_EVENT_TPC3_QM = 575, + GAUDI_EVENT_TPC4_QM = 576, + GAUDI_EVENT_TPC5_QM = 577, + GAUDI_EVENT_TPC6_QM = 578, + GAUDI_EVENT_TPC7_QM = 579, + GAUDI_EVENT_MME0_QM = 581, + GAUDI_EVENT_MME2_QM = 582, + GAUDI_EVENT_DMA0_QM = 583, + GAUDI_EVENT_DMA1_QM = 584, + GAUDI_EVENT_DMA2_QM = 585, + GAUDI_EVENT_DMA3_QM = 586, + GAUDI_EVENT_DMA4_QM = 587, + GAUDI_EVENT_DMA5_QM = 588, + GAUDI_EVENT_DMA6_QM = 589, + GAUDI_EVENT_DMA7_QM = 590, + GAUDI_EVENT_NIC0_QM0 = 594, + GAUDI_EVENT_NIC0_QM1 = 595, + GAUDI_EVENT_NIC1_QM0 = 596, + GAUDI_EVENT_NIC1_QM1 = 597, + GAUDI_EVENT_NIC2_QM0 = 598, + GAUDI_EVENT_NIC2_QM1 = 599, + GAUDI_EVENT_NIC3_QM0 = 600, + GAUDI_EVENT_NIC3_QM1 = 601, + GAUDI_EVENT_NIC4_QM0 = 602, + GAUDI_EVENT_NIC4_QM1 = 603, + GAUDI_EVENT_DMA0_CORE = 604, + GAUDI_EVENT_DMA1_CORE = 605, + GAUDI_EVENT_DMA2_CORE = 606, + GAUDI_EVENT_DMA3_CORE = 607, + GAUDI_EVENT_DMA4_CORE = 608, + GAUDI_EVENT_DMA5_CORE = 609, + GAUDI_EVENT_DMA6_CORE = 610, + GAUDI_EVENT_DMA7_CORE = 611, + GAUDI_EVENT_NIC0_QP0 = 612, + GAUDI_EVENT_NIC0_QP1 = 613, + GAUDI_EVENT_NIC1_QP0 = 614, + GAUDI_EVENT_NIC1_QP1 = 615, + GAUDI_EVENT_NIC2_QP0 = 616, + GAUDI_EVENT_NIC2_QP1 = 617, + GAUDI_EVENT_NIC3_QP0 = 618, + GAUDI_EVENT_NIC3_QP1 = 619, + GAUDI_EVENT_NIC4_QP0 = 620, + GAUDI_EVENT_NIC4_QP1 = 621, + GAUDI_EVENT_PI_UPDATE = 635, + GAUDI_EVENT_HALT_MACHINE = 636, + GAUDI_EVENT_INTS_REGISTER = 637, + GAUDI_EVENT_SOFT_RESET = 638, + GAUDI_EVENT_FW_ALIVE_S = 645, + GAUDI_EVENT_DEV_RESET_REQ = 646, + GAUDI_EVENT_PKT_QUEUE_OUT_SYNC = 647, + GAUDI_EVENT_STATUS_NIC0_ENG0 = 648, + GAUDI_EVENT_STATUS_NIC0_ENG1 = 649, + GAUDI_EVENT_STATUS_NIC1_ENG0 = 650, + GAUDI_EVENT_STATUS_NIC1_ENG1 = 651, + GAUDI_EVENT_STATUS_NIC2_ENG0 = 652, + GAUDI_EVENT_STATUS_NIC2_ENG1 = 653, + GAUDI_EVENT_STATUS_NIC3_ENG0 = 654, + GAUDI_EVENT_STATUS_NIC3_ENG1 = 655, + GAUDI_EVENT_STATUS_NIC4_ENG0 = 656, + GAUDI_EVENT_STATUS_NIC4_ENG1 = 657, + GAUDI_EVENT_FIX_POWER_ENV_S = 658, + GAUDI_EVENT_FIX_POWER_ENV_E = 659, + GAUDI_EVENT_FIX_THERMAL_ENV_S = 660, + GAUDI_EVENT_FIX_THERMAL_ENV_E = 661, + GAUDI_EVENT_RAZWI_OR_ADC_SW = 662, + GAUDI_EVENT_SIZE, +}; + +#endif /* __GAUDI_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h new file mode 100644 index 000000000..479b6b038 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h @@ -0,0 +1,710 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ +#define __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ + +struct gaudi_async_events_ids_map { + int fc_id; + int cpu_id; + int valid; + char name[64]; +}; + +static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = { + { .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" }, + { .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" }, + { .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" }, + { .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" }, + { .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" }, + { .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" }, + { .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" }, + { .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" }, + { .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" }, + { .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" }, + { .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" }, + { .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" }, + { .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" }, + { .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" }, + { .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" }, + { .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" }, + { .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" }, + { .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" }, + { .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" }, + { .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" }, + { .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" }, + { .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" }, + { .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" }, + { .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" }, + { .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" }, + { .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" }, + { .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" }, + { .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" }, + { .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" }, + { .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" }, + { .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" }, + { .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" }, + { .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" }, + { .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" }, + { .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" }, + { .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" }, + { .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" }, + { .fc_id = 82, .cpu_id = 57, .valid = 1, .name = "DMA4_DERR_ECC" }, + { .fc_id = 83, .cpu_id = 57, .valid = 1, .name = "DMA5_DERR_ECC" }, + { .fc_id = 84, .cpu_id = 57, .valid = 1, .name = "DMA6_DERR_ECC" }, + { .fc_id = 85, .cpu_id = 57, .valid = 1, .name = "DMA7_DERR_ECC" }, + { .fc_id = 86, .cpu_id = 58, .valid = 1, .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 87, .cpu_id = 59, .valid = 1, .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 60, .valid = 1, .name = "PSOC_MEM_SERR" }, + { .fc_id = 89, .cpu_id = 61, .valid = 1, + .name = "PSOC_CORESIGHT_SERR" }, + { .fc_id = 90, .cpu_id = 62, .valid = 1, .name = "PSOC_MEM_DERR" }, + { .fc_id = 91, .cpu_id = 63, .valid = 1, + .name = "PSOC_CORESIGHT_DERR" }, + { .fc_id = 92, .cpu_id = 64, .valid = 1, .name = "SRAM0_SERR" }, + { .fc_id = 93, .cpu_id = 64, .valid = 1, .name = "SRAM1_SERR" }, + { .fc_id = 94, .cpu_id = 64, .valid = 1, .name = "SRAM2_SERR" }, + { .fc_id = 95, .cpu_id = 64, .valid = 1, .name = "SRAM3_SERR" }, + { .fc_id = 96, .cpu_id = 64, .valid = 1, .name = "SRAM7_SERR" }, + { .fc_id = 97, .cpu_id = 64, .valid = 1, .name = "SRAM6_SERR" }, + { .fc_id = 98, .cpu_id = 64, .valid = 1, .name = "SRAM5_SERR" }, + { .fc_id = 99, .cpu_id = 64, .valid = 1, .name = "SRAM4_SERR" }, + { .fc_id = 100, .cpu_id = 64, .valid = 1, .name = "SRAM8_SERR" }, + { .fc_id = 101, .cpu_id = 64, .valid = 1, .name = "SRAM9_SERR" }, + { .fc_id = 102, .cpu_id = 64, .valid = 1, .name = "SRAM10_SERR" }, + { .fc_id = 103, .cpu_id = 64, .valid = 1, .name = "SRAM11_SERR" }, + { .fc_id = 104, .cpu_id = 64, .valid = 1, .name = "SRAM15_SERR" }, + { .fc_id = 105, .cpu_id = 64, .valid = 1, .name = "SRAM14_SERR" }, + { .fc_id = 106, .cpu_id = 64, .valid = 1, .name = "SRAM13_SERR" }, + { .fc_id = 107, .cpu_id = 64, .valid = 1, .name = "SRAM12_SERR" }, + { .fc_id = 108, .cpu_id = 64, .valid = 1, .name = "SRAM16_SERR" }, + { .fc_id = 109, .cpu_id = 64, .valid = 1, .name = "SRAM17_SERR" }, + { .fc_id = 110, .cpu_id = 64, .valid = 1, .name = "SRAM18_SERR" }, + { .fc_id = 111, .cpu_id = 64, .valid = 1, .name = "SRAM19_SERR" }, + { .fc_id = 112, .cpu_id = 64, .valid = 1, .name = "SRAM23_SERR" }, + { .fc_id = 113, .cpu_id = 64, .valid = 1, .name = "SRAM22_SERR" }, + { .fc_id = 114, .cpu_id = 64, .valid = 1, .name = "SRAM21_SERR" }, + { .fc_id = 115, .cpu_id = 64, .valid = 1, .name = "SRAM20_SERR" }, + { .fc_id = 116, .cpu_id = 64, .valid = 1, .name = "SRAM24_SERR" }, + { .fc_id = 117, .cpu_id = 64, .valid = 1, .name = "SRAM25_SERR" }, + { .fc_id = 118, .cpu_id = 64, .valid = 1, .name = "SRAM26_SERR" }, + { .fc_id = 119, .cpu_id = 64, .valid = 1, .name = "SRAM27_SERR" }, + { .fc_id = 120, .cpu_id = 64, .valid = 1, .name = "SRAM31_SERR" }, + { .fc_id = 121, .cpu_id = 64, .valid = 1, .name = "SRAM30_SERR" }, + { .fc_id = 122, .cpu_id = 64, .valid = 1, .name = "SRAM29_SERR" }, + { .fc_id = 123, .cpu_id = 64, .valid = 1, .name = "SRAM28_SERR" }, + { .fc_id = 124, .cpu_id = 65, .valid = 1, .name = "SRAM0_DERR" }, + { .fc_id = 125, .cpu_id = 65, .valid = 1, .name = "SRAM1_DERR" }, + { .fc_id = 126, .cpu_id = 65, .valid = 1, .name = "SRAM2_DERR" }, + { .fc_id = 127, .cpu_id = 65, .valid = 1, .name = "SRAM3_DERR" }, + { .fc_id = 128, .cpu_id = 65, .valid = 1, .name = "SRAM7_DERR" }, + { .fc_id = 129, .cpu_id = 65, .valid = 1, .name = "SRAM6_DERR" }, + { .fc_id = 130, .cpu_id = 65, .valid = 1, .name = "SRAM5_DERR" }, + { .fc_id = 131, .cpu_id = 65, .valid = 1, .name = "SRAM4_DERR" }, + { .fc_id = 132, .cpu_id = 65, .valid = 1, .name = "SRAM8_DERR" }, + { .fc_id = 133, .cpu_id = 65, .valid = 1, .name = "SRAM9_DERR" }, + { .fc_id = 134, .cpu_id = 65, .valid = 1, .name = "SRAM10_DERR" }, + { .fc_id = 135, .cpu_id = 65, .valid = 1, .name = "SRAM11_DERR" }, + { .fc_id = 136, .cpu_id = 65, .valid = 1, .name = "SRAM15_DERR" }, + { .fc_id = 137, .cpu_id = 65, .valid = 1, .name = "SRAM14_DERR" }, + { .fc_id = 138, .cpu_id = 65, .valid = 1, .name = "SRAM13_DERR" }, + { .fc_id = 139, .cpu_id = 65, .valid = 1, .name = "SRAM12_DERR" }, + { .fc_id = 140, .cpu_id = 65, .valid = 1, .name = "SRAM16_DERR" }, + { .fc_id = 141, .cpu_id = 65, .valid = 1, .name = "SRAM17_DERR" }, + { .fc_id = 142, .cpu_id = 65, .valid = 1, .name = "SRAM18_DERR" }, + { .fc_id = 143, .cpu_id = 65, .valid = 1, .name = "SRAM19_DERR" }, + { .fc_id = 144, .cpu_id = 65, .valid = 1, .name = "SRAM23_DERR" }, + { .fc_id = 145, .cpu_id = 65, .valid = 1, .name = "SRAM22_DERR" }, + { .fc_id = 146, .cpu_id = 65, .valid = 1, .name = "SRAM21_DERR" }, + { .fc_id = 147, .cpu_id = 65, .valid = 1, .name = "SRAM20_DERR" }, + { .fc_id = 148, .cpu_id = 65, .valid = 1, .name = "SRAM24_DERR" }, + { .fc_id = 149, .cpu_id = 65, .valid = 1, .name = "SRAM25_DERR" }, + { .fc_id = 150, .cpu_id = 65, .valid = 1, .name = "SRAM26_DERR" }, + { .fc_id = 151, .cpu_id = 65, .valid = 1, .name = "SRAM27_DERR" }, + { .fc_id = 152, .cpu_id = 65, .valid = 1, .name = "SRAM31_DERR" }, + { .fc_id = 153, .cpu_id = 65, .valid = 1, .name = "SRAM30_DERR" }, + { .fc_id = 154, .cpu_id = 65, .valid = 1, .name = "SRAM29_DERR" }, + { .fc_id = 155, .cpu_id = 65, .valid = 1, .name = "SRAM28_DERR" }, + { .fc_id = 156, .cpu_id = 66, .valid = 1, .name = "NIC0_SERR" }, + { .fc_id = 157, .cpu_id = 66, .valid = 1, .name = "NIC1_SERR" }, + { .fc_id = 158, .cpu_id = 66, .valid = 1, .name = "NIC2_SERR" }, + { .fc_id = 159, .cpu_id = 66, .valid = 1, .name = "NIC3_SERR" }, + { .fc_id = 160, .cpu_id = 66, .valid = 1, .name = "NIC4_SERR" }, + { .fc_id = 161, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 162, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 163, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 164, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 165, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 166, .cpu_id = 67, .valid = 1, .name = "NIC0_DERR" }, + { .fc_id = 167, .cpu_id = 67, .valid = 1, .name = "NIC1_DERR" }, + { .fc_id = 168, .cpu_id = 67, .valid = 1, .name = "NIC2_DERR" }, + { .fc_id = 169, .cpu_id = 67, .valid = 1, .name = "NIC3_DERR" }, + { .fc_id = 170, .cpu_id = 67, .valid = 1, .name = "NIC4_DERR" }, + { .fc_id = 171, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 172, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 173, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 174, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 175, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 176, .cpu_id = 68, .valid = 1, .name = "DMA_IF0_SERR" }, + { .fc_id = 177, .cpu_id = 68, .valid = 1, .name = "DMA_IF1_SERR" }, + { .fc_id = 178, .cpu_id = 68, .valid = 1, .name = "DMA_IF2_SERR" }, + { .fc_id = 179, .cpu_id = 68, .valid = 1, .name = "DMA_IF3_SERR" }, + { .fc_id = 180, .cpu_id = 69, .valid = 1, .name = "DMA_IF0_DERR" }, + { .fc_id = 181, .cpu_id = 69, .valid = 1, .name = "DMA_IF1_DERR" }, + { .fc_id = 182, .cpu_id = 69, .valid = 1, .name = "DMA_IF2_DERR" }, + { .fc_id = 183, .cpu_id = 69, .valid = 1, .name = "DMA_IF3_DERR" }, + { .fc_id = 184, .cpu_id = 70, .valid = 1, .name = "GIC500" }, + { .fc_id = 185, .cpu_id = 71, .valid = 1, .name = "HBM_0_SERR" }, + { .fc_id = 186, .cpu_id = 71, .valid = 1, .name = "HBM_1_SERR" }, + { .fc_id = 187, .cpu_id = 71, .valid = 1, .name = "HBM_2_SERR" }, + { .fc_id = 188, .cpu_id = 71, .valid = 1, .name = "HBM_3_SERR" }, + { .fc_id = 189, .cpu_id = 72, .valid = 1, .name = "HBM_0_DERR" }, + { .fc_id = 190, .cpu_id = 72, .valid = 1, .name = "HBM_1_DERR" }, + { .fc_id = 191, .cpu_id = 72, .valid = 1, .name = "HBM_2_DERR" }, + { .fc_id = 192, .cpu_id = 72, .valid = 1, .name = "HBM_3_DERR" }, + { .fc_id = 193, .cpu_id = 73, .valid = 1, .name = "MMU_SERR" }, + { .fc_id = 194, .cpu_id = 74, .valid = 1, .name = "MMU_DERR" }, + { .fc_id = 195, .cpu_id = 75, .valid = 0, .name = "" }, + { .fc_id = 196, .cpu_id = 76, .valid = 0, .name = "" }, + { .fc_id = 197, .cpu_id = 77, .valid = 0, .name = "" }, + { .fc_id = 198, .cpu_id = 78, .valid = 0, .name = "" }, + { .fc_id = 199, .cpu_id = 79, .valid = 0, .name = "" }, + { .fc_id = 200, .cpu_id = 80, .valid = 1, .name = "PCIE_DEC" }, + { .fc_id = 201, .cpu_id = 81, .valid = 1, .name = "TPC0_DEC" }, + { .fc_id = 202, .cpu_id = 82, .valid = 0, .name = "" }, + { .fc_id = 203, .cpu_id = 83, .valid = 1, .name = "TPC1_DEC" }, + { .fc_id = 204, .cpu_id = 84, .valid = 0, .name = "" }, + { .fc_id = 205, .cpu_id = 85, .valid = 1, .name = "TPC2_DEC" }, + { .fc_id = 206, .cpu_id = 86, .valid = 0, .name = "" }, + { .fc_id = 207, .cpu_id = 87, .valid = 1, .name = "TPC3_DEC" }, + { .fc_id = 208, .cpu_id = 88, .valid = 0, .name = "" }, + { .fc_id = 209, .cpu_id = 89, .valid = 1, .name = "TPC4_DEC" }, + { .fc_id = 210, .cpu_id = 90, .valid = 0, .name = "" }, + { .fc_id = 211, .cpu_id = 91, .valid = 1, .name = "TPC5_DEC" }, + { .fc_id = 212, .cpu_id = 92, .valid = 0, .name = "" }, + { .fc_id = 213, .cpu_id = 93, .valid = 1, .name = "TPC6_DEC" }, + { .fc_id = 214, .cpu_id = 94, .valid = 0, .name = "" }, + { .fc_id = 215, .cpu_id = 95, .valid = 1, .name = "TPC7_DEC" }, + { .fc_id = 216, .cpu_id = 96, .valid = 0, .name = "" }, + { .fc_id = 217, .cpu_id = 97, .valid = 1, .name = "AXI_ECC" }, + { .fc_id = 218, .cpu_id = 98, .valid = 1, .name = "L2_RAM_ECC" }, + { .fc_id = 219, .cpu_id = 99, .valid = 1, .name = "MME0_WBC_RSP" }, + { .fc_id = 220, .cpu_id = 100, .valid = 1, .name = "MME0_SBAB0_RSP" }, + { .fc_id = 221, .cpu_id = 101, .valid = 0, .name = "" }, + { .fc_id = 222, .cpu_id = 102, .valid = 0, .name = "" }, + { .fc_id = 223, .cpu_id = 103, .valid = 0, .name = "" }, + { .fc_id = 224, .cpu_id = 104, .valid = 1, .name = "MME1_WBC_RSP" }, + { .fc_id = 225, .cpu_id = 105, .valid = 1, .name = "MME1_SBAB0_RSP" }, + { .fc_id = 226, .cpu_id = 106, .valid = 0, .name = "" }, + { .fc_id = 227, .cpu_id = 107, .valid = 0, .name = "" }, + { .fc_id = 228, .cpu_id = 108, .valid = 0, .name = "" }, + { .fc_id = 229, .cpu_id = 109, .valid = 1, .name = "MME2_WBC_RSP" }, + { .fc_id = 230, .cpu_id = 110, .valid = 1, .name = "MME2_SBAB0_RSP" }, + { .fc_id = 231, .cpu_id = 111, .valid = 0, .name = "" }, + { .fc_id = 232, .cpu_id = 112, .valid = 0, .name = "" }, + { .fc_id = 233, .cpu_id = 113, .valid = 0, .name = "" }, + { .fc_id = 234, .cpu_id = 114, .valid = 1, .name = "MME3_WBC_RSP" }, + { .fc_id = 235, .cpu_id = 115, .valid = 1, .name = "MME3_SBAB0_RSP" }, + { .fc_id = 236, .cpu_id = 116, .valid = 0, .name = "" }, + { .fc_id = 237, .cpu_id = 117, .valid = 0, .name = "" }, + { .fc_id = 238, .cpu_id = 118, .valid = 0, .name = "" }, + { .fc_id = 239, .cpu_id = 119, .valid = 1, .name = "PLL0" }, + { .fc_id = 240, .cpu_id = 119, .valid = 1, .name = "PLL1" }, + { .fc_id = 241, .cpu_id = 119, .valid = 1, .name = "PLL2" }, + { .fc_id = 242, .cpu_id = 119, .valid = 1, .name = "PLL3" }, + { .fc_id = 243, .cpu_id = 119, .valid = 1, .name = "PLL4" }, + { .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" }, + { .fc_id = 245, .cpu_id = 119, .valid = 1, .name = "PLL6" }, + { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" }, + { .fc_id = 247, .cpu_id = 119, .valid = 1, .name = "PLL8" }, + { .fc_id = 248, .cpu_id = 119, .valid = 1, .name = "PLL9" }, + { .fc_id = 249, .cpu_id = 119, .valid = 1, .name = "PLL10" }, + { .fc_id = 250, .cpu_id = 119, .valid = 1, .name = "PLL11" }, + { .fc_id = 251, .cpu_id = 119, .valid = 1, .name = "PLL12" }, + { .fc_id = 252, .cpu_id = 119, .valid = 1, .name = "PLL13" }, + { .fc_id = 253, .cpu_id = 119, .valid = 1, .name = "PLL14" }, + { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" }, + { .fc_id = 255, .cpu_id = 119, .valid = 1, .name = "PLL16" }, + { .fc_id = 256, .cpu_id = 119, .valid = 1, .name = "PLL17" }, + { .fc_id = 257, .cpu_id = 120, .valid = 1, + .name = "CPU_AXI_SPLITTER" }, + { .fc_id = 258, .cpu_id = 121, .valid = 0, .name = "" }, + { .fc_id = 259, .cpu_id = 122, .valid = 0, .name = "" }, + { .fc_id = 260, .cpu_id = 123, .valid = 0, .name = "" }, + { .fc_id = 261, .cpu_id = 124, .valid = 0, .name = "" }, + { .fc_id = 262, .cpu_id = 125, .valid = 1, .name = "PSOC_AXI_DEC" }, + { .fc_id = 263, .cpu_id = 126, .valid = 1, .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 264, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_0" }, + { .fc_id = 265, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_1" }, + { .fc_id = 266, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_2" }, + { .fc_id = 267, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_3" }, + { .fc_id = 268, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_4" }, + { .fc_id = 269, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 270, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 271, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 272, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 273, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 274, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 275, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 276, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 277, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_0" }, + { .fc_id = 278, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_1" }, + { .fc_id = 279, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_2" }, + { .fc_id = 280, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_3" }, + { .fc_id = 281, .cpu_id = 130, .valid = 0, .name = "" }, + { .fc_id = 282, .cpu_id = 131, .valid = 0, .name = "" }, + { .fc_id = 283, .cpu_id = 132, .valid = 0, .name = "" }, + { .fc_id = 284, .cpu_id = 133, .valid = 0, .name = "" }, + { .fc_id = 285, .cpu_id = 134, .valid = 0, .name = "" }, + { .fc_id = 286, .cpu_id = 135, .valid = 0, .name = "" }, + { .fc_id = 287, .cpu_id = 136, .valid = 0, .name = "" }, + { .fc_id = 288, .cpu_id = 137, .valid = 0, .name = "" }, + { .fc_id = 289, .cpu_id = 138, .valid = 0, .name = "" }, + { .fc_id = 290, .cpu_id = 139, .valid = 1, .name = "PCIE_FLR" }, + { .fc_id = 291, .cpu_id = 140, .valid = 0, .name = "" }, + { .fc_id = 292, .cpu_id = 141, .valid = 0, .name = "" }, + { .fc_id = 293, .cpu_id = 142, .valid = 0, .name = "" }, + { .fc_id = 294, .cpu_id = 143, .valid = 0, .name = "" }, + { .fc_id = 295, .cpu_id = 144, .valid = 0, .name = "" }, + { .fc_id = 296, .cpu_id = 145, .valid = 0, .name = "" }, + { .fc_id = 297, .cpu_id = 146, .valid = 0, .name = "" }, + { .fc_id = 298, .cpu_id = 147, .valid = 0, .name = "" }, + { .fc_id = 299, .cpu_id = 148, .valid = 0, .name = "" }, + { .fc_id = 300, .cpu_id = 149, .valid = 1, .name = "TPC0_BMON_SPMU" }, + { .fc_id = 301, .cpu_id = 150, .valid = 1, .name = "TPC0_KRN_ERR" }, + { .fc_id = 302, .cpu_id = 151, .valid = 0, .name = "" }, + { .fc_id = 303, .cpu_id = 152, .valid = 0, .name = "" }, + { .fc_id = 304, .cpu_id = 153, .valid = 0, .name = "" }, + { .fc_id = 305, .cpu_id = 154, .valid = 0, .name = "" }, + { .fc_id = 306, .cpu_id = 155, .valid = 1, .name = "TPC1_BMON_SPMU" }, + { .fc_id = 307, .cpu_id = 156, .valid = 1, .name = "TPC1_KRN_ERR" }, + { .fc_id = 308, .cpu_id = 157, .valid = 0, .name = "" }, + { .fc_id = 309, .cpu_id = 158, .valid = 0, .name = "" }, + { .fc_id = 310, .cpu_id = 159, .valid = 0, .name = "" }, + { .fc_id = 311, .cpu_id = 160, .valid = 0, .name = "" }, + { .fc_id = 312, .cpu_id = 161, .valid = 1, .name = "TPC2_BMON_SPMU" }, + { .fc_id = 313, .cpu_id = 162, .valid = 1, .name = "TPC2_KRN_ERR" }, + { .fc_id = 314, .cpu_id = 163, .valid = 0, .name = "" }, + { .fc_id = 315, .cpu_id = 164, .valid = 0, .name = "" }, + { .fc_id = 316, .cpu_id = 165, .valid = 0, .name = "" }, + { .fc_id = 317, .cpu_id = 166, .valid = 0, .name = "" }, + { .fc_id = 318, .cpu_id = 167, .valid = 1, .name = "TPC3_BMON_SPMU" }, + { .fc_id = 319, .cpu_id = 168, .valid = 1, .name = "TPC3_KRN_ERR" }, + { .fc_id = 320, .cpu_id = 169, .valid = 0, .name = "" }, + { .fc_id = 321, .cpu_id = 170, .valid = 0, .name = "" }, + { .fc_id = 322, .cpu_id = 171, .valid = 0, .name = "" }, + { .fc_id = 323, .cpu_id = 172, .valid = 0, .name = "" }, + { .fc_id = 324, .cpu_id = 173, .valid = 1, .name = "TPC4_BMON_SPMU" }, + { .fc_id = 325, .cpu_id = 174, .valid = 1, .name = "TPC4_KRN_ERR" }, + { .fc_id = 326, .cpu_id = 175, .valid = 0, .name = "" }, + { .fc_id = 327, .cpu_id = 176, .valid = 0, .name = "" }, + { .fc_id = 328, .cpu_id = 177, .valid = 0, .name = "" }, + { .fc_id = 329, .cpu_id = 178, .valid = 0, .name = "" }, + { .fc_id = 330, .cpu_id = 179, .valid = 1, .name = "TPC5_BMON_SPMU" }, + { .fc_id = 331, .cpu_id = 180, .valid = 1, .name = "TPC5_KRN_ERR" }, + { .fc_id = 332, .cpu_id = 181, .valid = 0, .name = "" }, + { .fc_id = 333, .cpu_id = 182, .valid = 0, .name = "" }, + { .fc_id = 334, .cpu_id = 183, .valid = 0, .name = "" }, + { .fc_id = 335, .cpu_id = 184, .valid = 0, .name = "" }, + { .fc_id = 336, .cpu_id = 185, .valid = 1, .name = "TPC6_BMON_SPMU" }, + { .fc_id = 337, .cpu_id = 186, .valid = 1, .name = "TPC6_KRN_ERR" }, + { .fc_id = 338, .cpu_id = 187, .valid = 0, .name = "" }, + { .fc_id = 339, .cpu_id = 188, .valid = 0, .name = "" }, + { .fc_id = 340, .cpu_id = 189, .valid = 0, .name = "" }, + { .fc_id = 341, .cpu_id = 190, .valid = 0, .name = "" }, + { .fc_id = 342, .cpu_id = 191, .valid = 1, .name = "TPC7_BMON_SPMU" }, + { .fc_id = 343, .cpu_id = 192, .valid = 1, .name = "TPC7_KRN_ERR" }, + { .fc_id = 344, .cpu_id = 193, .valid = 0, .name = "" }, + { .fc_id = 345, .cpu_id = 194, .valid = 0, .name = "" }, + { .fc_id = 346, .cpu_id = 195, .valid = 0, .name = "" }, + { .fc_id = 347, .cpu_id = 196, .valid = 0, .name = "" }, + { .fc_id = 348, .cpu_id = 197, .valid = 0, .name = "" }, + { .fc_id = 349, .cpu_id = 198, .valid = 0, .name = "" }, + { .fc_id = 350, .cpu_id = 199, .valid = 0, .name = "" }, + { .fc_id = 351, .cpu_id = 200, .valid = 0, .name = "" }, + { .fc_id = 352, .cpu_id = 201, .valid = 0, .name = "" }, + { .fc_id = 353, .cpu_id = 202, .valid = 0, .name = "" }, + { .fc_id = 354, .cpu_id = 203, .valid = 0, .name = "" }, + { .fc_id = 355, .cpu_id = 204, .valid = 0, .name = "" }, + { .fc_id = 356, .cpu_id = 205, .valid = 0, .name = "" }, + { .fc_id = 357, .cpu_id = 206, .valid = 0, .name = "" }, + { .fc_id = 358, .cpu_id = 207, .valid = 0, .name = "" }, + { .fc_id = 359, .cpu_id = 208, .valid = 0, .name = "" }, + { .fc_id = 360, .cpu_id = 209, .valid = 0, .name = "" }, + { .fc_id = 361, .cpu_id = 210, .valid = 0, .name = "" }, + { .fc_id = 362, .cpu_id = 211, .valid = 0, .name = "" }, + { .fc_id = 363, .cpu_id = 212, .valid = 0, .name = "" }, + { .fc_id = 364, .cpu_id = 213, .valid = 0, .name = "" }, + { .fc_id = 365, .cpu_id = 214, .valid = 0, .name = "" }, + { .fc_id = 366, .cpu_id = 215, .valid = 0, .name = "" }, + { .fc_id = 367, .cpu_id = 216, .valid = 0, .name = "" }, + { .fc_id = 368, .cpu_id = 217, .valid = 0, .name = "" }, + { .fc_id = 369, .cpu_id = 218, .valid = 0, .name = "" }, + { .fc_id = 370, .cpu_id = 219, .valid = 0, .name = "" }, + { .fc_id = 371, .cpu_id = 220, .valid = 0, .name = "" }, + { .fc_id = 372, .cpu_id = 221, .valid = 0, .name = "" }, + { .fc_id = 373, .cpu_id = 222, .valid = 0, .name = "" }, + { .fc_id = 374, .cpu_id = 223, .valid = 0, .name = "" }, + { .fc_id = 375, .cpu_id = 224, .valid = 0, .name = "" }, + { .fc_id = 376, .cpu_id = 225, .valid = 0, .name = "" }, + { .fc_id = 377, .cpu_id = 226, .valid = 0, .name = "" }, + { .fc_id = 378, .cpu_id = 227, .valid = 0, .name = "" }, + { .fc_id = 379, .cpu_id = 228, .valid = 0, .name = "" }, + { .fc_id = 380, .cpu_id = 229, .valid = 1, .name = "MMU_PAGE_FAULT" }, + { .fc_id = 381, .cpu_id = 230, .valid = 1, .name = "MMU_WR_PERM" }, + { .fc_id = 382, .cpu_id = 231, .valid = 0, .name = "" }, + { .fc_id = 383, .cpu_id = 232, .valid = 1, .name = "DMA_BM_CH0" }, + { .fc_id = 384, .cpu_id = 233, .valid = 1, .name = "DMA_BM_CH1" }, + { .fc_id = 385, .cpu_id = 234, .valid = 1, .name = "DMA_BM_CH2" }, + { .fc_id = 386, .cpu_id = 235, .valid = 1, .name = "DMA_BM_CH3" }, + { .fc_id = 387, .cpu_id = 236, .valid = 1, .name = "DMA_BM_CH4" }, + { .fc_id = 388, .cpu_id = 237, .valid = 1, .name = "DMA_BM_CH5" }, + { .fc_id = 389, .cpu_id = 238, .valid = 1, .name = "DMA_BM_CH6" }, + { .fc_id = 390, .cpu_id = 239, .valid = 1, .name = "DMA_BM_CH7" }, + { .fc_id = 391, .cpu_id = 240, .valid = 0, .name = "" }, + { .fc_id = 392, .cpu_id = 241, .valid = 0, .name = "" }, + { .fc_id = 393, .cpu_id = 242, .valid = 0, .name = "" }, + { .fc_id = 394, .cpu_id = 243, .valid = 0, .name = "" }, + { .fc_id = 395, .cpu_id = 244, .valid = 1, .name = "HBM0_SPI_0" }, + { .fc_id = 396, .cpu_id = 245, .valid = 1, .name = "HBM0_SPI_1" }, + { .fc_id = 397, .cpu_id = 246, .valid = 0, .name = "" }, + { .fc_id = 398, .cpu_id = 247, .valid = 0, .name = "" }, + { .fc_id = 399, .cpu_id = 248, .valid = 1, .name = "HBM1_SPI_0" }, + { .fc_id = 400, .cpu_id = 249, .valid = 1, .name = "HBM1_SPI_1" }, + { .fc_id = 401, .cpu_id = 250, .valid = 0, .name = "" }, + { .fc_id = 402, .cpu_id = 251, .valid = 0, .name = "" }, + { .fc_id = 403, .cpu_id = 252, .valid = 1, .name = "HBM2_SPI_0" }, + { .fc_id = 404, .cpu_id = 253, .valid = 1, .name = "HBM2_SPI_1" }, + { .fc_id = 405, .cpu_id = 254, .valid = 0, .name = "" }, + { .fc_id = 406, .cpu_id = 255, .valid = 0, .name = "" }, + { .fc_id = 407, .cpu_id = 256, .valid = 1, .name = "HBM3_SPI_0" }, + { .fc_id = 408, .cpu_id = 257, .valid = 1, .name = "HBM3_SPI_1" }, + { .fc_id = 409, .cpu_id = 258, .valid = 0, .name = "" }, + { .fc_id = 410, .cpu_id = 259, .valid = 0, .name = "" }, + { .fc_id = 411, .cpu_id = 260, .valid = 0, .name = "" }, + { .fc_id = 412, .cpu_id = 261, .valid = 0, .name = "" }, + { .fc_id = 413, .cpu_id = 262, .valid = 0, .name = "" }, + { .fc_id = 414, .cpu_id = 263, .valid = 0, .name = "" }, + { .fc_id = 415, .cpu_id = 264, .valid = 0, .name = "" }, + { .fc_id = 416, .cpu_id = 265, .valid = 0, .name = "" }, + { .fc_id = 417, .cpu_id = 266, .valid = 0, .name = "" }, + { .fc_id = 418, .cpu_id = 267, .valid = 0, .name = "" }, + { .fc_id = 419, .cpu_id = 268, .valid = 0, .name = "" }, + { .fc_id = 420, .cpu_id = 269, .valid = 0, .name = "" }, + { .fc_id = 421, .cpu_id = 270, .valid = 1, .name = "PSOC_GPIO_U16_0" }, + { .fc_id = 422, .cpu_id = 271, .valid = 0, .name = "" }, + { .fc_id = 423, .cpu_id = 272, .valid = 0, .name = "" }, + { .fc_id = 424, .cpu_id = 273, .valid = 0, .name = "" }, + { .fc_id = 425, .cpu_id = 274, .valid = 0, .name = "" }, + { .fc_id = 426, .cpu_id = 275, .valid = 0, .name = "" }, + { .fc_id = 427, .cpu_id = 276, .valid = 0, .name = "" }, + { .fc_id = 428, .cpu_id = 277, .valid = 0, .name = "" }, + { .fc_id = 429, .cpu_id = 278, .valid = 0, .name = "" }, + { .fc_id = 430, .cpu_id = 279, .valid = 0, .name = "" }, + { .fc_id = 431, .cpu_id = 280, .valid = 0, .name = "" }, + { .fc_id = 432, .cpu_id = 281, .valid = 0, .name = "" }, + { .fc_id = 433, .cpu_id = 282, .valid = 0, .name = "" }, + { .fc_id = 434, .cpu_id = 283, .valid = 0, .name = "" }, + { .fc_id = 435, .cpu_id = 284, .valid = 0, .name = "" }, + { .fc_id = 436, .cpu_id = 285, .valid = 0, .name = "" }, + { .fc_id = 437, .cpu_id = 286, .valid = 0, .name = "" }, + { .fc_id = 438, .cpu_id = 287, .valid = 0, .name = "" }, + { .fc_id = 439, .cpu_id = 288, .valid = 0, .name = "" }, + { .fc_id = 440, .cpu_id = 289, .valid = 0, .name = "" }, + { .fc_id = 441, .cpu_id = 290, .valid = 0, .name = "" }, + { .fc_id = 442, .cpu_id = 291, .valid = 0, .name = "" }, + { .fc_id = 443, .cpu_id = 292, .valid = 0, .name = "" }, + { .fc_id = 444, .cpu_id = 293, .valid = 0, .name = "" }, + { .fc_id = 445, .cpu_id = 294, .valid = 0, .name = "" }, + { .fc_id = 446, .cpu_id = 295, .valid = 0, .name = "" }, + { .fc_id = 447, .cpu_id = 296, .valid = 0, .name = "" }, + { .fc_id = 448, .cpu_id = 297, .valid = 0, .name = "" }, + { .fc_id = 449, .cpu_id = 298, .valid = 0, .name = "" }, + { .fc_id = 450, .cpu_id = 299, .valid = 0, .name = "" }, + { .fc_id = 451, .cpu_id = 300, .valid = 0, .name = "" }, + { .fc_id = 452, .cpu_id = 301, .valid = 0, .name = "" }, + { .fc_id = 453, .cpu_id = 302, .valid = 0, .name = "" }, + { .fc_id = 454, .cpu_id = 303, .valid = 0, .name = "" }, + { .fc_id = 455, .cpu_id = 304, .valid = 0, .name = "" }, + { .fc_id = 456, .cpu_id = 305, .valid = 0, .name = "" }, + { .fc_id = 457, .cpu_id = 306, .valid = 0, .name = "" }, + { .fc_id = 458, .cpu_id = 307, .valid = 0, .name = "" }, + { .fc_id = 459, .cpu_id = 308, .valid = 0, .name = "" }, + { .fc_id = 460, .cpu_id = 309, .valid = 0, .name = "" }, + { .fc_id = 461, .cpu_id = 310, .valid = 0, .name = "" }, + { .fc_id = 462, .cpu_id = 311, .valid = 0, .name = "" }, + { .fc_id = 463, .cpu_id = 312, .valid = 0, .name = "" }, + { .fc_id = 464, .cpu_id = 313, .valid = 0, .name = "" }, + { .fc_id = 465, .cpu_id = 314, .valid = 0, .name = "" }, + { .fc_id = 466, .cpu_id = 315, .valid = 0, .name = "" }, + { .fc_id = 467, .cpu_id = 316, .valid = 0, .name = "" }, + { .fc_id = 468, .cpu_id = 317, .valid = 0, .name = "" }, + { .fc_id = 469, .cpu_id = 318, .valid = 0, .name = "" }, + { .fc_id = 470, .cpu_id = 319, .valid = 0, .name = "" }, + { .fc_id = 471, .cpu_id = 320, .valid = 0, .name = "" }, + { .fc_id = 472, .cpu_id = 321, .valid = 0, .name = "" }, + { .fc_id = 473, .cpu_id = 322, .valid = 0, .name = "" }, + { .fc_id = 474, .cpu_id = 323, .valid = 0, .name = "" }, + { .fc_id = 475, .cpu_id = 324, .valid = 0, .name = "" }, + { .fc_id = 476, .cpu_id = 325, .valid = 0, .name = "" }, + { .fc_id = 477, .cpu_id = 326, .valid = 0, .name = "" }, + { .fc_id = 478, .cpu_id = 327, .valid = 0, .name = "" }, + { .fc_id = 479, .cpu_id = 328, .valid = 0, .name = "" }, + { .fc_id = 480, .cpu_id = 329, .valid = 0, .name = "" }, + { .fc_id = 481, .cpu_id = 330, .valid = 0, .name = "" }, + { .fc_id = 482, .cpu_id = 331, .valid = 0, .name = "" }, + { .fc_id = 483, .cpu_id = 332, .valid = 1, + .name = "NIC0_CS_DBG_DERR" }, + { .fc_id = 484, .cpu_id = 333, .valid = 0, .name = "" }, + { .fc_id = 485, .cpu_id = 334, .valid = 0, .name = "" }, + { .fc_id = 486, .cpu_id = 335, .valid = 0, .name = "" }, + { .fc_id = 487, .cpu_id = 336, .valid = 1, + .name = "NIC1_CS_DBG_DERR" }, + { .fc_id = 488, .cpu_id = 337, .valid = 0, .name = "" }, + { .fc_id = 489, .cpu_id = 338, .valid = 0, .name = "" }, + { .fc_id = 490, .cpu_id = 339, .valid = 0, .name = "" }, + { .fc_id = 491, .cpu_id = 340, .valid = 1, + .name = "NIC2_CS_DBG_DERR" }, + { .fc_id = 492, .cpu_id = 341, .valid = 0, .name = "" }, + { .fc_id = 493, .cpu_id = 342, .valid = 0, .name = "" }, + { .fc_id = 494, .cpu_id = 343, .valid = 0, .name = "" }, + { .fc_id = 495, .cpu_id = 344, .valid = 1, + .name = "NIC3_CS_DBG_DERR" }, + { .fc_id = 496, .cpu_id = 345, .valid = 0, .name = "" }, + { .fc_id = 497, .cpu_id = 346, .valid = 0, .name = "" }, + { .fc_id = 498, .cpu_id = 347, .valid = 0, .name = "" }, + { .fc_id = 499, .cpu_id = 348, .valid = 1, + .name = "NIC4_CS_DBG_DERR" }, + { .fc_id = 500, .cpu_id = 349, .valid = 0, .name = "" }, + { .fc_id = 501, .cpu_id = 350, .valid = 0, .name = "" }, + { .fc_id = 502, .cpu_id = 351, .valid = 0, .name = "" }, + { .fc_id = 503, .cpu_id = 352, .valid = 0, .name = "" }, + { .fc_id = 504, .cpu_id = 353, .valid = 0, .name = "" }, + { .fc_id = 505, .cpu_id = 354, .valid = 0, .name = "" }, + { .fc_id = 506, .cpu_id = 355, .valid = 0, .name = "" }, + { .fc_id = 507, .cpu_id = 356, .valid = 0, .name = "" }, + { .fc_id = 508, .cpu_id = 357, .valid = 0, .name = "" }, + { .fc_id = 509, .cpu_id = 358, .valid = 0, .name = "" }, + { .fc_id = 510, .cpu_id = 359, .valid = 0, .name = "" }, + { .fc_id = 511, .cpu_id = 360, .valid = 0, .name = "" }, + { .fc_id = 512, .cpu_id = 361, .valid = 0, .name = "" }, + { .fc_id = 513, .cpu_id = 362, .valid = 0, .name = "" }, + { .fc_id = 514, .cpu_id = 363, .valid = 0, .name = "" }, + { .fc_id = 515, .cpu_id = 364, .valid = 0, .name = "" }, + { .fc_id = 516, .cpu_id = 365, .valid = 0, .name = "" }, + { .fc_id = 517, .cpu_id = 366, .valid = 0, .name = "" }, + { .fc_id = 518, .cpu_id = 367, .valid = 0, .name = "" }, + { .fc_id = 519, .cpu_id = 368, .valid = 0, .name = "" }, + { .fc_id = 520, .cpu_id = 369, .valid = 0, .name = "" }, + { .fc_id = 521, .cpu_id = 370, .valid = 0, .name = "" }, + { .fc_id = 522, .cpu_id = 371, .valid = 0, .name = "" }, + { .fc_id = 523, .cpu_id = 372, .valid = 0, .name = "" }, + { .fc_id = 524, .cpu_id = 373, .valid = 0, .name = "" }, + { .fc_id = 525, .cpu_id = 374, .valid = 0, .name = "" }, + { .fc_id = 526, .cpu_id = 375, .valid = 0, .name = "" }, + { .fc_id = 527, .cpu_id = 376, .valid = 0, .name = "" }, + { .fc_id = 528, .cpu_id = 377, .valid = 0, .name = "" }, + { .fc_id = 529, .cpu_id = 378, .valid = 0, .name = "" }, + { .fc_id = 530, .cpu_id = 379, .valid = 0, .name = "" }, + { .fc_id = 531, .cpu_id = 380, .valid = 0, .name = "" }, + { .fc_id = 532, .cpu_id = 381, .valid = 0, .name = "" }, + { .fc_id = 533, .cpu_id = 382, .valid = 0, .name = "" }, + { .fc_id = 534, .cpu_id = 383, .valid = 0, .name = "" }, + { .fc_id = 535, .cpu_id = 384, .valid = 0, .name = "" }, + { .fc_id = 536, .cpu_id = 385, .valid = 0, .name = "" }, + { .fc_id = 537, .cpu_id = 386, .valid = 0, .name = "" }, + { .fc_id = 538, .cpu_id = 387, .valid = 0, .name = "" }, + { .fc_id = 539, .cpu_id = 388, .valid = 0, .name = "" }, + { .fc_id = 540, .cpu_id = 389, .valid = 0, .name = "" }, + { .fc_id = 541, .cpu_id = 390, .valid = 0, .name = "" }, + { .fc_id = 542, .cpu_id = 391, .valid = 0, .name = "" }, + { .fc_id = 543, .cpu_id = 392, .valid = 0, .name = "" }, + { .fc_id = 544, .cpu_id = 393, .valid = 0, .name = "" }, + { .fc_id = 545, .cpu_id = 394, .valid = 0, .name = "" }, + { .fc_id = 546, .cpu_id = 395, .valid = 0, .name = "" }, + { .fc_id = 547, .cpu_id = 396, .valid = 0, .name = "" }, + { .fc_id = 548, .cpu_id = 397, .valid = 1, .name = "RAZWI_OR_ADC" }, + { .fc_id = 549, .cpu_id = 398, .valid = 0, .name = "" }, + { .fc_id = 550, .cpu_id = 399, .valid = 0, .name = "" }, + { .fc_id = 551, .cpu_id = 400, .valid = 0, .name = "" }, + { .fc_id = 552, .cpu_id = 401, .valid = 0, .name = "" }, + { .fc_id = 553, .cpu_id = 402, .valid = 0, .name = "" }, + { .fc_id = 554, .cpu_id = 403, .valid = 0, .name = "" }, + { .fc_id = 555, .cpu_id = 404, .valid = 0, .name = "" }, + { .fc_id = 556, .cpu_id = 405, .valid = 0, .name = "" }, + { .fc_id = 557, .cpu_id = 406, .valid = 0, .name = "" }, + { .fc_id = 558, .cpu_id = 407, .valid = 0, .name = "" }, + { .fc_id = 559, .cpu_id = 408, .valid = 0, .name = "" }, + { .fc_id = 560, .cpu_id = 409, .valid = 0, .name = "" }, + { .fc_id = 561, .cpu_id = 410, .valid = 0, .name = "" }, + { .fc_id = 562, .cpu_id = 411, .valid = 0, .name = "" }, + { .fc_id = 563, .cpu_id = 412, .valid = 0, .name = "" }, + { .fc_id = 564, .cpu_id = 413, .valid = 0, .name = "" }, + { .fc_id = 565, .cpu_id = 414, .valid = 0, .name = "" }, + { .fc_id = 566, .cpu_id = 415, .valid = 0, .name = "" }, + { .fc_id = 567, .cpu_id = 416, .valid = 0, .name = "" }, + { .fc_id = 568, .cpu_id = 417, .valid = 0, .name = "" }, + { .fc_id = 569, .cpu_id = 418, .valid = 0, .name = "" }, + { .fc_id = 570, .cpu_id = 419, .valid = 0, .name = "" }, + { .fc_id = 571, .cpu_id = 420, .valid = 0, .name = "" }, + { .fc_id = 572, .cpu_id = 421, .valid = 1, .name = "TPC0_QM" }, + { .fc_id = 573, .cpu_id = 422, .valid = 1, .name = "TPC1_QM" }, + { .fc_id = 574, .cpu_id = 423, .valid = 1, .name = "TPC2_QM" }, + { .fc_id = 575, .cpu_id = 424, .valid = 1, .name = "TPC3_QM" }, + { .fc_id = 576, .cpu_id = 425, .valid = 1, .name = "TPC4_QM" }, + { .fc_id = 577, .cpu_id = 426, .valid = 1, .name = "TPC5_QM" }, + { .fc_id = 578, .cpu_id = 427, .valid = 1, .name = "TPC6_QM" }, + { .fc_id = 579, .cpu_id = 428, .valid = 1, .name = "TPC7_QM" }, + { .fc_id = 580, .cpu_id = 429, .valid = 0, .name = "" }, + { .fc_id = 581, .cpu_id = 430, .valid = 1, .name = "MME0_QM" }, + { .fc_id = 582, .cpu_id = 431, .valid = 1, .name = "MME2_QM" }, + { .fc_id = 583, .cpu_id = 432, .valid = 1, .name = "DMA0_QM" }, + { .fc_id = 584, .cpu_id = 433, .valid = 1, .name = "DMA1_QM" }, + { .fc_id = 585, .cpu_id = 434, .valid = 1, .name = "DMA2_QM" }, + { .fc_id = 586, .cpu_id = 435, .valid = 1, .name = "DMA3_QM" }, + { .fc_id = 587, .cpu_id = 436, .valid = 1, .name = "DMA4_QM" }, + { .fc_id = 588, .cpu_id = 437, .valid = 1, .name = "DMA5_QM" }, + { .fc_id = 589, .cpu_id = 438, .valid = 1, .name = "DMA6_QM" }, + { .fc_id = 590, .cpu_id = 439, .valid = 1, .name = "DMA7_QM" }, + { .fc_id = 591, .cpu_id = 440, .valid = 0, .name = "" }, + { .fc_id = 592, .cpu_id = 441, .valid = 0, .name = "" }, + { .fc_id = 593, .cpu_id = 442, .valid = 0, .name = "" }, + { .fc_id = 594, .cpu_id = 443, .valid = 1, .name = "NIC0_QM0" }, + { .fc_id = 595, .cpu_id = 444, .valid = 1, .name = "NIC0_QM1" }, + { .fc_id = 596, .cpu_id = 445, .valid = 1, .name = "NIC1_QM0" }, + { .fc_id = 597, .cpu_id = 446, .valid = 1, .name = "NIC1_QM1" }, + { .fc_id = 598, .cpu_id = 447, .valid = 1, .name = "NIC2_QM0" }, + { .fc_id = 599, .cpu_id = 448, .valid = 1, .name = "NIC2_QM1" }, + { .fc_id = 600, .cpu_id = 449, .valid = 1, .name = "NIC3_QM0" }, + { .fc_id = 601, .cpu_id = 450, .valid = 1, .name = "NIC3_QM1" }, + { .fc_id = 602, .cpu_id = 451, .valid = 1, .name = "NIC4_QM0" }, + { .fc_id = 603, .cpu_id = 452, .valid = 1, .name = "NIC4_QM1" }, + { .fc_id = 604, .cpu_id = 453, .valid = 1, .name = "DMA0_CORE" }, + { .fc_id = 605, .cpu_id = 454, .valid = 1, .name = "DMA1_CORE" }, + { .fc_id = 606, .cpu_id = 455, .valid = 1, .name = "DMA2_CORE" }, + { .fc_id = 607, .cpu_id = 456, .valid = 1, .name = "DMA3_CORE" }, + { .fc_id = 608, .cpu_id = 457, .valid = 1, .name = "DMA4_CORE" }, + { .fc_id = 609, .cpu_id = 458, .valid = 1, .name = "DMA5_CORE" }, + { .fc_id = 610, .cpu_id = 459, .valid = 1, .name = "DMA6_CORE" }, + { .fc_id = 611, .cpu_id = 460, .valid = 1, .name = "DMA7_CORE" }, + { .fc_id = 612, .cpu_id = 461, .valid = 1, .name = "NIC0_QP0" }, + { .fc_id = 613, .cpu_id = 462, .valid = 1, .name = "NIC0_QP1" }, + { .fc_id = 614, .cpu_id = 463, .valid = 1, .name = "NIC1_QP0" }, + { .fc_id = 615, .cpu_id = 464, .valid = 1, .name = "NIC1_QP1" }, + { .fc_id = 616, .cpu_id = 465, .valid = 1, .name = "NIC2_QP0" }, + { .fc_id = 617, .cpu_id = 466, .valid = 1, .name = "NIC2_QP1" }, + { .fc_id = 618, .cpu_id = 467, .valid = 1, .name = "NIC3_QP0" }, + { .fc_id = 619, .cpu_id = 468, .valid = 1, .name = "NIC3_QP1" }, + { .fc_id = 620, .cpu_id = 469, .valid = 1, .name = "NIC4_QP0" }, + { .fc_id = 621, .cpu_id = 470, .valid = 1, .name = "NIC4_QP1" }, + { .fc_id = 622, .cpu_id = 471, .valid = 0, .name = "" }, + { .fc_id = 623, .cpu_id = 472, .valid = 0, .name = "" }, + { .fc_id = 624, .cpu_id = 473, .valid = 0, .name = "" }, + { .fc_id = 625, .cpu_id = 474, .valid = 0, .name = "" }, + { .fc_id = 626, .cpu_id = 475, .valid = 0, .name = "" }, + { .fc_id = 627, .cpu_id = 476, .valid = 0, .name = "" }, + { .fc_id = 628, .cpu_id = 477, .valid = 0, .name = "" }, + { .fc_id = 629, .cpu_id = 478, .valid = 0, .name = "" }, + { .fc_id = 630, .cpu_id = 479, .valid = 0, .name = "" }, + { .fc_id = 631, .cpu_id = 480, .valid = 0, .name = "" }, + { .fc_id = 632, .cpu_id = 481, .valid = 0, .name = "" }, + { .fc_id = 633, .cpu_id = 482, .valid = 0, .name = "" }, + { .fc_id = 634, .cpu_id = 483, .valid = 0, .name = "" }, + { .fc_id = 635, .cpu_id = 484, .valid = 1, .name = "PI_UPDATE" }, + { .fc_id = 636, .cpu_id = 485, .valid = 1, .name = "HALT_MACHINE" }, + { .fc_id = 637, .cpu_id = 486, .valid = 1, .name = "INTS_REGISTER" }, + { .fc_id = 638, .cpu_id = 487, .valid = 1, .name = "SOFT_RESET" }, + { .fc_id = 639, .cpu_id = 488, .valid = 0, .name = "" }, + { .fc_id = 640, .cpu_id = 489, .valid = 0, .name = "" }, + { .fc_id = 641, .cpu_id = 490, .valid = 0, .name = "" }, + { .fc_id = 642, .cpu_id = 491, .valid = 0, .name = "" }, + { .fc_id = 643, .cpu_id = 492, .valid = 0, .name = "" }, + { .fc_id = 644, .cpu_id = 493, .valid = 0, .name = "" }, + { .fc_id = 645, .cpu_id = 494, .valid = 1, .name = "FW_ALIVE_S" }, + { .fc_id = 646, .cpu_id = 495, .valid = 1, .name = "DEV_RESET_REQ" }, + { .fc_id = 647, .cpu_id = 496, .valid = 1, + .name = "PKT_QUEUE_OUT_SYNC" }, + { .fc_id = 648, .cpu_id = 497, .valid = 1, + .name = "STATUS_NIC0_ENG0" }, + { .fc_id = 649, .cpu_id = 498, .valid = 1, + .name = "STATUS_NIC0_ENG1" }, + { .fc_id = 650, .cpu_id = 499, .valid = 1, + .name = "STATUS_NIC1_ENG0" }, + { .fc_id = 651, .cpu_id = 500, .valid = 1, + .name = "STATUS_NIC1_ENG1" }, + { .fc_id = 652, .cpu_id = 501, .valid = 1, + .name = "STATUS_NIC2_ENG0" }, + { .fc_id = 653, .cpu_id = 502, .valid = 1, + .name = "STATUS_NIC2_ENG1" }, + { .fc_id = 654, .cpu_id = 503, .valid = 1, + .name = "STATUS_NIC3_ENG0" }, + { .fc_id = 655, .cpu_id = 504, .valid = 1, + .name = "STATUS_NIC3_ENG1" }, + { .fc_id = 656, .cpu_id = 505, .valid = 1, + .name = "STATUS_NIC4_ENG0" }, + { .fc_id = 657, .cpu_id = 506, .valid = 1, + .name = "STATUS_NIC4_ENG1" }, + { .fc_id = 658, .cpu_id = 507, .valid = 1, .name = "FIX_POWER_ENV_S" }, + { .fc_id = 659, .cpu_id = 508, .valid = 1, .name = "FIX_POWER_ENV_E" }, + { .fc_id = 660, .cpu_id = 509, .valid = 1, + .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 661, .cpu_id = 510, .valid = 1, + .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 662, .cpu_id = 511, .valid = 1, .name = "RAZWI_OR_ADC_SW" }, +}; + +#endif /* __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h new file mode 100644 index 000000000..c45cc7f4d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h @@ -0,0 +1,367 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_CORESIGHT_H +#define GAUDI_CORESIGHT_H + +enum gaudi_debug_stm_regs_index { + GAUDI_STM_FIRST = 0, + GAUDI_STM_MME0_ACC = GAUDI_STM_FIRST, + GAUDI_STM_MME0_SBAB, + GAUDI_STM_MME0_CTRL, + GAUDI_STM_MME1_ACC, + GAUDI_STM_MME1_SBAB, + GAUDI_STM_MME1_CTRL, + GAUDI_STM_MME2_ACC, + GAUDI_STM_MME2_SBAB, + GAUDI_STM_MME2_CTRL, + GAUDI_STM_MME3_ACC, + GAUDI_STM_MME3_SBAB, + GAUDI_STM_MME3_CTRL, + GAUDI_STM_DMA_IF_W_S, + GAUDI_STM_DMA_IF_E_S, + GAUDI_STM_DMA_IF_W_N, + GAUDI_STM_DMA_IF_E_N, + GAUDI_STM_CPU, + GAUDI_STM_DMA_CH_0_CS, + GAUDI_STM_DMA_CH_1_CS, + GAUDI_STM_DMA_CH_2_CS, + GAUDI_STM_DMA_CH_3_CS, + GAUDI_STM_DMA_CH_4_CS, + GAUDI_STM_DMA_CH_5_CS, + GAUDI_STM_DMA_CH_6_CS, + GAUDI_STM_DMA_CH_7_CS, + GAUDI_STM_PCIE, + GAUDI_STM_MMU_CS, + GAUDI_STM_PSOC, + GAUDI_STM_NIC0_0, + GAUDI_STM_NIC0_1, + GAUDI_STM_NIC1_0, + GAUDI_STM_NIC1_1, + GAUDI_STM_NIC2_0, + GAUDI_STM_NIC2_1, + GAUDI_STM_NIC3_0, + GAUDI_STM_NIC3_1, + GAUDI_STM_NIC4_0, + GAUDI_STM_NIC4_1, + GAUDI_STM_TPC0_EML, + GAUDI_STM_TPC1_EML, + GAUDI_STM_TPC2_EML, + GAUDI_STM_TPC3_EML, + GAUDI_STM_TPC4_EML, + GAUDI_STM_TPC5_EML, + GAUDI_STM_TPC6_EML, + GAUDI_STM_TPC7_EML, + GAUDI_STM_LAST = GAUDI_STM_TPC7_EML +}; + +enum gaudi_debug_etf_regs_index { + GAUDI_ETF_FIRST = 0, + GAUDI_ETF_MME0_ACC = GAUDI_ETF_FIRST, + GAUDI_ETF_MME0_SBAB, + GAUDI_ETF_MME0_CTRL, + GAUDI_ETF_MME1_ACC, + GAUDI_ETF_MME1_SBAB, + GAUDI_ETF_MME1_CTRL, + GAUDI_ETF_MME2_ACC, + GAUDI_ETF_MME2_SBAB, + GAUDI_ETF_MME2_CTRL, + GAUDI_ETF_MME3_ACC, + GAUDI_ETF_MME3_SBAB, + GAUDI_ETF_MME3_CTRL, + GAUDI_ETF_DMA_IF_W_S, + GAUDI_ETF_DMA_IF_E_S, + GAUDI_ETF_DMA_IF_W_N, + GAUDI_ETF_DMA_IF_E_N, + GAUDI_ETF_CPU_0, + GAUDI_ETF_CPU_1, + GAUDI_ETF_CPU_TRACE, + GAUDI_ETF_DMA_CH_0_CS, + GAUDI_ETF_DMA_CH_1_CS, + GAUDI_ETF_DMA_CH_2_CS, + GAUDI_ETF_DMA_CH_3_CS, + GAUDI_ETF_DMA_CH_4_CS, + GAUDI_ETF_DMA_CH_5_CS, + GAUDI_ETF_DMA_CH_6_CS, + GAUDI_ETF_DMA_CH_7_CS, + GAUDI_ETF_PCIE, + GAUDI_ETF_MMU_CS, + GAUDI_ETF_PSOC, + GAUDI_ETF_NIC0_0, + GAUDI_ETF_NIC0_1, + GAUDI_ETF_NIC1_0, + GAUDI_ETF_NIC1_1, + GAUDI_ETF_NIC2_0, + GAUDI_ETF_NIC2_1, + GAUDI_ETF_NIC3_0, + GAUDI_ETF_NIC3_1, + GAUDI_ETF_NIC4_0, + GAUDI_ETF_NIC4_1, + GAUDI_ETF_TPC0_EML, + GAUDI_ETF_TPC1_EML, + GAUDI_ETF_TPC2_EML, + GAUDI_ETF_TPC3_EML, + GAUDI_ETF_TPC4_EML, + GAUDI_ETF_TPC5_EML, + GAUDI_ETF_TPC6_EML, + GAUDI_ETF_TPC7_EML, + GAUDI_ETF_LAST = GAUDI_ETF_TPC7_EML +}; + +enum gaudi_debug_funnel_regs_index { + GAUDI_FUNNEL_FIRST = 0, + GAUDI_FUNNEL_MME0_ACC = GAUDI_FUNNEL_FIRST, + GAUDI_FUNNEL_MME1_ACC, + GAUDI_FUNNEL_MME2_ACC, + GAUDI_FUNNEL_MME3_ACC, + GAUDI_FUNNEL_SRAM_Y0_X0, + GAUDI_FUNNEL_SRAM_Y0_X1, + GAUDI_FUNNEL_SRAM_Y0_X2, + GAUDI_FUNNEL_SRAM_Y0_X3, + GAUDI_FUNNEL_SRAM_Y0_X4, + GAUDI_FUNNEL_SRAM_Y0_X5, + GAUDI_FUNNEL_SRAM_Y0_X6, + GAUDI_FUNNEL_SRAM_Y0_X7, + GAUDI_FUNNEL_SRAM_Y1_X0, + GAUDI_FUNNEL_SRAM_Y1_X1, + GAUDI_FUNNEL_SRAM_Y1_X2, + GAUDI_FUNNEL_SRAM_Y1_X3, + GAUDI_FUNNEL_SRAM_Y1_X4, + GAUDI_FUNNEL_SRAM_Y1_X5, + GAUDI_FUNNEL_SRAM_Y1_X6, + GAUDI_FUNNEL_SRAM_Y1_X7, + GAUDI_FUNNEL_SRAM_Y2_X0, + GAUDI_FUNNEL_SRAM_Y2_X1, + GAUDI_FUNNEL_SRAM_Y2_X2, + GAUDI_FUNNEL_SRAM_Y2_X3, + GAUDI_FUNNEL_SRAM_Y2_X4, + GAUDI_FUNNEL_SRAM_Y2_X5, + GAUDI_FUNNEL_SRAM_Y2_X6, + GAUDI_FUNNEL_SRAM_Y2_X7, + GAUDI_FUNNEL_SRAM_Y3_X0, + GAUDI_FUNNEL_SRAM_Y3_X1, + GAUDI_FUNNEL_SRAM_Y3_X2, + GAUDI_FUNNEL_SRAM_Y3_X4, + GAUDI_FUNNEL_SRAM_Y3_X3, + GAUDI_FUNNEL_SRAM_Y3_X5, + GAUDI_FUNNEL_SRAM_Y3_X6, + GAUDI_FUNNEL_SRAM_Y3_X7, + GAUDI_FUNNEL_SIF_0, + GAUDI_FUNNEL_SIF_1, + GAUDI_FUNNEL_SIF_2, + GAUDI_FUNNEL_SIF_3, + GAUDI_FUNNEL_SIF_4, + GAUDI_FUNNEL_SIF_5, + GAUDI_FUNNEL_SIF_6, + GAUDI_FUNNEL_SIF_7, + GAUDI_FUNNEL_NIF_0, + GAUDI_FUNNEL_NIF_1, + GAUDI_FUNNEL_NIF_2, + GAUDI_FUNNEL_NIF_3, + GAUDI_FUNNEL_NIF_4, + GAUDI_FUNNEL_NIF_5, + GAUDI_FUNNEL_NIF_6, + GAUDI_FUNNEL_NIF_7, + GAUDI_FUNNEL_DMA_IF_W_S, + GAUDI_FUNNEL_DMA_IF_E_S, + GAUDI_FUNNEL_DMA_IF_W_N, + GAUDI_FUNNEL_DMA_IF_E_N, + GAUDI_FUNNEL_CPU, + GAUDI_FUNNEL_NIC_TPC_W_S, + GAUDI_FUNNEL_NIC_TPC_E_S, + GAUDI_FUNNEL_NIC_TPC_W_N, + GAUDI_FUNNEL_NIC_TPC_E_N, + GAUDI_FUNNEL_PCIE, + GAUDI_FUNNEL_PSOC, + GAUDI_FUNNEL_NIC0, + GAUDI_FUNNEL_NIC1, + GAUDI_FUNNEL_NIC2, + GAUDI_FUNNEL_NIC3, + GAUDI_FUNNEL_NIC4, + GAUDI_FUNNEL_TPC0_EML, + GAUDI_FUNNEL_TPC1_EML, + GAUDI_FUNNEL_TPC2_EML, + GAUDI_FUNNEL_TPC3_EML, + GAUDI_FUNNEL_TPC4_EML, + GAUDI_FUNNEL_TPC5_EML, + GAUDI_FUNNEL_TPC6_EML, + GAUDI_FUNNEL_TPC7_EML, + GAUDI_FUNNEL_LAST = GAUDI_FUNNEL_TPC7_EML +}; + +enum gaudi_debug_bmon_regs_index { + GAUDI_BMON_FIRST = 0, + GAUDI_BMON_MME0_ACC_0 = GAUDI_BMON_FIRST, + GAUDI_BMON_MME0_SBAB_0, + GAUDI_BMON_MME0_SBAB_1, + GAUDI_BMON_MME0_CTRL_0, + GAUDI_BMON_MME0_CTRL_1, + GAUDI_BMON_MME1_ACC_0, + GAUDI_BMON_MME1_SBAB_0, + GAUDI_BMON_MME1_SBAB_1, + GAUDI_BMON_MME1_CTRL_0, + GAUDI_BMON_MME1_CTRL_1, + GAUDI_BMON_MME2_ACC_0, + GAUDI_BMON_MME2_SBAB_0, + GAUDI_BMON_MME2_SBAB_1, + GAUDI_BMON_MME2_CTRL_0, + GAUDI_BMON_MME2_CTRL_1, + GAUDI_BMON_MME3_ACC_0, + GAUDI_BMON_MME3_SBAB_0, + GAUDI_BMON_MME3_SBAB_1, + GAUDI_BMON_MME3_CTRL_0, + GAUDI_BMON_MME3_CTRL_1, + GAUDI_BMON_DMA_IF_W_S_SOB_WR, + GAUDI_BMON_DMA_IF_W_S_0_WR, + GAUDI_BMON_DMA_IF_W_S_0_RD, + GAUDI_BMON_DMA_IF_W_S_1_WR, + GAUDI_BMON_DMA_IF_W_S_1_RD, + GAUDI_BMON_DMA_IF_E_S_SOB_WR, + GAUDI_BMON_DMA_IF_E_S_0_WR, + GAUDI_BMON_DMA_IF_E_S_0_RD, + GAUDI_BMON_DMA_IF_E_S_1_WR, + GAUDI_BMON_DMA_IF_E_S_1_RD, + GAUDI_BMON_DMA_IF_W_N_SOB_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_RD, + GAUDI_BMON_DMA_IF_W_N_HBM1_WR, + GAUDI_BMON_DMA_IF_W_N_HBM1_RD, + GAUDI_BMON_DMA_IF_E_N_SOB_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_RD, + GAUDI_BMON_DMA_IF_E_N_HBM1_WR, + GAUDI_BMON_DMA_IF_E_N_HBM1_RD, + GAUDI_BMON_CPU_WR, + GAUDI_BMON_CPU_RD, + GAUDI_BMON_DMA_CH_0_0, + GAUDI_BMON_DMA_CH_0_1, + GAUDI_BMON_DMA_CH_1_0, + GAUDI_BMON_DMA_CH_1_1, + GAUDI_BMON_DMA_CH_2_0, + GAUDI_BMON_DMA_CH_2_1, + GAUDI_BMON_DMA_CH_3_0, + GAUDI_BMON_DMA_CH_3_1, + GAUDI_BMON_DMA_CH_4_0, + GAUDI_BMON_DMA_CH_4_1, + GAUDI_BMON_DMA_CH_5_0, + GAUDI_BMON_DMA_CH_5_1, + GAUDI_BMON_DMA_CH_6_0, + GAUDI_BMON_DMA_CH_6_1, + GAUDI_BMON_DMA_CH_7_0, + GAUDI_BMON_DMA_CH_7_1, + GAUDI_BMON_PCIE_MSTR_WR, + GAUDI_BMON_PCIE_MSTR_RD, + GAUDI_BMON_PCIE_SLV_WR, + GAUDI_BMON_PCIE_SLV_RD, + GAUDI_BMON_MMU_0, + GAUDI_BMON_MMU_1, + GAUDI_BMON_NIC0_0, + GAUDI_BMON_NIC0_1, + GAUDI_BMON_NIC0_2, + GAUDI_BMON_NIC0_3, + GAUDI_BMON_NIC0_4, + GAUDI_BMON_NIC1_0, + GAUDI_BMON_NIC1_1, + GAUDI_BMON_NIC1_2, + GAUDI_BMON_NIC1_3, + GAUDI_BMON_NIC1_4, + GAUDI_BMON_NIC2_0, + GAUDI_BMON_NIC2_1, + GAUDI_BMON_NIC2_2, + GAUDI_BMON_NIC2_3, + GAUDI_BMON_NIC2_4, + GAUDI_BMON_NIC3_0, + GAUDI_BMON_NIC3_1, + GAUDI_BMON_NIC3_2, + GAUDI_BMON_NIC3_3, + GAUDI_BMON_NIC3_4, + GAUDI_BMON_NIC4_0, + GAUDI_BMON_NIC4_1, + GAUDI_BMON_NIC4_2, + GAUDI_BMON_NIC4_3, + GAUDI_BMON_NIC4_4, + GAUDI_BMON_TPC0_EML_0, + GAUDI_BMON_TPC0_EML_1, + GAUDI_BMON_TPC0_EML_2, + GAUDI_BMON_TPC0_EML_3, + GAUDI_BMON_TPC1_EML_0, + GAUDI_BMON_TPC1_EML_1, + GAUDI_BMON_TPC1_EML_2, + GAUDI_BMON_TPC1_EML_3, + GAUDI_BMON_TPC2_EML_0, + GAUDI_BMON_TPC2_EML_1, + GAUDI_BMON_TPC2_EML_2, + GAUDI_BMON_TPC2_EML_3, + GAUDI_BMON_TPC3_EML_0, + GAUDI_BMON_TPC3_EML_1, + GAUDI_BMON_TPC3_EML_2, + GAUDI_BMON_TPC3_EML_3, + GAUDI_BMON_TPC4_EML_0, + GAUDI_BMON_TPC4_EML_1, + GAUDI_BMON_TPC4_EML_2, + GAUDI_BMON_TPC4_EML_3, + GAUDI_BMON_TPC5_EML_0, + GAUDI_BMON_TPC5_EML_1, + GAUDI_BMON_TPC5_EML_2, + GAUDI_BMON_TPC5_EML_3, + GAUDI_BMON_TPC6_EML_0, + GAUDI_BMON_TPC6_EML_1, + GAUDI_BMON_TPC6_EML_2, + GAUDI_BMON_TPC6_EML_3, + GAUDI_BMON_TPC7_EML_0, + GAUDI_BMON_TPC7_EML_1, + GAUDI_BMON_TPC7_EML_2, + GAUDI_BMON_TPC7_EML_3, + GAUDI_BMON_LAST = GAUDI_BMON_TPC7_EML_3 +}; + +enum gaudi_debug_spmu_regs_index { + GAUDI_SPMU_FIRST = 0, + GAUDI_SPMU_MME0_ACC = GAUDI_SPMU_FIRST, + GAUDI_SPMU_MME0_SBAB, + GAUDI_SPMU_MME0_CTRL, + GAUDI_SPMU_MME1_ACC, + GAUDI_SPMU_MME1_SBAB, + GAUDI_SPMU_MME1_CTRL, + GAUDI_SPMU_MME2_MME2_ACC, + GAUDI_SPMU_MME2_SBAB, + GAUDI_SPMU_MME2_CTRL, + GAUDI_SPMU_MME3_ACC, + GAUDI_SPMU_MME3_SBAB, + GAUDI_SPMU_MME3_CTRL, + GAUDI_SPMU_DMA_CH_0_CS, + GAUDI_SPMU_DMA_CH_1_CS, + GAUDI_SPMU_DMA_CH_2_CS, + GAUDI_SPMU_DMA_CH_3_CS, + GAUDI_SPMU_DMA_CH_4_CS, + GAUDI_SPMU_DMA_CH_5_CS, + GAUDI_SPMU_DMA_CH_6_CS, + GAUDI_SPMU_DMA_CH_7_CS, + GAUDI_SPMU_PCIE, + GAUDI_SPMU_MMU_CS, + GAUDI_SPMU_NIC0_0, + GAUDI_SPMU_NIC0_1, + GAUDI_SPMU_NIC1_0, + GAUDI_SPMU_NIC1_1, + GAUDI_SPMU_NIC2_0, + GAUDI_SPMU_NIC2_1, + GAUDI_SPMU_NIC3_0, + GAUDI_SPMU_NIC3_1, + GAUDI_SPMU_NIC4_0, + GAUDI_SPMU_NIC4_1, + GAUDI_SPMU_TPC0_EML, + GAUDI_SPMU_TPC1_EML, + GAUDI_SPMU_TPC2_EML, + GAUDI_SPMU_TPC3_EML, + GAUDI_SPMU_TPC4_EML, + GAUDI_SPMU_TPC5_EML, + GAUDI_SPMU_TPC6_EML, + GAUDI_SPMU_TPC7_EML, + GAUDI_SPMU_LAST = GAUDI_SPMU_TPC7_EML +}; + +#endif /* GAUDI_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h new file mode 100644 index 000000000..2dba02757 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_FW_IF_H +#define GAUDI_FW_IF_H + +#define GAUDI_EVENT_QUEUE_MSI_IDX 8 +#define GAUDI_NIC_PORT1_MSI_IDX 10 +#define GAUDI_NIC_PORT3_MSI_IDX 12 +#define GAUDI_NIC_PORT5_MSI_IDX 14 +#define GAUDI_NIC_PORT7_MSI_IDX 16 +#define GAUDI_NIC_PORT9_MSI_IDX 18 + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8MB in HBM */ + +/* HBM thermal delta in [Deg] added to composite (CTemp) */ +#define HBM_TEMP_ADJUST_COEFF 6 + +enum gaudi_nic_axi_error { + RXB, + RXE, + TXS, + TXE, + QPC_RESP, + NON_AXI_ERR, + TMR, +}; + +/* + * struct eq_nic_sei_event - describes an AXI error cause. + * @axi_error_cause: one of the events defined in enum gaudi_nic_axi_error. + * @id: can be either 0 or 1, to further describe unit with interrupt cause + * (i.e. TXE0 or TXE1). + * @pad[6]: padding structure to 64bit. + */ +struct eq_nic_sei_event { + __u8 axi_error_cause; + __u8 id; + __u8 pad[6]; +}; + +/* + * struct gaudi_nic_status - describes the status of a NIC port. + * @port: NIC port index. + * @bad_format_cnt: e.g. CRC. + * @responder_out_of_sequence_psn_cnt: e.g NAK. + * @high_ber_reinit_cnt: link reinit due to high BER. + * @correctable_err_cnt: e.g. bit-flip. + * @uncorrectable_err_cnt: e.g. MAC errors. + * @retraining_cnt: re-training counter. + * @up: is port up. + * @pcs_link: has PCS link. + * @phy_ready: is PHY ready. + * @auto_neg: is Autoneg enabled. + * @timeout_retransmission_cnt: timeout retransmission events + * @high_ber_cnt: high ber events + */ +struct gaudi_nic_status { + __u32 port; + __u32 bad_format_cnt; + __u32 responder_out_of_sequence_psn_cnt; + __u32 high_ber_reinit; + __u32 correctable_err_cnt; + __u32 uncorrectable_err_cnt; + __u32 retraining_cnt; + __u8 up; + __u8 pcs_link; + __u8 phy_ready; + __u8 auto_neg; + __u32 timeout_retransmission_cnt; + __u32 high_ber_cnt; +}; + +struct gaudi_cold_rst_data { + union { + struct { + u32 spsram_init_done : 1; + u32 reserved : 31; + }; + __le32 data; + }; +}; + +#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */ + +#endif /* GAUDI_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h new file mode 100644 index 000000000..880c57b26 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -0,0 +1,470 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_MASKS_H_ +#define GAUDI_MASKS_H_ + +#include "asic_reg/gaudi_regs.h" + +/* Useful masks for bits in various registers */ +#define PCI_DMA_QMAN_ENABLE (\ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF))) + +#define QMAN_EXTERNAL_MAKE_TRUSTED (\ + (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) + +#define QMAN_INTERNAL_MAKE_TRUSTED (\ + (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) + +#define HBM_DMA_QMAN_ENABLE (\ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) + +#define QMAN_MME_ENABLE (\ + (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) + +#define QMAN_TPC_ENABLE (\ + (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) + +#define NIC_QMAN_ENABLE (\ + (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF))) + +#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ + (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) + +#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ + (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) + +#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) + +#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) + +#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) + +#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) + +#define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) + +#define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) + +#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA)) + +/* RESET registers configuration */ +#define CFG_RST_L_PSOC_MASK BIT_MASK(0) +#define CFG_RST_L_PCIE_MASK BIT_MASK(1) +#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2) +#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3) +#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4) +#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5) +#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6) +#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7) +#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8) +#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9) +#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10) +#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11) +#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12) +#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13) +#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14) +#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15) +#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16) +#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17) +#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18) +#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19) +#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20) + +#define CFG_RST_L_IF_1_MASK BIT_MASK(21) +#define CFG_RST_L_IF_0_MASK BIT_MASK(22) +#define CFG_RST_L_IF_2_MASK BIT_MASK(23) +#define CFG_RST_L_IF_3_MASK BIT_MASK(24) +#define CFG_RST_L_IF_MASK GENMASK(24, 21) + +#define CFG_RST_L_TPC_0_MASK BIT_MASK(25) +#define CFG_RST_L_TPC_1_MASK BIT_MASK(26) +#define CFG_RST_L_TPC_2_MASK BIT_MASK(27) +#define CFG_RST_L_TPC_3_MASK BIT_MASK(28) +#define CFG_RST_L_TPC_4_MASK BIT_MASK(29) +#define CFG_RST_L_TPC_5_MASK BIT_MASK(30) +#define CFG_RST_L_TPC_6_MASK BIT_MASK(31) +#define CFG_RST_L_TPC_MASK GENMASK(31, 25) + +#define CFG_RST_H_TPC_7_MASK BIT_MASK(0) + +#define CFG_RST_H_MME_0_MASK BIT_MASK(1) +#define CFG_RST_H_MME_1_MASK BIT_MASK(2) +#define CFG_RST_H_MME_2_MASK BIT_MASK(3) +#define CFG_RST_H_MME_3_MASK BIT_MASK(4) +#define CFG_RST_H_MME_MASK GENMASK(4, 1) + +#define CFG_RST_H_HBM_0_MASK BIT_MASK(5) +#define CFG_RST_H_HBM_1_MASK BIT_MASK(6) +#define CFG_RST_H_HBM_2_MASK BIT_MASK(7) +#define CFG_RST_H_HBM_3_MASK BIT_MASK(8) +#define CFG_RST_H_HBM_MASK GENMASK(8, 5) + +#define CFG_RST_H_NIC_0_MASK BIT_MASK(9) +#define CFG_RST_H_NIC_1_MASK BIT_MASK(10) +#define CFG_RST_H_NIC_2_MASK BIT_MASK(11) +#define CFG_RST_H_NIC_3_MASK BIT_MASK(12) +#define CFG_RST_H_NIC_4_MASK BIT_MASK(13) +#define CFG_RST_H_NIC_MASK GENMASK(13, 9) + +#define CFG_RST_H_SM_0_MASK BIT_MASK(14) +#define CFG_RST_H_SM_1_MASK BIT_MASK(15) +#define CFG_RST_H_SM_2_MASK BIT_MASK(16) +#define CFG_RST_H_SM_3_MASK BIT_MASK(17) +#define CFG_RST_H_SM_MASK GENMASK(17, 14) + +#define CFG_RST_H_DMA_0_MASK BIT_MASK(18) +#define CFG_RST_H_DMA_1_MASK BIT_MASK(19) +#define CFG_RST_H_DMA_MASK GENMASK(19, 18) + +#define CFG_RST_H_CPU_MASK BIT_MASK(20) +#define CFG_RST_H_MMU_MASK BIT_MASK(21) + +#define UNIT_RST_L_PSOC_SHIFT 0 +#define UNIT_RST_L_PCIE_SHIFT 1 +#define UNIT_RST_L_PCIE_IF_SHIFT 2 +#define UNIT_RST_L_HBM_S_PLL_SHIFT 3 +#define UNIT_RST_L_TPC_S_PLL_SHIFT 4 +#define UNIT_RST_L_MME_S_PLL_SHIFT 5 +#define UNIT_RST_L_CPU_PLL_SHIFT 6 +#define UNIT_RST_L_PCIE_PLL_SHIFT 7 +#define UNIT_RST_L_NIC_S_PLL_SHIFT 8 +#define UNIT_RST_L_HBM_N_PLL_SHIFT 9 +#define UNIT_RST_L_TPC_N_PLL_SHIFT 10 +#define UNIT_RST_L_MME_N_PLL_SHIFT 11 +#define UNIT_RST_L_NIC_N_PLL_SHIFT 12 +#define UNIT_RST_L_DMA_W_PLL_SHIFT 13 +#define UNIT_RST_L_SIF_W_PLL_SHIFT 14 +#define UNIT_RST_L_MESH_W_PLL_SHIFT 15 +#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16 +#define UNIT_RST_L_DMA_E_PLL_SHIFT 17 +#define UNIT_RST_L_SIF_E_PLL_SHIFT 18 +#define UNIT_RST_L_MESH_E_PLL_SHIFT 19 +#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20 +#define UNIT_RST_L_TPC_0_SHIFT 21 +#define UNIT_RST_L_TPC_1_SHIFT 22 +#define UNIT_RST_L_TPC_2_SHIFT 23 +#define UNIT_RST_L_TPC_3_SHIFT 24 +#define UNIT_RST_L_TPC_4_SHIFT 25 +#define UNIT_RST_L_TPC_5_SHIFT 26 +#define UNIT_RST_L_TPC_6_SHIFT 27 +#define UNIT_RST_L_TPC_7_SHIFT 28 +#define UNIT_RST_L_MME_0_SHIFT 29 +#define UNIT_RST_L_MME_1_SHIFT 30 +#define UNIT_RST_L_MME_2_SHIFT 31 + +#define UNIT_RST_H_MME_3_SHIFT 0 +#define UNIT_RST_H_HBM_0_SHIFT 1 +#define UNIT_RST_H_HBM_1_SHIFT 2 +#define UNIT_RST_H_HBM_2_SHIFT 3 +#define UNIT_RST_H_HBM_3_SHIFT 4 +#define UNIT_RST_H_NIC_0_SHIFT 5 +#define UNIT_RST_H_NIC_1_SHIFT 6 +#define UNIT_RST_H_NIC_2_SHIFT 7 +#define UNIT_RST_H_NIC_3_SHIFT 8 +#define UNIT_RST_H_NIC_4_SHIFT 9 +#define UNIT_RST_H_SM_0_SHIFT 10 +#define UNIT_RST_H_SM_1_SHIFT 11 +#define UNIT_RST_H_SM_2_SHIFT 12 +#define UNIT_RST_H_SM_3_SHIFT 13 +#define UNIT_RST_H_IF_0_SHIFT 14 +#define UNIT_RST_H_IF_1_SHIFT 15 +#define UNIT_RST_H_IF_2_SHIFT 16 +#define UNIT_RST_H_IF_3_SHIFT 17 +#define UNIT_RST_H_DMA_0_SHIFT 18 +#define UNIT_RST_H_DMA_1_SHIFT 19 +#define UNIT_RST_H_CPU_SHIFT 20 +#define UNIT_RST_H_MMU_SHIFT 21 + +#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \ + (1 << UNIT_RST_H_HBM_1_SHIFT) | \ + (1 << UNIT_RST_H_HBM_2_SHIFT) | \ + (1 << UNIT_RST_H_HBM_3_SHIFT)) + +#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \ + (1 << UNIT_RST_H_NIC_1_SHIFT) | \ + (1 << UNIT_RST_H_NIC_2_SHIFT) | \ + (1 << UNIT_RST_H_NIC_3_SHIFT) | \ + (1 << UNIT_RST_H_NIC_4_SHIFT)) + +#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \ + (1 << UNIT_RST_H_SM_1_SHIFT) | \ + (1 << UNIT_RST_H_SM_2_SHIFT) | \ + (1 << UNIT_RST_H_SM_3_SHIFT)) + +#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \ + (1 << UNIT_RST_H_MME_1_SHIFT) | \ + (1 << UNIT_RST_H_MME_2_SHIFT)) + +#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT) + +#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \ + (1 << UNIT_RST_L_IF_1_SHIFT) | \ + (1 << UNIT_RST_L_IF_2_SHIFT) | \ + (1 << UNIT_RST_L_IF_3_SHIFT)) + +#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \ + (1 << UNIT_RST_L_TPC_1_SHIFT) | \ + (1 << UNIT_RST_L_TPC_2_SHIFT) | \ + (1 << UNIT_RST_L_TPC_3_SHIFT) | \ + (1 << UNIT_RST_L_TPC_4_SHIFT) | \ + (1 << UNIT_RST_L_TPC_5_SHIFT) | \ + (1 << UNIT_RST_L_TPC_6_SHIFT) | \ + (1 << UNIT_RST_L_TPC_7_SHIFT)) + +/* CPU_CA53_CFG_ARM_RST_CONTROL */ +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 + +#define CPU_RESET_ASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define CPU_RESET_CORE0_DEASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +/* QM_IDLE_MASK is valid for all engines QM idle check */ +#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CP_IDLE_MASK) + +/* CGM_IDLE_MASK is valid for all engines CGM idle check */ +#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK + +#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT)) + +#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 +#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 +#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000 + +#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK) + +#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \ + ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \ + (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK)) + +#define IS_DMA_IDLE(dma_core_sts0) \ + !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK) + +#define IS_TPC_IDLE(tpc_cfg_sts) \ + (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK) + +#define IS_MME_IDLE(mme_arch_sts) \ + (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) + +enum axi_id { + AXI_ID_MME, + AXI_ID_TPC, + AXI_ID_DMA, + AXI_ID_NIC, /* Local NIC */ + AXI_ID_PCI, + AXI_ID_CPU, + AXI_ID_PSOC, + AXI_ID_MMU, + AXI_ID_NIC_FT /* Feed-Through NIC */ +}; + +/* RAZWI initiator ID is built from the location in the chip and the AXI ID */ + +#define RAZWI_INITIATOR_AXI_ID_SHIFT 20 +#define RAZWI_INITIATOR_AXI_ID_MASK 0xF +#define RAZWI_INITIATOR_X_SHIFT 24 +#define RAZWI_INITIATOR_X_MASK 0xF +#define RAZWI_INITIATOR_Y_SHIFT 28 +#define RAZWI_INITIATOR_Y_MASK 0x7 + +#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \ + (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \ + RAZWI_INITIATOR_AXI_ID_SHIFT) + +#define RAZWI_INITIATOR_ID_X_Y(x, y) \ + ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ + (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) + +#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1) +#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1) +#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1) +#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1) +#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1) +#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1) +#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1) +#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \ + RAZWI_INITIATOR_ID_X_Y(8, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4) +#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6) +#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6) +#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6) +#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6) +#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6) +#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6) +#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6) +#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6) + +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 +#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 + +/* STLB_CACHE_INV */ +#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +#define MME_ACC_ACC_STALL_R_SHIFT 0 +#define MME_SBAB_SB_STALL_R_SHIFT 0 + +#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700 +#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000 + +#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0 +#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0 + +/* DMA_IF_HBM_CRED_EN */ +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0 +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2 + +#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0 + +/* MMU_UP_PAGE_ERROR_CAPTURE */ +#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_UP_ACCESS_ERROR_CAPTURE */ +#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +#define QM_ARB_ERR_MSG_EN_MASK (\ + QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ + QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ + QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) + +#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 +#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 + +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT 1 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT 8 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT 16 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT 17 +#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000 +#define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000 + +#endif /* GAUDI_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h new file mode 100644 index 000000000..66fc083a7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2017-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_PACKETS_H +#define GAUDI_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_LOAD_AND_EXE = 0xF, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GAUDI_PKT_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_CTL_EB_SHIFT 29 +#define GAUDI_PKT_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_CTL_RB_SHIFT 30 +#define GAUDI_PKT_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_CTL_MB_SHIFT 31 +#define GAUDI_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct gaudi_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[]; /* data starts here */ +}; + +#define GAUDI_PKT_LONG_CTL_OP_SHIFT 20 +#define GAUDI_PKT_LONG_CTL_OP_MASK 0x00300000 + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x00007FFF + +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT 31 +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF + +#define GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT 8 +#define GAUDI_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00 + +#define GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT 16 +#define GAUDI_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000 + +#define GAUDI_PKT_SHORT_CTL_ADDR_SHIFT 0 +#define GAUDI_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF + +#define GAUDI_PKT_SHORT_CTL_OP_SHIFT 20 +#define GAUDI_PKT_SHORT_CTL_OP_MASK 0x00300000 + +#define GAUDI_PKT_SHORT_CTL_BASE_SHIFT 22 +#define GAUDI_PKT_SHORT_CTL_BASE_MASK 0x00C00000 + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT 0 +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F + +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16 +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000 + +#define GAUDI_PKT_FENCE_CFG_ID_SHIFT 30 +#define GAUDI_PKT_FENCE_CFG_ID_MASK 0xC0000000 + +#define GAUDI_PKT_FENCE_CTL_PRED_SHIFT 0 +#define GAUDI_PKT_FENCE_CTL_PRED_MASK 0x0000001F + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK 0x00000001 + +#define GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT 3 +#define GAUDI_PKT_LIN_DMA_CTL_LIN_MASK 0x00000008 + +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4 +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010 + +#define GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_DST_ADDR_MASK 0x00FFFFFFFFFFFFFFull + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_arb_point { + __le32 cfg; + __le32 ctl; +}; + +struct packet_repeat { + __le32 cfg; + __le32 ctl; +}; + +struct packet_wait { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_SHIFT 0 +#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK 0x00000001 + +struct packet_load_and_exe { + __le32 cfg; + __le32 ctl; + __le64 src_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GAUDI_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h new file mode 100644 index 000000000..92f25c2ae --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_REG_MAP_H_ +#define GAUDI_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 +#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 +#define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 +#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 + +#endif /* GAUDI_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h b/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h new file mode 100644 index 000000000..2cf30c206 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 HabanaLabs Ltd. + * All Rights Reserved. + */ + +#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__ +#define __GAUDI2_ARC_COMMON_PACKETS_H__ + +/* + * CPU IDs for each ARC CPUs + */ + +#define CPU_ID_SCHED_ARC0 0 /* FARM_ARC0 */ +#define CPU_ID_SCHED_ARC1 1 /* FARM_ARC1 */ +#define CPU_ID_SCHED_ARC2 2 /* FARM_ARC2 */ +#define CPU_ID_SCHED_ARC3 3 /* FARM_ARC3 */ +/* Dcore1 MME Engine ARC instance used as scheduler */ +#define CPU_ID_SCHED_ARC4 4 /* DCORE1_MME0 */ +/* Dcore3 MME Engine ARC instance used as scheduler */ +#define CPU_ID_SCHED_ARC5 5 /* DCORE3_MME0 */ + +#define CPU_ID_TPC_QMAN_ARC0 6 /* DCORE0_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC1 7 /* DCORE0_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC2 8 /* DCORE0_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC3 9 /* DCORE0_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC4 10 /* DCORE0_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC5 11 /* DCORE0_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC6 12 /* DCORE1_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC7 13 /* DCORE1_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC8 14 /* DCORE1_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC9 15 /* DCORE1_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC10 16 /* DCORE1_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC11 17 /* DCORE1_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC12 18 /* DCORE2_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC13 19 /* DCORE2_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC14 20 /* DCORE2_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC15 21 /* DCORE2_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC16 22 /* DCORE2_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC17 23 /* DCORE2_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC18 24 /* DCORE3_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC19 25 /* DCORE3_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC20 26 /* DCORE3_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC21 27 /* DCORE3_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC22 28 /* DCORE3_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC23 29 /* DCORE3_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC24 30 /* DCORE0_TPC6 - Never present */ + +#define CPU_ID_MME_QMAN_ARC0 31 /* DCORE0_MME0 */ +#define CPU_ID_MME_QMAN_ARC1 32 /* DCORE2_MME0 */ + +#define CPU_ID_EDMA_QMAN_ARC0 33 /* DCORE0_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC1 34 /* DCORE0_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC2 35 /* DCORE1_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC3 36 /* DCORE1_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC4 37 /* DCORE2_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC5 38 /* DCORE2_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC6 39 /* DCORE3_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC7 40 /* DCORE3_EDMA1 */ + +#define CPU_ID_PDMA_QMAN_ARC0 41 /* DCORE0_PDMA0 */ +#define CPU_ID_PDMA_QMAN_ARC1 42 /* DCORE0_PDMA1 */ + +#define CPU_ID_ROT_QMAN_ARC0 43 /* ROT0 */ +#define CPU_ID_ROT_QMAN_ARC1 44 /* ROT1 */ + +#define CPU_ID_NIC_QMAN_ARC0 45 /* NIC0_0 */ +#define CPU_ID_NIC_QMAN_ARC1 46 /* NIC0_1 */ +#define CPU_ID_NIC_QMAN_ARC2 47 /* NIC1_0 */ +#define CPU_ID_NIC_QMAN_ARC3 48 /* NIC1_1 */ +#define CPU_ID_NIC_QMAN_ARC4 49 /* NIC2_0 */ +#define CPU_ID_NIC_QMAN_ARC5 50 /* NIC2_1 */ +#define CPU_ID_NIC_QMAN_ARC6 51 /* NIC3_0 */ +#define CPU_ID_NIC_QMAN_ARC7 52 /* NIC3_1 */ +#define CPU_ID_NIC_QMAN_ARC8 53 /* NIC4_0 */ +#define CPU_ID_NIC_QMAN_ARC9 54 /* NIC4_1 */ +#define CPU_ID_NIC_QMAN_ARC10 55 /* NIC5_0 */ +#define CPU_ID_NIC_QMAN_ARC11 56 /* NIC5_1 */ +#define CPU_ID_NIC_QMAN_ARC12 57 /* NIC6_0 */ +#define CPU_ID_NIC_QMAN_ARC13 58 /* NIC6_1 */ +#define CPU_ID_NIC_QMAN_ARC14 59 /* NIC7_0 */ +#define CPU_ID_NIC_QMAN_ARC15 60 /* NIC7_1 */ +#define CPU_ID_NIC_QMAN_ARC16 61 /* NIC8_0 */ +#define CPU_ID_NIC_QMAN_ARC17 62 /* NIC8_1 */ +#define CPU_ID_NIC_QMAN_ARC18 63 /* NIC9_0 */ +#define CPU_ID_NIC_QMAN_ARC19 64 /* NIC9_1 */ +#define CPU_ID_NIC_QMAN_ARC20 65 /* NIC10_0 */ +#define CPU_ID_NIC_QMAN_ARC21 66 /* NIC10_1 */ +#define CPU_ID_NIC_QMAN_ARC22 67 /* NIC11_0 */ +#define CPU_ID_NIC_QMAN_ARC23 68 /* NIC11_1 */ + +#define CPU_ID_MAX 69 +#define CPU_ID_SCHED_MAX 6 + +#define CPU_ID_ALL 0xFE +#define CPU_ID_INVALID 0xFF + +enum arc_regions_t { + ARC_REGION0_UNSED = 0, + /* + * Extension registers + * None + */ + ARC_REGION1_SRAM = 1, + /* + * Extension registers + * AUX_SRAM_LSB_ADDR + * AUX_SRAM_MSB_ADDR + * ARC Address: 0x1000_0000 + */ + ARC_REGION2_CFG = 2, + /* + * Extension registers + * AUX_CFG_LSB_ADDR + * AUX_CFG_MSB_ADDR + * ARC Address: 0x2000_0000 + */ + ARC_REGION3_GENERAL = 3, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_0 + * AUX_GENERAL_PURPOSE_MSB_ADDR_0 + * ARC Address: 0x3000_0000 + */ + ARC_REGION4_HBM0_FW = 4, + /* + * Extension registers + * AUX_HBM0_LSB_ADDR + * AUX_HBM0_MSB_ADDR + * AUX_HBM0_OFFSET + * ARC Address: 0x4000_0000 + */ + ARC_REGION5_HBM1_GC_DATA = 5, + /* + * Extension registers + * AUX_HBM1_LSB_ADDR + * AUX_HBM1_MSB_ADDR + * AUX_HBM1_OFFSET + * ARC Address: 0x5000_0000 + */ + ARC_REGION6_HBM2_GC_DATA = 6, + /* + * Extension registers + * AUX_HBM2_LSB_ADDR + * AUX_HBM2_MSB_ADDR + * AUX_HBM2_OFFSET + * ARC Address: 0x6000_0000 + */ + ARC_REGION7_HBM3_GC_DATA = 7, + /* + * Extension registers + * AUX_HBM3_LSB_ADDR + * AUX_HBM3_MSB_ADDR + * AUX_HBM3_OFFSET + * ARC Address: 0x7000_0000 + */ + ARC_REGION8_DCCM = 8, + /* + * Extension registers + * None + * ARC Address: 0x8000_0000 + */ + ARC_REGION9_PCIE = 9, + /* + * Extension registers + * AUX_PCIE_LSB_ADDR + * AUX_PCIE_MSB_ADDR + * ARC Address: 0x9000_0000 + */ + ARC_REGION10_GENERAL = 10, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_1 + * AUX_GENERAL_PURPOSE_MSB_ADDR_1 + * ARC Address: 0xA000_0000 + */ + ARC_REGION11_GENERAL = 11, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_2 + * AUX_GENERAL_PURPOSE_MSB_ADDR_2 + * ARC Address: 0xB000_0000 + */ + ARC_REGION12_GENERAL = 12, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_3 + * AUX_GENERAL_PURPOSE_MSB_ADDR_3 + * ARC Address: 0xC000_0000 + */ + ARC_REGION13_GENERAL = 13, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_4 + * AUX_GENERAL_PURPOSE_MSB_ADDR_4 + * ARC Address: 0xD000_0000 + */ + ARC_REGION14_GENERAL = 14, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_5 + * AUX_GENERAL_PURPOSE_MSB_ADDR_5 + * ARC Address: 0xE000_0000 + */ + ARC_REGION15_LBU = 15 + /* + * Extension registers + * None + * ARC Address: 0xF000_0000 + */ +}; + +#endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h new file mode 100644 index 000000000..1974df13b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h @@ -0,0 +1,567 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_ACP_ENG + * (Prototype: ARC_ACP_ENG) + ***************************************** + */ + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0 0x4E8F000 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_1 0x4E8F004 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_2 0x4E8F008 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_3 0x4E8F00C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_4 0x4E8F010 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_5 0x4E8F014 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_6 0x4E8F018 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_7 0x4E8F01C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_8 0x4E8F020 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_9 0x4E8F024 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_10 0x4E8F028 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_11 0x4E8F02C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_12 0x4E8F030 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_13 0x4E8F034 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_14 0x4E8F038 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_15 0x4E8F03C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_16 0x4E8F040 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_17 0x4E8F044 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_18 0x4E8F048 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_19 0x4E8F04C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_20 0x4E8F050 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_21 0x4E8F054 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_22 0x4E8F058 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_23 0x4E8F05C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_24 0x4E8F060 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_25 0x4E8F064 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_26 0x4E8F068 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_27 0x4E8F06C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_28 0x4E8F070 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_29 0x4E8F074 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_30 0x4E8F078 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_31 0x4E8F07C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_32 0x4E8F080 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_33 0x4E8F084 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_34 0x4E8F088 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_35 0x4E8F08C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_36 0x4E8F090 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_37 0x4E8F094 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_38 0x4E8F098 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_39 0x4E8F09C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_40 0x4E8F0A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_41 0x4E8F0A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_42 0x4E8F0A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_43 0x4E8F0AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_44 0x4E8F0B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_45 0x4E8F0B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_46 0x4E8F0B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_47 0x4E8F0BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_48 0x4E8F0C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_49 0x4E8F0C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_50 0x4E8F0C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_51 0x4E8F0CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_52 0x4E8F0D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_53 0x4E8F0D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_54 0x4E8F0D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_55 0x4E8F0DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_56 0x4E8F0E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_57 0x4E8F0E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_58 0x4E8F0E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_59 0x4E8F0EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_60 0x4E8F0F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_61 0x4E8F0F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_62 0x4E8F0F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_63 0x4E8F0FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_0 0x4E8F100 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_1 0x4E8F104 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_2 0x4E8F108 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_3 0x4E8F10C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_4 0x4E8F110 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_5 0x4E8F114 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_6 0x4E8F118 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_7 0x4E8F11C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_8 0x4E8F120 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_9 0x4E8F124 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_10 0x4E8F128 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_11 0x4E8F12C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_12 0x4E8F130 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_13 0x4E8F134 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_14 0x4E8F138 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_15 0x4E8F13C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_16 0x4E8F140 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_17 0x4E8F144 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_18 0x4E8F148 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_19 0x4E8F14C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_20 0x4E8F150 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_21 0x4E8F154 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_22 0x4E8F158 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_23 0x4E8F15C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_24 0x4E8F160 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_25 0x4E8F164 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_26 0x4E8F168 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_27 0x4E8F16C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_28 0x4E8F170 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_29 0x4E8F174 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_30 0x4E8F178 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_31 0x4E8F17C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_32 0x4E8F180 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_33 0x4E8F184 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_34 0x4E8F188 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_35 0x4E8F18C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_36 0x4E8F190 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_37 0x4E8F194 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_38 0x4E8F198 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_39 0x4E8F19C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_40 0x4E8F1A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_41 0x4E8F1A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_42 0x4E8F1A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_43 0x4E8F1AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_44 0x4E8F1B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_45 0x4E8F1B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_46 0x4E8F1B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_47 0x4E8F1BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_48 0x4E8F1C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_49 0x4E8F1C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_50 0x4E8F1C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_51 0x4E8F1CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_52 0x4E8F1D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_53 0x4E8F1D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_54 0x4E8F1D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_55 0x4E8F1DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_56 0x4E8F1E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_57 0x4E8F1E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_58 0x4E8F1E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_59 0x4E8F1EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_60 0x4E8F1F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_61 0x4E8F1F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_62 0x4E8F1F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_63 0x4E8F1FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_0 0x4E8F200 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_1 0x4E8F204 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_2 0x4E8F208 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_3 0x4E8F20C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_4 0x4E8F210 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_5 0x4E8F214 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_6 0x4E8F218 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_7 0x4E8F21C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_8 0x4E8F220 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_9 0x4E8F224 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_10 0x4E8F228 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_11 0x4E8F22C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_12 0x4E8F230 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_13 0x4E8F234 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_14 0x4E8F238 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_15 0x4E8F23C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_16 0x4E8F240 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_17 0x4E8F244 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_18 0x4E8F248 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_19 0x4E8F24C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_20 0x4E8F250 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_21 0x4E8F254 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_22 0x4E8F258 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_23 0x4E8F25C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_24 0x4E8F260 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_25 0x4E8F264 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_26 0x4E8F268 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_27 0x4E8F26C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_28 0x4E8F270 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_29 0x4E8F274 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_30 0x4E8F278 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_31 0x4E8F27C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_32 0x4E8F280 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_33 0x4E8F284 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_34 0x4E8F288 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_35 0x4E8F28C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_36 0x4E8F290 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_37 0x4E8F294 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_38 0x4E8F298 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_39 0x4E8F29C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_40 0x4E8F2A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_41 0x4E8F2A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_42 0x4E8F2A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_43 0x4E8F2AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_44 0x4E8F2B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_45 0x4E8F2B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_46 0x4E8F2B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_47 0x4E8F2BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_48 0x4E8F2C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_49 0x4E8F2C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_50 0x4E8F2C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_51 0x4E8F2CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_52 0x4E8F2D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_53 0x4E8F2D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_54 0x4E8F2D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_55 0x4E8F2DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_56 0x4E8F2E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_57 0x4E8F2E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_58 0x4E8F2E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_59 0x4E8F2EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_60 0x4E8F2F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_61 0x4E8F2F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_62 0x4E8F2F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_63 0x4E8F2FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_0 0x4E8F300 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_1 0x4E8F304 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_2 0x4E8F308 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_3 0x4E8F30C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_4 0x4E8F310 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_5 0x4E8F314 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_6 0x4E8F318 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_7 0x4E8F31C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_8 0x4E8F320 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_9 0x4E8F324 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_10 0x4E8F328 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_11 0x4E8F32C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_12 0x4E8F330 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_13 0x4E8F334 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_14 0x4E8F338 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_15 0x4E8F33C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_16 0x4E8F340 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_17 0x4E8F344 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_18 0x4E8F348 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_19 0x4E8F34C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_20 0x4E8F350 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_21 0x4E8F354 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_22 0x4E8F358 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_23 0x4E8F35C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_24 0x4E8F360 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_25 0x4E8F364 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_26 0x4E8F368 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_27 0x4E8F36C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_28 0x4E8F370 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_29 0x4E8F374 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_30 0x4E8F378 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_31 0x4E8F37C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_32 0x4E8F380 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_33 0x4E8F384 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_34 0x4E8F388 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_35 0x4E8F38C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_36 0x4E8F390 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_37 0x4E8F394 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_38 0x4E8F398 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_39 0x4E8F39C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_40 0x4E8F3A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_41 0x4E8F3A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_42 0x4E8F3A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_43 0x4E8F3AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_44 0x4E8F3B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_45 0x4E8F3B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_46 0x4E8F3B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_47 0x4E8F3BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_48 0x4E8F3C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_49 0x4E8F3C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_50 0x4E8F3C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_51 0x4E8F3CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_52 0x4E8F3D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_53 0x4E8F3D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_54 0x4E8F3D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_55 0x4E8F3DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_56 0x4E8F3E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_57 0x4E8F3E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_58 0x4E8F3E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_59 0x4E8F3EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_60 0x4E8F3F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_61 0x4E8F3F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_62 0x4E8F3F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_63 0x4E8F3FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x4E8F400 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x4E8F404 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x4E8F408 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x4E8F40C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x4E8F410 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x4E8F414 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x4E8F418 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x4E8F41C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x4E8F420 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x4E8F424 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x4E8F428 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x4E8F42C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x4E8F430 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x4E8F434 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x4E8F438 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG 0x4E8F43C + +#endif /* ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h new file mode 100644 index 000000000..fc2c52af6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h @@ -0,0 +1,819 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ +#define ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +/* ARC_FARM_ARC0_AUX_RUN_HALT_REQ */ +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_SHIFT 1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_RUN_HALT_ACK */ +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_SHIFT 4 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_SHIFT 8 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_SHIFT 12 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_SHIFT 16 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_SHIFT 17 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_SHIFT 20 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_MASK 0x100000 + +/* ARC_FARM_ARC0_AUX_RST_VEC_ADDR */ +#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_MASK 0x3FFFFF + +/* ARC_FARM_ARC0_AUX_DBG_MODE */ +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_MASK 0x10 +#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_MASK 0x100 +#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_SHIFT 12 +#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_SHIFT 16 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_MASK 0x10000 + +/* ARC_FARM_ARC0_AUX_CLUSTER_NUM */ +#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_ARC_NUM */ +#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_WAKE_UP_EVENT */ +#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE */ +#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CTI_AP_STS */ +#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL */ +#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_ARC_RST */ +#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_MASK 0x10 + +/* ARC_FARM_ARC0_AUX_ARC_RST_REQ */ +#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_MASK 0x3F + +/* ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_CFG_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM0_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM1_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM2_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM3_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_CONTEXT_ID */ +#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CID_OFFSET */ +#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_SW_INTR */ +#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_IRQ_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE */ +#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN */ +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_MASK 0x1 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_SHIFT 1 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK */ +#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_SHIFT 1 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR */ +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR */ +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_SCRATCHPAD */ +#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_MASK 0xF +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_MASK 0xF0 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_MASK 0xF00 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_MASK 0xF000 + +/* ARC_FARM_ARC0_AUX_CBU_LOCK_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_MASK 0x3 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_MASK 0x30 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_MASK 0x300 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_MASK 0x3000 + +/* ARC_FARM_ARC0_AUX_CBU_PROT_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_MASK 0x7 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_MASK 0x70 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_MASK 0x700 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_MASK 0x7000 + +/* ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING */ +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_MASK 0xFF +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_MASK 0xFF00 + +/* ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN */ +#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK */ +#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT */ +#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID */ +#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_MASK 0x7F + +/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_MASK 0xF +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_MASK 0xF0 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_MASK 0xF00 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_MASK 0xF000 + +/* ARC_FARM_ARC0_AUX_LBU_LOCK_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_MASK 0x3 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_MASK 0x30 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_MASK 0x300 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_MASK 0x3000 + +/* ARC_FARM_ARC0_AUX_LBU_PROT_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_MASK 0x7 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_MASK 0x70 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_MASK 0x700 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_MASK 0x7000 + +/* ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING */ +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_MASK 0xFF +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_MASK 0xFF00 + +/* ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN */ +#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK */ +#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT */ +#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID */ +#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK */ +#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK */ +#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_MASK 0xFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_MASK 0xFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT */ +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_MASK 0xF +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_SHIFT 4 +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG */ +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_MASK 0x1F + +/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT */ +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_MASK 0x1F + +/* ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_AUX2APB_PROT */ +#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN */ +#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 */ +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 */ +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_ARC_REGION_CFG */ +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_SHIFT 12 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_SHIFT 16 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_MASK 0x70000 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_SHIFT 20 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_MASK 0x700000 + +/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR */ +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR */ +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_SHIFT 1 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_MASK 0x3E + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN */ +#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK 0x1 + +#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h new file mode 100644 index 000000000..5345b5faa --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmARC_FARM_ARC0_AUX_RUN_HALT_REQ 0x4E88100 + +#define mmARC_FARM_ARC0_AUX_RUN_HALT_ACK 0x4E88104 + +#define mmARC_FARM_ARC0_AUX_RST_VEC_ADDR 0x4E88108 + +#define mmARC_FARM_ARC0_AUX_DBG_MODE 0x4E8810C + +#define mmARC_FARM_ARC0_AUX_CLUSTER_NUM 0x4E88110 + +#define mmARC_FARM_ARC0_AUX_ARC_NUM 0x4E88114 + +#define mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT 0x4E88118 + +#define mmARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE 0x4E8811C + +#define mmARC_FARM_ARC0_AUX_CTI_AP_STS 0x4E88120 + +#define mmARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL 0x4E88124 + +#define mmARC_FARM_ARC0_AUX_ARC_RST 0x4E88128 + +#define mmARC_FARM_ARC0_AUX_ARC_RST_REQ 0x4E8812C + +#define mmARC_FARM_ARC0_AUX_SRAM_LSB_ADDR 0x4E88130 + +#define mmARC_FARM_ARC0_AUX_SRAM_MSB_ADDR 0x4E88134 + +#define mmARC_FARM_ARC0_AUX_PCIE_LSB_ADDR 0x4E88138 + +#define mmARC_FARM_ARC0_AUX_PCIE_MSB_ADDR 0x4E8813C + +#define mmARC_FARM_ARC0_AUX_CFG_LSB_ADDR 0x4E88140 + +#define mmARC_FARM_ARC0_AUX_CFG_MSB_ADDR 0x4E88144 + +#define mmARC_FARM_ARC0_AUX_HBM0_LSB_ADDR 0x4E88150 + +#define mmARC_FARM_ARC0_AUX_HBM0_MSB_ADDR 0x4E88154 + +#define mmARC_FARM_ARC0_AUX_HBM1_LSB_ADDR 0x4E88158 + +#define mmARC_FARM_ARC0_AUX_HBM1_MSB_ADDR 0x4E8815C + +#define mmARC_FARM_ARC0_AUX_HBM2_LSB_ADDR 0x4E88160 + +#define mmARC_FARM_ARC0_AUX_HBM2_MSB_ADDR 0x4E88164 + +#define mmARC_FARM_ARC0_AUX_HBM3_LSB_ADDR 0x4E88168 + +#define mmARC_FARM_ARC0_AUX_HBM3_MSB_ADDR 0x4E8816C + +#define mmARC_FARM_ARC0_AUX_HBM0_OFFSET 0x4E88170 + +#define mmARC_FARM_ARC0_AUX_HBM1_OFFSET 0x4E88174 + +#define mmARC_FARM_ARC0_AUX_HBM2_OFFSET 0x4E88178 + +#define mmARC_FARM_ARC0_AUX_HBM3_OFFSET 0x4E8817C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E88180 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E88184 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E88188 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E8818C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E88190 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E88194 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E88198 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E8819C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E881A0 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E881A4 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E881A8 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E881AC + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E881B0 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E881B4 + +#define mmARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR 0x4E881B8 + +#define mmARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR 0x4E881BC + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_0 0x4E881C0 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_1 0x4E881C4 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_2 0x4E881C8 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_3 0x4E881CC + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_4 0x4E881D0 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_5 0x4E881D4 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_6 0x4E881D8 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_7 0x4E881DC + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_0 0x4E881E0 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_1 0x4E881E4 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_2 0x4E881E8 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_3 0x4E881EC + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_4 0x4E881F0 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_5 0x4E881F4 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_6 0x4E881F8 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_7 0x4E881FC + +#define mmARC_FARM_ARC0_AUX_SW_INTR_0 0x4E88200 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_1 0x4E88204 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_2 0x4E88208 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_3 0x4E8820C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_4 0x4E88210 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_5 0x4E88214 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_6 0x4E88218 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_7 0x4E8821C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_8 0x4E88220 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_9 0x4E88224 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_10 0x4E88228 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_11 0x4E8822C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_12 0x4E88230 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_13 0x4E88234 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_14 0x4E88238 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_15 0x4E8823C + +#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_0 0x4E88280 + +#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_1 0x4E88284 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS 0x4E88290 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR 0x4E88294 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK 0x4E88298 + +#define mmARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE 0x4E8829C + +#define mmARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN 0x4E882A0 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK 0x4E882A4 + +#define mmARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E882A8 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_STS 0x4E882B0 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR 0x4E882B4 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK 0x4E882B8 + +#define mmARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR 0x4E882BC + +#define mmARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME 0x4E882C0 + +#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR 0x4E882C4 + +#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME 0x4E882C8 + +#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR 0x4E882CC + +#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME 0x4E882D0 + +#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E882E0 + +#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E882E4 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP 0x4E882E8 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP 0x4E882EC + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E882F0 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E882F4 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_0 0x4E88300 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_1 0x4E88304 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_2 0x4E88308 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_3 0x4E8830C + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_4 0x4E88310 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_5 0x4E88314 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_6 0x4E88318 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_7 0x4E8831C + +#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT 0x4E88320 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT 0x4E88324 + +#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT 0x4E88328 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT 0x4E8832C + +#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT 0x4E88330 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT 0x4E88334 + +#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT 0x4E88338 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT 0x4E8833C + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR 0x4E88350 + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN 0x4E88354 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR 0x4E88358 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN 0x4E8835C + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR 0x4E88360 + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E88364 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR 0x4E88368 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E8836C + +#define mmARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR 0x4E88370 + +#define mmARC_FARM_ARC0_AUX_CBU_LOCK_OVR 0x4E88374 + +#define mmARC_FARM_ARC0_AUX_CBU_PROT_OVR 0x4E88378 + +#define mmARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING 0x4E8837C + +#define mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN 0x4E88380 + +#define mmARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK 0x4E88384 + +#define mmARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT 0x4E8838C + +#define mmARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID 0x4E88390 + +#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR 0x4E88400 + +#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN 0x4E88404 + +#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR 0x4E88408 + +#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN 0x4E8840C + +#define mmARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR 0x4E88420 + +#define mmARC_FARM_ARC0_AUX_LBU_LOCK_OVR 0x4E88424 + +#define mmARC_FARM_ARC0_AUX_LBU_PROT_OVR 0x4E88428 + +#define mmARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING 0x4E8842C + +#define mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN 0x4E88430 + +#define mmARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK 0x4E88434 + +#define mmARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT 0x4E8843C + +#define mmARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID 0x4E88440 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E88500 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E88504 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E88508 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E8850C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E88510 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E88514 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E88518 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E8851C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_0 0x4E88520 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_1 0x4E88524 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_2 0x4E88528 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_3 0x4E8852C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_4 0x4E88530 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_5 0x4E88534 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_6 0x4E88538 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_7 0x4E8853C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_0 0x4E88540 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_1 0x4E88544 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_2 0x4E88548 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_3 0x4E8854C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_4 0x4E88550 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_5 0x4E88554 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_6 0x4E88558 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_7 0x4E8855C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_0 0x4E88560 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_1 0x4E88564 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_2 0x4E88568 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_3 0x4E8856C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_4 0x4E88570 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_5 0x4E88574 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_6 0x4E88578 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_7 0x4E8857C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E88580 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E88584 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E88588 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E8858C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E88590 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E88594 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E88598 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E8859C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E885A0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E885A4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E885A8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E885AC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E885B0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E885B4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E885B8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E885BC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E885C0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E885C4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E885C8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E885CC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E885D0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E885D4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E885D8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E885DC + +#define mmARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E885E0 + +#define mmARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E885E4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN 0x4E88620 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG 0x4E88624 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG 0x4E88628 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT 0x4E88630 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER 0x4E88634 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST 0x4E88638 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK 0x4E8863C + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE 0x4E88640 + +#define mmARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT 0x4E88644 + +#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E88648 + +#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E8864C + +#define mmARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E88650 + +#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E88654 + +#define mmARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI 0x4E88658 + +#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E8865C + +#define mmARC_FARM_ARC0_AUX_AUX2APB_PROT 0x4E88700 + +#define mmARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN 0x4E88704 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E88708 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E8870C + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E88710 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E88714 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E88718 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E8871C + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E88720 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E88724 + +#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E88728 + +#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E8872C + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E88730 + +#define mmARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E88734 + +#define mmARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E88738 + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E8873C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN 0x4E88740 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E88750 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E88754 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E88758 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E8875C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E88760 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E88764 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E88768 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E8876C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E88770 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E88774 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E88778 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E8877C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E88780 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E88784 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E88788 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E8878C + +#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E88790 + +#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E88794 + +#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP 0x4E88798 + +#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP 0x4E8879C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 0x4E88800 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_1 0x4E88804 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_2 0x4E88808 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_3 0x4E8880C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_4 0x4E88810 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_5 0x4E88814 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_6 0x4E88818 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_7 0x4E8881C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_8 0x4E88820 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_9 0x4E88824 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_10 0x4E88828 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_11 0x4E8882C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_12 0x4E88830 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_13 0x4E88834 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_14 0x4E88838 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_15 0x4E8883C + +#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E88840 + +#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E88844 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E88848 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E8884C + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN 0x4E88850 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION 0x4E88854 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E88900 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL 0x4E88904 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E88908 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR 0x4E8890C + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER 0x4E88910 + +#define mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN 0x4E88920 + +#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h new file mode 100644 index 000000000..bde077eed --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_DUP_ENG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID 0x4E89900 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP 0x4E89904 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x4E89908 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_NO_SNOOP 0x4E8990C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x4E89910 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x4E89914 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_QOS 0x4E89918 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RSVD 0x4E8991C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x4E89920 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_CORE 0x4E89924 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_E2E_COORD 0x4E89928 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x4E89930 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x4E89934 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x4E89938 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x4E8993C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_COORD 0x4E89940 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_LOCK 0x4E89944 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_RSVD 0x4E89948 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD 0x4E8994C + +#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h new file mode 100644 index 000000000..491af75c1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_DUP_ENG + * (Prototype: ARC_DUP_ENG) + ***************************************** + */ + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x4E89000 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x4E89004 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x4E89008 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x4E8900C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x4E89010 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x4E89014 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x4E89018 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x4E8901C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x4E89020 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x4E89024 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x4E89028 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x4E8902C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x4E89030 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x4E89034 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x4E89038 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x4E8903C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x4E89040 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x4E89044 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x4E89048 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x4E8904C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x4E89050 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x4E89054 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x4E89058 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x4E8905C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x4E89060 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_0 0x4E89064 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_1 0x4E89068 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_2 0x4E8906C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_3 0x4E89070 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x4E89074 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x4E89078 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x4E8907C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x4E89080 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x4E89084 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x4E89088 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x4E8908C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x4E89090 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x4E89094 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x4E89098 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x4E8909C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x4E890A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x4E890A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x4E890A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x4E890AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x4E890B0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x4E890B4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x4E890B8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x4E890BC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x4E890C0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x4E890C4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x4E890C8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x4E890CC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x4E890D0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x4E890D4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x4E890D8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x4E890DC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x4E890E0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x4E890E4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x4E890E8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x4E890EC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x4E890F0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x4E890F4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x4E890F8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x4E890FC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x4E89100 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x4E89104 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x4E89108 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x4E8910C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x4E89110 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x4E89114 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x4E89118 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x4E8911C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x4E89120 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x4E89124 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x4E89128 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x4E8912C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x4E89130 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x4E89134 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x4E89138 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x4E8913C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x4E89140 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_MASK 0x4E89200 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_MASK 0x4E89204 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_MASK 0x4E89208 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_MASK 0x4E8920C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_MASK 0x4E89210 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_MASK 0x4E89214 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_0 0x4E89218 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_1 0x4E8921C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_2 0x4E89220 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_3 0x4E89224 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_4 0x4E89228 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_5 0x4E8922C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_6 0x4E89230 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_7 0x4E89234 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x4E89238 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x4E8923C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x4E89240 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x4E89244 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x4E89248 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x4E8924C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x4E89250 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x4E89254 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x4E89258 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x4E8925C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x4E89260 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x4E89264 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x4E89268 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x4E8926C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x4E89288 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x4E8928C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x4E89290 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x4E89294 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x4E89298 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x4E8929C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x4E892A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x4E892A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x4E892A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x4E892AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x4E892B0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x4E892B4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x4E892B8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x4E892BC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x4E892C0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x4E892C4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x4E892C8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x4E892CC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GENERAL_CFG 0x4E892D0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_BP_CFG 0x4E892D4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x4E892D8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x4E892DC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x4E892E0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x4E892E4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x4E892E8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x4E892EC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x4E892F0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x4E892F4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x4E892F8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x4E892FC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x4E89300 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x4E89304 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x4E89308 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x4E8930C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x4E894A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x4E894A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x4E894A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_STS 0x4E894AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x4E894B0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_0 0x4E894B4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_1 0x4E894B8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_2 0x4E894BC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_3 0x4E894C0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_4 0x4E894C4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_5 0x4E894C8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_6 0x4E894CC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_7 0x4E894D0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_8 0x4E894D4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_9 0x4E894D8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_10 0x4E894DC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_11 0x4E894E0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_12 0x4E894E4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_13 0x4E894E8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_14 0x4E894EC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_15 0x4E894F0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_16 0x4E894F4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_17 0x4E894F8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_18 0x4E894FC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_19 0x4E89500 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_20 0x4E89504 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_21 0x4E89508 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_22 0x4E8950C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_23 0x4E89510 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_24 0x4E89514 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_25 0x4E89518 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_26 0x4E8951C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_27 0x4E89520 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_28 0x4E89524 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_29 0x4E89528 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_30 0x4E8952C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_31 0x4E89530 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_32 0x4E89534 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_33 0x4E89538 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_34 0x4E8953C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_35 0x4E89540 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_36 0x4E89544 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_37 0x4E89548 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_38 0x4E8954C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_39 0x4E89550 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_40 0x4E89554 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_41 0x4E89558 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_42 0x4E8955C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_43 0x4E89560 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_44 0x4E89564 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_45 0x4E89568 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_46 0x4E8956C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_47 0x4E89570 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_48 0x4E89574 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_49 0x4E89578 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_50 0x4E8957C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_51 0x4E89580 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_52 0x4E89584 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_53 0x4E89588 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_54 0x4E8958C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_55 0x4E89590 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_56 0x4E89594 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_57 0x4E89598 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_58 0x4E8959C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_59 0x4E895A0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_60 0x4E895A4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_61 0x4E895A8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_62 0x4E895AC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_63 0x4E895B0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_0 0x4E895B4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_1 0x4E895B8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_2 0x4E895BC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_3 0x4E895C0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_4 0x4E895C4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_5 0x4E895C8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_6 0x4E895CC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_7 0x4E895D0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_8 0x4E895D4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_9 0x4E895D8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_10 0x4E895DC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_11 0x4E895E0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_12 0x4E895E4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_13 0x4E895E8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_14 0x4E895EC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_15 0x4E895F0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_16 0x4E895F4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_17 0x4E895F8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_18 0x4E895FC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_19 0x4E89600 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_20 0x4E89604 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_21 0x4E89608 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_22 0x4E8960C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_23 0x4E89610 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_24 0x4E89614 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_25 0x4E89618 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_26 0x4E8961C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_27 0x4E89620 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_28 0x4E89624 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_29 0x4E89628 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_30 0x4E8962C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_31 0x4E89630 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_32 0x4E89634 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_33 0x4E89638 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_34 0x4E8963C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_35 0x4E89640 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_36 0x4E89644 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_37 0x4E89648 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_38 0x4E8964C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_39 0x4E89650 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_40 0x4E89654 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_41 0x4E89658 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_42 0x4E8965C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_43 0x4E89660 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_44 0x4E89664 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_45 0x4E89668 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_46 0x4E8966C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_47 0x4E89670 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_48 0x4E89674 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_49 0x4E89678 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_50 0x4E8967C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_51 0x4E89680 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_52 0x4E89684 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_53 0x4E89688 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_54 0x4E8968C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_55 0x4E89690 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_56 0x4E89694 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_57 0x4E89698 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_58 0x4E8969C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_59 0x4E896A0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_60 0x4E896A4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_61 0x4E896A8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_62 0x4E896AC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63 0x4E896B0 + +#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h new file mode 100644 index 000000000..12d6a124a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_ASID */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT 16 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_QOS */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_MASK 0xF +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_MASK 0x70 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_CORE */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD */ +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_MASK 0x1F +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_SHIFT 8 +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_MASK 0xF00 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_COORD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_MASK 0x1 + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h new file mode 100644 index 000000000..23f9d2df5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_ASID 0x4E8B800 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP 0x4E8B804 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER 0x4E8B808 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP 0x4E8B80C + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION 0x4E8B810 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC 0x4E8B814 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_QOS 0x4E8B818 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RSVD 0x4E8B81C + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE 0x4E8B820 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_CORE 0x4E8B824 + +#define mmARC_FARM_KDMA_CTX_AXUSER_E2E_COORD 0x4E8B828 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO 0x4E8B830 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI 0x4E8B834 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO 0x4E8B838 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI 0x4E8B83C + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_COORD 0x4E8B840 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_LOCK 0x4E8B844 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_RSVD 0x4E8B848 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_OVRD 0x4E8B84C + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h new file mode 100644 index 000000000..bee4de0b2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +/* ARC_FARM_KDMA_CTX_RATE_LIM_TKN */ +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_SHIFT 0 +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_MASK 0xFF +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_SHIFT 16 +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_MASK 0xFF0000 + +/* ARC_FARM_KDMA_CTX_PWRLP */ +#define ARC_FARM_KDMA_CTX_PWRLP_DATA_SHIFT 0 +#define ARC_FARM_KDMA_CTX_PWRLP_DATA_MASK 0xFF +#define ARC_FARM_KDMA_CTX_PWRLP_EN_SHIFT 8 +#define ARC_FARM_KDMA_CTX_PWRLP_EN_MASK 0x100 + +/* ARC_FARM_KDMA_CTX_TE_NUMROWS */ +#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_IDX */ +#define ARC_FARM_KDMA_CTX_IDX_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_IDX_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_CTX_IDX_INC */ +#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_MASK 0xFF + +/* ARC_FARM_KDMA_CTX_CTRL */ +#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_SHIFT 0 +#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_MASK 0x1 +#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_MASK 0x30 +#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_SHIFT 8 +#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_MASK 0x100 +#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_SHIFT 9 +#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_MASK 0x200 +#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_SHIFT 12 +#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_MASK 0x1000 + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_0 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_1 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_1 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_2 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_2 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_3 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_3 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_4 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_4 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_1 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_1 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_2 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_2 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_3 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_3 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_4 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_4 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI */ +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO */ +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_WDATA */ +#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_OFFSET_LO */ +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_OFFSET_HI */ +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_OFFSET_LO */ +#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_OFFSET_HI */ +#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_BASE_LO */ +#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_BASE_HI */ +#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_BASE_LO */ +#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_BASE_HI */ +#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_0 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_COMMIT */ +#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_SHIFT 0 +#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK 0x1 +#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_SHIFT 1 +#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_MASK 0x6 +#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_SHIFT 4 +#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK 0x10 +#define ARC_FARM_KDMA_CTX_COMMIT_BF16_SHIFT 6 +#define ARC_FARM_KDMA_CTX_COMMIT_BF16_MASK 0x40 +#define ARC_FARM_KDMA_CTX_COMMIT_FP16_SHIFT 7 +#define ARC_FARM_KDMA_CTX_COMMIT_FP16_MASK 0x80 +#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_SHIFT 8 +#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_MASK 0x100 +#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_SHIFT 9 +#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_MASK 0x200 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_SHIFT 10 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_MASK 0x400 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_SHIFT 11 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_MASK 0x800 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_SHIFT 12 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_MASK 0x1000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_SHIFT 13 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_MASK 0x2000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_SHIFT 14 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_MASK 0x4000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_SHIFT 15 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_MASK 0x8000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_SHIFT 16 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_MASK 0x10000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_SHIFT 17 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_MASK 0x20000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_SHIFT 18 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_MASK 0x40000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_SHIFT 19 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_MASK 0x80000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_SHIFT 20 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_MASK 0x100000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_SHIFT 21 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_MASK 0x200000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_SHIFT 22 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_MASK 0x400000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_SHIFT 23 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_MASK 0x800000 +#define ARC_FARM_KDMA_CTX_COMMIT_LIN_SHIFT 31 +#define ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK 0x80000000 + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h new file mode 100644 index 000000000..b9f09e819 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CTX_RATE_LIM_TKN 0x4E8B860 + +#define mmARC_FARM_KDMA_CTX_PWRLP 0x4E8B864 + +#define mmARC_FARM_KDMA_CTX_TE_NUMROWS 0x4E8B868 + +#define mmARC_FARM_KDMA_CTX_IDX 0x4E8B86C + +#define mmARC_FARM_KDMA_CTX_IDX_INC 0x4E8B870 + +#define mmARC_FARM_KDMA_CTX_CTRL 0x4E8B874 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_0 0x4E8B878 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_1 0x4E8B87C + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_1 0x4E8B880 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_2 0x4E8B884 + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_2 0x4E8B888 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_3 0x4E8B88C + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_3 0x4E8B890 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_4 0x4E8B894 + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_4 0x4E8B898 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_1 0x4E8B89C + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_1 0x4E8B8A0 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_2 0x4E8B8A4 + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_2 0x4E8B8A8 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_3 0x4E8B8AC + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_3 0x4E8B8B0 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_4 0x4E8B8B4 + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_4 0x4E8B8B8 + +#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI 0x4E8B8BC + +#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO 0x4E8B8C0 + +#define mmARC_FARM_KDMA_CTX_WR_COMP_WDATA 0x4E8B8C4 + +#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_LO 0x4E8B8C8 + +#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_HI 0x4E8B8CC + +#define mmARC_FARM_KDMA_CTX_DST_OFFSET_LO 0x4E8B8D0 + +#define mmARC_FARM_KDMA_CTX_DST_OFFSET_HI 0x4E8B8D4 + +#define mmARC_FARM_KDMA_CTX_SRC_BASE_LO 0x4E8B8D8 + +#define mmARC_FARM_KDMA_CTX_SRC_BASE_HI 0x4E8B8DC + +#define mmARC_FARM_KDMA_CTX_DST_BASE_LO 0x4E8B8E0 + +#define mmARC_FARM_KDMA_CTX_DST_BASE_HI 0x4E8B8E4 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_0 0x4E8B8E8 + +#define mmARC_FARM_KDMA_CTX_COMMIT 0x4E8B8EC + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h new file mode 100644 index 000000000..d6dd2c066 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_KDMA_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmARC_FARM_KDMA_KDMA_CGM_CFG 0x4E8BE00 + +#define mmARC_FARM_KDMA_KDMA_CGM_STS 0x4E8BE04 + +#define mmARC_FARM_KDMA_KDMA_CGM_CFG1 0x4E8BE08 + +#endif /* ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h new file mode 100644 index 000000000..5903dbace --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* ARC_FARM_KDMA_CFG_0 */ +#define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0 +#define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1 + +/* ARC_FARM_KDMA_CFG_1 */ +#define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0 +#define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1 +#define ARC_FARM_KDMA_CFG_1_FLUSH_SHIFT 1 +#define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2 + +/* ARC_FARM_KDMA_PROT */ +#define ARC_FARM_KDMA_PROT_VAL_SHIFT 0 +#define ARC_FARM_KDMA_PROT_VAL_MASK 0x1 +#define ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT 1 +#define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2 + +/* ARC_FARM_KDMA_CKG */ +#define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0 +#define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1 +#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define ARC_FARM_KDMA_CKG_TE_SHIFT 2 +#define ARC_FARM_KDMA_CKG_TE_MASK 0x4 + +/* ARC_FARM_KDMA_RD_GLBL */ +#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* ARC_FARM_KDMA_RD_HBW_MAX_SIZE */ +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_RD_HBW_ARCACHE */ +#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_RD_HBW_INFLIGHTS */ +#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* ARC_FARM_KDMA_RD_LBW_MAX_SIZE */ +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_RD_LBW_ARCACHE */ +#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_RD_LBW_INFLIGHTS */ +#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_WR_HBW_MAX_AWID */ +#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* ARC_FARM_KDMA_WR_HBW_AWCACHE */ +#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_WR_HBW_INFLIGHTS */ +#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_WR_LBW_MAX_AWID */ +#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* ARC_FARM_KDMA_WR_LBW_AWCACHE */ +#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_WR_LBW_INFLIGHTS */ +#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* ARC_FARM_KDMA_WR_COMP_AWUSER */ +#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERR_CFG */ +#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* ARC_FARM_KDMA_ERR_CAUSE */ +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* ARC_FARM_KDMA_ERRMSG_ADDR_LO */ +#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERRMSG_ADDR_HI */ +#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERRMSG_WDATA */ +#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS0 */ +#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_SHIFT 0 +#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_MASK 0x7FFF +#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_SHIFT 16 +#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define ARC_FARM_KDMA_STS0_BUSY_SHIFT 31 +#define ARC_FARM_KDMA_STS0_BUSY_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS1 */ +#define ARC_FARM_KDMA_STS1_IS_HALT_SHIFT 0 +#define ARC_FARM_KDMA_STS1_IS_HALT_MASK 0x1 + +/* ARC_FARM_KDMA_STS_RD_CTX_SEL */ +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* ARC_FARM_KDMA_STS_RD_CTX_SIZE */ +#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_BASE_LO */ +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_BASE_HI */ +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_ID */ +#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO */ +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI */ +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR */ +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_CTX_SEL */ +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* ARC_FARM_KDMA_STS_WR_CTX_SIZE */ +#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_BASE_LO */ +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_BASE_HI */ +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_ID */ +#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO */ +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI */ +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR */ +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_PWRLP_CFG */ +#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define ARC_FARM_KDMA_PWRLP_CFG_CLR_SHIFT 4 +#define ARC_FARM_KDMA_PWRLP_CFG_CLR_MASK 0x10 + +/* ARC_FARM_KDMA_PWRLP_STS */ +#define ARC_FARM_KDMA_PWRLP_STS_RLVL_SHIFT 0 +#define ARC_FARM_KDMA_PWRLP_STS_RLVL_MASK 0x7F +#define ARC_FARM_KDMA_PWRLP_STS_WLVL_SHIFT 8 +#define ARC_FARM_KDMA_PWRLP_STS_WLVL_MASK 0x7F00 +#define ARC_FARM_KDMA_PWRLP_STS_RCNT_SHIFT 16 +#define ARC_FARM_KDMA_PWRLP_STS_RCNT_MASK 0x7F0000 +#define ARC_FARM_KDMA_PWRLP_STS_WCNT_SHIFT 23 +#define ARC_FARM_KDMA_PWRLP_STS_WCNT_MASK 0x3F800000 +#define ARC_FARM_KDMA_PWRLP_STS_RFULL_SHIFT 30 +#define ARC_FARM_KDMA_PWRLP_STS_RFULL_MASK 0x40000000 +#define ARC_FARM_KDMA_PWRLP_STS_WFULL_SHIFT 31 +#define ARC_FARM_KDMA_PWRLP_STS_WFULL_MASK 0x80000000 + +/* ARC_FARM_KDMA_DBG_DESC_CNT */ +#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_DBG_STS */ +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_SHIFT 6 +#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_MASK 0x40 +#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_SHIFT 7 +#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_MASK 0x80 +#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_SHIFT 9 +#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_MASK 0x200 +#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_SHIFT 10 +#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_MASK 0x400 +#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_SHIFT 11 +#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* ARC_FARM_KDMA_DBG_BUF_STS */ +#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_DBG_RD_DESC_ID */ +#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_DBG_WR_DESC_ID */ +#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_APB_DMA_LBW_BASE */ +#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE */ +#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG */ +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* ARC_FARM_KDMA_DBG_APB_ENABLER */ +#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_SHIFT 0 +#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* ARC_FARM_KDMA_L2H_CMPR_LO */ +#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_SHIFT 20 +#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* ARC_FARM_KDMA_L2H_CMPR_HI */ +#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_L2H_MASK_LO */ +#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_SHIFT 20 +#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* ARC_FARM_KDMA_L2H_MASK_HI */ +#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_IDLE_IND_MASK */ +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_SHIFT 0 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_MASK 0x1 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_SHIFT 1 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_MASK 0x2 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_SHIFT 3 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_MASK 0x8 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* ARC_FARM_KDMA_APB_ENABLER */ +#define ARC_FARM_KDMA_APB_ENABLER_DIS_SHIFT 0 +#define ARC_FARM_KDMA_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_ARC_FARM_KDMA_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h new file mode 100644 index 000000000..e312cf810 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CFG_0 0x4E8B000 + +#define mmARC_FARM_KDMA_CFG_1 0x4E8B004 + +#define mmARC_FARM_KDMA_PROT 0x4E8B008 + +#define mmARC_FARM_KDMA_CKG 0x4E8B00C + +#define mmARC_FARM_KDMA_RD_GLBL 0x4E8B07C + +#define mmARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND 0x4E8B080 + +#define mmARC_FARM_KDMA_RD_HBW_MAX_SIZE 0x4E8B084 + +#define mmARC_FARM_KDMA_RD_HBW_ARCACHE 0x4E8B088 + +#define mmARC_FARM_KDMA_RD_HBW_INFLIGHTS 0x4E8B090 + +#define mmARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG 0x4E8B094 + +#define mmARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND 0x4E8B0C0 + +#define mmARC_FARM_KDMA_RD_LBW_MAX_SIZE 0x4E8B0C4 + +#define mmARC_FARM_KDMA_RD_LBW_ARCACHE 0x4E8B0C8 + +#define mmARC_FARM_KDMA_RD_LBW_INFLIGHTS 0x4E8B0D0 + +#define mmARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG 0x4E8B0D4 + +#define mmARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND 0x4E8B100 + +#define mmARC_FARM_KDMA_WR_HBW_MAX_AWID 0x4E8B104 + +#define mmARC_FARM_KDMA_WR_HBW_AWCACHE 0x4E8B108 + +#define mmARC_FARM_KDMA_WR_HBW_INFLIGHTS 0x4E8B10C + +#define mmARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG 0x4E8B110 + +#define mmARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND 0x4E8B140 + +#define mmARC_FARM_KDMA_WR_LBW_MAX_AWID 0x4E8B144 + +#define mmARC_FARM_KDMA_WR_LBW_AWCACHE 0x4E8B148 + +#define mmARC_FARM_KDMA_WR_LBW_INFLIGHTS 0x4E8B14C + +#define mmARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG 0x4E8B150 + +#define mmARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND 0x4E8B180 + +#define mmARC_FARM_KDMA_WR_COMP_AWUSER 0x4E8B184 + +#define mmARC_FARM_KDMA_ERR_CFG 0x4E8B300 + +#define mmARC_FARM_KDMA_ERR_CAUSE 0x4E8B304 + +#define mmARC_FARM_KDMA_ERRMSG_ADDR_LO 0x4E8B308 + +#define mmARC_FARM_KDMA_ERRMSG_ADDR_HI 0x4E8B30C + +#define mmARC_FARM_KDMA_ERRMSG_WDATA 0x4E8B310 + +#define mmARC_FARM_KDMA_STS0 0x4E8B380 + +#define mmARC_FARM_KDMA_STS1 0x4E8B384 + +#define mmARC_FARM_KDMA_STS_RD_CTX_SEL 0x4E8B400 + +#define mmARC_FARM_KDMA_STS_RD_CTX_SIZE 0x4E8B404 + +#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_LO 0x4E8B408 + +#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_HI 0x4E8B40C + +#define mmARC_FARM_KDMA_STS_RD_CTX_ID 0x4E8B410 + +#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO 0x4E8B414 + +#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI 0x4E8B418 + +#define mmARC_FARM_KDMA_STS_RD_LB_AXI_ADDR 0x4E8B41C + +#define mmARC_FARM_KDMA_STS_WR_CTX_SEL 0x4E8B420 + +#define mmARC_FARM_KDMA_STS_WR_CTX_SIZE 0x4E8B424 + +#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_LO 0x4E8B428 + +#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_HI 0x4E8B42C + +#define mmARC_FARM_KDMA_STS_WR_CTX_ID 0x4E8B430 + +#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO 0x4E8B434 + +#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI 0x4E8B438 + +#define mmARC_FARM_KDMA_STS_WR_LB_AXI_ADDR 0x4E8B43C + +#define mmARC_FARM_KDMA_PWRLP_CFG 0x4E8B700 + +#define mmARC_FARM_KDMA_PWRLP_STS 0x4E8B704 + +#define mmARC_FARM_KDMA_DBG_DESC_CNT 0x4E8B710 + +#define mmARC_FARM_KDMA_DBG_STS 0x4E8B714 + +#define mmARC_FARM_KDMA_DBG_BUF_STS 0x4E8B718 + +#define mmARC_FARM_KDMA_DBG_RD_DESC_ID 0x4E8B720 + +#define mmARC_FARM_KDMA_DBG_WR_DESC_ID 0x4E8B724 + +#define mmARC_FARM_KDMA_APB_DMA_LBW_BASE 0x4E8B728 + +#define mmARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE 0x4E8B72C + +#define mmARC_FARM_KDMA_E2E_CRED_ASYNC_CFG 0x4E8B730 + +#define mmARC_FARM_KDMA_DBG_APB_ENABLER 0x4E8BE1C + +#define mmARC_FARM_KDMA_L2H_CMPR_LO 0x4E8BE20 + +#define mmARC_FARM_KDMA_L2H_CMPR_HI 0x4E8BE24 + +#define mmARC_FARM_KDMA_L2H_MASK_LO 0x4E8BE28 + +#define mmARC_FARM_KDMA_L2H_MASK_HI 0x4E8BE2C + +#define mmARC_FARM_KDMA_IDLE_IND_MASK 0x4E8BE30 + +#define mmARC_FARM_KDMA_APB_ENABLER 0x4E8BE34 + +#endif /* ASIC_REG_ARC_FARM_KDMA_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000..9b3eceec9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h @@ -0,0 +1,777 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF + * (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_ARUSER_OVR 0x4CC1104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108 + +#define mmCPU_IF_AWUSER_OVR 0x4CC110C + +#define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110 + +#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114 + +#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120 + +#define mmCPU_IF_AXCACHE_OVR 0x4CC1128 + +#define mmCPU_IF_LOCK_OVR 0x4CC112C + +#define mmCPU_IF_PROT_OVR 0x4CC1130 + +#define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134 + +#define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138 + +#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C + +#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140 + +#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144 + +#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148 + +#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C + +#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150 + +#define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154 + +#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158 + +#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C + +#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160 + +#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164 + +#define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168 + +#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C + +#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170 + +#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174 + +#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188 + +#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C + +#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0 + +#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4 + +#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8 + +#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC + +#define mmCPU_IF_PF_PQ_PI 0x4CC1200 + +#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204 + +#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208 + +#define mmCPU_IF_PQ_LENGTH 0x4CC120C + +#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210 + +#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214 + +#define mmCPU_IF_CQ_LENGTH 0x4CC1218 + +#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220 + +#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224 + +#define mmCPU_IF_EQ_LENGTH 0x4CC1228 + +#define mmCPU_IF_EQ_RD_OFFS 0x4CC122C + +#define mmCPU_IF_QUEUE_INIT 0x4CC1230 + +#define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300 + +#define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304 + +#define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308 + +#define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310 + +#define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314 + +#define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318 + +#define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320 + +#define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324 + +#define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328 + +#define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C + +#define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330 + +#define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334 + +#define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338 + +#define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C + +#define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340 + +#define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344 + +#define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348 + +#define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C + +#define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350 + +#define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354 + +#define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358 + +#define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C + +#define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360 + +#define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364 + +#define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368 + +#define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C + +#define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370 + +#define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374 + +#define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378 + +#define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C + +#define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380 + +#define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384 + +#define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388 + +#define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390 + +#define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394 + +#define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398 + +#define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0 + +#define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4 + +#define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8 + +#define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0 + +#define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4 + +#define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8 + +#define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0 + +#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4 + +#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8 + +#define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0 + +#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4 + +#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8 + +#define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0 + +#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4 + +#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8 + +#define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0 + +#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4 + +#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8 + +#define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400 + +#define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404 + +#define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408 + +#define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410 + +#define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414 + +#define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418 + +#define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420 + +#define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424 + +#define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428 + +#define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430 + +#define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434 + +#define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438 + +#define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440 + +#define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444 + +#define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448 + +#define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450 + +#define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454 + +#define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478 + +#define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480 + +#define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484 + +#define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488 + +#define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490 + +#define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494 + +#define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498 + +#define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0 + +#define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4 + +#define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8 + +#define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0 + +#define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4 + +#define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8 + +#define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0 + +#define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4 + +#define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8 + +#define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0 + +#define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4 + +#define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8 + +#define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC + +#define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0 + +#define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4 + +#define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8 + +#define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC + +#define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0 + +#define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4 + +#define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8 + +#define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC + +#define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500 + +#define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504 + +#define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518 + +#define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520 + +#define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524 + +#define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528 + +#define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530 + +#define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534 + +#define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538 + +#define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540 + +#define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544 + +#define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548 + +#define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550 + +#define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554 + +#define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558 + +#define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560 + +#define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564 + +#define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568 + +#define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570 + +#define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574 + +#define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588 + +#define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590 + +#define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594 + +#define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598 + +#define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600 + +#define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604 + +#define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608 + +#define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610 + +#define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614 + +#define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618 + +#define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C + +#define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620 + +#define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624 + +#define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628 + +#define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C + +#define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630 + +#define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634 + +#define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638 + +#define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC + +#define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700 + +#define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704 + +#define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708 + +#define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C + +#define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710 + +#define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714 + +#define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718 + +#define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C + +#define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720 + +#define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C + +#define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C + +#define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C + +#define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C + +#define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784 + +#define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0 + +#define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4 + +#define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC + +#define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC + +#define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C + +#define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840 + +#define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844 + +#define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848 + +#define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850 + +#define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854 + +#define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858 + +#define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860 + +#define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864 + +#define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868 + +#define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870 + +#define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874 + +#define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878 + +#define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900 + +#define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904 + +#define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908 + +#define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C + +#define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910 + +#define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914 + +#define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918 + +#define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C + +#define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920 + +#define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924 + +#define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928 + +#define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C + +#define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930 + +#define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934 + +#define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938 + +#define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C + +#define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940 + +#define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944 + +#define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948 + +#define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C + +#define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950 + +#define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954 + +#define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958 + +#define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C + +#define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960 + +#define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964 + +#define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968 + +#define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C + +#define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970 + +#define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974 + +#define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978 + +#define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C + +#define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980 + +#define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984 + +#define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988 + +#define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C + +#define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990 + +#define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994 + +#define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998 + +#define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C + +#define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0 + +#define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4 + +#define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8 + +#define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC + +#define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0 + +#define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4 + +#define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8 + +#define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC + +#define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0 + +#define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4 + +#define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8 + +#define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0 + +#define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4 + +#define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h new file mode 100644 index 000000000..296ab8320 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ +#define ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ + +/* + ***************************************** + * DCORE0_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +/* DCORE0_DEC0_CMD_SWREG0 */ +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG1 */ +#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG2 */ +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG3 */ +#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG4 */ +#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG5 */ +#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG6 */ +#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG7 */ +#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG8 */ +#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG9 */ +#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG10 */ +#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG11 */ +#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG12 */ +#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG13 */ +#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG14 */ +#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG15 */ +#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 +#define DCORE0_DEC0_CMD_SWREG15_RSV_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 + +/* DCORE0_DEC0_CMD_SWREG16 */ +#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG16_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG17 */ +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG17_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG18 */ +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG18_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG19 */ +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 + +/* DCORE0_DEC0_CMD_SWREG20 */ +#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG21 */ +#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG22 */ +#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG22_RSV_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG23 */ +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 +#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 +#define DCORE0_DEC0_CMD_SWREG23_RSV_SHIFT 24 +#define DCORE0_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 +#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 +#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 + +/* DCORE0_DEC0_CMD_SWREG24 */ +#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG25 */ +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG26 */ +#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG64 */ +#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG65 */ +#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG66 */ +#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG67 */ +#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h new file mode 100644 index 000000000..e26f0d77c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ +#define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ + +/* + ***************************************** + * DCORE0_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +#define mmDCORE0_DEC0_CMD_SWREG0 0x41E0000 + +#define mmDCORE0_DEC0_CMD_SWREG1 0x41E0004 + +#define mmDCORE0_DEC0_CMD_SWREG2 0x41E0008 + +#define mmDCORE0_DEC0_CMD_SWREG3 0x41E000C + +#define mmDCORE0_DEC0_CMD_SWREG4 0x41E0010 + +#define mmDCORE0_DEC0_CMD_SWREG5 0x41E0014 + +#define mmDCORE0_DEC0_CMD_SWREG6 0x41E0018 + +#define mmDCORE0_DEC0_CMD_SWREG7 0x41E001C + +#define mmDCORE0_DEC0_CMD_SWREG8 0x41E0020 + +#define mmDCORE0_DEC0_CMD_SWREG9 0x41E0024 + +#define mmDCORE0_DEC0_CMD_SWREG10 0x41E0028 + +#define mmDCORE0_DEC0_CMD_SWREG11 0x41E002C + +#define mmDCORE0_DEC0_CMD_SWREG12 0x41E0030 + +#define mmDCORE0_DEC0_CMD_SWREG13 0x41E0034 + +#define mmDCORE0_DEC0_CMD_SWREG14 0x41E0038 + +#define mmDCORE0_DEC0_CMD_SWREG15 0x41E003C + +#define mmDCORE0_DEC0_CMD_SWREG16 0x41E0040 + +#define mmDCORE0_DEC0_CMD_SWREG17 0x41E0044 + +#define mmDCORE0_DEC0_CMD_SWREG18 0x41E0048 + +#define mmDCORE0_DEC0_CMD_SWREG19 0x41E004C + +#define mmDCORE0_DEC0_CMD_SWREG20 0x41E0050 + +#define mmDCORE0_DEC0_CMD_SWREG21 0x41E0054 + +#define mmDCORE0_DEC0_CMD_SWREG22 0x41E0058 + +#define mmDCORE0_DEC0_CMD_SWREG23 0x41E005C + +#define mmDCORE0_DEC0_CMD_SWREG24 0x41E0060 + +#define mmDCORE0_DEC0_CMD_SWREG25 0x41E0064 + +#define mmDCORE0_DEC0_CMD_SWREG26 0x41E0068 + +#define mmDCORE0_DEC0_CMD_SWREG64 0x41E0100 + +#define mmDCORE0_DEC0_CMD_SWREG65 0x41E0104 + +#define mmDCORE0_DEC0_CMD_SWREG66 0x41E0108 + +#define mmDCORE0_DEC0_CMD_SWREG67 0x41E010C + +#endif /* ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h new file mode 100644 index 000000000..8de489392 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID 0x41CB800 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x41CB804 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41CB808 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41CB80C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41CB810 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41CB814 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_QOS 0x41CB818 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RSVD 0x41CB81C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41CB820 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_CORE 0x41CB824 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_E2E_COORD 0x41CB828 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41CB830 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41CB834 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41CB838 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41CB83C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_COORD 0x41CB840 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_LOCK 0x41CB844 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_RSVD 0x41CB848 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_OVRD 0x41CB84C + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h new file mode 100644 index 000000000..f73e76c8f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860 + +#define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864 + +#define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868 + +#define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C + +#define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870 + +#define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8 + +#define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h new file mode 100644 index 000000000..d600f6bf7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* DCORE0_EDMA0_CORE_CFG_0 */ +#define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1 + +/* DCORE0_EDMA0_CORE_CFG_1 */ +#define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0 +#define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1 +#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2 + +/* DCORE0_EDMA0_CORE_PROT */ +#define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1 +#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* DCORE0_EDMA0_CORE_CKG */ +#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 +#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 +#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2 +#define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4 + +/* DCORE0_EDMA0_CORE_RD_GLBL */ +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */ +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */ +#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */ +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */ +#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */ +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */ +#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */ +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */ +#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */ +#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERR_CFG */ +#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* DCORE0_EDMA0_CORE_ERR_CAUSE */ +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */ +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */ +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERRMSG_WDATA */ +#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS0 */ +#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS1 */ +#define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */ +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */ +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_PWRLP_CFG */ +#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 + +/* DCORE0_EDMA0_CORE_PWRLP_STS */ +#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F +#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_DBG_DESC_CNT */ +#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_DBG_STS */ +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* DCORE0_EDMA0_CORE_DBG_BUF_STS */ +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */ +#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */ +#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */ +#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */ +#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */ +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */ +#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* DCORE0_EDMA0_CORE_L2H_CMPR_LO */ +#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_CORE_L2H_CMPR_HI */ +#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_L2H_MASK_LO */ +#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_CORE_L2H_MASK_HI */ +#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_IDLE_IND_MASK */ +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* DCORE0_EDMA0_CORE_APB_ENABLER */ +#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h new file mode 100644 index 000000000..84f068e4c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CFG_0 0x41CB000 + +#define mmDCORE0_EDMA0_CORE_CFG_1 0x41CB004 + +#define mmDCORE0_EDMA0_CORE_PROT 0x41CB008 + +#define mmDCORE0_EDMA0_CORE_CKG 0x41CB00C + +#define mmDCORE0_EDMA0_CORE_RD_GLBL 0x41CB07C + +#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x41CB080 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE 0x41CB084 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE 0x41CB088 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS 0x41CB090 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x41CB094 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x41CB0C0 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE 0x41CB0C4 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE 0x41CB0C8 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS 0x41CB0D0 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x41CB0D4 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x41CB100 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID 0x41CB104 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE 0x41CB108 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS 0x41CB10C + +#define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x41CB110 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x41CB140 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID 0x41CB144 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE 0x41CB148 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS 0x41CB14C + +#define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x41CB150 + +#define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x41CB180 + +#define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER 0x41CB184 + +#define mmDCORE0_EDMA0_CORE_ERR_CFG 0x41CB300 + +#define mmDCORE0_EDMA0_CORE_ERR_CAUSE 0x41CB304 + +#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO 0x41CB308 + +#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI 0x41CB30C + +#define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA 0x41CB310 + +#define mmDCORE0_EDMA0_CORE_STS0 0x41CB380 + +#define mmDCORE0_EDMA0_CORE_STS1 0x41CB384 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL 0x41CB400 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE 0x41CB404 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO 0x41CB408 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI 0x41CB40C + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID 0x41CB410 + +#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x41CB414 + +#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x41CB418 + +#define mmDCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR 0x41CB41C + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SEL 0x41CB420 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SIZE 0x41CB424 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO 0x41CB428 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI 0x41CB42C + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_ID 0x41CB430 + +#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x41CB434 + +#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x41CB438 + +#define mmDCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR 0x41CB43C + +#define mmDCORE0_EDMA0_CORE_PWRLP_CFG 0x41CB700 + +#define mmDCORE0_EDMA0_CORE_PWRLP_STS 0x41CB704 + +#define mmDCORE0_EDMA0_CORE_DBG_DESC_CNT 0x41CB710 + +#define mmDCORE0_EDMA0_CORE_DBG_STS 0x41CB714 + +#define mmDCORE0_EDMA0_CORE_DBG_BUF_STS 0x41CB718 + +#define mmDCORE0_EDMA0_CORE_DBG_RD_DESC_ID 0x41CB720 + +#define mmDCORE0_EDMA0_CORE_DBG_WR_DESC_ID 0x41CB724 + +#define mmDCORE0_EDMA0_CORE_APB_DMA_LBW_BASE 0x41CB728 + +#define mmDCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x41CB72C + +#define mmDCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG 0x41CB730 + +#define mmDCORE0_EDMA0_CORE_DBG_APB_ENABLER 0x41CBE1C + +#define mmDCORE0_EDMA0_CORE_L2H_CMPR_LO 0x41CBE20 + +#define mmDCORE0_EDMA0_CORE_L2H_CMPR_HI 0x41CBE24 + +#define mmDCORE0_EDMA0_CORE_L2H_MASK_LO 0x41CBE28 + +#define mmDCORE0_EDMA0_CORE_L2H_MASK_HI 0x41CBE2C + +#define mmDCORE0_EDMA0_CORE_IDLE_IND_MASK 0x41CBE30 + +#define mmDCORE0_EDMA0_CORE_APB_ENABLER 0x41CBE34 + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h new file mode 100644 index 000000000..0fc45300d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x41C8100 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x41C8104 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x41C8108 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DBG_MODE 0x41C810C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM 0x41C8110 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_NUM 0x41C8114 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x41C8118 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x41C811C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_AP_STS 0x41C8120 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x41C8124 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST 0x41C8128 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ 0x41C812C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x41C8130 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x41C8134 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x41C8138 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x41C813C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x41C8140 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x41C8144 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x41C8150 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x41C8154 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x41C8158 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x41C815C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x41C8160 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x41C8164 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x41C8168 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x41C816C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_OFFSET 0x41C8170 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_OFFSET 0x41C8174 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_OFFSET 0x41C8178 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_OFFSET 0x41C817C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x41C8180 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x41C8184 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x41C8188 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x41C818C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x41C8190 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x41C8194 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x41C8198 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x41C819C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x41C81A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x41C81A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x41C81A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x41C81AC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x41C81B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x41C81B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x41C81B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x41C81BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x41C81C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x41C81C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x41C81C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x41C81CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x41C81D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x41C81D4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x41C81D8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x41C81DC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_0 0x41C81E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_1 0x41C81E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_2 0x41C81E8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_3 0x41C81EC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_4 0x41C81F0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_5 0x41C81F4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_6 0x41C81F8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7 0x41C81FC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_0 0x41C8200 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_1 0x41C8204 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_2 0x41C8208 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_3 0x41C820C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_4 0x41C8210 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_5 0x41C8214 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_6 0x41C8218 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_7 0x41C821C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_8 0x41C8220 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_9 0x41C8224 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_10 0x41C8228 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_11 0x41C822C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_12 0x41C8230 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_13 0x41C8234 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_14 0x41C8238 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_15 0x41C823C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x41C8280 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x41C8284 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x41C8290 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x41C8294 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x41C8298 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x41C829C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x41C82A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x41C82A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x41C82A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x41C82B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x41C82B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x41C82B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x41C82BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x41C82C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x41C82C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x41C82C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x41C82CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x41C82D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x41C82E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x41C82E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x41C82E8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x41C82EC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x41C82F0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x41C82F4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x41C8300 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x41C8304 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x41C8308 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x41C830C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x41C8310 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x41C8314 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x41C8318 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x41C831C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x41C8320 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x41C8324 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x41C8328 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x41C832C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x41C8330 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x41C8334 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x41C8338 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x41C833C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x41C8350 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x41C8354 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x41C8358 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x41C835C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x41C8360 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x41C8364 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x41C8368 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x41C836C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x41C8370 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x41C8374 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x41C8378 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x41C837C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x41C8380 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x41C8384 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x41C838C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x41C8390 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x41C8400 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x41C8404 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x41C8408 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x41C840C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x41C8420 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x41C8424 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x41C8428 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x41C842C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x41C8430 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x41C8434 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x41C843C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x41C8440 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x41C8500 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x41C8504 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x41C8508 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x41C850C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x41C8510 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x41C8514 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x41C8518 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x41C851C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x41C8520 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x41C8524 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x41C8528 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x41C852C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x41C8530 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x41C8534 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x41C8538 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x41C853C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x41C8540 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x41C8544 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x41C8548 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x41C854C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x41C8550 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x41C8554 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x41C8558 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x41C855C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x41C8560 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x41C8564 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x41C8568 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x41C856C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x41C8570 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x41C8574 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x41C8578 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x41C857C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x41C8580 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x41C8584 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x41C8588 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x41C858C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x41C8590 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x41C8594 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x41C8598 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x41C859C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x41C85A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x41C85A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x41C85A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x41C85AC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x41C85B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x41C85B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x41C85B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x41C85BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x41C85C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x41C85C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x41C85C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x41C85CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x41C85D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x41C85D4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x41C85D8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x41C85DC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x41C85E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x41C85E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x41C8620 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x41C8624 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x41C8628 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x41C8630 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x41C8634 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x41C8638 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x41C863C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x41C8640 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x41C8644 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x41C8648 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x41C864C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x41C8650 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x41C8654 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x41C8658 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x41C865C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_AUX2APB_PROT 0x41C8700 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x41C8704 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x41C8708 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x41C870C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x41C8710 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x41C8714 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x41C8718 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x41C871C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x41C8720 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x41C8724 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x41C8728 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x41C872C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x41C8730 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x41C8734 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x41C8738 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x41C873C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x41C8740 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x41C8750 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x41C8754 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x41C8758 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x41C875C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x41C8760 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x41C8764 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x41C8768 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x41C876C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x41C8770 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x41C8774 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x41C8778 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x41C877C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x41C8780 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x41C8784 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x41C8788 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x41C878C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x41C8790 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x41C8794 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x41C8798 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x41C879C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x41C8800 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x41C8804 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x41C8808 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x41C880C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x41C8810 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x41C8814 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x41C8818 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x41C881C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x41C8820 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x41C8824 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x41C8828 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x41C882C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x41C8830 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x41C8834 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x41C8838 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x41C883C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x41C8840 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x41C8844 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x41C8848 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x41C884C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x41C8850 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x41C8854 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x41C8900 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x41C8904 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x41C8908 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x41C890C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x41C8910 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x41C8920 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..88d2a133f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x41CAB80 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41CAB84 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41CAB88 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41CAB8C + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41CAB90 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41CAB94 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x41CAB98 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x41CAB9C + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41CABA0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x41CABA4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x41CABA8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41CABB0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41CABB4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41CABB8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41CABBC + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x41CABC0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x41CABC4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x41CABC8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x41CABCC + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h new file mode 100644 index 000000000..0b0a76a5b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_CGM_CFG 0x41CAD80 + +#define mmDCORE0_EDMA0_QM_CGM_STS 0x41CAD84 + +#define mmDCORE0_EDMA0_QM_CGM_CFG1 0x41CAD88 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h new file mode 100644 index 000000000..102e2a658 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h @@ -0,0 +1,1165 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +/* DCORE0_EDMA0_QM_GLBL_CFG0 */ +#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 + +/* DCORE0_EDMA0_QM_GLBL_CFG1 */ +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* DCORE0_EDMA0_QM_GLBL_CFG2 */ +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_CFG */ +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_AXCACHE */ +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 + +/* DCORE0_EDMA0_QM_GLBL_STS0 */ +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_GLBL_STS1 */ +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 + +/* DCORE0_EDMA0_QM_GLBL_ERR_STS */ +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */ +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* DCORE0_EDMA0_QM_GLBL_PROT */ +#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 + +/* DCORE0_EDMA0_QM_PQ_BASE_LO */ +#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_BASE_HI */ +#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_SIZE */ +#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F + +/* DCORE0_EDMA0_QM_PQ_PI */ +#define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_CI */ +#define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_CFG0 */ +#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 + +/* DCORE0_EDMA0_QM_PQ_CFG1 */ +#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_PQ_STS0 */ +#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_PQ_STS1 */ +#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_CQ_CFG0 */ +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* DCORE0_EDMA0_QM_CQ_STS0 */ +#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_CQ_CFG1 */ +#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_CQ_STS1 */ +#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_0 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_0 */ +#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_1 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_1 */ +#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_2 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_2 */ +#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_3 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_3 */ +#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_4 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_4 */ +#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_TSIZE_STS */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_STS */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE0_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE1_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE2_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE3_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_BARRIER_CFG */ +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_STS */ +#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100 +#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 +#define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10 +#define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400 +#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11 +#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 +#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 +#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 + +/* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */ +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */ +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_PRED */ +#define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_PRED_UPEN */ +#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_DBG_0 */ +#define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F +#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 +#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 +#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 +#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 +#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 +#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 +#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */ +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 + +/* DCORE0_EDMA0_QM_CP_IN_DATA_LO */ +#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_IN_DATA_HI */ +#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */ +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */ +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_SIZE */ +#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_PI */ +#define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_WDATA */ +#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */ +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */ +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_CFG */ +#define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 +#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 + +/* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */ +#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_MASK */ +#define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_ARB_CFG_0 */ +#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 +#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 + +/* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */ +#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */ +#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF + +/* DCORE0_EDMA0_QM_ARB_CFG_1 */ +#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */ +#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ +#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */ +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */ +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */ +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_ID */ +#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */ +#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* DCORE0_EDMA0_QM_ARB_BASE_LO */ +#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_BASE_HI */ +#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_STATE_STS */ +#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */ +#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MSG_STS */ +#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */ +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */ +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */ +#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 + +/* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 + +/* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */ +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */ +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */ +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_ARC_CQ_STS0 */ +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_ARC_CQ_STS1 */ +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ADDR_OVRD */ +#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 +#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_CI */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_CI */ +#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_CFG */ +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 + +/* DCORE0_EDMA0_QM_CP_EXT_SWITCH */ +#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 + +/* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */ +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_SWITCH_WD */ +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ +#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ +#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* DCORE0_EDMA0_QM_PQC_STS_0 */ +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 + +/* DCORE0_EDMA0_QM_PQC_STS_1 */ +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 + +/* DCORE0_EDMA0_QM_SEI_STATUS */ +#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 +#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 +#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 +#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 + +/* DCORE0_EDMA0_QM_SEI_MASK */ +#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 +#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 +#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 +#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 + +/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */ +#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_L2H_MASK_LO */ +#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_QM_L2H_MASK_HI */ +#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_L2H_CMPR_LO */ +#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_QM_L2H_CMPR_HI */ +#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */ +#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */ +#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_IND_GW_APB_CFG */ +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */ +#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */ +#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */ +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */ +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */ +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */ +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */ +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_CFG */ +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h new file mode 100644 index 000000000..32d475b9e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_GLBL_CFG0 0x41CA000 + +#define mmDCORE0_EDMA0_QM_GLBL_CFG1 0x41CA004 + +#define mmDCORE0_EDMA0_QM_GLBL_CFG2 0x41CA008 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG 0x41CA00C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG1 0x41CA010 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x41CA014 + +#define mmDCORE0_EDMA0_QM_GLBL_AXCACHE 0x41CA018 + +#define mmDCORE0_EDMA0_QM_GLBL_STS0 0x41CA01C + +#define mmDCORE0_EDMA0_QM_GLBL_STS1 0x41CA020 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_0 0x41CA024 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_1 0x41CA028 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_2 0x41CA02C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_3 0x41CA030 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_4 0x41CA034 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_0 0x41CA038 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_1 0x41CA03C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_2 0x41CA040 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_3 0x41CA044 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 0x41CA048 + +#define mmDCORE0_EDMA0_QM_GLBL_PROT 0x41CA04C + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_0 0x41CA050 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_1 0x41CA054 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_2 0x41CA058 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_3 0x41CA05C + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_0 0x41CA060 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_1 0x41CA064 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_2 0x41CA068 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_3 0x41CA06C + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_0 0x41CA070 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_1 0x41CA074 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_2 0x41CA078 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_3 0x41CA07C + +#define mmDCORE0_EDMA0_QM_PQ_PI_0 0x41CA080 + +#define mmDCORE0_EDMA0_QM_PQ_PI_1 0x41CA084 + +#define mmDCORE0_EDMA0_QM_PQ_PI_2 0x41CA088 + +#define mmDCORE0_EDMA0_QM_PQ_PI_3 0x41CA08C + +#define mmDCORE0_EDMA0_QM_PQ_CI_0 0x41CA090 + +#define mmDCORE0_EDMA0_QM_PQ_CI_1 0x41CA094 + +#define mmDCORE0_EDMA0_QM_PQ_CI_2 0x41CA098 + +#define mmDCORE0_EDMA0_QM_PQ_CI_3 0x41CA09C + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_0 0x41CA0A0 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_1 0x41CA0A4 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_2 0x41CA0A8 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_3 0x41CA0AC + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_0 0x41CA0B0 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_1 0x41CA0B4 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_2 0x41CA0B8 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_3 0x41CA0BC + +#define mmDCORE0_EDMA0_QM_PQ_STS0_0 0x41CA0C0 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_1 0x41CA0C4 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_2 0x41CA0C8 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_3 0x41CA0CC + +#define mmDCORE0_EDMA0_QM_PQ_STS1_0 0x41CA0D0 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_1 0x41CA0D4 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_2 0x41CA0D8 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_3 0x41CA0DC + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_0 0x41CA0E0 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_1 0x41CA0E4 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_2 0x41CA0E8 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_3 0x41CA0EC + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_4 0x41CA0F0 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_0 0x41CA0F4 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_1 0x41CA0F8 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_2 0x41CA0FC + +#define mmDCORE0_EDMA0_QM_CQ_STS0_3 0x41CA100 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_4 0x41CA104 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_0 0x41CA108 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_1 0x41CA10C + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_2 0x41CA110 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_3 0x41CA114 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_4 0x41CA118 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_0 0x41CA11C + +#define mmDCORE0_EDMA0_QM_CQ_STS1_1 0x41CA120 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_2 0x41CA124 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_3 0x41CA128 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_4 0x41CA12C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_0 0x41CA150 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_0 0x41CA154 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_0 0x41CA158 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_0 0x41CA15C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_1 0x41CA160 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_1 0x41CA164 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_1 0x41CA168 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_1 0x41CA16C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_2 0x41CA170 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_2 0x41CA174 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_2 0x41CA178 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_2 0x41CA17C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_3 0x41CA180 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_3 0x41CA184 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_3 0x41CA188 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_3 0x41CA18C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_4 0x41CA190 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_4 0x41CA194 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_4 0x41CA198 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_4 0x41CA19C + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_0 0x41CA1A0 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_1 0x41CA1A4 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_2 0x41CA1A8 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_3 0x41CA1AC + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_4 0x41CA1B0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_0 0x41CA1B4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_1 0x41CA1B8 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_2 0x41CA1BC + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_3 0x41CA1C0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_4 0x41CA1C4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_0 0x41CA1C8 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_1 0x41CA1CC + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_2 0x41CA1D0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_3 0x41CA1D4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_4 0x41CA1D8 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_0 0x41CA1DC + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_1 0x41CA1E0 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_2 0x41CA1E4 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_3 0x41CA1E8 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_4 0x41CA1EC + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x41CA1F0 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x41CA1F4 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x41CA1F8 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x41CA1FC + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x41CA200 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x41CA204 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x41CA208 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x41CA20C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x41CA210 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x41CA214 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x41CA218 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x41CA21C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x41CA220 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x41CA224 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x41CA228 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x41CA22C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x41CA230 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x41CA234 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x41CA238 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x41CA23C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x41CA240 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x41CA244 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x41CA248 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x41CA24C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x41CA250 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x41CA254 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x41CA258 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x41CA25C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x41CA260 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x41CA264 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x41CA268 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x41CA26C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x41CA270 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x41CA274 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x41CA278 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x41CA27C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x41CA280 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x41CA284 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x41CA288 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x41CA28C + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0 0x41CA290 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1 0x41CA294 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2 0x41CA298 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3 0x41CA29C + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4 0x41CA2A0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0 0x41CA2A4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1 0x41CA2A8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2 0x41CA2AC + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3 0x41CA2B0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4 0x41CA2B4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0 0x41CA2B8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1 0x41CA2BC + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2 0x41CA2C0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3 0x41CA2C4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4 0x41CA2C8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0 0x41CA2CC + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1 0x41CA2D0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2 0x41CA2D4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3 0x41CA2D8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4 0x41CA2DC + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0 0x41CA2E0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1 0x41CA2E4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2 0x41CA2E8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3 0x41CA2EC + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4 0x41CA2F0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0 0x41CA2F4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1 0x41CA2F8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2 0x41CA2FC + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3 0x41CA300 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4 0x41CA304 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0 0x41CA308 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1 0x41CA30C + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2 0x41CA310 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3 0x41CA314 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4 0x41CA318 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0 0x41CA31C + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1 0x41CA320 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2 0x41CA324 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3 0x41CA328 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4 0x41CA32C + +#define mmDCORE0_EDMA0_QM_CP_BARRIER_CFG 0x41CA330 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x41CA334 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x41CA338 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x41CA33C + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x41CA340 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x41CA344 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x41CA348 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x41CA34C + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x41CA350 + +#define mmDCORE0_EDMA0_QM_CP_STS_0 0x41CA368 + +#define mmDCORE0_EDMA0_QM_CP_STS_1 0x41CA36C + +#define mmDCORE0_EDMA0_QM_CP_STS_2 0x41CA370 + +#define mmDCORE0_EDMA0_QM_CP_STS_3 0x41CA374 + +#define mmDCORE0_EDMA0_QM_CP_STS_4 0x41CA378 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_0 0x41CA37C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_1 0x41CA380 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_2 0x41CA384 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_3 0x41CA388 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_4 0x41CA38C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_0 0x41CA390 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_1 0x41CA394 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_2 0x41CA398 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_3 0x41CA39C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_4 0x41CA3A0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_0 0x41CA3A4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_1 0x41CA3A8 + +#define mmDCORE0_EDMA0_QM_CP_PRED_2 0x41CA3AC + +#define mmDCORE0_EDMA0_QM_CP_PRED_3 0x41CA3B0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_4 0x41CA3B4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0 0x41CA3B8 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1 0x41CA3BC + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2 0x41CA3C0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3 0x41CA3C4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4 0x41CA3C8 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_0 0x41CA3CC + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_1 0x41CA3D0 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_2 0x41CA3D4 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_3 0x41CA3D8 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_4 0x41CA3DC + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_0 0x41CA3E0 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_1 0x41CA3E4 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_2 0x41CA3E8 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_3 0x41CA3EC + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_4 0x41CA3F0 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_0 0x41CA3F4 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_1 0x41CA3F8 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_2 0x41CA3FC + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_3 0x41CA400 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_4 0x41CA404 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_0 0x41CA408 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_1 0x41CA40C + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_2 0x41CA410 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_3 0x41CA414 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_4 0x41CA418 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_0 0x41CA41C + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_1 0x41CA420 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_2 0x41CA424 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_3 0x41CA428 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_0 0x41CA42C + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_1 0x41CA430 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_2 0x41CA434 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_3 0x41CA438 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_0 0x41CA43C + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_1 0x41CA440 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_2 0x41CA444 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_3 0x41CA448 + +#define mmDCORE0_EDMA0_QM_PQC_PI_0 0x41CA44C + +#define mmDCORE0_EDMA0_QM_PQC_PI_1 0x41CA450 + +#define mmDCORE0_EDMA0_QM_PQC_PI_2 0x41CA454 + +#define mmDCORE0_EDMA0_QM_PQC_PI_3 0x41CA458 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_0 0x41CA45C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_1 0x41CA460 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_2 0x41CA464 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_3 0x41CA468 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_0 0x41CA46C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_1 0x41CA470 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_2 0x41CA474 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_3 0x41CA478 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_0 0x41CA47C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_1 0x41CA480 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_2 0x41CA484 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_3 0x41CA488 + +#define mmDCORE0_EDMA0_QM_PQC_CFG 0x41CA48C + +#define mmDCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND 0x41CA490 + +#define mmDCORE0_EDMA0_QM_ARB_MASK 0x41CA4A0 + +#define mmDCORE0_EDMA0_QM_ARB_CFG_0 0x41CA4A4 + +#define mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH 0x41CA4A8 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0 0x41CA4AC + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1 0x41CA4B0 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2 0x41CA4B4 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3 0x41CA4B8 + +#define mmDCORE0_EDMA0_QM_ARB_CFG_1 0x41CA4BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_0 0x41CA4C0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_1 0x41CA4C4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_2 0x41CA4C8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_3 0x41CA4CC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_4 0x41CA4D0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_5 0x41CA4D4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_6 0x41CA4D8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_7 0x41CA4DC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_8 0x41CA4E0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_9 0x41CA4E4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_10 0x41CA4E8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_11 0x41CA4EC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_12 0x41CA4F0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_13 0x41CA4F4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_14 0x41CA4F8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_15 0x41CA4FC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_16 0x41CA500 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_17 0x41CA504 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_18 0x41CA508 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_19 0x41CA50C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_20 0x41CA510 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_21 0x41CA514 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_22 0x41CA518 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_23 0x41CA51C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_24 0x41CA520 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_25 0x41CA524 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_26 0x41CA528 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_27 0x41CA52C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_28 0x41CA530 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_29 0x41CA534 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_30 0x41CA538 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_31 0x41CA53C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_32 0x41CA540 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_33 0x41CA544 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_34 0x41CA548 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_35 0x41CA54C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_36 0x41CA550 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_37 0x41CA554 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_38 0x41CA558 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_39 0x41CA55C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_40 0x41CA560 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_41 0x41CA564 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_42 0x41CA568 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_43 0x41CA56C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_44 0x41CA570 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_45 0x41CA574 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_46 0x41CA578 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_47 0x41CA57C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_48 0x41CA580 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_49 0x41CA584 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_50 0x41CA588 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_51 0x41CA58C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_52 0x41CA590 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_53 0x41CA594 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_54 0x41CA598 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_55 0x41CA59C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_56 0x41CA5A0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_57 0x41CA5A4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_58 0x41CA5A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_59 0x41CA5AC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_60 0x41CA5B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_61 0x41CA5B4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_62 0x41CA5B8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_63 0x41CA5BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC 0x41CA5E0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x41CA5E4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x41CA5E8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x41CA5EC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x41CA5F0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x41CA5F4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x41CA5F8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x41CA5FC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x41CA600 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x41CA604 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x41CA608 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x41CA60C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x41CA610 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x41CA614 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x41CA618 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x41CA61C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x41CA620 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x41CA624 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x41CA628 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x41CA62C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x41CA630 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x41CA634 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x41CA638 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x41CA63C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x41CA640 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x41CA644 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x41CA648 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x41CA64C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x41CA650 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x41CA654 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x41CA658 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x41CA65C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x41CA660 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x41CA664 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x41CA668 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x41CA66C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x41CA670 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x41CA674 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x41CA678 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x41CA67C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x41CA680 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x41CA684 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x41CA688 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x41CA68C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x41CA690 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x41CA694 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x41CA698 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x41CA69C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x41CA6A0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x41CA6A4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x41CA6A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x41CA6AC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x41CA6B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x41CA6B4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x41CA6B8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x41CA6BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x41CA6C0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x41CA6C4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x41CA6C8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x41CA6CC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x41CA6D0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x41CA6D4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x41CA6D8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x41CA6DC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x41CA6E0 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x41CA704 + +#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN 0x41CA708 + +#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 0x41CA70C + +#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT 0x41CA710 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_ID 0x41CA714 + +#define mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER 0x41CA718 + +#define mmDCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x41CA744 + +#define mmDCORE0_EDMA0_QM_ARB_BASE_LO 0x41CA754 + +#define mmDCORE0_EDMA0_QM_ARB_BASE_HI 0x41CA758 + +#define mmDCORE0_EDMA0_QM_ARB_STATE_STS 0x41CA780 + +#define mmDCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x41CA784 + +#define mmDCORE0_EDMA0_QM_ARB_MSG_STS 0x41CA788 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x41CA78C + +#define mmDCORE0_EDMA0_QM_ARB_ERR_CAUSE 0x41CA79C + +#define mmDCORE0_EDMA0_QM_ARB_ERR_MSG_EN 0x41CA7A0 + +#define mmDCORE0_EDMA0_QM_ARB_ERR_STS_DRP 0x41CA7A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS 0x41CA7B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 0x41CA7B4 + +#define mmDCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG 0x41CA7FC + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG0 0x41CA800 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG1 0x41CA804 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO 0x41CA808 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI 0x41CA80C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE 0x41CA810 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL 0x41CA814 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS 0x41CA81C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_STS0 0x41CA820 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_STS1 0x41CA824 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS 0x41CA828 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS 0x41CA82C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS 0x41CA830 + +#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI 0x41CA834 + +#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO 0x41CA838 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x41CA83C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x41CA840 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x41CA844 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x41CA848 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x41CA84C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x41CA850 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI 0x41CA854 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO 0x41CA858 + +#define mmDCORE0_EDMA0_QM_ADDR_OVRD 0x41CA85C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0 0x41CA860 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1 0x41CA864 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2 0x41CA868 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3 0x41CA86C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4 0x41CA870 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI 0x41CA874 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_0 0x41CA878 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_1 0x41CA87C + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_2 0x41CA880 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_3 0x41CA884 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_4 0x41CA888 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI 0x41CA88C + +#define mmDCORE0_EDMA0_QM_CP_CFG 0x41CA890 + +#define mmDCORE0_EDMA0_QM_CP_EXT_SWITCH 0x41CA894 + +#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET 0x41CA898 + +#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD 0x41CA89C + +#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO 0x41CA8A4 + +#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI 0x41CA8A8 + +#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI 0x41CA8AC + +#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO 0x41CA8B0 + +#define mmDCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x41CA8B4 + +#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x41CA8B8 + +#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x41CA8BC + +#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_HI 0x41CA8C0 + +#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_LO 0x41CA8C4 + +#define mmDCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x41CA8C8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_0 0x41CA8D0 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_1 0x41CA8D4 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_2 0x41CA8D8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_3 0x41CA8DC + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_0 0x41CA8E0 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_1 0x41CA8E4 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_2 0x41CA8E8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_3 0x41CA8EC + +#define mmDCORE0_EDMA0_QM_SEI_STATUS 0x41CA8F0 + +#define mmDCORE0_EDMA0_QM_SEI_MASK 0x41CA8F4 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO 0x41CAD00 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI 0x41CAD04 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_WDATA 0x41CAD08 + +#define mmDCORE0_EDMA0_QM_L2H_MASK_LO 0x41CAD14 + +#define mmDCORE0_EDMA0_QM_L2H_MASK_HI 0x41CAD18 + +#define mmDCORE0_EDMA0_QM_L2H_CMPR_LO 0x41CAD1C + +#define mmDCORE0_EDMA0_QM_L2H_CMPR_HI 0x41CAD20 + +#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_BASE 0x41CAD24 + +#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_SIZE 0x41CAD28 + +#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x41CAD30 + +#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x41CAD34 + +#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x41CAD38 + +#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x41CAD3C + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_CFG 0x41CAD40 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_WDATA 0x41CAD44 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_RDATA 0x41CAD48 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_STATUS 0x41CAD4C + +#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_LO 0x41CAD60 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_HI 0x41CAD64 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_LO 0x41CAD68 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_HI 0x41CAD6C + +#define mmDCORE0_EDMA0_QM_PERF_CNT_CFG 0x41CAD70 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h new file mode 100644 index 000000000..b608a6345 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA1_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID 0x41DB800 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x41DB804 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41DB808 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41DB80C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41DB810 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41DB814 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_QOS 0x41DB818 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RSVD 0x41DB81C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41DB820 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_CORE 0x41DB824 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_E2E_COORD 0x41DB828 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41DB830 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41DB834 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41DB838 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41DB83C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_COORD 0x41DB840 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_LOCK 0x41DB844 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_RSVD 0x41DB848 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_OVRD 0x41DB84C + +#endif /* ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..c3a462f2a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA1_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x41DAB80 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41DAB84 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41DAB88 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41DAB8C + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41DAB90 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41DAB94 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x41DAB98 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x41DAB9C + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41DABA0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x41DABA4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x41DABA8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41DABB0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41DABB4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41DABB8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41DABBC + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x41DABC0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x41DABC4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x41DABC8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x41DABCC + +#endif /* ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h new file mode 100644 index 000000000..df51eac10 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ +#define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_MMU + * (Prototype: MMU) + ***************************************** + */ + +/* DCORE0_HMMU0_MMU_MMU_ENABLE */ +#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_FORCE_ORDERING */ +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2 + +/* DCORE0_HMMU0_MMU_FEATURE_ENABLE */ +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80 + +/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */ +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */ +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF + +/* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */ +#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF + +/* DCORE0_HMMU0_MMU_SCRAMBLER */ +#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 +#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 +#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8 +#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00 + +/* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */ +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 + +/* DCORE0_HMMU0_MMU_SPI_SEI_MASK */ +#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF + +/* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */ +#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF + +/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */ +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */ +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */ +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */ +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */ +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2 + +/* DCORE0_HMMU0_MMU_INTERRUPT_CLR */ +#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_INTERRUPT_MASK */ +#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF + +/* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */ +#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF + +/* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */ +#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1 + +/* DCORE0_HMMU0_MMU_PIPE_CREDIT */ +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000 + +/* DCORE0_HMMU0_MMU_MMU_BYPASS */ +#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */ +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK \ +0x100000 + +/* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */ +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000 + +/* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */ +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000 + +/* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */ +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000 + +/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */ +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */ +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */ +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */ +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */ +#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0 +#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1 + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_MMU_SRC_NUM */ +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E + +/* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */ +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */ +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h new file mode 100644 index 000000000..08ccd695e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ +#define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_MMU + * (Prototype: MMU) + ***************************************** + */ + +#define mmDCORE0_HMMU0_MMU_MMU_ENABLE 0x408000C + +#define mmDCORE0_HMMU0_MMU_FORCE_ORDERING 0x4080010 + +#define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE 0x4080014 + +#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 0x4080018 + +#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 0x408001C + +#define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE 0x4080020 + +#define mmDCORE0_HMMU0_MMU_SCRAMBLER 0x4080024 + +#define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY 0x4080028 + +#define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK 0x408002C + +#define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE 0x4080030 + +#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE 0x4080034 + +#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA 0x4080038 + +#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE 0x408003C + +#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA 0x4080040 + +#define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID 0x4080044 + +#define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR 0x4080048 + +#define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK 0x408004C + +#define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM 0x4080050 + +#define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR 0x4080054 + +#define mmDCORE0_HMMU0_MMU_PIPE_CREDIT 0x4080058 + +#define mmDCORE0_HMMU0_MMU_MMU_BYPASS 0x408006C + +#define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE 0x4080070 + +#define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG 0x40800A0 + +#define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT 0x40800D0 + +#define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT 0x40800F4 + +#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB 0x40800F8 + +#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB 0x40800FC + +#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB 0x4080100 + +#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB 0x4080104 + +#define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE 0x4080108 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 0x4080110 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 0x4080114 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 0x4080118 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 0x408011C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 0x4080120 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 0x4080124 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 0x4080128 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 0x408012C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 0x4080140 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 0x4080144 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_2 0x4080148 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_3 0x408014C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_4 0x4080150 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_5 0x4080154 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_6 0x4080158 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_7 0x408015C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0 0x4080170 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_1 0x4080174 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_2 0x4080178 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_3 0x408017C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_4 0x4080180 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_5 0x4080184 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_6 0x4080188 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_7 0x408018C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0 0x40801A0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_1 0x40801A4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_2 0x40801A8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_3 0x40801AC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_4 0x40801B0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_5 0x40801B4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_6 0x40801B8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_7 0x40801BC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0 0x40801D0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_1 0x40801D4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_2 0x40801D8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_3 0x40801DC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_4 0x40801E0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_5 0x40801E4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_6 0x40801E8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_7 0x40801EC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0 0x4080200 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_1 0x4080204 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_2 0x4080208 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_3 0x408020C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_4 0x4080210 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_5 0x4080214 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_6 0x4080218 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_7 0x408021C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0 0x4080230 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_1 0x4080234 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_2 0x4080238 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_3 0x408023C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_4 0x4080240 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_5 0x4080244 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_6 0x4080248 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_7 0x408024C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0 0x4080260 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_1 0x4080264 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_2 0x4080268 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_3 0x408026C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_4 0x4080270 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_5 0x4080274 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_6 0x4080278 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_7 0x408027C + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 0x4080290 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 0x4080294 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 0x4080298 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 0x408029C + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_VLD 0x4080300 + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 0x4080304 + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 0x4080308 + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_VLD 0x408030C + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 0x4080310 + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 0x4080314 + +#define mmDCORE0_HMMU0_MMU_MMU_SRC_NUM 0x408031C + +#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_LSB 0x4080320 + +#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_MSB 0x4080324 + +#endif /* ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h new file mode 100644 index 000000000..192eba5f0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ +#define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_STLB + * (Prototype: STLB) + ***************************************** + */ + +/* DCORE0_HMMU0_STLB_BUSY */ +#define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 +#define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_ASID */ +#define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF + +/* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ +#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ +#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_CACHE_INV */ +#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF + +/* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 + +/* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \ +0x7E00000 + +/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_INV_ALL_START */ +#define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 + +/* DCORE0_HMMU0_STLB_INV_ALL_SET */ +#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_INV_PS */ +#define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 + +/* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ +#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ +#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* DCORE0_HMMU0_STLB_INV_SET */ +#define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_SRAM_INIT */ +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +/* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ + +/* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 + +/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF + +/* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ + +/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ +#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 + +/* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 + +/* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ +#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 + +/* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ +#define \ +DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \ +0 +#define \ +DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ +0x1 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC + +/* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ +#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF + +#endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h new file mode 100644 index 000000000..864a259f6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ +#define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_STLB + * (Prototype: STLB) + ***************************************** + */ + +#define mmDCORE0_HMMU0_STLB_BUSY 0x4081000 + +#define mmDCORE0_HMMU0_STLB_ASID 0x4081004 + +#define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 0x4081008 + +#define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 0x408100C + +#define mmDCORE0_HMMU0_STLB_CACHE_INV 0x4081010 + +#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 0x4081014 + +#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 0x4081018 + +#define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN 0x408101C + +#define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE 0x4081020 + +#define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION 0x4081024 + +#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4081028 + +#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x408102C + +#define mmDCORE0_HMMU0_STLB_INV_ALL_START 0x4081034 + +#define mmDCORE0_HMMU0_STLB_INV_ALL_SET 0x4081038 + +#define mmDCORE0_HMMU0_STLB_INV_PS 0x408103C + +#define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX 0x4081040 + +#define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT 0x4081044 + +#define mmDCORE0_HMMU0_STLB_INV_SET 0x4081048 + +#define mmDCORE0_HMMU0_STLB_SRAM_INIT 0x408104C + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION 0x4081050 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS 0x4081054 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 0x4081058 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 0x408105C + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG 0x4081060 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 0x4081064 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 0x4081068 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 0x408106C + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 0x4081070 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 0x4081074 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 0x4081078 + +#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR 0x408107C + +#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK 0x4081080 + +#define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG 0x4081084 + +#define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT 0x4081088 + +#define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION 0x408108C + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB 0x4081090 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB 0x4081094 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB 0x4081098 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB 0x408109C + +#define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL 0x4081100 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4081104 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4081108 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x408110C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4081110 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4081114 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4081118 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x408111C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4081120 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4081124 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4081128 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 0x408112C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 0x4081130 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 0x4081134 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 0x4081138 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 0x408113C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 0x4081140 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 0x4081144 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 0x4081148 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 0x408114C + +#endif /* ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h new file mode 100644 index 000000000..07bed3ec7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_ACC_REGS_H_ +#define ASIC_REG_DCORE0_MME_ACC_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_ACC + * (Prototype: ACC) + ***************************************** + */ + +#define mmDCORE0_MME_ACC_WBC0_AXI 0x40F8000 + +#define mmDCORE0_MME_ACC_WBC1_AXI 0x40F8004 + +#define mmDCORE0_MME_ACC_WBC0_RL 0x40F8008 + +#define mmDCORE0_MME_ACC_WBC1_RL 0x40F800C + +#define mmDCORE0_MME_ACC_WBC_STALL 0x40F8010 + +#define mmDCORE0_MME_ACC_AWCACHE 0x40F8014 + +#define mmDCORE0_MME_ACC_AWPROT 0x40F8018 + +#define mmDCORE0_MME_ACC_AP_LFSR_POLY 0x40F801C + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA 0x40F8020 + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL 0x40F8024 + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA 0x40F8028 + +#define mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY 0x40F802C + +#define mmDCORE0_MME_ACC_WBC_SRC_BP 0x40F8030 + +#define mmDCORE0_MME_ACC_CLK_GATE_EN 0x40F8034 + +#define mmDCORE0_MME_ACC_WBC_INFLIGHTS 0x40F8038 + +#define mmDCORE0_MME_ACC_HBW_CLK_ENABLER_DIS 0x40F803C + +#define mmDCORE0_MME_ACC_E2E_CRDT_TOP0 0x40F8040 + +#define mmDCORE0_MME_ACC_E2E_CRDT_TOP1 0x40F8044 + +#define mmDCORE0_MME_ACC_INTR_CAUSE 0x40F8048 + +#define mmDCORE0_MME_ACC_INTR_MASK 0x40F804C + +#define mmDCORE0_MME_ACC_INTR_CLEAR 0x40F8050 + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 0x40F8054 + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 0x40F8058 + +#define mmDCORE0_MME_ACC_BIST 0x40F805C + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_2P_BVALID 0x40F8060 + +#endif /* ASIC_REG_DCORE0_MME_ACC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h new file mode 100644 index 000000000..c9043979f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0 0x40CB22C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1 0x40CB230 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2 0x40CB234 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3 0x40CB238 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4 0x40CB23C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h new file mode 100644 index 000000000..7d74aea45 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0 0x40CB240 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1 0x40CB244 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2 0x40CB248 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3 0x40CB24C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4 0x40CB250 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h new file mode 100644 index 000000000..f6f519eb5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0 0x40CB254 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1 0x40CB258 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2 0x40CB25C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3 0x40CB260 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4 0x40CB264 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h new file mode 100644 index 000000000..0e0c056ad --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0 0x40CB268 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1 0x40CB26C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2 0x40CB270 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3 0x40CB274 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4 0x40CB278 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h new file mode 100644 index 000000000..34c6134a2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0 0x40CB15C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1 0x40CB160 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2 0x40CB164 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3 0x40CB168 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4 0x40CB16C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h new file mode 100644 index 000000000..55065032f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0 0x40CB170 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1 0x40CB174 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2 0x40CB178 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3 0x40CB17C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4 0x40CB180 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h new file mode 100644 index 000000000..6022b387e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0 0x40CB184 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1 0x40CB188 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2 0x40CB18C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3 0x40CB190 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4 0x40CB194 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h new file mode 100644 index 000000000..f9c9b01f0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0 0x40CB198 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1 0x40CB19C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2 0x40CB1A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3 0x40CB1A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4 0x40CB1A8 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h new file mode 100644 index 000000000..d96119b8c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0 0x40CB1AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1 0x40CB1B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2 0x40CB1B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3 0x40CB1B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4 0x40CB1BC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h new file mode 100644 index 000000000..c80d6817e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0 0x40CB1C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1 0x40CB1C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2 0x40CB1C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3 0x40CB1CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4 0x40CB1D0 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h new file mode 100644 index 000000000..753b31dc1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0 0x40CB1D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1 0x40CB1D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2 0x40CB1DC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3 0x40CB1E0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4 0x40CB1E4 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h new file mode 100644 index 000000000..f68d043ed --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0 0x40CB1E8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1 0x40CB1EC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2 0x40CB1F0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3 0x40CB1F4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4 0x40CB1F8 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h new file mode 100644 index 000000000..a6dce326b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0 0x40CB1FC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1 0x40CB200 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2 0x40CB204 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3 0x40CB208 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4 0x40CB20C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h new file mode 100644 index 000000000..5ace0f43c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0 0x40CB210 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1 0x40CB214 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2 0x40CB218 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3 0x40CB21C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4 0x40CB220 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h new file mode 100644 index 000000000..b375393df --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR + * (Prototype: MME_ADDRESS_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW 0x40CB008 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH 0x40CB00C + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW 0x40CB010 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH 0x40CB014 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW 0x40CB018 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH 0x40CB01C + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW 0x40CB020 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH 0x40CB024 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h new file mode 100644 index 000000000..7c22b9383 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END + * (Prototype: MME_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 \ +0x40CB280 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW 0x40CB284 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH 0x40CB288 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP 0x40CB28C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 \ +0x40CB290 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT 0x40CB294 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS 0x40CB298 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER 0x40CB29C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA 0x40CB2A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN 0x40CB2A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT 0x40CB2A8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU 0x40CB2AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR 0x40CB2B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR 0x40CB2B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP 0x40CB2B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER 0x40CB2BC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER 0x40CB2C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER 0x40CB2C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER 0x40CB2C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE 0x40CB2CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE 0x40CB2D0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE 0x40CB2D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE 0x40CB2D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID 0x40CB2DC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h new file mode 100644 index 000000000..d17c165fa --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START + * (Prototype: MME_NON_TENSOR_DESCRIPTOR_START) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW 0x40CB028 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH 0x40CB02C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW 0x40CB030 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH 0x40CB034 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER 0x40CB038 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE 0x40CB03C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h new file mode 100644 index 000000000..7b77884e0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_A + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0 0x40CB040 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1 0x40CB044 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2 0x40CB048 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3 0x40CB04C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4 0x40CB050 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0 0x40CB054 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1 0x40CB058 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2 0x40CB05C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3 0x40CB060 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4 0x40CB064 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0 0x40CB068 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1 0x40CB06C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2 0x40CB070 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3 0x40CB074 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0 0x40CB078 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1 0x40CB07C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2 0x40CB080 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3 0x40CB084 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0 0x40CB088 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1 0x40CB08C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2 0x40CB090 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3 0x40CB094 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h new file mode 100644 index 000000000..a2a2ba454 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_B + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0 0x40CB098 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1 0x40CB09C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2 0x40CB0A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3 0x40CB0A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4 0x40CB0A8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0 0x40CB0AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1 0x40CB0B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2 0x40CB0B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3 0x40CB0B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4 0x40CB0BC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0 0x40CB0C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1 0x40CB0C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2 0x40CB0C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3 0x40CB0CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0 0x40CB0D0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1 0x40CB0D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2 0x40CB0D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3 0x40CB0DC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0 0x40CB0E0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1 0x40CB0E4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2 0x40CB0E8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3 0x40CB0EC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h new file mode 100644 index 000000000..7ad7b197c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0 0x40CB0F0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1 0x40CB0F4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2 0x40CB0F8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3 0x40CB0FC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4 0x40CB100 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0 0x40CB104 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1 0x40CB108 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2 0x40CB10C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3 0x40CB110 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4 0x40CB114 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0 0x40CB118 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1 0x40CB11C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2 0x40CB120 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3 0x40CB124 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0 0x40CB128 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1 0x40CB12C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2 0x40CB130 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3 0x40CB134 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0 0x40CB138 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1 0x40CB13C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2 0x40CB140 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3 0x40CB144 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h new file mode 100644 index 000000000..f699661d7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h @@ -0,0 +1,468 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +/* DCORE0_MME_CTRL_LO_ARCH_STATUS */ +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_CMD */ +#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F +#define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5 +#define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20 +#define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6 +#define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40 +#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7 +#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180 +#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9 +#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200 +#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10 +#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00 +#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12 +#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000 +#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15 +#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK \ +0x10000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK \ +0x100000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK \ +0x200000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_ARCH_A_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_B_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_QM_STALL */ +#define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00 + +/* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00 + +/* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ +#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F + +/* DCORE0_MME_CTRL_LO_REDUN */ +#define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0 +#define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F + +/* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_TH */ +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PROT */ +#define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7 + +/* DCORE0_MME_CTRL_LO_EU */ +#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2 +#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2 +#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000 +#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21 +#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000 + +/* DCORE0_MME_CTRL_LO_SBTE */ +#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F + +/* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ +#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ +#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31 +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0 +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0 +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ +#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ +#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_AGU */ +#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_QM */ +#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1 +#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000 + +/* DCORE0_MME_CTRL_LO_INTR_CAUSE */ +#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF + +/* DCORE0_MME_CTRL_LO_INTR_MASK */ +#define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF + +/* DCORE0_MME_CTRL_LO_INTR_CLEAR */ +#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF + +/* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ +#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_BIST */ +#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1 +#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ +#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ +#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_RL_CFG */ +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ +#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h new file mode 100644 index 000000000..a51617a6f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_MME_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID 0x40CBE00 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP 0x40CBE04 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_STRONG_ORDER 0x40CBE08 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_NO_SNOOP 0x40CBE0C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_REDUCTION 0x40CBE10 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_ATOMIC 0x40CBE14 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_QOS 0x40CBE18 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RSVD 0x40CBE1C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_EMEM_CPAGE 0x40CBE20 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_CORE 0x40CBE24 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_E2E_COORD 0x40CBE28 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_LO 0x40CBE30 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_HI 0x40CBE34 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_LO 0x40CBE38 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_HI 0x40CBE3C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_COORD 0x40CBE40 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_LOCK 0x40CBE44 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_RSVD 0x40CBE48 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_OVRD 0x40CBE4C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h new file mode 100644 index 000000000..1b91c9c13 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_STATUS 0x40CB000 + +#define mmDCORE0_MME_CTRL_LO_CMD 0x40CB004 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x40CB148 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x40CB14C + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x40CB150 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x40CB154 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x40CB158 + +#define mmDCORE0_MME_CTRL_LO_ARCH_A_SS 0x40CB224 + +#define mmDCORE0_MME_CTRL_LO_ARCH_B_SS 0x40CB228 + +#define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS 0x40CB27C + +#define mmDCORE0_MME_CTRL_LO_QM_STALL 0x40CB400 + +#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO 0x40CB404 + +#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI 0x40CB408 + +#define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x40CB40C + +#define mmDCORE0_MME_CTRL_LO_REDUN 0x40CB410 + +#define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x40CB414 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x40CB418 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x40CB41C + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x40CB420 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x40CB424 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x40CB428 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x40CB42C + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x40CB430 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 0x40CB434 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x40CB438 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_TH 0x40CB43C + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN 0x40CB440 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN 0x40CB444 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x40CB448 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x40CB44C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x40CB450 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x40CB454 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x40CB458 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 0x40CB45C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x40CB460 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x40CB464 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x40CB468 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x40CB46C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x40CB470 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x40CB474 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x40CB478 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x40CB47C + +#define mmDCORE0_MME_CTRL_LO_PROT 0x40CB480 + +#define mmDCORE0_MME_CTRL_LO_EU 0x40CB484 + +#define mmDCORE0_MME_CTRL_LO_SBTE 0x40CB488 + +#define mmDCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x40CB48C + +#define mmDCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x40CB490 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC 0x40CB494 + +#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x40CB498 + +#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x40CB49C + +#define mmDCORE0_MME_CTRL_LO_EU_ISOLATION_DIS 0x40CB4A0 + +#define mmDCORE0_MME_CTRL_LO_QM_SLV_CLK_EN 0x40CB4A4 + +#define mmDCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x40CB4A8 + +#define mmDCORE0_MME_CTRL_LO_AGU 0x40CB4AC + +#define mmDCORE0_MME_CTRL_LO_QM 0x40CB4B0 + +#define mmDCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x40CB4B4 + +#define mmDCORE0_MME_CTRL_LO_INTR_CAUSE 0x40CB4B8 + +#define mmDCORE0_MME_CTRL_LO_INTR_MASK 0x40CB4BC + +#define mmDCORE0_MME_CTRL_LO_INTR_CLEAR 0x40CB4C0 + +#define mmDCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x40CB4C4 + +#define mmDCORE0_MME_CTRL_LO_BIST 0x40CB4C8 + +#define mmDCORE0_MME_CTRL_LO_EU_RL_ENABLE 0x40CB4CC + +#define mmDCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x40CB4D0 + +#define mmDCORE0_MME_CTRL_LO_EU_RL_CFG 0x40CB4D4 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW0 0x40CB4D8 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW1 0x40CB4DC + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW2 0x40CB4E0 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW3 0x40CB4E4 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID 0x40CB4E8 + +#define mmDCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x40CB4EC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h new file mode 100644 index 000000000..f702fe6e9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h @@ -0,0 +1,567 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_ACP_ENG + * (Prototype: ARC_ACP_ENG) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0 0x40CF000 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_1 0x40CF004 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_2 0x40CF008 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_3 0x40CF00C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_4 0x40CF010 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_5 0x40CF014 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_6 0x40CF018 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_7 0x40CF01C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_8 0x40CF020 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_9 0x40CF024 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_10 0x40CF028 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_11 0x40CF02C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_12 0x40CF030 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_13 0x40CF034 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_14 0x40CF038 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_15 0x40CF03C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_16 0x40CF040 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_17 0x40CF044 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_18 0x40CF048 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_19 0x40CF04C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_20 0x40CF050 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_21 0x40CF054 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_22 0x40CF058 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_23 0x40CF05C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_24 0x40CF060 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_25 0x40CF064 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_26 0x40CF068 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_27 0x40CF06C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_28 0x40CF070 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_29 0x40CF074 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_30 0x40CF078 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_31 0x40CF07C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_32 0x40CF080 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_33 0x40CF084 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_34 0x40CF088 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_35 0x40CF08C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_36 0x40CF090 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_37 0x40CF094 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_38 0x40CF098 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_39 0x40CF09C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_40 0x40CF0A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_41 0x40CF0A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_42 0x40CF0A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_43 0x40CF0AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_44 0x40CF0B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_45 0x40CF0B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_46 0x40CF0B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_47 0x40CF0BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_48 0x40CF0C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_49 0x40CF0C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_50 0x40CF0C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_51 0x40CF0CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_52 0x40CF0D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_53 0x40CF0D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_54 0x40CF0D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_55 0x40CF0DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_56 0x40CF0E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_57 0x40CF0E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_58 0x40CF0E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_59 0x40CF0EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_60 0x40CF0F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_61 0x40CF0F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_62 0x40CF0F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_63 0x40CF0FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_0 0x40CF100 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_1 0x40CF104 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_2 0x40CF108 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_3 0x40CF10C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_4 0x40CF110 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_5 0x40CF114 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_6 0x40CF118 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_7 0x40CF11C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_8 0x40CF120 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_9 0x40CF124 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_10 0x40CF128 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_11 0x40CF12C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_12 0x40CF130 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_13 0x40CF134 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_14 0x40CF138 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_15 0x40CF13C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_16 0x40CF140 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_17 0x40CF144 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_18 0x40CF148 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_19 0x40CF14C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_20 0x40CF150 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_21 0x40CF154 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_22 0x40CF158 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_23 0x40CF15C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_24 0x40CF160 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_25 0x40CF164 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_26 0x40CF168 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_27 0x40CF16C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_28 0x40CF170 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_29 0x40CF174 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_30 0x40CF178 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_31 0x40CF17C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_32 0x40CF180 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_33 0x40CF184 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_34 0x40CF188 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_35 0x40CF18C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_36 0x40CF190 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_37 0x40CF194 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_38 0x40CF198 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_39 0x40CF19C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_40 0x40CF1A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_41 0x40CF1A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_42 0x40CF1A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_43 0x40CF1AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_44 0x40CF1B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_45 0x40CF1B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_46 0x40CF1B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_47 0x40CF1BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_48 0x40CF1C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_49 0x40CF1C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_50 0x40CF1C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_51 0x40CF1CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_52 0x40CF1D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_53 0x40CF1D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_54 0x40CF1D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_55 0x40CF1DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_56 0x40CF1E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_57 0x40CF1E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_58 0x40CF1E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_59 0x40CF1EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_60 0x40CF1F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_61 0x40CF1F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_62 0x40CF1F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_63 0x40CF1FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_0 0x40CF200 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_1 0x40CF204 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_2 0x40CF208 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_3 0x40CF20C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_4 0x40CF210 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_5 0x40CF214 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_6 0x40CF218 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_7 0x40CF21C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_8 0x40CF220 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_9 0x40CF224 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_10 0x40CF228 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_11 0x40CF22C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_12 0x40CF230 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_13 0x40CF234 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_14 0x40CF238 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_15 0x40CF23C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_16 0x40CF240 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_17 0x40CF244 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_18 0x40CF248 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_19 0x40CF24C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_20 0x40CF250 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_21 0x40CF254 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_22 0x40CF258 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_23 0x40CF25C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_24 0x40CF260 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_25 0x40CF264 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_26 0x40CF268 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_27 0x40CF26C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_28 0x40CF270 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_29 0x40CF274 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_30 0x40CF278 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_31 0x40CF27C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_32 0x40CF280 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_33 0x40CF284 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_34 0x40CF288 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_35 0x40CF28C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_36 0x40CF290 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_37 0x40CF294 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_38 0x40CF298 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_39 0x40CF29C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_40 0x40CF2A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_41 0x40CF2A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_42 0x40CF2A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_43 0x40CF2AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_44 0x40CF2B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_45 0x40CF2B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_46 0x40CF2B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_47 0x40CF2BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_48 0x40CF2C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_49 0x40CF2C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_50 0x40CF2C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_51 0x40CF2CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_52 0x40CF2D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_53 0x40CF2D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_54 0x40CF2D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_55 0x40CF2DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_56 0x40CF2E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_57 0x40CF2E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_58 0x40CF2E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_59 0x40CF2EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_60 0x40CF2F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_61 0x40CF2F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_62 0x40CF2F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_63 0x40CF2FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_0 0x40CF300 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_1 0x40CF304 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_2 0x40CF308 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_3 0x40CF30C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_4 0x40CF310 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_5 0x40CF314 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_6 0x40CF318 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_7 0x40CF31C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_8 0x40CF320 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_9 0x40CF324 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_10 0x40CF328 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_11 0x40CF32C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_12 0x40CF330 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_13 0x40CF334 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_14 0x40CF338 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_15 0x40CF33C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_16 0x40CF340 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_17 0x40CF344 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_18 0x40CF348 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_19 0x40CF34C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_20 0x40CF350 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_21 0x40CF354 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_22 0x40CF358 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_23 0x40CF35C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_24 0x40CF360 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_25 0x40CF364 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_26 0x40CF368 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_27 0x40CF36C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_28 0x40CF370 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_29 0x40CF374 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_30 0x40CF378 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_31 0x40CF37C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_32 0x40CF380 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_33 0x40CF384 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_34 0x40CF388 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_35 0x40CF38C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_36 0x40CF390 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_37 0x40CF394 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_38 0x40CF398 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_39 0x40CF39C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_40 0x40CF3A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_41 0x40CF3A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_42 0x40CF3A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_43 0x40CF3AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_44 0x40CF3B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_45 0x40CF3B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_46 0x40CF3B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_47 0x40CF3BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_48 0x40CF3C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_49 0x40CF3C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_50 0x40CF3C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_51 0x40CF3CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_52 0x40CF3D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_53 0x40CF3D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_54 0x40CF3D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_55 0x40CF3DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_56 0x40CF3E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_57 0x40CF3E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_58 0x40CF3E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_59 0x40CF3EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_60 0x40CF3F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_61 0x40CF3F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_62 0x40CF3F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_63 0x40CF3FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x40CF400 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x40CF404 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x40CF408 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x40CF40C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x40CF410 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x40CF414 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x40CF418 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x40CF41C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x40CF420 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x40CF424 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x40CF428 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x40CF42C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x40CF430 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x40CF434 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x40CF438 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG 0x40CF43C + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h new file mode 100644 index 000000000..917f8ab88 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ 0x40C8100 + +#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK 0x40C8104 + +#define mmDCORE0_MME_QM_ARC_AUX_RST_VEC_ADDR 0x40C8108 + +#define mmDCORE0_MME_QM_ARC_AUX_DBG_MODE 0x40C810C + +#define mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM 0x40C8110 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_NUM 0x40C8114 + +#define mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT 0x40C8118 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x40C811C + +#define mmDCORE0_MME_QM_ARC_AUX_CTI_AP_STS 0x40C8120 + +#define mmDCORE0_MME_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x40C8124 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST 0x40C8128 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ 0x40C812C + +#define mmDCORE0_MME_QM_ARC_AUX_SRAM_LSB_ADDR 0x40C8130 + +#define mmDCORE0_MME_QM_ARC_AUX_SRAM_MSB_ADDR 0x40C8134 + +#define mmDCORE0_MME_QM_ARC_AUX_PCIE_LSB_ADDR 0x40C8138 + +#define mmDCORE0_MME_QM_ARC_AUX_PCIE_MSB_ADDR 0x40C813C + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LSB_ADDR 0x40C8140 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_MSB_ADDR 0x40C8144 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_LSB_ADDR 0x40C8150 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_MSB_ADDR 0x40C8154 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_LSB_ADDR 0x40C8158 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_MSB_ADDR 0x40C815C + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_LSB_ADDR 0x40C8160 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_MSB_ADDR 0x40C8164 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_LSB_ADDR 0x40C8168 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_MSB_ADDR 0x40C816C + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_OFFSET 0x40C8170 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_OFFSET 0x40C8174 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_OFFSET 0x40C8178 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_OFFSET 0x40C817C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x40C8180 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x40C8184 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x40C8188 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x40C818C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x40C8190 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x40C8194 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x40C8198 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x40C819C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40C81A0 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40C81A4 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40C81A8 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40C81AC + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40C81B0 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40C81B4 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40C81B8 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40C81BC + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_0 0x40C81C0 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_1 0x40C81C4 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_2 0x40C81C8 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_3 0x40C81CC + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_4 0x40C81D0 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_5 0x40C81D4 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_6 0x40C81D8 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_7 0x40C81DC + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_0 0x40C81E0 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_1 0x40C81E4 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_2 0x40C81E8 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_3 0x40C81EC + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_4 0x40C81F0 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_5 0x40C81F4 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_6 0x40C81F8 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7 0x40C81FC + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_0 0x40C8200 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_1 0x40C8204 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_2 0x40C8208 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_3 0x40C820C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_4 0x40C8210 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_5 0x40C8214 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_6 0x40C8218 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_7 0x40C821C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_8 0x40C8220 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_9 0x40C8224 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_10 0x40C8228 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_11 0x40C822C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_12 0x40C8230 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_13 0x40C8234 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_14 0x40C8238 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_15 0x40C823C + +#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_0 0x40C8280 + +#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_1 0x40C8284 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_STS 0x40C8290 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x40C8294 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x40C8298 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x40C829C + +#define mmDCORE0_MME_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40C82A0 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40C82A4 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40C82A8 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_STS 0x40C82B0 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40C82B4 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40C82B8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40C82BC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40C82C0 + +#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40C82C4 + +#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40C82C8 + +#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40C82CC + +#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40C82D0 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40C82E0 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40C82E4 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40C82E8 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40C82EC + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40C82F0 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40C82F4 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0 0x40C8300 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_1 0x40C8304 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_2 0x40C8308 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_3 0x40C830C + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_4 0x40C8310 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_5 0x40C8314 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_6 0x40C8318 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_7 0x40C831C + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x40C8320 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x40C8324 + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x40C8328 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x40C832C + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x40C8330 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x40C8334 + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x40C8338 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x40C833C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR 0x40C8350 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x40C8354 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR 0x40C8358 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x40C835C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x40C8360 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x40C8364 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x40C8368 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x40C836C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AXCACHE_OVR 0x40C8370 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_LOCK_OVR 0x40C8374 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_PROT_OVR 0x40C8378 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x40C837C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x40C8380 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x40C8384 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x40C838C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_SEI_INTR_ID 0x40C8390 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR 0x40C8400 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x40C8404 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR 0x40C8408 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x40C840C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AXCACHE_OVR 0x40C8420 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_LOCK_OVR 0x40C8424 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_PROT_OVR 0x40C8428 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x40C842C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x40C8430 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x40C8434 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x40C843C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_SEI_INTR_ID 0x40C8440 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x40C8500 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x40C8504 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x40C8508 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x40C850C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x40C8510 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x40C8514 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x40C8518 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x40C851C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x40C8520 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x40C8524 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x40C8528 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x40C852C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x40C8530 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x40C8534 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x40C8538 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x40C853C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x40C8540 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x40C8544 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x40C8548 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x40C854C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x40C8550 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x40C8554 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x40C8558 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x40C855C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x40C8560 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x40C8564 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x40C8568 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x40C856C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x40C8570 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x40C8574 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x40C8578 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x40C857C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x40C8580 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x40C8584 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x40C8588 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x40C858C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x40C8590 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x40C8594 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x40C8598 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x40C859C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40C85A0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40C85A4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40C85A8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40C85AC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40C85B0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40C85B4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40C85B8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40C85BC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40C85C0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40C85C4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40C85C8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40C85CC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40C85D0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40C85D4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40C85D8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40C85DC + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40C85E0 + +#define mmDCORE0_MME_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40C85E4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x40C8620 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x40C8624 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x40C8628 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x40C8630 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x40C8634 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x40C8638 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x40C863C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x40C8640 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x40C8644 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x40C8648 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x40C864C + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x40C8650 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x40C8654 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x40C8658 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x40C865C + +#define mmDCORE0_MME_QM_ARC_AUX_AUX2APB_PROT 0x40C8700 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_FORK_WIN_EN 0x40C8704 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x40C8708 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x40C870C + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x40C8710 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x40C8714 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x40C8718 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x40C871C + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x40C8720 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x40C8724 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x40C8728 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x40C872C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x40C8730 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x40C8734 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x40C8738 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x40C873C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_WIN_EN 0x40C8740 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x40C8750 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x40C8754 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x40C8758 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x40C875C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x40C8760 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x40C8764 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x40C8768 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x40C876C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x40C8770 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x40C8774 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x40C8778 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x40C877C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x40C8780 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x40C8784 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x40C8788 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x40C878C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x40C8790 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x40C8794 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x40C8798 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x40C879C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_0 0x40C8800 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_1 0x40C8804 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_2 0x40C8808 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_3 0x40C880C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_4 0x40C8810 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_5 0x40C8814 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_6 0x40C8818 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_7 0x40C881C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_8 0x40C8820 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_9 0x40C8824 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_10 0x40C8828 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_11 0x40C882C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_12 0x40C8830 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_13 0x40C8834 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_14 0x40C8838 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_15 0x40C883C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x40C8840 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x40C8844 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x40C8848 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x40C884C + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x40C8850 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x40C8854 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x40C8900 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x40C8904 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x40C8908 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x40C890C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x40C8910 + +#define mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x40C8920 + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h new file mode 100644 index 000000000..c7ebaf73c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_DUP_ENG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_ASID 0x40C9900 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_MMU_BP 0x40C9904 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x40C9908 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_NO_SNOOP 0x40C990C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x40C9910 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x40C9914 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_QOS 0x40C9918 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RSVD 0x40C991C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x40C9920 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_CORE 0x40C9924 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_E2E_COORD 0x40C9928 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x40C9930 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x40C9934 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x40C9938 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x40C993C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_COORD 0x40C9940 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_LOCK 0x40C9944 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_RSVD 0x40C9948 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD 0x40C994C + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h new file mode 100644 index 000000000..61654e373 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_DUP_ENG + * (Prototype: ARC_DUP_ENG) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x40C9000 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x40C9004 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x40C9008 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x40C900C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x40C9010 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x40C9014 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x40C9018 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x40C901C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x40C9020 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x40C9024 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x40C9028 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x40C902C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x40C9030 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x40C9034 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x40C9038 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x40C903C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x40C9040 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x40C9044 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x40C9048 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x40C904C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x40C9050 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x40C9054 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x40C9058 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x40C905C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x40C9060 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_0 0x40C9064 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_1 0x40C9068 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_2 0x40C906C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_3 0x40C9070 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x40C9074 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x40C9078 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x40C907C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x40C9080 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x40C9084 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x40C9088 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x40C908C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x40C9090 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x40C9094 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x40C9098 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x40C909C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x40C90A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x40C90A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x40C90A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x40C90AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x40C90B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x40C90B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x40C90B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x40C90BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x40C90C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x40C90C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x40C90C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x40C90CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x40C90D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x40C90D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x40C90D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x40C90DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x40C90E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x40C90E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x40C90E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x40C90EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x40C90F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x40C90F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x40C90F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x40C90FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x40C9100 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x40C9104 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x40C9108 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x40C910C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x40C9110 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x40C9114 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x40C9118 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x40C911C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x40C9120 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x40C9124 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x40C9128 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x40C912C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x40C9130 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x40C9134 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x40C9138 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x40C913C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x40C9140 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_MASK 0x40C9200 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_MASK 0x40C9204 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_MASK 0x40C9208 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_MASK 0x40C920C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_MASK 0x40C9210 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_MASK 0x40C9214 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_0 0x40C9218 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_1 0x40C921C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_2 0x40C9220 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_3 0x40C9224 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_4 0x40C9228 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_5 0x40C922C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_6 0x40C9230 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_7 0x40C9234 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x40C9238 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x40C923C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x40C9240 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x40C9244 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x40C9248 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x40C924C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x40C9250 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x40C9254 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x40C9258 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x40C925C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x40C9260 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x40C9264 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x40C9268 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x40C926C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x40C9288 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x40C928C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x40C9290 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x40C9294 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x40C9298 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x40C929C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x40C92A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x40C92A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x40C92A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x40C92AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x40C92B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x40C92B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x40C92B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x40C92BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x40C92C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x40C92C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x40C92C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x40C92CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GENERAL_CFG 0x40C92D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_BP_CFG 0x40C92D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x40C92D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x40C92DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x40C92E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x40C92E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x40C92E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x40C92EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x40C92F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x40C92F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x40C92F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x40C92FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x40C9300 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x40C9304 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x40C9308 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x40C930C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x40C94A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x40C94A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x40C94A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_STS 0x40C94AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x40C94B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_0 0x40C94B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_1 0x40C94B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_2 0x40C94BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_3 0x40C94C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_4 0x40C94C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_5 0x40C94C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_6 0x40C94CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_7 0x40C94D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_8 0x40C94D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_9 0x40C94D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_10 0x40C94DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_11 0x40C94E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_12 0x40C94E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_13 0x40C94E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_14 0x40C94EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_15 0x40C94F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_16 0x40C94F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_17 0x40C94F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_18 0x40C94FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_19 0x40C9500 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_20 0x40C9504 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_21 0x40C9508 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_22 0x40C950C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_23 0x40C9510 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_24 0x40C9514 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_25 0x40C9518 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_26 0x40C951C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_27 0x40C9520 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_28 0x40C9524 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_29 0x40C9528 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_30 0x40C952C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_31 0x40C9530 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_32 0x40C9534 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_33 0x40C9538 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_34 0x40C953C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_35 0x40C9540 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_36 0x40C9544 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_37 0x40C9548 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_38 0x40C954C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_39 0x40C9550 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_40 0x40C9554 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_41 0x40C9558 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_42 0x40C955C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_43 0x40C9560 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_44 0x40C9564 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_45 0x40C9568 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_46 0x40C956C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_47 0x40C9570 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_48 0x40C9574 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_49 0x40C9578 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_50 0x40C957C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_51 0x40C9580 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_52 0x40C9584 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_53 0x40C9588 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_54 0x40C958C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_55 0x40C9590 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_56 0x40C9594 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_57 0x40C9598 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_58 0x40C959C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_59 0x40C95A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_60 0x40C95A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_61 0x40C95A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_62 0x40C95AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_63 0x40C95B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_0 0x40C95B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_1 0x40C95B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_2 0x40C95BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_3 0x40C95C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_4 0x40C95C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_5 0x40C95C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_6 0x40C95CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_7 0x40C95D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_8 0x40C95D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_9 0x40C95D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_10 0x40C95DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_11 0x40C95E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_12 0x40C95E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_13 0x40C95E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_14 0x40C95EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_15 0x40C95F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_16 0x40C95F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_17 0x40C95F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_18 0x40C95FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_19 0x40C9600 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_20 0x40C9604 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_21 0x40C9608 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_22 0x40C960C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_23 0x40C9610 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_24 0x40C9614 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_25 0x40C9618 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_26 0x40C961C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_27 0x40C9620 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_28 0x40C9624 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_29 0x40C9628 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_30 0x40C962C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_31 0x40C9630 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_32 0x40C9634 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_33 0x40C9638 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_34 0x40C963C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_35 0x40C9640 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_36 0x40C9644 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_37 0x40C9648 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_38 0x40C964C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_39 0x40C9650 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_40 0x40C9654 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_41 0x40C9658 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_42 0x40C965C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_43 0x40C9660 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_44 0x40C9664 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_45 0x40C9668 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_46 0x40C966C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_47 0x40C9670 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_48 0x40C9674 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_49 0x40C9678 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_50 0x40C967C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_51 0x40C9680 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_52 0x40C9684 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_53 0x40C9688 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_54 0x40C968C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_55 0x40C9690 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_56 0x40C9694 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_57 0x40C9698 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_58 0x40C969C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_59 0x40C96A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_60 0x40C96A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_61 0x40C96A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_62 0x40C96AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63 0x40C96B0 + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..32089b825 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID 0x40CAB80 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP 0x40CAB84 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x40CAB88 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x40CAB8C + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x40CAB90 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x40CAB94 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_QOS 0x40CAB98 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RSVD 0x40CAB9C + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x40CABA0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_CORE 0x40CABA4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_E2E_COORD 0x40CABA8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x40CABB0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x40CABB4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x40CABB8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x40CABBC + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_COORD 0x40CABC0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_LOCK 0x40CABC4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_RSVD 0x40CABC8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_OVRD 0x40CABCC + +#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h new file mode 100644 index 000000000..e168c1cc2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_AXUSER_SECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_ASID 0x40CAB00 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_MMU_BP 0x40CAB04 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x40CAB08 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_NO_SNOOP 0x40CAB0C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x40CAB10 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x40CAB14 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_QOS 0x40CAB18 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RSVD 0x40CAB1C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x40CAB20 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_CORE 0x40CAB24 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_E2E_COORD 0x40CAB28 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x40CAB30 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x40CAB34 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x40CAB38 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x40CAB3C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_COORD 0x40CAB40 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_LOCK 0x40CAB44 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_RSVD 0x40CAB48 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_OVRD 0x40CAB4C + +#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h new file mode 100644 index 000000000..543aba18e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_MME_QM_CGM_CFG 0x40CAD80 + +#define mmDCORE0_MME_QM_CGM_STS 0x40CAD84 + +#define mmDCORE0_MME_QM_CGM_CFG1 0x40CAD88 + +#endif /* ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h new file mode 100644 index 000000000..c45583fcc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000 + +#define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004 + +#define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008 + +#define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C + +#define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010 + +#define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014 + +#define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018 + +#define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C + +#define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048 + +#define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C + +#define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C + +#define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C + +#define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070 + +#define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074 + +#define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078 + +#define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C + +#define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080 + +#define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084 + +#define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088 + +#define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C + +#define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090 + +#define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094 + +#define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098 + +#define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C + +#define mmDCORE0_MME_QM_PQ_CFG0_0 0x40CA0A0 + +#define mmDCORE0_MME_QM_PQ_CFG0_1 0x40CA0A4 + +#define mmDCORE0_MME_QM_PQ_CFG0_2 0x40CA0A8 + +#define mmDCORE0_MME_QM_PQ_CFG0_3 0x40CA0AC + +#define mmDCORE0_MME_QM_PQ_CFG1_0 0x40CA0B0 + +#define mmDCORE0_MME_QM_PQ_CFG1_1 0x40CA0B4 + +#define mmDCORE0_MME_QM_PQ_CFG1_2 0x40CA0B8 + +#define mmDCORE0_MME_QM_PQ_CFG1_3 0x40CA0BC + +#define mmDCORE0_MME_QM_PQ_STS0_0 0x40CA0C0 + +#define mmDCORE0_MME_QM_PQ_STS0_1 0x40CA0C4 + +#define mmDCORE0_MME_QM_PQ_STS0_2 0x40CA0C8 + +#define mmDCORE0_MME_QM_PQ_STS0_3 0x40CA0CC + +#define mmDCORE0_MME_QM_PQ_STS1_0 0x40CA0D0 + +#define mmDCORE0_MME_QM_PQ_STS1_1 0x40CA0D4 + +#define mmDCORE0_MME_QM_PQ_STS1_2 0x40CA0D8 + +#define mmDCORE0_MME_QM_PQ_STS1_3 0x40CA0DC + +#define mmDCORE0_MME_QM_CQ_CFG0_0 0x40CA0E0 + +#define mmDCORE0_MME_QM_CQ_CFG0_1 0x40CA0E4 + +#define mmDCORE0_MME_QM_CQ_CFG0_2 0x40CA0E8 + +#define mmDCORE0_MME_QM_CQ_CFG0_3 0x40CA0EC + +#define mmDCORE0_MME_QM_CQ_CFG0_4 0x40CA0F0 + +#define mmDCORE0_MME_QM_CQ_STS0_0 0x40CA0F4 + +#define mmDCORE0_MME_QM_CQ_STS0_1 0x40CA0F8 + +#define mmDCORE0_MME_QM_CQ_STS0_2 0x40CA0FC + +#define mmDCORE0_MME_QM_CQ_STS0_3 0x40CA100 + +#define mmDCORE0_MME_QM_CQ_STS0_4 0x40CA104 + +#define mmDCORE0_MME_QM_CQ_CFG1_0 0x40CA108 + +#define mmDCORE0_MME_QM_CQ_CFG1_1 0x40CA10C + +#define mmDCORE0_MME_QM_CQ_CFG1_2 0x40CA110 + +#define mmDCORE0_MME_QM_CQ_CFG1_3 0x40CA114 + +#define mmDCORE0_MME_QM_CQ_CFG1_4 0x40CA118 + +#define mmDCORE0_MME_QM_CQ_STS1_0 0x40CA11C + +#define mmDCORE0_MME_QM_CQ_STS1_1 0x40CA120 + +#define mmDCORE0_MME_QM_CQ_STS1_2 0x40CA124 + +#define mmDCORE0_MME_QM_CQ_STS1_3 0x40CA128 + +#define mmDCORE0_MME_QM_CQ_STS1_4 0x40CA12C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_0 0x40CA150 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_0 0x40CA154 + +#define mmDCORE0_MME_QM_CQ_TSIZE_0 0x40CA158 + +#define mmDCORE0_MME_QM_CQ_CTL_0 0x40CA15C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_1 0x40CA160 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_1 0x40CA164 + +#define mmDCORE0_MME_QM_CQ_TSIZE_1 0x40CA168 + +#define mmDCORE0_MME_QM_CQ_CTL_1 0x40CA16C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_2 0x40CA170 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_2 0x40CA174 + +#define mmDCORE0_MME_QM_CQ_TSIZE_2 0x40CA178 + +#define mmDCORE0_MME_QM_CQ_CTL_2 0x40CA17C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_3 0x40CA180 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_3 0x40CA184 + +#define mmDCORE0_MME_QM_CQ_TSIZE_3 0x40CA188 + +#define mmDCORE0_MME_QM_CQ_CTL_3 0x40CA18C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_4 0x40CA190 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_4 0x40CA194 + +#define mmDCORE0_MME_QM_CQ_TSIZE_4 0x40CA198 + +#define mmDCORE0_MME_QM_CQ_CTL_4 0x40CA19C + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_0 0x40CA1A0 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_1 0x40CA1A4 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_2 0x40CA1A8 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_3 0x40CA1AC + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_4 0x40CA1B0 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_0 0x40CA1B4 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_1 0x40CA1B8 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_2 0x40CA1BC + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_3 0x40CA1C0 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_4 0x40CA1C4 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_0 0x40CA1C8 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_1 0x40CA1CC + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_2 0x40CA1D0 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_3 0x40CA1D4 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_4 0x40CA1D8 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_0 0x40CA1DC + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_1 0x40CA1E0 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_2 0x40CA1E4 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_3 0x40CA1E8 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_4 0x40CA1EC + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0 0x40CA1F0 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1 0x40CA1F4 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2 0x40CA1F8 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3 0x40CA1FC + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4 0x40CA200 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0 0x40CA204 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1 0x40CA208 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2 0x40CA20C + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3 0x40CA210 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4 0x40CA214 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0 0x40CA218 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1 0x40CA21C + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2 0x40CA220 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3 0x40CA224 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4 0x40CA228 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0 0x40CA22C + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1 0x40CA230 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2 0x40CA234 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3 0x40CA238 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4 0x40CA23C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0 0x40CA240 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1 0x40CA244 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2 0x40CA248 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3 0x40CA24C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4 0x40CA250 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0 0x40CA254 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1 0x40CA258 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2 0x40CA25C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3 0x40CA260 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4 0x40CA264 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0 0x40CA268 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1 0x40CA26C + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2 0x40CA270 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3 0x40CA274 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4 0x40CA278 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0 0x40CA27C + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1 0x40CA280 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2 0x40CA284 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3 0x40CA288 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4 0x40CA28C + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_0 0x40CA290 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_1 0x40CA294 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_2 0x40CA298 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_3 0x40CA29C + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_4 0x40CA2A0 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_0 0x40CA2A4 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_1 0x40CA2A8 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_2 0x40CA2AC + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_3 0x40CA2B0 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_4 0x40CA2B4 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_0 0x40CA2B8 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_1 0x40CA2BC + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_2 0x40CA2C0 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_3 0x40CA2C4 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_4 0x40CA2C8 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_0 0x40CA2CC + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_1 0x40CA2D0 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_2 0x40CA2D4 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_3 0x40CA2D8 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_4 0x40CA2DC + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_0 0x40CA2E0 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_1 0x40CA2E4 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_2 0x40CA2E8 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_3 0x40CA2EC + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_4 0x40CA2F0 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_0 0x40CA2F4 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_1 0x40CA2F8 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_2 0x40CA2FC + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_3 0x40CA300 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_4 0x40CA304 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_0 0x40CA308 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_1 0x40CA30C + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_2 0x40CA310 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_3 0x40CA314 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_4 0x40CA318 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_0 0x40CA31C + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_1 0x40CA320 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_2 0x40CA324 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_3 0x40CA328 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_4 0x40CA32C + +#define mmDCORE0_MME_QM_CP_BARRIER_CFG 0x40CA330 + +#define mmDCORE0_MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x40CA334 + +#define mmDCORE0_MME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x40CA338 + +#define mmDCORE0_MME_QM_CP_LDMA_TSIZE_OFFSET 0x40CA33C + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_0 0x40CA340 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_1 0x40CA344 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_2 0x40CA348 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_3 0x40CA34C + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_4 0x40CA350 + +#define mmDCORE0_MME_QM_CP_STS_0 0x40CA368 + +#define mmDCORE0_MME_QM_CP_STS_1 0x40CA36C + +#define mmDCORE0_MME_QM_CP_STS_2 0x40CA370 + +#define mmDCORE0_MME_QM_CP_STS_3 0x40CA374 + +#define mmDCORE0_MME_QM_CP_STS_4 0x40CA378 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_0 0x40CA37C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_1 0x40CA380 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_2 0x40CA384 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_3 0x40CA388 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_4 0x40CA38C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_0 0x40CA390 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_1 0x40CA394 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_2 0x40CA398 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_3 0x40CA39C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_4 0x40CA3A0 + +#define mmDCORE0_MME_QM_CP_PRED_0 0x40CA3A4 + +#define mmDCORE0_MME_QM_CP_PRED_1 0x40CA3A8 + +#define mmDCORE0_MME_QM_CP_PRED_2 0x40CA3AC + +#define mmDCORE0_MME_QM_CP_PRED_3 0x40CA3B0 + +#define mmDCORE0_MME_QM_CP_PRED_4 0x40CA3B4 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_0 0x40CA3B8 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_1 0x40CA3BC + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_2 0x40CA3C0 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_3 0x40CA3C4 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_4 0x40CA3C8 + +#define mmDCORE0_MME_QM_CP_DBG_0_0 0x40CA3CC + +#define mmDCORE0_MME_QM_CP_DBG_0_1 0x40CA3D0 + +#define mmDCORE0_MME_QM_CP_DBG_0_2 0x40CA3D4 + +#define mmDCORE0_MME_QM_CP_DBG_0_3 0x40CA3D8 + +#define mmDCORE0_MME_QM_CP_DBG_0_4 0x40CA3DC + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_0 0x40CA3E0 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_1 0x40CA3E4 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_2 0x40CA3E8 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_3 0x40CA3EC + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_4 0x40CA3F0 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_0 0x40CA3F4 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_1 0x40CA3F8 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_2 0x40CA3FC + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_3 0x40CA400 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_4 0x40CA404 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_0 0x40CA408 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_1 0x40CA40C + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_2 0x40CA410 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_3 0x40CA414 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_4 0x40CA418 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_0 0x40CA41C + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_1 0x40CA420 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_2 0x40CA424 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_3 0x40CA428 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_0 0x40CA42C + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_1 0x40CA430 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_2 0x40CA434 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_3 0x40CA438 + +#define mmDCORE0_MME_QM_PQC_SIZE_0 0x40CA43C + +#define mmDCORE0_MME_QM_PQC_SIZE_1 0x40CA440 + +#define mmDCORE0_MME_QM_PQC_SIZE_2 0x40CA444 + +#define mmDCORE0_MME_QM_PQC_SIZE_3 0x40CA448 + +#define mmDCORE0_MME_QM_PQC_PI_0 0x40CA44C + +#define mmDCORE0_MME_QM_PQC_PI_1 0x40CA450 + +#define mmDCORE0_MME_QM_PQC_PI_2 0x40CA454 + +#define mmDCORE0_MME_QM_PQC_PI_3 0x40CA458 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_0 0x40CA45C + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_1 0x40CA460 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_2 0x40CA464 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_3 0x40CA468 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_0 0x40CA46C + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_1 0x40CA470 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_2 0x40CA474 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_3 0x40CA478 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_0 0x40CA47C + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_1 0x40CA480 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_2 0x40CA484 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_3 0x40CA488 + +#define mmDCORE0_MME_QM_PQC_CFG 0x40CA48C + +#define mmDCORE0_MME_QM_PQC_SECURE_PUSH_IND 0x40CA490 + +#define mmDCORE0_MME_QM_ARB_MASK 0x40CA4A0 + +#define mmDCORE0_MME_QM_ARB_CFG_0 0x40CA4A4 + +#define mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH 0x40CA4A8 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0 0x40CA4AC + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1 0x40CA4B0 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2 0x40CA4B4 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3 0x40CA4B8 + +#define mmDCORE0_MME_QM_ARB_CFG_1 0x40CA4BC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_0 0x40CA4C0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_1 0x40CA4C4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_2 0x40CA4C8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_3 0x40CA4CC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_4 0x40CA4D0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_5 0x40CA4D4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_6 0x40CA4D8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_7 0x40CA4DC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_8 0x40CA4E0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_9 0x40CA4E4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_10 0x40CA4E8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_11 0x40CA4EC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_12 0x40CA4F0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_13 0x40CA4F4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_14 0x40CA4F8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_15 0x40CA4FC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_16 0x40CA500 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_17 0x40CA504 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_18 0x40CA508 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_19 0x40CA50C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_20 0x40CA510 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_21 0x40CA514 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_22 0x40CA518 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_23 0x40CA51C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_24 0x40CA520 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_25 0x40CA524 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_26 0x40CA528 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_27 0x40CA52C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_28 0x40CA530 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_29 0x40CA534 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_30 0x40CA538 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_31 0x40CA53C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_32 0x40CA540 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_33 0x40CA544 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_34 0x40CA548 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_35 0x40CA54C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_36 0x40CA550 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_37 0x40CA554 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_38 0x40CA558 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_39 0x40CA55C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_40 0x40CA560 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_41 0x40CA564 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_42 0x40CA568 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_43 0x40CA56C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_44 0x40CA570 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_45 0x40CA574 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_46 0x40CA578 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_47 0x40CA57C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_48 0x40CA580 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_49 0x40CA584 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_50 0x40CA588 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_51 0x40CA58C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_52 0x40CA590 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_53 0x40CA594 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_54 0x40CA598 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_55 0x40CA59C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_56 0x40CA5A0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_57 0x40CA5A4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_58 0x40CA5A8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_59 0x40CA5AC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_60 0x40CA5B0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_61 0x40CA5B4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_62 0x40CA5B8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_63 0x40CA5BC + +#define mmDCORE0_MME_QM_ARB_MST_CRED_INC 0x40CA5E0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x40CA5E4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x40CA5E8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x40CA5EC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x40CA5F0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x40CA5F4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x40CA5F8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x40CA5FC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x40CA600 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x40CA604 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x40CA608 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x40CA60C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x40CA610 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x40CA614 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x40CA618 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x40CA61C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x40CA620 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x40CA624 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x40CA628 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x40CA62C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x40CA630 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x40CA634 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x40CA638 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x40CA63C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x40CA640 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x40CA644 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x40CA648 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x40CA64C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x40CA650 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x40CA654 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x40CA658 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x40CA65C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x40CA660 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x40CA664 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x40CA668 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x40CA66C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x40CA670 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x40CA674 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x40CA678 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x40CA67C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x40CA680 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x40CA684 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x40CA688 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x40CA68C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x40CA690 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x40CA694 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x40CA698 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x40CA69C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x40CA6A0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x40CA6A4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x40CA6A8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x40CA6AC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x40CA6B0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x40CA6B4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x40CA6B8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x40CA6BC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x40CA6C0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x40CA6C4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x40CA6C8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x40CA6CC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x40CA6D0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x40CA6D4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x40CA6D8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x40CA6DC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x40CA6E0 + +#define mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x40CA704 + +#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN 0x40CA708 + +#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1 0x40CA70C + +#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_WDT 0x40CA710 + +#define mmDCORE0_MME_QM_ARB_SLV_ID 0x40CA714 + +#define mmDCORE0_MME_QM_ARB_MST_QUIET_PER 0x40CA718 + +#define mmDCORE0_MME_QM_ARB_MSG_MAX_INFLIGHT 0x40CA744 + +#define mmDCORE0_MME_QM_ARB_BASE_LO 0x40CA754 + +#define mmDCORE0_MME_QM_ARB_BASE_HI 0x40CA758 + +#define mmDCORE0_MME_QM_ARB_STATE_STS 0x40CA780 + +#define mmDCORE0_MME_QM_ARB_CHOICE_FULLNESS_STS 0x40CA784 + +#define mmDCORE0_MME_QM_ARB_MSG_STS 0x40CA788 + +#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_Q_HEAD 0x40CA78C + +#define mmDCORE0_MME_QM_ARB_ERR_CAUSE 0x40CA79C + +#define mmDCORE0_MME_QM_ARB_ERR_MSG_EN 0x40CA7A0 + +#define mmDCORE0_MME_QM_ARB_ERR_STS_DRP 0x40CA7A8 + +#define mmDCORE0_MME_QM_ARB_MST_CRED_STS 0x40CA7B0 + +#define mmDCORE0_MME_QM_ARB_MST_CRED_STS_1 0x40CA7B4 + +#define mmDCORE0_MME_QM_CSMR_STRICT_PRIO_CFG 0x40CA7FC + +#define mmDCORE0_MME_QM_ARC_CQ_CFG0 0x40CA800 + +#define mmDCORE0_MME_QM_ARC_CQ_CFG1 0x40CA804 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO 0x40CA808 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI 0x40CA80C + +#define mmDCORE0_MME_QM_ARC_CQ_TSIZE 0x40CA810 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL 0x40CA814 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_STS 0x40CA81C + +#define mmDCORE0_MME_QM_ARC_CQ_STS0 0x40CA820 + +#define mmDCORE0_MME_QM_ARC_CQ_STS1 0x40CA824 + +#define mmDCORE0_MME_QM_ARC_CQ_TSIZE_STS 0x40CA828 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS 0x40CA82C + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS 0x40CA830 + +#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_HI 0x40CA834 + +#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_LO 0x40CA838 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x40CA83C + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x40CA840 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_HI 0x40CA844 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO 0x40CA848 + +#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_HI 0x40CA84C + +#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO 0x40CA850 + +#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_HI 0x40CA854 + +#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 0x40CA858 + +#define mmDCORE0_MME_QM_ADDR_OVRD 0x40CA85C + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_0 0x40CA860 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_1 0x40CA864 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_2 0x40CA868 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_3 0x40CA86C + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_4 0x40CA870 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI 0x40CA874 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_0 0x40CA878 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_1 0x40CA87C + +#define mmDCORE0_MME_QM_CQ_CTL_CI_2 0x40CA880 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_3 0x40CA884 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_4 0x40CA888 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_CI 0x40CA88C + +#define mmDCORE0_MME_QM_CP_CFG 0x40CA890 + +#define mmDCORE0_MME_QM_CP_EXT_SWITCH 0x40CA894 + +#define mmDCORE0_MME_QM_CP_SWITCH_WD_SET 0x40CA898 + +#define mmDCORE0_MME_QM_CP_SWITCH_WD 0x40CA89C + +#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_LO 0x40CA8A4 + +#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_HI 0x40CA8A8 + +#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_HI 0x40CA8AC + +#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_LO 0x40CA8B0 + +#define mmDCORE0_MME_QM_ENGINE_ADDR_RANGE_SIZE 0x40CA8B4 + +#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_HI 0x40CA8B8 + +#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_LO 0x40CA8BC + +#define mmDCORE0_MME_QM_QM_BASE_ADDR_HI 0x40CA8C0 + +#define mmDCORE0_MME_QM_QM_BASE_ADDR_LO 0x40CA8C4 + +#define mmDCORE0_MME_QM_ARC_PQC_SECURE_PUSH_IND 0x40CA8C8 + +#define mmDCORE0_MME_QM_PQC_STS_0_0 0x40CA8D0 + +#define mmDCORE0_MME_QM_PQC_STS_0_1 0x40CA8D4 + +#define mmDCORE0_MME_QM_PQC_STS_0_2 0x40CA8D8 + +#define mmDCORE0_MME_QM_PQC_STS_0_3 0x40CA8DC + +#define mmDCORE0_MME_QM_PQC_STS_1_0 0x40CA8E0 + +#define mmDCORE0_MME_QM_PQC_STS_1_1 0x40CA8E4 + +#define mmDCORE0_MME_QM_PQC_STS_1_2 0x40CA8E8 + +#define mmDCORE0_MME_QM_PQC_STS_1_3 0x40CA8EC + +#define mmDCORE0_MME_QM_SEI_STATUS 0x40CA8F0 + +#define mmDCORE0_MME_QM_SEI_MASK 0x40CA8F4 + +#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_LO 0x40CAD00 + +#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_HI 0x40CAD04 + +#define mmDCORE0_MME_QM_GLBL_ERR_WDATA 0x40CAD08 + +#define mmDCORE0_MME_QM_L2H_MASK_LO 0x40CAD14 + +#define mmDCORE0_MME_QM_L2H_MASK_HI 0x40CAD18 + +#define mmDCORE0_MME_QM_L2H_CMPR_LO 0x40CAD1C + +#define mmDCORE0_MME_QM_L2H_CMPR_HI 0x40CAD20 + +#define mmDCORE0_MME_QM_LOCAL_RANGE_BASE 0x40CAD24 + +#define mmDCORE0_MME_QM_LOCAL_RANGE_SIZE 0x40CAD28 + +#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_1 0x40CAD30 + +#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_0 0x40CAD34 + +#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_1 0x40CAD38 + +#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_0 0x40CAD3C + +#define mmDCORE0_MME_QM_IND_GW_APB_CFG 0x40CAD40 + +#define mmDCORE0_MME_QM_IND_GW_APB_WDATA 0x40CAD44 + +#define mmDCORE0_MME_QM_IND_GW_APB_RDATA 0x40CAD48 + +#define mmDCORE0_MME_QM_IND_GW_APB_STATUS 0x40CAD4C + +#define mmDCORE0_MME_QM_PERF_CNT_FREE_LO 0x40CAD60 + +#define mmDCORE0_MME_QM_PERF_CNT_FREE_HI 0x40CAD64 + +#define mmDCORE0_MME_QM_PERF_CNT_IDLE_LO 0x40CAD68 + +#define mmDCORE0_MME_QM_PERF_CNT_IDLE_HI 0x40CAD6C + +#define mmDCORE0_MME_QM_PERF_CNT_CFG 0x40CAD70 + +#endif /* ASIC_REG_DCORE0_MME_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h new file mode 100644 index 000000000..077ae5232 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ +#define ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ + +/* + ***************************************** + * DCORE0_MME_SBTE0 + * (Prototype: SB) + ***************************************** + */ + +/* DCORE0_MME_SBTE0_MAX_SIZE */ +#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_MASK 0xFFFF +#define DCORE0_MME_SBTE0_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_MME_SBTE0_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* DCORE0_MME_SBTE0_FORCE_MISS */ +#define DCORE0_MME_SBTE0_FORCE_MISS_R_SHIFT 0 +#define DCORE0_MME_SBTE0_FORCE_MISS_R_MASK 0x1 + +/* DCORE0_MME_SBTE0_MAX */ +#define DCORE0_MME_SBTE0_MAX_OS_SHIFT 0 +#define DCORE0_MME_SBTE0_MAX_OS_MASK 0xFFFF + +/* DCORE0_MME_SBTE0_RL */ +#define DCORE0_MME_SBTE0_RL_SATURATION_SHIFT 0 +#define DCORE0_MME_SBTE0_RL_SATURATION_MASK 0xFF +#define DCORE0_MME_SBTE0_RL_TIMEOUT_SHIFT 8 +#define DCORE0_MME_SBTE0_RL_TIMEOUT_MASK 0xFF00 +#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_SHIFT 16 +#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_MASK 0x10000 + +/* DCORE0_MME_SBTE0_SB_STALL */ +#define DCORE0_MME_SBTE0_SB_STALL_R_SHIFT 0 +#define DCORE0_MME_SBTE0_SB_STALL_R_MASK 0x1 + +/* DCORE0_MME_SBTE0_INTR */ +#define DCORE0_MME_SBTE0_INTR_I0_SHIFT 0 +#define DCORE0_MME_SBTE0_INTR_I0_MASK 0x1 + +/* DCORE0_MME_SBTE0_ARUSER */ +#define DCORE0_MME_SBTE0_ARUSER_ASID_SHIFT 0 +#define DCORE0_MME_SBTE0_ARUSER_ASID_MASK 0x3FF +#define DCORE0_MME_SBTE0_ARUSER_MMBP_SHIFT 10 +#define DCORE0_MME_SBTE0_ARUSER_MMBP_MASK 0x400 +#define DCORE0_MME_SBTE0_ARUSER_DUMMY_SHIFT 11 +#define DCORE0_MME_SBTE0_ARUSER_DUMMY_MASK 0xFFFFF800 + +/* DCORE0_MME_SBTE0_ARCACHE */ +#define DCORE0_MME_SBTE0_ARCACHE_N_SHIFT 0 +#define DCORE0_MME_SBTE0_ARCACHE_N_MASK 0xF + +/* DCORE0_MME_SBTE0_STATUS */ +#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_SHIFT 0 +#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_PRTN */ +#define DCORE0_MME_SBTE0_PRTN_CLK_EN_SHIFT 0 +#define DCORE0_MME_SBTE0_PRTN_CLK_EN_MASK 0x1 + +/* DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS */ +#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_SHIFT 0 +#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_PROT */ +#define DCORE0_MME_SBTE0_PROT_W_SHIFT 0 +#define DCORE0_MME_SBTE0_PROT_W_MASK 0x7 + +/* DCORE0_MME_SBTE0_INTR_MASK */ +#define DCORE0_MME_SBTE0_INTR_MASK_W_SHIFT 0 +#define DCORE0_MME_SBTE0_INTR_MASK_W_MASK 0x1 + +/* DCORE0_MME_SBTE0_ARUSER_MSB */ +#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_SHIFT 0 +#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY */ +#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_SHIFT 0 +#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_ENABLE_CGATE */ +#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_SHIFT 0 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_MASK 0x1 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_SHIFT 4 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_MASK 0x10 + +/* DCORE0_MME_SBTE0_INTF_VLD_DBG */ +#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_SHIFT 0 +#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_INTF_RDY_DBG */ +#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_SHIFT 0 +#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h new file mode 100644 index 000000000..211fa2c2c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_SBTE0_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID 0x40D1A80 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP 0x40D1A84 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40D1A88 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40D1A8C + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40D1A90 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40D1A94 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_QOS 0x40D1A98 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RSVD 0x40D1A9C + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40D1AA0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_CORE 0x40D1AA4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_E2E_COORD 0x40D1AA8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40D1AB0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40D1AB4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40D1AB8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40D1ABC + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_COORD 0x40D1AC0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_LOCK 0x40D1AC4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_RSVD 0x40D1AC8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_OVRD 0x40D1ACC + +#endif /* ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h new file mode 100644 index 000000000..374a01d2b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_WB0_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID 0x40F9A80 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP 0x40F9A84 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40F9A88 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40F9A8C + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40F9A90 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40F9A94 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_QOS 0x40F9A98 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RSVD 0x40F9A9C + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40F9AA0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_CORE 0x40F9AA4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_E2E_COORD 0x40F9AA8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40F9AB0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40F9AB4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40F9AB8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40F9ABC + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_COORD 0x40F9AC0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_LOCK 0x40F9AC4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_RSVD 0x40F9AC8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_OVRD 0x40F9ACC + +#endif /* ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h new file mode 100644 index 000000000..22f4d6c80 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_CTRL + * (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDCORE0_RTR0_CTRL_MEM_NUM 0x4140100 + +#define mmDCORE0_RTR0_CTRL_MEM_MAP 0x4140104 + +#define mmDCORE0_RTR0_CTRL_WR_RL_MEM 0x4140108 + +#define mmDCORE0_RTR0_CTRL_WR_RL_PCI 0x414010C + +#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM 0x4140110 + +#define mmDCORE0_RTR0_CTRL_RD_RL_MEM 0x4140114 + +#define mmDCORE0_RTR0_CTRL_RD_RL_PCI 0x4140118 + +#define mmDCORE0_RTR0_CTRL_RD_RL_SRAM 0x414011C + +#define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED 0x4140120 + +#define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION 0x4140124 + +#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED 0x4140128 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 0x4140400 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 0x4140404 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 0x4140408 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 0x414040C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 0x4140410 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 0x4140414 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 0x4140418 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 0x414041C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 0x4140420 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 0x4140424 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 0x4140428 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 0x414042C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 0x4140430 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 0x4140434 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 0x4140438 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 0x414043C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 0x4140440 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 0x4140444 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 0x4140448 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 0x414044C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 0x4140450 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 0x4140454 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 0x4140458 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 0x414045C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 0x4140460 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 0x4140464 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 0x4140468 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 0x414046C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 0x4140470 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_9 0x4140474 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_10 0x4140478 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_11 0x414047C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_12 0x4140480 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_13 0x4140484 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_14 0x4140488 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_15 0x414048C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_0 0x4140490 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_1 0x4140494 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_2 0x4140498 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_3 0x414049C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_4 0x41404A0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_5 0x41404A4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_6 0x41404A8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_7 0x41404AC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_8 0x41404B0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_9 0x41404B4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_10 0x41404B8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_11 0x41404BC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_12 0x41404C0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_13 0x41404C4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_14 0x41404C8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_15 0x41404CC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_0 0x41404D0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_1 0x41404D4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_0 0x41404D8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_1 0x41404DC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR 0x4140AB8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR 0x4140ABC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET 0x4140AC0 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR 0x4140AC4 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR 0x4140AC8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET 0x4140ACC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR 0x4140AD0 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_SET 0x4140AD4 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR 0x4140AD8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET 0x4140ADC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_0 0x4140AE4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_1 0x4140AE8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_0 0x4140AEC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_1 0x4140AF0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_0 0x4140AF4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_1 0x4140AF8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_2 0x4140AFC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_3 0x4140B00 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_4 0x4140B04 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_5 0x4140B08 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_6 0x4140B0C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_7 0x4140B10 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_8 0x4140B14 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_9 0x4140B18 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_10 0x4140B1C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_11 0x4140B20 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_12 0x4140B24 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_13 0x4140B28 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_14 0x4140B2C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_15 0x4140B30 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_0 0x4140B34 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_1 0x4140B38 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_2 0x4140B3C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_3 0x4140B40 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_4 0x4140B44 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_5 0x4140B48 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_6 0x4140B4C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_7 0x4140B50 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_8 0x4140B54 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_9 0x4140B58 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_10 0x4140B5C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_11 0x4140B60 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_12 0x4140B64 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_13 0x4140B68 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_14 0x4140B6C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_15 0x4140B70 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_0 0x4140B74 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_1 0x4140B78 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_2 0x4140B7C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_3 0x4140B80 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_4 0x4140B84 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_5 0x4140B88 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_6 0x4140B8C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_7 0x4140B90 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_8 0x4140B94 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_9 0x4140B98 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_10 0x4140B9C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_11 0x4140BA0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_12 0x4140BA4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_13 0x4140BA8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_14 0x4140BAC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_15 0x4140BB0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_0 0x4140BB4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_1 0x4140BB8 + +#define mmDCORE0_RTR0_CTRL_RGL_WR_RED_CNT 0x4140BBC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_0 0x4140BC0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_1 0x4140BC4 + +#endif /* ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h new file mode 100644 index 000000000..3a7290b3a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW + * (Prototype: RANGE_REG_HBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142200 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142204 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142208 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414220C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142210 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142214 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142218 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414221C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142220 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142224 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142228 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414222C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142230 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142234 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142238 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414223C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142240 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142244 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142248 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414224C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142250 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142254 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142258 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414225C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142260 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142264 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142268 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414226C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142270 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142274 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142278 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414227C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142280 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142284 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142288 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414228C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142290 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142294 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142298 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414229C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41422A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41422A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41422A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41422AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41422B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41422B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41422B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41422BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_0 0x41422C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_1 0x41422C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_2 0x41422C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_3 0x41422CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_0 0x41422D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_1 0x41422D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_2 0x41422D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_3 0x41422DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_0 0x41422E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_1 0x41422E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_2 0x41422E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_3 0x41422EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_0 0x41422F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_1 0x41422F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_2 0x41422F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_3 0x41422FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_0 0x4142300 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_1 0x4142304 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_2 0x4142308 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_3 0x414230C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_0 0x4142310 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_1 0x4142314 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_2 0x4142318 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_3 0x414231C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_0 0x4142320 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_1 0x4142324 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_2 0x4142328 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_3 0x414232C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_0 0x4142330 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_1 0x4142334 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_2 0x4142338 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_3 0x414233C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_PCIE_EN 0x4142340 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_PCIE_EN 0x4142344 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AW 0x4142348 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AW 0x414234C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AR 0x4142350 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AR 0x4142354 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HI 0x4142358 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_LO 0x414235C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HI 0x4142360 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_LO 0x4142364 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_XY 0x4142368 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_XY 0x414236C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HAPPENED 0x4142370 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HAPPENED 0x4142374 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_RAZWI_ERR_RESP 0x4142378 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h new file mode 100644 index 000000000..5b52b88fe --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW + * (Prototype: RANGE_REG_LBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_0 0x4142600 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_1 0x4142604 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_2 0x4142608 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_3 0x414260C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_4 0x4142610 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_5 0x4142614 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_6 0x4142618 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_7 0x414261C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_8 0x4142620 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_9 0x4142624 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_10 0x4142628 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_11 0x414262C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_12 0x4142630 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_13 0x4142634 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_0 0x4142638 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_1 0x414263C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_2 0x4142640 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_3 0x4142644 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_4 0x4142648 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_5 0x414264C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_6 0x4142650 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_7 0x4142654 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_8 0x4142658 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_9 0x414265C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_10 0x4142660 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_11 0x4142664 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_12 0x4142668 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_13 0x414266C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142670 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142674 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142678 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_3 0x414267C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142680 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142684 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142688 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_7 0x414268C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142690 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142694 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142698 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_11 0x414269C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_12 0x41426A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_13 0x41426A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_0 0x41426A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_1 0x41426AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_2 0x41426B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_3 0x41426B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_4 0x41426B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_5 0x41426BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_6 0x41426C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_7 0x41426C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_8 0x41426C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_9 0x41426CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_10 0x41426D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_11 0x41426D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_12 0x41426D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_13 0x41426DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_0 0x41426E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_1 0x41426E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_2 0x41426E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_3 0x41426EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_0 0x41426F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_1 0x41426F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_2 0x41426F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_3 0x41426FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_0 0x4142700 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_1 0x4142704 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_2 0x4142708 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_3 0x414270C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_0 0x4142710 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_1 0x4142714 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_2 0x4142718 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_3 0x414271C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AW 0x4142720 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AW 0x4142724 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AR 0x4142728 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AR 0x414272C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI 0x4142730 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI 0x4142734 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_XY 0x4142738 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_XY 0x414273C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_HAPPENED 0x4142740 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_HAPPENED 0x4142744 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_RAZWI_ERR_RESP 0x4142748 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h new file mode 100644 index 000000000..d9b3f5cd3 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW + * (Prototype: RANGE_REG_HBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142000 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142004 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142008 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414200C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142010 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142014 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142018 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414201C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142020 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142024 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142028 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414202C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142030 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142034 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142038 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414203C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142040 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142044 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142048 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414204C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142050 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142054 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142058 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414205C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142060 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142064 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142068 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414206C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142070 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142074 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142078 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414207C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142080 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142084 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142088 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414208C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142090 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142094 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142098 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414209C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41420A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41420A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41420A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41420AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41420B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41420B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41420B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41420BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 0x41420C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_1 0x41420C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_2 0x41420C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_3 0x41420CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 0x41420D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_1 0x41420D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_2 0x41420D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_3 0x41420DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 0x41420E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_1 0x41420E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_2 0x41420E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_3 0x41420EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 0x41420F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_1 0x41420F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_2 0x41420F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_3 0x41420FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 0x4142100 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_1 0x4142104 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_2 0x4142108 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_3 0x414210C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 0x4142110 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_1 0x4142114 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_2 0x4142118 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_3 0x414211C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 0x4142120 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_1 0x4142124 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_2 0x4142128 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_3 0x414212C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 0x4142130 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_1 0x4142134 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_2 0x4142138 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_3 0x414213C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_PCIE_EN 0x4142140 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_PCIE_EN 0x4142144 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AW 0x4142148 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AW 0x414214C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AR 0x4142150 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AR 0x4142154 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI 0x4142158 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO 0x414215C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI 0x4142160 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO 0x4142164 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY 0x4142168 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY 0x414216C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED 0x4142170 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED 0x4142174 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_RAZWI_ERR_RESP 0x4142178 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h new file mode 100644 index 000000000..1bba940d3 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW + * (Prototype: RANGE_REG_LBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 0x4142400 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_1 0x4142404 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_2 0x4142408 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_3 0x414240C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_4 0x4142410 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_5 0x4142414 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_6 0x4142418 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_7 0x414241C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_8 0x4142420 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_9 0x4142424 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_10 0x4142428 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_11 0x414242C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_12 0x4142430 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_13 0x4142434 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 0x4142438 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_1 0x414243C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_2 0x4142440 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_3 0x4142444 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_4 0x4142448 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_5 0x414244C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_6 0x4142450 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_7 0x4142454 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_8 0x4142458 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_9 0x414245C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_10 0x4142460 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_11 0x4142464 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_12 0x4142468 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_13 0x414246C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142470 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142474 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142478 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_3 0x414247C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142480 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142484 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142488 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_7 0x414248C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142490 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142494 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142498 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_11 0x414249C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_12 0x41424A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_13 0x41424A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 0x41424A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_1 0x41424AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_2 0x41424B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_3 0x41424B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_4 0x41424B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_5 0x41424BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_6 0x41424C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_7 0x41424C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_8 0x41424C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_9 0x41424CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_10 0x41424D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_11 0x41424D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_12 0x41424D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_13 0x41424DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 0x41424E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_1 0x41424E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_2 0x41424E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_3 0x41424EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 0x41424F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_1 0x41424F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_2 0x41424F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_3 0x41424FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 0x4142500 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_1 0x4142504 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_2 0x4142508 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_3 0x414250C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 0x4142510 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_1 0x4142514 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_2 0x4142518 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_3 0x414251C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AW 0x4142520 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AW 0x4142524 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AR 0x4142528 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AR 0x414252C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI 0x4142530 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI 0x4142534 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY 0x4142538 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY 0x414253C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED 0x4142540 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED 0x4142544 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_RAZWI_ERR_RESP 0x4142548 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h new file mode 100644 index 000000000..f21540501 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_GLBL + * (Prototype: SOB_GLBL) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK */ +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_SHIFT 1 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_MASK 0x2 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_SHIFT 2 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_MASK 0x4 + +/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE */ +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK 0x7 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_SHIFT 4 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK 0xFFFF0 + +/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_MASK 0xFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_MASK 0xFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_ASID_SEC */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_LBW_DELAY */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_PI_SIZE */ +#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_SOB_ONLY */ +#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK 0x1 + +/* DCORE0_SYNC_MNGR_GLBL_CQ_INTR */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_SHIFT 8 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_MASK 0x100 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK 0x3F0000 + +/* DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE */ +#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2 */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_MASK 0xFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_PI */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_SEC */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_SHIFT 4 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_MASK 0x10 + +/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_LBW_DATA */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK 0x1 + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h new file mode 100644 index 000000000..c3c4991e6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h @@ -0,0 +1,1203 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_GLBL + * (Prototype: SOB_GLBL) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK 0x411E000 + +#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x411E004 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L 0x411E008 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H 0x411E00C + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_L 0x411E020 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_H 0x411E024 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC 0x411E030 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x411E034 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DELAY 0x411E038 + +#define mmDCORE0_SYNC_MNGR_GLBL_PI_SIZE 0x411E03C + +#define mmDCORE0_SYNC_MNGR_GLBL_SOB_ONLY 0x411E040 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR 0x411E044 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x411E048 + +#define mmDCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x411E04C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x411E050 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x411E054 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x411E058 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x411E05C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x411E060 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x411E064 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x411E068 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x411E06C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x411E070 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x411E074 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x411E078 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x411E07C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x411E080 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x411E084 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x411E088 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x411E08C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x411E090 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x411E094 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x411E098 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x411E09C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x411E0A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x411E0A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x411E0A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x411E0AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x411E0B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x411E0B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x411E0B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x411E0BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x411E0C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x411E0C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x411E0C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x411E0CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x411E0D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x411E0D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x411E0D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x411E0DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x411E0E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x411E0E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x411E0E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x411E0EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x411E0F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x411E0F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x411E0F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x411E0FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x411E100 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x411E104 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x411E108 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x411E10C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x411E110 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x411E114 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x411E118 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x411E11C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x411E120 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x411E124 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x411E128 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x411E12C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x411E130 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x411E134 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x411E138 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x411E13C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x411E140 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x411E144 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x411E148 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x411E14C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x411E150 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x411E154 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x411E158 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x411E15C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x411E160 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x411E164 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x411E168 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x411E16C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x411E170 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x411E174 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x411E178 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x411E17C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x411E180 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x411E184 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x411E188 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x411E18C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x411E190 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x411E194 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x411E198 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x411E19C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x411E1A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x411E1A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x411E1A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x411E1AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x411E1B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x411E1B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x411E1B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x411E1BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x411E1C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x411E1C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x411E1C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x411E1CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x411E1D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x411E1D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x411E1D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x411E1DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x411E1E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x411E1E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x411E1E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x411E1EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x411E1F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x411E1F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x411E1F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x411E1FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x411E200 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x411E204 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x411E208 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x411E20C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x411E210 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x411E214 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x411E218 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x411E21C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x411E220 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x411E224 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x411E228 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x411E22C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x411E230 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x411E234 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x411E238 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x411E23C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x411E240 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x411E244 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x411E248 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x411E24C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x411E250 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x411E254 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x411E258 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x411E25C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x411E260 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x411E264 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x411E268 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x411E26C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x411E270 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x411E274 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x411E278 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x411E27C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x411E280 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x411E284 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x411E288 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x411E28C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x411E290 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x411E294 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x411E298 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x411E29C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x411E2A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x411E2A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x411E2A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x411E2AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x411E2B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x411E2B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x411E2B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x411E2BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x411E2C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x411E2C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x411E2C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x411E2CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x411E2D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x411E2D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x411E2D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x411E2DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x411E2E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x411E2E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x411E2E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x411E2EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x411E2F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x411E2F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x411E2F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x411E2FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x411E300 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x411E304 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x411E308 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x411E30C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x411E310 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x411E314 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x411E318 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x411E31C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x411E320 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x411E324 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x411E328 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x411E32C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x411E330 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x411E334 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x411E338 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x411E33C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x411E340 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x411E344 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x411E348 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x411E34C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0 0x411E350 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1 0x411E354 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_2 0x411E358 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_3 0x411E35C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_4 0x411E360 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_5 0x411E364 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_6 0x411E368 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_7 0x411E36C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_8 0x411E370 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_9 0x411E374 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_10 0x411E378 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_11 0x411E37C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_12 0x411E380 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_13 0x411E384 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_14 0x411E388 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_15 0x411E38C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_16 0x411E390 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_17 0x411E394 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_18 0x411E398 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_19 0x411E39C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_20 0x411E3A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_21 0x411E3A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_22 0x411E3A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_23 0x411E3AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_24 0x411E3B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_25 0x411E3B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_26 0x411E3B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_27 0x411E3BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_28 0x411E3C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_29 0x411E3C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_30 0x411E3C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_31 0x411E3CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_32 0x411E3D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_33 0x411E3D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_34 0x411E3D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_35 0x411E3DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_36 0x411E3E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_37 0x411E3E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_38 0x411E3E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_39 0x411E3EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_40 0x411E3F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_41 0x411E3F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_42 0x411E3F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_43 0x411E3FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_44 0x411E400 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_45 0x411E404 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_46 0x411E408 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_47 0x411E40C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_48 0x411E410 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_49 0x411E414 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_50 0x411E418 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_51 0x411E41C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_52 0x411E420 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_53 0x411E424 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_54 0x411E428 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_55 0x411E42C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_56 0x411E430 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_57 0x411E434 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_58 0x411E438 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_59 0x411E43C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_60 0x411E440 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_61 0x411E444 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_62 0x411E448 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63 0x411E44C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_0 0x411E450 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_1 0x411E454 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_2 0x411E458 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_3 0x411E45C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_4 0x411E460 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_5 0x411E464 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_6 0x411E468 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_7 0x411E46C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_8 0x411E470 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_9 0x411E474 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_10 0x411E478 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_11 0x411E47C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_12 0x411E480 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_13 0x411E484 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_14 0x411E488 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_15 0x411E48C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_16 0x411E490 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_17 0x411E494 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_18 0x411E498 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_19 0x411E49C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_20 0x411E4A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_21 0x411E4A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_22 0x411E4A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_23 0x411E4AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_24 0x411E4B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_25 0x411E4B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_26 0x411E4B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_27 0x411E4BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_28 0x411E4C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_29 0x411E4C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_30 0x411E4C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_31 0x411E4CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_32 0x411E4D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_33 0x411E4D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_34 0x411E4D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_35 0x411E4DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_36 0x411E4E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_37 0x411E4E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_38 0x411E4E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_39 0x411E4EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_40 0x411E4F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_41 0x411E4F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_42 0x411E4F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_43 0x411E4FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_44 0x411E500 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_45 0x411E504 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_46 0x411E508 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_47 0x411E50C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_48 0x411E510 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_49 0x411E514 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_50 0x411E518 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_51 0x411E51C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_52 0x411E520 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_53 0x411E524 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_54 0x411E528 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_55 0x411E52C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_56 0x411E530 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_57 0x411E534 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_58 0x411E538 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_59 0x411E53C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_60 0x411E540 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_61 0x411E544 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_62 0x411E548 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_63 0x411E54C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x411E550 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x411E554 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x411E558 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x411E55C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x411E560 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x411E564 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x411E568 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x411E56C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x411E570 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x411E574 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x411E578 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x411E57C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x411E580 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x411E584 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x411E588 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x411E58C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x411E590 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x411E594 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x411E598 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x411E59C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x411E5A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x411E5A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x411E5A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x411E5AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x411E5B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x411E5B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x411E5B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x411E5BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x411E5C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x411E5C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x411E5C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x411E5CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x411E5D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x411E5D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x411E5D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x411E5DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x411E5E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x411E5E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x411E5E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x411E5EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x411E5F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x411E5F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x411E5F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x411E5FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x411E600 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x411E604 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x411E608 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x411E60C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x411E610 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x411E614 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x411E618 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x411E61C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x411E620 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x411E624 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x411E628 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x411E62C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x411E630 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x411E634 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x411E638 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x411E63C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x411E640 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x411E644 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x411E648 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x411E64C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x411E650 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x411E654 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x411E658 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x411E65C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x411E660 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x411E664 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x411E668 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x411E66C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x411E670 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x411E674 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x411E678 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x411E67C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x411E680 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x411E684 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x411E688 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x411E68C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x411E690 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x411E694 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x411E698 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x411E69C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x411E6A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x411E6A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x411E6A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x411E6AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x411E6B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x411E6B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x411E6B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x411E6BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x411E6C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x411E6C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x411E6C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x411E6CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x411E6D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x411E6D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x411E6D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x411E6DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x411E6E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x411E6E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x411E6E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x411E6EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x411E6F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x411E6F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x411E6F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x411E6FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x411E700 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x411E704 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x411E708 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x411E70C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x411E710 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x411E714 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x411E718 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x411E71C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x411E720 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x411E724 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x411E728 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x411E72C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x411E730 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x411E734 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x411E738 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x411E73C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x411E740 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x411E744 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x411E748 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x411E74C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 0x411E750 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1 0x411E754 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_2 0x411E758 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_3 0x411E75C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_4 0x411E760 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_5 0x411E764 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_6 0x411E768 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_7 0x411E76C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_8 0x411E770 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_9 0x411E774 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_10 0x411E778 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_11 0x411E77C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_12 0x411E780 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_13 0x411E784 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_14 0x411E788 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_15 0x411E78C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_16 0x411E790 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_17 0x411E794 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_18 0x411E798 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_19 0x411E79C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_20 0x411E7A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_21 0x411E7A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_22 0x411E7A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_23 0x411E7AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_24 0x411E7B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_25 0x411E7B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_26 0x411E7B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_27 0x411E7BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_28 0x411E7C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_29 0x411E7C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_30 0x411E7C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_31 0x411E7CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_32 0x411E7D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_33 0x411E7D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_34 0x411E7D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_35 0x411E7DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_36 0x411E7E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_37 0x411E7E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_38 0x411E7E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_39 0x411E7EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_40 0x411E7F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_41 0x411E7F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_42 0x411E7F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_43 0x411E7FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_44 0x411E800 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_45 0x411E804 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_46 0x411E808 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_47 0x411E80C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_48 0x411E810 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_49 0x411E814 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_50 0x411E818 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_51 0x411E81C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_52 0x411E820 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_53 0x411E824 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_54 0x411E828 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_55 0x411E82C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_56 0x411E830 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_57 0x411E834 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_58 0x411E838 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_59 0x411E83C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_60 0x411E840 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_61 0x411E844 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_62 0x411E848 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63 0x411E84C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x411E850 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x411E854 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x411E858 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x411E85C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x411E860 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x411E864 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x411E868 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x411E86C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x411E870 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x411E874 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x411E878 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x411E87C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x411E880 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x411E884 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x411E888 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x411E88C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x411E890 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x411E894 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x411E898 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x411E89C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x411E8A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x411E8A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x411E8A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x411E8AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x411E8B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x411E8B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x411E8B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x411E8BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x411E8C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x411E8C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x411E8C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x411E8CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x411E8D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x411E8D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x411E8D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x411E8DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x411E8E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x411E8E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x411E8E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x411E8EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x411E8F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x411E8F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x411E8F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x411E8FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x411E900 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x411E904 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x411E908 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x411E90C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x411E910 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x411E914 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x411E918 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x411E91C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x411E920 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x411E924 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x411E928 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x411E92C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x411E930 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x411E934 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x411E938 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x411E93C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x411E940 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x411E944 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x411E948 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x411E94C + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h new file mode 100644 index 000000000..76b273a41 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_MASK 0x3FF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT 16 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_MASK 0x3FF0000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_MASK 0xF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_MASK 0x70 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_MASK 0x1F +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_SHIFT 8 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_MASK 0xF00 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_MASK 0x1 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h new file mode 100644 index 000000000..0bddc7343 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID 0x411FA80 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP 0x411FA84 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x411FA88 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP 0x411FA8C + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x411FA90 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x411FA94 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS 0x411FA98 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD 0x411FA9C + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x411FAA0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE 0x411FAA4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD 0x411FAA8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x411FAB0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x411FAB4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x411FAB8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x411FABC + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD 0x411FAC0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK 0x411FAC4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD 0x411FAC8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD 0x411FACC + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h new file mode 100644 index 000000000..3a5b27df0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_OBJS + * (Prototype: SOB_OBJS) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_OBJS_SOB_OBJ */ +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK 0x7FFF +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_SHIFT 24 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_MASK 0x1000000 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_SHIFT 30 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_MASK 0x40000000 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT 31 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK 0x80000000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_ARM */ +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK 0xFF +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_SHIFT 8 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK 0xFF00 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_SHIFT 16 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK 0x10000 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_SHIFT 17 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK 0xFFFE0000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_CONFIG */ +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_MASK 0x1 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_SHIFT 4 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK 0x10 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_SHIFT 5 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK 0x60 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_SHIFT 8 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK 0x100 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_SHIFT 16 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_MASK 0xF0000 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_SHIFT 31 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_MASK 0x80000000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_STATUS */ +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_MASK 0x1 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_SHIFT 1 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_MASK 0x1FE +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_SHIFT 9 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_MASK 0x200 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_SHIFT 10 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_MASK 0x400 + +/* DCORE0_SYNC_MNGR_OBJS_SM_SEC */ +#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_SM_PRIV */ +#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h new file mode 100644 index 000000000..8f082a1c9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h @@ -0,0 +1,43543 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_OBJS + * (Prototype: SOB_OBJS) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4100000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4100004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x4100008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x4100010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x4100014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x4100018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x4100020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_10 0x4100028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_11 0x410002C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_12 0x4100030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_13 0x4100034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_14 0x4100038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_15 0x410003C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_16 0x4100040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_17 0x4100044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_18 0x4100048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_19 0x410004C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_20 0x4100050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_21 0x4100054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_22 0x4100058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_23 0x410005C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_24 0x4100060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_25 0x4100064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_26 0x4100068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_27 0x410006C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_28 0x4100070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_29 0x4100074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_30 0x4100078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_31 0x410007C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_32 0x4100080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_33 0x4100084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_34 0x4100088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_35 0x410008C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_36 0x4100090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_37 0x4100094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_38 0x4100098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_39 0x410009C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_40 0x41000A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_41 0x41000A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_42 0x41000A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_43 0x41000AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_44 0x41000B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_45 0x41000B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_46 0x41000B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_47 0x41000BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_48 0x41000C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_49 0x41000C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_50 0x41000C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_51 0x41000CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_52 0x41000D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_53 0x41000D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_54 0x41000D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_55 0x41000DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_56 0x41000E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_57 0x41000E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_58 0x41000E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_59 0x41000EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_60 0x41000F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_61 0x41000F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_62 0x41000F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_63 0x41000FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_64 0x4100100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_65 0x4100104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_66 0x4100108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_67 0x410010C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_68 0x4100110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_69 0x4100114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_70 0x4100118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_71 0x410011C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_72 0x4100120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_73 0x4100124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_74 0x4100128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_75 0x410012C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_76 0x4100130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_77 0x4100134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_78 0x4100138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_79 0x410013C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_80 0x4100140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_81 0x4100144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_82 0x4100148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_83 0x410014C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_84 0x4100150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_85 0x4100154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_86 0x4100158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_87 0x410015C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_88 0x4100160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_89 0x4100164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_90 0x4100168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_91 0x410016C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_92 0x4100170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_93 0x4100174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_94 0x4100178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_95 0x410017C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_96 0x4100180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_97 0x4100184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_98 0x4100188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_99 0x410018C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_100 0x4100190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_101 0x4100194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_102 0x4100198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_103 0x410019C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_104 0x41001A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_105 0x41001A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_106 0x41001A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_107 0x41001AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_108 0x41001B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_109 0x41001B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_110 0x41001B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_111 0x41001BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_112 0x41001C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_113 0x41001C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_114 0x41001C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_115 0x41001CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_116 0x41001D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_117 0x41001D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_118 0x41001D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_119 0x41001DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_120 0x41001E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_121 0x41001E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_122 0x41001E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_123 0x41001EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_124 0x41001F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_125 0x41001F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_126 0x41001F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_127 0x41001FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_128 0x4100200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_129 0x4100204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_130 0x4100208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_131 0x410020C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_132 0x4100210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_133 0x4100214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_134 0x4100218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_135 0x410021C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_136 0x4100220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_137 0x4100224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_138 0x4100228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_139 0x410022C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_140 0x4100230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_141 0x4100234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_142 0x4100238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_143 0x410023C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_144 0x4100240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_145 0x4100244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_146 0x4100248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_147 0x410024C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_148 0x4100250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_149 0x4100254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_150 0x4100258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_151 0x410025C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_152 0x4100260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_153 0x4100264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_154 0x4100268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_155 0x410026C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_156 0x4100270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_157 0x4100274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_158 0x4100278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_159 0x410027C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_160 0x4100280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_161 0x4100284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_162 0x4100288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_163 0x410028C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_164 0x4100290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_165 0x4100294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_166 0x4100298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_167 0x410029C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_168 0x41002A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_169 0x41002A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_170 0x41002A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_171 0x41002AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_172 0x41002B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_173 0x41002B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_174 0x41002B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_175 0x41002BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_176 0x41002C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_177 0x41002C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_178 0x41002C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_179 0x41002CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_180 0x41002D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_181 0x41002D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_182 0x41002D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_183 0x41002DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_184 0x41002E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_185 0x41002E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_186 0x41002E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_187 0x41002EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_188 0x41002F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_189 0x41002F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_190 0x41002F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_191 0x41002FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_192 0x4100300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_193 0x4100304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_194 0x4100308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_195 0x410030C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_196 0x4100310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_197 0x4100314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_198 0x4100318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_199 0x410031C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_200 0x4100320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_201 0x4100324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_202 0x4100328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_203 0x410032C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_204 0x4100330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_205 0x4100334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_206 0x4100338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_207 0x410033C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_208 0x4100340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_209 0x4100344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_210 0x4100348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_211 0x410034C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_212 0x4100350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_213 0x4100354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_214 0x4100358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_215 0x410035C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_216 0x4100360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_217 0x4100364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_218 0x4100368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_219 0x410036C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_220 0x4100370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_221 0x4100374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_222 0x4100378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_223 0x410037C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_224 0x4100380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_225 0x4100384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_226 0x4100388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_227 0x410038C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_228 0x4100390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_229 0x4100394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_230 0x4100398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_231 0x410039C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_232 0x41003A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_233 0x41003A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_234 0x41003A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_235 0x41003AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_236 0x41003B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_237 0x41003B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_238 0x41003B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_239 0x41003BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_240 0x41003C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_241 0x41003C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_242 0x41003C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_243 0x41003CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_244 0x41003D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_245 0x41003D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_246 0x41003D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_247 0x41003DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_248 0x41003E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_249 0x41003E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_250 0x41003E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_251 0x41003EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_252 0x41003F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_253 0x41003F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_254 0x41003F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_255 0x41003FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_256 0x4100400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_257 0x4100404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_258 0x4100408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_259 0x410040C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_260 0x4100410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_261 0x4100414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_262 0x4100418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_263 0x410041C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_264 0x4100420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_265 0x4100424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_266 0x4100428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_267 0x410042C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_268 0x4100430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_269 0x4100434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_270 0x4100438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_271 0x410043C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_272 0x4100440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_273 0x4100444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_274 0x4100448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_275 0x410044C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_276 0x4100450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_277 0x4100454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_278 0x4100458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_279 0x410045C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_280 0x4100460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_281 0x4100464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_282 0x4100468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_283 0x410046C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_284 0x4100470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_285 0x4100474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_286 0x4100478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_287 0x410047C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_288 0x4100480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_289 0x4100484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_290 0x4100488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_291 0x410048C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_292 0x4100490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_293 0x4100494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_294 0x4100498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_295 0x410049C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_296 0x41004A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_297 0x41004A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_298 0x41004A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_299 0x41004AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_300 0x41004B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_301 0x41004B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_302 0x41004B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_303 0x41004BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_304 0x41004C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_305 0x41004C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_306 0x41004C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_307 0x41004CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_308 0x41004D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_309 0x41004D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_310 0x41004D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_311 0x41004DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_312 0x41004E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_313 0x41004E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_314 0x41004E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_315 0x41004EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_316 0x41004F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_317 0x41004F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_318 0x41004F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_319 0x41004FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_320 0x4100500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_321 0x4100504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_322 0x4100508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_323 0x410050C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_324 0x4100510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_325 0x4100514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_326 0x4100518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_327 0x410051C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_328 0x4100520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_329 0x4100524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_330 0x4100528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_331 0x410052C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_332 0x4100530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_333 0x4100534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_334 0x4100538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_335 0x410053C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_336 0x4100540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_337 0x4100544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_338 0x4100548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_339 0x410054C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_340 0x4100550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_341 0x4100554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_342 0x4100558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_343 0x410055C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_344 0x4100560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_345 0x4100564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_346 0x4100568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_347 0x410056C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_348 0x4100570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_349 0x4100574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_350 0x4100578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_351 0x410057C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_352 0x4100580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_353 0x4100584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_354 0x4100588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_355 0x410058C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_356 0x4100590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_357 0x4100594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_358 0x4100598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_359 0x410059C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_360 0x41005A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_361 0x41005A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_362 0x41005A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_363 0x41005AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_364 0x41005B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_365 0x41005B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_366 0x41005B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_367 0x41005BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_368 0x41005C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_369 0x41005C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_370 0x41005C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_371 0x41005CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_372 0x41005D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_373 0x41005D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_374 0x41005D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_375 0x41005DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_376 0x41005E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_377 0x41005E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_378 0x41005E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_379 0x41005EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_380 0x41005F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_381 0x41005F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_382 0x41005F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_383 0x41005FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_384 0x4100600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_385 0x4100604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_386 0x4100608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_387 0x410060C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_388 0x4100610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_389 0x4100614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_390 0x4100618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_391 0x410061C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_392 0x4100620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_393 0x4100624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_394 0x4100628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_395 0x410062C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_396 0x4100630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_397 0x4100634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_398 0x4100638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_399 0x410063C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_400 0x4100640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_401 0x4100644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_402 0x4100648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_403 0x410064C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_404 0x4100650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_405 0x4100654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_406 0x4100658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_407 0x410065C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_408 0x4100660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_409 0x4100664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_410 0x4100668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_411 0x410066C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_412 0x4100670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_413 0x4100674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_414 0x4100678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_415 0x410067C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_416 0x4100680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_417 0x4100684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_418 0x4100688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_419 0x410068C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_420 0x4100690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_421 0x4100694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_422 0x4100698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_423 0x410069C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_424 0x41006A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_425 0x41006A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_426 0x41006A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_427 0x41006AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_428 0x41006B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_429 0x41006B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_430 0x41006B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_431 0x41006BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_432 0x41006C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_433 0x41006C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_434 0x41006C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_435 0x41006CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_436 0x41006D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_437 0x41006D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_438 0x41006D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_439 0x41006DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_440 0x41006E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_441 0x41006E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_442 0x41006E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_443 0x41006EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_444 0x41006F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_445 0x41006F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_446 0x41006F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_447 0x41006FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_448 0x4100700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_449 0x4100704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_450 0x4100708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_451 0x410070C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_452 0x4100710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_453 0x4100714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_454 0x4100718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_455 0x410071C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_456 0x4100720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_457 0x4100724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_458 0x4100728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_459 0x410072C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_460 0x4100730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_461 0x4100734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_462 0x4100738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_463 0x410073C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_464 0x4100740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_465 0x4100744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_466 0x4100748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_467 0x410074C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_468 0x4100750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_469 0x4100754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_470 0x4100758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_471 0x410075C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_472 0x4100760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_473 0x4100764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_474 0x4100768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_475 0x410076C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_476 0x4100770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_477 0x4100774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_478 0x4100778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_479 0x410077C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_480 0x4100780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_481 0x4100784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_482 0x4100788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_483 0x410078C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_484 0x4100790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_485 0x4100794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_486 0x4100798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_487 0x410079C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_488 0x41007A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_489 0x41007A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_490 0x41007A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_491 0x41007AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_492 0x41007B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_493 0x41007B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_494 0x41007B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_495 0x41007BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_496 0x41007C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_497 0x41007C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_498 0x41007C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_499 0x41007CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_500 0x41007D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_501 0x41007D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_502 0x41007D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_503 0x41007DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_504 0x41007E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_505 0x41007E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_506 0x41007E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_507 0x41007EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_508 0x41007F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_509 0x41007F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_510 0x41007F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_511 0x41007FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_512 0x4100800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_513 0x4100804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_514 0x4100808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_515 0x410080C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_516 0x4100810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_517 0x4100814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_518 0x4100818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_519 0x410081C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_520 0x4100820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_521 0x4100824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_522 0x4100828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_523 0x410082C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_524 0x4100830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_525 0x4100834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_526 0x4100838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_527 0x410083C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_528 0x4100840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_529 0x4100844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_530 0x4100848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_531 0x410084C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_532 0x4100850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_533 0x4100854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_534 0x4100858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_535 0x410085C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_536 0x4100860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_537 0x4100864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_538 0x4100868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_539 0x410086C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_540 0x4100870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_541 0x4100874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_542 0x4100878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_543 0x410087C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_544 0x4100880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_545 0x4100884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_546 0x4100888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_547 0x410088C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_548 0x4100890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_549 0x4100894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_550 0x4100898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_551 0x410089C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_552 0x41008A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_553 0x41008A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_554 0x41008A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_555 0x41008AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_556 0x41008B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_557 0x41008B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_558 0x41008B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_559 0x41008BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_560 0x41008C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_561 0x41008C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_562 0x41008C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_563 0x41008CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_564 0x41008D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_565 0x41008D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_566 0x41008D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_567 0x41008DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_568 0x41008E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_569 0x41008E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_570 0x41008E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_571 0x41008EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_572 0x41008F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_573 0x41008F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_574 0x41008F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_575 0x41008FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_576 0x4100900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_577 0x4100904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_578 0x4100908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_579 0x410090C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_580 0x4100910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_581 0x4100914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_582 0x4100918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_583 0x410091C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_584 0x4100920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_585 0x4100924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_586 0x4100928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_587 0x410092C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_588 0x4100930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_589 0x4100934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_590 0x4100938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_591 0x410093C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_592 0x4100940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_593 0x4100944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_594 0x4100948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_595 0x410094C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_596 0x4100950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_597 0x4100954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_598 0x4100958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_599 0x410095C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_600 0x4100960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_601 0x4100964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_602 0x4100968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_603 0x410096C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_604 0x4100970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_605 0x4100974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_606 0x4100978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_607 0x410097C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_608 0x4100980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_609 0x4100984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_610 0x4100988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_611 0x410098C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_612 0x4100990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_613 0x4100994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_614 0x4100998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_615 0x410099C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_616 0x41009A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_617 0x41009A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_618 0x41009A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_619 0x41009AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_620 0x41009B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_621 0x41009B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_622 0x41009B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_623 0x41009BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_624 0x41009C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_625 0x41009C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_626 0x41009C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_627 0x41009CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_628 0x41009D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_629 0x41009D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_630 0x41009D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_631 0x41009DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_632 0x41009E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_633 0x41009E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_634 0x41009E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_635 0x41009EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_636 0x41009F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_637 0x41009F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_638 0x41009F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_639 0x41009FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_640 0x4100A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_641 0x4100A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_642 0x4100A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_643 0x4100A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_644 0x4100A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_645 0x4100A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_646 0x4100A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_647 0x4100A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_648 0x4100A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_649 0x4100A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_650 0x4100A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_651 0x4100A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_652 0x4100A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_653 0x4100A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_654 0x4100A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_655 0x4100A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_656 0x4100A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_657 0x4100A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_658 0x4100A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_659 0x4100A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_660 0x4100A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_661 0x4100A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_662 0x4100A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_663 0x4100A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_664 0x4100A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_665 0x4100A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_666 0x4100A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_667 0x4100A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_668 0x4100A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_669 0x4100A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_670 0x4100A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_671 0x4100A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_672 0x4100A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_673 0x4100A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_674 0x4100A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_675 0x4100A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_676 0x4100A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_677 0x4100A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_678 0x4100A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_679 0x4100A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_680 0x4100AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_681 0x4100AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_682 0x4100AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_683 0x4100AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_684 0x4100AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_685 0x4100AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_686 0x4100AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_687 0x4100ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_688 0x4100AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_689 0x4100AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_690 0x4100AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_691 0x4100ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_692 0x4100AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_693 0x4100AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_694 0x4100AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_695 0x4100ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_696 0x4100AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_697 0x4100AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_698 0x4100AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_699 0x4100AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_700 0x4100AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_701 0x4100AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_702 0x4100AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_703 0x4100AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_704 0x4100B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_705 0x4100B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_706 0x4100B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_707 0x4100B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_708 0x4100B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_709 0x4100B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_710 0x4100B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_711 0x4100B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_712 0x4100B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_713 0x4100B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_714 0x4100B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_715 0x4100B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_716 0x4100B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_717 0x4100B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_718 0x4100B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_719 0x4100B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_720 0x4100B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_721 0x4100B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_722 0x4100B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_723 0x4100B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_724 0x4100B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_725 0x4100B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_726 0x4100B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_727 0x4100B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_728 0x4100B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_729 0x4100B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_730 0x4100B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_731 0x4100B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_732 0x4100B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_733 0x4100B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_734 0x4100B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_735 0x4100B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_736 0x4100B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_737 0x4100B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_738 0x4100B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_739 0x4100B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_740 0x4100B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_741 0x4100B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_742 0x4100B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_743 0x4100B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_744 0x4100BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_745 0x4100BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_746 0x4100BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_747 0x4100BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_748 0x4100BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_749 0x4100BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_750 0x4100BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_751 0x4100BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_752 0x4100BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_753 0x4100BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_754 0x4100BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_755 0x4100BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_756 0x4100BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_757 0x4100BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_758 0x4100BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_759 0x4100BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_760 0x4100BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_761 0x4100BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_762 0x4100BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_763 0x4100BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_764 0x4100BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_765 0x4100BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_766 0x4100BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_767 0x4100BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_768 0x4100C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_769 0x4100C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_770 0x4100C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_771 0x4100C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_772 0x4100C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_773 0x4100C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_774 0x4100C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_775 0x4100C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_776 0x4100C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_777 0x4100C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_778 0x4100C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_779 0x4100C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_780 0x4100C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_781 0x4100C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_782 0x4100C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_783 0x4100C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_784 0x4100C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_785 0x4100C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_786 0x4100C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_787 0x4100C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_788 0x4100C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_789 0x4100C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_790 0x4100C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_791 0x4100C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_792 0x4100C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_793 0x4100C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_794 0x4100C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_795 0x4100C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_796 0x4100C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_797 0x4100C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_798 0x4100C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_799 0x4100C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_800 0x4100C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_801 0x4100C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_802 0x4100C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_803 0x4100C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_804 0x4100C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_805 0x4100C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_806 0x4100C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_807 0x4100C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_808 0x4100CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_809 0x4100CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_810 0x4100CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_811 0x4100CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_812 0x4100CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_813 0x4100CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_814 0x4100CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_815 0x4100CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_816 0x4100CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_817 0x4100CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_818 0x4100CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_819 0x4100CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_820 0x4100CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_821 0x4100CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_822 0x4100CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_823 0x4100CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_824 0x4100CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_825 0x4100CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_826 0x4100CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_827 0x4100CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_828 0x4100CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_829 0x4100CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_830 0x4100CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_831 0x4100CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_832 0x4100D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_833 0x4100D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_834 0x4100D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_835 0x4100D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_836 0x4100D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_837 0x4100D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_838 0x4100D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_839 0x4100D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_840 0x4100D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_841 0x4100D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_842 0x4100D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_843 0x4100D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_844 0x4100D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_845 0x4100D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_846 0x4100D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_847 0x4100D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_848 0x4100D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_849 0x4100D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_850 0x4100D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_851 0x4100D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_852 0x4100D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_853 0x4100D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_854 0x4100D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_855 0x4100D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_856 0x4100D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_857 0x4100D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_858 0x4100D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_859 0x4100D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_860 0x4100D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_861 0x4100D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_862 0x4100D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_863 0x4100D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_864 0x4100D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_865 0x4100D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_866 0x4100D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_867 0x4100D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_868 0x4100D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_869 0x4100D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_870 0x4100D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_871 0x4100D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_872 0x4100DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_873 0x4100DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_874 0x4100DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_875 0x4100DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_876 0x4100DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_877 0x4100DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_878 0x4100DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_879 0x4100DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_880 0x4100DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_881 0x4100DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_882 0x4100DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_883 0x4100DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_884 0x4100DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_885 0x4100DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_886 0x4100DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_887 0x4100DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_888 0x4100DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_889 0x4100DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_890 0x4100DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_891 0x4100DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_892 0x4100DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_893 0x4100DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_894 0x4100DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_895 0x4100DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_896 0x4100E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_897 0x4100E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_898 0x4100E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_899 0x4100E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_900 0x4100E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_901 0x4100E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_902 0x4100E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_903 0x4100E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_904 0x4100E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_905 0x4100E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_906 0x4100E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_907 0x4100E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_908 0x4100E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_909 0x4100E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_910 0x4100E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_911 0x4100E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_912 0x4100E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_913 0x4100E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_914 0x4100E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_915 0x4100E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_916 0x4100E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_917 0x4100E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_918 0x4100E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_919 0x4100E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_920 0x4100E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_921 0x4100E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_922 0x4100E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_923 0x4100E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_924 0x4100E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_925 0x4100E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_926 0x4100E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_927 0x4100E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_928 0x4100E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_929 0x4100E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_930 0x4100E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_931 0x4100E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_932 0x4100E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_933 0x4100E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_934 0x4100E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_935 0x4100E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_936 0x4100EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_937 0x4100EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_938 0x4100EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_939 0x4100EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_940 0x4100EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_941 0x4100EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_942 0x4100EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_943 0x4100EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_944 0x4100EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_945 0x4100EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_946 0x4100EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_947 0x4100ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_948 0x4100ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_949 0x4100ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_950 0x4100ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_951 0x4100EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_952 0x4100EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_953 0x4100EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_954 0x4100EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_955 0x4100EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_956 0x4100EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_957 0x4100EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_958 0x4100EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_959 0x4100EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_960 0x4100F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_961 0x4100F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_962 0x4100F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_963 0x4100F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_964 0x4100F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_965 0x4100F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_966 0x4100F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_967 0x4100F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_968 0x4100F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_969 0x4100F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_970 0x4100F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_971 0x4100F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_972 0x4100F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_973 0x4100F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_974 0x4100F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_975 0x4100F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_976 0x4100F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_977 0x4100F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_978 0x4100F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_979 0x4100F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_980 0x4100F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_981 0x4100F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_982 0x4100F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_983 0x4100F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_984 0x4100F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_985 0x4100F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_986 0x4100F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_987 0x4100F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_988 0x4100F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_989 0x4100F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_990 0x4100F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_991 0x4100F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_992 0x4100F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_993 0x4100F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_994 0x4100F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_995 0x4100F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_996 0x4100F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_997 0x4100F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_998 0x4100F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_999 0x4100F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1000 0x4100FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1001 0x4100FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1002 0x4100FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1003 0x4100FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1004 0x4100FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1005 0x4100FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1006 0x4100FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1007 0x4100FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1008 0x4100FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1009 0x4100FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1010 0x4100FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1011 0x4100FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1012 0x4100FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1013 0x4100FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1014 0x4100FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1015 0x4100FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1016 0x4100FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1017 0x4100FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1018 0x4100FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1019 0x4100FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1020 0x4100FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1021 0x4100FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1022 0x4100FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1023 0x4100FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1024 0x4101000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1025 0x4101004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1026 0x4101008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1027 0x410100C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1028 0x4101010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1029 0x4101014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1030 0x4101018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1031 0x410101C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1032 0x4101020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1033 0x4101024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1034 0x4101028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1035 0x410102C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1036 0x4101030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1037 0x4101034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1038 0x4101038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1039 0x410103C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1040 0x4101040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1041 0x4101044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1042 0x4101048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1043 0x410104C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1044 0x4101050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1045 0x4101054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1046 0x4101058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1047 0x410105C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1048 0x4101060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1049 0x4101064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1050 0x4101068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1051 0x410106C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1052 0x4101070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1053 0x4101074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1054 0x4101078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1055 0x410107C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1056 0x4101080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1057 0x4101084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1058 0x4101088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1059 0x410108C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1060 0x4101090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1061 0x4101094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1062 0x4101098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1063 0x410109C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1064 0x41010A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1065 0x41010A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1066 0x41010A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1067 0x41010AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1068 0x41010B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1069 0x41010B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1070 0x41010B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1071 0x41010BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1072 0x41010C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1073 0x41010C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1074 0x41010C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1075 0x41010CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1076 0x41010D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1077 0x41010D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1078 0x41010D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1079 0x41010DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1080 0x41010E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1081 0x41010E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1082 0x41010E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1083 0x41010EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1084 0x41010F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1085 0x41010F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1086 0x41010F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1087 0x41010FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1088 0x4101100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1089 0x4101104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1090 0x4101108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1091 0x410110C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1092 0x4101110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1093 0x4101114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1094 0x4101118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1095 0x410111C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1096 0x4101120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1097 0x4101124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1098 0x4101128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1099 0x410112C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1100 0x4101130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1101 0x4101134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1102 0x4101138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1103 0x410113C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1104 0x4101140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1105 0x4101144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1106 0x4101148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1107 0x410114C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1108 0x4101150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1109 0x4101154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1110 0x4101158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1111 0x410115C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1112 0x4101160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1113 0x4101164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1114 0x4101168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1115 0x410116C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1116 0x4101170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1117 0x4101174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1118 0x4101178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1119 0x410117C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1120 0x4101180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1121 0x4101184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1122 0x4101188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1123 0x410118C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1124 0x4101190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1125 0x4101194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1126 0x4101198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1127 0x410119C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1128 0x41011A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1129 0x41011A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1130 0x41011A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1131 0x41011AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1132 0x41011B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1133 0x41011B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1134 0x41011B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1135 0x41011BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1136 0x41011C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1137 0x41011C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1138 0x41011C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1139 0x41011CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1140 0x41011D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1141 0x41011D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1142 0x41011D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1143 0x41011DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1144 0x41011E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1145 0x41011E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1146 0x41011E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1147 0x41011EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1148 0x41011F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1149 0x41011F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1150 0x41011F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1151 0x41011FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1152 0x4101200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1153 0x4101204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1154 0x4101208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1155 0x410120C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1156 0x4101210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1157 0x4101214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1158 0x4101218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1159 0x410121C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1160 0x4101220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1161 0x4101224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1162 0x4101228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1163 0x410122C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1164 0x4101230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1165 0x4101234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1166 0x4101238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1167 0x410123C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1168 0x4101240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1169 0x4101244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1170 0x4101248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1171 0x410124C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1172 0x4101250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1173 0x4101254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1174 0x4101258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1175 0x410125C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1176 0x4101260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1177 0x4101264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1178 0x4101268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1179 0x410126C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1180 0x4101270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1181 0x4101274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1182 0x4101278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1183 0x410127C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1184 0x4101280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1185 0x4101284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1186 0x4101288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1187 0x410128C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1188 0x4101290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1189 0x4101294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1190 0x4101298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1191 0x410129C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1192 0x41012A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1193 0x41012A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1194 0x41012A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1195 0x41012AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1196 0x41012B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1197 0x41012B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1198 0x41012B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1199 0x41012BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1200 0x41012C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1201 0x41012C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1202 0x41012C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1203 0x41012CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1204 0x41012D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1205 0x41012D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1206 0x41012D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1207 0x41012DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1208 0x41012E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1209 0x41012E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1210 0x41012E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1211 0x41012EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1212 0x41012F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1213 0x41012F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1214 0x41012F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1215 0x41012FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1216 0x4101300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1217 0x4101304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1218 0x4101308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1219 0x410130C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1220 0x4101310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1221 0x4101314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1222 0x4101318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1223 0x410131C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1224 0x4101320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1225 0x4101324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1226 0x4101328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1227 0x410132C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1228 0x4101330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1229 0x4101334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1230 0x4101338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1231 0x410133C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1232 0x4101340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1233 0x4101344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1234 0x4101348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1235 0x410134C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1236 0x4101350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1237 0x4101354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1238 0x4101358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1239 0x410135C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1240 0x4101360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1241 0x4101364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1242 0x4101368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1243 0x410136C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1244 0x4101370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1245 0x4101374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1246 0x4101378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1247 0x410137C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1248 0x4101380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1249 0x4101384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1250 0x4101388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1251 0x410138C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1252 0x4101390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1253 0x4101394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1254 0x4101398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1255 0x410139C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1256 0x41013A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1257 0x41013A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1258 0x41013A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1259 0x41013AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1260 0x41013B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1261 0x41013B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1262 0x41013B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1263 0x41013BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1264 0x41013C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1265 0x41013C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1266 0x41013C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1267 0x41013CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1268 0x41013D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1269 0x41013D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1270 0x41013D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1271 0x41013DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1272 0x41013E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1273 0x41013E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1274 0x41013E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1275 0x41013EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1276 0x41013F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1277 0x41013F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1278 0x41013F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1279 0x41013FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1280 0x4101400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1281 0x4101404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1282 0x4101408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1283 0x410140C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1284 0x4101410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1285 0x4101414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1286 0x4101418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1287 0x410141C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1288 0x4101420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1289 0x4101424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1290 0x4101428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1291 0x410142C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1292 0x4101430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1293 0x4101434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1294 0x4101438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1295 0x410143C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1296 0x4101440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1297 0x4101444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1298 0x4101448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1299 0x410144C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1300 0x4101450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1301 0x4101454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1302 0x4101458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1303 0x410145C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1304 0x4101460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1305 0x4101464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1306 0x4101468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1307 0x410146C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1308 0x4101470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1309 0x4101474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1310 0x4101478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1311 0x410147C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1312 0x4101480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1313 0x4101484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1314 0x4101488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1315 0x410148C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1316 0x4101490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1317 0x4101494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1318 0x4101498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1319 0x410149C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1320 0x41014A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1321 0x41014A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1322 0x41014A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1323 0x41014AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1324 0x41014B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1325 0x41014B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1326 0x41014B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1327 0x41014BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1328 0x41014C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1329 0x41014C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1330 0x41014C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1331 0x41014CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1332 0x41014D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1333 0x41014D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1334 0x41014D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1335 0x41014DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1336 0x41014E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1337 0x41014E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1338 0x41014E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1339 0x41014EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1340 0x41014F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1341 0x41014F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1342 0x41014F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1343 0x41014FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1344 0x4101500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1345 0x4101504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1346 0x4101508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1347 0x410150C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1348 0x4101510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1349 0x4101514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1350 0x4101518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1351 0x410151C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1352 0x4101520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1353 0x4101524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1354 0x4101528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1355 0x410152C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1356 0x4101530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1357 0x4101534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1358 0x4101538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1359 0x410153C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1360 0x4101540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1361 0x4101544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1362 0x4101548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1363 0x410154C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1364 0x4101550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1365 0x4101554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1366 0x4101558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1367 0x410155C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1368 0x4101560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1369 0x4101564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1370 0x4101568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1371 0x410156C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1372 0x4101570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1373 0x4101574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1374 0x4101578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1375 0x410157C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1376 0x4101580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1377 0x4101584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1378 0x4101588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1379 0x410158C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1380 0x4101590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1381 0x4101594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1382 0x4101598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1383 0x410159C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1384 0x41015A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1385 0x41015A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1386 0x41015A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1387 0x41015AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1388 0x41015B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1389 0x41015B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1390 0x41015B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1391 0x41015BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1392 0x41015C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1393 0x41015C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1394 0x41015C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1395 0x41015CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1396 0x41015D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1397 0x41015D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1398 0x41015D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1399 0x41015DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1400 0x41015E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1401 0x41015E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1402 0x41015E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1403 0x41015EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1404 0x41015F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1405 0x41015F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1406 0x41015F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1407 0x41015FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1408 0x4101600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1409 0x4101604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1410 0x4101608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1411 0x410160C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1412 0x4101610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1413 0x4101614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1414 0x4101618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1415 0x410161C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1416 0x4101620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1417 0x4101624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1418 0x4101628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1419 0x410162C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1420 0x4101630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1421 0x4101634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1422 0x4101638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1423 0x410163C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1424 0x4101640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1425 0x4101644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1426 0x4101648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1427 0x410164C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1428 0x4101650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1429 0x4101654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1430 0x4101658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1431 0x410165C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1432 0x4101660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1433 0x4101664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1434 0x4101668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1435 0x410166C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1436 0x4101670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1437 0x4101674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1438 0x4101678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1439 0x410167C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1440 0x4101680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1441 0x4101684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1442 0x4101688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1443 0x410168C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1444 0x4101690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1445 0x4101694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1446 0x4101698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1447 0x410169C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1448 0x41016A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1449 0x41016A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1450 0x41016A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1451 0x41016AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1452 0x41016B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1453 0x41016B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1454 0x41016B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1455 0x41016BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1456 0x41016C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1457 0x41016C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1458 0x41016C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1459 0x41016CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1460 0x41016D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1461 0x41016D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1462 0x41016D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1463 0x41016DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1464 0x41016E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1465 0x41016E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1466 0x41016E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1467 0x41016EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1468 0x41016F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1469 0x41016F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1470 0x41016F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1471 0x41016FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1472 0x4101700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1473 0x4101704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1474 0x4101708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1475 0x410170C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1476 0x4101710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1477 0x4101714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1478 0x4101718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1479 0x410171C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1480 0x4101720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1481 0x4101724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1482 0x4101728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1483 0x410172C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1484 0x4101730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1485 0x4101734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1486 0x4101738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1487 0x410173C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1488 0x4101740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1489 0x4101744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1490 0x4101748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1491 0x410174C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1492 0x4101750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1493 0x4101754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1494 0x4101758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1495 0x410175C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1496 0x4101760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1497 0x4101764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1498 0x4101768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1499 0x410176C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1500 0x4101770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1501 0x4101774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1502 0x4101778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1503 0x410177C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1504 0x4101780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1505 0x4101784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1506 0x4101788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1507 0x410178C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1508 0x4101790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1509 0x4101794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1510 0x4101798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1511 0x410179C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1512 0x41017A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1513 0x41017A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1514 0x41017A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1515 0x41017AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1516 0x41017B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1517 0x41017B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1518 0x41017B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1519 0x41017BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1520 0x41017C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1521 0x41017C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1522 0x41017C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1523 0x41017CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1524 0x41017D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1525 0x41017D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1526 0x41017D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1527 0x41017DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1528 0x41017E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1529 0x41017E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1530 0x41017E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1531 0x41017EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1532 0x41017F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1533 0x41017F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1534 0x41017F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1535 0x41017FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1536 0x4101800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1537 0x4101804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1538 0x4101808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1539 0x410180C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1540 0x4101810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1541 0x4101814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1542 0x4101818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1543 0x410181C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1544 0x4101820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1545 0x4101824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1546 0x4101828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1547 0x410182C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1548 0x4101830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1549 0x4101834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1550 0x4101838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1551 0x410183C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1552 0x4101840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1553 0x4101844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1554 0x4101848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1555 0x410184C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1556 0x4101850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1557 0x4101854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1558 0x4101858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1559 0x410185C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1560 0x4101860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1561 0x4101864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1562 0x4101868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1563 0x410186C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1564 0x4101870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1565 0x4101874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1566 0x4101878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1567 0x410187C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1568 0x4101880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1569 0x4101884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1570 0x4101888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1571 0x410188C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1572 0x4101890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1573 0x4101894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1574 0x4101898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1575 0x410189C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1576 0x41018A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1577 0x41018A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1578 0x41018A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1579 0x41018AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1580 0x41018B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1581 0x41018B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1582 0x41018B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1583 0x41018BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1584 0x41018C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1585 0x41018C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1586 0x41018C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1587 0x41018CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1588 0x41018D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1589 0x41018D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1590 0x41018D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1591 0x41018DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1592 0x41018E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1593 0x41018E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1594 0x41018E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1595 0x41018EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1596 0x41018F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1597 0x41018F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1598 0x41018F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1599 0x41018FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1600 0x4101900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1601 0x4101904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1602 0x4101908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1603 0x410190C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1604 0x4101910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1605 0x4101914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1606 0x4101918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1607 0x410191C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1608 0x4101920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1609 0x4101924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1610 0x4101928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1611 0x410192C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1612 0x4101930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1613 0x4101934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1614 0x4101938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1615 0x410193C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1616 0x4101940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1617 0x4101944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1618 0x4101948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1619 0x410194C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1620 0x4101950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1621 0x4101954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1622 0x4101958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1623 0x410195C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1624 0x4101960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1625 0x4101964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1626 0x4101968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1627 0x410196C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1628 0x4101970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1629 0x4101974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1630 0x4101978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1631 0x410197C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1632 0x4101980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1633 0x4101984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1634 0x4101988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1635 0x410198C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1636 0x4101990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1637 0x4101994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1638 0x4101998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1639 0x410199C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1640 0x41019A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1641 0x41019A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1642 0x41019A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1643 0x41019AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1644 0x41019B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1645 0x41019B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1646 0x41019B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1647 0x41019BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1648 0x41019C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1649 0x41019C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1650 0x41019C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1651 0x41019CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1652 0x41019D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1653 0x41019D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1654 0x41019D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1655 0x41019DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1656 0x41019E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1657 0x41019E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1658 0x41019E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1659 0x41019EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1660 0x41019F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1661 0x41019F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1662 0x41019F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1663 0x41019FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1664 0x4101A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1665 0x4101A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1666 0x4101A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1667 0x4101A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1668 0x4101A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1669 0x4101A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1670 0x4101A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1671 0x4101A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1672 0x4101A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1673 0x4101A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1674 0x4101A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1675 0x4101A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1676 0x4101A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1677 0x4101A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1678 0x4101A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1679 0x4101A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1680 0x4101A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1681 0x4101A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1682 0x4101A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1683 0x4101A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1684 0x4101A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1685 0x4101A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1686 0x4101A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1687 0x4101A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1688 0x4101A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1689 0x4101A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1690 0x4101A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1691 0x4101A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1692 0x4101A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1693 0x4101A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1694 0x4101A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1695 0x4101A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1696 0x4101A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1697 0x4101A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1698 0x4101A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1699 0x4101A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1700 0x4101A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1701 0x4101A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1702 0x4101A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1703 0x4101A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1704 0x4101AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1705 0x4101AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1706 0x4101AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1707 0x4101AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1708 0x4101AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1709 0x4101AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1710 0x4101AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1711 0x4101ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1712 0x4101AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1713 0x4101AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1714 0x4101AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1715 0x4101ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1716 0x4101AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1717 0x4101AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1718 0x4101AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1719 0x4101ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1720 0x4101AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1721 0x4101AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1722 0x4101AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1723 0x4101AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1724 0x4101AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1725 0x4101AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1726 0x4101AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1727 0x4101AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1728 0x4101B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1729 0x4101B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1730 0x4101B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1731 0x4101B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1732 0x4101B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1733 0x4101B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1734 0x4101B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1735 0x4101B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1736 0x4101B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1737 0x4101B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1738 0x4101B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1739 0x4101B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1740 0x4101B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1741 0x4101B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1742 0x4101B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1743 0x4101B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1744 0x4101B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1745 0x4101B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1746 0x4101B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1747 0x4101B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1748 0x4101B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1749 0x4101B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1750 0x4101B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1751 0x4101B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1752 0x4101B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1753 0x4101B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1754 0x4101B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1755 0x4101B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1756 0x4101B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1757 0x4101B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1758 0x4101B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1759 0x4101B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1760 0x4101B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1761 0x4101B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1762 0x4101B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1763 0x4101B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1764 0x4101B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1765 0x4101B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1766 0x4101B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1767 0x4101B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1768 0x4101BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1769 0x4101BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1770 0x4101BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1771 0x4101BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1772 0x4101BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1773 0x4101BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1774 0x4101BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1775 0x4101BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1776 0x4101BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1777 0x4101BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1778 0x4101BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1779 0x4101BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1780 0x4101BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1781 0x4101BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1782 0x4101BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1783 0x4101BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1784 0x4101BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1785 0x4101BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1786 0x4101BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1787 0x4101BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1788 0x4101BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1789 0x4101BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1790 0x4101BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1791 0x4101BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1792 0x4101C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1793 0x4101C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1794 0x4101C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1795 0x4101C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1796 0x4101C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1797 0x4101C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1798 0x4101C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1799 0x4101C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1800 0x4101C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1801 0x4101C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1802 0x4101C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1803 0x4101C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1804 0x4101C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1805 0x4101C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1806 0x4101C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1807 0x4101C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1808 0x4101C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1809 0x4101C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1810 0x4101C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1811 0x4101C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1812 0x4101C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1813 0x4101C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1814 0x4101C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1815 0x4101C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1816 0x4101C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1817 0x4101C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1818 0x4101C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1819 0x4101C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1820 0x4101C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1821 0x4101C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1822 0x4101C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1823 0x4101C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1824 0x4101C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1825 0x4101C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1826 0x4101C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1827 0x4101C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1828 0x4101C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1829 0x4101C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1830 0x4101C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1831 0x4101C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1832 0x4101CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1833 0x4101CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1834 0x4101CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1835 0x4101CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1836 0x4101CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1837 0x4101CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1838 0x4101CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1839 0x4101CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1840 0x4101CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1841 0x4101CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1842 0x4101CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1843 0x4101CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1844 0x4101CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1845 0x4101CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1846 0x4101CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1847 0x4101CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1848 0x4101CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1849 0x4101CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1850 0x4101CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1851 0x4101CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1852 0x4101CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1853 0x4101CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1854 0x4101CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1855 0x4101CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1856 0x4101D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1857 0x4101D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1858 0x4101D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1859 0x4101D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1860 0x4101D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1861 0x4101D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1862 0x4101D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1863 0x4101D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1864 0x4101D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1865 0x4101D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1866 0x4101D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1867 0x4101D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1868 0x4101D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1869 0x4101D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1870 0x4101D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1871 0x4101D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1872 0x4101D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1873 0x4101D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1874 0x4101D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1875 0x4101D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1876 0x4101D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1877 0x4101D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1878 0x4101D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1879 0x4101D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1880 0x4101D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1881 0x4101D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1882 0x4101D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1883 0x4101D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1884 0x4101D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1885 0x4101D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1886 0x4101D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1887 0x4101D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1888 0x4101D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1889 0x4101D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1890 0x4101D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1891 0x4101D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1892 0x4101D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1893 0x4101D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1894 0x4101D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1895 0x4101D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1896 0x4101DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1897 0x4101DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1898 0x4101DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1899 0x4101DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1900 0x4101DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1901 0x4101DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1902 0x4101DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1903 0x4101DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1904 0x4101DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1905 0x4101DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1906 0x4101DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1907 0x4101DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1908 0x4101DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1909 0x4101DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1910 0x4101DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1911 0x4101DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1912 0x4101DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1913 0x4101DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1914 0x4101DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1915 0x4101DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1916 0x4101DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1917 0x4101DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1918 0x4101DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1919 0x4101DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1920 0x4101E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1921 0x4101E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1922 0x4101E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1923 0x4101E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1924 0x4101E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1925 0x4101E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1926 0x4101E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1927 0x4101E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1928 0x4101E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1929 0x4101E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1930 0x4101E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1931 0x4101E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1932 0x4101E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1933 0x4101E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1934 0x4101E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1935 0x4101E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1936 0x4101E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1937 0x4101E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1938 0x4101E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1939 0x4101E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1940 0x4101E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1941 0x4101E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1942 0x4101E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1943 0x4101E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1944 0x4101E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1945 0x4101E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1946 0x4101E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1947 0x4101E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1948 0x4101E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1949 0x4101E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1950 0x4101E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1951 0x4101E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1952 0x4101E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1953 0x4101E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1954 0x4101E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1955 0x4101E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1956 0x4101E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1957 0x4101E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1958 0x4101E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1959 0x4101E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1960 0x4101EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1961 0x4101EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1962 0x4101EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1963 0x4101EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1964 0x4101EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1965 0x4101EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1966 0x4101EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1967 0x4101EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1968 0x4101EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1969 0x4101EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1970 0x4101EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1971 0x4101ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1972 0x4101ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1973 0x4101ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1974 0x4101ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1975 0x4101EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1976 0x4101EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1977 0x4101EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1978 0x4101EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1979 0x4101EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1980 0x4101EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1981 0x4101EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1982 0x4101EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1983 0x4101EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1984 0x4101F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1985 0x4101F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1986 0x4101F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1987 0x4101F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1988 0x4101F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1989 0x4101F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1990 0x4101F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1991 0x4101F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1992 0x4101F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1993 0x4101F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1994 0x4101F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1995 0x4101F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1996 0x4101F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1997 0x4101F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1998 0x4101F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1999 0x4101F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2000 0x4101F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2001 0x4101F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2002 0x4101F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2003 0x4101F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2004 0x4101F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2005 0x4101F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2006 0x4101F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2007 0x4101F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2008 0x4101F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2009 0x4101F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2010 0x4101F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2011 0x4101F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2012 0x4101F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2013 0x4101F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2014 0x4101F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2015 0x4101F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2016 0x4101F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2017 0x4101F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2018 0x4101F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2019 0x4101F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2020 0x4101F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2021 0x4101F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2022 0x4101F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2023 0x4101F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2024 0x4101FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2025 0x4101FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2026 0x4101FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2027 0x4101FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2028 0x4101FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2029 0x4101FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2030 0x4101FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2031 0x4101FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2032 0x4101FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2033 0x4101FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2034 0x4101FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2035 0x4101FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2036 0x4101FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2037 0x4101FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2038 0x4101FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2039 0x4101FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2040 0x4101FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2041 0x4101FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2042 0x4101FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2043 0x4101FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2044 0x4101FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2045 0x4101FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2046 0x4101FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4101FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2048 0x4102000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2049 0x4102004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2050 0x4102008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2051 0x410200C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2052 0x4102010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2053 0x4102014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2054 0x4102018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2055 0x410201C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2056 0x4102020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2057 0x4102024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2058 0x4102028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2059 0x410202C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2060 0x4102030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2061 0x4102034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2062 0x4102038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2063 0x410203C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2064 0x4102040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2065 0x4102044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2066 0x4102048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2067 0x410204C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2068 0x4102050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2069 0x4102054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2070 0x4102058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2071 0x410205C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2072 0x4102060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2073 0x4102064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2074 0x4102068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2075 0x410206C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2076 0x4102070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2077 0x4102074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2078 0x4102078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2079 0x410207C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2080 0x4102080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2081 0x4102084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2082 0x4102088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2083 0x410208C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2084 0x4102090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2085 0x4102094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2086 0x4102098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2087 0x410209C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2088 0x41020A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2089 0x41020A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2090 0x41020A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2091 0x41020AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2092 0x41020B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2093 0x41020B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2094 0x41020B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2095 0x41020BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2096 0x41020C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2097 0x41020C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2098 0x41020C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2099 0x41020CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2100 0x41020D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2101 0x41020D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2102 0x41020D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2103 0x41020DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2104 0x41020E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2105 0x41020E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2106 0x41020E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2107 0x41020EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2108 0x41020F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2109 0x41020F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2110 0x41020F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2111 0x41020FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2112 0x4102100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2113 0x4102104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2114 0x4102108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2115 0x410210C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2116 0x4102110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2117 0x4102114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2118 0x4102118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2119 0x410211C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2120 0x4102120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2121 0x4102124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2122 0x4102128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2123 0x410212C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2124 0x4102130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2125 0x4102134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2126 0x4102138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2127 0x410213C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2128 0x4102140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2129 0x4102144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2130 0x4102148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2131 0x410214C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2132 0x4102150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2133 0x4102154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2134 0x4102158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2135 0x410215C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2136 0x4102160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2137 0x4102164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2138 0x4102168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2139 0x410216C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2140 0x4102170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2141 0x4102174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2142 0x4102178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2143 0x410217C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2144 0x4102180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2145 0x4102184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2146 0x4102188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2147 0x410218C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2148 0x4102190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2149 0x4102194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2150 0x4102198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2151 0x410219C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2152 0x41021A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2153 0x41021A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2154 0x41021A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2155 0x41021AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2156 0x41021B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2157 0x41021B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2158 0x41021B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2159 0x41021BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2160 0x41021C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2161 0x41021C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2162 0x41021C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2163 0x41021CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2164 0x41021D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2165 0x41021D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2166 0x41021D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2167 0x41021DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2168 0x41021E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2169 0x41021E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2170 0x41021E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2171 0x41021EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2172 0x41021F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2173 0x41021F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2174 0x41021F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2175 0x41021FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2176 0x4102200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2177 0x4102204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2178 0x4102208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2179 0x410220C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2180 0x4102210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2181 0x4102214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2182 0x4102218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2183 0x410221C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2184 0x4102220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2185 0x4102224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2186 0x4102228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2187 0x410222C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2188 0x4102230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2189 0x4102234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2190 0x4102238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2191 0x410223C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2192 0x4102240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2193 0x4102244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2194 0x4102248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2195 0x410224C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2196 0x4102250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2197 0x4102254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2198 0x4102258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2199 0x410225C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2200 0x4102260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2201 0x4102264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2202 0x4102268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2203 0x410226C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2204 0x4102270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2205 0x4102274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2206 0x4102278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2207 0x410227C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2208 0x4102280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2209 0x4102284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2210 0x4102288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2211 0x410228C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2212 0x4102290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2213 0x4102294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2214 0x4102298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2215 0x410229C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2216 0x41022A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2217 0x41022A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2218 0x41022A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2219 0x41022AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2220 0x41022B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2221 0x41022B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2222 0x41022B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2223 0x41022BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2224 0x41022C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2225 0x41022C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2226 0x41022C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2227 0x41022CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2228 0x41022D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2229 0x41022D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2230 0x41022D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2231 0x41022DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2232 0x41022E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2233 0x41022E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2234 0x41022E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2235 0x41022EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2236 0x41022F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2237 0x41022F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2238 0x41022F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2239 0x41022FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2240 0x4102300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2241 0x4102304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2242 0x4102308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2243 0x410230C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2244 0x4102310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2245 0x4102314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2246 0x4102318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2247 0x410231C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2248 0x4102320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2249 0x4102324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2250 0x4102328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2251 0x410232C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2252 0x4102330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2253 0x4102334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2254 0x4102338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2255 0x410233C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2256 0x4102340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2257 0x4102344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2258 0x4102348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2259 0x410234C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2260 0x4102350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2261 0x4102354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2262 0x4102358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2263 0x410235C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2264 0x4102360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2265 0x4102364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2266 0x4102368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2267 0x410236C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2268 0x4102370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2269 0x4102374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2270 0x4102378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2271 0x410237C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2272 0x4102380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2273 0x4102384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2274 0x4102388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2275 0x410238C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2276 0x4102390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2277 0x4102394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2278 0x4102398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2279 0x410239C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2280 0x41023A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2281 0x41023A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2282 0x41023A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2283 0x41023AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2284 0x41023B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2285 0x41023B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2286 0x41023B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2287 0x41023BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2288 0x41023C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2289 0x41023C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2290 0x41023C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2291 0x41023CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2292 0x41023D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2293 0x41023D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2294 0x41023D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2295 0x41023DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2296 0x41023E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2297 0x41023E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2298 0x41023E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2299 0x41023EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2300 0x41023F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2301 0x41023F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2302 0x41023F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2303 0x41023FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2304 0x4102400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2305 0x4102404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2306 0x4102408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2307 0x410240C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2308 0x4102410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2309 0x4102414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2310 0x4102418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2311 0x410241C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2312 0x4102420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2313 0x4102424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2314 0x4102428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2315 0x410242C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2316 0x4102430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2317 0x4102434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2318 0x4102438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2319 0x410243C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2320 0x4102440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2321 0x4102444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2322 0x4102448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2323 0x410244C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2324 0x4102450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2325 0x4102454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2326 0x4102458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2327 0x410245C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2328 0x4102460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2329 0x4102464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2330 0x4102468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2331 0x410246C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2332 0x4102470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2333 0x4102474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2334 0x4102478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2335 0x410247C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2336 0x4102480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2337 0x4102484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2338 0x4102488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2339 0x410248C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2340 0x4102490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2341 0x4102494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2342 0x4102498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2343 0x410249C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2344 0x41024A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2345 0x41024A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2346 0x41024A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2347 0x41024AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2348 0x41024B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2349 0x41024B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2350 0x41024B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2351 0x41024BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2352 0x41024C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2353 0x41024C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2354 0x41024C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2355 0x41024CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2356 0x41024D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2357 0x41024D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2358 0x41024D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2359 0x41024DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2360 0x41024E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2361 0x41024E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2362 0x41024E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2363 0x41024EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2364 0x41024F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2365 0x41024F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2366 0x41024F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2367 0x41024FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2368 0x4102500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2369 0x4102504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2370 0x4102508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2371 0x410250C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2372 0x4102510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2373 0x4102514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2374 0x4102518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2375 0x410251C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2376 0x4102520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2377 0x4102524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2378 0x4102528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2379 0x410252C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2380 0x4102530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2381 0x4102534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2382 0x4102538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2383 0x410253C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2384 0x4102540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2385 0x4102544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2386 0x4102548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2387 0x410254C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2388 0x4102550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2389 0x4102554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2390 0x4102558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2391 0x410255C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2392 0x4102560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2393 0x4102564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2394 0x4102568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2395 0x410256C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2396 0x4102570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2397 0x4102574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2398 0x4102578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2399 0x410257C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2400 0x4102580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2401 0x4102584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2402 0x4102588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2403 0x410258C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2404 0x4102590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2405 0x4102594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2406 0x4102598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2407 0x410259C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2408 0x41025A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2409 0x41025A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2410 0x41025A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2411 0x41025AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2412 0x41025B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2413 0x41025B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2414 0x41025B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2415 0x41025BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2416 0x41025C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2417 0x41025C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2418 0x41025C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2419 0x41025CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2420 0x41025D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2421 0x41025D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2422 0x41025D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2423 0x41025DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2424 0x41025E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2425 0x41025E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2426 0x41025E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2427 0x41025EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2428 0x41025F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2429 0x41025F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2430 0x41025F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2431 0x41025FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2432 0x4102600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2433 0x4102604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2434 0x4102608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2435 0x410260C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2436 0x4102610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2437 0x4102614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2438 0x4102618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2439 0x410261C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2440 0x4102620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2441 0x4102624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2442 0x4102628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2443 0x410262C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2444 0x4102630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2445 0x4102634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2446 0x4102638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2447 0x410263C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2448 0x4102640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2449 0x4102644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2450 0x4102648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2451 0x410264C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2452 0x4102650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2453 0x4102654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2454 0x4102658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2455 0x410265C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2456 0x4102660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2457 0x4102664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2458 0x4102668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2459 0x410266C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2460 0x4102670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2461 0x4102674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2462 0x4102678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2463 0x410267C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2464 0x4102680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2465 0x4102684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2466 0x4102688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2467 0x410268C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2468 0x4102690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2469 0x4102694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2470 0x4102698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2471 0x410269C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2472 0x41026A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2473 0x41026A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2474 0x41026A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2475 0x41026AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2476 0x41026B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2477 0x41026B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2478 0x41026B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2479 0x41026BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2480 0x41026C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2481 0x41026C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2482 0x41026C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2483 0x41026CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2484 0x41026D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2485 0x41026D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2486 0x41026D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2487 0x41026DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2488 0x41026E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2489 0x41026E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2490 0x41026E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2491 0x41026EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2492 0x41026F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2493 0x41026F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2494 0x41026F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2495 0x41026FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2496 0x4102700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2497 0x4102704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2498 0x4102708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2499 0x410270C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2500 0x4102710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2501 0x4102714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2502 0x4102718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2503 0x410271C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2504 0x4102720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2505 0x4102724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2506 0x4102728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2507 0x410272C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2508 0x4102730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2509 0x4102734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2510 0x4102738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2511 0x410273C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2512 0x4102740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2513 0x4102744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2514 0x4102748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2515 0x410274C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2516 0x4102750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2517 0x4102754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2518 0x4102758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2519 0x410275C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2520 0x4102760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2521 0x4102764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2522 0x4102768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2523 0x410276C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2524 0x4102770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2525 0x4102774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2526 0x4102778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2527 0x410277C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2528 0x4102780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2529 0x4102784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2530 0x4102788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2531 0x410278C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2532 0x4102790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2533 0x4102794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2534 0x4102798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2535 0x410279C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2536 0x41027A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2537 0x41027A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2538 0x41027A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2539 0x41027AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2540 0x41027B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2541 0x41027B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2542 0x41027B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2543 0x41027BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2544 0x41027C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2545 0x41027C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2546 0x41027C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2547 0x41027CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2548 0x41027D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2549 0x41027D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2550 0x41027D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2551 0x41027DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2552 0x41027E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2553 0x41027E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2554 0x41027E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2555 0x41027EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2556 0x41027F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2557 0x41027F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2558 0x41027F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2559 0x41027FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2560 0x4102800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2561 0x4102804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2562 0x4102808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2563 0x410280C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2564 0x4102810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2565 0x4102814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2566 0x4102818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2567 0x410281C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2568 0x4102820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2569 0x4102824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2570 0x4102828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2571 0x410282C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2572 0x4102830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2573 0x4102834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2574 0x4102838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2575 0x410283C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2576 0x4102840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2577 0x4102844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2578 0x4102848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2579 0x410284C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2580 0x4102850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2581 0x4102854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2582 0x4102858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2583 0x410285C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2584 0x4102860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2585 0x4102864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2586 0x4102868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2587 0x410286C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2588 0x4102870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2589 0x4102874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2590 0x4102878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2591 0x410287C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2592 0x4102880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2593 0x4102884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2594 0x4102888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2595 0x410288C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2596 0x4102890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2597 0x4102894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2598 0x4102898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2599 0x410289C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2600 0x41028A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2601 0x41028A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2602 0x41028A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2603 0x41028AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2604 0x41028B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2605 0x41028B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2606 0x41028B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2607 0x41028BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2608 0x41028C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2609 0x41028C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2610 0x41028C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2611 0x41028CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2612 0x41028D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2613 0x41028D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2614 0x41028D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2615 0x41028DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2616 0x41028E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2617 0x41028E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2618 0x41028E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2619 0x41028EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2620 0x41028F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2621 0x41028F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2622 0x41028F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2623 0x41028FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2624 0x4102900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2625 0x4102904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2626 0x4102908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2627 0x410290C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2628 0x4102910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2629 0x4102914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2630 0x4102918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2631 0x410291C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2632 0x4102920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2633 0x4102924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2634 0x4102928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2635 0x410292C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2636 0x4102930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2637 0x4102934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2638 0x4102938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2639 0x410293C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2640 0x4102940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2641 0x4102944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2642 0x4102948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2643 0x410294C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2644 0x4102950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2645 0x4102954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2646 0x4102958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2647 0x410295C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2648 0x4102960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2649 0x4102964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2650 0x4102968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2651 0x410296C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2652 0x4102970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2653 0x4102974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2654 0x4102978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2655 0x410297C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2656 0x4102980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2657 0x4102984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2658 0x4102988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2659 0x410298C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2660 0x4102990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2661 0x4102994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2662 0x4102998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2663 0x410299C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2664 0x41029A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2665 0x41029A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2666 0x41029A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2667 0x41029AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2668 0x41029B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2669 0x41029B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2670 0x41029B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2671 0x41029BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2672 0x41029C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2673 0x41029C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2674 0x41029C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2675 0x41029CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2676 0x41029D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2677 0x41029D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2678 0x41029D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2679 0x41029DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2680 0x41029E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2681 0x41029E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2682 0x41029E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2683 0x41029EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2684 0x41029F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2685 0x41029F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2686 0x41029F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2687 0x41029FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2688 0x4102A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2689 0x4102A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2690 0x4102A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2691 0x4102A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2692 0x4102A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2693 0x4102A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2694 0x4102A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2695 0x4102A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2696 0x4102A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2697 0x4102A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2698 0x4102A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2699 0x4102A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2700 0x4102A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2701 0x4102A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2702 0x4102A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2703 0x4102A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2704 0x4102A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2705 0x4102A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2706 0x4102A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2707 0x4102A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2708 0x4102A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2709 0x4102A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2710 0x4102A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2711 0x4102A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2712 0x4102A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2713 0x4102A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2714 0x4102A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2715 0x4102A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2716 0x4102A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2717 0x4102A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2718 0x4102A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2719 0x4102A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2720 0x4102A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2721 0x4102A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2722 0x4102A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2723 0x4102A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2724 0x4102A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2725 0x4102A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2726 0x4102A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2727 0x4102A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2728 0x4102AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2729 0x4102AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2730 0x4102AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2731 0x4102AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2732 0x4102AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2733 0x4102AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2734 0x4102AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2735 0x4102ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2736 0x4102AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2737 0x4102AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2738 0x4102AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2739 0x4102ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2740 0x4102AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2741 0x4102AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2742 0x4102AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2743 0x4102ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2744 0x4102AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2745 0x4102AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2746 0x4102AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2747 0x4102AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2748 0x4102AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2749 0x4102AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2750 0x4102AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2751 0x4102AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2752 0x4102B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2753 0x4102B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2754 0x4102B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2755 0x4102B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2756 0x4102B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2757 0x4102B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2758 0x4102B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2759 0x4102B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2760 0x4102B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2761 0x4102B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2762 0x4102B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2763 0x4102B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2764 0x4102B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2765 0x4102B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2766 0x4102B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2767 0x4102B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2768 0x4102B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2769 0x4102B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2770 0x4102B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2771 0x4102B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2772 0x4102B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2773 0x4102B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2774 0x4102B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2775 0x4102B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2776 0x4102B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2777 0x4102B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2778 0x4102B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2779 0x4102B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2780 0x4102B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2781 0x4102B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2782 0x4102B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2783 0x4102B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2784 0x4102B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2785 0x4102B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2786 0x4102B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2787 0x4102B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2788 0x4102B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2789 0x4102B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2790 0x4102B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2791 0x4102B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2792 0x4102BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2793 0x4102BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2794 0x4102BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2795 0x4102BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2796 0x4102BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2797 0x4102BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2798 0x4102BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2799 0x4102BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2800 0x4102BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2801 0x4102BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2802 0x4102BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2803 0x4102BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2804 0x4102BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2805 0x4102BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2806 0x4102BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2807 0x4102BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2808 0x4102BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2809 0x4102BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2810 0x4102BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2811 0x4102BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2812 0x4102BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2813 0x4102BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2814 0x4102BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2815 0x4102BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2816 0x4102C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2817 0x4102C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2818 0x4102C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2819 0x4102C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2820 0x4102C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2821 0x4102C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2822 0x4102C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2823 0x4102C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2824 0x4102C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2825 0x4102C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2826 0x4102C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2827 0x4102C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2828 0x4102C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2829 0x4102C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2830 0x4102C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2831 0x4102C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2832 0x4102C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2833 0x4102C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2834 0x4102C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2835 0x4102C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2836 0x4102C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2837 0x4102C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2838 0x4102C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2839 0x4102C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2840 0x4102C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2841 0x4102C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2842 0x4102C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2843 0x4102C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2844 0x4102C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2845 0x4102C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2846 0x4102C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2847 0x4102C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2848 0x4102C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2849 0x4102C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2850 0x4102C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2851 0x4102C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2852 0x4102C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2853 0x4102C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2854 0x4102C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2855 0x4102C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2856 0x4102CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2857 0x4102CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2858 0x4102CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2859 0x4102CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2860 0x4102CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2861 0x4102CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2862 0x4102CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2863 0x4102CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2864 0x4102CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2865 0x4102CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2866 0x4102CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2867 0x4102CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2868 0x4102CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2869 0x4102CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2870 0x4102CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2871 0x4102CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2872 0x4102CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2873 0x4102CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2874 0x4102CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2875 0x4102CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2876 0x4102CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2877 0x4102CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2878 0x4102CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2879 0x4102CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2880 0x4102D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2881 0x4102D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2882 0x4102D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2883 0x4102D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2884 0x4102D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2885 0x4102D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2886 0x4102D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2887 0x4102D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2888 0x4102D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2889 0x4102D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2890 0x4102D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2891 0x4102D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2892 0x4102D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2893 0x4102D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2894 0x4102D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2895 0x4102D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2896 0x4102D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2897 0x4102D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2898 0x4102D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2899 0x4102D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2900 0x4102D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2901 0x4102D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2902 0x4102D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2903 0x4102D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2904 0x4102D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2905 0x4102D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2906 0x4102D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2907 0x4102D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2908 0x4102D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2909 0x4102D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2910 0x4102D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2911 0x4102D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2912 0x4102D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2913 0x4102D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2914 0x4102D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2915 0x4102D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2916 0x4102D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2917 0x4102D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2918 0x4102D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2919 0x4102D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2920 0x4102DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2921 0x4102DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2922 0x4102DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2923 0x4102DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2924 0x4102DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2925 0x4102DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2926 0x4102DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2927 0x4102DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2928 0x4102DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2929 0x4102DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2930 0x4102DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2931 0x4102DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2932 0x4102DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2933 0x4102DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2934 0x4102DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2935 0x4102DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2936 0x4102DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2937 0x4102DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2938 0x4102DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2939 0x4102DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2940 0x4102DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2941 0x4102DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2942 0x4102DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2943 0x4102DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2944 0x4102E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2945 0x4102E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2946 0x4102E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2947 0x4102E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2948 0x4102E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2949 0x4102E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2950 0x4102E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2951 0x4102E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2952 0x4102E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2953 0x4102E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2954 0x4102E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2955 0x4102E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2956 0x4102E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2957 0x4102E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2958 0x4102E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2959 0x4102E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2960 0x4102E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2961 0x4102E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2962 0x4102E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2963 0x4102E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2964 0x4102E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2965 0x4102E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2966 0x4102E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2967 0x4102E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2968 0x4102E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2969 0x4102E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2970 0x4102E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2971 0x4102E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2972 0x4102E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2973 0x4102E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2974 0x4102E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2975 0x4102E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2976 0x4102E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2977 0x4102E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2978 0x4102E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2979 0x4102E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2980 0x4102E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2981 0x4102E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2982 0x4102E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2983 0x4102E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2984 0x4102EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2985 0x4102EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2986 0x4102EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2987 0x4102EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2988 0x4102EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2989 0x4102EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2990 0x4102EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2991 0x4102EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2992 0x4102EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2993 0x4102EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2994 0x4102EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2995 0x4102ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2996 0x4102ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2997 0x4102ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2998 0x4102ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2999 0x4102EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3000 0x4102EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3001 0x4102EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3002 0x4102EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3003 0x4102EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3004 0x4102EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3005 0x4102EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3006 0x4102EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3007 0x4102EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3008 0x4102F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3009 0x4102F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3010 0x4102F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3011 0x4102F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3012 0x4102F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3013 0x4102F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3014 0x4102F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3015 0x4102F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3016 0x4102F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3017 0x4102F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3018 0x4102F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3019 0x4102F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3020 0x4102F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3021 0x4102F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3022 0x4102F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3023 0x4102F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3024 0x4102F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3025 0x4102F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3026 0x4102F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3027 0x4102F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3028 0x4102F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3029 0x4102F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3030 0x4102F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3031 0x4102F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3032 0x4102F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3033 0x4102F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3034 0x4102F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3035 0x4102F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3036 0x4102F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3037 0x4102F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3038 0x4102F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3039 0x4102F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3040 0x4102F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3041 0x4102F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3042 0x4102F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3043 0x4102F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3044 0x4102F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3045 0x4102F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3046 0x4102F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3047 0x4102F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3048 0x4102FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3049 0x4102FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3050 0x4102FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3051 0x4102FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3052 0x4102FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3053 0x4102FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3054 0x4102FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3055 0x4102FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3056 0x4102FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3057 0x4102FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3058 0x4102FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3059 0x4102FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3060 0x4102FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3061 0x4102FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3062 0x4102FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3063 0x4102FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3064 0x4102FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3065 0x4102FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3066 0x4102FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3067 0x4102FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3068 0x4102FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3069 0x4102FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3070 0x4102FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3071 0x4102FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3072 0x4103000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3073 0x4103004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3074 0x4103008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3075 0x410300C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3076 0x4103010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3077 0x4103014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3078 0x4103018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3079 0x410301C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3080 0x4103020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3081 0x4103024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3082 0x4103028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3083 0x410302C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3084 0x4103030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3085 0x4103034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3086 0x4103038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3087 0x410303C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3088 0x4103040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3089 0x4103044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3090 0x4103048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3091 0x410304C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3092 0x4103050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3093 0x4103054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3094 0x4103058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3095 0x410305C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3096 0x4103060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3097 0x4103064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3098 0x4103068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3099 0x410306C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3100 0x4103070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3101 0x4103074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3102 0x4103078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3103 0x410307C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3104 0x4103080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3105 0x4103084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3106 0x4103088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3107 0x410308C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3108 0x4103090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3109 0x4103094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3110 0x4103098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3111 0x410309C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3112 0x41030A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3113 0x41030A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3114 0x41030A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3115 0x41030AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3116 0x41030B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3117 0x41030B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3118 0x41030B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3119 0x41030BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3120 0x41030C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3121 0x41030C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3122 0x41030C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3123 0x41030CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3124 0x41030D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3125 0x41030D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3126 0x41030D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3127 0x41030DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3128 0x41030E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3129 0x41030E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3130 0x41030E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3131 0x41030EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3132 0x41030F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3133 0x41030F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3134 0x41030F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3135 0x41030FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3136 0x4103100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3137 0x4103104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3138 0x4103108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3139 0x410310C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3140 0x4103110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3141 0x4103114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3142 0x4103118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3143 0x410311C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3144 0x4103120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3145 0x4103124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3146 0x4103128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3147 0x410312C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3148 0x4103130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3149 0x4103134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3150 0x4103138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3151 0x410313C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3152 0x4103140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3153 0x4103144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3154 0x4103148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3155 0x410314C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3156 0x4103150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3157 0x4103154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3158 0x4103158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3159 0x410315C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3160 0x4103160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3161 0x4103164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3162 0x4103168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3163 0x410316C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3164 0x4103170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3165 0x4103174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3166 0x4103178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3167 0x410317C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3168 0x4103180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3169 0x4103184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3170 0x4103188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3171 0x410318C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3172 0x4103190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3173 0x4103194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3174 0x4103198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3175 0x410319C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3176 0x41031A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3177 0x41031A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3178 0x41031A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3179 0x41031AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3180 0x41031B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3181 0x41031B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3182 0x41031B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3183 0x41031BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3184 0x41031C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3185 0x41031C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3186 0x41031C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3187 0x41031CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3188 0x41031D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3189 0x41031D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3190 0x41031D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3191 0x41031DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3192 0x41031E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3193 0x41031E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3194 0x41031E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3195 0x41031EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3196 0x41031F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3197 0x41031F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3198 0x41031F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3199 0x41031FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3200 0x4103200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3201 0x4103204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3202 0x4103208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3203 0x410320C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3204 0x4103210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3205 0x4103214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3206 0x4103218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3207 0x410321C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3208 0x4103220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3209 0x4103224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3210 0x4103228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3211 0x410322C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3212 0x4103230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3213 0x4103234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3214 0x4103238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3215 0x410323C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3216 0x4103240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3217 0x4103244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3218 0x4103248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3219 0x410324C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3220 0x4103250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3221 0x4103254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3222 0x4103258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3223 0x410325C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3224 0x4103260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3225 0x4103264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3226 0x4103268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3227 0x410326C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3228 0x4103270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3229 0x4103274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3230 0x4103278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3231 0x410327C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3232 0x4103280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3233 0x4103284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3234 0x4103288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3235 0x410328C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3236 0x4103290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3237 0x4103294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3238 0x4103298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3239 0x410329C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3240 0x41032A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3241 0x41032A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3242 0x41032A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3243 0x41032AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3244 0x41032B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3245 0x41032B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3246 0x41032B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3247 0x41032BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3248 0x41032C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3249 0x41032C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3250 0x41032C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3251 0x41032CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3252 0x41032D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3253 0x41032D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3254 0x41032D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3255 0x41032DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3256 0x41032E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3257 0x41032E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3258 0x41032E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3259 0x41032EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3260 0x41032F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3261 0x41032F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3262 0x41032F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3263 0x41032FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3264 0x4103300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3265 0x4103304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3266 0x4103308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3267 0x410330C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3268 0x4103310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3269 0x4103314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3270 0x4103318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3271 0x410331C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3272 0x4103320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3273 0x4103324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3274 0x4103328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3275 0x410332C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3276 0x4103330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3277 0x4103334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3278 0x4103338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3279 0x410333C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3280 0x4103340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3281 0x4103344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3282 0x4103348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3283 0x410334C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3284 0x4103350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3285 0x4103354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3286 0x4103358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3287 0x410335C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3288 0x4103360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3289 0x4103364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3290 0x4103368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3291 0x410336C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3292 0x4103370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3293 0x4103374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3294 0x4103378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3295 0x410337C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3296 0x4103380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3297 0x4103384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3298 0x4103388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3299 0x410338C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3300 0x4103390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3301 0x4103394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3302 0x4103398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3303 0x410339C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3304 0x41033A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3305 0x41033A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3306 0x41033A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3307 0x41033AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3308 0x41033B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3309 0x41033B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3310 0x41033B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3311 0x41033BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3312 0x41033C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3313 0x41033C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3314 0x41033C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3315 0x41033CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3316 0x41033D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3317 0x41033D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3318 0x41033D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3319 0x41033DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3320 0x41033E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3321 0x41033E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3322 0x41033E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3323 0x41033EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3324 0x41033F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3325 0x41033F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3326 0x41033F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3327 0x41033FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3328 0x4103400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3329 0x4103404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3330 0x4103408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3331 0x410340C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3332 0x4103410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3333 0x4103414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3334 0x4103418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3335 0x410341C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3336 0x4103420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3337 0x4103424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3338 0x4103428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3339 0x410342C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3340 0x4103430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3341 0x4103434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3342 0x4103438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3343 0x410343C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3344 0x4103440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3345 0x4103444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3346 0x4103448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3347 0x410344C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3348 0x4103450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3349 0x4103454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3350 0x4103458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3351 0x410345C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3352 0x4103460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3353 0x4103464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3354 0x4103468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3355 0x410346C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3356 0x4103470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3357 0x4103474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3358 0x4103478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3359 0x410347C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3360 0x4103480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3361 0x4103484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3362 0x4103488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3363 0x410348C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3364 0x4103490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3365 0x4103494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3366 0x4103498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3367 0x410349C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3368 0x41034A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3369 0x41034A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3370 0x41034A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3371 0x41034AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3372 0x41034B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3373 0x41034B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3374 0x41034B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3375 0x41034BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3376 0x41034C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3377 0x41034C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3378 0x41034C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3379 0x41034CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3380 0x41034D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3381 0x41034D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3382 0x41034D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3383 0x41034DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3384 0x41034E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3385 0x41034E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3386 0x41034E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3387 0x41034EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3388 0x41034F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3389 0x41034F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3390 0x41034F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3391 0x41034FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3392 0x4103500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3393 0x4103504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3394 0x4103508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3395 0x410350C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3396 0x4103510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3397 0x4103514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3398 0x4103518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3399 0x410351C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3400 0x4103520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3401 0x4103524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3402 0x4103528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3403 0x410352C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3404 0x4103530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3405 0x4103534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3406 0x4103538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3407 0x410353C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3408 0x4103540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3409 0x4103544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3410 0x4103548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3411 0x410354C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3412 0x4103550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3413 0x4103554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3414 0x4103558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3415 0x410355C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3416 0x4103560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3417 0x4103564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3418 0x4103568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3419 0x410356C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3420 0x4103570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3421 0x4103574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3422 0x4103578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3423 0x410357C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3424 0x4103580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3425 0x4103584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3426 0x4103588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3427 0x410358C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3428 0x4103590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3429 0x4103594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3430 0x4103598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3431 0x410359C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3432 0x41035A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3433 0x41035A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3434 0x41035A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3435 0x41035AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3436 0x41035B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3437 0x41035B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3438 0x41035B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3439 0x41035BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3440 0x41035C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3441 0x41035C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3442 0x41035C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3443 0x41035CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3444 0x41035D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3445 0x41035D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3446 0x41035D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3447 0x41035DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3448 0x41035E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3449 0x41035E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3450 0x41035E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3451 0x41035EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3452 0x41035F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3453 0x41035F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3454 0x41035F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3455 0x41035FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3456 0x4103600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3457 0x4103604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3458 0x4103608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3459 0x410360C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3460 0x4103610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3461 0x4103614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3462 0x4103618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3463 0x410361C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3464 0x4103620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3465 0x4103624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3466 0x4103628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3467 0x410362C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3468 0x4103630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3469 0x4103634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3470 0x4103638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3471 0x410363C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3472 0x4103640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3473 0x4103644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3474 0x4103648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3475 0x410364C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3476 0x4103650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3477 0x4103654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3478 0x4103658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3479 0x410365C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3480 0x4103660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3481 0x4103664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3482 0x4103668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3483 0x410366C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3484 0x4103670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3485 0x4103674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3486 0x4103678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3487 0x410367C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3488 0x4103680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3489 0x4103684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3490 0x4103688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3491 0x410368C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3492 0x4103690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3493 0x4103694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3494 0x4103698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3495 0x410369C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3496 0x41036A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3497 0x41036A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3498 0x41036A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3499 0x41036AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3500 0x41036B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3501 0x41036B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3502 0x41036B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3503 0x41036BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3504 0x41036C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3505 0x41036C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3506 0x41036C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3507 0x41036CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3508 0x41036D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3509 0x41036D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3510 0x41036D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3511 0x41036DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3512 0x41036E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3513 0x41036E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3514 0x41036E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3515 0x41036EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3516 0x41036F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3517 0x41036F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3518 0x41036F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3519 0x41036FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3520 0x4103700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3521 0x4103704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3522 0x4103708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3523 0x410370C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3524 0x4103710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3525 0x4103714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3526 0x4103718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3527 0x410371C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3528 0x4103720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3529 0x4103724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3530 0x4103728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3531 0x410372C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3532 0x4103730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3533 0x4103734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3534 0x4103738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3535 0x410373C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3536 0x4103740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3537 0x4103744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3538 0x4103748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3539 0x410374C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3540 0x4103750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3541 0x4103754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3542 0x4103758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3543 0x410375C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3544 0x4103760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3545 0x4103764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3546 0x4103768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3547 0x410376C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3548 0x4103770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3549 0x4103774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3550 0x4103778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3551 0x410377C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3552 0x4103780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3553 0x4103784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3554 0x4103788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3555 0x410378C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3556 0x4103790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3557 0x4103794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3558 0x4103798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3559 0x410379C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3560 0x41037A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3561 0x41037A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3562 0x41037A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3563 0x41037AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3564 0x41037B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3565 0x41037B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3566 0x41037B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3567 0x41037BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3568 0x41037C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3569 0x41037C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3570 0x41037C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3571 0x41037CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3572 0x41037D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3573 0x41037D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3574 0x41037D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3575 0x41037DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3576 0x41037E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3577 0x41037E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3578 0x41037E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3579 0x41037EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3580 0x41037F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3581 0x41037F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3582 0x41037F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3583 0x41037FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3584 0x4103800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3585 0x4103804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3586 0x4103808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3587 0x410380C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3588 0x4103810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3589 0x4103814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3590 0x4103818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3591 0x410381C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3592 0x4103820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3593 0x4103824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3594 0x4103828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3595 0x410382C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3596 0x4103830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3597 0x4103834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3598 0x4103838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3599 0x410383C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3600 0x4103840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3601 0x4103844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3602 0x4103848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3603 0x410384C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3604 0x4103850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3605 0x4103854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3606 0x4103858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3607 0x410385C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3608 0x4103860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3609 0x4103864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3610 0x4103868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3611 0x410386C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3612 0x4103870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3613 0x4103874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3614 0x4103878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3615 0x410387C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3616 0x4103880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3617 0x4103884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3618 0x4103888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3619 0x410388C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3620 0x4103890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3621 0x4103894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3622 0x4103898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3623 0x410389C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3624 0x41038A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3625 0x41038A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3626 0x41038A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3627 0x41038AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3628 0x41038B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3629 0x41038B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3630 0x41038B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3631 0x41038BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3632 0x41038C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3633 0x41038C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3634 0x41038C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3635 0x41038CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3636 0x41038D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3637 0x41038D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3638 0x41038D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3639 0x41038DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3640 0x41038E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3641 0x41038E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3642 0x41038E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3643 0x41038EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3644 0x41038F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3645 0x41038F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3646 0x41038F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3647 0x41038FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3648 0x4103900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3649 0x4103904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3650 0x4103908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3651 0x410390C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3652 0x4103910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3653 0x4103914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3654 0x4103918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3655 0x410391C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3656 0x4103920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3657 0x4103924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3658 0x4103928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3659 0x410392C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3660 0x4103930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3661 0x4103934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3662 0x4103938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3663 0x410393C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3664 0x4103940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3665 0x4103944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3666 0x4103948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3667 0x410394C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3668 0x4103950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3669 0x4103954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3670 0x4103958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3671 0x410395C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3672 0x4103960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3673 0x4103964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3674 0x4103968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3675 0x410396C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3676 0x4103970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3677 0x4103974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3678 0x4103978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3679 0x410397C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3680 0x4103980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3681 0x4103984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3682 0x4103988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3683 0x410398C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3684 0x4103990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3685 0x4103994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3686 0x4103998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3687 0x410399C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3688 0x41039A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3689 0x41039A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3690 0x41039A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3691 0x41039AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3692 0x41039B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3693 0x41039B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3694 0x41039B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3695 0x41039BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3696 0x41039C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3697 0x41039C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3698 0x41039C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3699 0x41039CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3700 0x41039D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3701 0x41039D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3702 0x41039D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3703 0x41039DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3704 0x41039E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3705 0x41039E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3706 0x41039E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3707 0x41039EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3708 0x41039F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3709 0x41039F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3710 0x41039F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3711 0x41039FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3712 0x4103A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3713 0x4103A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3714 0x4103A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3715 0x4103A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3716 0x4103A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3717 0x4103A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3718 0x4103A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3719 0x4103A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3720 0x4103A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3721 0x4103A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3722 0x4103A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3723 0x4103A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3724 0x4103A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3725 0x4103A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3726 0x4103A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3727 0x4103A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3728 0x4103A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3729 0x4103A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3730 0x4103A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3731 0x4103A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3732 0x4103A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3733 0x4103A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3734 0x4103A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3735 0x4103A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3736 0x4103A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3737 0x4103A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3738 0x4103A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3739 0x4103A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3740 0x4103A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3741 0x4103A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3742 0x4103A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3743 0x4103A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3744 0x4103A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3745 0x4103A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3746 0x4103A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3747 0x4103A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3748 0x4103A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3749 0x4103A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3750 0x4103A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3751 0x4103A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3752 0x4103AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3753 0x4103AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3754 0x4103AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3755 0x4103AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3756 0x4103AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3757 0x4103AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3758 0x4103AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3759 0x4103ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3760 0x4103AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3761 0x4103AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3762 0x4103AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3763 0x4103ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3764 0x4103AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3765 0x4103AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3766 0x4103AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3767 0x4103ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3768 0x4103AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3769 0x4103AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3770 0x4103AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3771 0x4103AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3772 0x4103AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3773 0x4103AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3774 0x4103AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3775 0x4103AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3776 0x4103B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3777 0x4103B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3778 0x4103B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3779 0x4103B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3780 0x4103B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3781 0x4103B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3782 0x4103B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3783 0x4103B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3784 0x4103B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3785 0x4103B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3786 0x4103B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3787 0x4103B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3788 0x4103B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3789 0x4103B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3790 0x4103B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3791 0x4103B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3792 0x4103B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3793 0x4103B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3794 0x4103B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3795 0x4103B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3796 0x4103B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3797 0x4103B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3798 0x4103B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3799 0x4103B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3800 0x4103B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3801 0x4103B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3802 0x4103B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3803 0x4103B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3804 0x4103B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3805 0x4103B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3806 0x4103B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3807 0x4103B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3808 0x4103B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3809 0x4103B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3810 0x4103B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3811 0x4103B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3812 0x4103B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3813 0x4103B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3814 0x4103B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3815 0x4103B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3816 0x4103BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3817 0x4103BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3818 0x4103BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3819 0x4103BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3820 0x4103BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3821 0x4103BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3822 0x4103BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3823 0x4103BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3824 0x4103BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3825 0x4103BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3826 0x4103BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3827 0x4103BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3828 0x4103BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3829 0x4103BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3830 0x4103BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3831 0x4103BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3832 0x4103BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3833 0x4103BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3834 0x4103BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3835 0x4103BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3836 0x4103BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3837 0x4103BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3838 0x4103BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3839 0x4103BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3840 0x4103C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3841 0x4103C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3842 0x4103C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3843 0x4103C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3844 0x4103C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3845 0x4103C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3846 0x4103C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3847 0x4103C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3848 0x4103C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3849 0x4103C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3850 0x4103C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3851 0x4103C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3852 0x4103C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3853 0x4103C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3854 0x4103C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3855 0x4103C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3856 0x4103C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3857 0x4103C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3858 0x4103C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3859 0x4103C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3860 0x4103C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3861 0x4103C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3862 0x4103C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3863 0x4103C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3864 0x4103C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3865 0x4103C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3866 0x4103C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3867 0x4103C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3868 0x4103C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3869 0x4103C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3870 0x4103C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3871 0x4103C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3872 0x4103C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3873 0x4103C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3874 0x4103C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3875 0x4103C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3876 0x4103C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3877 0x4103C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3878 0x4103C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3879 0x4103C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3880 0x4103CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3881 0x4103CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3882 0x4103CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3883 0x4103CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3884 0x4103CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3885 0x4103CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3886 0x4103CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3887 0x4103CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3888 0x4103CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3889 0x4103CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3890 0x4103CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3891 0x4103CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3892 0x4103CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3893 0x4103CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3894 0x4103CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3895 0x4103CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3896 0x4103CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3897 0x4103CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3898 0x4103CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3899 0x4103CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3900 0x4103CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3901 0x4103CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3902 0x4103CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3903 0x4103CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3904 0x4103D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3905 0x4103D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3906 0x4103D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3907 0x4103D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3908 0x4103D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3909 0x4103D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3910 0x4103D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3911 0x4103D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3912 0x4103D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3913 0x4103D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3914 0x4103D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3915 0x4103D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3916 0x4103D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3917 0x4103D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3918 0x4103D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3919 0x4103D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3920 0x4103D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3921 0x4103D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3922 0x4103D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3923 0x4103D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3924 0x4103D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3925 0x4103D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3926 0x4103D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3927 0x4103D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3928 0x4103D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3929 0x4103D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3930 0x4103D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3931 0x4103D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3932 0x4103D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3933 0x4103D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3934 0x4103D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3935 0x4103D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3936 0x4103D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3937 0x4103D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3938 0x4103D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3939 0x4103D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3940 0x4103D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3941 0x4103D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3942 0x4103D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3943 0x4103D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3944 0x4103DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3945 0x4103DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3946 0x4103DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3947 0x4103DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3948 0x4103DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3949 0x4103DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3950 0x4103DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3951 0x4103DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3952 0x4103DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3953 0x4103DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3954 0x4103DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3955 0x4103DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3956 0x4103DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3957 0x4103DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3958 0x4103DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3959 0x4103DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3960 0x4103DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3961 0x4103DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3962 0x4103DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3963 0x4103DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3964 0x4103DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3965 0x4103DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3966 0x4103DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3967 0x4103DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3968 0x4103E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3969 0x4103E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3970 0x4103E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3971 0x4103E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3972 0x4103E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3973 0x4103E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3974 0x4103E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3975 0x4103E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3976 0x4103E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3977 0x4103E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3978 0x4103E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3979 0x4103E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3980 0x4103E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3981 0x4103E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3982 0x4103E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3983 0x4103E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3984 0x4103E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3985 0x4103E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3986 0x4103E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3987 0x4103E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3988 0x4103E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3989 0x4103E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3990 0x4103E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3991 0x4103E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3992 0x4103E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3993 0x4103E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3994 0x4103E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3995 0x4103E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3996 0x4103E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3997 0x4103E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3998 0x4103E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3999 0x4103E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4000 0x4103E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4001 0x4103E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4002 0x4103E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4003 0x4103E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4004 0x4103E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4005 0x4103E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4006 0x4103E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4007 0x4103E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4008 0x4103EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4009 0x4103EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4010 0x4103EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4011 0x4103EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4012 0x4103EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4013 0x4103EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4014 0x4103EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4015 0x4103EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4016 0x4103EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4017 0x4103EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4018 0x4103EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4019 0x4103ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4020 0x4103ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4021 0x4103ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4022 0x4103ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4023 0x4103EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4024 0x4103EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4025 0x4103EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4026 0x4103EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4027 0x4103EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4028 0x4103EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4029 0x4103EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4030 0x4103EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4031 0x4103EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4032 0x4103F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4033 0x4103F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4034 0x4103F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4035 0x4103F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4036 0x4103F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4037 0x4103F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4038 0x4103F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4039 0x4103F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4040 0x4103F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4041 0x4103F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4042 0x4103F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4043 0x4103F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4044 0x4103F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4045 0x4103F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4046 0x4103F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4047 0x4103F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4048 0x4103F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4049 0x4103F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4050 0x4103F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4051 0x4103F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4052 0x4103F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4053 0x4103F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4054 0x4103F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4055 0x4103F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4056 0x4103F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4057 0x4103F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4058 0x4103F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4059 0x4103F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4060 0x4103F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4061 0x4103F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4062 0x4103F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4063 0x4103F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4064 0x4103F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4065 0x4103F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4066 0x4103F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4067 0x4103F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4068 0x4103F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4069 0x4103F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4070 0x4103F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4071 0x4103F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4072 0x4103FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4073 0x4103FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4074 0x4103FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4075 0x4103FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4076 0x4103FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4077 0x4103FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4078 0x4103FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4079 0x4103FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4080 0x4103FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4081 0x4103FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4082 0x4103FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4083 0x4103FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4084 0x4103FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4085 0x4103FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4086 0x4103FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4087 0x4103FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4088 0x4103FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4089 0x4103FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4090 0x4103FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4091 0x4103FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4092 0x4103FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4093 0x4103FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4094 0x4103FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4095 0x4103FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4096 0x4104000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4097 0x4104004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4098 0x4104008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4099 0x410400C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4100 0x4104010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4101 0x4104014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4102 0x4104018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4103 0x410401C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4104 0x4104020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4105 0x4104024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4106 0x4104028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4107 0x410402C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4108 0x4104030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4109 0x4104034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4110 0x4104038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4111 0x410403C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4112 0x4104040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4113 0x4104044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4114 0x4104048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4115 0x410404C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4116 0x4104050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4117 0x4104054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4118 0x4104058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4119 0x410405C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4120 0x4104060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4121 0x4104064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4122 0x4104068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4123 0x410406C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4124 0x4104070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4125 0x4104074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4126 0x4104078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4127 0x410407C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4128 0x4104080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4129 0x4104084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4130 0x4104088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4131 0x410408C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4132 0x4104090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4133 0x4104094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4134 0x4104098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4135 0x410409C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4136 0x41040A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4137 0x41040A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4138 0x41040A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4139 0x41040AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4140 0x41040B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4141 0x41040B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4142 0x41040B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4143 0x41040BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4144 0x41040C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4145 0x41040C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4146 0x41040C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4147 0x41040CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4148 0x41040D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4149 0x41040D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4150 0x41040D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4151 0x41040DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4152 0x41040E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4153 0x41040E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4154 0x41040E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4155 0x41040EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4156 0x41040F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4157 0x41040F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4158 0x41040F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4159 0x41040FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4160 0x4104100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4161 0x4104104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4162 0x4104108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4163 0x410410C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4164 0x4104110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4165 0x4104114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4166 0x4104118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4167 0x410411C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4168 0x4104120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4169 0x4104124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4170 0x4104128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4171 0x410412C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4172 0x4104130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4173 0x4104134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4174 0x4104138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4175 0x410413C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4176 0x4104140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4177 0x4104144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4178 0x4104148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4179 0x410414C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4180 0x4104150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4181 0x4104154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4182 0x4104158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4183 0x410415C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4184 0x4104160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4185 0x4104164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4186 0x4104168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4187 0x410416C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4188 0x4104170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4189 0x4104174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4190 0x4104178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4191 0x410417C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4192 0x4104180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4193 0x4104184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4194 0x4104188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4195 0x410418C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4196 0x4104190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4197 0x4104194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4198 0x4104198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4199 0x410419C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4200 0x41041A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4201 0x41041A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4202 0x41041A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4203 0x41041AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4204 0x41041B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4205 0x41041B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4206 0x41041B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4207 0x41041BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4208 0x41041C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4209 0x41041C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4210 0x41041C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4211 0x41041CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4212 0x41041D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4213 0x41041D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4214 0x41041D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4215 0x41041DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4216 0x41041E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4217 0x41041E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4218 0x41041E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4219 0x41041EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4220 0x41041F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4221 0x41041F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4222 0x41041F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4223 0x41041FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4224 0x4104200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4225 0x4104204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4226 0x4104208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4227 0x410420C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4228 0x4104210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4229 0x4104214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4230 0x4104218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4231 0x410421C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4232 0x4104220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4233 0x4104224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4234 0x4104228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4235 0x410422C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4236 0x4104230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4237 0x4104234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4238 0x4104238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4239 0x410423C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4240 0x4104240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4241 0x4104244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4242 0x4104248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4243 0x410424C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4244 0x4104250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4245 0x4104254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4246 0x4104258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4247 0x410425C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4248 0x4104260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4249 0x4104264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4250 0x4104268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4251 0x410426C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4252 0x4104270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4253 0x4104274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4254 0x4104278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4255 0x410427C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4256 0x4104280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4257 0x4104284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4258 0x4104288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4259 0x410428C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4260 0x4104290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4261 0x4104294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4262 0x4104298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4263 0x410429C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4264 0x41042A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4265 0x41042A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4266 0x41042A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4267 0x41042AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4268 0x41042B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4269 0x41042B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4270 0x41042B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4271 0x41042BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4272 0x41042C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4273 0x41042C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4274 0x41042C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4275 0x41042CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4276 0x41042D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4277 0x41042D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4278 0x41042D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4279 0x41042DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4280 0x41042E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4281 0x41042E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4282 0x41042E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4283 0x41042EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4284 0x41042F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4285 0x41042F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4286 0x41042F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4287 0x41042FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4288 0x4104300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4289 0x4104304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4290 0x4104308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4291 0x410430C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4292 0x4104310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4293 0x4104314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4294 0x4104318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4295 0x410431C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4296 0x4104320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4297 0x4104324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4298 0x4104328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4299 0x410432C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4300 0x4104330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4301 0x4104334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4302 0x4104338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4303 0x410433C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4304 0x4104340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4305 0x4104344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4306 0x4104348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4307 0x410434C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4308 0x4104350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4309 0x4104354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4310 0x4104358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4311 0x410435C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4312 0x4104360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4313 0x4104364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4314 0x4104368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4315 0x410436C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4316 0x4104370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4317 0x4104374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4318 0x4104378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4319 0x410437C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4320 0x4104380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4321 0x4104384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4322 0x4104388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4323 0x410438C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4324 0x4104390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4325 0x4104394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4326 0x4104398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4327 0x410439C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4328 0x41043A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4329 0x41043A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4330 0x41043A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4331 0x41043AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4332 0x41043B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4333 0x41043B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4334 0x41043B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4335 0x41043BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4336 0x41043C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4337 0x41043C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4338 0x41043C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4339 0x41043CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4340 0x41043D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4341 0x41043D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4342 0x41043D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4343 0x41043DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4344 0x41043E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4345 0x41043E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4346 0x41043E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4347 0x41043EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4348 0x41043F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4349 0x41043F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4350 0x41043F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4351 0x41043FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4352 0x4104400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4353 0x4104404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4354 0x4104408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4355 0x410440C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4356 0x4104410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4357 0x4104414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4358 0x4104418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4359 0x410441C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4360 0x4104420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4361 0x4104424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4362 0x4104428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4363 0x410442C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4364 0x4104430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4365 0x4104434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4366 0x4104438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4367 0x410443C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4368 0x4104440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4369 0x4104444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4370 0x4104448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4371 0x410444C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4372 0x4104450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4373 0x4104454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4374 0x4104458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4375 0x410445C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4376 0x4104460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4377 0x4104464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4378 0x4104468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4379 0x410446C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4380 0x4104470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4381 0x4104474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4382 0x4104478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4383 0x410447C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4384 0x4104480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4385 0x4104484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4386 0x4104488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4387 0x410448C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4388 0x4104490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4389 0x4104494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4390 0x4104498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4391 0x410449C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4392 0x41044A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4393 0x41044A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4394 0x41044A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4395 0x41044AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4396 0x41044B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4397 0x41044B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4398 0x41044B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4399 0x41044BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4400 0x41044C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4401 0x41044C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4402 0x41044C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4403 0x41044CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4404 0x41044D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4405 0x41044D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4406 0x41044D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4407 0x41044DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4408 0x41044E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4409 0x41044E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4410 0x41044E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4411 0x41044EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4412 0x41044F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4413 0x41044F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4414 0x41044F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4415 0x41044FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4416 0x4104500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4417 0x4104504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4418 0x4104508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4419 0x410450C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4420 0x4104510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4421 0x4104514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4422 0x4104518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4423 0x410451C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4424 0x4104520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4425 0x4104524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4426 0x4104528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4427 0x410452C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4428 0x4104530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4429 0x4104534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4430 0x4104538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4431 0x410453C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4432 0x4104540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4433 0x4104544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4434 0x4104548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4435 0x410454C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4436 0x4104550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4437 0x4104554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4438 0x4104558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4439 0x410455C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4440 0x4104560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4441 0x4104564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4442 0x4104568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4443 0x410456C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4444 0x4104570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4445 0x4104574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4446 0x4104578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4447 0x410457C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4448 0x4104580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4449 0x4104584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4450 0x4104588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4451 0x410458C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4452 0x4104590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4453 0x4104594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4454 0x4104598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4455 0x410459C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4456 0x41045A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4457 0x41045A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4458 0x41045A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4459 0x41045AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4460 0x41045B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4461 0x41045B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4462 0x41045B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4463 0x41045BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4464 0x41045C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4465 0x41045C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4466 0x41045C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4467 0x41045CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4468 0x41045D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4469 0x41045D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4470 0x41045D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4471 0x41045DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4472 0x41045E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4473 0x41045E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4474 0x41045E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4475 0x41045EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4476 0x41045F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4477 0x41045F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4478 0x41045F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4479 0x41045FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4480 0x4104600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4481 0x4104604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4482 0x4104608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4483 0x410460C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4484 0x4104610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4485 0x4104614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4486 0x4104618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4487 0x410461C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4488 0x4104620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4489 0x4104624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4490 0x4104628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4491 0x410462C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4492 0x4104630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4493 0x4104634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4494 0x4104638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4495 0x410463C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4496 0x4104640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4497 0x4104644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4498 0x4104648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4499 0x410464C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4500 0x4104650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4501 0x4104654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4502 0x4104658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4503 0x410465C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4504 0x4104660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4505 0x4104664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4506 0x4104668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4507 0x410466C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4508 0x4104670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4509 0x4104674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4510 0x4104678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4511 0x410467C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4512 0x4104680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4513 0x4104684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4514 0x4104688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4515 0x410468C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4516 0x4104690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4517 0x4104694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4518 0x4104698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4519 0x410469C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4520 0x41046A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4521 0x41046A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4522 0x41046A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4523 0x41046AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4524 0x41046B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4525 0x41046B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4526 0x41046B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4527 0x41046BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4528 0x41046C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4529 0x41046C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4530 0x41046C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4531 0x41046CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4532 0x41046D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4533 0x41046D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4534 0x41046D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4535 0x41046DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4536 0x41046E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4537 0x41046E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4538 0x41046E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4539 0x41046EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4540 0x41046F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4541 0x41046F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4542 0x41046F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4543 0x41046FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4544 0x4104700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4545 0x4104704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4546 0x4104708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4547 0x410470C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4548 0x4104710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4549 0x4104714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4550 0x4104718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4551 0x410471C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4552 0x4104720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4553 0x4104724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4554 0x4104728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4555 0x410472C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4556 0x4104730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4557 0x4104734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4558 0x4104738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4559 0x410473C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4560 0x4104740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4561 0x4104744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4562 0x4104748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4563 0x410474C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4564 0x4104750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4565 0x4104754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4566 0x4104758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4567 0x410475C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4568 0x4104760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4569 0x4104764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4570 0x4104768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4571 0x410476C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4572 0x4104770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4573 0x4104774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4574 0x4104778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4575 0x410477C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4576 0x4104780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4577 0x4104784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4578 0x4104788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4579 0x410478C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4580 0x4104790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4581 0x4104794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4582 0x4104798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4583 0x410479C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4584 0x41047A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4585 0x41047A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4586 0x41047A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4587 0x41047AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4588 0x41047B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4589 0x41047B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4590 0x41047B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4591 0x41047BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4592 0x41047C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4593 0x41047C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4594 0x41047C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4595 0x41047CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4596 0x41047D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4597 0x41047D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4598 0x41047D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4599 0x41047DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4600 0x41047E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4601 0x41047E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4602 0x41047E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4603 0x41047EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4604 0x41047F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4605 0x41047F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4606 0x41047F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4607 0x41047FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4608 0x4104800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4609 0x4104804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4610 0x4104808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4611 0x410480C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4612 0x4104810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4613 0x4104814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4614 0x4104818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4615 0x410481C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4616 0x4104820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4617 0x4104824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4618 0x4104828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4619 0x410482C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4620 0x4104830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4621 0x4104834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4622 0x4104838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4623 0x410483C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4624 0x4104840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4625 0x4104844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4626 0x4104848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4627 0x410484C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4628 0x4104850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4629 0x4104854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4630 0x4104858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4631 0x410485C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4632 0x4104860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4633 0x4104864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4634 0x4104868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4635 0x410486C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4636 0x4104870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4637 0x4104874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4638 0x4104878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4639 0x410487C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4640 0x4104880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4641 0x4104884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4642 0x4104888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4643 0x410488C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4644 0x4104890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4645 0x4104894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4646 0x4104898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4647 0x410489C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4648 0x41048A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4649 0x41048A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4650 0x41048A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4651 0x41048AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4652 0x41048B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4653 0x41048B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4654 0x41048B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4655 0x41048BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4656 0x41048C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4657 0x41048C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4658 0x41048C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4659 0x41048CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4660 0x41048D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4661 0x41048D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4662 0x41048D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4663 0x41048DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4664 0x41048E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4665 0x41048E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4666 0x41048E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4667 0x41048EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4668 0x41048F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4669 0x41048F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4670 0x41048F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4671 0x41048FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4672 0x4104900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4673 0x4104904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4674 0x4104908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4675 0x410490C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4676 0x4104910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4677 0x4104914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4678 0x4104918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4679 0x410491C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4680 0x4104920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4681 0x4104924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4682 0x4104928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4683 0x410492C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4684 0x4104930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4685 0x4104934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4686 0x4104938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4687 0x410493C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4688 0x4104940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4689 0x4104944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4690 0x4104948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4691 0x410494C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4692 0x4104950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4693 0x4104954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4694 0x4104958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4695 0x410495C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4696 0x4104960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4697 0x4104964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4698 0x4104968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4699 0x410496C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4700 0x4104970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4701 0x4104974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4702 0x4104978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4703 0x410497C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4704 0x4104980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4705 0x4104984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4706 0x4104988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4707 0x410498C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4708 0x4104990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4709 0x4104994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4710 0x4104998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4711 0x410499C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4712 0x41049A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4713 0x41049A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4714 0x41049A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4715 0x41049AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4716 0x41049B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4717 0x41049B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4718 0x41049B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4719 0x41049BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4720 0x41049C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4721 0x41049C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4722 0x41049C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4723 0x41049CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4724 0x41049D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4725 0x41049D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4726 0x41049D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4727 0x41049DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4728 0x41049E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4729 0x41049E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4730 0x41049E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4731 0x41049EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4732 0x41049F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4733 0x41049F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4734 0x41049F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4735 0x41049FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4736 0x4104A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4737 0x4104A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4738 0x4104A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4739 0x4104A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4740 0x4104A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4741 0x4104A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4742 0x4104A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4743 0x4104A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4744 0x4104A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4745 0x4104A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4746 0x4104A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4747 0x4104A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4748 0x4104A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4749 0x4104A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4750 0x4104A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4751 0x4104A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4752 0x4104A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4753 0x4104A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4754 0x4104A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4755 0x4104A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4756 0x4104A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4757 0x4104A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4758 0x4104A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4759 0x4104A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4760 0x4104A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4761 0x4104A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4762 0x4104A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4763 0x4104A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4764 0x4104A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4765 0x4104A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4766 0x4104A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4767 0x4104A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4768 0x4104A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4769 0x4104A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4770 0x4104A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4771 0x4104A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4772 0x4104A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4773 0x4104A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4774 0x4104A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4775 0x4104A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4776 0x4104AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4777 0x4104AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4778 0x4104AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4779 0x4104AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4780 0x4104AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4781 0x4104AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4782 0x4104AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4783 0x4104ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4784 0x4104AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4785 0x4104AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4786 0x4104AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4787 0x4104ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4788 0x4104AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4789 0x4104AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4790 0x4104AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4791 0x4104ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4792 0x4104AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4793 0x4104AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4794 0x4104AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4795 0x4104AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4796 0x4104AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4797 0x4104AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4798 0x4104AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4799 0x4104AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4800 0x4104B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4801 0x4104B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4802 0x4104B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4803 0x4104B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4804 0x4104B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4805 0x4104B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4806 0x4104B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4807 0x4104B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4808 0x4104B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4809 0x4104B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4810 0x4104B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4811 0x4104B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4812 0x4104B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4813 0x4104B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4814 0x4104B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4815 0x4104B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4816 0x4104B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4817 0x4104B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4818 0x4104B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4819 0x4104B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4820 0x4104B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4821 0x4104B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4822 0x4104B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4823 0x4104B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4824 0x4104B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4825 0x4104B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4826 0x4104B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4827 0x4104B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4828 0x4104B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4829 0x4104B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4830 0x4104B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4831 0x4104B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4832 0x4104B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4833 0x4104B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4834 0x4104B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4835 0x4104B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4836 0x4104B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4837 0x4104B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4838 0x4104B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4839 0x4104B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4840 0x4104BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4841 0x4104BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4842 0x4104BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4843 0x4104BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4844 0x4104BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4845 0x4104BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4846 0x4104BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4847 0x4104BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4848 0x4104BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4849 0x4104BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4850 0x4104BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4851 0x4104BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4852 0x4104BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4853 0x4104BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4854 0x4104BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4855 0x4104BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4856 0x4104BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4857 0x4104BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4858 0x4104BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4859 0x4104BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4860 0x4104BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4861 0x4104BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4862 0x4104BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4863 0x4104BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4864 0x4104C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4865 0x4104C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4866 0x4104C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4867 0x4104C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4868 0x4104C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4869 0x4104C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4870 0x4104C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4871 0x4104C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4872 0x4104C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4873 0x4104C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4874 0x4104C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4875 0x4104C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4876 0x4104C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4877 0x4104C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4878 0x4104C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4879 0x4104C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4880 0x4104C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4881 0x4104C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4882 0x4104C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4883 0x4104C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4884 0x4104C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4885 0x4104C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4886 0x4104C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4887 0x4104C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4888 0x4104C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4889 0x4104C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4890 0x4104C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4891 0x4104C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4892 0x4104C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4893 0x4104C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4894 0x4104C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4895 0x4104C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4896 0x4104C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4897 0x4104C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4898 0x4104C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4899 0x4104C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4900 0x4104C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4901 0x4104C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4902 0x4104C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4903 0x4104C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4904 0x4104CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4905 0x4104CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4906 0x4104CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4907 0x4104CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4908 0x4104CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4909 0x4104CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4910 0x4104CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4911 0x4104CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4912 0x4104CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4913 0x4104CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4914 0x4104CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4915 0x4104CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4916 0x4104CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4917 0x4104CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4918 0x4104CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4919 0x4104CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4920 0x4104CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4921 0x4104CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4922 0x4104CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4923 0x4104CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4924 0x4104CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4925 0x4104CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4926 0x4104CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4927 0x4104CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4928 0x4104D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4929 0x4104D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4930 0x4104D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4931 0x4104D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4932 0x4104D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4933 0x4104D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4934 0x4104D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4935 0x4104D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4936 0x4104D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4937 0x4104D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4938 0x4104D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4939 0x4104D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4940 0x4104D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4941 0x4104D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4942 0x4104D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4943 0x4104D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4944 0x4104D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4945 0x4104D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4946 0x4104D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4947 0x4104D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4948 0x4104D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4949 0x4104D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4950 0x4104D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4951 0x4104D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4952 0x4104D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4953 0x4104D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4954 0x4104D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4955 0x4104D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4956 0x4104D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4957 0x4104D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4958 0x4104D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4959 0x4104D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4960 0x4104D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4961 0x4104D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4962 0x4104D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4963 0x4104D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4964 0x4104D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4965 0x4104D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4966 0x4104D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4967 0x4104D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4968 0x4104DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4969 0x4104DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4970 0x4104DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4971 0x4104DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4972 0x4104DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4973 0x4104DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4974 0x4104DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4975 0x4104DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4976 0x4104DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4977 0x4104DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4978 0x4104DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4979 0x4104DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4980 0x4104DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4981 0x4104DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4982 0x4104DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4983 0x4104DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4984 0x4104DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4985 0x4104DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4986 0x4104DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4987 0x4104DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4988 0x4104DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4989 0x4104DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4990 0x4104DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4991 0x4104DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4992 0x4104E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4993 0x4104E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4994 0x4104E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4995 0x4104E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4996 0x4104E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4997 0x4104E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4998 0x4104E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4999 0x4104E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5000 0x4104E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5001 0x4104E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5002 0x4104E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5003 0x4104E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5004 0x4104E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5005 0x4104E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5006 0x4104E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5007 0x4104E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5008 0x4104E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5009 0x4104E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5010 0x4104E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5011 0x4104E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5012 0x4104E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5013 0x4104E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5014 0x4104E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5015 0x4104E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5016 0x4104E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5017 0x4104E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5018 0x4104E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5019 0x4104E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5020 0x4104E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5021 0x4104E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5022 0x4104E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5023 0x4104E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5024 0x4104E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5025 0x4104E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5026 0x4104E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5027 0x4104E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5028 0x4104E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5029 0x4104E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5030 0x4104E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5031 0x4104E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5032 0x4104EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5033 0x4104EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5034 0x4104EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5035 0x4104EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5036 0x4104EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5037 0x4104EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5038 0x4104EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5039 0x4104EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5040 0x4104EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5041 0x4104EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5042 0x4104EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5043 0x4104ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5044 0x4104ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5045 0x4104ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5046 0x4104ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5047 0x4104EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5048 0x4104EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5049 0x4104EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5050 0x4104EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5051 0x4104EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5052 0x4104EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5053 0x4104EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5054 0x4104EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5055 0x4104EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5056 0x4104F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5057 0x4104F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5058 0x4104F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5059 0x4104F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5060 0x4104F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5061 0x4104F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5062 0x4104F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5063 0x4104F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5064 0x4104F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5065 0x4104F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5066 0x4104F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5067 0x4104F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5068 0x4104F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5069 0x4104F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5070 0x4104F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5071 0x4104F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5072 0x4104F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5073 0x4104F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5074 0x4104F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5075 0x4104F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5076 0x4104F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5077 0x4104F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5078 0x4104F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5079 0x4104F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5080 0x4104F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5081 0x4104F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5082 0x4104F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5083 0x4104F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5084 0x4104F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5085 0x4104F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5086 0x4104F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5087 0x4104F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5088 0x4104F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5089 0x4104F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5090 0x4104F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5091 0x4104F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5092 0x4104F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5093 0x4104F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5094 0x4104F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5095 0x4104F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5096 0x4104FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5097 0x4104FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5098 0x4104FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5099 0x4104FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5100 0x4104FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5101 0x4104FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5102 0x4104FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5103 0x4104FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5104 0x4104FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5105 0x4104FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5106 0x4104FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5107 0x4104FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5108 0x4104FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5109 0x4104FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5110 0x4104FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5111 0x4104FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5112 0x4104FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5113 0x4104FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5114 0x4104FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5115 0x4104FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5116 0x4104FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5117 0x4104FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5118 0x4104FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5119 0x4104FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5120 0x4105000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5121 0x4105004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5122 0x4105008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5123 0x410500C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5124 0x4105010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5125 0x4105014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5126 0x4105018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5127 0x410501C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5128 0x4105020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5129 0x4105024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5130 0x4105028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5131 0x410502C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5132 0x4105030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5133 0x4105034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5134 0x4105038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5135 0x410503C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5136 0x4105040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5137 0x4105044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5138 0x4105048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5139 0x410504C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5140 0x4105050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5141 0x4105054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5142 0x4105058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5143 0x410505C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5144 0x4105060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5145 0x4105064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5146 0x4105068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5147 0x410506C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5148 0x4105070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5149 0x4105074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5150 0x4105078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5151 0x410507C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5152 0x4105080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5153 0x4105084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5154 0x4105088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5155 0x410508C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5156 0x4105090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5157 0x4105094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5158 0x4105098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5159 0x410509C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5160 0x41050A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5161 0x41050A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5162 0x41050A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5163 0x41050AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5164 0x41050B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5165 0x41050B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5166 0x41050B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5167 0x41050BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5168 0x41050C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5169 0x41050C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5170 0x41050C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5171 0x41050CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5172 0x41050D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5173 0x41050D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5174 0x41050D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5175 0x41050DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5176 0x41050E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5177 0x41050E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5178 0x41050E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5179 0x41050EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5180 0x41050F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5181 0x41050F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5182 0x41050F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5183 0x41050FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5184 0x4105100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5185 0x4105104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5186 0x4105108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5187 0x410510C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5188 0x4105110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5189 0x4105114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5190 0x4105118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5191 0x410511C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5192 0x4105120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5193 0x4105124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5194 0x4105128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5195 0x410512C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5196 0x4105130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5197 0x4105134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5198 0x4105138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5199 0x410513C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5200 0x4105140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5201 0x4105144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5202 0x4105148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5203 0x410514C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5204 0x4105150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5205 0x4105154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5206 0x4105158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5207 0x410515C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5208 0x4105160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5209 0x4105164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5210 0x4105168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5211 0x410516C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5212 0x4105170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5213 0x4105174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5214 0x4105178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5215 0x410517C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5216 0x4105180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5217 0x4105184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5218 0x4105188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5219 0x410518C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5220 0x4105190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5221 0x4105194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5222 0x4105198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5223 0x410519C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5224 0x41051A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5225 0x41051A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5226 0x41051A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5227 0x41051AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5228 0x41051B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5229 0x41051B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5230 0x41051B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5231 0x41051BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5232 0x41051C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5233 0x41051C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5234 0x41051C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5235 0x41051CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5236 0x41051D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5237 0x41051D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5238 0x41051D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5239 0x41051DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5240 0x41051E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5241 0x41051E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5242 0x41051E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5243 0x41051EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5244 0x41051F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5245 0x41051F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5246 0x41051F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5247 0x41051FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5248 0x4105200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5249 0x4105204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5250 0x4105208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5251 0x410520C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5252 0x4105210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5253 0x4105214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5254 0x4105218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5255 0x410521C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5256 0x4105220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5257 0x4105224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5258 0x4105228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5259 0x410522C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5260 0x4105230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5261 0x4105234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5262 0x4105238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5263 0x410523C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5264 0x4105240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5265 0x4105244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5266 0x4105248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5267 0x410524C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5268 0x4105250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5269 0x4105254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5270 0x4105258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5271 0x410525C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5272 0x4105260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5273 0x4105264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5274 0x4105268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5275 0x410526C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5276 0x4105270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5277 0x4105274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5278 0x4105278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5279 0x410527C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5280 0x4105280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5281 0x4105284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5282 0x4105288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5283 0x410528C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5284 0x4105290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5285 0x4105294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5286 0x4105298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5287 0x410529C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5288 0x41052A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5289 0x41052A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5290 0x41052A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5291 0x41052AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5292 0x41052B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5293 0x41052B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5294 0x41052B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5295 0x41052BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5296 0x41052C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5297 0x41052C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5298 0x41052C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5299 0x41052CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5300 0x41052D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5301 0x41052D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5302 0x41052D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5303 0x41052DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5304 0x41052E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5305 0x41052E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5306 0x41052E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5307 0x41052EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5308 0x41052F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5309 0x41052F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5310 0x41052F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5311 0x41052FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5312 0x4105300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5313 0x4105304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5314 0x4105308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5315 0x410530C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5316 0x4105310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5317 0x4105314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5318 0x4105318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5319 0x410531C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5320 0x4105320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5321 0x4105324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5322 0x4105328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5323 0x410532C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5324 0x4105330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5325 0x4105334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5326 0x4105338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5327 0x410533C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5328 0x4105340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5329 0x4105344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5330 0x4105348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5331 0x410534C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5332 0x4105350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5333 0x4105354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5334 0x4105358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5335 0x410535C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5336 0x4105360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5337 0x4105364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5338 0x4105368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5339 0x410536C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5340 0x4105370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5341 0x4105374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5342 0x4105378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5343 0x410537C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5344 0x4105380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5345 0x4105384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5346 0x4105388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5347 0x410538C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5348 0x4105390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5349 0x4105394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5350 0x4105398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5351 0x410539C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5352 0x41053A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5353 0x41053A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5354 0x41053A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5355 0x41053AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5356 0x41053B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5357 0x41053B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5358 0x41053B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5359 0x41053BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5360 0x41053C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5361 0x41053C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5362 0x41053C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5363 0x41053CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5364 0x41053D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5365 0x41053D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5366 0x41053D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5367 0x41053DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5368 0x41053E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5369 0x41053E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5370 0x41053E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5371 0x41053EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5372 0x41053F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5373 0x41053F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5374 0x41053F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5375 0x41053FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5376 0x4105400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5377 0x4105404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5378 0x4105408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5379 0x410540C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5380 0x4105410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5381 0x4105414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5382 0x4105418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5383 0x410541C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5384 0x4105420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5385 0x4105424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5386 0x4105428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5387 0x410542C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5388 0x4105430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5389 0x4105434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5390 0x4105438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5391 0x410543C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5392 0x4105440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5393 0x4105444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5394 0x4105448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5395 0x410544C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5396 0x4105450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5397 0x4105454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5398 0x4105458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5399 0x410545C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5400 0x4105460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5401 0x4105464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5402 0x4105468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5403 0x410546C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5404 0x4105470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5405 0x4105474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5406 0x4105478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5407 0x410547C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5408 0x4105480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5409 0x4105484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5410 0x4105488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5411 0x410548C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5412 0x4105490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5413 0x4105494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5414 0x4105498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5415 0x410549C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5416 0x41054A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5417 0x41054A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5418 0x41054A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5419 0x41054AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5420 0x41054B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5421 0x41054B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5422 0x41054B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5423 0x41054BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5424 0x41054C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5425 0x41054C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5426 0x41054C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5427 0x41054CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5428 0x41054D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5429 0x41054D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5430 0x41054D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5431 0x41054DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5432 0x41054E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5433 0x41054E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5434 0x41054E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5435 0x41054EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5436 0x41054F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5437 0x41054F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5438 0x41054F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5439 0x41054FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5440 0x4105500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5441 0x4105504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5442 0x4105508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5443 0x410550C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5444 0x4105510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5445 0x4105514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5446 0x4105518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5447 0x410551C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5448 0x4105520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5449 0x4105524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5450 0x4105528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5451 0x410552C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5452 0x4105530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5453 0x4105534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5454 0x4105538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5455 0x410553C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5456 0x4105540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5457 0x4105544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5458 0x4105548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5459 0x410554C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5460 0x4105550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5461 0x4105554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5462 0x4105558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5463 0x410555C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5464 0x4105560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5465 0x4105564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5466 0x4105568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5467 0x410556C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5468 0x4105570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5469 0x4105574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5470 0x4105578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5471 0x410557C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5472 0x4105580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5473 0x4105584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5474 0x4105588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5475 0x410558C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5476 0x4105590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5477 0x4105594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5478 0x4105598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5479 0x410559C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5480 0x41055A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5481 0x41055A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5482 0x41055A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5483 0x41055AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5484 0x41055B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5485 0x41055B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5486 0x41055B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5487 0x41055BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5488 0x41055C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5489 0x41055C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5490 0x41055C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5491 0x41055CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5492 0x41055D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5493 0x41055D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5494 0x41055D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5495 0x41055DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5496 0x41055E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5497 0x41055E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5498 0x41055E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5499 0x41055EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5500 0x41055F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5501 0x41055F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5502 0x41055F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5503 0x41055FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5504 0x4105600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5505 0x4105604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5506 0x4105608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5507 0x410560C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5508 0x4105610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5509 0x4105614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5510 0x4105618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5511 0x410561C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5512 0x4105620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5513 0x4105624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5514 0x4105628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5515 0x410562C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5516 0x4105630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5517 0x4105634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5518 0x4105638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5519 0x410563C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5520 0x4105640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5521 0x4105644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5522 0x4105648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5523 0x410564C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5524 0x4105650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5525 0x4105654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5526 0x4105658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5527 0x410565C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5528 0x4105660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5529 0x4105664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5530 0x4105668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5531 0x410566C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5532 0x4105670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5533 0x4105674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5534 0x4105678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5535 0x410567C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5536 0x4105680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5537 0x4105684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5538 0x4105688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5539 0x410568C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5540 0x4105690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5541 0x4105694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5542 0x4105698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5543 0x410569C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5544 0x41056A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5545 0x41056A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5546 0x41056A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5547 0x41056AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5548 0x41056B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5549 0x41056B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5550 0x41056B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5551 0x41056BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5552 0x41056C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5553 0x41056C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5554 0x41056C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5555 0x41056CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5556 0x41056D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5557 0x41056D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5558 0x41056D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5559 0x41056DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5560 0x41056E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5561 0x41056E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5562 0x41056E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5563 0x41056EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5564 0x41056F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5565 0x41056F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5566 0x41056F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5567 0x41056FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5568 0x4105700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5569 0x4105704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5570 0x4105708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5571 0x410570C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5572 0x4105710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5573 0x4105714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5574 0x4105718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5575 0x410571C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5576 0x4105720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5577 0x4105724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5578 0x4105728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5579 0x410572C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5580 0x4105730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5581 0x4105734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5582 0x4105738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5583 0x410573C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5584 0x4105740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5585 0x4105744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5586 0x4105748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5587 0x410574C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5588 0x4105750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5589 0x4105754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5590 0x4105758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5591 0x410575C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5592 0x4105760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5593 0x4105764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5594 0x4105768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5595 0x410576C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5596 0x4105770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5597 0x4105774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5598 0x4105778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5599 0x410577C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5600 0x4105780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5601 0x4105784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5602 0x4105788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5603 0x410578C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5604 0x4105790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5605 0x4105794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5606 0x4105798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5607 0x410579C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5608 0x41057A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5609 0x41057A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5610 0x41057A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5611 0x41057AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5612 0x41057B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5613 0x41057B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5614 0x41057B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5615 0x41057BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5616 0x41057C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5617 0x41057C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5618 0x41057C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5619 0x41057CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5620 0x41057D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5621 0x41057D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5622 0x41057D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5623 0x41057DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5624 0x41057E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5625 0x41057E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5626 0x41057E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5627 0x41057EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5628 0x41057F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5629 0x41057F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5630 0x41057F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5631 0x41057FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5632 0x4105800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5633 0x4105804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5634 0x4105808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5635 0x410580C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5636 0x4105810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5637 0x4105814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5638 0x4105818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5639 0x410581C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5640 0x4105820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5641 0x4105824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5642 0x4105828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5643 0x410582C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5644 0x4105830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5645 0x4105834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5646 0x4105838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5647 0x410583C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5648 0x4105840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5649 0x4105844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5650 0x4105848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5651 0x410584C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5652 0x4105850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5653 0x4105854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5654 0x4105858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5655 0x410585C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5656 0x4105860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5657 0x4105864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5658 0x4105868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5659 0x410586C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5660 0x4105870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5661 0x4105874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5662 0x4105878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5663 0x410587C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5664 0x4105880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5665 0x4105884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5666 0x4105888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5667 0x410588C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5668 0x4105890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5669 0x4105894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5670 0x4105898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5671 0x410589C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5672 0x41058A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5673 0x41058A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5674 0x41058A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5675 0x41058AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5676 0x41058B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5677 0x41058B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5678 0x41058B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5679 0x41058BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5680 0x41058C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5681 0x41058C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5682 0x41058C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5683 0x41058CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5684 0x41058D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5685 0x41058D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5686 0x41058D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5687 0x41058DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5688 0x41058E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5689 0x41058E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5690 0x41058E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5691 0x41058EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5692 0x41058F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5693 0x41058F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5694 0x41058F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5695 0x41058FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5696 0x4105900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5697 0x4105904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5698 0x4105908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5699 0x410590C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5700 0x4105910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5701 0x4105914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5702 0x4105918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5703 0x410591C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5704 0x4105920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5705 0x4105924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5706 0x4105928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5707 0x410592C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5708 0x4105930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5709 0x4105934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5710 0x4105938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5711 0x410593C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5712 0x4105940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5713 0x4105944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5714 0x4105948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5715 0x410594C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5716 0x4105950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5717 0x4105954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5718 0x4105958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5719 0x410595C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5720 0x4105960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5721 0x4105964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5722 0x4105968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5723 0x410596C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5724 0x4105970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5725 0x4105974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5726 0x4105978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5727 0x410597C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5728 0x4105980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5729 0x4105984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5730 0x4105988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5731 0x410598C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5732 0x4105990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5733 0x4105994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5734 0x4105998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5735 0x410599C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5736 0x41059A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5737 0x41059A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5738 0x41059A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5739 0x41059AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5740 0x41059B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5741 0x41059B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5742 0x41059B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5743 0x41059BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5744 0x41059C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5745 0x41059C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5746 0x41059C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5747 0x41059CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5748 0x41059D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5749 0x41059D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5750 0x41059D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5751 0x41059DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5752 0x41059E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5753 0x41059E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5754 0x41059E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5755 0x41059EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5756 0x41059F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5757 0x41059F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5758 0x41059F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5759 0x41059FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5760 0x4105A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5761 0x4105A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5762 0x4105A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5763 0x4105A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5764 0x4105A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5765 0x4105A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5766 0x4105A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5767 0x4105A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5768 0x4105A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5769 0x4105A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5770 0x4105A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5771 0x4105A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5772 0x4105A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5773 0x4105A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5774 0x4105A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5775 0x4105A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5776 0x4105A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5777 0x4105A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5778 0x4105A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5779 0x4105A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5780 0x4105A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5781 0x4105A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5782 0x4105A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5783 0x4105A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5784 0x4105A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5785 0x4105A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5786 0x4105A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5787 0x4105A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5788 0x4105A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5789 0x4105A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5790 0x4105A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5791 0x4105A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5792 0x4105A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5793 0x4105A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5794 0x4105A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5795 0x4105A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5796 0x4105A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5797 0x4105A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5798 0x4105A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5799 0x4105A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5800 0x4105AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5801 0x4105AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5802 0x4105AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5803 0x4105AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5804 0x4105AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5805 0x4105AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5806 0x4105AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5807 0x4105ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5808 0x4105AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5809 0x4105AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5810 0x4105AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5811 0x4105ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5812 0x4105AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5813 0x4105AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5814 0x4105AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5815 0x4105ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5816 0x4105AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5817 0x4105AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5818 0x4105AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5819 0x4105AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5820 0x4105AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5821 0x4105AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5822 0x4105AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5823 0x4105AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5824 0x4105B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5825 0x4105B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5826 0x4105B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5827 0x4105B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5828 0x4105B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5829 0x4105B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5830 0x4105B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5831 0x4105B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5832 0x4105B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5833 0x4105B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5834 0x4105B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5835 0x4105B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5836 0x4105B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5837 0x4105B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5838 0x4105B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5839 0x4105B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5840 0x4105B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5841 0x4105B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5842 0x4105B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5843 0x4105B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5844 0x4105B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5845 0x4105B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5846 0x4105B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5847 0x4105B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5848 0x4105B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5849 0x4105B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5850 0x4105B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5851 0x4105B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5852 0x4105B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5853 0x4105B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5854 0x4105B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5855 0x4105B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5856 0x4105B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5857 0x4105B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5858 0x4105B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5859 0x4105B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5860 0x4105B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5861 0x4105B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5862 0x4105B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5863 0x4105B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5864 0x4105BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5865 0x4105BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5866 0x4105BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5867 0x4105BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5868 0x4105BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5869 0x4105BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5870 0x4105BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5871 0x4105BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5872 0x4105BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5873 0x4105BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5874 0x4105BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5875 0x4105BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5876 0x4105BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5877 0x4105BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5878 0x4105BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5879 0x4105BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5880 0x4105BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5881 0x4105BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5882 0x4105BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5883 0x4105BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5884 0x4105BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5885 0x4105BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5886 0x4105BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5887 0x4105BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5888 0x4105C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5889 0x4105C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5890 0x4105C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5891 0x4105C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5892 0x4105C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5893 0x4105C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5894 0x4105C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5895 0x4105C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5896 0x4105C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5897 0x4105C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5898 0x4105C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5899 0x4105C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5900 0x4105C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5901 0x4105C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5902 0x4105C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5903 0x4105C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5904 0x4105C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5905 0x4105C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5906 0x4105C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5907 0x4105C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5908 0x4105C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5909 0x4105C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5910 0x4105C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5911 0x4105C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5912 0x4105C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5913 0x4105C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5914 0x4105C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5915 0x4105C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5916 0x4105C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5917 0x4105C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5918 0x4105C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5919 0x4105C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5920 0x4105C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5921 0x4105C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5922 0x4105C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5923 0x4105C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5924 0x4105C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5925 0x4105C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5926 0x4105C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5927 0x4105C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5928 0x4105CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5929 0x4105CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5930 0x4105CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5931 0x4105CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5932 0x4105CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5933 0x4105CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5934 0x4105CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5935 0x4105CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5936 0x4105CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5937 0x4105CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5938 0x4105CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5939 0x4105CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5940 0x4105CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5941 0x4105CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5942 0x4105CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5943 0x4105CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5944 0x4105CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5945 0x4105CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5946 0x4105CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5947 0x4105CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5948 0x4105CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5949 0x4105CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5950 0x4105CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5951 0x4105CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5952 0x4105D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5953 0x4105D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5954 0x4105D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5955 0x4105D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5956 0x4105D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5957 0x4105D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5958 0x4105D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5959 0x4105D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5960 0x4105D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5961 0x4105D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5962 0x4105D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5963 0x4105D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5964 0x4105D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5965 0x4105D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5966 0x4105D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5967 0x4105D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5968 0x4105D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5969 0x4105D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5970 0x4105D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5971 0x4105D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5972 0x4105D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5973 0x4105D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5974 0x4105D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5975 0x4105D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5976 0x4105D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5977 0x4105D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5978 0x4105D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5979 0x4105D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5980 0x4105D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5981 0x4105D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5982 0x4105D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5983 0x4105D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5984 0x4105D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5985 0x4105D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5986 0x4105D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5987 0x4105D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5988 0x4105D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5989 0x4105D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5990 0x4105D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5991 0x4105D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5992 0x4105DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5993 0x4105DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5994 0x4105DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5995 0x4105DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5996 0x4105DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5997 0x4105DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5998 0x4105DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5999 0x4105DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6000 0x4105DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6001 0x4105DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6002 0x4105DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6003 0x4105DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6004 0x4105DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6005 0x4105DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6006 0x4105DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6007 0x4105DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6008 0x4105DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6009 0x4105DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6010 0x4105DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6011 0x4105DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6012 0x4105DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6013 0x4105DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6014 0x4105DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6015 0x4105DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6016 0x4105E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6017 0x4105E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6018 0x4105E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6019 0x4105E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6020 0x4105E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6021 0x4105E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6022 0x4105E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6023 0x4105E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6024 0x4105E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6025 0x4105E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6026 0x4105E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6027 0x4105E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6028 0x4105E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6029 0x4105E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6030 0x4105E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6031 0x4105E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6032 0x4105E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6033 0x4105E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6034 0x4105E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6035 0x4105E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6036 0x4105E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6037 0x4105E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6038 0x4105E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6039 0x4105E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6040 0x4105E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6041 0x4105E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6042 0x4105E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6043 0x4105E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6044 0x4105E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6045 0x4105E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6046 0x4105E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6047 0x4105E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6048 0x4105E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6049 0x4105E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6050 0x4105E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6051 0x4105E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6052 0x4105E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6053 0x4105E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6054 0x4105E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6055 0x4105E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6056 0x4105EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6057 0x4105EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6058 0x4105EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6059 0x4105EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6060 0x4105EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6061 0x4105EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6062 0x4105EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6063 0x4105EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6064 0x4105EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6065 0x4105EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6066 0x4105EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6067 0x4105ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6068 0x4105ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6069 0x4105ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6070 0x4105ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6071 0x4105EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6072 0x4105EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6073 0x4105EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6074 0x4105EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6075 0x4105EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6076 0x4105EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6077 0x4105EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6078 0x4105EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6079 0x4105EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6080 0x4105F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6081 0x4105F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6082 0x4105F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6083 0x4105F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6084 0x4105F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6085 0x4105F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6086 0x4105F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6087 0x4105F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6088 0x4105F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6089 0x4105F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6090 0x4105F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6091 0x4105F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6092 0x4105F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6093 0x4105F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6094 0x4105F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6095 0x4105F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6096 0x4105F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6097 0x4105F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6098 0x4105F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6099 0x4105F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6100 0x4105F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6101 0x4105F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6102 0x4105F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6103 0x4105F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6104 0x4105F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6105 0x4105F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6106 0x4105F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6107 0x4105F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6108 0x4105F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6109 0x4105F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6110 0x4105F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6111 0x4105F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6112 0x4105F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6113 0x4105F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6114 0x4105F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6115 0x4105F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6116 0x4105F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6117 0x4105F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6118 0x4105F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6119 0x4105F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6120 0x4105FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6121 0x4105FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6122 0x4105FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6123 0x4105FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6124 0x4105FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6125 0x4105FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6126 0x4105FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6127 0x4105FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6128 0x4105FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6129 0x4105FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6130 0x4105FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6131 0x4105FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6132 0x4105FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6133 0x4105FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6134 0x4105FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6135 0x4105FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6136 0x4105FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6137 0x4105FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6138 0x4105FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6139 0x4105FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6140 0x4105FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6141 0x4105FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6142 0x4105FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6143 0x4105FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6144 0x4106000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6145 0x4106004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6146 0x4106008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6147 0x410600C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6148 0x4106010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6149 0x4106014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6150 0x4106018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6151 0x410601C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6152 0x4106020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6153 0x4106024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6154 0x4106028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6155 0x410602C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6156 0x4106030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6157 0x4106034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6158 0x4106038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6159 0x410603C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6160 0x4106040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6161 0x4106044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6162 0x4106048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6163 0x410604C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6164 0x4106050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6165 0x4106054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6166 0x4106058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6167 0x410605C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6168 0x4106060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6169 0x4106064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6170 0x4106068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6171 0x410606C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6172 0x4106070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6173 0x4106074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6174 0x4106078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6175 0x410607C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6176 0x4106080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6177 0x4106084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6178 0x4106088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6179 0x410608C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6180 0x4106090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6181 0x4106094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6182 0x4106098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6183 0x410609C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6184 0x41060A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6185 0x41060A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6186 0x41060A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6187 0x41060AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6188 0x41060B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6189 0x41060B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6190 0x41060B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6191 0x41060BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6192 0x41060C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6193 0x41060C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6194 0x41060C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6195 0x41060CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6196 0x41060D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6197 0x41060D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6198 0x41060D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6199 0x41060DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6200 0x41060E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6201 0x41060E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6202 0x41060E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6203 0x41060EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6204 0x41060F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6205 0x41060F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6206 0x41060F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6207 0x41060FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6208 0x4106100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6209 0x4106104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6210 0x4106108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6211 0x410610C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6212 0x4106110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6213 0x4106114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6214 0x4106118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6215 0x410611C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6216 0x4106120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6217 0x4106124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6218 0x4106128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6219 0x410612C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6220 0x4106130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6221 0x4106134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6222 0x4106138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6223 0x410613C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6224 0x4106140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6225 0x4106144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6226 0x4106148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6227 0x410614C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6228 0x4106150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6229 0x4106154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6230 0x4106158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6231 0x410615C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6232 0x4106160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6233 0x4106164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6234 0x4106168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6235 0x410616C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6236 0x4106170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6237 0x4106174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6238 0x4106178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6239 0x410617C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6240 0x4106180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6241 0x4106184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6242 0x4106188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6243 0x410618C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6244 0x4106190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6245 0x4106194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6246 0x4106198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6247 0x410619C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6248 0x41061A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6249 0x41061A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6250 0x41061A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6251 0x41061AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6252 0x41061B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6253 0x41061B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6254 0x41061B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6255 0x41061BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6256 0x41061C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6257 0x41061C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6258 0x41061C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6259 0x41061CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6260 0x41061D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6261 0x41061D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6262 0x41061D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6263 0x41061DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6264 0x41061E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6265 0x41061E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6266 0x41061E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6267 0x41061EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6268 0x41061F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6269 0x41061F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6270 0x41061F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6271 0x41061FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6272 0x4106200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6273 0x4106204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6274 0x4106208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6275 0x410620C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6276 0x4106210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6277 0x4106214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6278 0x4106218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6279 0x410621C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6280 0x4106220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6281 0x4106224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6282 0x4106228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6283 0x410622C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6284 0x4106230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6285 0x4106234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6286 0x4106238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6287 0x410623C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6288 0x4106240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6289 0x4106244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6290 0x4106248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6291 0x410624C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6292 0x4106250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6293 0x4106254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6294 0x4106258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6295 0x410625C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6296 0x4106260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6297 0x4106264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6298 0x4106268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6299 0x410626C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6300 0x4106270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6301 0x4106274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6302 0x4106278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6303 0x410627C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6304 0x4106280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6305 0x4106284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6306 0x4106288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6307 0x410628C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6308 0x4106290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6309 0x4106294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6310 0x4106298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6311 0x410629C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6312 0x41062A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6313 0x41062A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6314 0x41062A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6315 0x41062AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6316 0x41062B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6317 0x41062B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6318 0x41062B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6319 0x41062BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6320 0x41062C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6321 0x41062C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6322 0x41062C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6323 0x41062CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6324 0x41062D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6325 0x41062D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6326 0x41062D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6327 0x41062DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6328 0x41062E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6329 0x41062E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6330 0x41062E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6331 0x41062EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6332 0x41062F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6333 0x41062F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6334 0x41062F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6335 0x41062FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6336 0x4106300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6337 0x4106304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6338 0x4106308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6339 0x410630C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6340 0x4106310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6341 0x4106314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6342 0x4106318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6343 0x410631C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6344 0x4106320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6345 0x4106324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6346 0x4106328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6347 0x410632C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6348 0x4106330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6349 0x4106334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6350 0x4106338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6351 0x410633C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6352 0x4106340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6353 0x4106344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6354 0x4106348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6355 0x410634C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6356 0x4106350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6357 0x4106354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6358 0x4106358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6359 0x410635C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6360 0x4106360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6361 0x4106364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6362 0x4106368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6363 0x410636C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6364 0x4106370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6365 0x4106374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6366 0x4106378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6367 0x410637C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6368 0x4106380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6369 0x4106384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6370 0x4106388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6371 0x410638C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6372 0x4106390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6373 0x4106394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6374 0x4106398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6375 0x410639C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6376 0x41063A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6377 0x41063A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6378 0x41063A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6379 0x41063AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6380 0x41063B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6381 0x41063B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6382 0x41063B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6383 0x41063BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6384 0x41063C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6385 0x41063C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6386 0x41063C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6387 0x41063CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6388 0x41063D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6389 0x41063D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6390 0x41063D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6391 0x41063DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6392 0x41063E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6393 0x41063E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6394 0x41063E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6395 0x41063EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6396 0x41063F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6397 0x41063F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6398 0x41063F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6399 0x41063FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6400 0x4106400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6401 0x4106404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6402 0x4106408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6403 0x410640C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6404 0x4106410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6405 0x4106414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6406 0x4106418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6407 0x410641C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6408 0x4106420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6409 0x4106424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6410 0x4106428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6411 0x410642C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6412 0x4106430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6413 0x4106434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6414 0x4106438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6415 0x410643C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6416 0x4106440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6417 0x4106444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6418 0x4106448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6419 0x410644C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6420 0x4106450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6421 0x4106454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6422 0x4106458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6423 0x410645C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6424 0x4106460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6425 0x4106464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6426 0x4106468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6427 0x410646C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6428 0x4106470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6429 0x4106474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6430 0x4106478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6431 0x410647C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6432 0x4106480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6433 0x4106484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6434 0x4106488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6435 0x410648C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6436 0x4106490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6437 0x4106494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6438 0x4106498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6439 0x410649C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6440 0x41064A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6441 0x41064A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6442 0x41064A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6443 0x41064AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6444 0x41064B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6445 0x41064B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6446 0x41064B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6447 0x41064BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6448 0x41064C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6449 0x41064C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6450 0x41064C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6451 0x41064CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6452 0x41064D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6453 0x41064D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6454 0x41064D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6455 0x41064DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6456 0x41064E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6457 0x41064E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6458 0x41064E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6459 0x41064EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6460 0x41064F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6461 0x41064F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6462 0x41064F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6463 0x41064FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6464 0x4106500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6465 0x4106504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6466 0x4106508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6467 0x410650C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6468 0x4106510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6469 0x4106514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6470 0x4106518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6471 0x410651C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6472 0x4106520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6473 0x4106524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6474 0x4106528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6475 0x410652C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6476 0x4106530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6477 0x4106534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6478 0x4106538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6479 0x410653C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6480 0x4106540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6481 0x4106544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6482 0x4106548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6483 0x410654C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6484 0x4106550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6485 0x4106554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6486 0x4106558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6487 0x410655C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6488 0x4106560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6489 0x4106564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6490 0x4106568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6491 0x410656C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6492 0x4106570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6493 0x4106574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6494 0x4106578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6495 0x410657C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6496 0x4106580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6497 0x4106584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6498 0x4106588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6499 0x410658C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6500 0x4106590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6501 0x4106594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6502 0x4106598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6503 0x410659C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6504 0x41065A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6505 0x41065A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6506 0x41065A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6507 0x41065AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6508 0x41065B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6509 0x41065B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6510 0x41065B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6511 0x41065BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6512 0x41065C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6513 0x41065C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6514 0x41065C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6515 0x41065CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6516 0x41065D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6517 0x41065D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6518 0x41065D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6519 0x41065DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6520 0x41065E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6521 0x41065E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6522 0x41065E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6523 0x41065EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6524 0x41065F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6525 0x41065F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6526 0x41065F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6527 0x41065FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6528 0x4106600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6529 0x4106604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6530 0x4106608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6531 0x410660C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6532 0x4106610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6533 0x4106614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6534 0x4106618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6535 0x410661C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6536 0x4106620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6537 0x4106624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6538 0x4106628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6539 0x410662C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6540 0x4106630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6541 0x4106634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6542 0x4106638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6543 0x410663C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6544 0x4106640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6545 0x4106644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6546 0x4106648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6547 0x410664C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6548 0x4106650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6549 0x4106654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6550 0x4106658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6551 0x410665C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6552 0x4106660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6553 0x4106664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6554 0x4106668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6555 0x410666C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6556 0x4106670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6557 0x4106674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6558 0x4106678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6559 0x410667C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6560 0x4106680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6561 0x4106684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6562 0x4106688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6563 0x410668C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6564 0x4106690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6565 0x4106694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6566 0x4106698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6567 0x410669C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6568 0x41066A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6569 0x41066A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6570 0x41066A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6571 0x41066AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6572 0x41066B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6573 0x41066B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6574 0x41066B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6575 0x41066BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6576 0x41066C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6577 0x41066C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6578 0x41066C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6579 0x41066CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6580 0x41066D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6581 0x41066D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6582 0x41066D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6583 0x41066DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6584 0x41066E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6585 0x41066E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6586 0x41066E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6587 0x41066EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6588 0x41066F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6589 0x41066F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6590 0x41066F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6591 0x41066FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6592 0x4106700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6593 0x4106704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6594 0x4106708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6595 0x410670C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6596 0x4106710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6597 0x4106714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6598 0x4106718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6599 0x410671C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6600 0x4106720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6601 0x4106724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6602 0x4106728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6603 0x410672C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6604 0x4106730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6605 0x4106734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6606 0x4106738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6607 0x410673C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6608 0x4106740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6609 0x4106744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6610 0x4106748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6611 0x410674C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6612 0x4106750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6613 0x4106754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6614 0x4106758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6615 0x410675C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6616 0x4106760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6617 0x4106764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6618 0x4106768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6619 0x410676C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6620 0x4106770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6621 0x4106774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6622 0x4106778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6623 0x410677C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6624 0x4106780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6625 0x4106784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6626 0x4106788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6627 0x410678C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6628 0x4106790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6629 0x4106794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6630 0x4106798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6631 0x410679C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6632 0x41067A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6633 0x41067A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6634 0x41067A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6635 0x41067AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6636 0x41067B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6637 0x41067B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6638 0x41067B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6639 0x41067BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6640 0x41067C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6641 0x41067C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6642 0x41067C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6643 0x41067CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6644 0x41067D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6645 0x41067D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6646 0x41067D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6647 0x41067DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6648 0x41067E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6649 0x41067E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6650 0x41067E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6651 0x41067EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6652 0x41067F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6653 0x41067F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6654 0x41067F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6655 0x41067FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6656 0x4106800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6657 0x4106804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6658 0x4106808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6659 0x410680C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6660 0x4106810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6661 0x4106814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6662 0x4106818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6663 0x410681C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6664 0x4106820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6665 0x4106824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6666 0x4106828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6667 0x410682C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6668 0x4106830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6669 0x4106834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6670 0x4106838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6671 0x410683C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6672 0x4106840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6673 0x4106844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6674 0x4106848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6675 0x410684C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6676 0x4106850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6677 0x4106854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6678 0x4106858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6679 0x410685C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6680 0x4106860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6681 0x4106864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6682 0x4106868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6683 0x410686C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6684 0x4106870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6685 0x4106874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6686 0x4106878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6687 0x410687C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6688 0x4106880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6689 0x4106884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6690 0x4106888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6691 0x410688C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6692 0x4106890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6693 0x4106894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6694 0x4106898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6695 0x410689C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6696 0x41068A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6697 0x41068A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6698 0x41068A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6699 0x41068AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6700 0x41068B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6701 0x41068B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6702 0x41068B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6703 0x41068BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6704 0x41068C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6705 0x41068C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6706 0x41068C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6707 0x41068CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6708 0x41068D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6709 0x41068D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6710 0x41068D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6711 0x41068DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6712 0x41068E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6713 0x41068E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6714 0x41068E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6715 0x41068EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6716 0x41068F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6717 0x41068F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6718 0x41068F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6719 0x41068FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6720 0x4106900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6721 0x4106904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6722 0x4106908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6723 0x410690C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6724 0x4106910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6725 0x4106914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6726 0x4106918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6727 0x410691C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6728 0x4106920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6729 0x4106924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6730 0x4106928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6731 0x410692C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6732 0x4106930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6733 0x4106934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6734 0x4106938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6735 0x410693C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6736 0x4106940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6737 0x4106944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6738 0x4106948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6739 0x410694C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6740 0x4106950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6741 0x4106954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6742 0x4106958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6743 0x410695C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6744 0x4106960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6745 0x4106964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6746 0x4106968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6747 0x410696C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6748 0x4106970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6749 0x4106974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6750 0x4106978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6751 0x410697C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6752 0x4106980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6753 0x4106984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6754 0x4106988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6755 0x410698C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6756 0x4106990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6757 0x4106994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6758 0x4106998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6759 0x410699C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6760 0x41069A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6761 0x41069A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6762 0x41069A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6763 0x41069AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6764 0x41069B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6765 0x41069B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6766 0x41069B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6767 0x41069BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6768 0x41069C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6769 0x41069C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6770 0x41069C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6771 0x41069CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6772 0x41069D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6773 0x41069D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6774 0x41069D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6775 0x41069DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6776 0x41069E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6777 0x41069E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6778 0x41069E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6779 0x41069EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6780 0x41069F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6781 0x41069F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6782 0x41069F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6783 0x41069FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6784 0x4106A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6785 0x4106A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6786 0x4106A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6787 0x4106A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6788 0x4106A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6789 0x4106A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6790 0x4106A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6791 0x4106A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6792 0x4106A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6793 0x4106A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6794 0x4106A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6795 0x4106A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6796 0x4106A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6797 0x4106A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6798 0x4106A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6799 0x4106A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6800 0x4106A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6801 0x4106A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6802 0x4106A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6803 0x4106A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6804 0x4106A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6805 0x4106A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6806 0x4106A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6807 0x4106A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6808 0x4106A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6809 0x4106A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6810 0x4106A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6811 0x4106A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6812 0x4106A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6813 0x4106A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6814 0x4106A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6815 0x4106A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6816 0x4106A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6817 0x4106A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6818 0x4106A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6819 0x4106A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6820 0x4106A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6821 0x4106A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6822 0x4106A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6823 0x4106A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6824 0x4106AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6825 0x4106AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6826 0x4106AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6827 0x4106AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6828 0x4106AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6829 0x4106AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6830 0x4106AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6831 0x4106ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6832 0x4106AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6833 0x4106AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6834 0x4106AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6835 0x4106ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6836 0x4106AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6837 0x4106AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6838 0x4106AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6839 0x4106ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6840 0x4106AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6841 0x4106AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6842 0x4106AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6843 0x4106AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6844 0x4106AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6845 0x4106AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6846 0x4106AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6847 0x4106AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6848 0x4106B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6849 0x4106B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6850 0x4106B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6851 0x4106B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6852 0x4106B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6853 0x4106B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6854 0x4106B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6855 0x4106B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6856 0x4106B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6857 0x4106B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6858 0x4106B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6859 0x4106B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6860 0x4106B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6861 0x4106B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6862 0x4106B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6863 0x4106B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6864 0x4106B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6865 0x4106B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6866 0x4106B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6867 0x4106B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6868 0x4106B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6869 0x4106B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6870 0x4106B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6871 0x4106B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6872 0x4106B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6873 0x4106B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6874 0x4106B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6875 0x4106B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6876 0x4106B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6877 0x4106B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6878 0x4106B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6879 0x4106B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6880 0x4106B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6881 0x4106B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6882 0x4106B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6883 0x4106B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6884 0x4106B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6885 0x4106B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6886 0x4106B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6887 0x4106B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6888 0x4106BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6889 0x4106BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6890 0x4106BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6891 0x4106BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6892 0x4106BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6893 0x4106BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6894 0x4106BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6895 0x4106BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6896 0x4106BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6897 0x4106BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6898 0x4106BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6899 0x4106BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6900 0x4106BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6901 0x4106BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6902 0x4106BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6903 0x4106BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6904 0x4106BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6905 0x4106BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6906 0x4106BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6907 0x4106BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6908 0x4106BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6909 0x4106BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6910 0x4106BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6911 0x4106BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6912 0x4106C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6913 0x4106C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6914 0x4106C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6915 0x4106C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6916 0x4106C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6917 0x4106C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6918 0x4106C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6919 0x4106C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6920 0x4106C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6921 0x4106C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6922 0x4106C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6923 0x4106C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6924 0x4106C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6925 0x4106C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6926 0x4106C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6927 0x4106C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6928 0x4106C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6929 0x4106C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6930 0x4106C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6931 0x4106C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6932 0x4106C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6933 0x4106C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6934 0x4106C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6935 0x4106C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6936 0x4106C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6937 0x4106C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6938 0x4106C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6939 0x4106C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6940 0x4106C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6941 0x4106C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6942 0x4106C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6943 0x4106C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6944 0x4106C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6945 0x4106C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6946 0x4106C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6947 0x4106C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6948 0x4106C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6949 0x4106C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6950 0x4106C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6951 0x4106C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6952 0x4106CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6953 0x4106CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6954 0x4106CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6955 0x4106CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6956 0x4106CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6957 0x4106CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6958 0x4106CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6959 0x4106CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6960 0x4106CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6961 0x4106CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6962 0x4106CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6963 0x4106CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6964 0x4106CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6965 0x4106CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6966 0x4106CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6967 0x4106CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6968 0x4106CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6969 0x4106CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6970 0x4106CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6971 0x4106CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6972 0x4106CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6973 0x4106CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6974 0x4106CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6975 0x4106CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6976 0x4106D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6977 0x4106D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6978 0x4106D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6979 0x4106D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6980 0x4106D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6981 0x4106D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6982 0x4106D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6983 0x4106D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6984 0x4106D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6985 0x4106D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6986 0x4106D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6987 0x4106D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6988 0x4106D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6989 0x4106D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6990 0x4106D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6991 0x4106D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6992 0x4106D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6993 0x4106D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6994 0x4106D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6995 0x4106D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6996 0x4106D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6997 0x4106D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6998 0x4106D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6999 0x4106D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7000 0x4106D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7001 0x4106D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7002 0x4106D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7003 0x4106D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7004 0x4106D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7005 0x4106D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7006 0x4106D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7007 0x4106D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7008 0x4106D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7009 0x4106D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7010 0x4106D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7011 0x4106D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7012 0x4106D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7013 0x4106D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7014 0x4106D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7015 0x4106D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7016 0x4106DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7017 0x4106DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7018 0x4106DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7019 0x4106DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7020 0x4106DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7021 0x4106DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7022 0x4106DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7023 0x4106DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7024 0x4106DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7025 0x4106DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7026 0x4106DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7027 0x4106DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7028 0x4106DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7029 0x4106DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7030 0x4106DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7031 0x4106DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7032 0x4106DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7033 0x4106DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7034 0x4106DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7035 0x4106DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7036 0x4106DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7037 0x4106DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7038 0x4106DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7039 0x4106DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7040 0x4106E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7041 0x4106E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7042 0x4106E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7043 0x4106E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7044 0x4106E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7045 0x4106E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7046 0x4106E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7047 0x4106E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7048 0x4106E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7049 0x4106E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7050 0x4106E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7051 0x4106E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7052 0x4106E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7053 0x4106E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7054 0x4106E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7055 0x4106E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7056 0x4106E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7057 0x4106E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7058 0x4106E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7059 0x4106E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7060 0x4106E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7061 0x4106E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7062 0x4106E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7063 0x4106E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7064 0x4106E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7065 0x4106E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7066 0x4106E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7067 0x4106E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7068 0x4106E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7069 0x4106E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7070 0x4106E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7071 0x4106E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7072 0x4106E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7073 0x4106E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7074 0x4106E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7075 0x4106E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7076 0x4106E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7077 0x4106E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7078 0x4106E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7079 0x4106E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7080 0x4106EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7081 0x4106EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7082 0x4106EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7083 0x4106EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7084 0x4106EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7085 0x4106EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7086 0x4106EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7087 0x4106EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7088 0x4106EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7089 0x4106EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7090 0x4106EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7091 0x4106ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7092 0x4106ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7093 0x4106ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7094 0x4106ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7095 0x4106EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7096 0x4106EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7097 0x4106EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7098 0x4106EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7099 0x4106EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7100 0x4106EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7101 0x4106EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7102 0x4106EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7103 0x4106EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7104 0x4106F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7105 0x4106F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7106 0x4106F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7107 0x4106F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7108 0x4106F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7109 0x4106F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7110 0x4106F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7111 0x4106F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7112 0x4106F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7113 0x4106F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7114 0x4106F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7115 0x4106F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7116 0x4106F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7117 0x4106F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7118 0x4106F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7119 0x4106F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7120 0x4106F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7121 0x4106F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7122 0x4106F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7123 0x4106F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7124 0x4106F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7125 0x4106F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7126 0x4106F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7127 0x4106F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7128 0x4106F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7129 0x4106F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7130 0x4106F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7131 0x4106F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7132 0x4106F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7133 0x4106F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7134 0x4106F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7135 0x4106F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7136 0x4106F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7137 0x4106F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7138 0x4106F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7139 0x4106F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7140 0x4106F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7141 0x4106F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7142 0x4106F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7143 0x4106F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7144 0x4106FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7145 0x4106FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7146 0x4106FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7147 0x4106FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7148 0x4106FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7149 0x4106FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7150 0x4106FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7151 0x4106FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7152 0x4106FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7153 0x4106FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7154 0x4106FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7155 0x4106FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7156 0x4106FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7157 0x4106FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7158 0x4106FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7159 0x4106FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7160 0x4106FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7161 0x4106FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7162 0x4106FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7163 0x4106FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7164 0x4106FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7165 0x4106FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7166 0x4106FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7167 0x4106FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7168 0x4107000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7169 0x4107004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7170 0x4107008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7171 0x410700C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7172 0x4107010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7173 0x4107014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7174 0x4107018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7175 0x410701C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7176 0x4107020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7177 0x4107024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7178 0x4107028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7179 0x410702C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7180 0x4107030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7181 0x4107034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7182 0x4107038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7183 0x410703C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7184 0x4107040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7185 0x4107044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7186 0x4107048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7187 0x410704C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7188 0x4107050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7189 0x4107054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7190 0x4107058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7191 0x410705C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7192 0x4107060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7193 0x4107064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7194 0x4107068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7195 0x410706C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7196 0x4107070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7197 0x4107074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7198 0x4107078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7199 0x410707C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7200 0x4107080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7201 0x4107084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7202 0x4107088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7203 0x410708C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7204 0x4107090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7205 0x4107094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7206 0x4107098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7207 0x410709C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7208 0x41070A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7209 0x41070A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7210 0x41070A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7211 0x41070AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7212 0x41070B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7213 0x41070B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7214 0x41070B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7215 0x41070BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7216 0x41070C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7217 0x41070C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7218 0x41070C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7219 0x41070CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7220 0x41070D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7221 0x41070D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7222 0x41070D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7223 0x41070DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7224 0x41070E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7225 0x41070E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7226 0x41070E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7227 0x41070EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7228 0x41070F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7229 0x41070F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7230 0x41070F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7231 0x41070FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7232 0x4107100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7233 0x4107104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7234 0x4107108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7235 0x410710C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7236 0x4107110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7237 0x4107114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7238 0x4107118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7239 0x410711C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7240 0x4107120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7241 0x4107124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7242 0x4107128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7243 0x410712C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7244 0x4107130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7245 0x4107134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7246 0x4107138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7247 0x410713C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7248 0x4107140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7249 0x4107144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7250 0x4107148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7251 0x410714C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7252 0x4107150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7253 0x4107154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7254 0x4107158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7255 0x410715C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7256 0x4107160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7257 0x4107164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7258 0x4107168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7259 0x410716C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7260 0x4107170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7261 0x4107174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7262 0x4107178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7263 0x410717C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7264 0x4107180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7265 0x4107184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7266 0x4107188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7267 0x410718C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7268 0x4107190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7269 0x4107194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7270 0x4107198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7271 0x410719C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7272 0x41071A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7273 0x41071A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7274 0x41071A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7275 0x41071AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7276 0x41071B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7277 0x41071B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7278 0x41071B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7279 0x41071BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7280 0x41071C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7281 0x41071C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7282 0x41071C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7283 0x41071CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7284 0x41071D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7285 0x41071D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7286 0x41071D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7287 0x41071DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7288 0x41071E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7289 0x41071E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7290 0x41071E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7291 0x41071EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7292 0x41071F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7293 0x41071F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7294 0x41071F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7295 0x41071FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7296 0x4107200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7297 0x4107204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7298 0x4107208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7299 0x410720C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7300 0x4107210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7301 0x4107214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7302 0x4107218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7303 0x410721C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7304 0x4107220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7305 0x4107224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7306 0x4107228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7307 0x410722C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7308 0x4107230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7309 0x4107234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7310 0x4107238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7311 0x410723C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7312 0x4107240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7313 0x4107244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7314 0x4107248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7315 0x410724C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7316 0x4107250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7317 0x4107254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7318 0x4107258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7319 0x410725C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7320 0x4107260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7321 0x4107264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7322 0x4107268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7323 0x410726C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7324 0x4107270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7325 0x4107274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7326 0x4107278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7327 0x410727C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7328 0x4107280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7329 0x4107284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7330 0x4107288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7331 0x410728C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7332 0x4107290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7333 0x4107294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7334 0x4107298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7335 0x410729C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7336 0x41072A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7337 0x41072A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7338 0x41072A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7339 0x41072AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7340 0x41072B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7341 0x41072B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7342 0x41072B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7343 0x41072BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7344 0x41072C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7345 0x41072C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7346 0x41072C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7347 0x41072CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7348 0x41072D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7349 0x41072D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7350 0x41072D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7351 0x41072DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7352 0x41072E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7353 0x41072E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7354 0x41072E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7355 0x41072EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7356 0x41072F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7357 0x41072F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7358 0x41072F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7359 0x41072FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7360 0x4107300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7361 0x4107304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7362 0x4107308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7363 0x410730C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7364 0x4107310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7365 0x4107314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7366 0x4107318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7367 0x410731C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7368 0x4107320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7369 0x4107324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7370 0x4107328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7371 0x410732C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7372 0x4107330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7373 0x4107334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7374 0x4107338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7375 0x410733C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7376 0x4107340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7377 0x4107344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7378 0x4107348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7379 0x410734C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7380 0x4107350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7381 0x4107354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7382 0x4107358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7383 0x410735C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7384 0x4107360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7385 0x4107364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7386 0x4107368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7387 0x410736C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7388 0x4107370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7389 0x4107374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7390 0x4107378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7391 0x410737C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7392 0x4107380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7393 0x4107384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7394 0x4107388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7395 0x410738C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7396 0x4107390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7397 0x4107394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7398 0x4107398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7399 0x410739C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7400 0x41073A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7401 0x41073A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7402 0x41073A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7403 0x41073AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7404 0x41073B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7405 0x41073B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7406 0x41073B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7407 0x41073BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7408 0x41073C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7409 0x41073C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7410 0x41073C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7411 0x41073CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7412 0x41073D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7413 0x41073D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7414 0x41073D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7415 0x41073DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7416 0x41073E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7417 0x41073E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7418 0x41073E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7419 0x41073EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7420 0x41073F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7421 0x41073F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7422 0x41073F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7423 0x41073FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7424 0x4107400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7425 0x4107404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7426 0x4107408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7427 0x410740C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7428 0x4107410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7429 0x4107414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7430 0x4107418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7431 0x410741C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7432 0x4107420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7433 0x4107424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7434 0x4107428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7435 0x410742C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7436 0x4107430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7437 0x4107434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7438 0x4107438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7439 0x410743C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7440 0x4107440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7441 0x4107444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7442 0x4107448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7443 0x410744C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7444 0x4107450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7445 0x4107454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7446 0x4107458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7447 0x410745C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7448 0x4107460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7449 0x4107464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7450 0x4107468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7451 0x410746C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7452 0x4107470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7453 0x4107474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7454 0x4107478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7455 0x410747C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7456 0x4107480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7457 0x4107484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7458 0x4107488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7459 0x410748C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7460 0x4107490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7461 0x4107494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7462 0x4107498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7463 0x410749C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7464 0x41074A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7465 0x41074A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7466 0x41074A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7467 0x41074AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7468 0x41074B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7469 0x41074B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7470 0x41074B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7471 0x41074BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7472 0x41074C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7473 0x41074C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7474 0x41074C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7475 0x41074CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7476 0x41074D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7477 0x41074D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7478 0x41074D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7479 0x41074DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7480 0x41074E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7481 0x41074E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7482 0x41074E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7483 0x41074EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7484 0x41074F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7485 0x41074F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7486 0x41074F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7487 0x41074FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7488 0x4107500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7489 0x4107504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7490 0x4107508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7491 0x410750C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7492 0x4107510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7493 0x4107514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7494 0x4107518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7495 0x410751C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7496 0x4107520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7497 0x4107524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7498 0x4107528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7499 0x410752C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7500 0x4107530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7501 0x4107534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7502 0x4107538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7503 0x410753C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7504 0x4107540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7505 0x4107544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7506 0x4107548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7507 0x410754C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7508 0x4107550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7509 0x4107554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7510 0x4107558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7511 0x410755C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7512 0x4107560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7513 0x4107564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7514 0x4107568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7515 0x410756C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7516 0x4107570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7517 0x4107574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7518 0x4107578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7519 0x410757C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7520 0x4107580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7521 0x4107584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7522 0x4107588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7523 0x410758C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7524 0x4107590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7525 0x4107594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7526 0x4107598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7527 0x410759C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7528 0x41075A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7529 0x41075A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7530 0x41075A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7531 0x41075AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7532 0x41075B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7533 0x41075B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7534 0x41075B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7535 0x41075BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7536 0x41075C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7537 0x41075C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7538 0x41075C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7539 0x41075CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7540 0x41075D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7541 0x41075D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7542 0x41075D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7543 0x41075DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7544 0x41075E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7545 0x41075E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7546 0x41075E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7547 0x41075EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7548 0x41075F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7549 0x41075F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7550 0x41075F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7551 0x41075FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7552 0x4107600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7553 0x4107604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7554 0x4107608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7555 0x410760C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7556 0x4107610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7557 0x4107614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7558 0x4107618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7559 0x410761C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7560 0x4107620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7561 0x4107624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7562 0x4107628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7563 0x410762C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7564 0x4107630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7565 0x4107634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7566 0x4107638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7567 0x410763C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7568 0x4107640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7569 0x4107644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7570 0x4107648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7571 0x410764C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7572 0x4107650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7573 0x4107654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7574 0x4107658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7575 0x410765C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7576 0x4107660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7577 0x4107664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7578 0x4107668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7579 0x410766C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7580 0x4107670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7581 0x4107674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7582 0x4107678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7583 0x410767C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7584 0x4107680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7585 0x4107684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7586 0x4107688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7587 0x410768C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7588 0x4107690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7589 0x4107694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7590 0x4107698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7591 0x410769C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7592 0x41076A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7593 0x41076A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7594 0x41076A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7595 0x41076AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7596 0x41076B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7597 0x41076B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7598 0x41076B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7599 0x41076BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7600 0x41076C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7601 0x41076C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7602 0x41076C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7603 0x41076CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7604 0x41076D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7605 0x41076D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7606 0x41076D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7607 0x41076DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7608 0x41076E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7609 0x41076E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7610 0x41076E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7611 0x41076EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7612 0x41076F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7613 0x41076F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7614 0x41076F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7615 0x41076FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7616 0x4107700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7617 0x4107704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7618 0x4107708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7619 0x410770C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7620 0x4107710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7621 0x4107714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7622 0x4107718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7623 0x410771C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7624 0x4107720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7625 0x4107724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7626 0x4107728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7627 0x410772C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7628 0x4107730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7629 0x4107734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7630 0x4107738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7631 0x410773C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7632 0x4107740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7633 0x4107744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7634 0x4107748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7635 0x410774C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7636 0x4107750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7637 0x4107754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7638 0x4107758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7639 0x410775C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7640 0x4107760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7641 0x4107764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7642 0x4107768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7643 0x410776C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7644 0x4107770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7645 0x4107774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7646 0x4107778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7647 0x410777C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7648 0x4107780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7649 0x4107784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7650 0x4107788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7651 0x410778C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7652 0x4107790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7653 0x4107794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7654 0x4107798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7655 0x410779C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7656 0x41077A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7657 0x41077A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7658 0x41077A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7659 0x41077AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7660 0x41077B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7661 0x41077B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7662 0x41077B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7663 0x41077BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7664 0x41077C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7665 0x41077C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7666 0x41077C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7667 0x41077CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7668 0x41077D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7669 0x41077D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7670 0x41077D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7671 0x41077DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7672 0x41077E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7673 0x41077E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7674 0x41077E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7675 0x41077EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7676 0x41077F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7677 0x41077F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7678 0x41077F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7679 0x41077FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7680 0x4107800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7681 0x4107804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7682 0x4107808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7683 0x410780C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7684 0x4107810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7685 0x4107814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7686 0x4107818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7687 0x410781C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7688 0x4107820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7689 0x4107824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7690 0x4107828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7691 0x410782C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7692 0x4107830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7693 0x4107834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7694 0x4107838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7695 0x410783C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7696 0x4107840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7697 0x4107844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7698 0x4107848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7699 0x410784C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7700 0x4107850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7701 0x4107854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7702 0x4107858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7703 0x410785C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7704 0x4107860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7705 0x4107864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7706 0x4107868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7707 0x410786C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7708 0x4107870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7709 0x4107874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7710 0x4107878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7711 0x410787C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7712 0x4107880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7713 0x4107884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7714 0x4107888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7715 0x410788C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7716 0x4107890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7717 0x4107894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7718 0x4107898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7719 0x410789C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7720 0x41078A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7721 0x41078A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7722 0x41078A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7723 0x41078AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7724 0x41078B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7725 0x41078B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7726 0x41078B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7727 0x41078BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7728 0x41078C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7729 0x41078C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7730 0x41078C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7731 0x41078CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7732 0x41078D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7733 0x41078D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7734 0x41078D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7735 0x41078DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7736 0x41078E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7737 0x41078E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7738 0x41078E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7739 0x41078EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7740 0x41078F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7741 0x41078F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7742 0x41078F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7743 0x41078FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7744 0x4107900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7745 0x4107904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7746 0x4107908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7747 0x410790C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7748 0x4107910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7749 0x4107914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7750 0x4107918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7751 0x410791C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7752 0x4107920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7753 0x4107924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7754 0x4107928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7755 0x410792C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7756 0x4107930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7757 0x4107934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7758 0x4107938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7759 0x410793C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7760 0x4107940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7761 0x4107944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7762 0x4107948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7763 0x410794C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7764 0x4107950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7765 0x4107954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7766 0x4107958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7767 0x410795C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7768 0x4107960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7769 0x4107964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7770 0x4107968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7771 0x410796C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7772 0x4107970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7773 0x4107974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7774 0x4107978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7775 0x410797C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7776 0x4107980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7777 0x4107984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7778 0x4107988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7779 0x410798C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7780 0x4107990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7781 0x4107994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7782 0x4107998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7783 0x410799C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7784 0x41079A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7785 0x41079A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7786 0x41079A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7787 0x41079AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7788 0x41079B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7789 0x41079B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7790 0x41079B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7791 0x41079BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7792 0x41079C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7793 0x41079C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7794 0x41079C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7795 0x41079CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7796 0x41079D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7797 0x41079D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7798 0x41079D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7799 0x41079DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7800 0x41079E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7801 0x41079E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7802 0x41079E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7803 0x41079EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7804 0x41079F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7805 0x41079F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7806 0x41079F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7807 0x41079FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7808 0x4107A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7809 0x4107A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7810 0x4107A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7811 0x4107A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7812 0x4107A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7813 0x4107A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7814 0x4107A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7815 0x4107A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7816 0x4107A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7817 0x4107A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7818 0x4107A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7819 0x4107A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7820 0x4107A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7821 0x4107A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7822 0x4107A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7823 0x4107A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7824 0x4107A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7825 0x4107A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7826 0x4107A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7827 0x4107A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7828 0x4107A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7829 0x4107A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7830 0x4107A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7831 0x4107A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7832 0x4107A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7833 0x4107A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7834 0x4107A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7835 0x4107A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7836 0x4107A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7837 0x4107A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7838 0x4107A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7839 0x4107A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7840 0x4107A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7841 0x4107A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7842 0x4107A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7843 0x4107A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7844 0x4107A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7845 0x4107A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7846 0x4107A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7847 0x4107A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7848 0x4107AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7849 0x4107AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7850 0x4107AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7851 0x4107AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7852 0x4107AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7853 0x4107AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7854 0x4107AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7855 0x4107ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7856 0x4107AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7857 0x4107AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7858 0x4107AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7859 0x4107ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7860 0x4107AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7861 0x4107AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7862 0x4107AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7863 0x4107ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7864 0x4107AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7865 0x4107AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7866 0x4107AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7867 0x4107AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7868 0x4107AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7869 0x4107AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7870 0x4107AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7871 0x4107AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7872 0x4107B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7873 0x4107B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7874 0x4107B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7875 0x4107B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7876 0x4107B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7877 0x4107B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7878 0x4107B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7879 0x4107B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7880 0x4107B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7881 0x4107B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7882 0x4107B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7883 0x4107B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7884 0x4107B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7885 0x4107B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7886 0x4107B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7887 0x4107B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7888 0x4107B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7889 0x4107B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7890 0x4107B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7891 0x4107B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7892 0x4107B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7893 0x4107B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7894 0x4107B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7895 0x4107B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7896 0x4107B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7897 0x4107B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7898 0x4107B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7899 0x4107B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7900 0x4107B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7901 0x4107B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7902 0x4107B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7903 0x4107B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7904 0x4107B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7905 0x4107B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7906 0x4107B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7907 0x4107B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7908 0x4107B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7909 0x4107B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7910 0x4107B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7911 0x4107B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7912 0x4107BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7913 0x4107BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7914 0x4107BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7915 0x4107BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7916 0x4107BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7917 0x4107BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7918 0x4107BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7919 0x4107BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7920 0x4107BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7921 0x4107BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7922 0x4107BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7923 0x4107BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7924 0x4107BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7925 0x4107BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7926 0x4107BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7927 0x4107BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7928 0x4107BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7929 0x4107BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7930 0x4107BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7931 0x4107BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7932 0x4107BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7933 0x4107BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7934 0x4107BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7935 0x4107BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7936 0x4107C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7937 0x4107C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7938 0x4107C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7939 0x4107C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7940 0x4107C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7941 0x4107C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7942 0x4107C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7943 0x4107C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7944 0x4107C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7945 0x4107C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7946 0x4107C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7947 0x4107C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7948 0x4107C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7949 0x4107C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7950 0x4107C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7951 0x4107C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7952 0x4107C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7953 0x4107C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7954 0x4107C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7955 0x4107C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7956 0x4107C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7957 0x4107C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7958 0x4107C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7959 0x4107C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7960 0x4107C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7961 0x4107C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7962 0x4107C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7963 0x4107C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7964 0x4107C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7965 0x4107C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7966 0x4107C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7967 0x4107C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7968 0x4107C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7969 0x4107C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7970 0x4107C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7971 0x4107C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7972 0x4107C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7973 0x4107C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7974 0x4107C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7975 0x4107C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7976 0x4107CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7977 0x4107CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7978 0x4107CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7979 0x4107CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7980 0x4107CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7981 0x4107CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7982 0x4107CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7983 0x4107CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7984 0x4107CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7985 0x4107CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7986 0x4107CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7987 0x4107CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7988 0x4107CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7989 0x4107CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7990 0x4107CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7991 0x4107CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7992 0x4107CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7993 0x4107CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7994 0x4107CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7995 0x4107CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7996 0x4107CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7997 0x4107CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7998 0x4107CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7999 0x4107CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8000 0x4107D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8001 0x4107D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8002 0x4107D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8003 0x4107D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8004 0x4107D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8005 0x4107D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8006 0x4107D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8007 0x4107D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8008 0x4107D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8009 0x4107D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8010 0x4107D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8011 0x4107D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8012 0x4107D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8013 0x4107D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8014 0x4107D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8015 0x4107D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8016 0x4107D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8017 0x4107D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8018 0x4107D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8019 0x4107D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8020 0x4107D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8021 0x4107D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8022 0x4107D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8023 0x4107D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8024 0x4107D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8025 0x4107D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8026 0x4107D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8027 0x4107D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8028 0x4107D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8029 0x4107D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8030 0x4107D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8031 0x4107D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8032 0x4107D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8033 0x4107D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8034 0x4107D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8035 0x4107D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8036 0x4107D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8037 0x4107D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8038 0x4107D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8039 0x4107D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8040 0x4107DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8041 0x4107DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8042 0x4107DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8043 0x4107DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8044 0x4107DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8045 0x4107DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8046 0x4107DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8047 0x4107DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8048 0x4107DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8049 0x4107DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8050 0x4107DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8051 0x4107DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8052 0x4107DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8053 0x4107DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8054 0x4107DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8055 0x4107DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8056 0x4107DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8057 0x4107DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8058 0x4107DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8059 0x4107DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8060 0x4107DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8061 0x4107DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8062 0x4107DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8063 0x4107DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8064 0x4107E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8065 0x4107E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8066 0x4107E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8067 0x4107E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8068 0x4107E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8069 0x4107E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8070 0x4107E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8071 0x4107E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8072 0x4107E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8073 0x4107E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8074 0x4107E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8075 0x4107E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8076 0x4107E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8077 0x4107E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8078 0x4107E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8079 0x4107E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8080 0x4107E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8081 0x4107E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8082 0x4107E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8083 0x4107E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8084 0x4107E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8085 0x4107E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8086 0x4107E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8087 0x4107E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8088 0x4107E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8089 0x4107E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8090 0x4107E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8091 0x4107E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8092 0x4107E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8093 0x4107E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8094 0x4107E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8095 0x4107E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8096 0x4107E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8097 0x4107E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8098 0x4107E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8099 0x4107E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8100 0x4107E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8101 0x4107E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8102 0x4107E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8103 0x4107E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8104 0x4107EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8105 0x4107EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8106 0x4107EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8107 0x4107EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8108 0x4107EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8109 0x4107EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8110 0x4107EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8111 0x4107EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8112 0x4107EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8113 0x4107EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8114 0x4107EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8115 0x4107ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8116 0x4107ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8117 0x4107ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8118 0x4107ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8119 0x4107EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8120 0x4107EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8121 0x4107EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8122 0x4107EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8123 0x4107EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8124 0x4107EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8125 0x4107EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8126 0x4107EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8127 0x4107EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8128 0x4107F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8129 0x4107F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8130 0x4107F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8131 0x4107F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8132 0x4107F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8133 0x4107F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8134 0x4107F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8135 0x4107F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8136 0x4107F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8137 0x4107F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8138 0x4107F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8139 0x4107F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8140 0x4107F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8141 0x4107F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8142 0x4107F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8143 0x4107F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8144 0x4107F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8145 0x4107F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8146 0x4107F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8147 0x4107F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8148 0x4107F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8149 0x4107F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8150 0x4107F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8151 0x4107F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8152 0x4107F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8153 0x4107F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8154 0x4107F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8155 0x4107F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8156 0x4107F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8157 0x4107F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8158 0x4107F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8159 0x4107F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8160 0x4107F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8161 0x4107F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8162 0x4107F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8163 0x4107F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8164 0x4107F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8165 0x4107F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8166 0x4107F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8167 0x4107F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8168 0x4107FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8169 0x4107FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8170 0x4107FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8171 0x4107FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8172 0x4107FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8173 0x4107FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8174 0x4107FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8175 0x4107FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8176 0x4107FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8177 0x4107FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8178 0x4107FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8179 0x4107FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8180 0x4107FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8181 0x4107FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8182 0x4107FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8183 0x4107FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8184 0x4107FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8185 0x4107FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8186 0x4107FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8187 0x4107FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8188 0x4107FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8189 0x4107FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8190 0x4107FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 0x4107FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4108000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1 0x4108004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2 0x4108008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_3 0x410800C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_4 0x4108010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_5 0x4108014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_6 0x4108018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_7 0x410801C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_8 0x4108020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_9 0x4108024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_10 0x4108028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_11 0x410802C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_12 0x4108030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_13 0x4108034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_14 0x4108038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_15 0x410803C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_16 0x4108040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_17 0x4108044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_18 0x4108048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_19 0x410804C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_20 0x4108050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_21 0x4108054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_22 0x4108058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_23 0x410805C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_24 0x4108060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_25 0x4108064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_26 0x4108068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_27 0x410806C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_28 0x4108070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_29 0x4108074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_30 0x4108078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_31 0x410807C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_32 0x4108080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_33 0x4108084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_34 0x4108088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_35 0x410808C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_36 0x4108090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_37 0x4108094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_38 0x4108098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_39 0x410809C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_40 0x41080A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_41 0x41080A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_42 0x41080A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_43 0x41080AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_44 0x41080B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_45 0x41080B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_46 0x41080B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_47 0x41080BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_48 0x41080C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_49 0x41080C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_50 0x41080C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_51 0x41080CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_52 0x41080D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_53 0x41080D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_54 0x41080D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_55 0x41080DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_56 0x41080E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_57 0x41080E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_58 0x41080E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_59 0x41080EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_60 0x41080F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_61 0x41080F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_62 0x41080F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_63 0x41080FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_64 0x4108100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_65 0x4108104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_66 0x4108108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_67 0x410810C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_68 0x4108110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_69 0x4108114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_70 0x4108118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_71 0x410811C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_72 0x4108120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_73 0x4108124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_74 0x4108128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_75 0x410812C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_76 0x4108130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_77 0x4108134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_78 0x4108138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_79 0x410813C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_80 0x4108140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_81 0x4108144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_82 0x4108148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_83 0x410814C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_84 0x4108150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_85 0x4108154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_86 0x4108158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_87 0x410815C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_88 0x4108160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_89 0x4108164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_90 0x4108168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_91 0x410816C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_92 0x4108170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_93 0x4108174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_94 0x4108178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_95 0x410817C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_96 0x4108180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_97 0x4108184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_98 0x4108188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_99 0x410818C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_100 0x4108190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_101 0x4108194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_102 0x4108198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_103 0x410819C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_104 0x41081A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_105 0x41081A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_106 0x41081A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_107 0x41081AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_108 0x41081B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_109 0x41081B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_110 0x41081B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_111 0x41081BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_112 0x41081C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_113 0x41081C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_114 0x41081C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_115 0x41081CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_116 0x41081D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_117 0x41081D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_118 0x41081D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_119 0x41081DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_120 0x41081E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_121 0x41081E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_122 0x41081E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_123 0x41081EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_124 0x41081F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_125 0x41081F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_126 0x41081F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_127 0x41081FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_128 0x4108200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_129 0x4108204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_130 0x4108208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_131 0x410820C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_132 0x4108210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_133 0x4108214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_134 0x4108218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_135 0x410821C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_136 0x4108220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_137 0x4108224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_138 0x4108228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_139 0x410822C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_140 0x4108230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_141 0x4108234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_142 0x4108238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_143 0x410823C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_144 0x4108240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_145 0x4108244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_146 0x4108248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_147 0x410824C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_148 0x4108250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_149 0x4108254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_150 0x4108258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_151 0x410825C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_152 0x4108260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_153 0x4108264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_154 0x4108268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_155 0x410826C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_156 0x4108270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_157 0x4108274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_158 0x4108278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_159 0x410827C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_160 0x4108280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_161 0x4108284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_162 0x4108288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_163 0x410828C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_164 0x4108290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_165 0x4108294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_166 0x4108298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_167 0x410829C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_168 0x41082A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_169 0x41082A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_170 0x41082A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_171 0x41082AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_172 0x41082B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_173 0x41082B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_174 0x41082B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_175 0x41082BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_176 0x41082C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_177 0x41082C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_178 0x41082C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_179 0x41082CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_180 0x41082D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_181 0x41082D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_182 0x41082D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_183 0x41082DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_184 0x41082E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_185 0x41082E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_186 0x41082E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_187 0x41082EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_188 0x41082F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_189 0x41082F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_190 0x41082F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_191 0x41082FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_192 0x4108300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_193 0x4108304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_194 0x4108308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_195 0x410830C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_196 0x4108310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_197 0x4108314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_198 0x4108318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_199 0x410831C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_200 0x4108320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_201 0x4108324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_202 0x4108328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_203 0x410832C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_204 0x4108330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_205 0x4108334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_206 0x4108338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_207 0x410833C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_208 0x4108340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_209 0x4108344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_210 0x4108348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_211 0x410834C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_212 0x4108350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_213 0x4108354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_214 0x4108358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_215 0x410835C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_216 0x4108360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_217 0x4108364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_218 0x4108368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_219 0x410836C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_220 0x4108370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_221 0x4108374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_222 0x4108378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_223 0x410837C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_224 0x4108380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_225 0x4108384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_226 0x4108388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_227 0x410838C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_228 0x4108390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_229 0x4108394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_230 0x4108398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_231 0x410839C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_232 0x41083A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_233 0x41083A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_234 0x41083A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_235 0x41083AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_236 0x41083B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_237 0x41083B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_238 0x41083B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_239 0x41083BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_240 0x41083C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_241 0x41083C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_242 0x41083C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_243 0x41083CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_244 0x41083D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_245 0x41083D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_246 0x41083D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_247 0x41083DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_248 0x41083E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_249 0x41083E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_250 0x41083E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_251 0x41083EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_252 0x41083F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_253 0x41083F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_254 0x41083F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_255 0x41083FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_256 0x4108400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_257 0x4108404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_258 0x4108408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_259 0x410840C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_260 0x4108410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_261 0x4108414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_262 0x4108418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_263 0x410841C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_264 0x4108420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_265 0x4108424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_266 0x4108428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_267 0x410842C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_268 0x4108430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_269 0x4108434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_270 0x4108438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_271 0x410843C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_272 0x4108440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_273 0x4108444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_274 0x4108448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_275 0x410844C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_276 0x4108450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_277 0x4108454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_278 0x4108458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_279 0x410845C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_280 0x4108460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_281 0x4108464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_282 0x4108468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_283 0x410846C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_284 0x4108470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_285 0x4108474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_286 0x4108478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_287 0x410847C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_288 0x4108480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_289 0x4108484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_290 0x4108488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_291 0x410848C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_292 0x4108490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_293 0x4108494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_294 0x4108498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_295 0x410849C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_296 0x41084A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_297 0x41084A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_298 0x41084A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_299 0x41084AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_300 0x41084B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_301 0x41084B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_302 0x41084B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_303 0x41084BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_304 0x41084C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_305 0x41084C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_306 0x41084C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_307 0x41084CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_308 0x41084D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_309 0x41084D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_310 0x41084D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_311 0x41084DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_312 0x41084E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_313 0x41084E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_314 0x41084E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_315 0x41084EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_316 0x41084F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_317 0x41084F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_318 0x41084F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_319 0x41084FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_320 0x4108500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_321 0x4108504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_322 0x4108508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_323 0x410850C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_324 0x4108510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_325 0x4108514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_326 0x4108518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_327 0x410851C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_328 0x4108520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_329 0x4108524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_330 0x4108528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_331 0x410852C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_332 0x4108530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_333 0x4108534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_334 0x4108538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_335 0x410853C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_336 0x4108540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_337 0x4108544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_338 0x4108548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_339 0x410854C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_340 0x4108550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_341 0x4108554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_342 0x4108558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_343 0x410855C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_344 0x4108560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_345 0x4108564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_346 0x4108568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_347 0x410856C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_348 0x4108570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_349 0x4108574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_350 0x4108578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_351 0x410857C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_352 0x4108580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_353 0x4108584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_354 0x4108588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_355 0x410858C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_356 0x4108590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_357 0x4108594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_358 0x4108598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_359 0x410859C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_360 0x41085A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_361 0x41085A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_362 0x41085A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_363 0x41085AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_364 0x41085B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_365 0x41085B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_366 0x41085B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_367 0x41085BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_368 0x41085C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_369 0x41085C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_370 0x41085C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_371 0x41085CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_372 0x41085D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_373 0x41085D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_374 0x41085D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_375 0x41085DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_376 0x41085E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_377 0x41085E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_378 0x41085E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_379 0x41085EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_380 0x41085F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_381 0x41085F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_382 0x41085F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_383 0x41085FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_384 0x4108600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_385 0x4108604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_386 0x4108608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_387 0x410860C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_388 0x4108610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_389 0x4108614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_390 0x4108618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_391 0x410861C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_392 0x4108620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_393 0x4108624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_394 0x4108628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_395 0x410862C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_396 0x4108630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_397 0x4108634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_398 0x4108638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_399 0x410863C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_400 0x4108640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_401 0x4108644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_402 0x4108648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_403 0x410864C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_404 0x4108650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_405 0x4108654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_406 0x4108658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_407 0x410865C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_408 0x4108660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_409 0x4108664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_410 0x4108668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_411 0x410866C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_412 0x4108670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_413 0x4108674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_414 0x4108678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_415 0x410867C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_416 0x4108680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_417 0x4108684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_418 0x4108688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_419 0x410868C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_420 0x4108690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_421 0x4108694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_422 0x4108698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_423 0x410869C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_424 0x41086A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_425 0x41086A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_426 0x41086A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_427 0x41086AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_428 0x41086B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_429 0x41086B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_430 0x41086B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_431 0x41086BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_432 0x41086C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_433 0x41086C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_434 0x41086C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_435 0x41086CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_436 0x41086D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_437 0x41086D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_438 0x41086D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_439 0x41086DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_440 0x41086E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_441 0x41086E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_442 0x41086E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_443 0x41086EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_444 0x41086F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_445 0x41086F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_446 0x41086F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_447 0x41086FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_448 0x4108700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_449 0x4108704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_450 0x4108708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_451 0x410870C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_452 0x4108710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_453 0x4108714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_454 0x4108718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_455 0x410871C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_456 0x4108720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_457 0x4108724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_458 0x4108728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_459 0x410872C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_460 0x4108730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_461 0x4108734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_462 0x4108738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_463 0x410873C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_464 0x4108740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_465 0x4108744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_466 0x4108748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_467 0x410874C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_468 0x4108750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_469 0x4108754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_470 0x4108758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_471 0x410875C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_472 0x4108760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_473 0x4108764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_474 0x4108768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_475 0x410876C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_476 0x4108770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_477 0x4108774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_478 0x4108778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_479 0x410877C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_480 0x4108780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_481 0x4108784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_482 0x4108788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_483 0x410878C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_484 0x4108790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_485 0x4108794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_486 0x4108798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_487 0x410879C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_488 0x41087A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_489 0x41087A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_490 0x41087A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_491 0x41087AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_492 0x41087B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_493 0x41087B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_494 0x41087B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_495 0x41087BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_496 0x41087C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_497 0x41087C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_498 0x41087C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_499 0x41087CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_500 0x41087D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_501 0x41087D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_502 0x41087D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_503 0x41087DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_504 0x41087E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_505 0x41087E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_506 0x41087E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_507 0x41087EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_508 0x41087F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_509 0x41087F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_510 0x41087F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_511 0x41087FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_512 0x4108800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_513 0x4108804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_514 0x4108808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_515 0x410880C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_516 0x4108810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_517 0x4108814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_518 0x4108818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_519 0x410881C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_520 0x4108820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_521 0x4108824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_522 0x4108828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_523 0x410882C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_524 0x4108830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_525 0x4108834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_526 0x4108838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_527 0x410883C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_528 0x4108840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_529 0x4108844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_530 0x4108848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_531 0x410884C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_532 0x4108850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_533 0x4108854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_534 0x4108858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_535 0x410885C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_536 0x4108860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_537 0x4108864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_538 0x4108868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_539 0x410886C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_540 0x4108870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_541 0x4108874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_542 0x4108878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_543 0x410887C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_544 0x4108880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_545 0x4108884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_546 0x4108888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_547 0x410888C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_548 0x4108890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_549 0x4108894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_550 0x4108898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_551 0x410889C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_552 0x41088A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_553 0x41088A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_554 0x41088A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_555 0x41088AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_556 0x41088B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_557 0x41088B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_558 0x41088B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_559 0x41088BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_560 0x41088C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_561 0x41088C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_562 0x41088C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_563 0x41088CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_564 0x41088D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_565 0x41088D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_566 0x41088D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_567 0x41088DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_568 0x41088E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_569 0x41088E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_570 0x41088E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_571 0x41088EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_572 0x41088F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_573 0x41088F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_574 0x41088F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_575 0x41088FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_576 0x4108900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_577 0x4108904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_578 0x4108908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_579 0x410890C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_580 0x4108910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_581 0x4108914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_582 0x4108918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_583 0x410891C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_584 0x4108920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_585 0x4108924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_586 0x4108928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_587 0x410892C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_588 0x4108930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_589 0x4108934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_590 0x4108938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_591 0x410893C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_592 0x4108940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_593 0x4108944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_594 0x4108948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_595 0x410894C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_596 0x4108950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_597 0x4108954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_598 0x4108958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_599 0x410895C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_600 0x4108960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_601 0x4108964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_602 0x4108968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_603 0x410896C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_604 0x4108970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_605 0x4108974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_606 0x4108978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_607 0x410897C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_608 0x4108980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_609 0x4108984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_610 0x4108988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_611 0x410898C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_612 0x4108990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_613 0x4108994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_614 0x4108998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_615 0x410899C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_616 0x41089A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_617 0x41089A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_618 0x41089A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_619 0x41089AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_620 0x41089B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_621 0x41089B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_622 0x41089B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_623 0x41089BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_624 0x41089C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_625 0x41089C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_626 0x41089C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_627 0x41089CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_628 0x41089D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_629 0x41089D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_630 0x41089D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_631 0x41089DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_632 0x41089E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_633 0x41089E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_634 0x41089E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_635 0x41089EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_636 0x41089F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_637 0x41089F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_638 0x41089F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_639 0x41089FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_640 0x4108A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_641 0x4108A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_642 0x4108A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_643 0x4108A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_644 0x4108A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_645 0x4108A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_646 0x4108A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_647 0x4108A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_648 0x4108A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_649 0x4108A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_650 0x4108A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_651 0x4108A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_652 0x4108A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_653 0x4108A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_654 0x4108A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_655 0x4108A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_656 0x4108A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_657 0x4108A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_658 0x4108A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_659 0x4108A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_660 0x4108A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_661 0x4108A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_662 0x4108A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_663 0x4108A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_664 0x4108A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_665 0x4108A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_666 0x4108A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_667 0x4108A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_668 0x4108A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_669 0x4108A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_670 0x4108A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_671 0x4108A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_672 0x4108A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_673 0x4108A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_674 0x4108A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_675 0x4108A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_676 0x4108A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_677 0x4108A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_678 0x4108A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_679 0x4108A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_680 0x4108AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_681 0x4108AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_682 0x4108AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_683 0x4108AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_684 0x4108AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_685 0x4108AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_686 0x4108AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_687 0x4108ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_688 0x4108AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_689 0x4108AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_690 0x4108AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_691 0x4108ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_692 0x4108AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_693 0x4108AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_694 0x4108AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_695 0x4108ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_696 0x4108AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_697 0x4108AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_698 0x4108AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_699 0x4108AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_700 0x4108AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_701 0x4108AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_702 0x4108AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_703 0x4108AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_704 0x4108B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_705 0x4108B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_706 0x4108B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_707 0x4108B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_708 0x4108B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_709 0x4108B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_710 0x4108B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_711 0x4108B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_712 0x4108B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_713 0x4108B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_714 0x4108B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_715 0x4108B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_716 0x4108B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_717 0x4108B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_718 0x4108B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_719 0x4108B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_720 0x4108B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_721 0x4108B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_722 0x4108B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_723 0x4108B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_724 0x4108B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_725 0x4108B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_726 0x4108B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_727 0x4108B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_728 0x4108B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_729 0x4108B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_730 0x4108B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_731 0x4108B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_732 0x4108B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_733 0x4108B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_734 0x4108B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_735 0x4108B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_736 0x4108B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_737 0x4108B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_738 0x4108B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_739 0x4108B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_740 0x4108B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_741 0x4108B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_742 0x4108B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_743 0x4108B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_744 0x4108BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_745 0x4108BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_746 0x4108BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_747 0x4108BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_748 0x4108BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_749 0x4108BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_750 0x4108BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_751 0x4108BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_752 0x4108BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_753 0x4108BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_754 0x4108BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_755 0x4108BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_756 0x4108BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_757 0x4108BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_758 0x4108BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_759 0x4108BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_760 0x4108BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_761 0x4108BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_762 0x4108BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_763 0x4108BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_764 0x4108BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_765 0x4108BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_766 0x4108BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_767 0x4108BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_768 0x4108C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_769 0x4108C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_770 0x4108C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_771 0x4108C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_772 0x4108C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_773 0x4108C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_774 0x4108C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_775 0x4108C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_776 0x4108C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_777 0x4108C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_778 0x4108C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_779 0x4108C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_780 0x4108C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_781 0x4108C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_782 0x4108C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_783 0x4108C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_784 0x4108C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_785 0x4108C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_786 0x4108C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_787 0x4108C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_788 0x4108C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_789 0x4108C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_790 0x4108C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_791 0x4108C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_792 0x4108C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_793 0x4108C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_794 0x4108C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_795 0x4108C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_796 0x4108C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_797 0x4108C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_798 0x4108C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_799 0x4108C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_800 0x4108C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_801 0x4108C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_802 0x4108C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_803 0x4108C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_804 0x4108C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_805 0x4108C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_806 0x4108C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_807 0x4108C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_808 0x4108CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_809 0x4108CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_810 0x4108CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_811 0x4108CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_812 0x4108CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_813 0x4108CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_814 0x4108CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_815 0x4108CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_816 0x4108CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_817 0x4108CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_818 0x4108CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_819 0x4108CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_820 0x4108CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_821 0x4108CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_822 0x4108CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_823 0x4108CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_824 0x4108CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_825 0x4108CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_826 0x4108CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_827 0x4108CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_828 0x4108CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_829 0x4108CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_830 0x4108CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_831 0x4108CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_832 0x4108D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_833 0x4108D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_834 0x4108D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_835 0x4108D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_836 0x4108D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_837 0x4108D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_838 0x4108D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_839 0x4108D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_840 0x4108D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_841 0x4108D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_842 0x4108D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_843 0x4108D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_844 0x4108D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_845 0x4108D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_846 0x4108D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_847 0x4108D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_848 0x4108D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_849 0x4108D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_850 0x4108D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_851 0x4108D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_852 0x4108D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_853 0x4108D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_854 0x4108D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_855 0x4108D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_856 0x4108D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_857 0x4108D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_858 0x4108D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_859 0x4108D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_860 0x4108D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_861 0x4108D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_862 0x4108D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_863 0x4108D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_864 0x4108D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_865 0x4108D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_866 0x4108D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_867 0x4108D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_868 0x4108D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_869 0x4108D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_870 0x4108D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_871 0x4108D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_872 0x4108DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_873 0x4108DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_874 0x4108DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_875 0x4108DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_876 0x4108DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_877 0x4108DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_878 0x4108DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_879 0x4108DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_880 0x4108DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_881 0x4108DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_882 0x4108DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_883 0x4108DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_884 0x4108DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_885 0x4108DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_886 0x4108DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_887 0x4108DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_888 0x4108DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_889 0x4108DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_890 0x4108DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_891 0x4108DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_892 0x4108DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_893 0x4108DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_894 0x4108DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_895 0x4108DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_896 0x4108E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_897 0x4108E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_898 0x4108E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_899 0x4108E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_900 0x4108E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_901 0x4108E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_902 0x4108E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_903 0x4108E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_904 0x4108E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_905 0x4108E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_906 0x4108E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_907 0x4108E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_908 0x4108E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_909 0x4108E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_910 0x4108E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_911 0x4108E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_912 0x4108E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_913 0x4108E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_914 0x4108E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_915 0x4108E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_916 0x4108E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_917 0x4108E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_918 0x4108E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_919 0x4108E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_920 0x4108E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_921 0x4108E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_922 0x4108E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_923 0x4108E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_924 0x4108E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_925 0x4108E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_926 0x4108E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_927 0x4108E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_928 0x4108E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_929 0x4108E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_930 0x4108E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_931 0x4108E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_932 0x4108E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_933 0x4108E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_934 0x4108E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_935 0x4108E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_936 0x4108EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_937 0x4108EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_938 0x4108EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_939 0x4108EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_940 0x4108EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_941 0x4108EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_942 0x4108EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_943 0x4108EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_944 0x4108EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_945 0x4108EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_946 0x4108EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_947 0x4108ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_948 0x4108ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_949 0x4108ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_950 0x4108ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_951 0x4108EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_952 0x4108EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_953 0x4108EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_954 0x4108EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_955 0x4108EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_956 0x4108EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_957 0x4108EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_958 0x4108EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_959 0x4108EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_960 0x4108F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_961 0x4108F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_962 0x4108F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_963 0x4108F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_964 0x4108F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_965 0x4108F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_966 0x4108F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_967 0x4108F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_968 0x4108F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_969 0x4108F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_970 0x4108F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_971 0x4108F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_972 0x4108F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_973 0x4108F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_974 0x4108F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_975 0x4108F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_976 0x4108F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_977 0x4108F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_978 0x4108F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_979 0x4108F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_980 0x4108F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_981 0x4108F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_982 0x4108F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_983 0x4108F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_984 0x4108F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_985 0x4108F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_986 0x4108F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_987 0x4108F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_988 0x4108F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_989 0x4108F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_990 0x4108F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_991 0x4108F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_992 0x4108F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_993 0x4108F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_994 0x4108F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_995 0x4108F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_996 0x4108F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_997 0x4108F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_998 0x4108F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_999 0x4108F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1000 0x4108FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1001 0x4108FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1002 0x4108FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1003 0x4108FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1004 0x4108FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1005 0x4108FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1006 0x4108FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1007 0x4108FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1008 0x4108FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1009 0x4108FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1010 0x4108FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1011 0x4108FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1012 0x4108FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1013 0x4108FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1014 0x4108FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1015 0x4108FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1016 0x4108FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1017 0x4108FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1018 0x4108FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1019 0x4108FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1020 0x4108FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1021 0x4108FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1022 0x4108FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1023 0x4108FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1024 0x4109000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1025 0x4109004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1026 0x4109008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1027 0x410900C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1028 0x4109010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1029 0x4109014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1030 0x4109018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1031 0x410901C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1032 0x4109020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1033 0x4109024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1034 0x4109028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1035 0x410902C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1036 0x4109030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1037 0x4109034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1038 0x4109038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1039 0x410903C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1040 0x4109040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1041 0x4109044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1042 0x4109048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1043 0x410904C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1044 0x4109050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1045 0x4109054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1046 0x4109058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1047 0x410905C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1048 0x4109060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1049 0x4109064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1050 0x4109068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1051 0x410906C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1052 0x4109070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1053 0x4109074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1054 0x4109078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1055 0x410907C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1056 0x4109080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1057 0x4109084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1058 0x4109088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1059 0x410908C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1060 0x4109090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1061 0x4109094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1062 0x4109098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1063 0x410909C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1064 0x41090A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1065 0x41090A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1066 0x41090A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1067 0x41090AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1068 0x41090B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1069 0x41090B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1070 0x41090B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1071 0x41090BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1072 0x41090C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1073 0x41090C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1074 0x41090C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1075 0x41090CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1076 0x41090D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1077 0x41090D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1078 0x41090D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1079 0x41090DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1080 0x41090E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1081 0x41090E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1082 0x41090E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1083 0x41090EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1084 0x41090F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1085 0x41090F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1086 0x41090F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1087 0x41090FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1088 0x4109100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1089 0x4109104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1090 0x4109108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1091 0x410910C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1092 0x4109110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1093 0x4109114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1094 0x4109118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1095 0x410911C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1096 0x4109120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1097 0x4109124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1098 0x4109128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1099 0x410912C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1100 0x4109130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1101 0x4109134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1102 0x4109138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1103 0x410913C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1104 0x4109140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1105 0x4109144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1106 0x4109148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1107 0x410914C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1108 0x4109150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1109 0x4109154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1110 0x4109158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1111 0x410915C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1112 0x4109160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1113 0x4109164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1114 0x4109168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1115 0x410916C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1116 0x4109170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1117 0x4109174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1118 0x4109178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1119 0x410917C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1120 0x4109180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1121 0x4109184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1122 0x4109188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1123 0x410918C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1124 0x4109190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1125 0x4109194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1126 0x4109198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1127 0x410919C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1128 0x41091A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1129 0x41091A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1130 0x41091A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1131 0x41091AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1132 0x41091B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1133 0x41091B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1134 0x41091B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1135 0x41091BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1136 0x41091C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1137 0x41091C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1138 0x41091C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1139 0x41091CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1140 0x41091D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1141 0x41091D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1142 0x41091D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1143 0x41091DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1144 0x41091E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1145 0x41091E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1146 0x41091E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1147 0x41091EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1148 0x41091F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1149 0x41091F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1150 0x41091F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1151 0x41091FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1152 0x4109200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1153 0x4109204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1154 0x4109208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1155 0x410920C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1156 0x4109210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1157 0x4109214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1158 0x4109218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1159 0x410921C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1160 0x4109220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1161 0x4109224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1162 0x4109228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1163 0x410922C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1164 0x4109230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1165 0x4109234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1166 0x4109238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1167 0x410923C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1168 0x4109240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1169 0x4109244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1170 0x4109248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1171 0x410924C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1172 0x4109250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1173 0x4109254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1174 0x4109258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1175 0x410925C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1176 0x4109260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1177 0x4109264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1178 0x4109268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1179 0x410926C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1180 0x4109270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1181 0x4109274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1182 0x4109278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1183 0x410927C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1184 0x4109280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1185 0x4109284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1186 0x4109288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1187 0x410928C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1188 0x4109290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1189 0x4109294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1190 0x4109298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1191 0x410929C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1192 0x41092A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1193 0x41092A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1194 0x41092A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1195 0x41092AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1196 0x41092B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1197 0x41092B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1198 0x41092B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1199 0x41092BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1200 0x41092C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1201 0x41092C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1202 0x41092C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1203 0x41092CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1204 0x41092D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1205 0x41092D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1206 0x41092D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1207 0x41092DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1208 0x41092E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1209 0x41092E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1210 0x41092E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1211 0x41092EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1212 0x41092F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1213 0x41092F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1214 0x41092F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1215 0x41092FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1216 0x4109300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1217 0x4109304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1218 0x4109308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1219 0x410930C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1220 0x4109310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1221 0x4109314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1222 0x4109318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1223 0x410931C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1224 0x4109320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1225 0x4109324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1226 0x4109328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1227 0x410932C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1228 0x4109330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1229 0x4109334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1230 0x4109338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1231 0x410933C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1232 0x4109340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1233 0x4109344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1234 0x4109348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1235 0x410934C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1236 0x4109350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1237 0x4109354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1238 0x4109358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1239 0x410935C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1240 0x4109360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1241 0x4109364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1242 0x4109368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1243 0x410936C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1244 0x4109370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1245 0x4109374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1246 0x4109378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1247 0x410937C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1248 0x4109380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1249 0x4109384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1250 0x4109388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1251 0x410938C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1252 0x4109390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1253 0x4109394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1254 0x4109398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1255 0x410939C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1256 0x41093A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1257 0x41093A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1258 0x41093A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1259 0x41093AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1260 0x41093B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1261 0x41093B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1262 0x41093B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1263 0x41093BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1264 0x41093C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1265 0x41093C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1266 0x41093C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1267 0x41093CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1268 0x41093D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1269 0x41093D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1270 0x41093D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1271 0x41093DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1272 0x41093E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1273 0x41093E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1274 0x41093E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1275 0x41093EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1276 0x41093F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1277 0x41093F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1278 0x41093F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1279 0x41093FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1280 0x4109400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1281 0x4109404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1282 0x4109408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1283 0x410940C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1284 0x4109410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1285 0x4109414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1286 0x4109418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1287 0x410941C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1288 0x4109420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1289 0x4109424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1290 0x4109428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1291 0x410942C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1292 0x4109430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1293 0x4109434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1294 0x4109438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1295 0x410943C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1296 0x4109440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1297 0x4109444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1298 0x4109448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1299 0x410944C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1300 0x4109450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1301 0x4109454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1302 0x4109458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1303 0x410945C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1304 0x4109460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1305 0x4109464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1306 0x4109468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1307 0x410946C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1308 0x4109470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1309 0x4109474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1310 0x4109478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1311 0x410947C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1312 0x4109480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1313 0x4109484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1314 0x4109488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1315 0x410948C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1316 0x4109490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1317 0x4109494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1318 0x4109498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1319 0x410949C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1320 0x41094A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1321 0x41094A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1322 0x41094A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1323 0x41094AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1324 0x41094B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1325 0x41094B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1326 0x41094B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1327 0x41094BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1328 0x41094C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1329 0x41094C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1330 0x41094C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1331 0x41094CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1332 0x41094D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1333 0x41094D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1334 0x41094D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1335 0x41094DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1336 0x41094E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1337 0x41094E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1338 0x41094E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1339 0x41094EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1340 0x41094F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1341 0x41094F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1342 0x41094F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1343 0x41094FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1344 0x4109500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1345 0x4109504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1346 0x4109508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1347 0x410950C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1348 0x4109510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1349 0x4109514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1350 0x4109518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1351 0x410951C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1352 0x4109520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1353 0x4109524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1354 0x4109528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1355 0x410952C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1356 0x4109530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1357 0x4109534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1358 0x4109538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1359 0x410953C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1360 0x4109540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1361 0x4109544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1362 0x4109548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1363 0x410954C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1364 0x4109550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1365 0x4109554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1366 0x4109558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1367 0x410955C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1368 0x4109560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1369 0x4109564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1370 0x4109568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1371 0x410956C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1372 0x4109570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1373 0x4109574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1374 0x4109578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1375 0x410957C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1376 0x4109580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1377 0x4109584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1378 0x4109588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1379 0x410958C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1380 0x4109590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1381 0x4109594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1382 0x4109598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1383 0x410959C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1384 0x41095A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1385 0x41095A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1386 0x41095A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1387 0x41095AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1388 0x41095B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1389 0x41095B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1390 0x41095B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1391 0x41095BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1392 0x41095C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1393 0x41095C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1394 0x41095C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1395 0x41095CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1396 0x41095D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1397 0x41095D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1398 0x41095D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1399 0x41095DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1400 0x41095E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1401 0x41095E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1402 0x41095E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1403 0x41095EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1404 0x41095F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1405 0x41095F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1406 0x41095F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1407 0x41095FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1408 0x4109600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1409 0x4109604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1410 0x4109608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1411 0x410960C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1412 0x4109610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1413 0x4109614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1414 0x4109618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1415 0x410961C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1416 0x4109620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1417 0x4109624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1418 0x4109628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1419 0x410962C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1420 0x4109630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1421 0x4109634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1422 0x4109638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1423 0x410963C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1424 0x4109640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1425 0x4109644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1426 0x4109648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1427 0x410964C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1428 0x4109650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1429 0x4109654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1430 0x4109658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1431 0x410965C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1432 0x4109660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1433 0x4109664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1434 0x4109668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1435 0x410966C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1436 0x4109670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1437 0x4109674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1438 0x4109678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1439 0x410967C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1440 0x4109680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1441 0x4109684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1442 0x4109688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1443 0x410968C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1444 0x4109690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1445 0x4109694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1446 0x4109698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1447 0x410969C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1448 0x41096A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1449 0x41096A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1450 0x41096A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1451 0x41096AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1452 0x41096B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1453 0x41096B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1454 0x41096B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1455 0x41096BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1456 0x41096C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1457 0x41096C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1458 0x41096C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1459 0x41096CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1460 0x41096D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1461 0x41096D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1462 0x41096D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1463 0x41096DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1464 0x41096E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1465 0x41096E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1466 0x41096E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1467 0x41096EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1468 0x41096F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1469 0x41096F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1470 0x41096F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1471 0x41096FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1472 0x4109700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1473 0x4109704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1474 0x4109708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1475 0x410970C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1476 0x4109710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1477 0x4109714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1478 0x4109718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1479 0x410971C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1480 0x4109720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1481 0x4109724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1482 0x4109728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1483 0x410972C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1484 0x4109730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1485 0x4109734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1486 0x4109738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1487 0x410973C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1488 0x4109740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1489 0x4109744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1490 0x4109748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1491 0x410974C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1492 0x4109750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1493 0x4109754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1494 0x4109758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1495 0x410975C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1496 0x4109760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1497 0x4109764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1498 0x4109768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1499 0x410976C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1500 0x4109770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1501 0x4109774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1502 0x4109778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1503 0x410977C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1504 0x4109780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1505 0x4109784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1506 0x4109788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1507 0x410978C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1508 0x4109790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1509 0x4109794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1510 0x4109798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1511 0x410979C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1512 0x41097A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1513 0x41097A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1514 0x41097A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1515 0x41097AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1516 0x41097B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1517 0x41097B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1518 0x41097B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1519 0x41097BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1520 0x41097C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1521 0x41097C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1522 0x41097C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1523 0x41097CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1524 0x41097D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1525 0x41097D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1526 0x41097D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1527 0x41097DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1528 0x41097E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1529 0x41097E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1530 0x41097E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1531 0x41097EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1532 0x41097F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1533 0x41097F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1534 0x41097F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1535 0x41097FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1536 0x4109800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1537 0x4109804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1538 0x4109808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1539 0x410980C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1540 0x4109810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1541 0x4109814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1542 0x4109818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1543 0x410981C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1544 0x4109820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1545 0x4109824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1546 0x4109828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1547 0x410982C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1548 0x4109830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1549 0x4109834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1550 0x4109838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1551 0x410983C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1552 0x4109840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1553 0x4109844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1554 0x4109848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1555 0x410984C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1556 0x4109850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1557 0x4109854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1558 0x4109858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1559 0x410985C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1560 0x4109860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1561 0x4109864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1562 0x4109868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1563 0x410986C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1564 0x4109870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1565 0x4109874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1566 0x4109878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1567 0x410987C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1568 0x4109880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1569 0x4109884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1570 0x4109888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1571 0x410988C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1572 0x4109890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1573 0x4109894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1574 0x4109898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1575 0x410989C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1576 0x41098A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1577 0x41098A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1578 0x41098A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1579 0x41098AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1580 0x41098B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1581 0x41098B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1582 0x41098B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1583 0x41098BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1584 0x41098C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1585 0x41098C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1586 0x41098C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1587 0x41098CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1588 0x41098D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1589 0x41098D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1590 0x41098D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1591 0x41098DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1592 0x41098E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1593 0x41098E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1594 0x41098E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1595 0x41098EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1596 0x41098F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1597 0x41098F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1598 0x41098F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1599 0x41098FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1600 0x4109900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1601 0x4109904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1602 0x4109908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1603 0x410990C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1604 0x4109910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1605 0x4109914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1606 0x4109918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1607 0x410991C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1608 0x4109920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1609 0x4109924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1610 0x4109928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1611 0x410992C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1612 0x4109930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1613 0x4109934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1614 0x4109938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1615 0x410993C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1616 0x4109940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1617 0x4109944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1618 0x4109948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1619 0x410994C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1620 0x4109950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1621 0x4109954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1622 0x4109958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1623 0x410995C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1624 0x4109960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1625 0x4109964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1626 0x4109968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1627 0x410996C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1628 0x4109970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1629 0x4109974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1630 0x4109978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1631 0x410997C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1632 0x4109980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1633 0x4109984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1634 0x4109988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1635 0x410998C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1636 0x4109990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1637 0x4109994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1638 0x4109998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1639 0x410999C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1640 0x41099A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1641 0x41099A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1642 0x41099A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1643 0x41099AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1644 0x41099B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1645 0x41099B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1646 0x41099B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1647 0x41099BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1648 0x41099C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1649 0x41099C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1650 0x41099C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1651 0x41099CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1652 0x41099D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1653 0x41099D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1654 0x41099D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1655 0x41099DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1656 0x41099E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1657 0x41099E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1658 0x41099E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1659 0x41099EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1660 0x41099F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1661 0x41099F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1662 0x41099F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1663 0x41099FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1664 0x4109A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1665 0x4109A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1666 0x4109A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1667 0x4109A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1668 0x4109A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1669 0x4109A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1670 0x4109A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1671 0x4109A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1672 0x4109A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1673 0x4109A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1674 0x4109A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1675 0x4109A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1676 0x4109A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1677 0x4109A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1678 0x4109A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1679 0x4109A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1680 0x4109A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1681 0x4109A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1682 0x4109A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1683 0x4109A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1684 0x4109A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1685 0x4109A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1686 0x4109A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1687 0x4109A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1688 0x4109A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1689 0x4109A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1690 0x4109A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1691 0x4109A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1692 0x4109A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1693 0x4109A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1694 0x4109A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1695 0x4109A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1696 0x4109A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1697 0x4109A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1698 0x4109A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1699 0x4109A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1700 0x4109A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1701 0x4109A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1702 0x4109A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1703 0x4109A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1704 0x4109AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1705 0x4109AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1706 0x4109AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1707 0x4109AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1708 0x4109AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1709 0x4109AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1710 0x4109AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1711 0x4109ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1712 0x4109AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1713 0x4109AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1714 0x4109AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1715 0x4109ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1716 0x4109AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1717 0x4109AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1718 0x4109AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1719 0x4109ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1720 0x4109AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1721 0x4109AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1722 0x4109AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1723 0x4109AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1724 0x4109AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1725 0x4109AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1726 0x4109AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1727 0x4109AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1728 0x4109B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1729 0x4109B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1730 0x4109B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1731 0x4109B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1732 0x4109B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1733 0x4109B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1734 0x4109B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1735 0x4109B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1736 0x4109B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1737 0x4109B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1738 0x4109B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1739 0x4109B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1740 0x4109B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1741 0x4109B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1742 0x4109B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1743 0x4109B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1744 0x4109B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1745 0x4109B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1746 0x4109B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1747 0x4109B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1748 0x4109B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1749 0x4109B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1750 0x4109B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1751 0x4109B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1752 0x4109B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1753 0x4109B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1754 0x4109B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1755 0x4109B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1756 0x4109B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1757 0x4109B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1758 0x4109B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1759 0x4109B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1760 0x4109B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1761 0x4109B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1762 0x4109B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1763 0x4109B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1764 0x4109B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1765 0x4109B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1766 0x4109B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1767 0x4109B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1768 0x4109BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1769 0x4109BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1770 0x4109BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1771 0x4109BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1772 0x4109BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1773 0x4109BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1774 0x4109BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1775 0x4109BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1776 0x4109BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1777 0x4109BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1778 0x4109BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1779 0x4109BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1780 0x4109BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1781 0x4109BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1782 0x4109BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1783 0x4109BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1784 0x4109BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1785 0x4109BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1786 0x4109BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1787 0x4109BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1788 0x4109BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1789 0x4109BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1790 0x4109BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1791 0x4109BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1792 0x4109C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1793 0x4109C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1794 0x4109C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1795 0x4109C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1796 0x4109C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1797 0x4109C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1798 0x4109C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1799 0x4109C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1800 0x4109C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1801 0x4109C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1802 0x4109C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1803 0x4109C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1804 0x4109C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1805 0x4109C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1806 0x4109C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1807 0x4109C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1808 0x4109C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1809 0x4109C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1810 0x4109C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1811 0x4109C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1812 0x4109C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1813 0x4109C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1814 0x4109C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1815 0x4109C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1816 0x4109C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1817 0x4109C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1818 0x4109C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1819 0x4109C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1820 0x4109C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1821 0x4109C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1822 0x4109C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1823 0x4109C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1824 0x4109C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1825 0x4109C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1826 0x4109C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1827 0x4109C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1828 0x4109C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1829 0x4109C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1830 0x4109C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1831 0x4109C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1832 0x4109CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1833 0x4109CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1834 0x4109CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1835 0x4109CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1836 0x4109CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1837 0x4109CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1838 0x4109CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1839 0x4109CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1840 0x4109CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1841 0x4109CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1842 0x4109CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1843 0x4109CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1844 0x4109CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1845 0x4109CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1846 0x4109CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1847 0x4109CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1848 0x4109CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1849 0x4109CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1850 0x4109CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1851 0x4109CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1852 0x4109CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1853 0x4109CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1854 0x4109CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1855 0x4109CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1856 0x4109D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1857 0x4109D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1858 0x4109D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1859 0x4109D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1860 0x4109D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1861 0x4109D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1862 0x4109D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1863 0x4109D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1864 0x4109D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1865 0x4109D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1866 0x4109D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1867 0x4109D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1868 0x4109D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1869 0x4109D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1870 0x4109D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1871 0x4109D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1872 0x4109D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1873 0x4109D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1874 0x4109D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1875 0x4109D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1876 0x4109D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1877 0x4109D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1878 0x4109D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1879 0x4109D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1880 0x4109D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1881 0x4109D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1882 0x4109D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1883 0x4109D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1884 0x4109D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1885 0x4109D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1886 0x4109D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1887 0x4109D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1888 0x4109D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1889 0x4109D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1890 0x4109D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1891 0x4109D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1892 0x4109D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1893 0x4109D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1894 0x4109D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1895 0x4109D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1896 0x4109DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1897 0x4109DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1898 0x4109DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1899 0x4109DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1900 0x4109DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1901 0x4109DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1902 0x4109DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1903 0x4109DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1904 0x4109DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1905 0x4109DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1906 0x4109DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1907 0x4109DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1908 0x4109DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1909 0x4109DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1910 0x4109DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1911 0x4109DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1912 0x4109DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1913 0x4109DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1914 0x4109DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1915 0x4109DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1916 0x4109DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1917 0x4109DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1918 0x4109DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1919 0x4109DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1920 0x4109E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1921 0x4109E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1922 0x4109E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1923 0x4109E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1924 0x4109E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1925 0x4109E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1926 0x4109E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1927 0x4109E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1928 0x4109E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1929 0x4109E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1930 0x4109E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1931 0x4109E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1932 0x4109E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1933 0x4109E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1934 0x4109E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1935 0x4109E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1936 0x4109E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1937 0x4109E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1938 0x4109E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1939 0x4109E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1940 0x4109E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1941 0x4109E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1942 0x4109E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1943 0x4109E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1944 0x4109E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1945 0x4109E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1946 0x4109E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1947 0x4109E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1948 0x4109E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1949 0x4109E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1950 0x4109E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1951 0x4109E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1952 0x4109E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1953 0x4109E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1954 0x4109E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1955 0x4109E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1956 0x4109E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1957 0x4109E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1958 0x4109E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1959 0x4109E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1960 0x4109EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1961 0x4109EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1962 0x4109EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1963 0x4109EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1964 0x4109EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1965 0x4109EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1966 0x4109EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1967 0x4109EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1968 0x4109EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1969 0x4109EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1970 0x4109EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1971 0x4109ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1972 0x4109ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1973 0x4109ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1974 0x4109ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1975 0x4109EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1976 0x4109EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1977 0x4109EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1978 0x4109EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1979 0x4109EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1980 0x4109EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1981 0x4109EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1982 0x4109EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1983 0x4109EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1984 0x4109F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1985 0x4109F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1986 0x4109F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1987 0x4109F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1988 0x4109F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1989 0x4109F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1990 0x4109F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1991 0x4109F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1992 0x4109F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1993 0x4109F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1994 0x4109F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1995 0x4109F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1996 0x4109F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1997 0x4109F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1998 0x4109F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1999 0x4109F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2000 0x4109F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2001 0x4109F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2002 0x4109F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2003 0x4109F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2004 0x4109F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2005 0x4109F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2006 0x4109F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2007 0x4109F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2008 0x4109F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2009 0x4109F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2010 0x4109F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2011 0x4109F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2012 0x4109F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2013 0x4109F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2014 0x4109F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2015 0x4109F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2016 0x4109F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2017 0x4109F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2018 0x4109F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2019 0x4109F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2020 0x4109F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2021 0x4109F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2022 0x4109F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2023 0x4109F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2024 0x4109FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2025 0x4109FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2026 0x4109FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2027 0x4109FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2028 0x4109FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2029 0x4109FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2030 0x4109FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2031 0x4109FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2032 0x4109FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2033 0x4109FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2034 0x4109FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2035 0x4109FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2036 0x4109FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2037 0x4109FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2038 0x4109FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2039 0x4109FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2040 0x4109FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2041 0x4109FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2042 0x4109FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2043 0x4109FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2044 0x4109FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2045 0x4109FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2046 0x4109FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2047 0x4109FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x410A000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1 0x410A004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2 0x410A008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_3 0x410A00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_4 0x410A010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_5 0x410A014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_6 0x410A018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_7 0x410A01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_8 0x410A020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_9 0x410A024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_10 0x410A028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_11 0x410A02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_12 0x410A030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_13 0x410A034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_14 0x410A038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_15 0x410A03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_16 0x410A040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_17 0x410A044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_18 0x410A048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_19 0x410A04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_20 0x410A050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_21 0x410A054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_22 0x410A058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_23 0x410A05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_24 0x410A060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_25 0x410A064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_26 0x410A068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_27 0x410A06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_28 0x410A070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_29 0x410A074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_30 0x410A078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_31 0x410A07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_32 0x410A080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_33 0x410A084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_34 0x410A088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_35 0x410A08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_36 0x410A090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_37 0x410A094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_38 0x410A098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_39 0x410A09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_40 0x410A0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_41 0x410A0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_42 0x410A0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_43 0x410A0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_44 0x410A0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_45 0x410A0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_46 0x410A0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_47 0x410A0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_48 0x410A0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_49 0x410A0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_50 0x410A0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_51 0x410A0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_52 0x410A0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_53 0x410A0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_54 0x410A0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_55 0x410A0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_56 0x410A0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_57 0x410A0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_58 0x410A0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_59 0x410A0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_60 0x410A0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_61 0x410A0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_62 0x410A0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_63 0x410A0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_64 0x410A100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_65 0x410A104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_66 0x410A108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_67 0x410A10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_68 0x410A110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_69 0x410A114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_70 0x410A118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_71 0x410A11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_72 0x410A120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_73 0x410A124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_74 0x410A128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_75 0x410A12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_76 0x410A130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_77 0x410A134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_78 0x410A138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_79 0x410A13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_80 0x410A140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_81 0x410A144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_82 0x410A148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_83 0x410A14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_84 0x410A150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_85 0x410A154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_86 0x410A158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_87 0x410A15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_88 0x410A160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_89 0x410A164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_90 0x410A168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_91 0x410A16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_92 0x410A170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_93 0x410A174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_94 0x410A178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_95 0x410A17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_96 0x410A180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_97 0x410A184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_98 0x410A188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_99 0x410A18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_100 0x410A190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_101 0x410A194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_102 0x410A198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_103 0x410A19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_104 0x410A1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_105 0x410A1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_106 0x410A1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_107 0x410A1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_108 0x410A1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_109 0x410A1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_110 0x410A1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_111 0x410A1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_112 0x410A1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_113 0x410A1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_114 0x410A1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_115 0x410A1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_116 0x410A1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_117 0x410A1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_118 0x410A1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_119 0x410A1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_120 0x410A1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_121 0x410A1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_122 0x410A1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_123 0x410A1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_124 0x410A1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_125 0x410A1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_126 0x410A1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_127 0x410A1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_128 0x410A200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_129 0x410A204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_130 0x410A208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_131 0x410A20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_132 0x410A210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_133 0x410A214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_134 0x410A218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_135 0x410A21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_136 0x410A220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_137 0x410A224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_138 0x410A228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_139 0x410A22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_140 0x410A230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_141 0x410A234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_142 0x410A238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_143 0x410A23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_144 0x410A240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_145 0x410A244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_146 0x410A248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_147 0x410A24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_148 0x410A250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_149 0x410A254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_150 0x410A258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_151 0x410A25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_152 0x410A260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_153 0x410A264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_154 0x410A268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_155 0x410A26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_156 0x410A270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_157 0x410A274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_158 0x410A278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_159 0x410A27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_160 0x410A280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_161 0x410A284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_162 0x410A288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_163 0x410A28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_164 0x410A290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_165 0x410A294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_166 0x410A298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_167 0x410A29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_168 0x410A2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_169 0x410A2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_170 0x410A2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_171 0x410A2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_172 0x410A2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_173 0x410A2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_174 0x410A2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_175 0x410A2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_176 0x410A2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_177 0x410A2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_178 0x410A2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_179 0x410A2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_180 0x410A2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_181 0x410A2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_182 0x410A2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_183 0x410A2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_184 0x410A2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_185 0x410A2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_186 0x410A2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_187 0x410A2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_188 0x410A2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_189 0x410A2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_190 0x410A2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_191 0x410A2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_192 0x410A300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_193 0x410A304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_194 0x410A308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_195 0x410A30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_196 0x410A310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_197 0x410A314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_198 0x410A318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_199 0x410A31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_200 0x410A320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_201 0x410A324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_202 0x410A328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_203 0x410A32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_204 0x410A330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_205 0x410A334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_206 0x410A338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_207 0x410A33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_208 0x410A340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_209 0x410A344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_210 0x410A348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_211 0x410A34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_212 0x410A350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_213 0x410A354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_214 0x410A358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_215 0x410A35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_216 0x410A360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_217 0x410A364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_218 0x410A368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_219 0x410A36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_220 0x410A370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_221 0x410A374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_222 0x410A378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_223 0x410A37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_224 0x410A380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_225 0x410A384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_226 0x410A388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_227 0x410A38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_228 0x410A390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_229 0x410A394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_230 0x410A398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_231 0x410A39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_232 0x410A3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_233 0x410A3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_234 0x410A3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_235 0x410A3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_236 0x410A3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_237 0x410A3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_238 0x410A3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_239 0x410A3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_240 0x410A3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_241 0x410A3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_242 0x410A3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_243 0x410A3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_244 0x410A3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_245 0x410A3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_246 0x410A3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_247 0x410A3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_248 0x410A3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_249 0x410A3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_250 0x410A3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_251 0x410A3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_252 0x410A3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_253 0x410A3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_254 0x410A3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_255 0x410A3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_256 0x410A400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_257 0x410A404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_258 0x410A408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_259 0x410A40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_260 0x410A410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_261 0x410A414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_262 0x410A418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_263 0x410A41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_264 0x410A420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_265 0x410A424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_266 0x410A428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_267 0x410A42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_268 0x410A430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_269 0x410A434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_270 0x410A438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_271 0x410A43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_272 0x410A440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_273 0x410A444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_274 0x410A448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_275 0x410A44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_276 0x410A450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_277 0x410A454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_278 0x410A458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_279 0x410A45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_280 0x410A460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_281 0x410A464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_282 0x410A468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_283 0x410A46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_284 0x410A470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_285 0x410A474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_286 0x410A478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_287 0x410A47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_288 0x410A480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_289 0x410A484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_290 0x410A488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_291 0x410A48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_292 0x410A490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_293 0x410A494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_294 0x410A498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_295 0x410A49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_296 0x410A4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_297 0x410A4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_298 0x410A4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_299 0x410A4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_300 0x410A4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_301 0x410A4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_302 0x410A4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_303 0x410A4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_304 0x410A4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_305 0x410A4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_306 0x410A4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_307 0x410A4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_308 0x410A4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_309 0x410A4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_310 0x410A4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_311 0x410A4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_312 0x410A4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_313 0x410A4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_314 0x410A4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_315 0x410A4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_316 0x410A4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_317 0x410A4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_318 0x410A4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_319 0x410A4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_320 0x410A500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_321 0x410A504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_322 0x410A508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_323 0x410A50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_324 0x410A510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_325 0x410A514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_326 0x410A518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_327 0x410A51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_328 0x410A520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_329 0x410A524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_330 0x410A528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_331 0x410A52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_332 0x410A530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_333 0x410A534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_334 0x410A538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_335 0x410A53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_336 0x410A540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_337 0x410A544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_338 0x410A548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_339 0x410A54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_340 0x410A550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_341 0x410A554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_342 0x410A558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_343 0x410A55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_344 0x410A560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_345 0x410A564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_346 0x410A568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_347 0x410A56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_348 0x410A570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_349 0x410A574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_350 0x410A578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_351 0x410A57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_352 0x410A580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_353 0x410A584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_354 0x410A588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_355 0x410A58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_356 0x410A590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_357 0x410A594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_358 0x410A598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_359 0x410A59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_360 0x410A5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_361 0x410A5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_362 0x410A5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_363 0x410A5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_364 0x410A5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_365 0x410A5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_366 0x410A5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_367 0x410A5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_368 0x410A5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_369 0x410A5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_370 0x410A5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_371 0x410A5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_372 0x410A5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_373 0x410A5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_374 0x410A5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_375 0x410A5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_376 0x410A5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_377 0x410A5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_378 0x410A5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_379 0x410A5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_380 0x410A5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_381 0x410A5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_382 0x410A5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_383 0x410A5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_384 0x410A600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_385 0x410A604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_386 0x410A608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_387 0x410A60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_388 0x410A610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_389 0x410A614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_390 0x410A618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_391 0x410A61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_392 0x410A620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_393 0x410A624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_394 0x410A628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_395 0x410A62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_396 0x410A630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_397 0x410A634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_398 0x410A638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_399 0x410A63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_400 0x410A640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_401 0x410A644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_402 0x410A648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_403 0x410A64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_404 0x410A650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_405 0x410A654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_406 0x410A658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_407 0x410A65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_408 0x410A660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_409 0x410A664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_410 0x410A668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_411 0x410A66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_412 0x410A670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_413 0x410A674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_414 0x410A678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_415 0x410A67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_416 0x410A680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_417 0x410A684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_418 0x410A688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_419 0x410A68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_420 0x410A690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_421 0x410A694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_422 0x410A698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_423 0x410A69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_424 0x410A6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_425 0x410A6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_426 0x410A6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_427 0x410A6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_428 0x410A6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_429 0x410A6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_430 0x410A6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_431 0x410A6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_432 0x410A6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_433 0x410A6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_434 0x410A6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_435 0x410A6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_436 0x410A6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_437 0x410A6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_438 0x410A6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_439 0x410A6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_440 0x410A6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_441 0x410A6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_442 0x410A6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_443 0x410A6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_444 0x410A6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_445 0x410A6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_446 0x410A6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_447 0x410A6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_448 0x410A700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_449 0x410A704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_450 0x410A708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_451 0x410A70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_452 0x410A710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_453 0x410A714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_454 0x410A718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_455 0x410A71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_456 0x410A720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_457 0x410A724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_458 0x410A728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_459 0x410A72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_460 0x410A730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_461 0x410A734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_462 0x410A738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_463 0x410A73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_464 0x410A740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_465 0x410A744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_466 0x410A748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_467 0x410A74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_468 0x410A750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_469 0x410A754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_470 0x410A758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_471 0x410A75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_472 0x410A760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_473 0x410A764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_474 0x410A768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_475 0x410A76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_476 0x410A770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_477 0x410A774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_478 0x410A778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_479 0x410A77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_480 0x410A780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_481 0x410A784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_482 0x410A788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_483 0x410A78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_484 0x410A790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_485 0x410A794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_486 0x410A798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_487 0x410A79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_488 0x410A7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_489 0x410A7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_490 0x410A7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_491 0x410A7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_492 0x410A7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_493 0x410A7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_494 0x410A7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_495 0x410A7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_496 0x410A7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_497 0x410A7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_498 0x410A7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_499 0x410A7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_500 0x410A7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_501 0x410A7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_502 0x410A7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_503 0x410A7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_504 0x410A7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_505 0x410A7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_506 0x410A7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_507 0x410A7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_508 0x410A7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_509 0x410A7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_510 0x410A7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_511 0x410A7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_512 0x410A800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_513 0x410A804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_514 0x410A808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_515 0x410A80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_516 0x410A810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_517 0x410A814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_518 0x410A818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_519 0x410A81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_520 0x410A820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_521 0x410A824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_522 0x410A828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_523 0x410A82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_524 0x410A830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_525 0x410A834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_526 0x410A838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_527 0x410A83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_528 0x410A840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_529 0x410A844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_530 0x410A848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_531 0x410A84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_532 0x410A850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_533 0x410A854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_534 0x410A858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_535 0x410A85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_536 0x410A860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_537 0x410A864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_538 0x410A868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_539 0x410A86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_540 0x410A870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_541 0x410A874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_542 0x410A878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_543 0x410A87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_544 0x410A880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_545 0x410A884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_546 0x410A888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_547 0x410A88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_548 0x410A890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_549 0x410A894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_550 0x410A898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_551 0x410A89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_552 0x410A8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_553 0x410A8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_554 0x410A8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_555 0x410A8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_556 0x410A8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_557 0x410A8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_558 0x410A8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_559 0x410A8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_560 0x410A8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_561 0x410A8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_562 0x410A8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_563 0x410A8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_564 0x410A8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_565 0x410A8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_566 0x410A8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_567 0x410A8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_568 0x410A8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_569 0x410A8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_570 0x410A8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_571 0x410A8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_572 0x410A8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_573 0x410A8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_574 0x410A8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_575 0x410A8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_576 0x410A900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_577 0x410A904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_578 0x410A908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_579 0x410A90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_580 0x410A910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_581 0x410A914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_582 0x410A918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_583 0x410A91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_584 0x410A920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_585 0x410A924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_586 0x410A928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_587 0x410A92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_588 0x410A930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_589 0x410A934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_590 0x410A938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_591 0x410A93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_592 0x410A940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_593 0x410A944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_594 0x410A948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_595 0x410A94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_596 0x410A950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_597 0x410A954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_598 0x410A958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_599 0x410A95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_600 0x410A960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_601 0x410A964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_602 0x410A968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_603 0x410A96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_604 0x410A970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_605 0x410A974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_606 0x410A978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_607 0x410A97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_608 0x410A980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_609 0x410A984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_610 0x410A988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_611 0x410A98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_612 0x410A990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_613 0x410A994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_614 0x410A998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_615 0x410A99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_616 0x410A9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_617 0x410A9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_618 0x410A9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_619 0x410A9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_620 0x410A9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_621 0x410A9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_622 0x410A9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_623 0x410A9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_624 0x410A9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_625 0x410A9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_626 0x410A9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_627 0x410A9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_628 0x410A9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_629 0x410A9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_630 0x410A9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_631 0x410A9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_632 0x410A9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_633 0x410A9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_634 0x410A9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_635 0x410A9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_636 0x410A9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_637 0x410A9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_638 0x410A9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_639 0x410A9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_640 0x410AA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_641 0x410AA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_642 0x410AA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_643 0x410AA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_644 0x410AA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_645 0x410AA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_646 0x410AA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_647 0x410AA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_648 0x410AA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_649 0x410AA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_650 0x410AA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_651 0x410AA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_652 0x410AA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_653 0x410AA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_654 0x410AA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_655 0x410AA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_656 0x410AA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_657 0x410AA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_658 0x410AA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_659 0x410AA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_660 0x410AA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_661 0x410AA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_662 0x410AA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_663 0x410AA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_664 0x410AA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_665 0x410AA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_666 0x410AA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_667 0x410AA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_668 0x410AA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_669 0x410AA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_670 0x410AA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_671 0x410AA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_672 0x410AA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_673 0x410AA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_674 0x410AA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_675 0x410AA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_676 0x410AA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_677 0x410AA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_678 0x410AA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_679 0x410AA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_680 0x410AAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_681 0x410AAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_682 0x410AAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_683 0x410AAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_684 0x410AAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_685 0x410AAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_686 0x410AAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_687 0x410AABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_688 0x410AAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_689 0x410AAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_690 0x410AAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_691 0x410AACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_692 0x410AAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_693 0x410AAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_694 0x410AAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_695 0x410AADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_696 0x410AAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_697 0x410AAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_698 0x410AAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_699 0x410AAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_700 0x410AAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_701 0x410AAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_702 0x410AAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_703 0x410AAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_704 0x410AB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_705 0x410AB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_706 0x410AB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_707 0x410AB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_708 0x410AB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_709 0x410AB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_710 0x410AB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_711 0x410AB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_712 0x410AB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_713 0x410AB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_714 0x410AB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_715 0x410AB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_716 0x410AB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_717 0x410AB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_718 0x410AB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_719 0x410AB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_720 0x410AB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_721 0x410AB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_722 0x410AB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_723 0x410AB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_724 0x410AB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_725 0x410AB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_726 0x410AB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_727 0x410AB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_728 0x410AB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_729 0x410AB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_730 0x410AB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_731 0x410AB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_732 0x410AB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_733 0x410AB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_734 0x410AB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_735 0x410AB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_736 0x410AB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_737 0x410AB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_738 0x410AB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_739 0x410AB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_740 0x410AB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_741 0x410AB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_742 0x410AB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_743 0x410AB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_744 0x410ABA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_745 0x410ABA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_746 0x410ABA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_747 0x410ABAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_748 0x410ABB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_749 0x410ABB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_750 0x410ABB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_751 0x410ABBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_752 0x410ABC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_753 0x410ABC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_754 0x410ABC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_755 0x410ABCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_756 0x410ABD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_757 0x410ABD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_758 0x410ABD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_759 0x410ABDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_760 0x410ABE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_761 0x410ABE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_762 0x410ABE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_763 0x410ABEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_764 0x410ABF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_765 0x410ABF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_766 0x410ABF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_767 0x410ABFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_768 0x410AC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_769 0x410AC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_770 0x410AC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_771 0x410AC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_772 0x410AC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_773 0x410AC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_774 0x410AC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_775 0x410AC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_776 0x410AC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_777 0x410AC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_778 0x410AC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_779 0x410AC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_780 0x410AC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_781 0x410AC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_782 0x410AC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_783 0x410AC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_784 0x410AC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_785 0x410AC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_786 0x410AC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_787 0x410AC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_788 0x410AC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_789 0x410AC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_790 0x410AC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_791 0x410AC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_792 0x410AC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_793 0x410AC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_794 0x410AC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_795 0x410AC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_796 0x410AC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_797 0x410AC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_798 0x410AC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_799 0x410AC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_800 0x410AC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_801 0x410AC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_802 0x410AC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_803 0x410AC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_804 0x410AC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_805 0x410AC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_806 0x410AC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_807 0x410AC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_808 0x410ACA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_809 0x410ACA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_810 0x410ACA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_811 0x410ACAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_812 0x410ACB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_813 0x410ACB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_814 0x410ACB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_815 0x410ACBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_816 0x410ACC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_817 0x410ACC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_818 0x410ACC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_819 0x410ACCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_820 0x410ACD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_821 0x410ACD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_822 0x410ACD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_823 0x410ACDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_824 0x410ACE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_825 0x410ACE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_826 0x410ACE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_827 0x410ACEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_828 0x410ACF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_829 0x410ACF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_830 0x410ACF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_831 0x410ACFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_832 0x410AD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_833 0x410AD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_834 0x410AD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_835 0x410AD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_836 0x410AD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_837 0x410AD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_838 0x410AD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_839 0x410AD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_840 0x410AD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_841 0x410AD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_842 0x410AD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_843 0x410AD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_844 0x410AD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_845 0x410AD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_846 0x410AD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_847 0x410AD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_848 0x410AD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_849 0x410AD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_850 0x410AD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_851 0x410AD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_852 0x410AD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_853 0x410AD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_854 0x410AD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_855 0x410AD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_856 0x410AD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_857 0x410AD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_858 0x410AD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_859 0x410AD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_860 0x410AD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_861 0x410AD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_862 0x410AD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_863 0x410AD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_864 0x410AD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_865 0x410AD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_866 0x410AD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_867 0x410AD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_868 0x410AD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_869 0x410AD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_870 0x410AD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_871 0x410AD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_872 0x410ADA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_873 0x410ADA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_874 0x410ADA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_875 0x410ADAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_876 0x410ADB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_877 0x410ADB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_878 0x410ADB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_879 0x410ADBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_880 0x410ADC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_881 0x410ADC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_882 0x410ADC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_883 0x410ADCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_884 0x410ADD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_885 0x410ADD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_886 0x410ADD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_887 0x410ADDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_888 0x410ADE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_889 0x410ADE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_890 0x410ADE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_891 0x410ADEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_892 0x410ADF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_893 0x410ADF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_894 0x410ADF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_895 0x410ADFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_896 0x410AE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_897 0x410AE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_898 0x410AE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_899 0x410AE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_900 0x410AE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_901 0x410AE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_902 0x410AE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_903 0x410AE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_904 0x410AE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_905 0x410AE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_906 0x410AE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_907 0x410AE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_908 0x410AE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_909 0x410AE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_910 0x410AE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_911 0x410AE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_912 0x410AE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_913 0x410AE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_914 0x410AE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_915 0x410AE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_916 0x410AE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_917 0x410AE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_918 0x410AE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_919 0x410AE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_920 0x410AE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_921 0x410AE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_922 0x410AE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_923 0x410AE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_924 0x410AE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_925 0x410AE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_926 0x410AE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_927 0x410AE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_928 0x410AE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_929 0x410AE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_930 0x410AE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_931 0x410AE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_932 0x410AE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_933 0x410AE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_934 0x410AE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_935 0x410AE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_936 0x410AEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_937 0x410AEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_938 0x410AEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_939 0x410AEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_940 0x410AEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_941 0x410AEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_942 0x410AEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_943 0x410AEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_944 0x410AEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_945 0x410AEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_946 0x410AEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_947 0x410AECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_948 0x410AED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_949 0x410AED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_950 0x410AED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_951 0x410AEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_952 0x410AEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_953 0x410AEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_954 0x410AEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_955 0x410AEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_956 0x410AEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_957 0x410AEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_958 0x410AEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_959 0x410AEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_960 0x410AF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_961 0x410AF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_962 0x410AF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_963 0x410AF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_964 0x410AF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_965 0x410AF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_966 0x410AF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_967 0x410AF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_968 0x410AF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_969 0x410AF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_970 0x410AF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_971 0x410AF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_972 0x410AF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_973 0x410AF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_974 0x410AF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_975 0x410AF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_976 0x410AF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_977 0x410AF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_978 0x410AF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_979 0x410AF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_980 0x410AF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_981 0x410AF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_982 0x410AF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_983 0x410AF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_984 0x410AF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_985 0x410AF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_986 0x410AF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_987 0x410AF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_988 0x410AF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_989 0x410AF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_990 0x410AF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_991 0x410AF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_992 0x410AF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_993 0x410AF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_994 0x410AF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_995 0x410AF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_996 0x410AF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_997 0x410AF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_998 0x410AF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_999 0x410AF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1000 0x410AFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1001 0x410AFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1002 0x410AFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1003 0x410AFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1004 0x410AFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1005 0x410AFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1006 0x410AFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1007 0x410AFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1008 0x410AFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1009 0x410AFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1010 0x410AFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1011 0x410AFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1012 0x410AFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1013 0x410AFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1014 0x410AFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1015 0x410AFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1016 0x410AFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1017 0x410AFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1018 0x410AFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1019 0x410AFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1020 0x410AFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1021 0x410AFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1022 0x410AFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1023 0x410AFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1024 0x410B000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1025 0x410B004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1026 0x410B008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1027 0x410B00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1028 0x410B010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1029 0x410B014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1030 0x410B018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1031 0x410B01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1032 0x410B020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1033 0x410B024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1034 0x410B028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1035 0x410B02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1036 0x410B030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1037 0x410B034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1038 0x410B038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1039 0x410B03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1040 0x410B040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1041 0x410B044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1042 0x410B048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1043 0x410B04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1044 0x410B050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1045 0x410B054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1046 0x410B058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1047 0x410B05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1048 0x410B060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1049 0x410B064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1050 0x410B068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1051 0x410B06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1052 0x410B070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1053 0x410B074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1054 0x410B078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1055 0x410B07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1056 0x410B080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1057 0x410B084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1058 0x410B088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1059 0x410B08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1060 0x410B090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1061 0x410B094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1062 0x410B098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1063 0x410B09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1064 0x410B0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1065 0x410B0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1066 0x410B0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1067 0x410B0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1068 0x410B0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1069 0x410B0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1070 0x410B0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1071 0x410B0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1072 0x410B0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1073 0x410B0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1074 0x410B0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1075 0x410B0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1076 0x410B0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1077 0x410B0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1078 0x410B0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1079 0x410B0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1080 0x410B0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1081 0x410B0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1082 0x410B0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1083 0x410B0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1084 0x410B0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1085 0x410B0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1086 0x410B0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1087 0x410B0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1088 0x410B100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1089 0x410B104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1090 0x410B108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1091 0x410B10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1092 0x410B110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1093 0x410B114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1094 0x410B118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1095 0x410B11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1096 0x410B120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1097 0x410B124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1098 0x410B128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1099 0x410B12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1100 0x410B130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1101 0x410B134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1102 0x410B138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1103 0x410B13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1104 0x410B140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1105 0x410B144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1106 0x410B148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1107 0x410B14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1108 0x410B150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1109 0x410B154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1110 0x410B158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1111 0x410B15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1112 0x410B160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1113 0x410B164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1114 0x410B168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1115 0x410B16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1116 0x410B170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1117 0x410B174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1118 0x410B178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1119 0x410B17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1120 0x410B180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1121 0x410B184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1122 0x410B188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1123 0x410B18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1124 0x410B190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1125 0x410B194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1126 0x410B198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1127 0x410B19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1128 0x410B1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1129 0x410B1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1130 0x410B1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1131 0x410B1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1132 0x410B1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1133 0x410B1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1134 0x410B1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1135 0x410B1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1136 0x410B1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1137 0x410B1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1138 0x410B1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1139 0x410B1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1140 0x410B1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1141 0x410B1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1142 0x410B1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1143 0x410B1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1144 0x410B1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1145 0x410B1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1146 0x410B1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1147 0x410B1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1148 0x410B1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1149 0x410B1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1150 0x410B1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1151 0x410B1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1152 0x410B200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1153 0x410B204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1154 0x410B208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1155 0x410B20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1156 0x410B210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1157 0x410B214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1158 0x410B218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1159 0x410B21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1160 0x410B220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1161 0x410B224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1162 0x410B228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1163 0x410B22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1164 0x410B230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1165 0x410B234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1166 0x410B238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1167 0x410B23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1168 0x410B240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1169 0x410B244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1170 0x410B248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1171 0x410B24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1172 0x410B250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1173 0x410B254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1174 0x410B258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1175 0x410B25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1176 0x410B260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1177 0x410B264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1178 0x410B268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1179 0x410B26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1180 0x410B270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1181 0x410B274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1182 0x410B278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1183 0x410B27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1184 0x410B280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1185 0x410B284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1186 0x410B288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1187 0x410B28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1188 0x410B290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1189 0x410B294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1190 0x410B298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1191 0x410B29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1192 0x410B2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1193 0x410B2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1194 0x410B2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1195 0x410B2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1196 0x410B2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1197 0x410B2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1198 0x410B2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1199 0x410B2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1200 0x410B2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1201 0x410B2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1202 0x410B2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1203 0x410B2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1204 0x410B2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1205 0x410B2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1206 0x410B2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1207 0x410B2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1208 0x410B2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1209 0x410B2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1210 0x410B2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1211 0x410B2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1212 0x410B2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1213 0x410B2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1214 0x410B2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1215 0x410B2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1216 0x410B300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1217 0x410B304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1218 0x410B308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1219 0x410B30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1220 0x410B310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1221 0x410B314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1222 0x410B318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1223 0x410B31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1224 0x410B320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1225 0x410B324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1226 0x410B328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1227 0x410B32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1228 0x410B330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1229 0x410B334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1230 0x410B338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1231 0x410B33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1232 0x410B340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1233 0x410B344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1234 0x410B348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1235 0x410B34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1236 0x410B350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1237 0x410B354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1238 0x410B358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1239 0x410B35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1240 0x410B360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1241 0x410B364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1242 0x410B368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1243 0x410B36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1244 0x410B370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1245 0x410B374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1246 0x410B378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1247 0x410B37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1248 0x410B380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1249 0x410B384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1250 0x410B388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1251 0x410B38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1252 0x410B390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1253 0x410B394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1254 0x410B398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1255 0x410B39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1256 0x410B3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1257 0x410B3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1258 0x410B3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1259 0x410B3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1260 0x410B3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1261 0x410B3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1262 0x410B3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1263 0x410B3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1264 0x410B3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1265 0x410B3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1266 0x410B3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1267 0x410B3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1268 0x410B3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1269 0x410B3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1270 0x410B3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1271 0x410B3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1272 0x410B3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1273 0x410B3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1274 0x410B3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1275 0x410B3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1276 0x410B3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1277 0x410B3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1278 0x410B3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1279 0x410B3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1280 0x410B400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1281 0x410B404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1282 0x410B408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1283 0x410B40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1284 0x410B410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1285 0x410B414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1286 0x410B418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1287 0x410B41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1288 0x410B420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1289 0x410B424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1290 0x410B428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1291 0x410B42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1292 0x410B430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1293 0x410B434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1294 0x410B438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1295 0x410B43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1296 0x410B440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1297 0x410B444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1298 0x410B448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1299 0x410B44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1300 0x410B450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1301 0x410B454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1302 0x410B458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1303 0x410B45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1304 0x410B460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1305 0x410B464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1306 0x410B468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1307 0x410B46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1308 0x410B470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1309 0x410B474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1310 0x410B478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1311 0x410B47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1312 0x410B480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1313 0x410B484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1314 0x410B488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1315 0x410B48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1316 0x410B490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1317 0x410B494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1318 0x410B498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1319 0x410B49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1320 0x410B4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1321 0x410B4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1322 0x410B4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1323 0x410B4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1324 0x410B4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1325 0x410B4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1326 0x410B4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1327 0x410B4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1328 0x410B4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1329 0x410B4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1330 0x410B4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1331 0x410B4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1332 0x410B4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1333 0x410B4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1334 0x410B4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1335 0x410B4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1336 0x410B4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1337 0x410B4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1338 0x410B4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1339 0x410B4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1340 0x410B4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1341 0x410B4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1342 0x410B4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1343 0x410B4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1344 0x410B500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1345 0x410B504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1346 0x410B508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1347 0x410B50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1348 0x410B510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1349 0x410B514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1350 0x410B518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1351 0x410B51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1352 0x410B520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1353 0x410B524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1354 0x410B528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1355 0x410B52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1356 0x410B530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1357 0x410B534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1358 0x410B538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1359 0x410B53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1360 0x410B540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1361 0x410B544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1362 0x410B548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1363 0x410B54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1364 0x410B550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1365 0x410B554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1366 0x410B558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1367 0x410B55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1368 0x410B560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1369 0x410B564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1370 0x410B568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1371 0x410B56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1372 0x410B570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1373 0x410B574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1374 0x410B578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1375 0x410B57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1376 0x410B580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1377 0x410B584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1378 0x410B588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1379 0x410B58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1380 0x410B590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1381 0x410B594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1382 0x410B598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1383 0x410B59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1384 0x410B5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1385 0x410B5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1386 0x410B5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1387 0x410B5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1388 0x410B5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1389 0x410B5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1390 0x410B5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1391 0x410B5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1392 0x410B5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1393 0x410B5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1394 0x410B5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1395 0x410B5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1396 0x410B5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1397 0x410B5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1398 0x410B5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1399 0x410B5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1400 0x410B5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1401 0x410B5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1402 0x410B5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1403 0x410B5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1404 0x410B5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1405 0x410B5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1406 0x410B5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1407 0x410B5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1408 0x410B600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1409 0x410B604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1410 0x410B608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1411 0x410B60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1412 0x410B610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1413 0x410B614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1414 0x410B618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1415 0x410B61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1416 0x410B620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1417 0x410B624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1418 0x410B628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1419 0x410B62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1420 0x410B630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1421 0x410B634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1422 0x410B638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1423 0x410B63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1424 0x410B640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1425 0x410B644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1426 0x410B648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1427 0x410B64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1428 0x410B650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1429 0x410B654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1430 0x410B658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1431 0x410B65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1432 0x410B660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1433 0x410B664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1434 0x410B668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1435 0x410B66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1436 0x410B670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1437 0x410B674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1438 0x410B678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1439 0x410B67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1440 0x410B680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1441 0x410B684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1442 0x410B688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1443 0x410B68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1444 0x410B690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1445 0x410B694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1446 0x410B698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1447 0x410B69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1448 0x410B6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1449 0x410B6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1450 0x410B6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1451 0x410B6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1452 0x410B6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1453 0x410B6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1454 0x410B6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1455 0x410B6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1456 0x410B6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1457 0x410B6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1458 0x410B6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1459 0x410B6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1460 0x410B6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1461 0x410B6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1462 0x410B6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1463 0x410B6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1464 0x410B6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1465 0x410B6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1466 0x410B6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1467 0x410B6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1468 0x410B6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1469 0x410B6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1470 0x410B6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1471 0x410B6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1472 0x410B700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1473 0x410B704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1474 0x410B708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1475 0x410B70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1476 0x410B710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1477 0x410B714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1478 0x410B718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1479 0x410B71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1480 0x410B720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1481 0x410B724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1482 0x410B728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1483 0x410B72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1484 0x410B730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1485 0x410B734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1486 0x410B738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1487 0x410B73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1488 0x410B740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1489 0x410B744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1490 0x410B748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1491 0x410B74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1492 0x410B750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1493 0x410B754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1494 0x410B758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1495 0x410B75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1496 0x410B760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1497 0x410B764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1498 0x410B768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1499 0x410B76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1500 0x410B770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1501 0x410B774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1502 0x410B778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1503 0x410B77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1504 0x410B780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1505 0x410B784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1506 0x410B788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1507 0x410B78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1508 0x410B790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1509 0x410B794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1510 0x410B798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1511 0x410B79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1512 0x410B7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1513 0x410B7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1514 0x410B7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1515 0x410B7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1516 0x410B7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1517 0x410B7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1518 0x410B7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1519 0x410B7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1520 0x410B7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1521 0x410B7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1522 0x410B7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1523 0x410B7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1524 0x410B7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1525 0x410B7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1526 0x410B7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1527 0x410B7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1528 0x410B7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1529 0x410B7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1530 0x410B7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1531 0x410B7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1532 0x410B7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1533 0x410B7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1534 0x410B7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1535 0x410B7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1536 0x410B800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1537 0x410B804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1538 0x410B808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1539 0x410B80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1540 0x410B810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1541 0x410B814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1542 0x410B818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1543 0x410B81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1544 0x410B820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1545 0x410B824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1546 0x410B828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1547 0x410B82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1548 0x410B830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1549 0x410B834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1550 0x410B838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1551 0x410B83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1552 0x410B840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1553 0x410B844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1554 0x410B848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1555 0x410B84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1556 0x410B850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1557 0x410B854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1558 0x410B858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1559 0x410B85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1560 0x410B860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1561 0x410B864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1562 0x410B868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1563 0x410B86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1564 0x410B870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1565 0x410B874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1566 0x410B878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1567 0x410B87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1568 0x410B880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1569 0x410B884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1570 0x410B888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1571 0x410B88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1572 0x410B890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1573 0x410B894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1574 0x410B898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1575 0x410B89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1576 0x410B8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1577 0x410B8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1578 0x410B8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1579 0x410B8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1580 0x410B8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1581 0x410B8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1582 0x410B8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1583 0x410B8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1584 0x410B8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1585 0x410B8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1586 0x410B8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1587 0x410B8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1588 0x410B8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1589 0x410B8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1590 0x410B8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1591 0x410B8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1592 0x410B8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1593 0x410B8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1594 0x410B8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1595 0x410B8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1596 0x410B8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1597 0x410B8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1598 0x410B8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1599 0x410B8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1600 0x410B900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1601 0x410B904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1602 0x410B908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1603 0x410B90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1604 0x410B910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1605 0x410B914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1606 0x410B918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1607 0x410B91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1608 0x410B920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1609 0x410B924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1610 0x410B928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1611 0x410B92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1612 0x410B930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1613 0x410B934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1614 0x410B938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1615 0x410B93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1616 0x410B940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1617 0x410B944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1618 0x410B948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1619 0x410B94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1620 0x410B950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1621 0x410B954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1622 0x410B958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1623 0x410B95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1624 0x410B960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1625 0x410B964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1626 0x410B968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1627 0x410B96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1628 0x410B970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1629 0x410B974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1630 0x410B978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1631 0x410B97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1632 0x410B980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1633 0x410B984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1634 0x410B988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1635 0x410B98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1636 0x410B990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1637 0x410B994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1638 0x410B998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1639 0x410B99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1640 0x410B9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1641 0x410B9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1642 0x410B9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1643 0x410B9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1644 0x410B9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1645 0x410B9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1646 0x410B9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1647 0x410B9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1648 0x410B9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1649 0x410B9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1650 0x410B9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1651 0x410B9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1652 0x410B9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1653 0x410B9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1654 0x410B9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1655 0x410B9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1656 0x410B9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1657 0x410B9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1658 0x410B9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1659 0x410B9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1660 0x410B9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1661 0x410B9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1662 0x410B9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1663 0x410B9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1664 0x410BA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1665 0x410BA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1666 0x410BA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1667 0x410BA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1668 0x410BA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1669 0x410BA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1670 0x410BA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1671 0x410BA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1672 0x410BA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1673 0x410BA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1674 0x410BA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1675 0x410BA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1676 0x410BA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1677 0x410BA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1678 0x410BA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1679 0x410BA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1680 0x410BA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1681 0x410BA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1682 0x410BA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1683 0x410BA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1684 0x410BA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1685 0x410BA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1686 0x410BA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1687 0x410BA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1688 0x410BA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1689 0x410BA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1690 0x410BA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1691 0x410BA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1692 0x410BA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1693 0x410BA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1694 0x410BA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1695 0x410BA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1696 0x410BA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1697 0x410BA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1698 0x410BA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1699 0x410BA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1700 0x410BA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1701 0x410BA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1702 0x410BA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1703 0x410BA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1704 0x410BAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1705 0x410BAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1706 0x410BAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1707 0x410BAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1708 0x410BAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1709 0x410BAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1710 0x410BAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1711 0x410BABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1712 0x410BAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1713 0x410BAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1714 0x410BAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1715 0x410BACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1716 0x410BAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1717 0x410BAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1718 0x410BAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1719 0x410BADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1720 0x410BAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1721 0x410BAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1722 0x410BAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1723 0x410BAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1724 0x410BAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1725 0x410BAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1726 0x410BAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1727 0x410BAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1728 0x410BB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1729 0x410BB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1730 0x410BB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1731 0x410BB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1732 0x410BB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1733 0x410BB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1734 0x410BB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1735 0x410BB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1736 0x410BB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1737 0x410BB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1738 0x410BB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1739 0x410BB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1740 0x410BB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1741 0x410BB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1742 0x410BB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1743 0x410BB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1744 0x410BB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1745 0x410BB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1746 0x410BB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1747 0x410BB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1748 0x410BB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1749 0x410BB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1750 0x410BB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1751 0x410BB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1752 0x410BB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1753 0x410BB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1754 0x410BB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1755 0x410BB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1756 0x410BB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1757 0x410BB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1758 0x410BB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1759 0x410BB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1760 0x410BB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1761 0x410BB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1762 0x410BB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1763 0x410BB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1764 0x410BB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1765 0x410BB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1766 0x410BB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1767 0x410BB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1768 0x410BBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1769 0x410BBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1770 0x410BBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1771 0x410BBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1772 0x410BBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1773 0x410BBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1774 0x410BBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1775 0x410BBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1776 0x410BBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1777 0x410BBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1778 0x410BBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1779 0x410BBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1780 0x410BBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1781 0x410BBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1782 0x410BBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1783 0x410BBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1784 0x410BBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1785 0x410BBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1786 0x410BBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1787 0x410BBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1788 0x410BBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1789 0x410BBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1790 0x410BBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1791 0x410BBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1792 0x410BC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1793 0x410BC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1794 0x410BC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1795 0x410BC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1796 0x410BC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1797 0x410BC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1798 0x410BC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1799 0x410BC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1800 0x410BC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1801 0x410BC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1802 0x410BC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1803 0x410BC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1804 0x410BC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1805 0x410BC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1806 0x410BC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1807 0x410BC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1808 0x410BC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1809 0x410BC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1810 0x410BC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1811 0x410BC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1812 0x410BC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1813 0x410BC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1814 0x410BC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1815 0x410BC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1816 0x410BC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1817 0x410BC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1818 0x410BC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1819 0x410BC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1820 0x410BC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1821 0x410BC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1822 0x410BC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1823 0x410BC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1824 0x410BC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1825 0x410BC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1826 0x410BC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1827 0x410BC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1828 0x410BC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1829 0x410BC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1830 0x410BC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1831 0x410BC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1832 0x410BCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1833 0x410BCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1834 0x410BCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1835 0x410BCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1836 0x410BCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1837 0x410BCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1838 0x410BCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1839 0x410BCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1840 0x410BCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1841 0x410BCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1842 0x410BCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1843 0x410BCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1844 0x410BCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1845 0x410BCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1846 0x410BCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1847 0x410BCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1848 0x410BCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1849 0x410BCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1850 0x410BCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1851 0x410BCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1852 0x410BCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1853 0x410BCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1854 0x410BCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1855 0x410BCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1856 0x410BD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1857 0x410BD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1858 0x410BD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1859 0x410BD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1860 0x410BD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1861 0x410BD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1862 0x410BD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1863 0x410BD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1864 0x410BD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1865 0x410BD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1866 0x410BD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1867 0x410BD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1868 0x410BD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1869 0x410BD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1870 0x410BD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1871 0x410BD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1872 0x410BD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1873 0x410BD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1874 0x410BD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1875 0x410BD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1876 0x410BD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1877 0x410BD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1878 0x410BD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1879 0x410BD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1880 0x410BD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1881 0x410BD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1882 0x410BD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1883 0x410BD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1884 0x410BD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1885 0x410BD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1886 0x410BD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1887 0x410BD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1888 0x410BD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1889 0x410BD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1890 0x410BD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1891 0x410BD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1892 0x410BD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1893 0x410BD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1894 0x410BD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1895 0x410BD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1896 0x410BDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1897 0x410BDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1898 0x410BDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1899 0x410BDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1900 0x410BDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1901 0x410BDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1902 0x410BDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1903 0x410BDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1904 0x410BDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1905 0x410BDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1906 0x410BDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1907 0x410BDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1908 0x410BDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1909 0x410BDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1910 0x410BDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1911 0x410BDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1912 0x410BDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1913 0x410BDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1914 0x410BDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1915 0x410BDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1916 0x410BDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1917 0x410BDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1918 0x410BDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1919 0x410BDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1920 0x410BE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1921 0x410BE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1922 0x410BE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1923 0x410BE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1924 0x410BE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1925 0x410BE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1926 0x410BE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1927 0x410BE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1928 0x410BE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1929 0x410BE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1930 0x410BE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1931 0x410BE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1932 0x410BE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1933 0x410BE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1934 0x410BE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1935 0x410BE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1936 0x410BE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1937 0x410BE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1938 0x410BE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1939 0x410BE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1940 0x410BE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1941 0x410BE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1942 0x410BE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1943 0x410BE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1944 0x410BE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1945 0x410BE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1946 0x410BE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1947 0x410BE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1948 0x410BE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1949 0x410BE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1950 0x410BE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1951 0x410BE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1952 0x410BE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1953 0x410BE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1954 0x410BE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1955 0x410BE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1956 0x410BE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1957 0x410BE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1958 0x410BE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1959 0x410BE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1960 0x410BEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1961 0x410BEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1962 0x410BEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1963 0x410BEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1964 0x410BEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1965 0x410BEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1966 0x410BEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1967 0x410BEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1968 0x410BEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1969 0x410BEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1970 0x410BEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1971 0x410BECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1972 0x410BED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1973 0x410BED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1974 0x410BED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1975 0x410BEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1976 0x410BEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1977 0x410BEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1978 0x410BEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1979 0x410BEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1980 0x410BEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1981 0x410BEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1982 0x410BEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1983 0x410BEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1984 0x410BF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1985 0x410BF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1986 0x410BF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1987 0x410BF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1988 0x410BF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1989 0x410BF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1990 0x410BF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1991 0x410BF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1992 0x410BF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1993 0x410BF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1994 0x410BF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1995 0x410BF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1996 0x410BF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1997 0x410BF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1998 0x410BF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1999 0x410BF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2000 0x410BF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2001 0x410BF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2002 0x410BF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2003 0x410BF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2004 0x410BF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2005 0x410BF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2006 0x410BF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2007 0x410BF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2008 0x410BF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2009 0x410BF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2010 0x410BF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2011 0x410BF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2012 0x410BF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2013 0x410BF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2014 0x410BF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2015 0x410BF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2016 0x410BF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2017 0x410BF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2018 0x410BF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2019 0x410BF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2020 0x410BF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2021 0x410BF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2022 0x410BF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2023 0x410BF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2024 0x410BFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2025 0x410BFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2026 0x410BFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2027 0x410BFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2028 0x410BFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2029 0x410BFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2030 0x410BFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2031 0x410BFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2032 0x410BFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2033 0x410BFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2034 0x410BFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2035 0x410BFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2036 0x410BFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2037 0x410BFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2038 0x410BFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2039 0x410BFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2040 0x410BFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2041 0x410BFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2042 0x410BFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2043 0x410BFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2044 0x410BFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2045 0x410BFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2046 0x410BFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2047 0x410BFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x410C000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1 0x410C004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2 0x410C008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_3 0x410C00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_4 0x410C010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_5 0x410C014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_6 0x410C018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_7 0x410C01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_8 0x410C020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_9 0x410C024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_10 0x410C028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_11 0x410C02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_12 0x410C030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_13 0x410C034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_14 0x410C038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_15 0x410C03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_16 0x410C040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_17 0x410C044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_18 0x410C048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_19 0x410C04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_20 0x410C050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_21 0x410C054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_22 0x410C058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_23 0x410C05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_24 0x410C060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_25 0x410C064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_26 0x410C068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_27 0x410C06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_28 0x410C070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_29 0x410C074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_30 0x410C078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_31 0x410C07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_32 0x410C080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_33 0x410C084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_34 0x410C088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_35 0x410C08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_36 0x410C090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_37 0x410C094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_38 0x410C098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_39 0x410C09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_40 0x410C0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_41 0x410C0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_42 0x410C0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_43 0x410C0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_44 0x410C0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_45 0x410C0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_46 0x410C0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_47 0x410C0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_48 0x410C0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_49 0x410C0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_50 0x410C0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_51 0x410C0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_52 0x410C0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_53 0x410C0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_54 0x410C0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_55 0x410C0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_56 0x410C0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_57 0x410C0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_58 0x410C0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_59 0x410C0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_60 0x410C0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_61 0x410C0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_62 0x410C0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_63 0x410C0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_64 0x410C100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_65 0x410C104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_66 0x410C108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_67 0x410C10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_68 0x410C110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_69 0x410C114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_70 0x410C118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_71 0x410C11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_72 0x410C120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_73 0x410C124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_74 0x410C128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_75 0x410C12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_76 0x410C130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_77 0x410C134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_78 0x410C138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_79 0x410C13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_80 0x410C140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_81 0x410C144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_82 0x410C148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_83 0x410C14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_84 0x410C150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_85 0x410C154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_86 0x410C158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_87 0x410C15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_88 0x410C160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_89 0x410C164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_90 0x410C168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_91 0x410C16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_92 0x410C170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_93 0x410C174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_94 0x410C178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_95 0x410C17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_96 0x410C180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_97 0x410C184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_98 0x410C188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_99 0x410C18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_100 0x410C190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_101 0x410C194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_102 0x410C198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_103 0x410C19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_104 0x410C1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_105 0x410C1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_106 0x410C1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_107 0x410C1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_108 0x410C1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_109 0x410C1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_110 0x410C1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_111 0x410C1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_112 0x410C1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_113 0x410C1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_114 0x410C1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_115 0x410C1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_116 0x410C1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_117 0x410C1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_118 0x410C1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_119 0x410C1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_120 0x410C1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_121 0x410C1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_122 0x410C1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_123 0x410C1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_124 0x410C1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_125 0x410C1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_126 0x410C1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_127 0x410C1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_128 0x410C200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_129 0x410C204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_130 0x410C208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_131 0x410C20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_132 0x410C210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_133 0x410C214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_134 0x410C218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_135 0x410C21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_136 0x410C220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_137 0x410C224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_138 0x410C228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_139 0x410C22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_140 0x410C230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_141 0x410C234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_142 0x410C238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_143 0x410C23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_144 0x410C240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_145 0x410C244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_146 0x410C248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_147 0x410C24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_148 0x410C250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_149 0x410C254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_150 0x410C258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_151 0x410C25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_152 0x410C260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_153 0x410C264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_154 0x410C268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_155 0x410C26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_156 0x410C270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_157 0x410C274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_158 0x410C278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_159 0x410C27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_160 0x410C280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_161 0x410C284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_162 0x410C288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_163 0x410C28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_164 0x410C290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_165 0x410C294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_166 0x410C298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_167 0x410C29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_168 0x410C2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_169 0x410C2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_170 0x410C2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_171 0x410C2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_172 0x410C2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_173 0x410C2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_174 0x410C2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_175 0x410C2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_176 0x410C2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_177 0x410C2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_178 0x410C2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_179 0x410C2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_180 0x410C2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_181 0x410C2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_182 0x410C2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_183 0x410C2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_184 0x410C2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_185 0x410C2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_186 0x410C2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_187 0x410C2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_188 0x410C2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_189 0x410C2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_190 0x410C2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_191 0x410C2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_192 0x410C300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_193 0x410C304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_194 0x410C308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_195 0x410C30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_196 0x410C310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_197 0x410C314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_198 0x410C318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_199 0x410C31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_200 0x410C320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_201 0x410C324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_202 0x410C328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_203 0x410C32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_204 0x410C330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_205 0x410C334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_206 0x410C338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_207 0x410C33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_208 0x410C340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_209 0x410C344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_210 0x410C348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_211 0x410C34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_212 0x410C350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_213 0x410C354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_214 0x410C358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_215 0x410C35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_216 0x410C360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_217 0x410C364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_218 0x410C368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_219 0x410C36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_220 0x410C370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_221 0x410C374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_222 0x410C378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_223 0x410C37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_224 0x410C380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_225 0x410C384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_226 0x410C388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_227 0x410C38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_228 0x410C390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_229 0x410C394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_230 0x410C398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_231 0x410C39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_232 0x410C3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_233 0x410C3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_234 0x410C3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_235 0x410C3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_236 0x410C3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_237 0x410C3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_238 0x410C3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_239 0x410C3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_240 0x410C3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_241 0x410C3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_242 0x410C3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_243 0x410C3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_244 0x410C3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_245 0x410C3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_246 0x410C3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_247 0x410C3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_248 0x410C3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_249 0x410C3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_250 0x410C3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_251 0x410C3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_252 0x410C3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_253 0x410C3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_254 0x410C3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_255 0x410C3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_256 0x410C400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_257 0x410C404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_258 0x410C408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_259 0x410C40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_260 0x410C410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_261 0x410C414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_262 0x410C418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_263 0x410C41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_264 0x410C420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_265 0x410C424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_266 0x410C428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_267 0x410C42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_268 0x410C430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_269 0x410C434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_270 0x410C438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_271 0x410C43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_272 0x410C440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_273 0x410C444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_274 0x410C448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_275 0x410C44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_276 0x410C450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_277 0x410C454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_278 0x410C458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_279 0x410C45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_280 0x410C460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_281 0x410C464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_282 0x410C468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_283 0x410C46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_284 0x410C470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_285 0x410C474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_286 0x410C478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_287 0x410C47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_288 0x410C480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_289 0x410C484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_290 0x410C488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_291 0x410C48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_292 0x410C490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_293 0x410C494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_294 0x410C498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_295 0x410C49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_296 0x410C4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_297 0x410C4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_298 0x410C4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_299 0x410C4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_300 0x410C4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_301 0x410C4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_302 0x410C4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_303 0x410C4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_304 0x410C4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_305 0x410C4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_306 0x410C4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_307 0x410C4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_308 0x410C4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_309 0x410C4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_310 0x410C4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_311 0x410C4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_312 0x410C4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_313 0x410C4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_314 0x410C4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_315 0x410C4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_316 0x410C4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_317 0x410C4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_318 0x410C4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_319 0x410C4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_320 0x410C500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_321 0x410C504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_322 0x410C508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_323 0x410C50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_324 0x410C510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_325 0x410C514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_326 0x410C518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_327 0x410C51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_328 0x410C520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_329 0x410C524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_330 0x410C528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_331 0x410C52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_332 0x410C530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_333 0x410C534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_334 0x410C538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_335 0x410C53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_336 0x410C540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_337 0x410C544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_338 0x410C548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_339 0x410C54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_340 0x410C550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_341 0x410C554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_342 0x410C558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_343 0x410C55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_344 0x410C560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_345 0x410C564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_346 0x410C568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_347 0x410C56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_348 0x410C570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_349 0x410C574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_350 0x410C578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_351 0x410C57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_352 0x410C580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_353 0x410C584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_354 0x410C588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_355 0x410C58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_356 0x410C590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_357 0x410C594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_358 0x410C598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_359 0x410C59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_360 0x410C5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_361 0x410C5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_362 0x410C5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_363 0x410C5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_364 0x410C5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_365 0x410C5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_366 0x410C5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_367 0x410C5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_368 0x410C5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_369 0x410C5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_370 0x410C5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_371 0x410C5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_372 0x410C5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_373 0x410C5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_374 0x410C5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_375 0x410C5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_376 0x410C5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_377 0x410C5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_378 0x410C5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_379 0x410C5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_380 0x410C5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_381 0x410C5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_382 0x410C5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_383 0x410C5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_384 0x410C600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_385 0x410C604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_386 0x410C608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_387 0x410C60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_388 0x410C610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_389 0x410C614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_390 0x410C618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_391 0x410C61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_392 0x410C620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_393 0x410C624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_394 0x410C628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_395 0x410C62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_396 0x410C630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_397 0x410C634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_398 0x410C638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_399 0x410C63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_400 0x410C640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_401 0x410C644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_402 0x410C648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_403 0x410C64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_404 0x410C650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_405 0x410C654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_406 0x410C658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_407 0x410C65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_408 0x410C660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_409 0x410C664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_410 0x410C668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_411 0x410C66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_412 0x410C670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_413 0x410C674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_414 0x410C678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_415 0x410C67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_416 0x410C680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_417 0x410C684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_418 0x410C688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_419 0x410C68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_420 0x410C690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_421 0x410C694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_422 0x410C698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_423 0x410C69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_424 0x410C6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_425 0x410C6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_426 0x410C6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_427 0x410C6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_428 0x410C6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_429 0x410C6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_430 0x410C6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_431 0x410C6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_432 0x410C6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_433 0x410C6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_434 0x410C6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_435 0x410C6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_436 0x410C6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_437 0x410C6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_438 0x410C6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_439 0x410C6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_440 0x410C6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_441 0x410C6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_442 0x410C6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_443 0x410C6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_444 0x410C6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_445 0x410C6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_446 0x410C6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_447 0x410C6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_448 0x410C700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_449 0x410C704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_450 0x410C708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_451 0x410C70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_452 0x410C710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_453 0x410C714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_454 0x410C718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_455 0x410C71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_456 0x410C720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_457 0x410C724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_458 0x410C728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_459 0x410C72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_460 0x410C730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_461 0x410C734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_462 0x410C738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_463 0x410C73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_464 0x410C740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_465 0x410C744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_466 0x410C748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_467 0x410C74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_468 0x410C750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_469 0x410C754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_470 0x410C758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_471 0x410C75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_472 0x410C760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_473 0x410C764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_474 0x410C768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_475 0x410C76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_476 0x410C770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_477 0x410C774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_478 0x410C778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_479 0x410C77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_480 0x410C780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_481 0x410C784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_482 0x410C788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_483 0x410C78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_484 0x410C790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_485 0x410C794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_486 0x410C798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_487 0x410C79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_488 0x410C7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_489 0x410C7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_490 0x410C7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_491 0x410C7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_492 0x410C7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_493 0x410C7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_494 0x410C7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_495 0x410C7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_496 0x410C7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_497 0x410C7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_498 0x410C7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_499 0x410C7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_500 0x410C7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_501 0x410C7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_502 0x410C7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_503 0x410C7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_504 0x410C7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_505 0x410C7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_506 0x410C7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_507 0x410C7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_508 0x410C7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_509 0x410C7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_510 0x410C7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_511 0x410C7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_512 0x410C800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_513 0x410C804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_514 0x410C808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_515 0x410C80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_516 0x410C810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_517 0x410C814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_518 0x410C818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_519 0x410C81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_520 0x410C820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_521 0x410C824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_522 0x410C828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_523 0x410C82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_524 0x410C830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_525 0x410C834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_526 0x410C838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_527 0x410C83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_528 0x410C840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_529 0x410C844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_530 0x410C848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_531 0x410C84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_532 0x410C850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_533 0x410C854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_534 0x410C858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_535 0x410C85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_536 0x410C860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_537 0x410C864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_538 0x410C868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_539 0x410C86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_540 0x410C870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_541 0x410C874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_542 0x410C878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_543 0x410C87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_544 0x410C880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_545 0x410C884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_546 0x410C888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_547 0x410C88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_548 0x410C890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_549 0x410C894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_550 0x410C898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_551 0x410C89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_552 0x410C8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_553 0x410C8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_554 0x410C8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_555 0x410C8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_556 0x410C8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_557 0x410C8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_558 0x410C8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_559 0x410C8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_560 0x410C8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_561 0x410C8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_562 0x410C8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_563 0x410C8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_564 0x410C8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_565 0x410C8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_566 0x410C8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_567 0x410C8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_568 0x410C8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_569 0x410C8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_570 0x410C8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_571 0x410C8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_572 0x410C8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_573 0x410C8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_574 0x410C8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_575 0x410C8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_576 0x410C900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_577 0x410C904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_578 0x410C908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_579 0x410C90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_580 0x410C910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_581 0x410C914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_582 0x410C918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_583 0x410C91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_584 0x410C920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_585 0x410C924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_586 0x410C928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_587 0x410C92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_588 0x410C930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_589 0x410C934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_590 0x410C938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_591 0x410C93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_592 0x410C940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_593 0x410C944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_594 0x410C948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_595 0x410C94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_596 0x410C950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_597 0x410C954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_598 0x410C958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_599 0x410C95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_600 0x410C960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_601 0x410C964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_602 0x410C968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_603 0x410C96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_604 0x410C970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_605 0x410C974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_606 0x410C978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_607 0x410C97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_608 0x410C980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_609 0x410C984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_610 0x410C988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_611 0x410C98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_612 0x410C990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_613 0x410C994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_614 0x410C998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_615 0x410C99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_616 0x410C9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_617 0x410C9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_618 0x410C9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_619 0x410C9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_620 0x410C9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_621 0x410C9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_622 0x410C9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_623 0x410C9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_624 0x410C9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_625 0x410C9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_626 0x410C9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_627 0x410C9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_628 0x410C9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_629 0x410C9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_630 0x410C9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_631 0x410C9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_632 0x410C9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_633 0x410C9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_634 0x410C9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_635 0x410C9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_636 0x410C9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_637 0x410C9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_638 0x410C9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_639 0x410C9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_640 0x410CA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_641 0x410CA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_642 0x410CA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_643 0x410CA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_644 0x410CA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_645 0x410CA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_646 0x410CA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_647 0x410CA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_648 0x410CA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_649 0x410CA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_650 0x410CA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_651 0x410CA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_652 0x410CA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_653 0x410CA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_654 0x410CA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_655 0x410CA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_656 0x410CA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_657 0x410CA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_658 0x410CA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_659 0x410CA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_660 0x410CA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_661 0x410CA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_662 0x410CA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_663 0x410CA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_664 0x410CA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_665 0x410CA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_666 0x410CA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_667 0x410CA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_668 0x410CA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_669 0x410CA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_670 0x410CA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_671 0x410CA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_672 0x410CA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_673 0x410CA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_674 0x410CA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_675 0x410CA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_676 0x410CA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_677 0x410CA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_678 0x410CA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_679 0x410CA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_680 0x410CAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_681 0x410CAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_682 0x410CAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_683 0x410CAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_684 0x410CAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_685 0x410CAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_686 0x410CAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_687 0x410CABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_688 0x410CAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_689 0x410CAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_690 0x410CAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_691 0x410CACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_692 0x410CAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_693 0x410CAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_694 0x410CAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_695 0x410CADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_696 0x410CAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_697 0x410CAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_698 0x410CAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_699 0x410CAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_700 0x410CAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_701 0x410CAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_702 0x410CAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_703 0x410CAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_704 0x410CB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_705 0x410CB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_706 0x410CB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_707 0x410CB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_708 0x410CB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_709 0x410CB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_710 0x410CB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_711 0x410CB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_712 0x410CB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_713 0x410CB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_714 0x410CB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_715 0x410CB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_716 0x410CB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_717 0x410CB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_718 0x410CB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_719 0x410CB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_720 0x410CB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_721 0x410CB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_722 0x410CB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_723 0x410CB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_724 0x410CB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_725 0x410CB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_726 0x410CB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_727 0x410CB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_728 0x410CB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_729 0x410CB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_730 0x410CB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_731 0x410CB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_732 0x410CB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_733 0x410CB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_734 0x410CB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_735 0x410CB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_736 0x410CB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_737 0x410CB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_738 0x410CB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_739 0x410CB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_740 0x410CB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_741 0x410CB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_742 0x410CB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_743 0x410CB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_744 0x410CBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_745 0x410CBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_746 0x410CBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_747 0x410CBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_748 0x410CBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_749 0x410CBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_750 0x410CBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_751 0x410CBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_752 0x410CBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_753 0x410CBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_754 0x410CBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_755 0x410CBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_756 0x410CBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_757 0x410CBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_758 0x410CBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_759 0x410CBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_760 0x410CBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_761 0x410CBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_762 0x410CBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_763 0x410CBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_764 0x410CBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_765 0x410CBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_766 0x410CBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_767 0x410CBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_768 0x410CC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_769 0x410CC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_770 0x410CC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_771 0x410CC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_772 0x410CC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_773 0x410CC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_774 0x410CC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_775 0x410CC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_776 0x410CC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_777 0x410CC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_778 0x410CC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_779 0x410CC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_780 0x410CC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_781 0x410CC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_782 0x410CC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_783 0x410CC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_784 0x410CC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_785 0x410CC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_786 0x410CC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_787 0x410CC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_788 0x410CC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_789 0x410CC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_790 0x410CC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_791 0x410CC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_792 0x410CC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_793 0x410CC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_794 0x410CC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_795 0x410CC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_796 0x410CC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_797 0x410CC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_798 0x410CC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_799 0x410CC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_800 0x410CC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_801 0x410CC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_802 0x410CC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_803 0x410CC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_804 0x410CC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_805 0x410CC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_806 0x410CC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_807 0x410CC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_808 0x410CCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_809 0x410CCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_810 0x410CCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_811 0x410CCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_812 0x410CCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_813 0x410CCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_814 0x410CCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_815 0x410CCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_816 0x410CCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_817 0x410CCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_818 0x410CCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_819 0x410CCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_820 0x410CCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_821 0x410CCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_822 0x410CCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_823 0x410CCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_824 0x410CCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_825 0x410CCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_826 0x410CCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_827 0x410CCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_828 0x410CCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_829 0x410CCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_830 0x410CCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_831 0x410CCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_832 0x410CD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_833 0x410CD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_834 0x410CD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_835 0x410CD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_836 0x410CD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_837 0x410CD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_838 0x410CD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_839 0x410CD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_840 0x410CD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_841 0x410CD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_842 0x410CD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_843 0x410CD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_844 0x410CD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_845 0x410CD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_846 0x410CD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_847 0x410CD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_848 0x410CD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_849 0x410CD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_850 0x410CD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_851 0x410CD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_852 0x410CD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_853 0x410CD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_854 0x410CD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_855 0x410CD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_856 0x410CD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_857 0x410CD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_858 0x410CD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_859 0x410CD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_860 0x410CD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_861 0x410CD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_862 0x410CD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_863 0x410CD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_864 0x410CD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_865 0x410CD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_866 0x410CD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_867 0x410CD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_868 0x410CD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_869 0x410CD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_870 0x410CD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_871 0x410CD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_872 0x410CDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_873 0x410CDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_874 0x410CDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_875 0x410CDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_876 0x410CDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_877 0x410CDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_878 0x410CDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_879 0x410CDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_880 0x410CDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_881 0x410CDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_882 0x410CDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_883 0x410CDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_884 0x410CDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_885 0x410CDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_886 0x410CDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_887 0x410CDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_888 0x410CDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_889 0x410CDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_890 0x410CDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_891 0x410CDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_892 0x410CDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_893 0x410CDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_894 0x410CDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_895 0x410CDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_896 0x410CE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_897 0x410CE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_898 0x410CE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_899 0x410CE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_900 0x410CE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_901 0x410CE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_902 0x410CE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_903 0x410CE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_904 0x410CE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_905 0x410CE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_906 0x410CE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_907 0x410CE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_908 0x410CE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_909 0x410CE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_910 0x410CE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_911 0x410CE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_912 0x410CE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_913 0x410CE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_914 0x410CE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_915 0x410CE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_916 0x410CE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_917 0x410CE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_918 0x410CE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_919 0x410CE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_920 0x410CE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_921 0x410CE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_922 0x410CE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_923 0x410CE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_924 0x410CE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_925 0x410CE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_926 0x410CE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_927 0x410CE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_928 0x410CE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_929 0x410CE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_930 0x410CE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_931 0x410CE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_932 0x410CE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_933 0x410CE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_934 0x410CE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_935 0x410CE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_936 0x410CEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_937 0x410CEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_938 0x410CEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_939 0x410CEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_940 0x410CEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_941 0x410CEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_942 0x410CEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_943 0x410CEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_944 0x410CEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_945 0x410CEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_946 0x410CEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_947 0x410CECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_948 0x410CED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_949 0x410CED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_950 0x410CED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_951 0x410CEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_952 0x410CEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_953 0x410CEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_954 0x410CEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_955 0x410CEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_956 0x410CEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_957 0x410CEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_958 0x410CEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_959 0x410CEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_960 0x410CF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_961 0x410CF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_962 0x410CF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_963 0x410CF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_964 0x410CF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_965 0x410CF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_966 0x410CF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_967 0x410CF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_968 0x410CF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_969 0x410CF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_970 0x410CF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_971 0x410CF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_972 0x410CF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_973 0x410CF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_974 0x410CF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_975 0x410CF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_976 0x410CF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_977 0x410CF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_978 0x410CF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_979 0x410CF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_980 0x410CF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_981 0x410CF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_982 0x410CF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_983 0x410CF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_984 0x410CF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_985 0x410CF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_986 0x410CF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_987 0x410CF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_988 0x410CF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_989 0x410CF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_990 0x410CF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_991 0x410CF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_992 0x410CF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_993 0x410CF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_994 0x410CF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_995 0x410CF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_996 0x410CF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_997 0x410CF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_998 0x410CF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_999 0x410CF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1000 0x410CFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1001 0x410CFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1002 0x410CFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1003 0x410CFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1004 0x410CFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1005 0x410CFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1006 0x410CFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1007 0x410CFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1008 0x410CFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1009 0x410CFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1010 0x410CFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1011 0x410CFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1012 0x410CFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1013 0x410CFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1014 0x410CFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1015 0x410CFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1016 0x410CFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1017 0x410CFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1018 0x410CFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1019 0x410CFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1020 0x410CFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1021 0x410CFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1022 0x410CFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1023 0x410CFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1024 0x410D000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1025 0x410D004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1026 0x410D008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1027 0x410D00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1028 0x410D010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1029 0x410D014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1030 0x410D018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1031 0x410D01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1032 0x410D020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1033 0x410D024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1034 0x410D028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1035 0x410D02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1036 0x410D030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1037 0x410D034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1038 0x410D038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1039 0x410D03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1040 0x410D040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1041 0x410D044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1042 0x410D048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1043 0x410D04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1044 0x410D050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1045 0x410D054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1046 0x410D058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1047 0x410D05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1048 0x410D060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1049 0x410D064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1050 0x410D068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1051 0x410D06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1052 0x410D070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1053 0x410D074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1054 0x410D078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1055 0x410D07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1056 0x410D080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1057 0x410D084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1058 0x410D088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1059 0x410D08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1060 0x410D090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1061 0x410D094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1062 0x410D098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1063 0x410D09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1064 0x410D0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1065 0x410D0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1066 0x410D0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1067 0x410D0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1068 0x410D0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1069 0x410D0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1070 0x410D0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1071 0x410D0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1072 0x410D0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1073 0x410D0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1074 0x410D0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1075 0x410D0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1076 0x410D0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1077 0x410D0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1078 0x410D0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1079 0x410D0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1080 0x410D0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1081 0x410D0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1082 0x410D0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1083 0x410D0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1084 0x410D0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1085 0x410D0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1086 0x410D0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1087 0x410D0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1088 0x410D100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1089 0x410D104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1090 0x410D108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1091 0x410D10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1092 0x410D110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1093 0x410D114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1094 0x410D118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1095 0x410D11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1096 0x410D120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1097 0x410D124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1098 0x410D128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1099 0x410D12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1100 0x410D130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1101 0x410D134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1102 0x410D138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1103 0x410D13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1104 0x410D140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1105 0x410D144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1106 0x410D148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1107 0x410D14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1108 0x410D150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1109 0x410D154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1110 0x410D158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1111 0x410D15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1112 0x410D160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1113 0x410D164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1114 0x410D168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1115 0x410D16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1116 0x410D170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1117 0x410D174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1118 0x410D178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1119 0x410D17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1120 0x410D180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1121 0x410D184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1122 0x410D188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1123 0x410D18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1124 0x410D190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1125 0x410D194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1126 0x410D198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1127 0x410D19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1128 0x410D1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1129 0x410D1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1130 0x410D1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1131 0x410D1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1132 0x410D1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1133 0x410D1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1134 0x410D1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1135 0x410D1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1136 0x410D1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1137 0x410D1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1138 0x410D1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1139 0x410D1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1140 0x410D1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1141 0x410D1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1142 0x410D1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1143 0x410D1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1144 0x410D1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1145 0x410D1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1146 0x410D1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1147 0x410D1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1148 0x410D1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1149 0x410D1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1150 0x410D1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1151 0x410D1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1152 0x410D200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1153 0x410D204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1154 0x410D208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1155 0x410D20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1156 0x410D210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1157 0x410D214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1158 0x410D218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1159 0x410D21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1160 0x410D220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1161 0x410D224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1162 0x410D228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1163 0x410D22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1164 0x410D230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1165 0x410D234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1166 0x410D238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1167 0x410D23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1168 0x410D240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1169 0x410D244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1170 0x410D248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1171 0x410D24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1172 0x410D250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1173 0x410D254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1174 0x410D258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1175 0x410D25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1176 0x410D260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1177 0x410D264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1178 0x410D268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1179 0x410D26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1180 0x410D270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1181 0x410D274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1182 0x410D278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1183 0x410D27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1184 0x410D280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1185 0x410D284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1186 0x410D288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1187 0x410D28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1188 0x410D290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1189 0x410D294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1190 0x410D298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1191 0x410D29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1192 0x410D2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1193 0x410D2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1194 0x410D2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1195 0x410D2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1196 0x410D2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1197 0x410D2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1198 0x410D2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1199 0x410D2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1200 0x410D2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1201 0x410D2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1202 0x410D2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1203 0x410D2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1204 0x410D2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1205 0x410D2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1206 0x410D2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1207 0x410D2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1208 0x410D2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1209 0x410D2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1210 0x410D2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1211 0x410D2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1212 0x410D2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1213 0x410D2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1214 0x410D2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1215 0x410D2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1216 0x410D300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1217 0x410D304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1218 0x410D308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1219 0x410D30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1220 0x410D310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1221 0x410D314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1222 0x410D318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1223 0x410D31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1224 0x410D320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1225 0x410D324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1226 0x410D328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1227 0x410D32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1228 0x410D330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1229 0x410D334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1230 0x410D338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1231 0x410D33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1232 0x410D340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1233 0x410D344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1234 0x410D348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1235 0x410D34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1236 0x410D350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1237 0x410D354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1238 0x410D358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1239 0x410D35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1240 0x410D360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1241 0x410D364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1242 0x410D368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1243 0x410D36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1244 0x410D370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1245 0x410D374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1246 0x410D378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1247 0x410D37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1248 0x410D380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1249 0x410D384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1250 0x410D388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1251 0x410D38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1252 0x410D390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1253 0x410D394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1254 0x410D398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1255 0x410D39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1256 0x410D3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1257 0x410D3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1258 0x410D3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1259 0x410D3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1260 0x410D3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1261 0x410D3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1262 0x410D3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1263 0x410D3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1264 0x410D3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1265 0x410D3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1266 0x410D3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1267 0x410D3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1268 0x410D3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1269 0x410D3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1270 0x410D3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1271 0x410D3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1272 0x410D3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1273 0x410D3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1274 0x410D3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1275 0x410D3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1276 0x410D3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1277 0x410D3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1278 0x410D3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1279 0x410D3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1280 0x410D400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1281 0x410D404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1282 0x410D408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1283 0x410D40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1284 0x410D410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1285 0x410D414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1286 0x410D418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1287 0x410D41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1288 0x410D420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1289 0x410D424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1290 0x410D428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1291 0x410D42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1292 0x410D430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1293 0x410D434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1294 0x410D438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1295 0x410D43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1296 0x410D440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1297 0x410D444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1298 0x410D448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1299 0x410D44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1300 0x410D450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1301 0x410D454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1302 0x410D458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1303 0x410D45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1304 0x410D460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1305 0x410D464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1306 0x410D468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1307 0x410D46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1308 0x410D470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1309 0x410D474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1310 0x410D478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1311 0x410D47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1312 0x410D480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1313 0x410D484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1314 0x410D488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1315 0x410D48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1316 0x410D490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1317 0x410D494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1318 0x410D498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1319 0x410D49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1320 0x410D4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1321 0x410D4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1322 0x410D4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1323 0x410D4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1324 0x410D4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1325 0x410D4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1326 0x410D4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1327 0x410D4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1328 0x410D4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1329 0x410D4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1330 0x410D4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1331 0x410D4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1332 0x410D4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1333 0x410D4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1334 0x410D4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1335 0x410D4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1336 0x410D4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1337 0x410D4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1338 0x410D4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1339 0x410D4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1340 0x410D4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1341 0x410D4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1342 0x410D4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1343 0x410D4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1344 0x410D500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1345 0x410D504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1346 0x410D508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1347 0x410D50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1348 0x410D510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1349 0x410D514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1350 0x410D518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1351 0x410D51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1352 0x410D520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1353 0x410D524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1354 0x410D528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1355 0x410D52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1356 0x410D530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1357 0x410D534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1358 0x410D538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1359 0x410D53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1360 0x410D540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1361 0x410D544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1362 0x410D548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1363 0x410D54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1364 0x410D550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1365 0x410D554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1366 0x410D558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1367 0x410D55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1368 0x410D560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1369 0x410D564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1370 0x410D568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1371 0x410D56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1372 0x410D570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1373 0x410D574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1374 0x410D578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1375 0x410D57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1376 0x410D580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1377 0x410D584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1378 0x410D588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1379 0x410D58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1380 0x410D590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1381 0x410D594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1382 0x410D598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1383 0x410D59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1384 0x410D5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1385 0x410D5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1386 0x410D5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1387 0x410D5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1388 0x410D5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1389 0x410D5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1390 0x410D5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1391 0x410D5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1392 0x410D5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1393 0x410D5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1394 0x410D5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1395 0x410D5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1396 0x410D5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1397 0x410D5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1398 0x410D5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1399 0x410D5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1400 0x410D5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1401 0x410D5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1402 0x410D5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1403 0x410D5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1404 0x410D5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1405 0x410D5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1406 0x410D5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1407 0x410D5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1408 0x410D600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1409 0x410D604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1410 0x410D608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1411 0x410D60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1412 0x410D610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1413 0x410D614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1414 0x410D618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1415 0x410D61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1416 0x410D620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1417 0x410D624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1418 0x410D628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1419 0x410D62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1420 0x410D630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1421 0x410D634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1422 0x410D638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1423 0x410D63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1424 0x410D640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1425 0x410D644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1426 0x410D648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1427 0x410D64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1428 0x410D650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1429 0x410D654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1430 0x410D658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1431 0x410D65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1432 0x410D660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1433 0x410D664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1434 0x410D668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1435 0x410D66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1436 0x410D670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1437 0x410D674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1438 0x410D678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1439 0x410D67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1440 0x410D680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1441 0x410D684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1442 0x410D688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1443 0x410D68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1444 0x410D690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1445 0x410D694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1446 0x410D698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1447 0x410D69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1448 0x410D6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1449 0x410D6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1450 0x410D6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1451 0x410D6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1452 0x410D6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1453 0x410D6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1454 0x410D6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1455 0x410D6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1456 0x410D6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1457 0x410D6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1458 0x410D6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1459 0x410D6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1460 0x410D6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1461 0x410D6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1462 0x410D6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1463 0x410D6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1464 0x410D6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1465 0x410D6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1466 0x410D6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1467 0x410D6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1468 0x410D6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1469 0x410D6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1470 0x410D6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1471 0x410D6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1472 0x410D700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1473 0x410D704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1474 0x410D708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1475 0x410D70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1476 0x410D710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1477 0x410D714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1478 0x410D718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1479 0x410D71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1480 0x410D720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1481 0x410D724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1482 0x410D728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1483 0x410D72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1484 0x410D730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1485 0x410D734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1486 0x410D738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1487 0x410D73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1488 0x410D740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1489 0x410D744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1490 0x410D748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1491 0x410D74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1492 0x410D750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1493 0x410D754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1494 0x410D758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1495 0x410D75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1496 0x410D760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1497 0x410D764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1498 0x410D768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1499 0x410D76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1500 0x410D770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1501 0x410D774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1502 0x410D778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1503 0x410D77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1504 0x410D780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1505 0x410D784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1506 0x410D788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1507 0x410D78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1508 0x410D790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1509 0x410D794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1510 0x410D798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1511 0x410D79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1512 0x410D7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1513 0x410D7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1514 0x410D7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1515 0x410D7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1516 0x410D7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1517 0x410D7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1518 0x410D7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1519 0x410D7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1520 0x410D7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1521 0x410D7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1522 0x410D7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1523 0x410D7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1524 0x410D7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1525 0x410D7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1526 0x410D7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1527 0x410D7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1528 0x410D7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1529 0x410D7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1530 0x410D7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1531 0x410D7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1532 0x410D7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1533 0x410D7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1534 0x410D7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1535 0x410D7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1536 0x410D800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1537 0x410D804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1538 0x410D808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1539 0x410D80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1540 0x410D810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1541 0x410D814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1542 0x410D818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1543 0x410D81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1544 0x410D820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1545 0x410D824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1546 0x410D828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1547 0x410D82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1548 0x410D830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1549 0x410D834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1550 0x410D838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1551 0x410D83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1552 0x410D840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1553 0x410D844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1554 0x410D848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1555 0x410D84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1556 0x410D850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1557 0x410D854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1558 0x410D858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1559 0x410D85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1560 0x410D860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1561 0x410D864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1562 0x410D868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1563 0x410D86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1564 0x410D870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1565 0x410D874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1566 0x410D878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1567 0x410D87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1568 0x410D880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1569 0x410D884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1570 0x410D888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1571 0x410D88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1572 0x410D890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1573 0x410D894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1574 0x410D898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1575 0x410D89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1576 0x410D8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1577 0x410D8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1578 0x410D8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1579 0x410D8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1580 0x410D8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1581 0x410D8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1582 0x410D8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1583 0x410D8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1584 0x410D8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1585 0x410D8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1586 0x410D8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1587 0x410D8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1588 0x410D8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1589 0x410D8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1590 0x410D8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1591 0x410D8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1592 0x410D8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1593 0x410D8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1594 0x410D8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1595 0x410D8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1596 0x410D8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1597 0x410D8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1598 0x410D8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1599 0x410D8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1600 0x410D900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1601 0x410D904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1602 0x410D908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1603 0x410D90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1604 0x410D910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1605 0x410D914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1606 0x410D918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1607 0x410D91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1608 0x410D920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1609 0x410D924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1610 0x410D928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1611 0x410D92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1612 0x410D930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1613 0x410D934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1614 0x410D938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1615 0x410D93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1616 0x410D940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1617 0x410D944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1618 0x410D948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1619 0x410D94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1620 0x410D950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1621 0x410D954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1622 0x410D958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1623 0x410D95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1624 0x410D960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1625 0x410D964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1626 0x410D968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1627 0x410D96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1628 0x410D970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1629 0x410D974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1630 0x410D978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1631 0x410D97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1632 0x410D980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1633 0x410D984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1634 0x410D988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1635 0x410D98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1636 0x410D990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1637 0x410D994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1638 0x410D998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1639 0x410D99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1640 0x410D9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1641 0x410D9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1642 0x410D9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1643 0x410D9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1644 0x410D9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1645 0x410D9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1646 0x410D9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1647 0x410D9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1648 0x410D9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1649 0x410D9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1650 0x410D9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1651 0x410D9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1652 0x410D9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1653 0x410D9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1654 0x410D9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1655 0x410D9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1656 0x410D9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1657 0x410D9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1658 0x410D9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1659 0x410D9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1660 0x410D9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1661 0x410D9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1662 0x410D9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1663 0x410D9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1664 0x410DA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1665 0x410DA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1666 0x410DA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1667 0x410DA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1668 0x410DA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1669 0x410DA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1670 0x410DA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1671 0x410DA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1672 0x410DA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1673 0x410DA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1674 0x410DA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1675 0x410DA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1676 0x410DA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1677 0x410DA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1678 0x410DA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1679 0x410DA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1680 0x410DA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1681 0x410DA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1682 0x410DA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1683 0x410DA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1684 0x410DA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1685 0x410DA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1686 0x410DA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1687 0x410DA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1688 0x410DA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1689 0x410DA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1690 0x410DA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1691 0x410DA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1692 0x410DA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1693 0x410DA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1694 0x410DA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1695 0x410DA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1696 0x410DA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1697 0x410DA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1698 0x410DA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1699 0x410DA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1700 0x410DA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1701 0x410DA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1702 0x410DA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1703 0x410DA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1704 0x410DAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1705 0x410DAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1706 0x410DAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1707 0x410DAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1708 0x410DAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1709 0x410DAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1710 0x410DAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1711 0x410DABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1712 0x410DAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1713 0x410DAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1714 0x410DAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1715 0x410DACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1716 0x410DAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1717 0x410DAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1718 0x410DAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1719 0x410DADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1720 0x410DAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1721 0x410DAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1722 0x410DAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1723 0x410DAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1724 0x410DAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1725 0x410DAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1726 0x410DAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1727 0x410DAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1728 0x410DB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1729 0x410DB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1730 0x410DB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1731 0x410DB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1732 0x410DB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1733 0x410DB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1734 0x410DB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1735 0x410DB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1736 0x410DB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1737 0x410DB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1738 0x410DB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1739 0x410DB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1740 0x410DB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1741 0x410DB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1742 0x410DB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1743 0x410DB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1744 0x410DB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1745 0x410DB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1746 0x410DB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1747 0x410DB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1748 0x410DB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1749 0x410DB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1750 0x410DB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1751 0x410DB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1752 0x410DB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1753 0x410DB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1754 0x410DB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1755 0x410DB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1756 0x410DB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1757 0x410DB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1758 0x410DB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1759 0x410DB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1760 0x410DB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1761 0x410DB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1762 0x410DB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1763 0x410DB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1764 0x410DB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1765 0x410DB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1766 0x410DB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1767 0x410DB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1768 0x410DBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1769 0x410DBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1770 0x410DBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1771 0x410DBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1772 0x410DBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1773 0x410DBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1774 0x410DBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1775 0x410DBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1776 0x410DBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1777 0x410DBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1778 0x410DBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1779 0x410DBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1780 0x410DBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1781 0x410DBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1782 0x410DBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1783 0x410DBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1784 0x410DBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1785 0x410DBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1786 0x410DBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1787 0x410DBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1788 0x410DBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1789 0x410DBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1790 0x410DBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1791 0x410DBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1792 0x410DC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1793 0x410DC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1794 0x410DC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1795 0x410DC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1796 0x410DC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1797 0x410DC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1798 0x410DC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1799 0x410DC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1800 0x410DC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1801 0x410DC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1802 0x410DC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1803 0x410DC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1804 0x410DC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1805 0x410DC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1806 0x410DC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1807 0x410DC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1808 0x410DC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1809 0x410DC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1810 0x410DC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1811 0x410DC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1812 0x410DC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1813 0x410DC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1814 0x410DC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1815 0x410DC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1816 0x410DC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1817 0x410DC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1818 0x410DC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1819 0x410DC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1820 0x410DC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1821 0x410DC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1822 0x410DC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1823 0x410DC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1824 0x410DC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1825 0x410DC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1826 0x410DC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1827 0x410DC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1828 0x410DC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1829 0x410DC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1830 0x410DC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1831 0x410DC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1832 0x410DCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1833 0x410DCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1834 0x410DCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1835 0x410DCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1836 0x410DCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1837 0x410DCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1838 0x410DCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1839 0x410DCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1840 0x410DCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1841 0x410DCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1842 0x410DCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1843 0x410DCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1844 0x410DCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1845 0x410DCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1846 0x410DCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1847 0x410DCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1848 0x410DCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1849 0x410DCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1850 0x410DCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1851 0x410DCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1852 0x410DCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1853 0x410DCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1854 0x410DCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1855 0x410DCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1856 0x410DD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1857 0x410DD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1858 0x410DD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1859 0x410DD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1860 0x410DD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1861 0x410DD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1862 0x410DD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1863 0x410DD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1864 0x410DD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1865 0x410DD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1866 0x410DD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1867 0x410DD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1868 0x410DD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1869 0x410DD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1870 0x410DD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1871 0x410DD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1872 0x410DD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1873 0x410DD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1874 0x410DD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1875 0x410DD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1876 0x410DD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1877 0x410DD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1878 0x410DD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1879 0x410DD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1880 0x410DD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1881 0x410DD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1882 0x410DD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1883 0x410DD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1884 0x410DD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1885 0x410DD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1886 0x410DD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1887 0x410DD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1888 0x410DD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1889 0x410DD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1890 0x410DD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1891 0x410DD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1892 0x410DD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1893 0x410DD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1894 0x410DD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1895 0x410DD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1896 0x410DDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1897 0x410DDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1898 0x410DDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1899 0x410DDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1900 0x410DDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1901 0x410DDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1902 0x410DDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1903 0x410DDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1904 0x410DDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1905 0x410DDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1906 0x410DDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1907 0x410DDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1908 0x410DDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1909 0x410DDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1910 0x410DDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1911 0x410DDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1912 0x410DDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1913 0x410DDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1914 0x410DDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1915 0x410DDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1916 0x410DDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1917 0x410DDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1918 0x410DDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1919 0x410DDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1920 0x410DE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1921 0x410DE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1922 0x410DE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1923 0x410DE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1924 0x410DE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1925 0x410DE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1926 0x410DE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1927 0x410DE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1928 0x410DE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1929 0x410DE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1930 0x410DE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1931 0x410DE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1932 0x410DE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1933 0x410DE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1934 0x410DE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1935 0x410DE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1936 0x410DE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1937 0x410DE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1938 0x410DE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1939 0x410DE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1940 0x410DE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1941 0x410DE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1942 0x410DE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1943 0x410DE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1944 0x410DE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1945 0x410DE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1946 0x410DE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1947 0x410DE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1948 0x410DE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1949 0x410DE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1950 0x410DE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1951 0x410DE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1952 0x410DE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1953 0x410DE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1954 0x410DE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1955 0x410DE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1956 0x410DE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1957 0x410DE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1958 0x410DE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1959 0x410DE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1960 0x410DEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1961 0x410DEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1962 0x410DEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1963 0x410DEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1964 0x410DEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1965 0x410DEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1966 0x410DEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1967 0x410DEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1968 0x410DEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1969 0x410DEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1970 0x410DEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1971 0x410DECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1972 0x410DED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1973 0x410DED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1974 0x410DED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1975 0x410DEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1976 0x410DEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1977 0x410DEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1978 0x410DEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1979 0x410DEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1980 0x410DEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1981 0x410DEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1982 0x410DEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1983 0x410DEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1984 0x410DF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1985 0x410DF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1986 0x410DF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1987 0x410DF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1988 0x410DF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1989 0x410DF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1990 0x410DF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1991 0x410DF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1992 0x410DF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1993 0x410DF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1994 0x410DF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1995 0x410DF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1996 0x410DF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1997 0x410DF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1998 0x410DF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1999 0x410DF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2000 0x410DF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2001 0x410DF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2002 0x410DF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2003 0x410DF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2004 0x410DF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2005 0x410DF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2006 0x410DF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2007 0x410DF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2008 0x410DF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2009 0x410DF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2010 0x410DF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2011 0x410DF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2012 0x410DF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2013 0x410DF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2014 0x410DF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2015 0x410DF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2016 0x410DF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2017 0x410DF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2018 0x410DF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2019 0x410DF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2020 0x410DF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2021 0x410DF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2022 0x410DF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2023 0x410DF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2024 0x410DFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2025 0x410DFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2026 0x410DFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2027 0x410DFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2028 0x410DFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2029 0x410DFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2030 0x410DFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2031 0x410DFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2032 0x410DFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2033 0x410DFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2034 0x410DFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2035 0x410DFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2036 0x410DFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2037 0x410DFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2038 0x410DFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2039 0x410DFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2040 0x410DFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2041 0x410DFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2042 0x410DFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2043 0x410DFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2044 0x410DFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2045 0x410DFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2046 0x410DFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2047 0x410DFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 0x410E000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1 0x410E004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2 0x410E008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_3 0x410E00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_4 0x410E010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_5 0x410E014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_6 0x410E018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_7 0x410E01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_8 0x410E020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_9 0x410E024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_10 0x410E028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_11 0x410E02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_12 0x410E030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_13 0x410E034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_14 0x410E038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_15 0x410E03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_16 0x410E040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_17 0x410E044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_18 0x410E048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_19 0x410E04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_20 0x410E050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_21 0x410E054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_22 0x410E058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_23 0x410E05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_24 0x410E060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_25 0x410E064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_26 0x410E068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_27 0x410E06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_28 0x410E070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_29 0x410E074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_30 0x410E078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_31 0x410E07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_32 0x410E080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_33 0x410E084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_34 0x410E088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_35 0x410E08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_36 0x410E090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_37 0x410E094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_38 0x410E098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_39 0x410E09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_40 0x410E0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_41 0x410E0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_42 0x410E0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_43 0x410E0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_44 0x410E0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_45 0x410E0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_46 0x410E0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_47 0x410E0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_48 0x410E0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_49 0x410E0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_50 0x410E0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_51 0x410E0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_52 0x410E0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_53 0x410E0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_54 0x410E0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_55 0x410E0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_56 0x410E0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_57 0x410E0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_58 0x410E0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_59 0x410E0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_60 0x410E0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_61 0x410E0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_62 0x410E0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_63 0x410E0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_64 0x410E100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_65 0x410E104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_66 0x410E108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_67 0x410E10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_68 0x410E110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_69 0x410E114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_70 0x410E118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_71 0x410E11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_72 0x410E120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_73 0x410E124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_74 0x410E128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_75 0x410E12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_76 0x410E130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_77 0x410E134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_78 0x410E138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_79 0x410E13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_80 0x410E140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_81 0x410E144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_82 0x410E148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_83 0x410E14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_84 0x410E150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_85 0x410E154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_86 0x410E158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_87 0x410E15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_88 0x410E160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_89 0x410E164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_90 0x410E168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_91 0x410E16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_92 0x410E170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_93 0x410E174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_94 0x410E178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_95 0x410E17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_96 0x410E180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_97 0x410E184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_98 0x410E188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_99 0x410E18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_100 0x410E190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_101 0x410E194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_102 0x410E198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_103 0x410E19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_104 0x410E1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_105 0x410E1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_106 0x410E1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_107 0x410E1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_108 0x410E1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_109 0x410E1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_110 0x410E1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_111 0x410E1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_112 0x410E1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_113 0x410E1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_114 0x410E1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_115 0x410E1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_116 0x410E1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_117 0x410E1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_118 0x410E1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_119 0x410E1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_120 0x410E1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_121 0x410E1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_122 0x410E1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_123 0x410E1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_124 0x410E1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_125 0x410E1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_126 0x410E1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_127 0x410E1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_128 0x410E200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_129 0x410E204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_130 0x410E208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_131 0x410E20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_132 0x410E210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_133 0x410E214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_134 0x410E218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_135 0x410E21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_136 0x410E220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_137 0x410E224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_138 0x410E228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_139 0x410E22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_140 0x410E230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_141 0x410E234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_142 0x410E238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_143 0x410E23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_144 0x410E240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_145 0x410E244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_146 0x410E248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_147 0x410E24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_148 0x410E250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_149 0x410E254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_150 0x410E258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_151 0x410E25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_152 0x410E260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_153 0x410E264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_154 0x410E268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_155 0x410E26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_156 0x410E270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_157 0x410E274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_158 0x410E278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_159 0x410E27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_160 0x410E280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_161 0x410E284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_162 0x410E288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_163 0x410E28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_164 0x410E290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_165 0x410E294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_166 0x410E298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_167 0x410E29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_168 0x410E2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_169 0x410E2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_170 0x410E2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_171 0x410E2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_172 0x410E2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_173 0x410E2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_174 0x410E2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_175 0x410E2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_176 0x410E2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_177 0x410E2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_178 0x410E2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_179 0x410E2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_180 0x410E2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_181 0x410E2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_182 0x410E2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_183 0x410E2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_184 0x410E2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_185 0x410E2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_186 0x410E2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_187 0x410E2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_188 0x410E2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_189 0x410E2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_190 0x410E2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_191 0x410E2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_192 0x410E300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_193 0x410E304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_194 0x410E308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_195 0x410E30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_196 0x410E310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_197 0x410E314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_198 0x410E318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_199 0x410E31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_200 0x410E320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_201 0x410E324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_202 0x410E328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_203 0x410E32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_204 0x410E330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_205 0x410E334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_206 0x410E338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_207 0x410E33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_208 0x410E340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_209 0x410E344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_210 0x410E348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_211 0x410E34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_212 0x410E350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_213 0x410E354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_214 0x410E358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_215 0x410E35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_216 0x410E360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_217 0x410E364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_218 0x410E368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_219 0x410E36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_220 0x410E370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_221 0x410E374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_222 0x410E378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_223 0x410E37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_224 0x410E380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_225 0x410E384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_226 0x410E388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_227 0x410E38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_228 0x410E390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_229 0x410E394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_230 0x410E398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_231 0x410E39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_232 0x410E3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_233 0x410E3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_234 0x410E3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_235 0x410E3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_236 0x410E3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_237 0x410E3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_238 0x410E3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_239 0x410E3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_240 0x410E3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_241 0x410E3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_242 0x410E3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_243 0x410E3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_244 0x410E3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_245 0x410E3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_246 0x410E3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_247 0x410E3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_248 0x410E3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_249 0x410E3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_250 0x410E3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_251 0x410E3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_252 0x410E3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_253 0x410E3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_254 0x410E3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_255 0x410E3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_256 0x410E400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_257 0x410E404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_258 0x410E408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_259 0x410E40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_260 0x410E410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_261 0x410E414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_262 0x410E418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_263 0x410E41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_264 0x410E420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_265 0x410E424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_266 0x410E428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_267 0x410E42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_268 0x410E430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_269 0x410E434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_270 0x410E438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_271 0x410E43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_272 0x410E440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_273 0x410E444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_274 0x410E448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_275 0x410E44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_276 0x410E450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_277 0x410E454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_278 0x410E458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_279 0x410E45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_280 0x410E460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_281 0x410E464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_282 0x410E468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_283 0x410E46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_284 0x410E470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_285 0x410E474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_286 0x410E478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_287 0x410E47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_288 0x410E480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_289 0x410E484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_290 0x410E488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_291 0x410E48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_292 0x410E490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_293 0x410E494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_294 0x410E498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_295 0x410E49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_296 0x410E4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_297 0x410E4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_298 0x410E4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_299 0x410E4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_300 0x410E4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_301 0x410E4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_302 0x410E4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_303 0x410E4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_304 0x410E4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_305 0x410E4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_306 0x410E4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_307 0x410E4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_308 0x410E4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_309 0x410E4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_310 0x410E4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_311 0x410E4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_312 0x410E4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_313 0x410E4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_314 0x410E4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_315 0x410E4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_316 0x410E4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_317 0x410E4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_318 0x410E4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_319 0x410E4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_320 0x410E500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_321 0x410E504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_322 0x410E508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_323 0x410E50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_324 0x410E510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_325 0x410E514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_326 0x410E518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_327 0x410E51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_328 0x410E520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_329 0x410E524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_330 0x410E528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_331 0x410E52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_332 0x410E530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_333 0x410E534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_334 0x410E538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_335 0x410E53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_336 0x410E540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_337 0x410E544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_338 0x410E548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_339 0x410E54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_340 0x410E550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_341 0x410E554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_342 0x410E558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_343 0x410E55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_344 0x410E560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_345 0x410E564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_346 0x410E568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_347 0x410E56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_348 0x410E570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_349 0x410E574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_350 0x410E578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_351 0x410E57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_352 0x410E580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_353 0x410E584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_354 0x410E588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_355 0x410E58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_356 0x410E590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_357 0x410E594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_358 0x410E598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_359 0x410E59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_360 0x410E5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_361 0x410E5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_362 0x410E5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_363 0x410E5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_364 0x410E5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_365 0x410E5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_366 0x410E5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_367 0x410E5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_368 0x410E5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_369 0x410E5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_370 0x410E5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_371 0x410E5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_372 0x410E5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_373 0x410E5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_374 0x410E5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_375 0x410E5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_376 0x410E5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_377 0x410E5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_378 0x410E5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_379 0x410E5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_380 0x410E5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_381 0x410E5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_382 0x410E5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_383 0x410E5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_384 0x410E600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_385 0x410E604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_386 0x410E608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_387 0x410E60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_388 0x410E610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_389 0x410E614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_390 0x410E618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_391 0x410E61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_392 0x410E620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_393 0x410E624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_394 0x410E628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_395 0x410E62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_396 0x410E630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_397 0x410E634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_398 0x410E638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_399 0x410E63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_400 0x410E640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_401 0x410E644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_402 0x410E648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_403 0x410E64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_404 0x410E650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_405 0x410E654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_406 0x410E658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_407 0x410E65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_408 0x410E660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_409 0x410E664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_410 0x410E668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_411 0x410E66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_412 0x410E670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_413 0x410E674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_414 0x410E678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_415 0x410E67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_416 0x410E680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_417 0x410E684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_418 0x410E688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_419 0x410E68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_420 0x410E690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_421 0x410E694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_422 0x410E698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_423 0x410E69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_424 0x410E6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_425 0x410E6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_426 0x410E6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_427 0x410E6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_428 0x410E6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_429 0x410E6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_430 0x410E6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_431 0x410E6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_432 0x410E6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_433 0x410E6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_434 0x410E6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_435 0x410E6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_436 0x410E6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_437 0x410E6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_438 0x410E6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_439 0x410E6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_440 0x410E6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_441 0x410E6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_442 0x410E6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_443 0x410E6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_444 0x410E6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_445 0x410E6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_446 0x410E6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_447 0x410E6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_448 0x410E700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_449 0x410E704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_450 0x410E708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_451 0x410E70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_452 0x410E710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_453 0x410E714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_454 0x410E718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_455 0x410E71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_456 0x410E720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_457 0x410E724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_458 0x410E728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_459 0x410E72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_460 0x410E730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_461 0x410E734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_462 0x410E738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_463 0x410E73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_464 0x410E740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_465 0x410E744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_466 0x410E748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_467 0x410E74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_468 0x410E750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_469 0x410E754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_470 0x410E758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_471 0x410E75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_472 0x410E760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_473 0x410E764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_474 0x410E768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_475 0x410E76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_476 0x410E770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_477 0x410E774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_478 0x410E778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_479 0x410E77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_480 0x410E780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_481 0x410E784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_482 0x410E788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_483 0x410E78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_484 0x410E790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_485 0x410E794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_486 0x410E798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_487 0x410E79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_488 0x410E7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_489 0x410E7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_490 0x410E7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_491 0x410E7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_492 0x410E7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_493 0x410E7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_494 0x410E7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_495 0x410E7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_496 0x410E7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_497 0x410E7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_498 0x410E7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_499 0x410E7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_500 0x410E7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_501 0x410E7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_502 0x410E7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_503 0x410E7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_504 0x410E7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_505 0x410E7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_506 0x410E7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_507 0x410E7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_508 0x410E7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_509 0x410E7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_510 0x410E7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_511 0x410E7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_512 0x410E800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_513 0x410E804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_514 0x410E808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_515 0x410E80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_516 0x410E810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_517 0x410E814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_518 0x410E818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_519 0x410E81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_520 0x410E820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_521 0x410E824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_522 0x410E828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_523 0x410E82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_524 0x410E830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_525 0x410E834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_526 0x410E838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_527 0x410E83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_528 0x410E840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_529 0x410E844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_530 0x410E848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_531 0x410E84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_532 0x410E850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_533 0x410E854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_534 0x410E858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_535 0x410E85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_536 0x410E860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_537 0x410E864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_538 0x410E868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_539 0x410E86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_540 0x410E870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_541 0x410E874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_542 0x410E878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_543 0x410E87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_544 0x410E880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_545 0x410E884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_546 0x410E888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_547 0x410E88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_548 0x410E890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_549 0x410E894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_550 0x410E898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_551 0x410E89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_552 0x410E8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_553 0x410E8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_554 0x410E8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_555 0x410E8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_556 0x410E8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_557 0x410E8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_558 0x410E8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_559 0x410E8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_560 0x410E8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_561 0x410E8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_562 0x410E8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_563 0x410E8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_564 0x410E8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_565 0x410E8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_566 0x410E8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_567 0x410E8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_568 0x410E8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_569 0x410E8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_570 0x410E8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_571 0x410E8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_572 0x410E8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_573 0x410E8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_574 0x410E8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_575 0x410E8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_576 0x410E900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_577 0x410E904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_578 0x410E908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_579 0x410E90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_580 0x410E910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_581 0x410E914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_582 0x410E918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_583 0x410E91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_584 0x410E920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_585 0x410E924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_586 0x410E928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_587 0x410E92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_588 0x410E930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_589 0x410E934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_590 0x410E938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_591 0x410E93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_592 0x410E940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_593 0x410E944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_594 0x410E948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_595 0x410E94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_596 0x410E950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_597 0x410E954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_598 0x410E958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_599 0x410E95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_600 0x410E960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_601 0x410E964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_602 0x410E968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_603 0x410E96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_604 0x410E970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_605 0x410E974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_606 0x410E978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_607 0x410E97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_608 0x410E980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_609 0x410E984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_610 0x410E988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_611 0x410E98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_612 0x410E990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_613 0x410E994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_614 0x410E998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_615 0x410E99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_616 0x410E9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_617 0x410E9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_618 0x410E9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_619 0x410E9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_620 0x410E9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_621 0x410E9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_622 0x410E9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_623 0x410E9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_624 0x410E9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_625 0x410E9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_626 0x410E9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_627 0x410E9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_628 0x410E9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_629 0x410E9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_630 0x410E9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_631 0x410E9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_632 0x410E9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_633 0x410E9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_634 0x410E9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_635 0x410E9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_636 0x410E9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_637 0x410E9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_638 0x410E9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_639 0x410E9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_640 0x410EA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_641 0x410EA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_642 0x410EA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_643 0x410EA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_644 0x410EA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_645 0x410EA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_646 0x410EA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_647 0x410EA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_648 0x410EA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_649 0x410EA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_650 0x410EA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_651 0x410EA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_652 0x410EA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_653 0x410EA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_654 0x410EA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_655 0x410EA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_656 0x410EA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_657 0x410EA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_658 0x410EA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_659 0x410EA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_660 0x410EA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_661 0x410EA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_662 0x410EA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_663 0x410EA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_664 0x410EA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_665 0x410EA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_666 0x410EA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_667 0x410EA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_668 0x410EA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_669 0x410EA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_670 0x410EA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_671 0x410EA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_672 0x410EA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_673 0x410EA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_674 0x410EA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_675 0x410EA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_676 0x410EA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_677 0x410EA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_678 0x410EA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_679 0x410EA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_680 0x410EAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_681 0x410EAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_682 0x410EAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_683 0x410EAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_684 0x410EAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_685 0x410EAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_686 0x410EAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_687 0x410EABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_688 0x410EAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_689 0x410EAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_690 0x410EAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_691 0x410EACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_692 0x410EAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_693 0x410EAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_694 0x410EAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_695 0x410EADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_696 0x410EAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_697 0x410EAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_698 0x410EAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_699 0x410EAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_700 0x410EAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_701 0x410EAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_702 0x410EAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_703 0x410EAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_704 0x410EB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_705 0x410EB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_706 0x410EB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_707 0x410EB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_708 0x410EB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_709 0x410EB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_710 0x410EB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_711 0x410EB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_712 0x410EB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_713 0x410EB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_714 0x410EB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_715 0x410EB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_716 0x410EB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_717 0x410EB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_718 0x410EB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_719 0x410EB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_720 0x410EB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_721 0x410EB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_722 0x410EB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_723 0x410EB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_724 0x410EB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_725 0x410EB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_726 0x410EB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_727 0x410EB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_728 0x410EB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_729 0x410EB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_730 0x410EB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_731 0x410EB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_732 0x410EB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_733 0x410EB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_734 0x410EB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_735 0x410EB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_736 0x410EB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_737 0x410EB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_738 0x410EB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_739 0x410EB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_740 0x410EB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_741 0x410EB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_742 0x410EB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_743 0x410EB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_744 0x410EBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_745 0x410EBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_746 0x410EBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_747 0x410EBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_748 0x410EBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_749 0x410EBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_750 0x410EBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_751 0x410EBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_752 0x410EBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_753 0x410EBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_754 0x410EBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_755 0x410EBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_756 0x410EBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_757 0x410EBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_758 0x410EBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_759 0x410EBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_760 0x410EBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_761 0x410EBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_762 0x410EBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_763 0x410EBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_764 0x410EBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_765 0x410EBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_766 0x410EBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_767 0x410EBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_768 0x410EC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_769 0x410EC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_770 0x410EC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_771 0x410EC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_772 0x410EC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_773 0x410EC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_774 0x410EC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_775 0x410EC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_776 0x410EC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_777 0x410EC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_778 0x410EC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_779 0x410EC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_780 0x410EC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_781 0x410EC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_782 0x410EC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_783 0x410EC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_784 0x410EC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_785 0x410EC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_786 0x410EC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_787 0x410EC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_788 0x410EC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_789 0x410EC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_790 0x410EC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_791 0x410EC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_792 0x410EC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_793 0x410EC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_794 0x410EC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_795 0x410EC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_796 0x410EC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_797 0x410EC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_798 0x410EC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_799 0x410EC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_800 0x410EC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_801 0x410EC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_802 0x410EC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_803 0x410EC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_804 0x410EC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_805 0x410EC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_806 0x410EC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_807 0x410EC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_808 0x410ECA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_809 0x410ECA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_810 0x410ECA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_811 0x410ECAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_812 0x410ECB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_813 0x410ECB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_814 0x410ECB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_815 0x410ECBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_816 0x410ECC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_817 0x410ECC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_818 0x410ECC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_819 0x410ECCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_820 0x410ECD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_821 0x410ECD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_822 0x410ECD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_823 0x410ECDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_824 0x410ECE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_825 0x410ECE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_826 0x410ECE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_827 0x410ECEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_828 0x410ECF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_829 0x410ECF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_830 0x410ECF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_831 0x410ECFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_832 0x410ED00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_833 0x410ED04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_834 0x410ED08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_835 0x410ED0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_836 0x410ED10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_837 0x410ED14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_838 0x410ED18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_839 0x410ED1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_840 0x410ED20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_841 0x410ED24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_842 0x410ED28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_843 0x410ED2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_844 0x410ED30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_845 0x410ED34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_846 0x410ED38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_847 0x410ED3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_848 0x410ED40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_849 0x410ED44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_850 0x410ED48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_851 0x410ED4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_852 0x410ED50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_853 0x410ED54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_854 0x410ED58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_855 0x410ED5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_856 0x410ED60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_857 0x410ED64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_858 0x410ED68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_859 0x410ED6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_860 0x410ED70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_861 0x410ED74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_862 0x410ED78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_863 0x410ED7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_864 0x410ED80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_865 0x410ED84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_866 0x410ED88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_867 0x410ED8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_868 0x410ED90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_869 0x410ED94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_870 0x410ED98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_871 0x410ED9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_872 0x410EDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_873 0x410EDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_874 0x410EDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_875 0x410EDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_876 0x410EDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_877 0x410EDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_878 0x410EDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_879 0x410EDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_880 0x410EDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_881 0x410EDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_882 0x410EDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_883 0x410EDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_884 0x410EDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_885 0x410EDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_886 0x410EDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_887 0x410EDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_888 0x410EDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_889 0x410EDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_890 0x410EDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_891 0x410EDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_892 0x410EDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_893 0x410EDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_894 0x410EDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_895 0x410EDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_896 0x410EE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_897 0x410EE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_898 0x410EE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_899 0x410EE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_900 0x410EE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_901 0x410EE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_902 0x410EE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_903 0x410EE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_904 0x410EE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_905 0x410EE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_906 0x410EE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_907 0x410EE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_908 0x410EE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_909 0x410EE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_910 0x410EE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_911 0x410EE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_912 0x410EE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_913 0x410EE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_914 0x410EE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_915 0x410EE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_916 0x410EE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_917 0x410EE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_918 0x410EE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_919 0x410EE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_920 0x410EE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_921 0x410EE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_922 0x410EE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_923 0x410EE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_924 0x410EE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_925 0x410EE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_926 0x410EE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_927 0x410EE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_928 0x410EE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_929 0x410EE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_930 0x410EE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_931 0x410EE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_932 0x410EE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_933 0x410EE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_934 0x410EE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_935 0x410EE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_936 0x410EEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_937 0x410EEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_938 0x410EEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_939 0x410EEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_940 0x410EEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_941 0x410EEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_942 0x410EEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_943 0x410EEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_944 0x410EEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_945 0x410EEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_946 0x410EEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_947 0x410EECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_948 0x410EED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_949 0x410EED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_950 0x410EED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_951 0x410EEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_952 0x410EEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_953 0x410EEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_954 0x410EEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_955 0x410EEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_956 0x410EEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_957 0x410EEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_958 0x410EEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_959 0x410EEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_960 0x410EF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_961 0x410EF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_962 0x410EF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_963 0x410EF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_964 0x410EF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_965 0x410EF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_966 0x410EF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_967 0x410EF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_968 0x410EF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_969 0x410EF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_970 0x410EF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_971 0x410EF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_972 0x410EF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_973 0x410EF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_974 0x410EF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_975 0x410EF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_976 0x410EF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_977 0x410EF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_978 0x410EF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_979 0x410EF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_980 0x410EF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_981 0x410EF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_982 0x410EF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_983 0x410EF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_984 0x410EF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_985 0x410EF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_986 0x410EF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_987 0x410EF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_988 0x410EF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_989 0x410EF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_990 0x410EF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_991 0x410EF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_992 0x410EF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_993 0x410EF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_994 0x410EF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_995 0x410EF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_996 0x410EF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_997 0x410EF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_998 0x410EF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_999 0x410EF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1000 0x410EFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1001 0x410EFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1002 0x410EFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1003 0x410EFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1004 0x410EFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1005 0x410EFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1006 0x410EFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1007 0x410EFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1008 0x410EFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1009 0x410EFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1010 0x410EFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1011 0x410EFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1012 0x410EFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1013 0x410EFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1014 0x410EFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1015 0x410EFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1016 0x410EFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1017 0x410EFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1018 0x410EFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1019 0x410EFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1020 0x410EFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1021 0x410EFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1022 0x410EFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1023 0x410EFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1024 0x410F000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1025 0x410F004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1026 0x410F008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1027 0x410F00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1028 0x410F010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1029 0x410F014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1030 0x410F018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1031 0x410F01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1032 0x410F020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1033 0x410F024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1034 0x410F028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1035 0x410F02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1036 0x410F030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1037 0x410F034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1038 0x410F038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1039 0x410F03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1040 0x410F040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1041 0x410F044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1042 0x410F048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1043 0x410F04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1044 0x410F050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1045 0x410F054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1046 0x410F058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1047 0x410F05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1048 0x410F060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1049 0x410F064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1050 0x410F068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1051 0x410F06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1052 0x410F070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1053 0x410F074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1054 0x410F078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1055 0x410F07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1056 0x410F080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1057 0x410F084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1058 0x410F088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1059 0x410F08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1060 0x410F090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1061 0x410F094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1062 0x410F098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1063 0x410F09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1064 0x410F0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1065 0x410F0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1066 0x410F0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1067 0x410F0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1068 0x410F0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1069 0x410F0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1070 0x410F0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1071 0x410F0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1072 0x410F0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1073 0x410F0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1074 0x410F0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1075 0x410F0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1076 0x410F0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1077 0x410F0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1078 0x410F0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1079 0x410F0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1080 0x410F0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1081 0x410F0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1082 0x410F0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1083 0x410F0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1084 0x410F0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1085 0x410F0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1086 0x410F0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1087 0x410F0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1088 0x410F100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1089 0x410F104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1090 0x410F108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1091 0x410F10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1092 0x410F110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1093 0x410F114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1094 0x410F118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1095 0x410F11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1096 0x410F120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1097 0x410F124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1098 0x410F128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1099 0x410F12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1100 0x410F130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1101 0x410F134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1102 0x410F138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1103 0x410F13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1104 0x410F140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1105 0x410F144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1106 0x410F148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1107 0x410F14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1108 0x410F150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1109 0x410F154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1110 0x410F158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1111 0x410F15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1112 0x410F160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1113 0x410F164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1114 0x410F168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1115 0x410F16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1116 0x410F170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1117 0x410F174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1118 0x410F178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1119 0x410F17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1120 0x410F180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1121 0x410F184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1122 0x410F188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1123 0x410F18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1124 0x410F190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1125 0x410F194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1126 0x410F198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1127 0x410F19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1128 0x410F1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1129 0x410F1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1130 0x410F1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1131 0x410F1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1132 0x410F1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1133 0x410F1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1134 0x410F1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1135 0x410F1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1136 0x410F1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1137 0x410F1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1138 0x410F1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1139 0x410F1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1140 0x410F1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1141 0x410F1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1142 0x410F1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1143 0x410F1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1144 0x410F1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1145 0x410F1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1146 0x410F1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1147 0x410F1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1148 0x410F1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1149 0x410F1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1150 0x410F1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1151 0x410F1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1152 0x410F200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1153 0x410F204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1154 0x410F208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1155 0x410F20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1156 0x410F210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1157 0x410F214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1158 0x410F218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1159 0x410F21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1160 0x410F220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1161 0x410F224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1162 0x410F228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1163 0x410F22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1164 0x410F230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1165 0x410F234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1166 0x410F238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1167 0x410F23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1168 0x410F240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1169 0x410F244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1170 0x410F248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1171 0x410F24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1172 0x410F250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1173 0x410F254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1174 0x410F258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1175 0x410F25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1176 0x410F260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1177 0x410F264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1178 0x410F268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1179 0x410F26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1180 0x410F270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1181 0x410F274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1182 0x410F278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1183 0x410F27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1184 0x410F280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1185 0x410F284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1186 0x410F288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1187 0x410F28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1188 0x410F290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1189 0x410F294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1190 0x410F298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1191 0x410F29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1192 0x410F2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1193 0x410F2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1194 0x410F2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1195 0x410F2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1196 0x410F2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1197 0x410F2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1198 0x410F2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1199 0x410F2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1200 0x410F2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1201 0x410F2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1202 0x410F2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1203 0x410F2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1204 0x410F2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1205 0x410F2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1206 0x410F2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1207 0x410F2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1208 0x410F2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1209 0x410F2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1210 0x410F2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1211 0x410F2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1212 0x410F2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1213 0x410F2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1214 0x410F2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1215 0x410F2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1216 0x410F300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1217 0x410F304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1218 0x410F308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1219 0x410F30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1220 0x410F310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1221 0x410F314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1222 0x410F318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1223 0x410F31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1224 0x410F320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1225 0x410F324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1226 0x410F328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1227 0x410F32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1228 0x410F330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1229 0x410F334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1230 0x410F338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1231 0x410F33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1232 0x410F340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1233 0x410F344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1234 0x410F348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1235 0x410F34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1236 0x410F350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1237 0x410F354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1238 0x410F358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1239 0x410F35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1240 0x410F360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1241 0x410F364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1242 0x410F368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1243 0x410F36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1244 0x410F370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1245 0x410F374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1246 0x410F378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1247 0x410F37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1248 0x410F380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1249 0x410F384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1250 0x410F388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1251 0x410F38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1252 0x410F390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1253 0x410F394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1254 0x410F398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1255 0x410F39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1256 0x410F3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1257 0x410F3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1258 0x410F3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1259 0x410F3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1260 0x410F3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1261 0x410F3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1262 0x410F3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1263 0x410F3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1264 0x410F3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1265 0x410F3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1266 0x410F3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1267 0x410F3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1268 0x410F3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1269 0x410F3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1270 0x410F3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1271 0x410F3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1272 0x410F3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1273 0x410F3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1274 0x410F3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1275 0x410F3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1276 0x410F3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1277 0x410F3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1278 0x410F3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1279 0x410F3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1280 0x410F400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1281 0x410F404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1282 0x410F408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1283 0x410F40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1284 0x410F410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1285 0x410F414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1286 0x410F418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1287 0x410F41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1288 0x410F420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1289 0x410F424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1290 0x410F428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1291 0x410F42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1292 0x410F430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1293 0x410F434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1294 0x410F438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1295 0x410F43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1296 0x410F440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1297 0x410F444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1298 0x410F448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1299 0x410F44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1300 0x410F450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1301 0x410F454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1302 0x410F458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1303 0x410F45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1304 0x410F460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1305 0x410F464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1306 0x410F468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1307 0x410F46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1308 0x410F470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1309 0x410F474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1310 0x410F478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1311 0x410F47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1312 0x410F480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1313 0x410F484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1314 0x410F488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1315 0x410F48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1316 0x410F490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1317 0x410F494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1318 0x410F498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1319 0x410F49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1320 0x410F4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1321 0x410F4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1322 0x410F4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1323 0x410F4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1324 0x410F4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1325 0x410F4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1326 0x410F4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1327 0x410F4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1328 0x410F4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1329 0x410F4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1330 0x410F4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1331 0x410F4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1332 0x410F4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1333 0x410F4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1334 0x410F4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1335 0x410F4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1336 0x410F4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1337 0x410F4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1338 0x410F4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1339 0x410F4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1340 0x410F4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1341 0x410F4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1342 0x410F4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1343 0x410F4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1344 0x410F500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1345 0x410F504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1346 0x410F508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1347 0x410F50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1348 0x410F510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1349 0x410F514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1350 0x410F518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1351 0x410F51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1352 0x410F520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1353 0x410F524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1354 0x410F528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1355 0x410F52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1356 0x410F530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1357 0x410F534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1358 0x410F538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1359 0x410F53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1360 0x410F540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1361 0x410F544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1362 0x410F548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1363 0x410F54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1364 0x410F550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1365 0x410F554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1366 0x410F558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1367 0x410F55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1368 0x410F560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1369 0x410F564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1370 0x410F568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1371 0x410F56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1372 0x410F570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1373 0x410F574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1374 0x410F578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1375 0x410F57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1376 0x410F580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1377 0x410F584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1378 0x410F588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1379 0x410F58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1380 0x410F590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1381 0x410F594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1382 0x410F598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1383 0x410F59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1384 0x410F5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1385 0x410F5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1386 0x410F5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1387 0x410F5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1388 0x410F5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1389 0x410F5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1390 0x410F5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1391 0x410F5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1392 0x410F5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1393 0x410F5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1394 0x410F5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1395 0x410F5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1396 0x410F5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1397 0x410F5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1398 0x410F5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1399 0x410F5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1400 0x410F5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1401 0x410F5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1402 0x410F5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1403 0x410F5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1404 0x410F5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1405 0x410F5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1406 0x410F5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1407 0x410F5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1408 0x410F600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1409 0x410F604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1410 0x410F608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1411 0x410F60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1412 0x410F610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1413 0x410F614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1414 0x410F618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1415 0x410F61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1416 0x410F620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1417 0x410F624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1418 0x410F628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1419 0x410F62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1420 0x410F630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1421 0x410F634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1422 0x410F638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1423 0x410F63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1424 0x410F640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1425 0x410F644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1426 0x410F648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1427 0x410F64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1428 0x410F650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1429 0x410F654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1430 0x410F658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1431 0x410F65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1432 0x410F660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1433 0x410F664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1434 0x410F668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1435 0x410F66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1436 0x410F670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1437 0x410F674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1438 0x410F678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1439 0x410F67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1440 0x410F680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1441 0x410F684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1442 0x410F688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1443 0x410F68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1444 0x410F690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1445 0x410F694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1446 0x410F698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1447 0x410F69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1448 0x410F6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1449 0x410F6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1450 0x410F6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1451 0x410F6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1452 0x410F6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1453 0x410F6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1454 0x410F6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1455 0x410F6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1456 0x410F6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1457 0x410F6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1458 0x410F6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1459 0x410F6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1460 0x410F6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1461 0x410F6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1462 0x410F6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1463 0x410F6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1464 0x410F6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1465 0x410F6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1466 0x410F6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1467 0x410F6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1468 0x410F6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1469 0x410F6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1470 0x410F6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1471 0x410F6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1472 0x410F700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1473 0x410F704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1474 0x410F708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1475 0x410F70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1476 0x410F710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1477 0x410F714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1478 0x410F718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1479 0x410F71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1480 0x410F720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1481 0x410F724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1482 0x410F728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1483 0x410F72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1484 0x410F730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1485 0x410F734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1486 0x410F738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1487 0x410F73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1488 0x410F740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1489 0x410F744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1490 0x410F748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1491 0x410F74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1492 0x410F750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1493 0x410F754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1494 0x410F758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1495 0x410F75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1496 0x410F760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1497 0x410F764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1498 0x410F768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1499 0x410F76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1500 0x410F770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1501 0x410F774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1502 0x410F778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1503 0x410F77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1504 0x410F780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1505 0x410F784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1506 0x410F788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1507 0x410F78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1508 0x410F790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1509 0x410F794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1510 0x410F798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1511 0x410F79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1512 0x410F7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1513 0x410F7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1514 0x410F7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1515 0x410F7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1516 0x410F7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1517 0x410F7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1518 0x410F7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1519 0x410F7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1520 0x410F7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1521 0x410F7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1522 0x410F7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1523 0x410F7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1524 0x410F7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1525 0x410F7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1526 0x410F7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1527 0x410F7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1528 0x410F7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1529 0x410F7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1530 0x410F7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1531 0x410F7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1532 0x410F7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1533 0x410F7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1534 0x410F7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1535 0x410F7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1536 0x410F800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1537 0x410F804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1538 0x410F808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1539 0x410F80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1540 0x410F810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1541 0x410F814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1542 0x410F818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1543 0x410F81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1544 0x410F820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1545 0x410F824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1546 0x410F828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1547 0x410F82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1548 0x410F830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1549 0x410F834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1550 0x410F838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1551 0x410F83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1552 0x410F840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1553 0x410F844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1554 0x410F848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1555 0x410F84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1556 0x410F850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1557 0x410F854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1558 0x410F858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1559 0x410F85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1560 0x410F860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1561 0x410F864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1562 0x410F868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1563 0x410F86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1564 0x410F870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1565 0x410F874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1566 0x410F878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1567 0x410F87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1568 0x410F880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1569 0x410F884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1570 0x410F888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1571 0x410F88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1572 0x410F890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1573 0x410F894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1574 0x410F898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1575 0x410F89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1576 0x410F8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1577 0x410F8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1578 0x410F8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1579 0x410F8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1580 0x410F8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1581 0x410F8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1582 0x410F8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1583 0x410F8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1584 0x410F8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1585 0x410F8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1586 0x410F8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1587 0x410F8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1588 0x410F8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1589 0x410F8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1590 0x410F8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1591 0x410F8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1592 0x410F8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1593 0x410F8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1594 0x410F8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1595 0x410F8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1596 0x410F8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1597 0x410F8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1598 0x410F8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1599 0x410F8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1600 0x410F900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1601 0x410F904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1602 0x410F908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1603 0x410F90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1604 0x410F910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1605 0x410F914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1606 0x410F918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1607 0x410F91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1608 0x410F920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1609 0x410F924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1610 0x410F928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1611 0x410F92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1612 0x410F930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1613 0x410F934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1614 0x410F938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1615 0x410F93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1616 0x410F940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1617 0x410F944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1618 0x410F948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1619 0x410F94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1620 0x410F950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1621 0x410F954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1622 0x410F958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1623 0x410F95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1624 0x410F960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1625 0x410F964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1626 0x410F968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1627 0x410F96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1628 0x410F970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1629 0x410F974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1630 0x410F978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1631 0x410F97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1632 0x410F980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1633 0x410F984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1634 0x410F988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1635 0x410F98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1636 0x410F990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1637 0x410F994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1638 0x410F998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1639 0x410F99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1640 0x410F9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1641 0x410F9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1642 0x410F9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1643 0x410F9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1644 0x410F9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1645 0x410F9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1646 0x410F9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1647 0x410F9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1648 0x410F9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1649 0x410F9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1650 0x410F9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1651 0x410F9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1652 0x410F9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1653 0x410F9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1654 0x410F9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1655 0x410F9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1656 0x410F9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1657 0x410F9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1658 0x410F9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1659 0x410F9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1660 0x410F9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1661 0x410F9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1662 0x410F9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1663 0x410F9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1664 0x410FA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1665 0x410FA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1666 0x410FA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1667 0x410FA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1668 0x410FA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1669 0x410FA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1670 0x410FA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1671 0x410FA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1672 0x410FA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1673 0x410FA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1674 0x410FA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1675 0x410FA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1676 0x410FA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1677 0x410FA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1678 0x410FA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1679 0x410FA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1680 0x410FA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1681 0x410FA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1682 0x410FA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1683 0x410FA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1684 0x410FA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1685 0x410FA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1686 0x410FA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1687 0x410FA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1688 0x410FA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1689 0x410FA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1690 0x410FA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1691 0x410FA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1692 0x410FA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1693 0x410FA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1694 0x410FA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1695 0x410FA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1696 0x410FA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1697 0x410FA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1698 0x410FA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1699 0x410FA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1700 0x410FA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1701 0x410FA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1702 0x410FA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1703 0x410FA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1704 0x410FAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1705 0x410FAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1706 0x410FAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1707 0x410FAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1708 0x410FAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1709 0x410FAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1710 0x410FAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1711 0x410FABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1712 0x410FAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1713 0x410FAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1714 0x410FAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1715 0x410FACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1716 0x410FAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1717 0x410FAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1718 0x410FAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1719 0x410FADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1720 0x410FAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1721 0x410FAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1722 0x410FAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1723 0x410FAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1724 0x410FAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1725 0x410FAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1726 0x410FAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1727 0x410FAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1728 0x410FB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1729 0x410FB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1730 0x410FB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1731 0x410FB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1732 0x410FB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1733 0x410FB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1734 0x410FB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1735 0x410FB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1736 0x410FB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1737 0x410FB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1738 0x410FB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1739 0x410FB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1740 0x410FB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1741 0x410FB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1742 0x410FB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1743 0x410FB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1744 0x410FB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1745 0x410FB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1746 0x410FB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1747 0x410FB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1748 0x410FB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1749 0x410FB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1750 0x410FB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1751 0x410FB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1752 0x410FB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1753 0x410FB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1754 0x410FB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1755 0x410FB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1756 0x410FB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1757 0x410FB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1758 0x410FB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1759 0x410FB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1760 0x410FB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1761 0x410FB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1762 0x410FB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1763 0x410FB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1764 0x410FB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1765 0x410FB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1766 0x410FB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1767 0x410FB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1768 0x410FBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1769 0x410FBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1770 0x410FBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1771 0x410FBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1772 0x410FBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1773 0x410FBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1774 0x410FBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1775 0x410FBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1776 0x410FBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1777 0x410FBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1778 0x410FBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1779 0x410FBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1780 0x410FBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1781 0x410FBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1782 0x410FBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1783 0x410FBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1784 0x410FBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1785 0x410FBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1786 0x410FBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1787 0x410FBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1788 0x410FBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1789 0x410FBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1790 0x410FBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1791 0x410FBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1792 0x410FC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1793 0x410FC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1794 0x410FC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1795 0x410FC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1796 0x410FC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1797 0x410FC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1798 0x410FC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1799 0x410FC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1800 0x410FC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1801 0x410FC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1802 0x410FC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1803 0x410FC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1804 0x410FC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1805 0x410FC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1806 0x410FC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1807 0x410FC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1808 0x410FC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1809 0x410FC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1810 0x410FC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1811 0x410FC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1812 0x410FC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1813 0x410FC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1814 0x410FC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1815 0x410FC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1816 0x410FC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1817 0x410FC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1818 0x410FC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1819 0x410FC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1820 0x410FC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1821 0x410FC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1822 0x410FC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1823 0x410FC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1824 0x410FC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1825 0x410FC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1826 0x410FC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1827 0x410FC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1828 0x410FC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1829 0x410FC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1830 0x410FC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1831 0x410FC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1832 0x410FCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1833 0x410FCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1834 0x410FCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1835 0x410FCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1836 0x410FCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1837 0x410FCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1838 0x410FCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1839 0x410FCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1840 0x410FCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1841 0x410FCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1842 0x410FCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1843 0x410FCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1844 0x410FCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1845 0x410FCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1846 0x410FCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1847 0x410FCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1848 0x410FCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1849 0x410FCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1850 0x410FCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1851 0x410FCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1852 0x410FCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1853 0x410FCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1854 0x410FCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1855 0x410FCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1856 0x410FD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1857 0x410FD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1858 0x410FD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1859 0x410FD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1860 0x410FD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1861 0x410FD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1862 0x410FD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1863 0x410FD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1864 0x410FD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1865 0x410FD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1866 0x410FD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1867 0x410FD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1868 0x410FD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1869 0x410FD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1870 0x410FD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1871 0x410FD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1872 0x410FD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1873 0x410FD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1874 0x410FD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1875 0x410FD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1876 0x410FD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1877 0x410FD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1878 0x410FD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1879 0x410FD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1880 0x410FD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1881 0x410FD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1882 0x410FD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1883 0x410FD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1884 0x410FD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1885 0x410FD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1886 0x410FD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1887 0x410FD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1888 0x410FD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1889 0x410FD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1890 0x410FD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1891 0x410FD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1892 0x410FD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1893 0x410FD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1894 0x410FD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1895 0x410FD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1896 0x410FDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1897 0x410FDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1898 0x410FDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1899 0x410FDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1900 0x410FDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1901 0x410FDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1902 0x410FDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1903 0x410FDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1904 0x410FDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1905 0x410FDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1906 0x410FDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1907 0x410FDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1908 0x410FDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1909 0x410FDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1910 0x410FDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1911 0x410FDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1912 0x410FDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1913 0x410FDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1914 0x410FDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1915 0x410FDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1916 0x410FDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1917 0x410FDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1918 0x410FDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1919 0x410FDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1920 0x410FE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1921 0x410FE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1922 0x410FE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1923 0x410FE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1924 0x410FE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1925 0x410FE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1926 0x410FE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1927 0x410FE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1928 0x410FE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1929 0x410FE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1930 0x410FE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1931 0x410FE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1932 0x410FE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1933 0x410FE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1934 0x410FE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1935 0x410FE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1936 0x410FE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1937 0x410FE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1938 0x410FE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1939 0x410FE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1940 0x410FE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1941 0x410FE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1942 0x410FE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1943 0x410FE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1944 0x410FE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1945 0x410FE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1946 0x410FE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1947 0x410FE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1948 0x410FE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1949 0x410FE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1950 0x410FE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1951 0x410FE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1952 0x410FE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1953 0x410FE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1954 0x410FE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1955 0x410FE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1956 0x410FE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1957 0x410FE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1958 0x410FE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1959 0x410FE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1960 0x410FEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1961 0x410FEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1962 0x410FEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1963 0x410FEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1964 0x410FEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1965 0x410FEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1966 0x410FEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1967 0x410FEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1968 0x410FEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1969 0x410FEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1970 0x410FEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1971 0x410FECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1972 0x410FED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1973 0x410FED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1974 0x410FED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1975 0x410FEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1976 0x410FEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1977 0x410FEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1978 0x410FEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1979 0x410FEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1980 0x410FEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1981 0x410FEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1982 0x410FEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1983 0x410FEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1984 0x410FF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1985 0x410FF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1986 0x410FF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1987 0x410FF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1988 0x410FF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1989 0x410FF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1990 0x410FF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1991 0x410FF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1992 0x410FF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1993 0x410FF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1994 0x410FF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1995 0x410FF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1996 0x410FF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1997 0x410FF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1998 0x410FF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1999 0x410FF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2000 0x410FF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2001 0x410FF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2002 0x410FF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2003 0x410FF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2004 0x410FF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2005 0x410FF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2006 0x410FF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2007 0x410FF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2008 0x410FF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2009 0x410FF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2010 0x410FF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2011 0x410FF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2012 0x410FF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2013 0x410FF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2014 0x410FF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2015 0x410FF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2016 0x410FF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2017 0x410FF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2018 0x410FF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2019 0x410FF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2020 0x410FF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2021 0x410FF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2022 0x410FF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2023 0x410FF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2024 0x410FFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2025 0x410FFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2026 0x410FFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2027 0x410FFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2028 0x410FFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2029 0x410FFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2030 0x410FFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2031 0x410FFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2032 0x410FFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2033 0x410FFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2034 0x410FFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2035 0x410FFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2036 0x410FFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2037 0x410FFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2038 0x410FFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2039 0x410FFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2040 0x410FFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2041 0x410FFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2042 0x410FFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2043 0x410FFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2044 0x410FFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2045 0x410FFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2046 0x410FFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2047 0x410FFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 0x4110000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1 0x4110004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2 0x4110008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_3 0x411000C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_4 0x4110010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_5 0x4110014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_6 0x4110018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_7 0x411001C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_8 0x4110020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_9 0x4110024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_10 0x4110028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_11 0x411002C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_12 0x4110030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_13 0x4110034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_14 0x4110038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_15 0x411003C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_16 0x4110040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_17 0x4110044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_18 0x4110048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_19 0x411004C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_20 0x4110050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_21 0x4110054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_22 0x4110058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_23 0x411005C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_24 0x4110060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_25 0x4110064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_26 0x4110068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_27 0x411006C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_28 0x4110070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_29 0x4110074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_30 0x4110078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_31 0x411007C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_32 0x4110080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_33 0x4110084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_34 0x4110088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_35 0x411008C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_36 0x4110090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_37 0x4110094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_38 0x4110098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_39 0x411009C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_40 0x41100A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_41 0x41100A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_42 0x41100A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_43 0x41100AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_44 0x41100B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_45 0x41100B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_46 0x41100B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_47 0x41100BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_48 0x41100C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_49 0x41100C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_50 0x41100C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_51 0x41100CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_52 0x41100D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_53 0x41100D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_54 0x41100D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_55 0x41100DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_56 0x41100E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_57 0x41100E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_58 0x41100E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_59 0x41100EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_60 0x41100F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_61 0x41100F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_62 0x41100F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_63 0x41100FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_64 0x4110100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_65 0x4110104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_66 0x4110108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_67 0x411010C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_68 0x4110110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_69 0x4110114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_70 0x4110118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_71 0x411011C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_72 0x4110120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_73 0x4110124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_74 0x4110128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_75 0x411012C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_76 0x4110130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_77 0x4110134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_78 0x4110138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_79 0x411013C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_80 0x4110140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_81 0x4110144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_82 0x4110148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_83 0x411014C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_84 0x4110150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_85 0x4110154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_86 0x4110158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_87 0x411015C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_88 0x4110160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_89 0x4110164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_90 0x4110168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_91 0x411016C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_92 0x4110170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_93 0x4110174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_94 0x4110178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_95 0x411017C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_96 0x4110180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_97 0x4110184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_98 0x4110188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_99 0x411018C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_100 0x4110190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_101 0x4110194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_102 0x4110198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_103 0x411019C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_104 0x41101A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_105 0x41101A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_106 0x41101A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_107 0x41101AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_108 0x41101B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_109 0x41101B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_110 0x41101B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_111 0x41101BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_112 0x41101C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_113 0x41101C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_114 0x41101C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_115 0x41101CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_116 0x41101D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_117 0x41101D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_118 0x41101D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_119 0x41101DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_120 0x41101E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_121 0x41101E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_122 0x41101E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_123 0x41101EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_124 0x41101F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_125 0x41101F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_126 0x41101F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_127 0x41101FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_128 0x4110200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_129 0x4110204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_130 0x4110208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_131 0x411020C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_132 0x4110210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_133 0x4110214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_134 0x4110218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_135 0x411021C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_136 0x4110220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_137 0x4110224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_138 0x4110228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_139 0x411022C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_140 0x4110230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_141 0x4110234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_142 0x4110238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_143 0x411023C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_144 0x4110240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_145 0x4110244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_146 0x4110248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_147 0x411024C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_148 0x4110250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_149 0x4110254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_150 0x4110258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_151 0x411025C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_152 0x4110260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_153 0x4110264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_154 0x4110268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_155 0x411026C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_156 0x4110270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_157 0x4110274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_158 0x4110278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_159 0x411027C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_160 0x4110280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_161 0x4110284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_162 0x4110288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_163 0x411028C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_164 0x4110290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_165 0x4110294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_166 0x4110298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_167 0x411029C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_168 0x41102A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_169 0x41102A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_170 0x41102A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_171 0x41102AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_172 0x41102B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_173 0x41102B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_174 0x41102B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_175 0x41102BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_176 0x41102C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_177 0x41102C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_178 0x41102C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_179 0x41102CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_180 0x41102D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_181 0x41102D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_182 0x41102D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_183 0x41102DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_184 0x41102E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_185 0x41102E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_186 0x41102E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_187 0x41102EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_188 0x41102F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_189 0x41102F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_190 0x41102F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_191 0x41102FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_192 0x4110300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_193 0x4110304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_194 0x4110308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_195 0x411030C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_196 0x4110310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_197 0x4110314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_198 0x4110318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_199 0x411031C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_200 0x4110320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_201 0x4110324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_202 0x4110328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_203 0x411032C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_204 0x4110330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_205 0x4110334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_206 0x4110338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_207 0x411033C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_208 0x4110340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_209 0x4110344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_210 0x4110348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_211 0x411034C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_212 0x4110350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_213 0x4110354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_214 0x4110358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_215 0x411035C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_216 0x4110360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_217 0x4110364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_218 0x4110368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_219 0x411036C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_220 0x4110370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_221 0x4110374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_222 0x4110378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_223 0x411037C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_224 0x4110380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_225 0x4110384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_226 0x4110388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_227 0x411038C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_228 0x4110390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_229 0x4110394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_230 0x4110398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_231 0x411039C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_232 0x41103A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_233 0x41103A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_234 0x41103A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_235 0x41103AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_236 0x41103B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_237 0x41103B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_238 0x41103B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_239 0x41103BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_240 0x41103C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_241 0x41103C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_242 0x41103C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_243 0x41103CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_244 0x41103D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_245 0x41103D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_246 0x41103D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_247 0x41103DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_248 0x41103E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_249 0x41103E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_250 0x41103E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_251 0x41103EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_252 0x41103F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_253 0x41103F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_254 0x41103F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_255 0x41103FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_256 0x4110400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_257 0x4110404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_258 0x4110408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_259 0x411040C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_260 0x4110410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_261 0x4110414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_262 0x4110418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_263 0x411041C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_264 0x4110420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_265 0x4110424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_266 0x4110428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_267 0x411042C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_268 0x4110430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_269 0x4110434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_270 0x4110438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_271 0x411043C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_272 0x4110440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_273 0x4110444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_274 0x4110448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_275 0x411044C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_276 0x4110450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_277 0x4110454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_278 0x4110458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_279 0x411045C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_280 0x4110460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_281 0x4110464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_282 0x4110468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_283 0x411046C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_284 0x4110470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_285 0x4110474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_286 0x4110478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_287 0x411047C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_288 0x4110480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_289 0x4110484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_290 0x4110488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_291 0x411048C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_292 0x4110490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_293 0x4110494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_294 0x4110498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_295 0x411049C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_296 0x41104A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_297 0x41104A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_298 0x41104A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_299 0x41104AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_300 0x41104B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_301 0x41104B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_302 0x41104B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_303 0x41104BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_304 0x41104C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_305 0x41104C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_306 0x41104C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_307 0x41104CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_308 0x41104D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_309 0x41104D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_310 0x41104D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_311 0x41104DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_312 0x41104E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_313 0x41104E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_314 0x41104E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_315 0x41104EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_316 0x41104F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_317 0x41104F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_318 0x41104F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_319 0x41104FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_320 0x4110500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_321 0x4110504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_322 0x4110508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_323 0x411050C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_324 0x4110510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_325 0x4110514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_326 0x4110518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_327 0x411051C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_328 0x4110520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_329 0x4110524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_330 0x4110528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_331 0x411052C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_332 0x4110530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_333 0x4110534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_334 0x4110538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_335 0x411053C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_336 0x4110540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_337 0x4110544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_338 0x4110548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_339 0x411054C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_340 0x4110550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_341 0x4110554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_342 0x4110558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_343 0x411055C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_344 0x4110560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_345 0x4110564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_346 0x4110568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_347 0x411056C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_348 0x4110570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_349 0x4110574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_350 0x4110578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_351 0x411057C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_352 0x4110580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_353 0x4110584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_354 0x4110588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_355 0x411058C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_356 0x4110590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_357 0x4110594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_358 0x4110598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_359 0x411059C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_360 0x41105A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_361 0x41105A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_362 0x41105A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_363 0x41105AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_364 0x41105B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_365 0x41105B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_366 0x41105B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_367 0x41105BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_368 0x41105C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_369 0x41105C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_370 0x41105C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_371 0x41105CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_372 0x41105D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_373 0x41105D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_374 0x41105D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_375 0x41105DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_376 0x41105E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_377 0x41105E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_378 0x41105E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_379 0x41105EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_380 0x41105F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_381 0x41105F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_382 0x41105F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_383 0x41105FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_384 0x4110600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_385 0x4110604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_386 0x4110608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_387 0x411060C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_388 0x4110610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_389 0x4110614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_390 0x4110618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_391 0x411061C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_392 0x4110620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_393 0x4110624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_394 0x4110628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_395 0x411062C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_396 0x4110630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_397 0x4110634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_398 0x4110638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_399 0x411063C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_400 0x4110640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_401 0x4110644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_402 0x4110648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_403 0x411064C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_404 0x4110650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_405 0x4110654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_406 0x4110658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_407 0x411065C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_408 0x4110660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_409 0x4110664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_410 0x4110668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_411 0x411066C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_412 0x4110670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_413 0x4110674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_414 0x4110678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_415 0x411067C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_416 0x4110680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_417 0x4110684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_418 0x4110688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_419 0x411068C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_420 0x4110690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_421 0x4110694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_422 0x4110698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_423 0x411069C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_424 0x41106A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_425 0x41106A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_426 0x41106A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_427 0x41106AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_428 0x41106B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_429 0x41106B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_430 0x41106B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_431 0x41106BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_432 0x41106C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_433 0x41106C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_434 0x41106C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_435 0x41106CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_436 0x41106D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_437 0x41106D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_438 0x41106D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_439 0x41106DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_440 0x41106E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_441 0x41106E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_442 0x41106E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_443 0x41106EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_444 0x41106F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_445 0x41106F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_446 0x41106F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_447 0x41106FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_448 0x4110700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_449 0x4110704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_450 0x4110708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_451 0x411070C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_452 0x4110710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_453 0x4110714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_454 0x4110718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_455 0x411071C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_456 0x4110720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_457 0x4110724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_458 0x4110728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_459 0x411072C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_460 0x4110730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_461 0x4110734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_462 0x4110738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_463 0x411073C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_464 0x4110740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_465 0x4110744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_466 0x4110748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_467 0x411074C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_468 0x4110750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_469 0x4110754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_470 0x4110758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_471 0x411075C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_472 0x4110760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_473 0x4110764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_474 0x4110768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_475 0x411076C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_476 0x4110770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_477 0x4110774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_478 0x4110778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_479 0x411077C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_480 0x4110780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_481 0x4110784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_482 0x4110788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_483 0x411078C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_484 0x4110790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_485 0x4110794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_486 0x4110798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_487 0x411079C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_488 0x41107A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_489 0x41107A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_490 0x41107A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_491 0x41107AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_492 0x41107B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_493 0x41107B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_494 0x41107B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_495 0x41107BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_496 0x41107C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_497 0x41107C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_498 0x41107C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_499 0x41107CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_500 0x41107D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_501 0x41107D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_502 0x41107D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_503 0x41107DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_504 0x41107E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_505 0x41107E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_506 0x41107E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_507 0x41107EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_508 0x41107F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_509 0x41107F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_510 0x41107F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_511 0x41107FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_512 0x4110800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_513 0x4110804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_514 0x4110808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_515 0x411080C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_516 0x4110810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_517 0x4110814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_518 0x4110818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_519 0x411081C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_520 0x4110820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_521 0x4110824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_522 0x4110828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_523 0x411082C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_524 0x4110830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_525 0x4110834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_526 0x4110838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_527 0x411083C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_528 0x4110840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_529 0x4110844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_530 0x4110848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_531 0x411084C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_532 0x4110850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_533 0x4110854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_534 0x4110858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_535 0x411085C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_536 0x4110860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_537 0x4110864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_538 0x4110868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_539 0x411086C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_540 0x4110870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_541 0x4110874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_542 0x4110878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_543 0x411087C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_544 0x4110880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_545 0x4110884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_546 0x4110888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_547 0x411088C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_548 0x4110890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_549 0x4110894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_550 0x4110898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_551 0x411089C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_552 0x41108A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_553 0x41108A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_554 0x41108A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_555 0x41108AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_556 0x41108B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_557 0x41108B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_558 0x41108B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_559 0x41108BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_560 0x41108C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_561 0x41108C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_562 0x41108C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_563 0x41108CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_564 0x41108D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_565 0x41108D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_566 0x41108D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_567 0x41108DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_568 0x41108E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_569 0x41108E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_570 0x41108E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_571 0x41108EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_572 0x41108F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_573 0x41108F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_574 0x41108F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_575 0x41108FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_576 0x4110900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_577 0x4110904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_578 0x4110908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_579 0x411090C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_580 0x4110910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_581 0x4110914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_582 0x4110918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_583 0x411091C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_584 0x4110920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_585 0x4110924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_586 0x4110928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_587 0x411092C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_588 0x4110930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_589 0x4110934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_590 0x4110938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_591 0x411093C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_592 0x4110940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_593 0x4110944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_594 0x4110948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_595 0x411094C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_596 0x4110950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_597 0x4110954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_598 0x4110958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_599 0x411095C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_600 0x4110960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_601 0x4110964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_602 0x4110968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_603 0x411096C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_604 0x4110970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_605 0x4110974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_606 0x4110978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_607 0x411097C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_608 0x4110980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_609 0x4110984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_610 0x4110988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_611 0x411098C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_612 0x4110990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_613 0x4110994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_614 0x4110998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_615 0x411099C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_616 0x41109A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_617 0x41109A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_618 0x41109A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_619 0x41109AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_620 0x41109B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_621 0x41109B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_622 0x41109B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_623 0x41109BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_624 0x41109C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_625 0x41109C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_626 0x41109C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_627 0x41109CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_628 0x41109D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_629 0x41109D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_630 0x41109D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_631 0x41109DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_632 0x41109E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_633 0x41109E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_634 0x41109E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_635 0x41109EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_636 0x41109F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_637 0x41109F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_638 0x41109F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_639 0x41109FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_640 0x4110A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_641 0x4110A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_642 0x4110A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_643 0x4110A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_644 0x4110A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_645 0x4110A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_646 0x4110A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_647 0x4110A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_648 0x4110A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_649 0x4110A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_650 0x4110A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_651 0x4110A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_652 0x4110A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_653 0x4110A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_654 0x4110A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_655 0x4110A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_656 0x4110A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_657 0x4110A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_658 0x4110A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_659 0x4110A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_660 0x4110A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_661 0x4110A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_662 0x4110A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_663 0x4110A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_664 0x4110A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_665 0x4110A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_666 0x4110A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_667 0x4110A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_668 0x4110A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_669 0x4110A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_670 0x4110A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_671 0x4110A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_672 0x4110A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_673 0x4110A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_674 0x4110A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_675 0x4110A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_676 0x4110A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_677 0x4110A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_678 0x4110A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_679 0x4110A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_680 0x4110AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_681 0x4110AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_682 0x4110AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_683 0x4110AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_684 0x4110AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_685 0x4110AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_686 0x4110AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_687 0x4110ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_688 0x4110AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_689 0x4110AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_690 0x4110AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_691 0x4110ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_692 0x4110AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_693 0x4110AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_694 0x4110AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_695 0x4110ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_696 0x4110AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_697 0x4110AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_698 0x4110AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_699 0x4110AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_700 0x4110AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_701 0x4110AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_702 0x4110AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_703 0x4110AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_704 0x4110B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_705 0x4110B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_706 0x4110B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_707 0x4110B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_708 0x4110B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_709 0x4110B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_710 0x4110B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_711 0x4110B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_712 0x4110B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_713 0x4110B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_714 0x4110B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_715 0x4110B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_716 0x4110B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_717 0x4110B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_718 0x4110B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_719 0x4110B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_720 0x4110B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_721 0x4110B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_722 0x4110B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_723 0x4110B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_724 0x4110B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_725 0x4110B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_726 0x4110B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_727 0x4110B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_728 0x4110B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_729 0x4110B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_730 0x4110B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_731 0x4110B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_732 0x4110B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_733 0x4110B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_734 0x4110B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_735 0x4110B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_736 0x4110B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_737 0x4110B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_738 0x4110B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_739 0x4110B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_740 0x4110B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_741 0x4110B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_742 0x4110B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_743 0x4110B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_744 0x4110BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_745 0x4110BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_746 0x4110BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_747 0x4110BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_748 0x4110BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_749 0x4110BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_750 0x4110BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_751 0x4110BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_752 0x4110BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_753 0x4110BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_754 0x4110BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_755 0x4110BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_756 0x4110BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_757 0x4110BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_758 0x4110BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_759 0x4110BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_760 0x4110BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_761 0x4110BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_762 0x4110BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_763 0x4110BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_764 0x4110BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_765 0x4110BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_766 0x4110BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_767 0x4110BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_768 0x4110C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_769 0x4110C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_770 0x4110C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_771 0x4110C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_772 0x4110C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_773 0x4110C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_774 0x4110C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_775 0x4110C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_776 0x4110C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_777 0x4110C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_778 0x4110C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_779 0x4110C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_780 0x4110C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_781 0x4110C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_782 0x4110C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_783 0x4110C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_784 0x4110C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_785 0x4110C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_786 0x4110C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_787 0x4110C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_788 0x4110C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_789 0x4110C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_790 0x4110C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_791 0x4110C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_792 0x4110C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_793 0x4110C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_794 0x4110C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_795 0x4110C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_796 0x4110C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_797 0x4110C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_798 0x4110C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_799 0x4110C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_800 0x4110C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_801 0x4110C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_802 0x4110C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_803 0x4110C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_804 0x4110C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_805 0x4110C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_806 0x4110C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_807 0x4110C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_808 0x4110CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_809 0x4110CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_810 0x4110CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_811 0x4110CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_812 0x4110CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_813 0x4110CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_814 0x4110CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_815 0x4110CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_816 0x4110CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_817 0x4110CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_818 0x4110CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_819 0x4110CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_820 0x4110CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_821 0x4110CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_822 0x4110CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_823 0x4110CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_824 0x4110CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_825 0x4110CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_826 0x4110CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_827 0x4110CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_828 0x4110CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_829 0x4110CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_830 0x4110CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_831 0x4110CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_832 0x4110D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_833 0x4110D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_834 0x4110D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_835 0x4110D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_836 0x4110D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_837 0x4110D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_838 0x4110D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_839 0x4110D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_840 0x4110D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_841 0x4110D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_842 0x4110D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_843 0x4110D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_844 0x4110D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_845 0x4110D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_846 0x4110D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_847 0x4110D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_848 0x4110D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_849 0x4110D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_850 0x4110D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_851 0x4110D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_852 0x4110D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_853 0x4110D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_854 0x4110D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_855 0x4110D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_856 0x4110D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_857 0x4110D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_858 0x4110D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_859 0x4110D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_860 0x4110D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_861 0x4110D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_862 0x4110D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_863 0x4110D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_864 0x4110D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_865 0x4110D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_866 0x4110D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_867 0x4110D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_868 0x4110D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_869 0x4110D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_870 0x4110D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_871 0x4110D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_872 0x4110DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_873 0x4110DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_874 0x4110DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_875 0x4110DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_876 0x4110DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_877 0x4110DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_878 0x4110DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_879 0x4110DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_880 0x4110DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_881 0x4110DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_882 0x4110DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_883 0x4110DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_884 0x4110DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_885 0x4110DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_886 0x4110DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_887 0x4110DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_888 0x4110DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_889 0x4110DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_890 0x4110DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_891 0x4110DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_892 0x4110DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_893 0x4110DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_894 0x4110DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_895 0x4110DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_896 0x4110E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_897 0x4110E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_898 0x4110E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_899 0x4110E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_900 0x4110E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_901 0x4110E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_902 0x4110E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_903 0x4110E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_904 0x4110E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_905 0x4110E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_906 0x4110E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_907 0x4110E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_908 0x4110E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_909 0x4110E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_910 0x4110E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_911 0x4110E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_912 0x4110E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_913 0x4110E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_914 0x4110E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_915 0x4110E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_916 0x4110E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_917 0x4110E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_918 0x4110E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_919 0x4110E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_920 0x4110E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_921 0x4110E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_922 0x4110E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_923 0x4110E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_924 0x4110E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_925 0x4110E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_926 0x4110E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_927 0x4110E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_928 0x4110E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_929 0x4110E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_930 0x4110E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_931 0x4110E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_932 0x4110E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_933 0x4110E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_934 0x4110E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_935 0x4110E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_936 0x4110EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_937 0x4110EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_938 0x4110EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_939 0x4110EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_940 0x4110EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_941 0x4110EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_942 0x4110EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_943 0x4110EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_944 0x4110EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_945 0x4110EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_946 0x4110EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_947 0x4110ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_948 0x4110ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_949 0x4110ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_950 0x4110ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_951 0x4110EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_952 0x4110EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_953 0x4110EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_954 0x4110EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_955 0x4110EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_956 0x4110EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_957 0x4110EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_958 0x4110EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_959 0x4110EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_960 0x4110F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_961 0x4110F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_962 0x4110F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_963 0x4110F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_964 0x4110F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_965 0x4110F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_966 0x4110F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_967 0x4110F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_968 0x4110F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_969 0x4110F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_970 0x4110F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_971 0x4110F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_972 0x4110F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_973 0x4110F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_974 0x4110F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_975 0x4110F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_976 0x4110F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_977 0x4110F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_978 0x4110F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_979 0x4110F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_980 0x4110F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_981 0x4110F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_982 0x4110F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_983 0x4110F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_984 0x4110F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_985 0x4110F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_986 0x4110F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_987 0x4110F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_988 0x4110F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_989 0x4110F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_990 0x4110F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_991 0x4110F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_992 0x4110F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_993 0x4110F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_994 0x4110F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_995 0x4110F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_996 0x4110F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_997 0x4110F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_998 0x4110F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_999 0x4110F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1000 0x4110FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1001 0x4110FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1002 0x4110FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1003 0x4110FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1004 0x4110FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1005 0x4110FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1006 0x4110FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1007 0x4110FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1008 0x4110FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1009 0x4110FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1010 0x4110FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1011 0x4110FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1012 0x4110FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1013 0x4110FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1014 0x4110FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1015 0x4110FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1016 0x4110FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1017 0x4110FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1018 0x4110FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1019 0x4110FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1020 0x4110FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1021 0x4110FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1022 0x4110FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1023 0x4110FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1024 0x4111000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1025 0x4111004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1026 0x4111008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1027 0x411100C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1028 0x4111010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1029 0x4111014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1030 0x4111018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1031 0x411101C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1032 0x4111020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1033 0x4111024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1034 0x4111028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1035 0x411102C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1036 0x4111030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1037 0x4111034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1038 0x4111038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1039 0x411103C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1040 0x4111040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1041 0x4111044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1042 0x4111048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1043 0x411104C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1044 0x4111050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1045 0x4111054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1046 0x4111058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1047 0x411105C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1048 0x4111060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1049 0x4111064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1050 0x4111068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1051 0x411106C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1052 0x4111070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1053 0x4111074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1054 0x4111078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1055 0x411107C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1056 0x4111080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1057 0x4111084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1058 0x4111088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1059 0x411108C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1060 0x4111090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1061 0x4111094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1062 0x4111098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1063 0x411109C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1064 0x41110A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1065 0x41110A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1066 0x41110A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1067 0x41110AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1068 0x41110B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1069 0x41110B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1070 0x41110B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1071 0x41110BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1072 0x41110C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1073 0x41110C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1074 0x41110C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1075 0x41110CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1076 0x41110D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1077 0x41110D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1078 0x41110D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1079 0x41110DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1080 0x41110E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1081 0x41110E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1082 0x41110E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1083 0x41110EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1084 0x41110F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1085 0x41110F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1086 0x41110F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1087 0x41110FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1088 0x4111100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1089 0x4111104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1090 0x4111108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1091 0x411110C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1092 0x4111110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1093 0x4111114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1094 0x4111118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1095 0x411111C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1096 0x4111120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1097 0x4111124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1098 0x4111128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1099 0x411112C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1100 0x4111130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1101 0x4111134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1102 0x4111138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1103 0x411113C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1104 0x4111140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1105 0x4111144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1106 0x4111148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1107 0x411114C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1108 0x4111150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1109 0x4111154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1110 0x4111158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1111 0x411115C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1112 0x4111160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1113 0x4111164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1114 0x4111168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1115 0x411116C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1116 0x4111170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1117 0x4111174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1118 0x4111178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1119 0x411117C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1120 0x4111180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1121 0x4111184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1122 0x4111188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1123 0x411118C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1124 0x4111190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1125 0x4111194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1126 0x4111198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1127 0x411119C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1128 0x41111A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1129 0x41111A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1130 0x41111A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1131 0x41111AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1132 0x41111B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1133 0x41111B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1134 0x41111B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1135 0x41111BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1136 0x41111C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1137 0x41111C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1138 0x41111C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1139 0x41111CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1140 0x41111D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1141 0x41111D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1142 0x41111D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1143 0x41111DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1144 0x41111E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1145 0x41111E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1146 0x41111E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1147 0x41111EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1148 0x41111F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1149 0x41111F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1150 0x41111F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1151 0x41111FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1152 0x4111200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1153 0x4111204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1154 0x4111208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1155 0x411120C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1156 0x4111210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1157 0x4111214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1158 0x4111218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1159 0x411121C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1160 0x4111220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1161 0x4111224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1162 0x4111228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1163 0x411122C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1164 0x4111230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1165 0x4111234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1166 0x4111238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1167 0x411123C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1168 0x4111240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1169 0x4111244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1170 0x4111248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1171 0x411124C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1172 0x4111250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1173 0x4111254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1174 0x4111258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1175 0x411125C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1176 0x4111260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1177 0x4111264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1178 0x4111268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1179 0x411126C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1180 0x4111270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1181 0x4111274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1182 0x4111278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1183 0x411127C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1184 0x4111280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1185 0x4111284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1186 0x4111288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1187 0x411128C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1188 0x4111290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1189 0x4111294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1190 0x4111298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1191 0x411129C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1192 0x41112A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1193 0x41112A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1194 0x41112A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1195 0x41112AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1196 0x41112B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1197 0x41112B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1198 0x41112B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1199 0x41112BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1200 0x41112C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1201 0x41112C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1202 0x41112C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1203 0x41112CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1204 0x41112D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1205 0x41112D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1206 0x41112D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1207 0x41112DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1208 0x41112E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1209 0x41112E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1210 0x41112E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1211 0x41112EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1212 0x41112F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1213 0x41112F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1214 0x41112F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1215 0x41112FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1216 0x4111300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1217 0x4111304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1218 0x4111308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1219 0x411130C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1220 0x4111310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1221 0x4111314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1222 0x4111318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1223 0x411131C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1224 0x4111320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1225 0x4111324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1226 0x4111328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1227 0x411132C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1228 0x4111330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1229 0x4111334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1230 0x4111338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1231 0x411133C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1232 0x4111340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1233 0x4111344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1234 0x4111348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1235 0x411134C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1236 0x4111350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1237 0x4111354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1238 0x4111358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1239 0x411135C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1240 0x4111360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1241 0x4111364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1242 0x4111368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1243 0x411136C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1244 0x4111370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1245 0x4111374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1246 0x4111378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1247 0x411137C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1248 0x4111380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1249 0x4111384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1250 0x4111388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1251 0x411138C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1252 0x4111390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1253 0x4111394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1254 0x4111398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1255 0x411139C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1256 0x41113A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1257 0x41113A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1258 0x41113A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1259 0x41113AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1260 0x41113B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1261 0x41113B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1262 0x41113B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1263 0x41113BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1264 0x41113C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1265 0x41113C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1266 0x41113C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1267 0x41113CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1268 0x41113D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1269 0x41113D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1270 0x41113D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1271 0x41113DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1272 0x41113E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1273 0x41113E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1274 0x41113E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1275 0x41113EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1276 0x41113F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1277 0x41113F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1278 0x41113F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1279 0x41113FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1280 0x4111400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1281 0x4111404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1282 0x4111408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1283 0x411140C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1284 0x4111410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1285 0x4111414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1286 0x4111418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1287 0x411141C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1288 0x4111420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1289 0x4111424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1290 0x4111428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1291 0x411142C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1292 0x4111430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1293 0x4111434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1294 0x4111438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1295 0x411143C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1296 0x4111440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1297 0x4111444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1298 0x4111448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1299 0x411144C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1300 0x4111450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1301 0x4111454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1302 0x4111458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1303 0x411145C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1304 0x4111460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1305 0x4111464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1306 0x4111468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1307 0x411146C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1308 0x4111470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1309 0x4111474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1310 0x4111478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1311 0x411147C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1312 0x4111480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1313 0x4111484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1314 0x4111488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1315 0x411148C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1316 0x4111490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1317 0x4111494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1318 0x4111498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1319 0x411149C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1320 0x41114A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1321 0x41114A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1322 0x41114A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1323 0x41114AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1324 0x41114B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1325 0x41114B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1326 0x41114B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1327 0x41114BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1328 0x41114C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1329 0x41114C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1330 0x41114C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1331 0x41114CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1332 0x41114D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1333 0x41114D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1334 0x41114D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1335 0x41114DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1336 0x41114E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1337 0x41114E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1338 0x41114E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1339 0x41114EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1340 0x41114F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1341 0x41114F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1342 0x41114F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1343 0x41114FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1344 0x4111500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1345 0x4111504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1346 0x4111508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1347 0x411150C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1348 0x4111510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1349 0x4111514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1350 0x4111518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1351 0x411151C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1352 0x4111520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1353 0x4111524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1354 0x4111528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1355 0x411152C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1356 0x4111530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1357 0x4111534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1358 0x4111538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1359 0x411153C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1360 0x4111540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1361 0x4111544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1362 0x4111548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1363 0x411154C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1364 0x4111550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1365 0x4111554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1366 0x4111558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1367 0x411155C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1368 0x4111560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1369 0x4111564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1370 0x4111568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1371 0x411156C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1372 0x4111570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1373 0x4111574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1374 0x4111578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1375 0x411157C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1376 0x4111580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1377 0x4111584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1378 0x4111588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1379 0x411158C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1380 0x4111590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1381 0x4111594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1382 0x4111598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1383 0x411159C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1384 0x41115A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1385 0x41115A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1386 0x41115A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1387 0x41115AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1388 0x41115B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1389 0x41115B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1390 0x41115B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1391 0x41115BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1392 0x41115C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1393 0x41115C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1394 0x41115C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1395 0x41115CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1396 0x41115D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1397 0x41115D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1398 0x41115D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1399 0x41115DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1400 0x41115E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1401 0x41115E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1402 0x41115E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1403 0x41115EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1404 0x41115F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1405 0x41115F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1406 0x41115F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1407 0x41115FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1408 0x4111600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1409 0x4111604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1410 0x4111608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1411 0x411160C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1412 0x4111610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1413 0x4111614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1414 0x4111618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1415 0x411161C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1416 0x4111620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1417 0x4111624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1418 0x4111628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1419 0x411162C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1420 0x4111630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1421 0x4111634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1422 0x4111638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1423 0x411163C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1424 0x4111640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1425 0x4111644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1426 0x4111648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1427 0x411164C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1428 0x4111650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1429 0x4111654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1430 0x4111658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1431 0x411165C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1432 0x4111660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1433 0x4111664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1434 0x4111668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1435 0x411166C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1436 0x4111670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1437 0x4111674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1438 0x4111678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1439 0x411167C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1440 0x4111680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1441 0x4111684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1442 0x4111688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1443 0x411168C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1444 0x4111690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1445 0x4111694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1446 0x4111698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1447 0x411169C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1448 0x41116A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1449 0x41116A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1450 0x41116A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1451 0x41116AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1452 0x41116B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1453 0x41116B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1454 0x41116B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1455 0x41116BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1456 0x41116C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1457 0x41116C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1458 0x41116C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1459 0x41116CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1460 0x41116D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1461 0x41116D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1462 0x41116D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1463 0x41116DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1464 0x41116E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1465 0x41116E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1466 0x41116E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1467 0x41116EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1468 0x41116F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1469 0x41116F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1470 0x41116F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1471 0x41116FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1472 0x4111700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1473 0x4111704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1474 0x4111708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1475 0x411170C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1476 0x4111710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1477 0x4111714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1478 0x4111718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1479 0x411171C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1480 0x4111720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1481 0x4111724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1482 0x4111728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1483 0x411172C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1484 0x4111730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1485 0x4111734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1486 0x4111738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1487 0x411173C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1488 0x4111740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1489 0x4111744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1490 0x4111748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1491 0x411174C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1492 0x4111750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1493 0x4111754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1494 0x4111758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1495 0x411175C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1496 0x4111760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1497 0x4111764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1498 0x4111768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1499 0x411176C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1500 0x4111770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1501 0x4111774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1502 0x4111778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1503 0x411177C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1504 0x4111780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1505 0x4111784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1506 0x4111788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1507 0x411178C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1508 0x4111790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1509 0x4111794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1510 0x4111798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1511 0x411179C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1512 0x41117A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1513 0x41117A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1514 0x41117A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1515 0x41117AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1516 0x41117B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1517 0x41117B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1518 0x41117B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1519 0x41117BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1520 0x41117C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1521 0x41117C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1522 0x41117C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1523 0x41117CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1524 0x41117D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1525 0x41117D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1526 0x41117D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1527 0x41117DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1528 0x41117E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1529 0x41117E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1530 0x41117E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1531 0x41117EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1532 0x41117F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1533 0x41117F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1534 0x41117F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1535 0x41117FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1536 0x4111800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1537 0x4111804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1538 0x4111808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1539 0x411180C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1540 0x4111810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1541 0x4111814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1542 0x4111818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1543 0x411181C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1544 0x4111820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1545 0x4111824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1546 0x4111828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1547 0x411182C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1548 0x4111830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1549 0x4111834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1550 0x4111838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1551 0x411183C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1552 0x4111840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1553 0x4111844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1554 0x4111848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1555 0x411184C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1556 0x4111850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1557 0x4111854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1558 0x4111858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1559 0x411185C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1560 0x4111860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1561 0x4111864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1562 0x4111868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1563 0x411186C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1564 0x4111870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1565 0x4111874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1566 0x4111878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1567 0x411187C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1568 0x4111880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1569 0x4111884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1570 0x4111888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1571 0x411188C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1572 0x4111890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1573 0x4111894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1574 0x4111898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1575 0x411189C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1576 0x41118A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1577 0x41118A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1578 0x41118A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1579 0x41118AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1580 0x41118B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1581 0x41118B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1582 0x41118B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1583 0x41118BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1584 0x41118C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1585 0x41118C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1586 0x41118C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1587 0x41118CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1588 0x41118D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1589 0x41118D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1590 0x41118D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1591 0x41118DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1592 0x41118E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1593 0x41118E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1594 0x41118E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1595 0x41118EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1596 0x41118F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1597 0x41118F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1598 0x41118F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1599 0x41118FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1600 0x4111900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1601 0x4111904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1602 0x4111908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1603 0x411190C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1604 0x4111910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1605 0x4111914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1606 0x4111918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1607 0x411191C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1608 0x4111920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1609 0x4111924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1610 0x4111928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1611 0x411192C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1612 0x4111930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1613 0x4111934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1614 0x4111938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1615 0x411193C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1616 0x4111940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1617 0x4111944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1618 0x4111948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1619 0x411194C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1620 0x4111950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1621 0x4111954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1622 0x4111958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1623 0x411195C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1624 0x4111960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1625 0x4111964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1626 0x4111968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1627 0x411196C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1628 0x4111970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1629 0x4111974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1630 0x4111978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1631 0x411197C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1632 0x4111980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1633 0x4111984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1634 0x4111988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1635 0x411198C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1636 0x4111990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1637 0x4111994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1638 0x4111998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1639 0x411199C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1640 0x41119A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1641 0x41119A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1642 0x41119A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1643 0x41119AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1644 0x41119B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1645 0x41119B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1646 0x41119B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1647 0x41119BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1648 0x41119C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1649 0x41119C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1650 0x41119C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1651 0x41119CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1652 0x41119D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1653 0x41119D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1654 0x41119D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1655 0x41119DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1656 0x41119E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1657 0x41119E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1658 0x41119E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1659 0x41119EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1660 0x41119F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1661 0x41119F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1662 0x41119F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1663 0x41119FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1664 0x4111A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1665 0x4111A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1666 0x4111A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1667 0x4111A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1668 0x4111A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1669 0x4111A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1670 0x4111A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1671 0x4111A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1672 0x4111A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1673 0x4111A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1674 0x4111A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1675 0x4111A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1676 0x4111A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1677 0x4111A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1678 0x4111A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1679 0x4111A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1680 0x4111A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1681 0x4111A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1682 0x4111A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1683 0x4111A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1684 0x4111A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1685 0x4111A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1686 0x4111A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1687 0x4111A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1688 0x4111A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1689 0x4111A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1690 0x4111A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1691 0x4111A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1692 0x4111A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1693 0x4111A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1694 0x4111A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1695 0x4111A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1696 0x4111A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1697 0x4111A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1698 0x4111A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1699 0x4111A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1700 0x4111A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1701 0x4111A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1702 0x4111A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1703 0x4111A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1704 0x4111AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1705 0x4111AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1706 0x4111AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1707 0x4111AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1708 0x4111AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1709 0x4111AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1710 0x4111AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1711 0x4111ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1712 0x4111AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1713 0x4111AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1714 0x4111AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1715 0x4111ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1716 0x4111AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1717 0x4111AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1718 0x4111AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1719 0x4111ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1720 0x4111AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1721 0x4111AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1722 0x4111AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1723 0x4111AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1724 0x4111AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1725 0x4111AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1726 0x4111AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1727 0x4111AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1728 0x4111B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1729 0x4111B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1730 0x4111B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1731 0x4111B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1732 0x4111B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1733 0x4111B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1734 0x4111B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1735 0x4111B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1736 0x4111B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1737 0x4111B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1738 0x4111B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1739 0x4111B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1740 0x4111B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1741 0x4111B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1742 0x4111B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1743 0x4111B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1744 0x4111B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1745 0x4111B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1746 0x4111B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1747 0x4111B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1748 0x4111B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1749 0x4111B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1750 0x4111B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1751 0x4111B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1752 0x4111B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1753 0x4111B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1754 0x4111B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1755 0x4111B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1756 0x4111B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1757 0x4111B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1758 0x4111B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1759 0x4111B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1760 0x4111B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1761 0x4111B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1762 0x4111B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1763 0x4111B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1764 0x4111B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1765 0x4111B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1766 0x4111B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1767 0x4111B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1768 0x4111BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1769 0x4111BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1770 0x4111BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1771 0x4111BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1772 0x4111BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1773 0x4111BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1774 0x4111BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1775 0x4111BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1776 0x4111BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1777 0x4111BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1778 0x4111BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1779 0x4111BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1780 0x4111BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1781 0x4111BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1782 0x4111BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1783 0x4111BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1784 0x4111BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1785 0x4111BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1786 0x4111BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1787 0x4111BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1788 0x4111BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1789 0x4111BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1790 0x4111BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1791 0x4111BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1792 0x4111C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1793 0x4111C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1794 0x4111C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1795 0x4111C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1796 0x4111C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1797 0x4111C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1798 0x4111C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1799 0x4111C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1800 0x4111C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1801 0x4111C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1802 0x4111C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1803 0x4111C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1804 0x4111C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1805 0x4111C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1806 0x4111C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1807 0x4111C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1808 0x4111C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1809 0x4111C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1810 0x4111C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1811 0x4111C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1812 0x4111C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1813 0x4111C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1814 0x4111C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1815 0x4111C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1816 0x4111C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1817 0x4111C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1818 0x4111C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1819 0x4111C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1820 0x4111C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1821 0x4111C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1822 0x4111C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1823 0x4111C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1824 0x4111C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1825 0x4111C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1826 0x4111C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1827 0x4111C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1828 0x4111C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1829 0x4111C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1830 0x4111C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1831 0x4111C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1832 0x4111CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1833 0x4111CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1834 0x4111CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1835 0x4111CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1836 0x4111CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1837 0x4111CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1838 0x4111CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1839 0x4111CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1840 0x4111CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1841 0x4111CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1842 0x4111CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1843 0x4111CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1844 0x4111CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1845 0x4111CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1846 0x4111CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1847 0x4111CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1848 0x4111CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1849 0x4111CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1850 0x4111CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1851 0x4111CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1852 0x4111CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1853 0x4111CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1854 0x4111CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1855 0x4111CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1856 0x4111D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1857 0x4111D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1858 0x4111D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1859 0x4111D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1860 0x4111D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1861 0x4111D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1862 0x4111D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1863 0x4111D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1864 0x4111D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1865 0x4111D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1866 0x4111D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1867 0x4111D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1868 0x4111D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1869 0x4111D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1870 0x4111D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1871 0x4111D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1872 0x4111D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1873 0x4111D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1874 0x4111D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1875 0x4111D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1876 0x4111D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1877 0x4111D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1878 0x4111D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1879 0x4111D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1880 0x4111D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1881 0x4111D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1882 0x4111D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1883 0x4111D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1884 0x4111D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1885 0x4111D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1886 0x4111D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1887 0x4111D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1888 0x4111D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1889 0x4111D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1890 0x4111D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1891 0x4111D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1892 0x4111D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1893 0x4111D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1894 0x4111D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1895 0x4111D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1896 0x4111DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1897 0x4111DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1898 0x4111DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1899 0x4111DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1900 0x4111DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1901 0x4111DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1902 0x4111DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1903 0x4111DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1904 0x4111DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1905 0x4111DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1906 0x4111DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1907 0x4111DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1908 0x4111DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1909 0x4111DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1910 0x4111DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1911 0x4111DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1912 0x4111DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1913 0x4111DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1914 0x4111DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1915 0x4111DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1916 0x4111DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1917 0x4111DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1918 0x4111DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1919 0x4111DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1920 0x4111E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1921 0x4111E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1922 0x4111E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1923 0x4111E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1924 0x4111E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1925 0x4111E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1926 0x4111E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1927 0x4111E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1928 0x4111E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1929 0x4111E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1930 0x4111E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1931 0x4111E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1932 0x4111E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1933 0x4111E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1934 0x4111E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1935 0x4111E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1936 0x4111E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1937 0x4111E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1938 0x4111E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1939 0x4111E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1940 0x4111E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1941 0x4111E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1942 0x4111E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1943 0x4111E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1944 0x4111E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1945 0x4111E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1946 0x4111E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1947 0x4111E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1948 0x4111E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1949 0x4111E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1950 0x4111E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1951 0x4111E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1952 0x4111E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1953 0x4111E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1954 0x4111E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1955 0x4111E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1956 0x4111E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1957 0x4111E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1958 0x4111E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1959 0x4111E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1960 0x4111EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1961 0x4111EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1962 0x4111EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1963 0x4111EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1964 0x4111EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1965 0x4111EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1966 0x4111EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1967 0x4111EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1968 0x4111EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1969 0x4111EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1970 0x4111EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1971 0x4111ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1972 0x4111ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1973 0x4111ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1974 0x4111ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1975 0x4111EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1976 0x4111EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1977 0x4111EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1978 0x4111EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1979 0x4111EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1980 0x4111EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1981 0x4111EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1982 0x4111EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1983 0x4111EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1984 0x4111F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1985 0x4111F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1986 0x4111F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1987 0x4111F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1988 0x4111F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1989 0x4111F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1990 0x4111F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1991 0x4111F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1992 0x4111F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1993 0x4111F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1994 0x4111F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1995 0x4111F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1996 0x4111F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1997 0x4111F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1998 0x4111F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1999 0x4111F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2000 0x4111F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2001 0x4111F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2002 0x4111F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2003 0x4111F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2004 0x4111F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2005 0x4111F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2006 0x4111F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2007 0x4111F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2008 0x4111F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2009 0x4111F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2010 0x4111F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2011 0x4111F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2012 0x4111F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2013 0x4111F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2014 0x4111F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2015 0x4111F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2016 0x4111F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2017 0x4111F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2018 0x4111F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2019 0x4111F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2020 0x4111F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2021 0x4111F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2022 0x4111F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2023 0x4111F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2024 0x4111FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2025 0x4111FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2026 0x4111FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2027 0x4111FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2028 0x4111FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2029 0x4111FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2030 0x4111FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2031 0x4111FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2032 0x4111FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2033 0x4111FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2034 0x4111FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2035 0x4111FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2036 0x4111FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2037 0x4111FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2038 0x4111FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2039 0x4111FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2040 0x4111FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2041 0x4111FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2042 0x4111FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2043 0x4111FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2044 0x4111FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2045 0x4111FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2046 0x4111FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2047 0x4111FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 0x4112000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1 0x4112004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2 0x4112008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_3 0x411200C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_4 0x4112010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_5 0x4112014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_6 0x4112018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_7 0x411201C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_8 0x4112020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_9 0x4112024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_10 0x4112028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_11 0x411202C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_12 0x4112030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_13 0x4112034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_14 0x4112038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_15 0x411203C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_16 0x4112040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_17 0x4112044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_18 0x4112048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_19 0x411204C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_20 0x4112050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_21 0x4112054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_22 0x4112058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_23 0x411205C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_24 0x4112060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_25 0x4112064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_26 0x4112068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_27 0x411206C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_28 0x4112070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_29 0x4112074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_30 0x4112078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_31 0x411207C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_32 0x4112080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_33 0x4112084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_34 0x4112088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_35 0x411208C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_36 0x4112090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_37 0x4112094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_38 0x4112098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_39 0x411209C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_40 0x41120A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_41 0x41120A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_42 0x41120A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_43 0x41120AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_44 0x41120B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_45 0x41120B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_46 0x41120B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_47 0x41120BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_48 0x41120C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_49 0x41120C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_50 0x41120C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_51 0x41120CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_52 0x41120D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_53 0x41120D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_54 0x41120D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_55 0x41120DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_56 0x41120E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_57 0x41120E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_58 0x41120E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_59 0x41120EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_60 0x41120F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_61 0x41120F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_62 0x41120F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_63 0x41120FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_64 0x4112100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_65 0x4112104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_66 0x4112108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_67 0x411210C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_68 0x4112110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_69 0x4112114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_70 0x4112118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_71 0x411211C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_72 0x4112120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_73 0x4112124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_74 0x4112128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_75 0x411212C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_76 0x4112130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_77 0x4112134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_78 0x4112138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_79 0x411213C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_80 0x4112140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_81 0x4112144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_82 0x4112148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_83 0x411214C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_84 0x4112150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_85 0x4112154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_86 0x4112158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_87 0x411215C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_88 0x4112160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_89 0x4112164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_90 0x4112168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_91 0x411216C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_92 0x4112170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_93 0x4112174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_94 0x4112178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_95 0x411217C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_96 0x4112180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_97 0x4112184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_98 0x4112188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_99 0x411218C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_100 0x4112190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_101 0x4112194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_102 0x4112198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_103 0x411219C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_104 0x41121A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_105 0x41121A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_106 0x41121A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_107 0x41121AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_108 0x41121B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_109 0x41121B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_110 0x41121B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_111 0x41121BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_112 0x41121C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_113 0x41121C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_114 0x41121C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_115 0x41121CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_116 0x41121D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_117 0x41121D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_118 0x41121D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_119 0x41121DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_120 0x41121E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_121 0x41121E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_122 0x41121E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_123 0x41121EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_124 0x41121F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_125 0x41121F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_126 0x41121F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_127 0x41121FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_128 0x4112200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_129 0x4112204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_130 0x4112208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_131 0x411220C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_132 0x4112210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_133 0x4112214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_134 0x4112218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_135 0x411221C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_136 0x4112220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_137 0x4112224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_138 0x4112228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_139 0x411222C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_140 0x4112230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_141 0x4112234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_142 0x4112238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_143 0x411223C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_144 0x4112240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_145 0x4112244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_146 0x4112248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_147 0x411224C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_148 0x4112250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_149 0x4112254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_150 0x4112258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_151 0x411225C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_152 0x4112260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_153 0x4112264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_154 0x4112268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_155 0x411226C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_156 0x4112270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_157 0x4112274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_158 0x4112278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_159 0x411227C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_160 0x4112280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_161 0x4112284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_162 0x4112288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_163 0x411228C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_164 0x4112290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_165 0x4112294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_166 0x4112298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_167 0x411229C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_168 0x41122A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_169 0x41122A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_170 0x41122A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_171 0x41122AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_172 0x41122B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_173 0x41122B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_174 0x41122B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_175 0x41122BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_176 0x41122C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_177 0x41122C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_178 0x41122C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_179 0x41122CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_180 0x41122D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_181 0x41122D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_182 0x41122D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_183 0x41122DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_184 0x41122E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_185 0x41122E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_186 0x41122E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_187 0x41122EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_188 0x41122F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_189 0x41122F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_190 0x41122F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_191 0x41122FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_192 0x4112300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_193 0x4112304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_194 0x4112308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_195 0x411230C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_196 0x4112310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_197 0x4112314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_198 0x4112318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_199 0x411231C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_200 0x4112320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_201 0x4112324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_202 0x4112328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_203 0x411232C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_204 0x4112330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_205 0x4112334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_206 0x4112338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_207 0x411233C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_208 0x4112340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_209 0x4112344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_210 0x4112348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_211 0x411234C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_212 0x4112350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_213 0x4112354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_214 0x4112358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_215 0x411235C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_216 0x4112360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_217 0x4112364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_218 0x4112368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_219 0x411236C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_220 0x4112370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_221 0x4112374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_222 0x4112378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_223 0x411237C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_224 0x4112380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_225 0x4112384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_226 0x4112388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_227 0x411238C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_228 0x4112390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_229 0x4112394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_230 0x4112398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_231 0x411239C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_232 0x41123A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_233 0x41123A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_234 0x41123A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_235 0x41123AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_236 0x41123B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_237 0x41123B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_238 0x41123B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_239 0x41123BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_240 0x41123C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_241 0x41123C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_242 0x41123C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_243 0x41123CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_244 0x41123D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_245 0x41123D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_246 0x41123D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_247 0x41123DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_248 0x41123E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_249 0x41123E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_250 0x41123E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_251 0x41123EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_252 0x41123F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_253 0x41123F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_254 0x41123F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_255 0x41123FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_256 0x4112400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_257 0x4112404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_258 0x4112408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_259 0x411240C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_260 0x4112410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_261 0x4112414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_262 0x4112418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_263 0x411241C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_264 0x4112420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_265 0x4112424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_266 0x4112428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_267 0x411242C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_268 0x4112430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_269 0x4112434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_270 0x4112438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_271 0x411243C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_272 0x4112440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_273 0x4112444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_274 0x4112448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_275 0x411244C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_276 0x4112450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_277 0x4112454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_278 0x4112458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_279 0x411245C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_280 0x4112460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_281 0x4112464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_282 0x4112468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_283 0x411246C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_284 0x4112470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_285 0x4112474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_286 0x4112478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_287 0x411247C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_288 0x4112480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_289 0x4112484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_290 0x4112488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_291 0x411248C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_292 0x4112490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_293 0x4112494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_294 0x4112498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_295 0x411249C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_296 0x41124A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_297 0x41124A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_298 0x41124A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_299 0x41124AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_300 0x41124B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_301 0x41124B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_302 0x41124B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_303 0x41124BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_304 0x41124C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_305 0x41124C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_306 0x41124C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_307 0x41124CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_308 0x41124D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_309 0x41124D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_310 0x41124D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_311 0x41124DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_312 0x41124E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_313 0x41124E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_314 0x41124E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_315 0x41124EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_316 0x41124F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_317 0x41124F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_318 0x41124F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_319 0x41124FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_320 0x4112500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_321 0x4112504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_322 0x4112508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_323 0x411250C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_324 0x4112510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_325 0x4112514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_326 0x4112518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_327 0x411251C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_328 0x4112520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_329 0x4112524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_330 0x4112528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_331 0x411252C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_332 0x4112530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_333 0x4112534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_334 0x4112538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_335 0x411253C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_336 0x4112540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_337 0x4112544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_338 0x4112548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_339 0x411254C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_340 0x4112550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_341 0x4112554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_342 0x4112558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_343 0x411255C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_344 0x4112560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_345 0x4112564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_346 0x4112568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_347 0x411256C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_348 0x4112570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_349 0x4112574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_350 0x4112578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_351 0x411257C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_352 0x4112580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_353 0x4112584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_354 0x4112588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_355 0x411258C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_356 0x4112590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_357 0x4112594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_358 0x4112598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_359 0x411259C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_360 0x41125A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_361 0x41125A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_362 0x41125A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_363 0x41125AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_364 0x41125B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_365 0x41125B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_366 0x41125B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_367 0x41125BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_368 0x41125C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_369 0x41125C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_370 0x41125C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_371 0x41125CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_372 0x41125D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_373 0x41125D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_374 0x41125D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_375 0x41125DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_376 0x41125E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_377 0x41125E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_378 0x41125E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_379 0x41125EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_380 0x41125F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_381 0x41125F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_382 0x41125F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_383 0x41125FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_384 0x4112600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_385 0x4112604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_386 0x4112608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_387 0x411260C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_388 0x4112610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_389 0x4112614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_390 0x4112618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_391 0x411261C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_392 0x4112620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_393 0x4112624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_394 0x4112628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_395 0x411262C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_396 0x4112630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_397 0x4112634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_398 0x4112638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_399 0x411263C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_400 0x4112640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_401 0x4112644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_402 0x4112648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_403 0x411264C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_404 0x4112650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_405 0x4112654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_406 0x4112658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_407 0x411265C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_408 0x4112660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_409 0x4112664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_410 0x4112668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_411 0x411266C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_412 0x4112670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_413 0x4112674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_414 0x4112678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_415 0x411267C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_416 0x4112680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_417 0x4112684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_418 0x4112688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_419 0x411268C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_420 0x4112690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_421 0x4112694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_422 0x4112698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_423 0x411269C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_424 0x41126A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_425 0x41126A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_426 0x41126A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_427 0x41126AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_428 0x41126B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_429 0x41126B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_430 0x41126B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_431 0x41126BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_432 0x41126C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_433 0x41126C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_434 0x41126C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_435 0x41126CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_436 0x41126D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_437 0x41126D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_438 0x41126D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_439 0x41126DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_440 0x41126E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_441 0x41126E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_442 0x41126E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_443 0x41126EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_444 0x41126F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_445 0x41126F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_446 0x41126F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_447 0x41126FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_448 0x4112700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_449 0x4112704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_450 0x4112708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_451 0x411270C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_452 0x4112710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_453 0x4112714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_454 0x4112718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_455 0x411271C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_456 0x4112720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_457 0x4112724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_458 0x4112728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_459 0x411272C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_460 0x4112730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_461 0x4112734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_462 0x4112738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_463 0x411273C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_464 0x4112740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_465 0x4112744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_466 0x4112748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_467 0x411274C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_468 0x4112750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_469 0x4112754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_470 0x4112758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_471 0x411275C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_472 0x4112760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_473 0x4112764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_474 0x4112768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_475 0x411276C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_476 0x4112770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_477 0x4112774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_478 0x4112778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_479 0x411277C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_480 0x4112780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_481 0x4112784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_482 0x4112788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_483 0x411278C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_484 0x4112790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_485 0x4112794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_486 0x4112798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_487 0x411279C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_488 0x41127A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_489 0x41127A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_490 0x41127A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_491 0x41127AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_492 0x41127B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_493 0x41127B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_494 0x41127B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_495 0x41127BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_496 0x41127C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_497 0x41127C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_498 0x41127C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_499 0x41127CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_500 0x41127D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_501 0x41127D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_502 0x41127D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_503 0x41127DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_504 0x41127E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_505 0x41127E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_506 0x41127E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_507 0x41127EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_508 0x41127F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_509 0x41127F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_510 0x41127F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_511 0x41127FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_512 0x4112800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_513 0x4112804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_514 0x4112808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_515 0x411280C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_516 0x4112810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_517 0x4112814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_518 0x4112818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_519 0x411281C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_520 0x4112820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_521 0x4112824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_522 0x4112828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_523 0x411282C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_524 0x4112830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_525 0x4112834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_526 0x4112838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_527 0x411283C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_528 0x4112840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_529 0x4112844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_530 0x4112848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_531 0x411284C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_532 0x4112850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_533 0x4112854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_534 0x4112858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_535 0x411285C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_536 0x4112860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_537 0x4112864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_538 0x4112868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_539 0x411286C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_540 0x4112870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_541 0x4112874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_542 0x4112878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_543 0x411287C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_544 0x4112880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_545 0x4112884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_546 0x4112888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_547 0x411288C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_548 0x4112890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_549 0x4112894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_550 0x4112898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_551 0x411289C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_552 0x41128A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_553 0x41128A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_554 0x41128A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_555 0x41128AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_556 0x41128B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_557 0x41128B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_558 0x41128B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_559 0x41128BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_560 0x41128C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_561 0x41128C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_562 0x41128C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_563 0x41128CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_564 0x41128D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_565 0x41128D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_566 0x41128D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_567 0x41128DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_568 0x41128E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_569 0x41128E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_570 0x41128E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_571 0x41128EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_572 0x41128F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_573 0x41128F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_574 0x41128F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_575 0x41128FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_576 0x4112900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_577 0x4112904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_578 0x4112908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_579 0x411290C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_580 0x4112910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_581 0x4112914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_582 0x4112918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_583 0x411291C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_584 0x4112920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_585 0x4112924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_586 0x4112928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_587 0x411292C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_588 0x4112930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_589 0x4112934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_590 0x4112938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_591 0x411293C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_592 0x4112940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_593 0x4112944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_594 0x4112948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_595 0x411294C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_596 0x4112950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_597 0x4112954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_598 0x4112958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_599 0x411295C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_600 0x4112960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_601 0x4112964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_602 0x4112968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_603 0x411296C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_604 0x4112970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_605 0x4112974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_606 0x4112978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_607 0x411297C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_608 0x4112980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_609 0x4112984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_610 0x4112988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_611 0x411298C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_612 0x4112990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_613 0x4112994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_614 0x4112998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_615 0x411299C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_616 0x41129A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_617 0x41129A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_618 0x41129A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_619 0x41129AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_620 0x41129B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_621 0x41129B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_622 0x41129B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_623 0x41129BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_624 0x41129C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_625 0x41129C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_626 0x41129C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_627 0x41129CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_628 0x41129D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_629 0x41129D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_630 0x41129D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_631 0x41129DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_632 0x41129E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_633 0x41129E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_634 0x41129E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_635 0x41129EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_636 0x41129F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_637 0x41129F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_638 0x41129F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_639 0x41129FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_640 0x4112A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_641 0x4112A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_642 0x4112A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_643 0x4112A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_644 0x4112A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_645 0x4112A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_646 0x4112A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_647 0x4112A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_648 0x4112A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_649 0x4112A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_650 0x4112A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_651 0x4112A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_652 0x4112A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_653 0x4112A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_654 0x4112A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_655 0x4112A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_656 0x4112A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_657 0x4112A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_658 0x4112A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_659 0x4112A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_660 0x4112A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_661 0x4112A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_662 0x4112A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_663 0x4112A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_664 0x4112A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_665 0x4112A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_666 0x4112A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_667 0x4112A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_668 0x4112A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_669 0x4112A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_670 0x4112A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_671 0x4112A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_672 0x4112A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_673 0x4112A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_674 0x4112A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_675 0x4112A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_676 0x4112A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_677 0x4112A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_678 0x4112A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_679 0x4112A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_680 0x4112AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_681 0x4112AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_682 0x4112AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_683 0x4112AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_684 0x4112AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_685 0x4112AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_686 0x4112AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_687 0x4112ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_688 0x4112AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_689 0x4112AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_690 0x4112AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_691 0x4112ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_692 0x4112AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_693 0x4112AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_694 0x4112AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_695 0x4112ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_696 0x4112AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_697 0x4112AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_698 0x4112AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_699 0x4112AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_700 0x4112AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_701 0x4112AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_702 0x4112AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_703 0x4112AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_704 0x4112B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_705 0x4112B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_706 0x4112B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_707 0x4112B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_708 0x4112B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_709 0x4112B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_710 0x4112B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_711 0x4112B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_712 0x4112B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_713 0x4112B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_714 0x4112B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_715 0x4112B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_716 0x4112B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_717 0x4112B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_718 0x4112B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_719 0x4112B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_720 0x4112B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_721 0x4112B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_722 0x4112B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_723 0x4112B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_724 0x4112B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_725 0x4112B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_726 0x4112B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_727 0x4112B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_728 0x4112B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_729 0x4112B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_730 0x4112B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_731 0x4112B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_732 0x4112B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_733 0x4112B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_734 0x4112B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_735 0x4112B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_736 0x4112B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_737 0x4112B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_738 0x4112B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_739 0x4112B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_740 0x4112B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_741 0x4112B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_742 0x4112B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_743 0x4112B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_744 0x4112BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_745 0x4112BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_746 0x4112BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_747 0x4112BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_748 0x4112BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_749 0x4112BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_750 0x4112BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_751 0x4112BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_752 0x4112BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_753 0x4112BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_754 0x4112BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_755 0x4112BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_756 0x4112BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_757 0x4112BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_758 0x4112BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_759 0x4112BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_760 0x4112BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_761 0x4112BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_762 0x4112BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_763 0x4112BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_764 0x4112BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_765 0x4112BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_766 0x4112BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_767 0x4112BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_768 0x4112C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_769 0x4112C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_770 0x4112C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_771 0x4112C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_772 0x4112C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_773 0x4112C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_774 0x4112C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_775 0x4112C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_776 0x4112C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_777 0x4112C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_778 0x4112C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_779 0x4112C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_780 0x4112C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_781 0x4112C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_782 0x4112C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_783 0x4112C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_784 0x4112C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_785 0x4112C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_786 0x4112C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_787 0x4112C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_788 0x4112C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_789 0x4112C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_790 0x4112C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_791 0x4112C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_792 0x4112C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_793 0x4112C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_794 0x4112C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_795 0x4112C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_796 0x4112C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_797 0x4112C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_798 0x4112C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_799 0x4112C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_800 0x4112C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_801 0x4112C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_802 0x4112C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_803 0x4112C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_804 0x4112C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_805 0x4112C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_806 0x4112C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_807 0x4112C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_808 0x4112CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_809 0x4112CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_810 0x4112CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_811 0x4112CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_812 0x4112CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_813 0x4112CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_814 0x4112CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_815 0x4112CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_816 0x4112CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_817 0x4112CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_818 0x4112CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_819 0x4112CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_820 0x4112CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_821 0x4112CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_822 0x4112CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_823 0x4112CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_824 0x4112CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_825 0x4112CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_826 0x4112CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_827 0x4112CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_828 0x4112CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_829 0x4112CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_830 0x4112CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_831 0x4112CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_832 0x4112D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_833 0x4112D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_834 0x4112D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_835 0x4112D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_836 0x4112D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_837 0x4112D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_838 0x4112D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_839 0x4112D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_840 0x4112D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_841 0x4112D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_842 0x4112D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_843 0x4112D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_844 0x4112D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_845 0x4112D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_846 0x4112D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_847 0x4112D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_848 0x4112D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_849 0x4112D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_850 0x4112D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_851 0x4112D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_852 0x4112D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_853 0x4112D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_854 0x4112D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_855 0x4112D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_856 0x4112D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_857 0x4112D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_858 0x4112D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_859 0x4112D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_860 0x4112D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_861 0x4112D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_862 0x4112D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_863 0x4112D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_864 0x4112D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_865 0x4112D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_866 0x4112D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_867 0x4112D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_868 0x4112D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_869 0x4112D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_870 0x4112D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_871 0x4112D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_872 0x4112DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_873 0x4112DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_874 0x4112DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_875 0x4112DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_876 0x4112DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_877 0x4112DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_878 0x4112DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_879 0x4112DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_880 0x4112DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_881 0x4112DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_882 0x4112DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_883 0x4112DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_884 0x4112DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_885 0x4112DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_886 0x4112DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_887 0x4112DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_888 0x4112DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_889 0x4112DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_890 0x4112DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_891 0x4112DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_892 0x4112DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_893 0x4112DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_894 0x4112DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_895 0x4112DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_896 0x4112E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_897 0x4112E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_898 0x4112E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_899 0x4112E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_900 0x4112E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_901 0x4112E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_902 0x4112E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_903 0x4112E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_904 0x4112E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_905 0x4112E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_906 0x4112E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_907 0x4112E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_908 0x4112E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_909 0x4112E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_910 0x4112E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_911 0x4112E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_912 0x4112E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_913 0x4112E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_914 0x4112E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_915 0x4112E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_916 0x4112E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_917 0x4112E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_918 0x4112E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_919 0x4112E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_920 0x4112E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_921 0x4112E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_922 0x4112E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_923 0x4112E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_924 0x4112E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_925 0x4112E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_926 0x4112E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_927 0x4112E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_928 0x4112E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_929 0x4112E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_930 0x4112E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_931 0x4112E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_932 0x4112E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_933 0x4112E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_934 0x4112E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_935 0x4112E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_936 0x4112EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_937 0x4112EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_938 0x4112EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_939 0x4112EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_940 0x4112EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_941 0x4112EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_942 0x4112EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_943 0x4112EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_944 0x4112EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_945 0x4112EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_946 0x4112EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_947 0x4112ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_948 0x4112ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_949 0x4112ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_950 0x4112ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_951 0x4112EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_952 0x4112EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_953 0x4112EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_954 0x4112EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_955 0x4112EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_956 0x4112EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_957 0x4112EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_958 0x4112EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_959 0x4112EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_960 0x4112F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_961 0x4112F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_962 0x4112F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_963 0x4112F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_964 0x4112F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_965 0x4112F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_966 0x4112F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_967 0x4112F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_968 0x4112F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_969 0x4112F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_970 0x4112F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_971 0x4112F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_972 0x4112F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_973 0x4112F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_974 0x4112F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_975 0x4112F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_976 0x4112F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_977 0x4112F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_978 0x4112F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_979 0x4112F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_980 0x4112F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_981 0x4112F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_982 0x4112F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_983 0x4112F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_984 0x4112F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_985 0x4112F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_986 0x4112F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_987 0x4112F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_988 0x4112F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_989 0x4112F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_990 0x4112F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_991 0x4112F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_992 0x4112F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_993 0x4112F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_994 0x4112F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_995 0x4112F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_996 0x4112F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_997 0x4112F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_998 0x4112F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_999 0x4112F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1000 0x4112FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1001 0x4112FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1002 0x4112FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1003 0x4112FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1004 0x4112FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1005 0x4112FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1006 0x4112FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1007 0x4112FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1008 0x4112FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1009 0x4112FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1010 0x4112FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1011 0x4112FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1012 0x4112FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1013 0x4112FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1014 0x4112FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1015 0x4112FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1016 0x4112FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1017 0x4112FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1018 0x4112FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1019 0x4112FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1020 0x4112FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1021 0x4112FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1022 0x4112FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1023 0x4112FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1024 0x4113000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1025 0x4113004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1026 0x4113008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1027 0x411300C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1028 0x4113010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1029 0x4113014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1030 0x4113018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1031 0x411301C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1032 0x4113020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1033 0x4113024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1034 0x4113028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1035 0x411302C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1036 0x4113030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1037 0x4113034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1038 0x4113038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1039 0x411303C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1040 0x4113040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1041 0x4113044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1042 0x4113048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1043 0x411304C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1044 0x4113050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1045 0x4113054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1046 0x4113058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1047 0x411305C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1048 0x4113060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1049 0x4113064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1050 0x4113068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1051 0x411306C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1052 0x4113070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1053 0x4113074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1054 0x4113078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1055 0x411307C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1056 0x4113080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1057 0x4113084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1058 0x4113088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1059 0x411308C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1060 0x4113090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1061 0x4113094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1062 0x4113098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1063 0x411309C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1064 0x41130A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1065 0x41130A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1066 0x41130A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1067 0x41130AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1068 0x41130B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1069 0x41130B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1070 0x41130B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1071 0x41130BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1072 0x41130C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1073 0x41130C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1074 0x41130C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1075 0x41130CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1076 0x41130D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1077 0x41130D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1078 0x41130D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1079 0x41130DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1080 0x41130E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1081 0x41130E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1082 0x41130E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1083 0x41130EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1084 0x41130F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1085 0x41130F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1086 0x41130F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1087 0x41130FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1088 0x4113100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1089 0x4113104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1090 0x4113108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1091 0x411310C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1092 0x4113110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1093 0x4113114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1094 0x4113118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1095 0x411311C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1096 0x4113120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1097 0x4113124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1098 0x4113128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1099 0x411312C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1100 0x4113130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1101 0x4113134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1102 0x4113138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1103 0x411313C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1104 0x4113140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1105 0x4113144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1106 0x4113148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1107 0x411314C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1108 0x4113150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1109 0x4113154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1110 0x4113158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1111 0x411315C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1112 0x4113160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1113 0x4113164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1114 0x4113168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1115 0x411316C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1116 0x4113170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1117 0x4113174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1118 0x4113178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1119 0x411317C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1120 0x4113180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1121 0x4113184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1122 0x4113188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1123 0x411318C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1124 0x4113190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1125 0x4113194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1126 0x4113198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1127 0x411319C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1128 0x41131A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1129 0x41131A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1130 0x41131A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1131 0x41131AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1132 0x41131B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1133 0x41131B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1134 0x41131B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1135 0x41131BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1136 0x41131C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1137 0x41131C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1138 0x41131C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1139 0x41131CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1140 0x41131D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1141 0x41131D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1142 0x41131D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1143 0x41131DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1144 0x41131E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1145 0x41131E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1146 0x41131E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1147 0x41131EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1148 0x41131F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1149 0x41131F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1150 0x41131F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1151 0x41131FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1152 0x4113200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1153 0x4113204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1154 0x4113208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1155 0x411320C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1156 0x4113210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1157 0x4113214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1158 0x4113218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1159 0x411321C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1160 0x4113220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1161 0x4113224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1162 0x4113228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1163 0x411322C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1164 0x4113230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1165 0x4113234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1166 0x4113238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1167 0x411323C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1168 0x4113240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1169 0x4113244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1170 0x4113248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1171 0x411324C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1172 0x4113250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1173 0x4113254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1174 0x4113258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1175 0x411325C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1176 0x4113260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1177 0x4113264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1178 0x4113268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1179 0x411326C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1180 0x4113270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1181 0x4113274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1182 0x4113278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1183 0x411327C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1184 0x4113280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1185 0x4113284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1186 0x4113288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1187 0x411328C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1188 0x4113290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1189 0x4113294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1190 0x4113298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1191 0x411329C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1192 0x41132A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1193 0x41132A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1194 0x41132A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1195 0x41132AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1196 0x41132B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1197 0x41132B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1198 0x41132B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1199 0x41132BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1200 0x41132C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1201 0x41132C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1202 0x41132C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1203 0x41132CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1204 0x41132D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1205 0x41132D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1206 0x41132D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1207 0x41132DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1208 0x41132E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1209 0x41132E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1210 0x41132E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1211 0x41132EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1212 0x41132F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1213 0x41132F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1214 0x41132F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1215 0x41132FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1216 0x4113300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1217 0x4113304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1218 0x4113308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1219 0x411330C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1220 0x4113310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1221 0x4113314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1222 0x4113318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1223 0x411331C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1224 0x4113320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1225 0x4113324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1226 0x4113328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1227 0x411332C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1228 0x4113330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1229 0x4113334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1230 0x4113338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1231 0x411333C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1232 0x4113340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1233 0x4113344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1234 0x4113348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1235 0x411334C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1236 0x4113350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1237 0x4113354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1238 0x4113358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1239 0x411335C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1240 0x4113360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1241 0x4113364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1242 0x4113368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1243 0x411336C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1244 0x4113370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1245 0x4113374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1246 0x4113378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1247 0x411337C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1248 0x4113380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1249 0x4113384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1250 0x4113388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1251 0x411338C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1252 0x4113390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1253 0x4113394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1254 0x4113398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1255 0x411339C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1256 0x41133A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1257 0x41133A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1258 0x41133A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1259 0x41133AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1260 0x41133B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1261 0x41133B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1262 0x41133B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1263 0x41133BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1264 0x41133C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1265 0x41133C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1266 0x41133C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1267 0x41133CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1268 0x41133D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1269 0x41133D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1270 0x41133D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1271 0x41133DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1272 0x41133E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1273 0x41133E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1274 0x41133E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1275 0x41133EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1276 0x41133F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1277 0x41133F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1278 0x41133F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1279 0x41133FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1280 0x4113400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1281 0x4113404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1282 0x4113408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1283 0x411340C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1284 0x4113410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1285 0x4113414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1286 0x4113418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1287 0x411341C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1288 0x4113420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1289 0x4113424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1290 0x4113428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1291 0x411342C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1292 0x4113430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1293 0x4113434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1294 0x4113438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1295 0x411343C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1296 0x4113440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1297 0x4113444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1298 0x4113448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1299 0x411344C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1300 0x4113450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1301 0x4113454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1302 0x4113458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1303 0x411345C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1304 0x4113460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1305 0x4113464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1306 0x4113468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1307 0x411346C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1308 0x4113470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1309 0x4113474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1310 0x4113478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1311 0x411347C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1312 0x4113480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1313 0x4113484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1314 0x4113488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1315 0x411348C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1316 0x4113490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1317 0x4113494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1318 0x4113498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1319 0x411349C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1320 0x41134A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1321 0x41134A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1322 0x41134A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1323 0x41134AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1324 0x41134B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1325 0x41134B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1326 0x41134B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1327 0x41134BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1328 0x41134C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1329 0x41134C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1330 0x41134C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1331 0x41134CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1332 0x41134D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1333 0x41134D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1334 0x41134D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1335 0x41134DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1336 0x41134E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1337 0x41134E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1338 0x41134E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1339 0x41134EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1340 0x41134F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1341 0x41134F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1342 0x41134F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1343 0x41134FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1344 0x4113500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1345 0x4113504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1346 0x4113508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1347 0x411350C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1348 0x4113510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1349 0x4113514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1350 0x4113518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1351 0x411351C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1352 0x4113520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1353 0x4113524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1354 0x4113528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1355 0x411352C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1356 0x4113530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1357 0x4113534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1358 0x4113538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1359 0x411353C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1360 0x4113540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1361 0x4113544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1362 0x4113548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1363 0x411354C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1364 0x4113550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1365 0x4113554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1366 0x4113558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1367 0x411355C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1368 0x4113560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1369 0x4113564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1370 0x4113568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1371 0x411356C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1372 0x4113570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1373 0x4113574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1374 0x4113578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1375 0x411357C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1376 0x4113580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1377 0x4113584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1378 0x4113588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1379 0x411358C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1380 0x4113590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1381 0x4113594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1382 0x4113598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1383 0x411359C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1384 0x41135A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1385 0x41135A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1386 0x41135A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1387 0x41135AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1388 0x41135B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1389 0x41135B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1390 0x41135B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1391 0x41135BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1392 0x41135C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1393 0x41135C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1394 0x41135C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1395 0x41135CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1396 0x41135D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1397 0x41135D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1398 0x41135D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1399 0x41135DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1400 0x41135E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1401 0x41135E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1402 0x41135E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1403 0x41135EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1404 0x41135F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1405 0x41135F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1406 0x41135F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1407 0x41135FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1408 0x4113600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1409 0x4113604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1410 0x4113608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1411 0x411360C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1412 0x4113610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1413 0x4113614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1414 0x4113618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1415 0x411361C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1416 0x4113620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1417 0x4113624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1418 0x4113628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1419 0x411362C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1420 0x4113630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1421 0x4113634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1422 0x4113638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1423 0x411363C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1424 0x4113640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1425 0x4113644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1426 0x4113648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1427 0x411364C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1428 0x4113650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1429 0x4113654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1430 0x4113658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1431 0x411365C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1432 0x4113660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1433 0x4113664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1434 0x4113668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1435 0x411366C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1436 0x4113670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1437 0x4113674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1438 0x4113678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1439 0x411367C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1440 0x4113680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1441 0x4113684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1442 0x4113688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1443 0x411368C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1444 0x4113690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1445 0x4113694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1446 0x4113698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1447 0x411369C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1448 0x41136A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1449 0x41136A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1450 0x41136A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1451 0x41136AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1452 0x41136B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1453 0x41136B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1454 0x41136B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1455 0x41136BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1456 0x41136C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1457 0x41136C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1458 0x41136C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1459 0x41136CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1460 0x41136D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1461 0x41136D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1462 0x41136D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1463 0x41136DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1464 0x41136E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1465 0x41136E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1466 0x41136E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1467 0x41136EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1468 0x41136F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1469 0x41136F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1470 0x41136F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1471 0x41136FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1472 0x4113700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1473 0x4113704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1474 0x4113708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1475 0x411370C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1476 0x4113710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1477 0x4113714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1478 0x4113718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1479 0x411371C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1480 0x4113720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1481 0x4113724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1482 0x4113728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1483 0x411372C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1484 0x4113730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1485 0x4113734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1486 0x4113738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1487 0x411373C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1488 0x4113740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1489 0x4113744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1490 0x4113748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1491 0x411374C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1492 0x4113750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1493 0x4113754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1494 0x4113758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1495 0x411375C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1496 0x4113760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1497 0x4113764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1498 0x4113768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1499 0x411376C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1500 0x4113770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1501 0x4113774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1502 0x4113778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1503 0x411377C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1504 0x4113780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1505 0x4113784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1506 0x4113788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1507 0x411378C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1508 0x4113790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1509 0x4113794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1510 0x4113798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1511 0x411379C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1512 0x41137A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1513 0x41137A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1514 0x41137A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1515 0x41137AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1516 0x41137B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1517 0x41137B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1518 0x41137B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1519 0x41137BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1520 0x41137C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1521 0x41137C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1522 0x41137C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1523 0x41137CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1524 0x41137D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1525 0x41137D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1526 0x41137D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1527 0x41137DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1528 0x41137E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1529 0x41137E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1530 0x41137E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1531 0x41137EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1532 0x41137F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1533 0x41137F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1534 0x41137F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1535 0x41137FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1536 0x4113800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1537 0x4113804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1538 0x4113808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1539 0x411380C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1540 0x4113810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1541 0x4113814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1542 0x4113818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1543 0x411381C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1544 0x4113820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1545 0x4113824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1546 0x4113828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1547 0x411382C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1548 0x4113830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1549 0x4113834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1550 0x4113838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1551 0x411383C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1552 0x4113840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1553 0x4113844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1554 0x4113848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1555 0x411384C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1556 0x4113850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1557 0x4113854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1558 0x4113858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1559 0x411385C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1560 0x4113860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1561 0x4113864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1562 0x4113868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1563 0x411386C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1564 0x4113870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1565 0x4113874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1566 0x4113878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1567 0x411387C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1568 0x4113880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1569 0x4113884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1570 0x4113888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1571 0x411388C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1572 0x4113890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1573 0x4113894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1574 0x4113898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1575 0x411389C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1576 0x41138A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1577 0x41138A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1578 0x41138A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1579 0x41138AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1580 0x41138B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1581 0x41138B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1582 0x41138B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1583 0x41138BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1584 0x41138C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1585 0x41138C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1586 0x41138C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1587 0x41138CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1588 0x41138D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1589 0x41138D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1590 0x41138D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1591 0x41138DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1592 0x41138E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1593 0x41138E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1594 0x41138E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1595 0x41138EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1596 0x41138F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1597 0x41138F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1598 0x41138F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1599 0x41138FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1600 0x4113900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1601 0x4113904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1602 0x4113908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1603 0x411390C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1604 0x4113910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1605 0x4113914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1606 0x4113918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1607 0x411391C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1608 0x4113920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1609 0x4113924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1610 0x4113928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1611 0x411392C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1612 0x4113930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1613 0x4113934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1614 0x4113938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1615 0x411393C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1616 0x4113940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1617 0x4113944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1618 0x4113948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1619 0x411394C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1620 0x4113950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1621 0x4113954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1622 0x4113958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1623 0x411395C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1624 0x4113960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1625 0x4113964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1626 0x4113968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1627 0x411396C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1628 0x4113970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1629 0x4113974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1630 0x4113978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1631 0x411397C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1632 0x4113980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1633 0x4113984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1634 0x4113988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1635 0x411398C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1636 0x4113990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1637 0x4113994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1638 0x4113998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1639 0x411399C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1640 0x41139A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1641 0x41139A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1642 0x41139A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1643 0x41139AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1644 0x41139B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1645 0x41139B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1646 0x41139B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1647 0x41139BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1648 0x41139C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1649 0x41139C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1650 0x41139C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1651 0x41139CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1652 0x41139D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1653 0x41139D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1654 0x41139D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1655 0x41139DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1656 0x41139E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1657 0x41139E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1658 0x41139E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1659 0x41139EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1660 0x41139F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1661 0x41139F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1662 0x41139F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1663 0x41139FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1664 0x4113A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1665 0x4113A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1666 0x4113A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1667 0x4113A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1668 0x4113A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1669 0x4113A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1670 0x4113A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1671 0x4113A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1672 0x4113A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1673 0x4113A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1674 0x4113A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1675 0x4113A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1676 0x4113A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1677 0x4113A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1678 0x4113A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1679 0x4113A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1680 0x4113A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1681 0x4113A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1682 0x4113A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1683 0x4113A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1684 0x4113A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1685 0x4113A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1686 0x4113A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1687 0x4113A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1688 0x4113A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1689 0x4113A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1690 0x4113A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1691 0x4113A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1692 0x4113A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1693 0x4113A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1694 0x4113A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1695 0x4113A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1696 0x4113A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1697 0x4113A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1698 0x4113A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1699 0x4113A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1700 0x4113A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1701 0x4113A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1702 0x4113A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1703 0x4113A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1704 0x4113AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1705 0x4113AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1706 0x4113AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1707 0x4113AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1708 0x4113AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1709 0x4113AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1710 0x4113AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1711 0x4113ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1712 0x4113AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1713 0x4113AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1714 0x4113AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1715 0x4113ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1716 0x4113AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1717 0x4113AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1718 0x4113AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1719 0x4113ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1720 0x4113AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1721 0x4113AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1722 0x4113AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1723 0x4113AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1724 0x4113AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1725 0x4113AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1726 0x4113AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1727 0x4113AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1728 0x4113B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1729 0x4113B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1730 0x4113B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1731 0x4113B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1732 0x4113B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1733 0x4113B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1734 0x4113B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1735 0x4113B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1736 0x4113B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1737 0x4113B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1738 0x4113B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1739 0x4113B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1740 0x4113B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1741 0x4113B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1742 0x4113B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1743 0x4113B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1744 0x4113B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1745 0x4113B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1746 0x4113B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1747 0x4113B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1748 0x4113B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1749 0x4113B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1750 0x4113B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1751 0x4113B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1752 0x4113B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1753 0x4113B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1754 0x4113B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1755 0x4113B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1756 0x4113B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1757 0x4113B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1758 0x4113B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1759 0x4113B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1760 0x4113B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1761 0x4113B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1762 0x4113B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1763 0x4113B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1764 0x4113B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1765 0x4113B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1766 0x4113B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1767 0x4113B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1768 0x4113BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1769 0x4113BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1770 0x4113BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1771 0x4113BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1772 0x4113BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1773 0x4113BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1774 0x4113BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1775 0x4113BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1776 0x4113BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1777 0x4113BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1778 0x4113BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1779 0x4113BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1780 0x4113BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1781 0x4113BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1782 0x4113BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1783 0x4113BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1784 0x4113BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1785 0x4113BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1786 0x4113BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1787 0x4113BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1788 0x4113BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1789 0x4113BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1790 0x4113BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1791 0x4113BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1792 0x4113C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1793 0x4113C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1794 0x4113C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1795 0x4113C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1796 0x4113C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1797 0x4113C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1798 0x4113C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1799 0x4113C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1800 0x4113C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1801 0x4113C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1802 0x4113C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1803 0x4113C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1804 0x4113C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1805 0x4113C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1806 0x4113C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1807 0x4113C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1808 0x4113C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1809 0x4113C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1810 0x4113C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1811 0x4113C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1812 0x4113C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1813 0x4113C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1814 0x4113C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1815 0x4113C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1816 0x4113C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1817 0x4113C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1818 0x4113C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1819 0x4113C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1820 0x4113C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1821 0x4113C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1822 0x4113C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1823 0x4113C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1824 0x4113C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1825 0x4113C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1826 0x4113C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1827 0x4113C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1828 0x4113C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1829 0x4113C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1830 0x4113C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1831 0x4113C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1832 0x4113CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1833 0x4113CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1834 0x4113CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1835 0x4113CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1836 0x4113CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1837 0x4113CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1838 0x4113CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1839 0x4113CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1840 0x4113CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1841 0x4113CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1842 0x4113CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1843 0x4113CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1844 0x4113CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1845 0x4113CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1846 0x4113CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1847 0x4113CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1848 0x4113CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1849 0x4113CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1850 0x4113CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1851 0x4113CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1852 0x4113CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1853 0x4113CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1854 0x4113CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1855 0x4113CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1856 0x4113D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1857 0x4113D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1858 0x4113D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1859 0x4113D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1860 0x4113D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1861 0x4113D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1862 0x4113D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1863 0x4113D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1864 0x4113D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1865 0x4113D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1866 0x4113D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1867 0x4113D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1868 0x4113D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1869 0x4113D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1870 0x4113D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1871 0x4113D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1872 0x4113D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1873 0x4113D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1874 0x4113D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1875 0x4113D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1876 0x4113D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1877 0x4113D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1878 0x4113D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1879 0x4113D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1880 0x4113D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1881 0x4113D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1882 0x4113D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1883 0x4113D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1884 0x4113D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1885 0x4113D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1886 0x4113D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1887 0x4113D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1888 0x4113D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1889 0x4113D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1890 0x4113D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1891 0x4113D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1892 0x4113D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1893 0x4113D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1894 0x4113D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1895 0x4113D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1896 0x4113DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1897 0x4113DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1898 0x4113DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1899 0x4113DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1900 0x4113DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1901 0x4113DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1902 0x4113DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1903 0x4113DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1904 0x4113DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1905 0x4113DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1906 0x4113DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1907 0x4113DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1908 0x4113DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1909 0x4113DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1910 0x4113DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1911 0x4113DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1912 0x4113DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1913 0x4113DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1914 0x4113DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1915 0x4113DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1916 0x4113DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1917 0x4113DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1918 0x4113DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1919 0x4113DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1920 0x4113E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1921 0x4113E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1922 0x4113E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1923 0x4113E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1924 0x4113E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1925 0x4113E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1926 0x4113E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1927 0x4113E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1928 0x4113E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1929 0x4113E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1930 0x4113E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1931 0x4113E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1932 0x4113E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1933 0x4113E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1934 0x4113E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1935 0x4113E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1936 0x4113E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1937 0x4113E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1938 0x4113E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1939 0x4113E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1940 0x4113E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1941 0x4113E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1942 0x4113E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1943 0x4113E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1944 0x4113E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1945 0x4113E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1946 0x4113E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1947 0x4113E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1948 0x4113E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1949 0x4113E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1950 0x4113E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1951 0x4113E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1952 0x4113E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1953 0x4113E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1954 0x4113E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1955 0x4113E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1956 0x4113E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1957 0x4113E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1958 0x4113E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1959 0x4113E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1960 0x4113EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1961 0x4113EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1962 0x4113EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1963 0x4113EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1964 0x4113EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1965 0x4113EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1966 0x4113EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1967 0x4113EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1968 0x4113EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1969 0x4113EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1970 0x4113EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1971 0x4113ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1972 0x4113ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1973 0x4113ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1974 0x4113ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1975 0x4113EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1976 0x4113EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1977 0x4113EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1978 0x4113EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1979 0x4113EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1980 0x4113EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1981 0x4113EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1982 0x4113EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1983 0x4113EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1984 0x4113F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1985 0x4113F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1986 0x4113F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1987 0x4113F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1988 0x4113F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1989 0x4113F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1990 0x4113F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1991 0x4113F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1992 0x4113F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1993 0x4113F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1994 0x4113F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1995 0x4113F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1996 0x4113F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1997 0x4113F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1998 0x4113F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1999 0x4113F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2000 0x4113F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2001 0x4113F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2002 0x4113F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2003 0x4113F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2004 0x4113F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2005 0x4113F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2006 0x4113F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2007 0x4113F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2008 0x4113F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2009 0x4113F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2010 0x4113F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2011 0x4113F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2012 0x4113F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2013 0x4113F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2014 0x4113F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2015 0x4113F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2016 0x4113F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2017 0x4113F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2018 0x4113F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2019 0x4113F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2020 0x4113F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2021 0x4113F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2022 0x4113F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2023 0x4113F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2024 0x4113FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2025 0x4113FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2026 0x4113FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2027 0x4113FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2028 0x4113FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2029 0x4113FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2030 0x4113FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2031 0x4113FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2032 0x4113FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2033 0x4113FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2034 0x4113FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2035 0x4113FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2036 0x4113FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2037 0x4113FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2038 0x4113FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2039 0x4113FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2040 0x4113FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2041 0x4113FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2042 0x4113FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2043 0x4113FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2044 0x4113FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2045 0x4113FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2046 0x4113FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 0x4113FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 0x4114000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_1 0x4114004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_2 0x4114008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_3 0x411400C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_4 0x4114010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_5 0x4114014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_6 0x4114018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_7 0x411401C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_8 0x4114020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_9 0x4114024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_10 0x4114028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_11 0x411402C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_12 0x4114030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_13 0x4114034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_14 0x4114038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_15 0x411403C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_16 0x4114040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_17 0x4114044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_18 0x4114048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_19 0x411404C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_20 0x4114050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_21 0x4114054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_22 0x4114058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_23 0x411405C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_24 0x4114060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_25 0x4114064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_26 0x4114068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_27 0x411406C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_28 0x4114070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_29 0x4114074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_30 0x4114078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_31 0x411407C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_32 0x4114080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_33 0x4114084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_34 0x4114088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_35 0x411408C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_36 0x4114090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_37 0x4114094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_38 0x4114098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_39 0x411409C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_40 0x41140A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_41 0x41140A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_42 0x41140A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_43 0x41140AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_44 0x41140B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_45 0x41140B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_46 0x41140B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_47 0x41140BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_48 0x41140C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_49 0x41140C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_50 0x41140C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_51 0x41140CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_52 0x41140D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_53 0x41140D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_54 0x41140D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_55 0x41140DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_56 0x41140E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_57 0x41140E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_58 0x41140E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_59 0x41140EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_60 0x41140F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_61 0x41140F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_62 0x41140F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_63 0x41140FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_64 0x4114100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_65 0x4114104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_66 0x4114108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_67 0x411410C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_68 0x4114110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_69 0x4114114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_70 0x4114118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_71 0x411411C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_72 0x4114120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_73 0x4114124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_74 0x4114128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_75 0x411412C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_76 0x4114130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_77 0x4114134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_78 0x4114138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_79 0x411413C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_80 0x4114140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_81 0x4114144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_82 0x4114148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_83 0x411414C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_84 0x4114150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_85 0x4114154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_86 0x4114158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_87 0x411415C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_88 0x4114160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_89 0x4114164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_90 0x4114168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_91 0x411416C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_92 0x4114170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_93 0x4114174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_94 0x4114178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_95 0x411417C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_96 0x4114180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_97 0x4114184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_98 0x4114188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_99 0x411418C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_100 0x4114190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_101 0x4114194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_102 0x4114198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_103 0x411419C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_104 0x41141A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_105 0x41141A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_106 0x41141A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_107 0x41141AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_108 0x41141B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_109 0x41141B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_110 0x41141B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_111 0x41141BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_112 0x41141C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_113 0x41141C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_114 0x41141C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_115 0x41141CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_116 0x41141D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_117 0x41141D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_118 0x41141D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_119 0x41141DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_120 0x41141E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_121 0x41141E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_122 0x41141E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_123 0x41141EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_124 0x41141F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_125 0x41141F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_126 0x41141F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_127 0x41141FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_128 0x4114200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_129 0x4114204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_130 0x4114208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_131 0x411420C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_132 0x4114210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_133 0x4114214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_134 0x4114218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_135 0x411421C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_136 0x4114220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_137 0x4114224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_138 0x4114228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_139 0x411422C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_140 0x4114230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_141 0x4114234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_142 0x4114238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_143 0x411423C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_144 0x4114240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_145 0x4114244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_146 0x4114248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_147 0x411424C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_148 0x4114250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_149 0x4114254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_150 0x4114258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_151 0x411425C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_152 0x4114260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_153 0x4114264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_154 0x4114268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_155 0x411426C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_156 0x4114270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_157 0x4114274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_158 0x4114278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_159 0x411427C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_160 0x4114280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_161 0x4114284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_162 0x4114288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_163 0x411428C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_164 0x4114290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_165 0x4114294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_166 0x4114298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_167 0x411429C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_168 0x41142A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_169 0x41142A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_170 0x41142A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_171 0x41142AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_172 0x41142B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_173 0x41142B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_174 0x41142B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_175 0x41142BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_176 0x41142C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_177 0x41142C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_178 0x41142C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_179 0x41142CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_180 0x41142D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_181 0x41142D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_182 0x41142D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_183 0x41142DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_184 0x41142E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_185 0x41142E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_186 0x41142E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_187 0x41142EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_188 0x41142F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_189 0x41142F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_190 0x41142F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_191 0x41142FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_192 0x4114300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_193 0x4114304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_194 0x4114308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_195 0x411430C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_196 0x4114310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_197 0x4114314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_198 0x4114318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_199 0x411431C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_200 0x4114320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_201 0x4114324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_202 0x4114328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_203 0x411432C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_204 0x4114330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_205 0x4114334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_206 0x4114338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_207 0x411433C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_208 0x4114340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_209 0x4114344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_210 0x4114348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_211 0x411434C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_212 0x4114350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_213 0x4114354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_214 0x4114358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_215 0x411435C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_216 0x4114360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_217 0x4114364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_218 0x4114368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_219 0x411436C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_220 0x4114370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_221 0x4114374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_222 0x4114378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_223 0x411437C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_224 0x4114380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_225 0x4114384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_226 0x4114388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_227 0x411438C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_228 0x4114390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_229 0x4114394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_230 0x4114398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_231 0x411439C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_232 0x41143A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_233 0x41143A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_234 0x41143A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_235 0x41143AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_236 0x41143B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_237 0x41143B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_238 0x41143B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_239 0x41143BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_240 0x41143C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_241 0x41143C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_242 0x41143C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_243 0x41143CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_244 0x41143D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_245 0x41143D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_246 0x41143D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_247 0x41143DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_248 0x41143E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_249 0x41143E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_250 0x41143E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_251 0x41143EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_252 0x41143F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_253 0x41143F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_254 0x41143F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_255 0x41143FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_256 0x4114400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_257 0x4114404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_258 0x4114408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_259 0x411440C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_260 0x4114410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_261 0x4114414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_262 0x4114418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_263 0x411441C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_264 0x4114420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_265 0x4114424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_266 0x4114428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_267 0x411442C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_268 0x4114430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_269 0x4114434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_270 0x4114438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_271 0x411443C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_272 0x4114440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_273 0x4114444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_274 0x4114448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_275 0x411444C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_276 0x4114450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_277 0x4114454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_278 0x4114458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_279 0x411445C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_280 0x4114460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_281 0x4114464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_282 0x4114468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_283 0x411446C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_284 0x4114470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_285 0x4114474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_286 0x4114478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_287 0x411447C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_288 0x4114480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_289 0x4114484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_290 0x4114488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_291 0x411448C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_292 0x4114490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_293 0x4114494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_294 0x4114498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_295 0x411449C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_296 0x41144A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_297 0x41144A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_298 0x41144A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_299 0x41144AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_300 0x41144B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_301 0x41144B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_302 0x41144B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_303 0x41144BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_304 0x41144C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_305 0x41144C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_306 0x41144C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_307 0x41144CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_308 0x41144D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_309 0x41144D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_310 0x41144D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_311 0x41144DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_312 0x41144E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_313 0x41144E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_314 0x41144E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_315 0x41144EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_316 0x41144F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_317 0x41144F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_318 0x41144F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_319 0x41144FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_320 0x4114500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_321 0x4114504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_322 0x4114508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_323 0x411450C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_324 0x4114510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_325 0x4114514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_326 0x4114518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_327 0x411451C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_328 0x4114520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_329 0x4114524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_330 0x4114528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_331 0x411452C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_332 0x4114530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_333 0x4114534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_334 0x4114538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_335 0x411453C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_336 0x4114540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_337 0x4114544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_338 0x4114548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_339 0x411454C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_340 0x4114550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_341 0x4114554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_342 0x4114558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_343 0x411455C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_344 0x4114560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_345 0x4114564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_346 0x4114568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_347 0x411456C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_348 0x4114570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_349 0x4114574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_350 0x4114578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_351 0x411457C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_352 0x4114580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_353 0x4114584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_354 0x4114588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_355 0x411458C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_356 0x4114590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_357 0x4114594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_358 0x4114598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_359 0x411459C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_360 0x41145A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_361 0x41145A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_362 0x41145A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_363 0x41145AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_364 0x41145B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_365 0x41145B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_366 0x41145B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_367 0x41145BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_368 0x41145C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_369 0x41145C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_370 0x41145C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_371 0x41145CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_372 0x41145D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_373 0x41145D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_374 0x41145D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_375 0x41145DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_376 0x41145E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_377 0x41145E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_378 0x41145E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_379 0x41145EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_380 0x41145F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_381 0x41145F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_382 0x41145F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_383 0x41145FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_384 0x4114600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_385 0x4114604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_386 0x4114608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_387 0x411460C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_388 0x4114610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_389 0x4114614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_390 0x4114618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_391 0x411461C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_392 0x4114620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_393 0x4114624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_394 0x4114628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_395 0x411462C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_396 0x4114630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_397 0x4114634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_398 0x4114638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_399 0x411463C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_400 0x4114640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_401 0x4114644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_402 0x4114648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_403 0x411464C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_404 0x4114650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_405 0x4114654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_406 0x4114658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_407 0x411465C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_408 0x4114660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_409 0x4114664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_410 0x4114668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_411 0x411466C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_412 0x4114670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_413 0x4114674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_414 0x4114678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_415 0x411467C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_416 0x4114680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_417 0x4114684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_418 0x4114688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_419 0x411468C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_420 0x4114690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_421 0x4114694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_422 0x4114698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_423 0x411469C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_424 0x41146A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_425 0x41146A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_426 0x41146A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_427 0x41146AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_428 0x41146B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_429 0x41146B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_430 0x41146B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_431 0x41146BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_432 0x41146C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_433 0x41146C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_434 0x41146C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_435 0x41146CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_436 0x41146D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_437 0x41146D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_438 0x41146D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_439 0x41146DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_440 0x41146E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_441 0x41146E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_442 0x41146E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_443 0x41146EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_444 0x41146F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_445 0x41146F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_446 0x41146F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_447 0x41146FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_448 0x4114700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_449 0x4114704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_450 0x4114708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_451 0x411470C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_452 0x4114710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_453 0x4114714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_454 0x4114718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_455 0x411471C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_456 0x4114720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_457 0x4114724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_458 0x4114728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_459 0x411472C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_460 0x4114730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_461 0x4114734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_462 0x4114738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_463 0x411473C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_464 0x4114740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_465 0x4114744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_466 0x4114748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_467 0x411474C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_468 0x4114750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_469 0x4114754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_470 0x4114758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_471 0x411475C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_472 0x4114760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_473 0x4114764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_474 0x4114768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_475 0x411476C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_476 0x4114770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_477 0x4114774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_478 0x4114778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_479 0x411477C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_480 0x4114780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_481 0x4114784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_482 0x4114788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_483 0x411478C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_484 0x4114790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_485 0x4114794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_486 0x4114798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_487 0x411479C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_488 0x41147A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_489 0x41147A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_490 0x41147A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_491 0x41147AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_492 0x41147B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_493 0x41147B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_494 0x41147B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_495 0x41147BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_496 0x41147C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_497 0x41147C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_498 0x41147C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_499 0x41147CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_500 0x41147D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_501 0x41147D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_502 0x41147D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_503 0x41147DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_504 0x41147E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_505 0x41147E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_506 0x41147E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_507 0x41147EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_508 0x41147F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_509 0x41147F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_510 0x41147F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_511 0x41147FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_512 0x4114800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_513 0x4114804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_514 0x4114808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_515 0x411480C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_516 0x4114810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_517 0x4114814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_518 0x4114818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_519 0x411481C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_520 0x4114820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_521 0x4114824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_522 0x4114828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_523 0x411482C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_524 0x4114830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_525 0x4114834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_526 0x4114838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_527 0x411483C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_528 0x4114840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_529 0x4114844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_530 0x4114848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_531 0x411484C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_532 0x4114850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_533 0x4114854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_534 0x4114858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_535 0x411485C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_536 0x4114860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_537 0x4114864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_538 0x4114868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_539 0x411486C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_540 0x4114870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_541 0x4114874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_542 0x4114878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_543 0x411487C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_544 0x4114880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_545 0x4114884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_546 0x4114888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_547 0x411488C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_548 0x4114890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_549 0x4114894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_550 0x4114898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_551 0x411489C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_552 0x41148A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_553 0x41148A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_554 0x41148A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_555 0x41148AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_556 0x41148B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_557 0x41148B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_558 0x41148B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_559 0x41148BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_560 0x41148C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_561 0x41148C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_562 0x41148C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_563 0x41148CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_564 0x41148D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_565 0x41148D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_566 0x41148D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_567 0x41148DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_568 0x41148E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_569 0x41148E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_570 0x41148E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_571 0x41148EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_572 0x41148F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_573 0x41148F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_574 0x41148F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_575 0x41148FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_576 0x4114900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_577 0x4114904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_578 0x4114908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_579 0x411490C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_580 0x4114910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_581 0x4114914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_582 0x4114918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_583 0x411491C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_584 0x4114920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_585 0x4114924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_586 0x4114928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_587 0x411492C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_588 0x4114930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_589 0x4114934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_590 0x4114938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_591 0x411493C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_592 0x4114940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_593 0x4114944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_594 0x4114948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_595 0x411494C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_596 0x4114950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_597 0x4114954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_598 0x4114958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_599 0x411495C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_600 0x4114960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_601 0x4114964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_602 0x4114968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_603 0x411496C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_604 0x4114970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_605 0x4114974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_606 0x4114978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_607 0x411497C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_608 0x4114980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_609 0x4114984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_610 0x4114988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_611 0x411498C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_612 0x4114990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_613 0x4114994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_614 0x4114998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_615 0x411499C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_616 0x41149A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_617 0x41149A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_618 0x41149A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_619 0x41149AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_620 0x41149B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_621 0x41149B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_622 0x41149B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_623 0x41149BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_624 0x41149C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_625 0x41149C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_626 0x41149C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_627 0x41149CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_628 0x41149D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_629 0x41149D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_630 0x41149D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_631 0x41149DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_632 0x41149E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_633 0x41149E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_634 0x41149E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_635 0x41149EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_636 0x41149F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_637 0x41149F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_638 0x41149F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_639 0x41149FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_0 0x4115000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_1 0x4115004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_2 0x4115008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_3 0x411500C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_4 0x4115010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_5 0x4115014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_6 0x4115018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_7 0x411501C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_8 0x4115020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_9 0x4115024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_10 0x4115028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_11 0x411502C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_12 0x4115030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_13 0x4115034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_14 0x4115038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_15 0x411503C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_16 0x4115040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_17 0x4115044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_18 0x4115048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_19 0x411504C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_20 0x4115050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_21 0x4115054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_22 0x4115058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_23 0x411505C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_24 0x4115060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_25 0x4115064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_26 0x4115068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_27 0x411506C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_28 0x4115070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_29 0x4115074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_30 0x4115078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_31 0x411507C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_32 0x4115080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_33 0x4115084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_34 0x4115088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_35 0x411508C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_36 0x4115090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_37 0x4115094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_38 0x4115098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_39 0x411509C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_40 0x41150A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_41 0x41150A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_42 0x41150A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_43 0x41150AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_44 0x41150B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_45 0x41150B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_46 0x41150B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_47 0x41150BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_48 0x41150C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_49 0x41150C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_50 0x41150C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_51 0x41150CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_52 0x41150D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_53 0x41150D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_54 0x41150D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_55 0x41150DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_56 0x41150E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_57 0x41150E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_58 0x41150E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_59 0x41150EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_60 0x41150F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_61 0x41150F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_62 0x41150F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_63 0x41150FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_64 0x4115100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_65 0x4115104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_66 0x4115108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_67 0x411510C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_68 0x4115110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_69 0x4115114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_70 0x4115118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_71 0x411511C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_72 0x4115120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_73 0x4115124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_74 0x4115128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_75 0x411512C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_76 0x4115130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_77 0x4115134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_78 0x4115138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_79 0x411513C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_80 0x4115140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_81 0x4115144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_82 0x4115148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_83 0x411514C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_84 0x4115150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_85 0x4115154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_86 0x4115158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_87 0x411515C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_88 0x4115160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_89 0x4115164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_90 0x4115168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_91 0x411516C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_92 0x4115170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_93 0x4115174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_94 0x4115178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_95 0x411517C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_96 0x4115180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_97 0x4115184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_98 0x4115188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_99 0x411518C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_100 0x4115190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_101 0x4115194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_102 0x4115198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_103 0x411519C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_104 0x41151A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_105 0x41151A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_106 0x41151A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_107 0x41151AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_108 0x41151B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_109 0x41151B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_110 0x41151B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_111 0x41151BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_112 0x41151C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_113 0x41151C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_114 0x41151C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_115 0x41151CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_116 0x41151D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_117 0x41151D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_118 0x41151D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_119 0x41151DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_120 0x41151E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_121 0x41151E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_122 0x41151E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_123 0x41151EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_124 0x41151F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_125 0x41151F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_126 0x41151F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_127 0x41151FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_128 0x4115200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_129 0x4115204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_130 0x4115208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_131 0x411520C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_132 0x4115210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_133 0x4115214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_134 0x4115218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_135 0x411521C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_136 0x4115220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_137 0x4115224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_138 0x4115228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_139 0x411522C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_140 0x4115230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_141 0x4115234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_142 0x4115238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_143 0x411523C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_144 0x4115240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_145 0x4115244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_146 0x4115248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_147 0x411524C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_148 0x4115250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_149 0x4115254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_150 0x4115258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_151 0x411525C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_152 0x4115260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_153 0x4115264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_154 0x4115268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_155 0x411526C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_156 0x4115270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_157 0x4115274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_158 0x4115278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_159 0x411527C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_160 0x4115280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_161 0x4115284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_162 0x4115288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_163 0x411528C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_164 0x4115290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_165 0x4115294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_166 0x4115298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_167 0x411529C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_168 0x41152A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_169 0x41152A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_170 0x41152A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_171 0x41152AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_172 0x41152B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_173 0x41152B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_174 0x41152B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_175 0x41152BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_176 0x41152C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_177 0x41152C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_178 0x41152C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_179 0x41152CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_180 0x41152D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_181 0x41152D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_182 0x41152D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_183 0x41152DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_184 0x41152E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_185 0x41152E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_186 0x41152E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_187 0x41152EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_188 0x41152F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_189 0x41152F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_190 0x41152F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_191 0x41152FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_192 0x4115300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_193 0x4115304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_194 0x4115308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_195 0x411530C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_196 0x4115310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_197 0x4115314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_198 0x4115318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_199 0x411531C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_200 0x4115320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_201 0x4115324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_202 0x4115328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_203 0x411532C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_204 0x4115330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_205 0x4115334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_206 0x4115338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_207 0x411533C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_208 0x4115340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_209 0x4115344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_210 0x4115348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_211 0x411534C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_212 0x4115350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_213 0x4115354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_214 0x4115358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_215 0x411535C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_216 0x4115360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_217 0x4115364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_218 0x4115368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_219 0x411536C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_220 0x4115370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_221 0x4115374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_222 0x4115378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_223 0x411537C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_224 0x4115380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_225 0x4115384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_226 0x4115388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_227 0x411538C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_228 0x4115390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_229 0x4115394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_230 0x4115398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_231 0x411539C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_232 0x41153A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_233 0x41153A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_234 0x41153A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_235 0x41153AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_236 0x41153B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_237 0x41153B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_238 0x41153B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_239 0x41153BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_240 0x41153C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_241 0x41153C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_242 0x41153C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_243 0x41153CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_244 0x41153D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_245 0x41153D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_246 0x41153D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_247 0x41153DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_248 0x41153E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_249 0x41153E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_250 0x41153E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_251 0x41153EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_252 0x41153F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_253 0x41153F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_254 0x41153F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_255 0x41153FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_256 0x4115400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_257 0x4115404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_258 0x4115408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_259 0x411540C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_260 0x4115410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_261 0x4115414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_262 0x4115418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_263 0x411541C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_264 0x4115420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_265 0x4115424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_266 0x4115428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_267 0x411542C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_268 0x4115430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_269 0x4115434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_270 0x4115438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_271 0x411543C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_272 0x4115440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_273 0x4115444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_274 0x4115448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_275 0x411544C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_276 0x4115450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_277 0x4115454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_278 0x4115458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_279 0x411545C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_280 0x4115460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_281 0x4115464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_282 0x4115468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_283 0x411546C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_284 0x4115470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_285 0x4115474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_286 0x4115478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_287 0x411547C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_288 0x4115480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_289 0x4115484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_290 0x4115488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_291 0x411548C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_292 0x4115490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_293 0x4115494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_294 0x4115498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_295 0x411549C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_296 0x41154A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_297 0x41154A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_298 0x41154A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_299 0x41154AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_300 0x41154B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_301 0x41154B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_302 0x41154B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_303 0x41154BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_304 0x41154C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_305 0x41154C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_306 0x41154C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_307 0x41154CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_308 0x41154D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_309 0x41154D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_310 0x41154D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_311 0x41154DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_312 0x41154E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_313 0x41154E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_314 0x41154E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_315 0x41154EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_316 0x41154F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_317 0x41154F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_318 0x41154F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_319 0x41154FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_320 0x4115500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_321 0x4115504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_322 0x4115508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_323 0x411550C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_324 0x4115510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_325 0x4115514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_326 0x4115518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_327 0x411551C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_328 0x4115520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_329 0x4115524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_330 0x4115528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_331 0x411552C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_332 0x4115530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_333 0x4115534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_334 0x4115538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_335 0x411553C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_336 0x4115540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_337 0x4115544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_338 0x4115548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_339 0x411554C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_340 0x4115550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_341 0x4115554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_342 0x4115558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_343 0x411555C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_344 0x4115560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_345 0x4115564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_346 0x4115568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_347 0x411556C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_348 0x4115570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_349 0x4115574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_350 0x4115578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_351 0x411557C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_352 0x4115580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_353 0x4115584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_354 0x4115588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_355 0x411558C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_356 0x4115590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_357 0x4115594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_358 0x4115598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_359 0x411559C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_360 0x41155A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_361 0x41155A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_362 0x41155A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_363 0x41155AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_364 0x41155B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_365 0x41155B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_366 0x41155B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_367 0x41155BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_368 0x41155C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_369 0x41155C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_370 0x41155C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_371 0x41155CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_372 0x41155D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_373 0x41155D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_374 0x41155D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_375 0x41155DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_376 0x41155E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_377 0x41155E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_378 0x41155E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_379 0x41155EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_380 0x41155F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_381 0x41155F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_382 0x41155F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_383 0x41155FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_384 0x4115600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_385 0x4115604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_386 0x4115608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_387 0x411560C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_388 0x4115610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_389 0x4115614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_390 0x4115618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_391 0x411561C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_392 0x4115620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_393 0x4115624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_394 0x4115628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_395 0x411562C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_396 0x4115630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_397 0x4115634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_398 0x4115638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_399 0x411563C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_400 0x4115640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_401 0x4115644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_402 0x4115648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_403 0x411564C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_404 0x4115650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_405 0x4115654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_406 0x4115658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_407 0x411565C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_408 0x4115660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_409 0x4115664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_410 0x4115668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_411 0x411566C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_412 0x4115670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_413 0x4115674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_414 0x4115678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_415 0x411567C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_416 0x4115680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_417 0x4115684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_418 0x4115688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_419 0x411568C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_420 0x4115690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_421 0x4115694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_422 0x4115698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_423 0x411569C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_424 0x41156A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_425 0x41156A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_426 0x41156A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_427 0x41156AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_428 0x41156B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_429 0x41156B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_430 0x41156B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_431 0x41156BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_432 0x41156C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_433 0x41156C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_434 0x41156C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_435 0x41156CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_436 0x41156D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_437 0x41156D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_438 0x41156D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_439 0x41156DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_440 0x41156E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_441 0x41156E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_442 0x41156E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_443 0x41156EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_444 0x41156F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_445 0x41156F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_446 0x41156F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_447 0x41156FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_448 0x4115700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_449 0x4115704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_450 0x4115708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_451 0x411570C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_452 0x4115710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_453 0x4115714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_454 0x4115718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_455 0x411571C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_456 0x4115720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_457 0x4115724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_458 0x4115728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_459 0x411572C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_460 0x4115730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_461 0x4115734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_462 0x4115738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_463 0x411573C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_464 0x4115740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_465 0x4115744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_466 0x4115748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_467 0x411574C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_468 0x4115750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_469 0x4115754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_470 0x4115758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_471 0x411575C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_472 0x4115760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_473 0x4115764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_474 0x4115768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_475 0x411576C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_476 0x4115770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_477 0x4115774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_478 0x4115778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_479 0x411577C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_480 0x4115780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_481 0x4115784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_482 0x4115788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_483 0x411578C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_484 0x4115790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_485 0x4115794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_486 0x4115798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_487 0x411579C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_488 0x41157A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_489 0x41157A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_490 0x41157A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_491 0x41157AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_492 0x41157B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_493 0x41157B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_494 0x41157B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_495 0x41157BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_496 0x41157C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_497 0x41157C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_498 0x41157C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_499 0x41157CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_500 0x41157D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_501 0x41157D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_502 0x41157D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_503 0x41157DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_504 0x41157E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_505 0x41157E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_506 0x41157E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_507 0x41157EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_508 0x41157F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_509 0x41157F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_510 0x41157F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_511 0x41157FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_512 0x4115800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_513 0x4115804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_514 0x4115808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_515 0x411580C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_516 0x4115810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_517 0x4115814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_518 0x4115818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_519 0x411581C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_520 0x4115820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_521 0x4115824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_522 0x4115828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_523 0x411582C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_524 0x4115830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_525 0x4115834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_526 0x4115838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_527 0x411583C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_528 0x4115840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_529 0x4115844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_530 0x4115848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_531 0x411584C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_532 0x4115850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_533 0x4115854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_534 0x4115858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_535 0x411585C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_536 0x4115860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_537 0x4115864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_538 0x4115868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_539 0x411586C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_540 0x4115870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_541 0x4115874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_542 0x4115878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_543 0x411587C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_544 0x4115880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_545 0x4115884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_546 0x4115888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_547 0x411588C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_548 0x4115890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_549 0x4115894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_550 0x4115898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_551 0x411589C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_552 0x41158A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_553 0x41158A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_554 0x41158A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_555 0x41158AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_556 0x41158B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_557 0x41158B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_558 0x41158B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_559 0x41158BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_560 0x41158C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_561 0x41158C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_562 0x41158C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_563 0x41158CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_564 0x41158D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_565 0x41158D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_566 0x41158D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_567 0x41158DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_568 0x41158E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_569 0x41158E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_570 0x41158E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_571 0x41158EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_572 0x41158F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_573 0x41158F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_574 0x41158F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_575 0x41158FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_576 0x4115900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_577 0x4115904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_578 0x4115908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_579 0x411590C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_580 0x4115910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_581 0x4115914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_582 0x4115918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_583 0x411591C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_584 0x4115920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_585 0x4115924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_586 0x4115928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_587 0x411592C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_588 0x4115930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_589 0x4115934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_590 0x4115938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_591 0x411593C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_592 0x4115940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_593 0x4115944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_594 0x4115948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_595 0x411594C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_596 0x4115950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_597 0x4115954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_598 0x4115958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_599 0x411595C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_600 0x4115960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_601 0x4115964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_602 0x4115968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_603 0x411596C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_604 0x4115970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_605 0x4115974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_606 0x4115978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_607 0x411597C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_608 0x4115980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_609 0x4115984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_610 0x4115988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_611 0x411598C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_612 0x4115990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_613 0x4115994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_614 0x4115998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_615 0x411599C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_616 0x41159A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_617 0x41159A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_618 0x41159A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_619 0x41159AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_620 0x41159B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_621 0x41159B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_622 0x41159B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_623 0x41159BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_624 0x41159C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_625 0x41159C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_626 0x41159C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_627 0x41159CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_628 0x41159D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_629 0x41159D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_630 0x41159D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_631 0x41159DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_632 0x41159E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_633 0x41159E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_634 0x41159E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_635 0x41159EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_636 0x41159F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_637 0x41159F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_638 0x41159F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_639 0x41159FC + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h new file mode 100644 index 000000000..2d4a22680 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_ASID 0x400BE00 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP 0x400BE04 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_STRONG_ORDER 0x400BE08 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_NO_SNOOP 0x400BE0C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_REDUCTION 0x400BE10 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_ATOMIC 0x400BE14 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_QOS 0x400BE18 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RSVD 0x400BE1C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_EMEM_CPAGE 0x400BE20 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_CORE 0x400BE24 + +#define mmDCORE0_TPC0_CFG_AXUSER_E2E_COORD 0x400BE28 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_LO 0x400BE30 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_HI 0x400BE34 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_LO 0x400BE38 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_HI 0x400BE3C + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_COORD 0x400BE40 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_LOCK 0x400BE44 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_RSVD 0x400BE48 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_OVRD 0x400BE4C + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h new file mode 100644 index 000000000..cdab39deb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_KERNEL + * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0x400B508 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x400B50C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_0 0x400B510 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_0 0x400B514 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_1 0x400B518 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_1 0x400B51C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_2 0x400B520 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_2 0x400B524 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_3 0x400B528 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_3 0x400B52C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_4 0x400B530 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_4 0x400B534 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG 0x400B538 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID 0x400B53C + +#define mmDCORE0_TPC0_CFG_KERNEL_POWER_LOOP 0x400B540 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_0 0x400B544 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_1 0x400B548 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_2 0x400B54C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_3 0x400B550 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_4 0x400B554 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_5 0x400B558 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_6 0x400B55C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_7 0x400B560 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_8 0x400B564 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_9 0x400B568 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_10 0x400B56C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_11 0x400B570 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_12 0x400B574 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_13 0x400B578 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_14 0x400B57C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_15 0x400B580 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_16 0x400B584 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_17 0x400B588 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_18 0x400B58C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_19 0x400B590 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_20 0x400B594 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_21 0x400B598 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_22 0x400B59C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_23 0x400B5A0 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_24 0x400B5A4 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_25 0x400B5A8 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_26 0x400B5AC + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_27 0x400B5B0 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_28 0x400B5B4 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_29 0x400B5B8 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_30 0x400B5BC + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_31 0x400B5C0 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID_INC 0x400B5C4 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x400B5C8 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x400B5CC + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x400B5D0 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x400B5D4 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x400B5D8 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h new file mode 100644 index 000000000..4ef1c1edc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_KERNEL_TENSOR_0 + * (Prototype: TPC_TENSOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0x400B000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0x400B004 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0x400B008 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0x400B00C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0x400B010 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0x400B014 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0x400B018 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0x400B01C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0x400B020 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0x400B024 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0x400B028 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0x400B02C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0x400B030 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0x400B034 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE 0x400B038 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B03C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B040 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B044 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B048 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B04C + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h new file mode 100644 index 000000000..cdecbd0f9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG + * (Prototype: TPC) + ***************************************** + */ + +/* DCORE0_TPC0_CFG_TPC_COUNT */ +#define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_ID */ +#define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STALL_ON_ERR */ +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_CLK_EN */ +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10 + +/* DCORE0_TPC0_CFG_IQ_RL_EN */ +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_IQ_RL_SAT */ +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */ +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */ +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +/* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */ +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */ +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_LOCK */ +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_SB */ +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_CNT */ +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000 + +/* DCORE0_TPC0_CFG_CGU_CPE */ +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +/* DCORE0_TPC0_CFG_FP16_FTZ_IN */ +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1 + +/* DCORE0_TPC0_CFG_DCACHE_CFG */ +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT 2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK 0x4 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT 3 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK 0x8 + +/* DCORE0_TPC0_CFG_E2E_CRDT_TOP */ +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0 + +/* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */ +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_SB_L0CD */ +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_CONV_ROUND_CSR */ +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_TSB_OCCUPANCY */ +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000 + +/* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00 + +/* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000 + +/* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK 0x10 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT 8 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK 0xFFFF00 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_FP8_143_BIAS */ +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT 0 +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK 0xF + +/* DCORE0_TPC0_CFG_ROUND_CSR */ +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_HB_PROT */ +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_LB_PROT */ +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_SEMAPHORE */ +#define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_VFLAGS */ +#define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_VFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_SFLAGS */ +#define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STATUS */ +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_CMD */ +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* DCORE0_TPC0_CFG_TPC_EXECUTE */ +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_STALL */ +#define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_RD_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_WR_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_MSS_CONFIG */ +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */ +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_INTR_MASK */ +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_CREDITS */ +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* DCORE0_TPC0_CFG_OPCODE_EXEC */ +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* DCORE0_TPC0_CFG_TSB_CFG */ +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT 17 +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK 0x20000 + +/* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000 + +/* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h new file mode 100644 index 000000000..4cd9e26a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM + * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18 + +#define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C + +#define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20 + +#define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24 + +#define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28 + +#define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C + +#define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30 + +#define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34 + +#define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38 + +#define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C + +#define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40 + +#define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44 + +#define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48 + +#define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C + +#define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50 + +#define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54 + +#define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58 + +#define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C + +#define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60 + +#define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64 + +#define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68 + +#define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C + +#define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70 + +#define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74 + +#define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78 + +#define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C + +#define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80 + +#define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84 + +#define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88 + +#define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C + +#define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90 + +#define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94 + +#define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98 + +#define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h new file mode 100644 index 000000000..8da278a3f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM_SYNC_OBJECT + * (Prototype: SYNC_OBJECT) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0x400BADC + +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR 0x400BAE0 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h new file mode 100644 index 000000000..2e4ff06e4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM_TENSOR_0 + * (Prototype: TPC_TENSOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0x400B5DC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0x400B5E0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0x400B5E4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0x400B5E8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0x400B5EC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0x400B5F0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0x400B5F4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0x400B5F8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0x400B5FC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0x400B600 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0x400B604 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0x400B608 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0x400B60C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0x400B610 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE 0x400B614 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B618 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B61C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B620 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B624 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B628 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h new file mode 100644 index 000000000..4d48f0c68 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG + * (Prototype: TPC) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18 + +#define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C + +#define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20 + +#define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24 + +#define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28 + +#define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C + +#define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30 + +#define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44 + +#define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68 + +#define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C + +#define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C + +#define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C + +#define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90 + +#define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94 + +#define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98 + +#define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C + +#define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0 + +#define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4 + +#define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8 + +#define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC + +#define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0 + +#define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4 + +#define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT 0x400BCB8 + +#define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT 0x400BCBC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO 0x400BCC0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI 0x400BCC4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO 0x400BCC8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI 0x400BCCC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO 0x400BCD0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI 0x400BCD4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO 0x400BCD8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI 0x400BCDC + +#define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM 0x400BCE0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL 0x400BCE4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 0x400BCE8 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 0x400BCEC + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 0x400BCF0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 0x400BCF4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 0x400BCF8 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 0x400BCFC + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 0x400BD00 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 0x400BD04 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 0x400BD08 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 0x400BD0C + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 0x400BD10 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 0x400BD14 + +#define mmDCORE0_TPC0_CFG_FP8_143_BIAS 0x400BD64 + +#define mmDCORE0_TPC0_CFG_ROUND_CSR 0x400BD68 + +#define mmDCORE0_TPC0_CFG_HB_PROT 0x400BD6C + +#define mmDCORE0_TPC0_CFG_LB_PROT 0x400BD70 + +#define mmDCORE0_TPC0_CFG_SEMAPHORE 0x400BD74 + +#define mmDCORE0_TPC0_CFG_VFLAGS 0x400BD78 + +#define mmDCORE0_TPC0_CFG_SFLAGS 0x400BD7C + +#define mmDCORE0_TPC0_CFG_LFSR_POLYNOM 0x400BD80 + +#define mmDCORE0_TPC0_CFG_STATUS 0x400BD84 + +#define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH 0x400BD88 + +#define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE 0x400BD8C + +#define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH 0x400BD90 + +#define mmDCORE0_TPC0_CFG_TPC_CMD 0x400BD94 + +#define mmDCORE0_TPC0_CFG_TPC_EXECUTE 0x400BD98 + +#define mmDCORE0_TPC0_CFG_TPC_STALL 0x400BD9C + +#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0x400BDA0 + +#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0x400BDA4 + +#define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT 0x400BDA8 + +#define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT 0x400BDAC + +#define mmDCORE0_TPC0_CFG_MSS_CONFIG 0x400BDB0 + +#define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE 0x400BDB4 + +#define mmDCORE0_TPC0_CFG_TPC_INTR_MASK 0x400BDB8 + +#define mmDCORE0_TPC0_CFG_WQ_CREDITS 0x400BDBC + +#define mmDCORE0_TPC0_CFG_OPCODE_EXEC 0x400BDC0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0x400BDC4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0x400BDC8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0x400BDCC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0x400BDD0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0x400BDD4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0x400BDD8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0x400BDDC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0x400BDE0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE 0x400BDE4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG 0x400BDE8 + +#define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR 0x400BDEC + +#define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR 0x400BDF0 + +#define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR 0x400BDF4 + +#define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR 0x400BDF8 + +#define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR 0x400BDFC + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h new file mode 100644 index 000000000..76ab8a1a7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h new file mode 100644 index 000000000..f07da4a24 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_BUSMON_0 + * (Prototype: BMON) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000 + +#define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004 + +#define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008 + +#define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 0x7038 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 0x703C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 0x7040 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 0x7044 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 0x7048 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 0x704C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 0x7050 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 0x7054 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 0x7058 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 0x705C + +#define mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION 0x7060 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDL 0x7070 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDH 0x7074 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDENL 0x7078 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDENH 0x707C + +#define mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP 0x7090 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR 0x7100 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTREN 0x7104 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRENL 0x7108 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRL 0x710C + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRENH 0x7120 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRH 0x7124 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE 0x7200 + +#define mmDCORE0_TPC0_EML_BUSMON_0_RELEASE 0x7204 + +#define mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE 0x7208 + +#define mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN 0x720C + +#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD 0x7220 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN 0x7224 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L 0x7228 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H 0x722C + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD 0x7304 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD 0x7308 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD 0x7310 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD 0x7314 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD 0x7320 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD 0x7324 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT 0x7400 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT 0x7404 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT 0x7408 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT 0x740C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT 0x7410 + +#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC 0x7420 + +#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP 0x7424 + +#define mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH 0x7FBC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 0x7FC0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 0x7FC4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID 0x7FC8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE 0x7FCC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 0x7FD0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 0x7FD4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 0x7FD8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 0x7FDC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 0x7FE0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 0x7FE4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 0x7FE8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 0x7FEC + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 0x7FF0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 0x7FF4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 0x7FF8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 0x7FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h new file mode 100644 index 000000000..aee9cbc78 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_ETF + * (Prototype: ETF_1KB) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004 + +#define mmDCORE0_TPC0_EML_ETF_STS 0x200C + +#define mmDCORE0_TPC0_EML_ETF_RRD 0x2010 + +#define mmDCORE0_TPC0_EML_ETF_RRP 0x2014 + +#define mmDCORE0_TPC0_EML_ETF_RWP 0x2018 + +#define mmDCORE0_TPC0_EML_ETF_TRG 0x201C + +#define mmDCORE0_TPC0_EML_ETF_CTL 0x2020 + +#define mmDCORE0_TPC0_EML_ETF_RWD 0x2024 + +#define mmDCORE0_TPC0_EML_ETF_MODE 0x2028 + +#define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C + +#define mmDCORE0_TPC0_EML_ETF_CBUFLEVEL 0x2030 + +#define mmDCORE0_TPC0_EML_ETF_BUFWM 0x2034 + +#define mmDCORE0_TPC0_EML_ETF_FFSR 0x2300 + +#define mmDCORE0_TPC0_EML_ETF_FFCR 0x2304 + +#define mmDCORE0_TPC0_EML_ETF_PSCR 0x2308 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 0x2ED0 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 0x2ED4 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 0x2ED8 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 0x2EDC + +#define mmDCORE0_TPC0_EML_ETF_ITMISCOP0 0x2EE0 + +#define mmDCORE0_TPC0_EML_ETF_ITTRFLIN 0x2EE8 + +#define mmDCORE0_TPC0_EML_ETF_ITATBDATA0 0x2EEC + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR2 0x2EF0 + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR1 0x2EF4 + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR0 0x2EF8 + +#define mmDCORE0_TPC0_EML_ETF_ITCTRL 0x2F00 + +#define mmDCORE0_TPC0_EML_ETF_CLAIMSET 0x2FA0 + +#define mmDCORE0_TPC0_EML_ETF_CLAIMCLR 0x2FA4 + +#define mmDCORE0_TPC0_EML_ETF_LAR 0x2FB0 + +#define mmDCORE0_TPC0_EML_ETF_LSR 0x2FB4 + +#define mmDCORE0_TPC0_EML_ETF_AUTHSTATUS 0x2FB8 + +#define mmDCORE0_TPC0_EML_ETF_DEVID 0x2FC8 + +#define mmDCORE0_TPC0_EML_ETF_DEVTYPE 0x2FCC + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID4 0x2FD0 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID5 0x2FD4 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID6 0x2FD8 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID7 0x2FDC + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID0 0x2FE0 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID1 0x2FE4 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID2 0x2FE8 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID3 0x2FEC + +#define mmDCORE0_TPC0_EML_ETF_COMPID0 0x2FF0 + +#define mmDCORE0_TPC0_EML_ETF_COMPID1 0x2FF4 + +#define mmDCORE0_TPC0_EML_ETF_COMPID2 0x2FF8 + +#define mmDCORE0_TPC0_EML_ETF_COMPID3 0x2FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h new file mode 100644 index 000000000..dee670b66 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_FUNNEL + * (Prototype: FUNNEL_2X1) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000 + +#define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4 + +#define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC + +#define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h new file mode 100644 index 000000000..580ae5747 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_SPMU + * (Prototype: SPMU) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC + +#define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414 + +#define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634 + +#define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0 + +#define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4 + +#define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20 + +#define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40 + +#define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80 + +#define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04 + +#define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC + +#define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0 + +#define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4 + +#define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h new file mode 100644 index 000000000..91686c563 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_STM + * (Prototype: STM) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04 + +#define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08 + +#define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C + +#define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10 + +#define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC + +#define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00 + +#define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20 + +#define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60 + +#define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64 + +#define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68 + +#define mmDCORE0_TPC0_EML_STM_STMHEMASTR 0x3DF4 + +#define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R 0x3DF8 + +#define mmDCORE0_TPC0_EML_STM_STMHEIDR 0x3DFC + +#define mmDCORE0_TPC0_EML_STM_STMSPER 0x3E00 + +#define mmDCORE0_TPC0_EML_STM_STMSPTER 0x3E20 + +#define mmDCORE0_TPC0_EML_STM_STMSPSCR 0x3E60 + +#define mmDCORE0_TPC0_EML_STM_STMSPMSCR 0x3E64 + +#define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER 0x3E68 + +#define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER 0x3E6C + +#define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR 0x3E70 + +#define mmDCORE0_TPC0_EML_STM_STMTCSR 0x3E80 + +#define mmDCORE0_TPC0_EML_STM_STMTSSTIMR 0x3E84 + +#define mmDCORE0_TPC0_EML_STM_STMTSFREQR 0x3E8C + +#define mmDCORE0_TPC0_EML_STM_STMSYNCR 0x3E90 + +#define mmDCORE0_TPC0_EML_STM_STMAUXCR 0x3E94 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT1R 0x3EA0 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT2R 0x3EA4 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT3R 0x3EA8 + +#define mmDCORE0_TPC0_EML_STM_STMITTRIGGER 0x3EE8 + +#define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 0x3EEC + +#define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 0x3EF0 + +#define mmDCORE0_TPC0_EML_STM_STMITATBID 0x3EF4 + +#define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 0x3EF8 + +#define mmDCORE0_TPC0_EML_STM_STMITCTRL 0x3F00 + +#define mmDCORE0_TPC0_EML_STM_STMCLAIMSET 0x3FA0 + +#define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR 0x3FA4 + +#define mmDCORE0_TPC0_EML_STM_STMLAR 0x3FB0 + +#define mmDCORE0_TPC0_EML_STM_STMLSR 0x3FB4 + +#define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS 0x3FB8 + +#define mmDCORE0_TPC0_EML_STM_STMDEVARCH 0x3FBC + +#define mmDCORE0_TPC0_EML_STM_STMDEVID 0x3FC8 + +#define mmDCORE0_TPC0_EML_STM_STMDEVTYPE 0x3FCC + +#define mmDCORE0_TPC0_EML_STM_STMPIDR4 0x3FD0 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR5 0x3FD4 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR6 0x3FD8 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR7 0x3FDC + +#define mmDCORE0_TPC0_EML_STM_STMPIDR0 0x3FE0 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR1 0x3FE4 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR2 0x3FE8 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR3 0x3FEC + +#define mmDCORE0_TPC0_EML_STM_STMCIDR0 0x3FF0 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR1 0x3FF4 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR2 0x3FF8 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR3 0x3FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h new file mode 100644 index 000000000..e007dabc5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100 + +#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104 + +#define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114 + +#define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134 + +#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138 + +#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C + +#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280 + +#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324 + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334 + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C + +#define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910 + +#define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..149b85f5f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID 0x400AB80 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x400AB84 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x400AB88 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x400AB8C + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x400AB90 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x400AB94 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_QOS 0x400AB98 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RSVD 0x400AB9C + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x400ABA0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_CORE 0x400ABA4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_E2E_COORD 0x400ABA8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x400ABB0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x400ABB4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x400ABB8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x400ABBC + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_COORD 0x400ABC0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_LOCK 0x400ABC4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_RSVD 0x400ABC8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_OVRD 0x400ABCC + +#endif /* ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h new file mode 100644 index 000000000..d4aad1875 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_CGM_CFG 0x400AD80 + +#define mmDCORE0_TPC0_QM_CGM_STS 0x400AD84 + +#define mmDCORE0_TPC0_QM_CGM_CFG1 0x400AD88 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h new file mode 100644 index 000000000..cca8683cb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_GLBL_CFG0 0x400A000 + +#define mmDCORE0_TPC0_QM_GLBL_CFG1 0x400A004 + +#define mmDCORE0_TPC0_QM_GLBL_CFG2 0x400A008 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG 0x400A00C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 0x400A010 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN 0x400A014 + +#define mmDCORE0_TPC0_QM_GLBL_AXCACHE 0x400A018 + +#define mmDCORE0_TPC0_QM_GLBL_STS0 0x400A01C + +#define mmDCORE0_TPC0_QM_GLBL_STS1 0x400A020 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 0x400A024 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 0x400A028 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 0x400A02C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 0x400A030 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 0x400A034 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 0x400A038 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 0x400A03C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 0x400A040 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 0x400A044 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 0x400A048 + +#define mmDCORE0_TPC0_QM_GLBL_PROT 0x400A04C + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 0x400A050 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 0x400A054 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 0x400A058 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 0x400A05C + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 0x400A060 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 0x400A064 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 0x400A068 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 0x400A06C + +#define mmDCORE0_TPC0_QM_PQ_SIZE_0 0x400A070 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_1 0x400A074 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_2 0x400A078 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_3 0x400A07C + +#define mmDCORE0_TPC0_QM_PQ_PI_0 0x400A080 + +#define mmDCORE0_TPC0_QM_PQ_PI_1 0x400A084 + +#define mmDCORE0_TPC0_QM_PQ_PI_2 0x400A088 + +#define mmDCORE0_TPC0_QM_PQ_PI_3 0x400A08C + +#define mmDCORE0_TPC0_QM_PQ_CI_0 0x400A090 + +#define mmDCORE0_TPC0_QM_PQ_CI_1 0x400A094 + +#define mmDCORE0_TPC0_QM_PQ_CI_2 0x400A098 + +#define mmDCORE0_TPC0_QM_PQ_CI_3 0x400A09C + +#define mmDCORE0_TPC0_QM_PQ_CFG0_0 0x400A0A0 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_1 0x400A0A4 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_2 0x400A0A8 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_3 0x400A0AC + +#define mmDCORE0_TPC0_QM_PQ_CFG1_0 0x400A0B0 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_1 0x400A0B4 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_2 0x400A0B8 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_3 0x400A0BC + +#define mmDCORE0_TPC0_QM_PQ_STS0_0 0x400A0C0 + +#define mmDCORE0_TPC0_QM_PQ_STS0_1 0x400A0C4 + +#define mmDCORE0_TPC0_QM_PQ_STS0_2 0x400A0C8 + +#define mmDCORE0_TPC0_QM_PQ_STS0_3 0x400A0CC + +#define mmDCORE0_TPC0_QM_PQ_STS1_0 0x400A0D0 + +#define mmDCORE0_TPC0_QM_PQ_STS1_1 0x400A0D4 + +#define mmDCORE0_TPC0_QM_PQ_STS1_2 0x400A0D8 + +#define mmDCORE0_TPC0_QM_PQ_STS1_3 0x400A0DC + +#define mmDCORE0_TPC0_QM_CQ_CFG0_0 0x400A0E0 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_1 0x400A0E4 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_2 0x400A0E8 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_3 0x400A0EC + +#define mmDCORE0_TPC0_QM_CQ_CFG0_4 0x400A0F0 + +#define mmDCORE0_TPC0_QM_CQ_STS0_0 0x400A0F4 + +#define mmDCORE0_TPC0_QM_CQ_STS0_1 0x400A0F8 + +#define mmDCORE0_TPC0_QM_CQ_STS0_2 0x400A0FC + +#define mmDCORE0_TPC0_QM_CQ_STS0_3 0x400A100 + +#define mmDCORE0_TPC0_QM_CQ_STS0_4 0x400A104 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_0 0x400A108 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_1 0x400A10C + +#define mmDCORE0_TPC0_QM_CQ_CFG1_2 0x400A110 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_3 0x400A114 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_4 0x400A118 + +#define mmDCORE0_TPC0_QM_CQ_STS1_0 0x400A11C + +#define mmDCORE0_TPC0_QM_CQ_STS1_1 0x400A120 + +#define mmDCORE0_TPC0_QM_CQ_STS1_2 0x400A124 + +#define mmDCORE0_TPC0_QM_CQ_STS1_3 0x400A128 + +#define mmDCORE0_TPC0_QM_CQ_STS1_4 0x400A12C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 0x400A150 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 0x400A154 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_0 0x400A158 + +#define mmDCORE0_TPC0_QM_CQ_CTL_0 0x400A15C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 0x400A160 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 0x400A164 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_1 0x400A168 + +#define mmDCORE0_TPC0_QM_CQ_CTL_1 0x400A16C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 0x400A170 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 0x400A174 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_2 0x400A178 + +#define mmDCORE0_TPC0_QM_CQ_CTL_2 0x400A17C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 0x400A180 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 0x400A184 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_3 0x400A188 + +#define mmDCORE0_TPC0_QM_CQ_CTL_3 0x400A18C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 0x400A190 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 0x400A194 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_4 0x400A198 + +#define mmDCORE0_TPC0_QM_CQ_CTL_4 0x400A19C + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 0x400A1A0 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 0x400A1A4 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 0x400A1A8 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 0x400A1AC + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 0x400A1B0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 0x400A1B4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 0x400A1B8 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 0x400A1BC + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 0x400A1C0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 0x400A1C4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 0x400A1C8 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 0x400A1CC + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 0x400A1D0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 0x400A1D4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 0x400A1D8 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 0x400A1DC + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 0x400A1E0 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 0x400A1E4 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 0x400A1E8 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 0x400A1EC + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0x400A1F0 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0x400A1F4 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0x400A1F8 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0x400A1FC + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0x400A200 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0x400A204 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0x400A208 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0x400A20C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0x400A210 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0x400A214 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0x400A218 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0x400A21C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0x400A220 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0x400A224 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0x400A228 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0x400A22C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0x400A230 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0x400A234 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0x400A238 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0x400A23C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0x400A240 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0x400A244 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0x400A248 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0x400A24C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0x400A250 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0x400A254 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0x400A258 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0x400A25C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0x400A260 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0x400A264 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0x400A268 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0x400A26C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0x400A270 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0x400A274 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0x400A278 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0x400A27C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0x400A280 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0x400A284 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0x400A288 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0x400A28C + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 0x400A290 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 0x400A294 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 0x400A298 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 0x400A29C + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 0x400A2A0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 0x400A2A4 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 0x400A2A8 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 0x400A2AC + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 0x400A2B0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 0x400A2B4 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 0x400A2B8 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 0x400A2BC + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 0x400A2C0 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 0x400A2C4 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 0x400A2C8 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 0x400A2CC + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 0x400A2D0 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 0x400A2D4 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 0x400A2D8 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 0x400A2DC + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 0x400A2E0 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 0x400A2E4 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 0x400A2E8 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 0x400A2EC + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 0x400A2F0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 0x400A2F4 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 0x400A2F8 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 0x400A2FC + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 0x400A300 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 0x400A304 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 0x400A308 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 0x400A30C + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 0x400A310 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 0x400A314 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 0x400A318 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 0x400A31C + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 0x400A320 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 0x400A324 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 0x400A328 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 0x400A32C + +#define mmDCORE0_TPC0_QM_CP_BARRIER_CFG 0x400A330 + +#define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x400A334 + +#define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x400A338 + +#define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET 0x400A33C + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 0x400A340 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 0x400A344 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 0x400A348 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 0x400A34C + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 0x400A350 + +#define mmDCORE0_TPC0_QM_CP_STS_0 0x400A368 + +#define mmDCORE0_TPC0_QM_CP_STS_1 0x400A36C + +#define mmDCORE0_TPC0_QM_CP_STS_2 0x400A370 + +#define mmDCORE0_TPC0_QM_CP_STS_3 0x400A374 + +#define mmDCORE0_TPC0_QM_CP_STS_4 0x400A378 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 0x400A37C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 0x400A380 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 0x400A384 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 0x400A388 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 0x400A38C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 0x400A390 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 0x400A394 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 0x400A398 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 0x400A39C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 0x400A3A0 + +#define mmDCORE0_TPC0_QM_CP_PRED_0 0x400A3A4 + +#define mmDCORE0_TPC0_QM_CP_PRED_1 0x400A3A8 + +#define mmDCORE0_TPC0_QM_CP_PRED_2 0x400A3AC + +#define mmDCORE0_TPC0_QM_CP_PRED_3 0x400A3B0 + +#define mmDCORE0_TPC0_QM_CP_PRED_4 0x400A3B4 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 0x400A3B8 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 0x400A3BC + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 0x400A3C0 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 0x400A3C4 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 0x400A3C8 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_0 0x400A3CC + +#define mmDCORE0_TPC0_QM_CP_DBG_0_1 0x400A3D0 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_2 0x400A3D4 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_3 0x400A3D8 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_4 0x400A3DC + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 0x400A3E0 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 0x400A3E4 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 0x400A3E8 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 0x400A3EC + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 0x400A3F0 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 0x400A3F4 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 0x400A3F8 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 0x400A3FC + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 0x400A400 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 0x400A404 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 0x400A408 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 0x400A40C + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 0x400A410 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 0x400A414 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 0x400A418 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 0x400A41C + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 0x400A420 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 0x400A424 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 0x400A428 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 0x400A42C + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 0x400A430 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 0x400A434 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 0x400A438 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_0 0x400A43C + +#define mmDCORE0_TPC0_QM_PQC_SIZE_1 0x400A440 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_2 0x400A444 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_3 0x400A448 + +#define mmDCORE0_TPC0_QM_PQC_PI_0 0x400A44C + +#define mmDCORE0_TPC0_QM_PQC_PI_1 0x400A450 + +#define mmDCORE0_TPC0_QM_PQC_PI_2 0x400A454 + +#define mmDCORE0_TPC0_QM_PQC_PI_3 0x400A458 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 0x400A45C + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 0x400A460 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 0x400A464 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 0x400A468 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 0x400A46C + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 0x400A470 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 0x400A474 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 0x400A478 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 0x400A47C + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 0x400A480 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 0x400A484 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 0x400A488 + +#define mmDCORE0_TPC0_QM_PQC_CFG 0x400A48C + +#define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND 0x400A490 + +#define mmDCORE0_TPC0_QM_ARB_MASK 0x400A4A0 + +#define mmDCORE0_TPC0_QM_ARB_CFG_0 0x400A4A4 + +#define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH 0x400A4A8 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 0x400A4AC + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 0x400A4B0 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 0x400A4B4 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 0x400A4B8 + +#define mmDCORE0_TPC0_QM_ARB_CFG_1 0x400A4BC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 0x400A4C0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 0x400A4C4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 0x400A4C8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 0x400A4CC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 0x400A4D0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 0x400A4D4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 0x400A4D8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 0x400A4DC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 0x400A4E0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 0x400A4E4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 0x400A4E8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 0x400A4EC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 0x400A4F0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 0x400A4F4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 0x400A4F8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 0x400A4FC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 0x400A500 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 0x400A504 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 0x400A508 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 0x400A50C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 0x400A510 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 0x400A514 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 0x400A518 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 0x400A51C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 0x400A520 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 0x400A524 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 0x400A528 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 0x400A52C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 0x400A530 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 0x400A534 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 0x400A538 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 0x400A53C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 0x400A540 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 0x400A544 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 0x400A548 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 0x400A54C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 0x400A550 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 0x400A554 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 0x400A558 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 0x400A55C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 0x400A560 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 0x400A564 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 0x400A568 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 0x400A56C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 0x400A570 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 0x400A574 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 0x400A578 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 0x400A57C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 0x400A580 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 0x400A584 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 0x400A588 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 0x400A58C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 0x400A590 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 0x400A594 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 0x400A598 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 0x400A59C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 0x400A5A0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 0x400A5A4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 0x400A5A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 0x400A5AC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 0x400A5B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 0x400A5B4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 0x400A5B8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 0x400A5BC + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC 0x400A5E0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x400A5E4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x400A5E8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x400A5EC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x400A5F0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x400A5F4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x400A5F8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x400A5FC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x400A600 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x400A604 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x400A608 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x400A60C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x400A610 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x400A614 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x400A618 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x400A61C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x400A620 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x400A624 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x400A628 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x400A62C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x400A630 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x400A634 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x400A638 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x400A63C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x400A640 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x400A644 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x400A648 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x400A64C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x400A650 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x400A654 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x400A658 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x400A65C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x400A660 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x400A664 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x400A668 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x400A66C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x400A670 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x400A674 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x400A678 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x400A67C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x400A680 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x400A684 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x400A688 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x400A68C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x400A690 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x400A694 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x400A698 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x400A69C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x400A6A0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x400A6A4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x400A6A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x400A6AC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x400A6B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x400A6B4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x400A6B8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x400A6BC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x400A6C0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x400A6C4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x400A6C8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x400A6CC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x400A6D0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x400A6D4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x400A6D8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x400A6DC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x400A6E0 + +#define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x400A704 + +#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN 0x400A708 + +#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 0x400A70C + +#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT 0x400A710 + +#define mmDCORE0_TPC0_QM_ARB_SLV_ID 0x400A714 + +#define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER 0x400A718 + +#define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT 0x400A744 + +#define mmDCORE0_TPC0_QM_ARB_BASE_LO 0x400A754 + +#define mmDCORE0_TPC0_QM_ARB_BASE_HI 0x400A758 + +#define mmDCORE0_TPC0_QM_ARB_STATE_STS 0x400A780 + +#define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS 0x400A784 + +#define mmDCORE0_TPC0_QM_ARB_MSG_STS 0x400A788 + +#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD 0x400A78C + +#define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE 0x400A79C + +#define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN 0x400A7A0 + +#define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP 0x400A7A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS 0x400A7B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 0x400A7B4 + +#define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG 0x400A7FC + +#define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 0x400A800 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 0x400A804 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO 0x400A808 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI 0x400A80C + +#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE 0x400A810 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL 0x400A814 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS 0x400A81C + +#define mmDCORE0_TPC0_QM_ARC_CQ_STS0 0x400A820 + +#define mmDCORE0_TPC0_QM_ARC_CQ_STS1 0x400A824 + +#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS 0x400A828 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS 0x400A82C + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS 0x400A830 + +#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI 0x400A834 + +#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO 0x400A838 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x400A83C + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x400A840 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x400A844 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x400A848 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI 0x400A84C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO 0x400A850 + +#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI 0x400A854 + +#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO 0x400A858 + +#define mmDCORE0_TPC0_QM_ADDR_OVRD 0x400A85C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 0x400A860 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 0x400A864 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 0x400A868 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 0x400A86C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 0x400A870 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI 0x400A874 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 0x400A878 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 0x400A87C + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 0x400A880 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 0x400A884 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 0x400A888 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI 0x400A88C + +#define mmDCORE0_TPC0_QM_CP_CFG 0x400A890 + +#define mmDCORE0_TPC0_QM_CP_EXT_SWITCH 0x400A894 + +#define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET 0x400A898 + +#define mmDCORE0_TPC0_QM_CP_SWITCH_WD 0x400A89C + +#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO 0x400A8A4 + +#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI 0x400A8A8 + +#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI 0x400A8AC + +#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO 0x400A8B0 + +#define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE 0x400A8B4 + +#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x400A8B8 + +#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x400A8BC + +#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI 0x400A8C0 + +#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO 0x400A8C4 + +#define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND 0x400A8C8 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_0 0x400A8D0 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_1 0x400A8D4 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_2 0x400A8D8 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_3 0x400A8DC + +#define mmDCORE0_TPC0_QM_PQC_STS_1_0 0x400A8E0 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_1 0x400A8E4 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_2 0x400A8E8 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_3 0x400A8EC + +#define mmDCORE0_TPC0_QM_SEI_STATUS 0x400A8F0 + +#define mmDCORE0_TPC0_QM_SEI_MASK 0x400A8F4 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO 0x400AD00 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI 0x400AD04 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA 0x400AD08 + +#define mmDCORE0_TPC0_QM_L2H_MASK_LO 0x400AD14 + +#define mmDCORE0_TPC0_QM_L2H_MASK_HI 0x400AD18 + +#define mmDCORE0_TPC0_QM_L2H_CMPR_LO 0x400AD1C + +#define mmDCORE0_TPC0_QM_L2H_CMPR_HI 0x400AD20 + +#define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE 0x400AD24 + +#define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE 0x400AD28 + +#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 0x400AD30 + +#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 0x400AD34 + +#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 0x400AD38 + +#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 0x400AD3C + +#define mmDCORE0_TPC0_QM_IND_GW_APB_CFG 0x400AD40 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA 0x400AD44 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA 0x400AD48 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS 0x400AD4C + +#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO 0x400AD60 + +#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI 0x400AD64 + +#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO 0x400AD68 + +#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI 0x400AD6C + +#define mmDCORE0_TPC0_QM_PERF_CNT_CFG 0x400AD70 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h new file mode 100644 index 000000000..e68667cc7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x41E3C00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x41E3C04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x41E3C08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x41E3C0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x41E3C10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x41E3C14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x41E3C18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x41E3C1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x41E3C20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x41E3C24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x41E3C28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x41E3C30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x41E3C34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x41E3C38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x41E3C3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x41E3C40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x41E3C44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x41E3C48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x41E3C4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h new file mode 100644 index 000000000..f7ffdcbd1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x41E3B00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x41E3B04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x41E3B08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x41E3B0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x41E3B10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x41E3B14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x41E3B18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x41E3B1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x41E3B20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x41E3B24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x41E3B28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x41E3B30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x41E3B34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x41E3B38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x41E3B3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x41E3B40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x41E3B44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x41E3B48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x41E3B4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h new file mode 100644 index 000000000..4c1bb5306 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x41E3900 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x41E3904 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x41E3908 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x41E390C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x41E3910 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x41E3914 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x41E3918 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x41E391C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x41E3920 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x41E3924 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x41E3928 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x41E3930 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x41E3934 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x41E3938 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x41E393C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x41E3940 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x41E3944 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x41E3948 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x41E394C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h new file mode 100644 index 000000000..e413905ff --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x41E3A00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x41E3A04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x41E3A08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x41E3A0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x41E3A10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x41E3A14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x41E3A18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x41E3A1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x41E3A20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x41E3A24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x41E3A28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x41E3A30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x41E3A34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x41E3A38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x41E3A3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x41E3A40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x41E3A44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x41E3A48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x41E3A4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h new file mode 100644 index 000000000..bce75ac6e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x41E3800 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x41E3804 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x41E3808 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x41E380C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x41E3810 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x41E3814 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x41E3818 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x41E381C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x41E3820 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x41E3824 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x41E3828 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x41E3830 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x41E3834 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x41E3838 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x41E383C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x41E3840 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x41E3844 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x41E3848 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x41E384C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h new file mode 100644 index 000000000..68dd98459 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h @@ -0,0 +1,581 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +/* DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE */ +#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_GRACEFUL */ +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 + +/* DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR */ +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK \ +0x8 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \ +0x100 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h new file mode 100644 index 000000000..d2844307a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100 + +#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104 + +#define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108 + +#define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C + +#define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110 + +#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114 + +#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C + +#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x41E3320 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x41E3330 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x41E3334 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x41E3338 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x41E3340 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x41E3350 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x41E3360 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x41E3380 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x41E3390 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x41E3394 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x41E33C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x41E33D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x41E33E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x41E3400 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x41E3410 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x41E3420 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x41E3430 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x41E3434 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x41E3438 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x41E3440 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x41E3450 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x41E3460 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x41E3480 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x41E3490 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x41E3494 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x41E34C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x41E34D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x41E34E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x41E3500 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x41E3510 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x41E3520 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x41E3530 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x41E3534 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x41E3538 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x41E3540 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x41E3550 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x41E3560 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x41E3580 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x41E3590 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x41E3594 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x41E35C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x41E35D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x41E35E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x41E3600 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x41E3610 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x41E3620 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x41E3630 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x41E3634 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x41E3638 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x41E3640 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x41E3650 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x41E3660 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x41E3680 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x41E3690 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x41E3694 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x41E36C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x41E36D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x41E36E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x41E3700 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x41E3704 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x41E3708 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x41E370C + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x41E3714 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x41E3718 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x41E371C + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x41E3720 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x41E3724 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x41E3728 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x41E372C + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x41E3730 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x41E3734 + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h new file mode 100644 index 000000000..89b522b12 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_CTRL_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x41E4E80 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x41E4E84 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x41E4E88 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x41E4E8C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x41E4E90 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x41E4E94 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x41E4E98 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x41E4E9C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x41E4EA0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x41E4EA4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x41E4EA8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x41E4EAC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x41E4EB0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x41E4EB4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x41E4EB8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x41E4EBC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x41E4EC0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x41E4EC4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x41E4EC8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x41E4ECC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x41E4ED0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x41E4ED4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x41E4ED8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x41E4EDC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x41E4EE0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x41E4EE4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x41E4EE8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x41E4EEC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x41E4EF0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x41E4EF4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x41E4EF8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x41E4EFC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x41E4F00 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x41E4F04 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x41E4F0C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x41E4F10 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x41E4F14 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x41E4F18 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x41E4F1C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x41E4F20 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x41E4F24 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_RM 0x41E4F28 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x41E4F40 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x41E4F44 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x41E4F48 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x41E4F60 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x41E4F64 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x41E4F68 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x41E4F6C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x41E4F80 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x41E4F84 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x41E4F88 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x41E4F8C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x41E4F90 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x41E4F94 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x41E4F98 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x41E4F9C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x41E4FA0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x41E4FA4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x41E4FA8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x41E4FAC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x41E4FB0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x41E4FB4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x41E4FB8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x41E4FBC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x41E4FC0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x41E4FC4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x41E4FC8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x41E4FCC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x41E4FD0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x41E4FD4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x41E4FD8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x41E4FDC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x41E4FE0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x41E4FE4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x41E4FE8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x41E4FEC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x41E4FF0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x41E4FF4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x41E4FF8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x41E4FFC + +#endif /* ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h new file mode 100644 index 000000000..622613dc7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE1_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE1_MME_CTRL_LO_ARCH_STATUS 0x42CB000 + +#define mmDCORE1_MME_CTRL_LO_CMD 0x42CB004 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x42CB148 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x42CB14C + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x42CB150 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x42CB154 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x42CB158 + +#define mmDCORE1_MME_CTRL_LO_ARCH_A_SS 0x42CB224 + +#define mmDCORE1_MME_CTRL_LO_ARCH_B_SS 0x42CB228 + +#define mmDCORE1_MME_CTRL_LO_ARCH_COUT_SS 0x42CB27C + +#define mmDCORE1_MME_CTRL_LO_QM_STALL 0x42CB400 + +#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_LO 0x42CB404 + +#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_HI 0x42CB408 + +#define mmDCORE1_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x42CB40C + +#define mmDCORE1_MME_CTRL_LO_REDUN 0x42CB410 + +#define mmDCORE1_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x42CB414 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x42CB418 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x42CB41C + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x42CB420 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x42CB424 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x42CB428 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x42CB42C + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x42CB430 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_DESC0 0x42CB434 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x42CB438 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_TH 0x42CB43C + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_MIN 0x42CB440 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_CTRL_EN 0x42CB444 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x42CB448 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x42CB44C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x42CB450 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x42CB454 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x42CB458 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_F8 0x42CB45C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x42CB460 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x42CB464 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x42CB468 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x42CB46C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x42CB470 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x42CB474 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x42CB478 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x42CB47C + +#define mmDCORE1_MME_CTRL_LO_PROT 0x42CB480 + +#define mmDCORE1_MME_CTRL_LO_EU 0x42CB484 + +#define mmDCORE1_MME_CTRL_LO_SBTE 0x42CB488 + +#define mmDCORE1_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x42CB48C + +#define mmDCORE1_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x42CB490 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_SAT_SEC 0x42CB494 + +#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x42CB498 + +#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x42CB49C + +#define mmDCORE1_MME_CTRL_LO_EU_ISOLATION_DIS 0x42CB4A0 + +#define mmDCORE1_MME_CTRL_LO_QM_SLV_CLK_EN 0x42CB4A4 + +#define mmDCORE1_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x42CB4A8 + +#define mmDCORE1_MME_CTRL_LO_AGU 0x42CB4AC + +#define mmDCORE1_MME_CTRL_LO_QM 0x42CB4B0 + +#define mmDCORE1_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x42CB4B4 + +#define mmDCORE1_MME_CTRL_LO_INTR_CAUSE 0x42CB4B8 + +#define mmDCORE1_MME_CTRL_LO_INTR_MASK 0x42CB4BC + +#define mmDCORE1_MME_CTRL_LO_INTR_CLEAR 0x42CB4C0 + +#define mmDCORE1_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x42CB4C4 + +#define mmDCORE1_MME_CTRL_LO_BIST 0x42CB4C8 + +#define mmDCORE1_MME_CTRL_LO_EU_RL_ENABLE 0x42CB4CC + +#define mmDCORE1_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x42CB4D0 + +#define mmDCORE1_MME_CTRL_LO_EU_RL_CFG 0x42CB4D4 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW0 0x42CB4D8 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW1 0x42CB4DC + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW2 0x42CB4E0 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW3 0x42CB4E4 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_WKL_ID 0x42CB4E8 + +#define mmDCORE1_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x42CB4EC + +#endif /* ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h new file mode 100644 index 000000000..b06469f5a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE3_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE3_MME_CTRL_LO_ARCH_STATUS 0x46CB000 + +#define mmDCORE3_MME_CTRL_LO_CMD 0x46CB004 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x46CB148 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x46CB14C + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x46CB150 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x46CB154 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x46CB158 + +#define mmDCORE3_MME_CTRL_LO_ARCH_A_SS 0x46CB224 + +#define mmDCORE3_MME_CTRL_LO_ARCH_B_SS 0x46CB228 + +#define mmDCORE3_MME_CTRL_LO_ARCH_COUT_SS 0x46CB27C + +#define mmDCORE3_MME_CTRL_LO_QM_STALL 0x46CB400 + +#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_LO 0x46CB404 + +#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_HI 0x46CB408 + +#define mmDCORE3_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x46CB40C + +#define mmDCORE3_MME_CTRL_LO_REDUN 0x46CB410 + +#define mmDCORE3_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x46CB414 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x46CB418 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x46CB41C + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x46CB420 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x46CB424 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x46CB428 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x46CB42C + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x46CB430 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_DESC0 0x46CB434 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x46CB438 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_TH 0x46CB43C + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_MIN 0x46CB440 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_CTRL_EN 0x46CB444 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x46CB448 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x46CB44C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x46CB450 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x46CB454 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x46CB458 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_F8 0x46CB45C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x46CB460 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x46CB464 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x46CB468 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x46CB46C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x46CB470 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x46CB474 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x46CB478 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x46CB47C + +#define mmDCORE3_MME_CTRL_LO_PROT 0x46CB480 + +#define mmDCORE3_MME_CTRL_LO_EU 0x46CB484 + +#define mmDCORE3_MME_CTRL_LO_SBTE 0x46CB488 + +#define mmDCORE3_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x46CB48C + +#define mmDCORE3_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x46CB490 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_SAT_SEC 0x46CB494 + +#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x46CB498 + +#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x46CB49C + +#define mmDCORE3_MME_CTRL_LO_EU_ISOLATION_DIS 0x46CB4A0 + +#define mmDCORE3_MME_CTRL_LO_QM_SLV_CLK_EN 0x46CB4A4 + +#define mmDCORE3_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x46CB4A8 + +#define mmDCORE3_MME_CTRL_LO_AGU 0x46CB4AC + +#define mmDCORE3_MME_CTRL_LO_QM 0x46CB4B0 + +#define mmDCORE3_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x46CB4B4 + +#define mmDCORE3_MME_CTRL_LO_INTR_CAUSE 0x46CB4B8 + +#define mmDCORE3_MME_CTRL_LO_INTR_MASK 0x46CB4BC + +#define mmDCORE3_MME_CTRL_LO_INTR_CLEAR 0x46CB4C0 + +#define mmDCORE3_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x46CB4C4 + +#define mmDCORE3_MME_CTRL_LO_BIST 0x46CB4C8 + +#define mmDCORE3_MME_CTRL_LO_EU_RL_ENABLE 0x46CB4CC + +#define mmDCORE3_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x46CB4D0 + +#define mmDCORE3_MME_CTRL_LO_EU_RL_CFG 0x46CB4D4 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW0 0x46CB4D8 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW1 0x46CB4DC + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW2 0x46CB4E0 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW3 0x46CB4E4 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_WKL_ID 0x46CB4E8 + +#define mmDCORE3_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x46CB4EC + +#endif /* ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h new file mode 100644 index 000000000..3caee4515 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h @@ -0,0 +1,45067 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_ +#define GAUDI2_BLOCKS_LINUX_DRIVER_H_ + +#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull +#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull +#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull +#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull +#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull +#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull +#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull +#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull +#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull +#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull +#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull +#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull +#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull +#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull +#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull +#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull +#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull +#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull +#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull +#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC0_EML_CS_BASE 0x1FF000ull +#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC1_ROM_TABLE_BASE 0x200000ull +#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_SPMU_BASE 0x201000ull +#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_ETF_BASE 0x202000ull +#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_STM_BASE 0x203000ull +#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC1_EML_CTI_BASE 0x205000ull +#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull +#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull +#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull +#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull +#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull +#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull +#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC1_EML_CFG_BASE 0x240000ull +#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull +#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull +#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull +#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull +#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull +#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull +#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull +#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC1_EML_CS_BASE 0x3FF000ull +#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC2_ROM_TABLE_BASE 0x400000ull +#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_SPMU_BASE 0x401000ull +#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_ETF_BASE 0x402000ull +#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_STM_BASE 0x403000ull +#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC2_EML_CTI_BASE 0x405000ull +#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull +#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull +#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull +#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull +#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull +#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull +#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC2_EML_CFG_BASE 0x440000ull +#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull +#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull +#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull +#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull +#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull +#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull +#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull +#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC2_EML_CS_BASE 0x5FF000ull +#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC3_ROM_TABLE_BASE 0x600000ull +#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_SPMU_BASE 0x601000ull +#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_ETF_BASE 0x602000ull +#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_STM_BASE 0x603000ull +#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC3_EML_CTI_BASE 0x605000ull +#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull +#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull +#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull +#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull +#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull +#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull +#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC3_EML_CFG_BASE 0x640000ull +#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull +#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull +#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull +#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull +#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull +#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull +#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull +#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC3_EML_CS_BASE 0x7FF000ull +#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC4_ROM_TABLE_BASE 0x800000ull +#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_SPMU_BASE 0x801000ull +#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_ETF_BASE 0x802000ull +#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_STM_BASE 0x803000ull +#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC4_EML_CTI_BASE 0x805000ull +#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull +#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull +#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull +#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull +#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull +#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull +#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC4_EML_CFG_BASE 0x840000ull +#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull +#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull +#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull +#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull +#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull +#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull +#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull +#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC4_EML_CS_BASE 0x9FF000ull +#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull +#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_SPMU_BASE 0xA01000ull +#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_ETF_BASE 0xA02000ull +#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_STM_BASE 0xA03000ull +#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC5_EML_CTI_BASE 0xA05000ull +#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull +#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull +#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull +#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull +#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull +#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull +#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC5_EML_CFG_BASE 0xA40000ull +#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull +#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull +#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull +#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull +#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull +#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull +#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull +#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC5_EML_CS_BASE 0xBFF000ull +#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull +#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_SPMU_BASE 0xC01000ull +#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_ETF_BASE 0xC02000ull +#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_STM_BASE 0xC03000ull +#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC6_EML_CTI_BASE 0xC05000ull +#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull +#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull +#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull +#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull +#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull +#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull +#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC6_EML_CFG_BASE 0xC40000ull +#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull +#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull +#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull +#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull +#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull +#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull +#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull +#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC6_EML_CS_BASE 0xDFF000ull +#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CS_SECTION 0x201000 +#define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull +#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_SPMU_BASE 0x1001000ull +#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_ETF_BASE 0x1002000ull +#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_STM_BASE 0x1003000ull +#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC0_EML_CTI_BASE 0x1005000ull +#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull +#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull +#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull +#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull +#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull +#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull +#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC0_EML_CFG_BASE 0x1040000ull +#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull +#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull +#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull +#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull +#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull +#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull +#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull +#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC0_EML_CS_BASE 0x11FF000ull +#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull +#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_SPMU_BASE 0x1201000ull +#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_ETF_BASE 0x1202000ull +#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_STM_BASE 0x1203000ull +#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC1_EML_CTI_BASE 0x1205000ull +#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull +#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull +#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull +#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull +#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull +#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull +#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC1_EML_CFG_BASE 0x1240000ull +#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull +#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull +#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull +#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull +#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull +#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull +#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull +#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC1_EML_CS_BASE 0x13FF000ull +#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull +#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_SPMU_BASE 0x1401000ull +#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_ETF_BASE 0x1402000ull +#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_STM_BASE 0x1403000ull +#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC2_EML_CTI_BASE 0x1405000ull +#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull +#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull +#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull +#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull +#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull +#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull +#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC2_EML_CFG_BASE 0x1440000ull +#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull +#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull +#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull +#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull +#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull +#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull +#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull +#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC2_EML_CS_BASE 0x15FF000ull +#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull +#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_SPMU_BASE 0x1601000ull +#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_ETF_BASE 0x1602000ull +#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_STM_BASE 0x1603000ull +#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC3_EML_CTI_BASE 0x1605000ull +#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull +#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull +#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull +#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull +#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull +#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull +#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC3_EML_CFG_BASE 0x1640000ull +#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull +#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull +#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull +#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull +#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull +#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull +#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull +#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC3_EML_CS_BASE 0x17FF000ull +#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull +#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_SPMU_BASE 0x1801000ull +#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_ETF_BASE 0x1802000ull +#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_STM_BASE 0x1803000ull +#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC4_EML_CTI_BASE 0x1805000ull +#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull +#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull +#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull +#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull +#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull +#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull +#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC4_EML_CFG_BASE 0x1840000ull +#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull +#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull +#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull +#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull +#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull +#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull +#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull +#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC4_EML_CS_BASE 0x19FF000ull +#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull +#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull +#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_ETF_BASE 0x1A02000ull +#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_STM_BASE 0x1A03000ull +#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC5_EML_CTI_BASE 0x1A05000ull +#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull +#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull +#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull +#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull +#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull +#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull +#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC5_EML_CFG_BASE 0x1A40000ull +#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull +#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull +#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull +#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull +#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull +#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull +#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC5_EML_CS_BASE 0x1BFF000ull +#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull +#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_SPMU_BASE 0x2001000ull +#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_ETF_BASE 0x2002000ull +#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_STM_BASE 0x2003000ull +#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC0_EML_CTI_BASE 0x2005000ull +#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull +#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull +#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull +#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull +#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull +#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull +#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC0_EML_CFG_BASE 0x2040000ull +#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull +#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull +#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull +#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull +#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull +#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull +#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull +#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC0_EML_CS_BASE 0x21FF000ull +#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull +#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_SPMU_BASE 0x2201000ull +#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_ETF_BASE 0x2202000ull +#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_STM_BASE 0x2203000ull +#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC1_EML_CTI_BASE 0x2205000ull +#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull +#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull +#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull +#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull +#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull +#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull +#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC1_EML_CFG_BASE 0x2240000ull +#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull +#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull +#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull +#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull +#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull +#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull +#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull +#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC1_EML_CS_BASE 0x23FF000ull +#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull +#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_SPMU_BASE 0x2401000ull +#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_ETF_BASE 0x2402000ull +#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_STM_BASE 0x2403000ull +#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC2_EML_CTI_BASE 0x2405000ull +#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull +#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull +#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull +#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull +#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull +#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull +#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC2_EML_CFG_BASE 0x2440000ull +#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull +#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull +#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull +#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull +#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull +#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull +#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull +#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC2_EML_CS_BASE 0x25FF000ull +#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull +#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_SPMU_BASE 0x2601000ull +#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_ETF_BASE 0x2602000ull +#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_STM_BASE 0x2603000ull +#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC3_EML_CTI_BASE 0x2605000ull +#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull +#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull +#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull +#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull +#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull +#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull +#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC3_EML_CFG_BASE 0x2640000ull +#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull +#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull +#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull +#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull +#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull +#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull +#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull +#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC3_EML_CS_BASE 0x27FF000ull +#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull +#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_SPMU_BASE 0x2801000ull +#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_ETF_BASE 0x2802000ull +#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_STM_BASE 0x2803000ull +#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC4_EML_CTI_BASE 0x2805000ull +#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull +#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull +#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull +#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull +#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull +#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull +#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC4_EML_CFG_BASE 0x2840000ull +#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull +#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull +#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull +#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull +#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull +#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull +#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull +#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC4_EML_CS_BASE 0x29FF000ull +#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull +#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull +#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_ETF_BASE 0x2A02000ull +#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_STM_BASE 0x2A03000ull +#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC5_EML_CTI_BASE 0x2A05000ull +#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull +#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull +#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull +#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull +#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull +#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull +#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC5_EML_CFG_BASE 0x2A40000ull +#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull +#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull +#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull +#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull +#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull +#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull +#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull +#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC5_EML_CS_BASE 0x2BFF000ull +#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull +#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_SPMU_BASE 0x3001000ull +#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_ETF_BASE 0x3002000ull +#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_STM_BASE 0x3003000ull +#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC0_EML_CTI_BASE 0x3005000ull +#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull +#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull +#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull +#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull +#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull +#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull +#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC0_EML_CFG_BASE 0x3040000ull +#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull +#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull +#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull +#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull +#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull +#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull +#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull +#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC0_EML_CS_BASE 0x31FF000ull +#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull +#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_SPMU_BASE 0x3201000ull +#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_ETF_BASE 0x3202000ull +#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_STM_BASE 0x3203000ull +#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC1_EML_CTI_BASE 0x3205000ull +#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull +#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull +#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull +#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull +#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull +#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull +#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC1_EML_CFG_BASE 0x3240000ull +#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull +#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull +#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull +#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull +#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull +#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull +#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull +#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC1_EML_CS_BASE 0x33FF000ull +#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull +#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_SPMU_BASE 0x3401000ull +#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_ETF_BASE 0x3402000ull +#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_STM_BASE 0x3403000ull +#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC2_EML_CTI_BASE 0x3405000ull +#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull +#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull +#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull +#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull +#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull +#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull +#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC2_EML_CFG_BASE 0x3440000ull +#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull +#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull +#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull +#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull +#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull +#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull +#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull +#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC2_EML_CS_BASE 0x35FF000ull +#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull +#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_SPMU_BASE 0x3601000ull +#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_ETF_BASE 0x3602000ull +#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_STM_BASE 0x3603000ull +#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC3_EML_CTI_BASE 0x3605000ull +#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull +#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull +#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull +#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull +#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull +#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull +#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC3_EML_CFG_BASE 0x3640000ull +#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull +#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull +#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull +#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull +#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull +#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull +#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull +#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC3_EML_CS_BASE 0x37FF000ull +#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull +#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_SPMU_BASE 0x3801000ull +#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_ETF_BASE 0x3802000ull +#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_STM_BASE 0x3803000ull +#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC4_EML_CTI_BASE 0x3805000ull +#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull +#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull +#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull +#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull +#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull +#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull +#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC4_EML_CFG_BASE 0x3840000ull +#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull +#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull +#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull +#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull +#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull +#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull +#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull +#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC4_EML_CS_BASE 0x39FF000ull +#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull +#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull +#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_ETF_BASE 0x3A02000ull +#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_STM_BASE 0x3A03000ull +#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC5_EML_CTI_BASE 0x3A05000ull +#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull +#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull +#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull +#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull +#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull +#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull +#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC5_EML_CFG_BASE 0x3A40000ull +#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull +#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull +#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull +#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull +#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull +#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull +#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull +#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC5_EML_CS_BASE 0x3BFF000ull +#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE0_TPC0_QM_DCCM_BASE 0x4000000ull +#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull +#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC0_QM_BASE 0x400A000ull +#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_SECTION 0x9000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull +#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull +#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull +#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_CGM_BASE 0x400AD80ull +#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull +#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_CFG_BASE 0x400B000ull +#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_CFG_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull +#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull +#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull +#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull +#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull +#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull +#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull +#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull +#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull +#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull +#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull +#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull +#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC1_QM_DCCM_BASE 0x4010000ull +#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull +#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC1_QM_BASE 0x401A000ull +#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_SECTION 0x9000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull +#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull +#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull +#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_CGM_BASE 0x401AD80ull +#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull +#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_CFG_BASE 0x401B000ull +#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_CFG_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull +#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull +#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull +#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull +#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull +#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull +#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull +#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull +#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull +#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull +#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull +#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull +#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC2_QM_DCCM_BASE 0x4020000ull +#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull +#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC2_QM_BASE 0x402A000ull +#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_SECTION 0x9000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull +#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull +#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull +#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_CGM_BASE 0x402AD80ull +#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull +#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_CFG_BASE 0x402B000ull +#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_CFG_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull +#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull +#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull +#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull +#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull +#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull +#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull +#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull +#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull +#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull +#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull +#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull +#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC3_QM_DCCM_BASE 0x4030000ull +#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull +#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC3_QM_BASE 0x403A000ull +#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_SECTION 0x9000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull +#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull +#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull +#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_CGM_BASE 0x403AD80ull +#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull +#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_CFG_BASE 0x403B000ull +#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_CFG_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull +#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull +#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull +#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull +#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull +#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull +#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull +#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull +#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull +#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull +#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull +#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull +#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC4_QM_DCCM_BASE 0x4040000ull +#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull +#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC4_QM_BASE 0x404A000ull +#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_SECTION 0x9000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull +#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull +#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull +#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_CGM_BASE 0x404AD80ull +#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull +#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_CFG_BASE 0x404B000ull +#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_CFG_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull +#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull +#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull +#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull +#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull +#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull +#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull +#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull +#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull +#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull +#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull +#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull +#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC5_QM_DCCM_BASE 0x4050000ull +#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull +#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC5_QM_BASE 0x405A000ull +#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_SECTION 0x9000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull +#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull +#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull +#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_CGM_BASE 0x405AD80ull +#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull +#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_CFG_BASE 0x405B000ull +#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_CFG_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull +#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull +#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull +#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull +#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull +#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull +#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull +#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull +#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull +#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull +#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull +#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull +#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC6_QM_DCCM_BASE 0x4060000ull +#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull +#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC6_QM_BASE 0x406A000ull +#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_SECTION 0x9000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull +#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull +#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull +#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_CGM_BASE 0x406AD80ull +#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull +#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_CFG_BASE 0x406B000ull +#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_CFG_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull +#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull +#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull +#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull +#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull +#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull +#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull +#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull +#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull +#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull +#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull +#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull +#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180 +#define mmDCORE0_HMMU0_MMU_BASE 0x4080000ull +#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull +#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU0_STLB_BASE 0x4081000ull +#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull +#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull +#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull +#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU1_MMU_BASE 0x4090000ull +#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull +#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU1_STLB_BASE 0x4091000ull +#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull +#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull +#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull +#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU2_MMU_BASE 0x40A0000ull +#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull +#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU2_STLB_BASE 0x40A1000ull +#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull +#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull +#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull +#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU3_MMU_BASE 0x40B0000ull +#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull +#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU3_STLB_BASE 0x40B1000ull +#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull +#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull +#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull +#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull +#define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull +#define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull +#define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull +#define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull +#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull +#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_BASE 0x40CA000ull +#define DCORE0_MME_QM_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_SECTION 0x9000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull +#define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull +#define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull +#define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull +#define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_MME_QM_CGM_BASE 0x40CAD80ull +#define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull +#define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_BASE 0x40CB000ull +#define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull +#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull +#define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull +#define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_BASE 0x40CC000ull +#define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull +#define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_EU_BIST_BASE 0x40CD000ull +#define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE0_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull +#define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull +#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull +#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull +#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull +#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull +#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull +#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull +#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull +#define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull +#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_BASE 0x40D0000ull +#define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_SECTION 0xE800 +#define mmDCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull +#define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull +#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull +#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull +#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE1_BASE 0x40D8000ull +#define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_SECTION 0xE800 +#define mmDCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull +#define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull +#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull +#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull +#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE2_BASE 0x40E0000ull +#define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_SECTION 0xE800 +#define mmDCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull +#define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull +#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull +#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull +#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE3_BASE 0x40E8000ull +#define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_SECTION 0xE800 +#define mmDCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull +#define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull +#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull +#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull +#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE4_BASE 0x40F0000ull +#define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_SECTION 0xE800 +#define mmDCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull +#define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull +#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull +#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull +#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_ACC_BASE 0x40F8000ull +#define DCORE0_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_SECTION 0xE800 +#define mmDCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull +#define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull +#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull +#define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull +#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull +#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull +#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull +#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull +#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull +#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull +#define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull +#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull +#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull +#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull +#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull +#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull +#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull +#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HIF0_BASE 0x4120000ull +#define DCORE0_HIF0_MAX_OFFSET 0x1000 +#define DCORE0_HIF0_SECTION 0xE800 +#define mmDCORE0_HIF0_SPECIAL_BASE 0x4120E80ull +#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF1_BASE 0x4124000ull +#define DCORE0_HIF1_MAX_OFFSET 0x1000 +#define DCORE0_HIF1_SECTION 0xE800 +#define mmDCORE0_HIF1_SPECIAL_BASE 0x4124E80ull +#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF2_BASE 0x4128000ull +#define DCORE0_HIF2_MAX_OFFSET 0x1000 +#define DCORE0_HIF2_SECTION 0xE800 +#define mmDCORE0_HIF2_SPECIAL_BASE 0x4128E80ull +#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF3_BASE 0x412C000ull +#define DCORE0_HIF3_MAX_OFFSET 0x1000 +#define DCORE0_HIF3_SECTION 0xE800 +#define mmDCORE0_HIF3_SPECIAL_BASE 0x412CE80ull +#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE0_RTR0_CTRL_BASE 0x4140000ull +#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull +#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_H3_BASE 0x4141000ull +#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_H3_SECTION 0xE800 +#define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull +#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull +#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull +#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull +#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull +#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull +#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_BASE 0x4144000ull +#define DCORE0_RTR0_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_SECTION 0x3000 +#define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull +#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull +#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull +#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR0_SPECIAL_BASE 0x4144E80ull +#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull +#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR1_CTRL_BASE 0x4148000ull +#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull +#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_H3_BASE 0x4149000ull +#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_H3_SECTION 0xE800 +#define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull +#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull +#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull +#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull +#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull +#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull +#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_BASE 0x414C000ull +#define DCORE0_RTR1_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_SECTION 0x3000 +#define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull +#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull +#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull +#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR1_SPECIAL_BASE 0x414CE80ull +#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull +#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR2_CTRL_BASE 0x4150000ull +#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull +#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_H3_BASE 0x4151000ull +#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_H3_SECTION 0xE800 +#define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull +#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull +#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull +#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull +#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull +#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull +#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_BASE 0x4154000ull +#define DCORE0_RTR2_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_SECTION 0x3000 +#define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull +#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull +#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull +#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR2_SPECIAL_BASE 0x4154E80ull +#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull +#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR3_CTRL_BASE 0x4158000ull +#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull +#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_H3_BASE 0x4159000ull +#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_H3_SECTION 0xE800 +#define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull +#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull +#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull +#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull +#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull +#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull +#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_BASE 0x415C000ull +#define DCORE0_RTR3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_SECTION 0x3000 +#define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull +#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull +#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull +#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR3_SPECIAL_BASE 0x415CE80ull +#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull +#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR4_CTRL_BASE 0x4160000ull +#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull +#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_H3_BASE 0x4161000ull +#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_H3_SECTION 0xE800 +#define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull +#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull +#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull +#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull +#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull +#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull +#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_BASE 0x4164000ull +#define DCORE0_RTR4_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_SECTION 0x3000 +#define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull +#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull +#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull +#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR4_SPECIAL_BASE 0x4164E80ull +#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull +#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR5_CTRL_BASE 0x4168000ull +#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull +#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_H3_BASE 0x4169000ull +#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_H3_SECTION 0xE800 +#define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull +#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull +#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull +#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull +#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull +#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull +#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_BASE 0x416C000ull +#define DCORE0_RTR5_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_SECTION 0x3000 +#define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull +#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull +#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull +#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR5_SPECIAL_BASE 0x416CE80ull +#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull +#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR6_CTRL_BASE 0x4170000ull +#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull +#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_H3_BASE 0x4171000ull +#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_H3_SECTION 0xE800 +#define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull +#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull +#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull +#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull +#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull +#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull +#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_BASE 0x4174000ull +#define DCORE0_RTR6_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_SECTION 0x3000 +#define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull +#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull +#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull +#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR6_SPECIAL_BASE 0x4174E80ull +#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull +#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR7_CTRL_BASE 0x4178000ull +#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull +#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_H3_BASE 0x4179000ull +#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_H3_SECTION 0xE800 +#define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull +#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull +#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull +#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull +#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull +#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull +#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_BASE 0x417C000ull +#define DCORE0_RTR7_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_SECTION 0x3000 +#define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull +#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull +#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull +#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR7_SPECIAL_BASE 0x417CE80ull +#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull +#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_SRAM0_BANK_BASE 0x4180000ull +#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull +#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM0_RTR_BASE 0x4181000ull +#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull +#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM1_BANK_BASE 0x4188000ull +#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull +#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM1_RTR_BASE 0x4189000ull +#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull +#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM2_BANK_BASE 0x4190000ull +#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull +#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM2_RTR_BASE 0x4191000ull +#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull +#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM3_BANK_BASE 0x4198000ull +#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull +#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM3_RTR_BASE 0x4199000ull +#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull +#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM4_BANK_BASE 0x41A0000ull +#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull +#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM4_RTR_BASE 0x41A1000ull +#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull +#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM5_BANK_BASE 0x41A8000ull +#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull +#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM5_RTR_BASE 0x41A9000ull +#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull +#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM6_BANK_BASE 0x41B0000ull +#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull +#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM6_RTR_BASE 0x41B1000ull +#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull +#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM7_BANK_BASE 0x41B8000ull +#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull +#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM7_RTR_BASE 0x41B9000ull +#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull +#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull +#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull +#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_EDMA0_QM_BASE 0x41CA000ull +#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_SECTION 0x9000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull +#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull +#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull +#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull +#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull +#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA0_CORE_BASE 0x41CB000ull +#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull +#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull +#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull +#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull +#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull +#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull +#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull +#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_EDMA1_QM_BASE 0x41DA000ull +#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_SECTION 0x9000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull +#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull +#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull +#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull +#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull +#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA1_CORE_BASE 0x41DB000ull +#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull +#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull +#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull +#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull +#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull +#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_DEC0_CMD_BASE 0x41E0000ull +#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC0_CMD_SECTION 0x1000 +#define mmDCORE0_DEC0_VSI_BASE 0x41E1000ull +#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC0_VSI_SECTION 0x1000 +#define mmDCORE0_DEC0_L2C_BASE 0x41E2000ull +#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC0_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull +#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC0_CTRL_BASE 0x41E4000ull +#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull +#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull +#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE0_DEC1_CMD_BASE 0x41F0000ull +#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC1_CMD_SECTION 0x1000 +#define mmDCORE0_DEC1_VSI_BASE 0x41F1000ull +#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC1_VSI_SECTION 0x1000 +#define mmDCORE0_DEC1_L2C_BASE 0x41F2000ull +#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC1_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull +#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC1_CTRL_BASE 0x41F4000ull +#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull +#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull +#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE1_TPC0_QM_DCCM_BASE 0x4200000ull +#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull +#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC0_QM_BASE 0x420A000ull +#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_SECTION 0x9000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull +#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull +#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull +#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_CGM_BASE 0x420AD80ull +#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull +#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_CFG_BASE 0x420B000ull +#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_CFG_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull +#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull +#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull +#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull +#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull +#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull +#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull +#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull +#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull +#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull +#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull +#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull +#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC1_QM_DCCM_BASE 0x4210000ull +#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull +#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC1_QM_BASE 0x421A000ull +#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_SECTION 0x9000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull +#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull +#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull +#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_CGM_BASE 0x421AD80ull +#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull +#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_CFG_BASE 0x421B000ull +#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_CFG_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull +#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull +#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull +#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull +#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull +#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull +#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull +#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull +#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull +#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull +#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull +#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull +#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC2_QM_DCCM_BASE 0x4220000ull +#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull +#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC2_QM_BASE 0x422A000ull +#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_SECTION 0x9000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull +#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull +#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull +#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_CGM_BASE 0x422AD80ull +#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull +#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_CFG_BASE 0x422B000ull +#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_CFG_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull +#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull +#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull +#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull +#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull +#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull +#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull +#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull +#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull +#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull +#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull +#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull +#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC3_QM_DCCM_BASE 0x4230000ull +#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull +#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC3_QM_BASE 0x423A000ull +#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_SECTION 0x9000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull +#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull +#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull +#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_CGM_BASE 0x423AD80ull +#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull +#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_CFG_BASE 0x423B000ull +#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_CFG_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull +#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull +#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull +#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull +#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull +#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull +#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull +#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull +#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull +#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull +#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull +#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull +#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC4_QM_DCCM_BASE 0x4240000ull +#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull +#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC4_QM_BASE 0x424A000ull +#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_SECTION 0x9000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull +#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull +#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull +#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_CGM_BASE 0x424AD80ull +#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull +#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_CFG_BASE 0x424B000ull +#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_CFG_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull +#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull +#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull +#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull +#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull +#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull +#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull +#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull +#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull +#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull +#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull +#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull +#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC5_QM_DCCM_BASE 0x4250000ull +#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull +#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC5_QM_BASE 0x425A000ull +#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_SECTION 0x9000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull +#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull +#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull +#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_CGM_BASE 0x425AD80ull +#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull +#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_CFG_BASE 0x425B000ull +#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_CFG_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull +#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull +#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull +#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull +#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull +#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull +#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull +#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull +#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull +#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull +#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull +#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull +#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE1_HMMU0_MMU_BASE 0x4280000ull +#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull +#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU0_STLB_BASE 0x4281000ull +#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull +#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull +#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull +#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU1_MMU_BASE 0x4290000ull +#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull +#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU1_STLB_BASE 0x4291000ull +#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull +#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull +#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull +#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU2_MMU_BASE 0x42A0000ull +#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull +#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU2_STLB_BASE 0x42A1000ull +#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull +#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull +#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull +#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU3_MMU_BASE 0x42B0000ull +#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull +#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU3_STLB_BASE 0x42B1000ull +#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull +#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull +#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull +#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull +#define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull +#define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull +#define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull +#define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull +#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull +#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_BASE 0x42CA000ull +#define DCORE1_MME_QM_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_SECTION 0x9000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull +#define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull +#define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull +#define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull +#define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_MME_QM_CGM_BASE 0x42CAD80ull +#define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull +#define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_BASE 0x42CB000ull +#define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull +#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull +#define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull +#define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_BASE 0x42CC000ull +#define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull +#define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_EU_BIST_BASE 0x42CD000ull +#define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE1_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull +#define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull +#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull +#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull +#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull +#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull +#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull +#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull +#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull +#define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull +#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_BASE 0x42D0000ull +#define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_SECTION 0xE800 +#define mmDCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull +#define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull +#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull +#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull +#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE1_BASE 0x42D8000ull +#define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_SECTION 0xE800 +#define mmDCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull +#define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull +#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull +#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull +#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE2_BASE 0x42E0000ull +#define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_SECTION 0xE800 +#define mmDCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull +#define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull +#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull +#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull +#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE3_BASE 0x42E8000ull +#define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_SECTION 0xE800 +#define mmDCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull +#define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull +#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull +#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull +#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE4_BASE 0x42F0000ull +#define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_SECTION 0xE800 +#define mmDCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull +#define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull +#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull +#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull +#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_ACC_BASE 0x42F8000ull +#define DCORE1_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_SECTION 0xE800 +#define mmDCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull +#define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull +#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull +#define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull +#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull +#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull +#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull +#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull +#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull +#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull +#define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull +#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull +#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull +#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull +#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull +#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull +#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull +#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HIF0_BASE 0x4320000ull +#define DCORE1_HIF0_MAX_OFFSET 0x1000 +#define DCORE1_HIF0_SECTION 0xE800 +#define mmDCORE1_HIF0_SPECIAL_BASE 0x4320E80ull +#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF1_BASE 0x4324000ull +#define DCORE1_HIF1_MAX_OFFSET 0x1000 +#define DCORE1_HIF1_SECTION 0xE800 +#define mmDCORE1_HIF1_SPECIAL_BASE 0x4324E80ull +#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF2_BASE 0x4328000ull +#define DCORE1_HIF2_MAX_OFFSET 0x1000 +#define DCORE1_HIF2_SECTION 0xE800 +#define mmDCORE1_HIF2_SPECIAL_BASE 0x4328E80ull +#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF3_BASE 0x432C000ull +#define DCORE1_HIF3_MAX_OFFSET 0x1000 +#define DCORE1_HIF3_SECTION 0xE800 +#define mmDCORE1_HIF3_SPECIAL_BASE 0x432CE80ull +#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE1_RTR0_CTRL_BASE 0x4340000ull +#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull +#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_H3_BASE 0x4341000ull +#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_H3_SECTION 0xE800 +#define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull +#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull +#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull +#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull +#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull +#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull +#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_BASE 0x4344000ull +#define DCORE1_RTR0_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_SECTION 0x3000 +#define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull +#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull +#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull +#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR0_SPECIAL_BASE 0x4344E80ull +#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull +#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR1_CTRL_BASE 0x4348000ull +#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull +#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_H3_BASE 0x4349000ull +#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_H3_SECTION 0xE800 +#define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull +#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull +#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull +#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull +#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull +#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull +#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_BASE 0x434C000ull +#define DCORE1_RTR1_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_SECTION 0x3000 +#define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull +#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull +#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull +#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR1_SPECIAL_BASE 0x434CE80ull +#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull +#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR2_CTRL_BASE 0x4350000ull +#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull +#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_H3_BASE 0x4351000ull +#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_H3_SECTION 0xE800 +#define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull +#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull +#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull +#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull +#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull +#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull +#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_BASE 0x4354000ull +#define DCORE1_RTR2_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_SECTION 0x3000 +#define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull +#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull +#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull +#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR2_SPECIAL_BASE 0x4354E80ull +#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull +#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR3_CTRL_BASE 0x4358000ull +#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull +#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_H3_BASE 0x4359000ull +#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_H3_SECTION 0xE800 +#define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull +#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull +#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull +#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull +#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull +#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull +#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_BASE 0x435C000ull +#define DCORE1_RTR3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_SECTION 0x3000 +#define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull +#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull +#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull +#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR3_SPECIAL_BASE 0x435CE80ull +#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull +#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR4_CTRL_BASE 0x4360000ull +#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull +#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_H3_BASE 0x4361000ull +#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_H3_SECTION 0xE800 +#define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull +#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull +#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull +#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull +#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull +#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull +#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_BASE 0x4364000ull +#define DCORE1_RTR4_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_SECTION 0x3000 +#define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull +#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull +#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull +#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR4_SPECIAL_BASE 0x4364E80ull +#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull +#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR5_CTRL_BASE 0x4368000ull +#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull +#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_H3_BASE 0x4369000ull +#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_H3_SECTION 0xE800 +#define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull +#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull +#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull +#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull +#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull +#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull +#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_BASE 0x436C000ull +#define DCORE1_RTR5_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_SECTION 0x3000 +#define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull +#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull +#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull +#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR5_SPECIAL_BASE 0x436CE80ull +#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull +#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR6_CTRL_BASE 0x4370000ull +#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull +#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_H3_BASE 0x4371000ull +#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_H3_SECTION 0xE800 +#define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull +#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull +#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull +#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull +#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull +#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull +#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_BASE 0x4374000ull +#define DCORE1_RTR6_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_SECTION 0x3000 +#define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull +#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull +#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull +#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR6_SPECIAL_BASE 0x4374E80ull +#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull +#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR7_CTRL_BASE 0x4378000ull +#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull +#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_H3_BASE 0x4379000ull +#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_H3_SECTION 0xE800 +#define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull +#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull +#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull +#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull +#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull +#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull +#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_BASE 0x437C000ull +#define DCORE1_RTR7_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_SECTION 0x3000 +#define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull +#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull +#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull +#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR7_SPECIAL_BASE 0x437CE80ull +#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull +#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_SRAM0_BANK_BASE 0x4380000ull +#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull +#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM0_RTR_BASE 0x4381000ull +#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull +#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM1_BANK_BASE 0x4388000ull +#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull +#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM1_RTR_BASE 0x4389000ull +#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull +#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM2_BANK_BASE 0x4390000ull +#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull +#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM2_RTR_BASE 0x4391000ull +#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull +#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM3_BANK_BASE 0x4398000ull +#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull +#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM3_RTR_BASE 0x4399000ull +#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull +#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM4_BANK_BASE 0x43A0000ull +#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull +#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM4_RTR_BASE 0x43A1000ull +#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull +#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM5_BANK_BASE 0x43A8000ull +#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull +#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM5_RTR_BASE 0x43A9000ull +#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull +#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM6_BANK_BASE 0x43B0000ull +#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull +#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM6_RTR_BASE 0x43B1000ull +#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull +#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM7_BANK_BASE 0x43B8000ull +#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull +#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM7_RTR_BASE 0x43B9000ull +#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull +#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull +#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull +#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_EDMA0_QM_BASE 0x43CA000ull +#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_SECTION 0x9000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull +#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull +#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull +#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull +#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull +#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA0_CORE_BASE 0x43CB000ull +#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull +#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull +#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull +#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull +#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull +#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull +#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull +#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_EDMA1_QM_BASE 0x43DA000ull +#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_SECTION 0x9000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull +#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull +#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull +#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull +#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull +#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA1_CORE_BASE 0x43DB000ull +#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull +#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull +#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull +#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull +#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull +#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_DEC0_CMD_BASE 0x43E0000ull +#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC0_CMD_SECTION 0x1000 +#define mmDCORE1_DEC0_VSI_BASE 0x43E1000ull +#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC0_VSI_SECTION 0x1000 +#define mmDCORE1_DEC0_L2C_BASE 0x43E2000ull +#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC0_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull +#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC0_CTRL_BASE 0x43E4000ull +#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull +#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull +#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE1_DEC1_CMD_BASE 0x43F0000ull +#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC1_CMD_SECTION 0x1000 +#define mmDCORE1_DEC1_VSI_BASE 0x43F1000ull +#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC1_VSI_SECTION 0x1000 +#define mmDCORE1_DEC1_L2C_BASE 0x43F2000ull +#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC1_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull +#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC1_CTRL_BASE 0x43F4000ull +#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull +#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull +#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE2_TPC0_QM_DCCM_BASE 0x4400000ull +#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull +#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC0_QM_BASE 0x440A000ull +#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_SECTION 0x9000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull +#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull +#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull +#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_CGM_BASE 0x440AD80ull +#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull +#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_CFG_BASE 0x440B000ull +#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_CFG_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull +#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull +#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull +#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull +#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull +#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull +#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull +#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull +#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull +#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull +#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull +#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull +#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC1_QM_DCCM_BASE 0x4410000ull +#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull +#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC1_QM_BASE 0x441A000ull +#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_SECTION 0x9000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull +#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull +#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull +#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_CGM_BASE 0x441AD80ull +#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull +#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_CFG_BASE 0x441B000ull +#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_CFG_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull +#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull +#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull +#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull +#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull +#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull +#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull +#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull +#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull +#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull +#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull +#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull +#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC2_QM_DCCM_BASE 0x4420000ull +#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull +#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC2_QM_BASE 0x442A000ull +#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_SECTION 0x9000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull +#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull +#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull +#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_CGM_BASE 0x442AD80ull +#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull +#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_CFG_BASE 0x442B000ull +#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_CFG_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull +#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull +#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull +#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull +#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull +#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull +#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull +#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull +#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull +#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull +#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull +#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull +#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC3_QM_DCCM_BASE 0x4430000ull +#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull +#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC3_QM_BASE 0x443A000ull +#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_SECTION 0x9000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull +#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull +#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull +#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_CGM_BASE 0x443AD80ull +#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull +#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_CFG_BASE 0x443B000ull +#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_CFG_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull +#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull +#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull +#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull +#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull +#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull +#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull +#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull +#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull +#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull +#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull +#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull +#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC4_QM_DCCM_BASE 0x4440000ull +#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull +#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC4_QM_BASE 0x444A000ull +#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_SECTION 0x9000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull +#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull +#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull +#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_CGM_BASE 0x444AD80ull +#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull +#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_CFG_BASE 0x444B000ull +#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_CFG_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull +#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull +#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull +#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull +#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull +#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull +#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull +#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull +#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull +#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull +#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull +#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull +#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC5_QM_DCCM_BASE 0x4450000ull +#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull +#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC5_QM_BASE 0x445A000ull +#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_SECTION 0x9000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull +#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull +#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull +#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_CGM_BASE 0x445AD80ull +#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull +#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_CFG_BASE 0x445B000ull +#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_CFG_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull +#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull +#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull +#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull +#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull +#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull +#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull +#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull +#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull +#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull +#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull +#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull +#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE2_HMMU0_MMU_BASE 0x4480000ull +#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull +#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU0_STLB_BASE 0x4481000ull +#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull +#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull +#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull +#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU1_MMU_BASE 0x4490000ull +#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull +#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU1_STLB_BASE 0x4491000ull +#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull +#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull +#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull +#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU2_MMU_BASE 0x44A0000ull +#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull +#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU2_STLB_BASE 0x44A1000ull +#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull +#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull +#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull +#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU3_MMU_BASE 0x44B0000ull +#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull +#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU3_STLB_BASE 0x44B1000ull +#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull +#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull +#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull +#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull +#define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull +#define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull +#define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull +#define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull +#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull +#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_BASE 0x44CA000ull +#define DCORE2_MME_QM_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_SECTION 0x9000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull +#define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull +#define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull +#define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull +#define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_MME_QM_CGM_BASE 0x44CAD80ull +#define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull +#define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_BASE 0x44CB000ull +#define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull +#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull +#define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull +#define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_BASE 0x44CC000ull +#define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull +#define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_EU_BIST_BASE 0x44CD000ull +#define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE2_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull +#define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull +#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull +#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull +#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull +#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull +#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull +#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull +#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull +#define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull +#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_BASE 0x44D0000ull +#define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_SECTION 0xE800 +#define mmDCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull +#define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull +#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull +#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull +#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE1_BASE 0x44D8000ull +#define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_SECTION 0xE800 +#define mmDCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull +#define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull +#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull +#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull +#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE2_BASE 0x44E0000ull +#define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_SECTION 0xE800 +#define mmDCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull +#define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull +#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull +#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull +#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE3_BASE 0x44E8000ull +#define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_SECTION 0xE800 +#define mmDCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull +#define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull +#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull +#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull +#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE4_BASE 0x44F0000ull +#define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_SECTION 0xE800 +#define mmDCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull +#define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull +#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull +#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull +#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_ACC_BASE 0x44F8000ull +#define DCORE2_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_SECTION 0xE800 +#define mmDCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull +#define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull +#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull +#define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull +#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull +#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull +#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull +#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull +#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull +#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull +#define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull +#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull +#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull +#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull +#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull +#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull +#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull +#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HIF0_BASE 0x4520000ull +#define DCORE2_HIF0_MAX_OFFSET 0x1000 +#define DCORE2_HIF0_SECTION 0xE800 +#define mmDCORE2_HIF0_SPECIAL_BASE 0x4520E80ull +#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF1_BASE 0x4524000ull +#define DCORE2_HIF1_MAX_OFFSET 0x1000 +#define DCORE2_HIF1_SECTION 0xE800 +#define mmDCORE2_HIF1_SPECIAL_BASE 0x4524E80ull +#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF2_BASE 0x4528000ull +#define DCORE2_HIF2_MAX_OFFSET 0x1000 +#define DCORE2_HIF2_SECTION 0xE800 +#define mmDCORE2_HIF2_SPECIAL_BASE 0x4528E80ull +#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF3_BASE 0x452C000ull +#define DCORE2_HIF3_MAX_OFFSET 0x1000 +#define DCORE2_HIF3_SECTION 0xE800 +#define mmDCORE2_HIF3_SPECIAL_BASE 0x452CE80ull +#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE2_RTR0_CTRL_BASE 0x4540000ull +#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull +#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_H3_BASE 0x4541000ull +#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_H3_SECTION 0xE800 +#define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull +#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull +#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull +#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull +#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull +#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull +#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_BASE 0x4544000ull +#define DCORE2_RTR0_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_SECTION 0x3000 +#define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull +#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull +#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull +#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR0_SPECIAL_BASE 0x4544E80ull +#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull +#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR1_CTRL_BASE 0x4548000ull +#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull +#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_H3_BASE 0x4549000ull +#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_H3_SECTION 0xE800 +#define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull +#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull +#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull +#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull +#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull +#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull +#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_BASE 0x454C000ull +#define DCORE2_RTR1_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_SECTION 0x3000 +#define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull +#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull +#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull +#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR1_SPECIAL_BASE 0x454CE80ull +#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull +#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR2_CTRL_BASE 0x4550000ull +#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull +#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_H3_BASE 0x4551000ull +#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_H3_SECTION 0xE800 +#define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull +#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull +#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull +#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull +#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull +#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull +#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_BASE 0x4554000ull +#define DCORE2_RTR2_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_SECTION 0x3000 +#define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull +#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull +#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull +#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR2_SPECIAL_BASE 0x4554E80ull +#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull +#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR3_CTRL_BASE 0x4558000ull +#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull +#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_H3_BASE 0x4559000ull +#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_H3_SECTION 0xE800 +#define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull +#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull +#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull +#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull +#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull +#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull +#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_BASE 0x455C000ull +#define DCORE2_RTR3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_SECTION 0x3000 +#define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull +#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull +#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull +#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR3_SPECIAL_BASE 0x455CE80ull +#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull +#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR4_CTRL_BASE 0x4560000ull +#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull +#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_H3_BASE 0x4561000ull +#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_H3_SECTION 0xE800 +#define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull +#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull +#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull +#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull +#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull +#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull +#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_BASE 0x4564000ull +#define DCORE2_RTR4_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_SECTION 0x3000 +#define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull +#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull +#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull +#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR4_SPECIAL_BASE 0x4564E80ull +#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull +#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR5_CTRL_BASE 0x4568000ull +#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull +#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_H3_BASE 0x4569000ull +#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_H3_SECTION 0xE800 +#define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull +#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull +#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull +#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull +#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull +#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull +#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_BASE 0x456C000ull +#define DCORE2_RTR5_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_SECTION 0x3000 +#define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull +#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull +#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull +#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR5_SPECIAL_BASE 0x456CE80ull +#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull +#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR6_CTRL_BASE 0x4570000ull +#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull +#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_H3_BASE 0x4571000ull +#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_H3_SECTION 0xE800 +#define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull +#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull +#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull +#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull +#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull +#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull +#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_BASE 0x4574000ull +#define DCORE2_RTR6_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_SECTION 0x3000 +#define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull +#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull +#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull +#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR6_SPECIAL_BASE 0x4574E80ull +#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull +#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR7_CTRL_BASE 0x4578000ull +#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull +#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_H3_BASE 0x4579000ull +#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_H3_SECTION 0xE800 +#define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull +#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull +#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull +#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull +#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull +#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull +#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_BASE 0x457C000ull +#define DCORE2_RTR7_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_SECTION 0x3000 +#define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull +#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull +#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull +#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR7_SPECIAL_BASE 0x457CE80ull +#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull +#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_SRAM0_BANK_BASE 0x4580000ull +#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull +#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM0_RTR_BASE 0x4581000ull +#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull +#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM1_BANK_BASE 0x4588000ull +#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull +#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM1_RTR_BASE 0x4589000ull +#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull +#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM2_BANK_BASE 0x4590000ull +#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull +#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM2_RTR_BASE 0x4591000ull +#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull +#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM3_BANK_BASE 0x4598000ull +#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull +#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM3_RTR_BASE 0x4599000ull +#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull +#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM4_BANK_BASE 0x45A0000ull +#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull +#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM4_RTR_BASE 0x45A1000ull +#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull +#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM5_BANK_BASE 0x45A8000ull +#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull +#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM5_RTR_BASE 0x45A9000ull +#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull +#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM6_BANK_BASE 0x45B0000ull +#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull +#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM6_RTR_BASE 0x45B1000ull +#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull +#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM7_BANK_BASE 0x45B8000ull +#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull +#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM7_RTR_BASE 0x45B9000ull +#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull +#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull +#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull +#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_EDMA0_QM_BASE 0x45CA000ull +#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_SECTION 0x9000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull +#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull +#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull +#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull +#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull +#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA0_CORE_BASE 0x45CB000ull +#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull +#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull +#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull +#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull +#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull +#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull +#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull +#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_EDMA1_QM_BASE 0x45DA000ull +#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_SECTION 0x9000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull +#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull +#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull +#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull +#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull +#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA1_CORE_BASE 0x45DB000ull +#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull +#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull +#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull +#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull +#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull +#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_DEC0_CMD_BASE 0x45E0000ull +#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC0_CMD_SECTION 0x1000 +#define mmDCORE2_DEC0_VSI_BASE 0x45E1000ull +#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC0_VSI_SECTION 0x1000 +#define mmDCORE2_DEC0_L2C_BASE 0x45E2000ull +#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC0_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull +#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC0_CTRL_BASE 0x45E4000ull +#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull +#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull +#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE2_DEC1_CMD_BASE 0x45F0000ull +#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC1_CMD_SECTION 0x1000 +#define mmDCORE2_DEC1_VSI_BASE 0x45F1000ull +#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC1_VSI_SECTION 0x1000 +#define mmDCORE2_DEC1_L2C_BASE 0x45F2000ull +#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC1_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull +#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC1_CTRL_BASE 0x45F4000ull +#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull +#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull +#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE3_TPC0_QM_DCCM_BASE 0x4600000ull +#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull +#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC0_QM_BASE 0x460A000ull +#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_SECTION 0x9000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull +#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull +#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull +#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_CGM_BASE 0x460AD80ull +#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull +#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_CFG_BASE 0x460B000ull +#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_CFG_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull +#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull +#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull +#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull +#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull +#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull +#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull +#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull +#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull +#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull +#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull +#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull +#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC1_QM_DCCM_BASE 0x4610000ull +#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull +#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC1_QM_BASE 0x461A000ull +#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_SECTION 0x9000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull +#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull +#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull +#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_CGM_BASE 0x461AD80ull +#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull +#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_CFG_BASE 0x461B000ull +#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_CFG_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull +#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull +#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull +#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull +#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull +#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull +#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull +#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull +#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull +#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull +#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull +#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull +#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC2_QM_DCCM_BASE 0x4620000ull +#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull +#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC2_QM_BASE 0x462A000ull +#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_SECTION 0x9000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull +#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull +#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull +#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_CGM_BASE 0x462AD80ull +#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull +#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_CFG_BASE 0x462B000ull +#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_CFG_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull +#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull +#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull +#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull +#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull +#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull +#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull +#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull +#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull +#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull +#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull +#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull +#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC3_QM_DCCM_BASE 0x4630000ull +#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull +#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC3_QM_BASE 0x463A000ull +#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_SECTION 0x9000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull +#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull +#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull +#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_CGM_BASE 0x463AD80ull +#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull +#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_CFG_BASE 0x463B000ull +#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_CFG_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull +#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull +#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull +#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull +#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull +#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull +#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull +#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull +#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull +#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull +#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull +#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull +#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC4_QM_DCCM_BASE 0x4640000ull +#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull +#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC4_QM_BASE 0x464A000ull +#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_SECTION 0x9000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull +#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull +#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull +#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_CGM_BASE 0x464AD80ull +#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull +#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_CFG_BASE 0x464B000ull +#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_CFG_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull +#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull +#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull +#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull +#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull +#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull +#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull +#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull +#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull +#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull +#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull +#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull +#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC5_QM_DCCM_BASE 0x4650000ull +#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull +#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC5_QM_BASE 0x465A000ull +#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_SECTION 0x9000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull +#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull +#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull +#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_CGM_BASE 0x465AD80ull +#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull +#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_CFG_BASE 0x465B000ull +#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_CFG_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull +#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull +#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull +#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull +#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull +#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull +#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull +#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull +#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull +#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull +#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull +#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull +#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE3_HMMU0_MMU_BASE 0x4680000ull +#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull +#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU0_STLB_BASE 0x4681000ull +#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull +#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull +#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull +#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU1_MMU_BASE 0x4690000ull +#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull +#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU1_STLB_BASE 0x4691000ull +#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull +#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull +#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull +#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU2_MMU_BASE 0x46A0000ull +#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull +#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU2_STLB_BASE 0x46A1000ull +#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull +#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull +#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull +#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU3_MMU_BASE 0x46B0000ull +#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull +#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU3_STLB_BASE 0x46B1000ull +#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull +#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull +#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull +#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull +#define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull +#define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull +#define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull +#define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull +#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull +#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_BASE 0x46CA000ull +#define DCORE3_MME_QM_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_SECTION 0x9000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull +#define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull +#define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull +#define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull +#define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_MME_QM_CGM_BASE 0x46CAD80ull +#define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull +#define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_BASE 0x46CB000ull +#define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull +#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull +#define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull +#define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_BASE 0x46CC000ull +#define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull +#define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_EU_BIST_BASE 0x46CD000ull +#define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE3_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull +#define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull +#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull +#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull +#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull +#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull +#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull +#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull +#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull +#define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull +#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_BASE 0x46D0000ull +#define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_SECTION 0xE800 +#define mmDCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull +#define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull +#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull +#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull +#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE1_BASE 0x46D8000ull +#define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_SECTION 0xE800 +#define mmDCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull +#define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull +#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull +#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull +#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE2_BASE 0x46E0000ull +#define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_SECTION 0xE800 +#define mmDCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull +#define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull +#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull +#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull +#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE3_BASE 0x46E8000ull +#define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_SECTION 0xE800 +#define mmDCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull +#define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull +#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull +#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull +#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE4_BASE 0x46F0000ull +#define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_SECTION 0xE800 +#define mmDCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull +#define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull +#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull +#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull +#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_ACC_BASE 0x46F8000ull +#define DCORE3_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_SECTION 0xE800 +#define mmDCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull +#define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull +#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull +#define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull +#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull +#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull +#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull +#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull +#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull +#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull +#define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull +#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull +#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull +#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull +#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull +#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull +#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull +#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HIF0_BASE 0x4720000ull +#define DCORE3_HIF0_MAX_OFFSET 0x1000 +#define DCORE3_HIF0_SECTION 0xE800 +#define mmDCORE3_HIF0_SPECIAL_BASE 0x4720E80ull +#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF1_BASE 0x4724000ull +#define DCORE3_HIF1_MAX_OFFSET 0x1000 +#define DCORE3_HIF1_SECTION 0xE800 +#define mmDCORE3_HIF1_SPECIAL_BASE 0x4724E80ull +#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF2_BASE 0x4728000ull +#define DCORE3_HIF2_MAX_OFFSET 0x1000 +#define DCORE3_HIF2_SECTION 0xE800 +#define mmDCORE3_HIF2_SPECIAL_BASE 0x4728E80ull +#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF3_BASE 0x472C000ull +#define DCORE3_HIF3_MAX_OFFSET 0x1000 +#define DCORE3_HIF3_SECTION 0xE800 +#define mmDCORE3_HIF3_SPECIAL_BASE 0x472CE80ull +#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE3_RTR0_CTRL_BASE 0x4740000ull +#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull +#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_H3_BASE 0x4741000ull +#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_H3_SECTION 0xE800 +#define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull +#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull +#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull +#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull +#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull +#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull +#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_BASE 0x4744000ull +#define DCORE3_RTR0_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_SECTION 0x3000 +#define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull +#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull +#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull +#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR0_SPECIAL_BASE 0x4744E80ull +#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull +#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR1_CTRL_BASE 0x4748000ull +#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull +#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_H3_BASE 0x4749000ull +#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_H3_SECTION 0xE800 +#define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull +#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull +#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull +#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull +#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull +#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull +#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_BASE 0x474C000ull +#define DCORE3_RTR1_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_SECTION 0x3000 +#define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull +#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull +#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull +#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR1_SPECIAL_BASE 0x474CE80ull +#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull +#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR2_CTRL_BASE 0x4750000ull +#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull +#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_H3_BASE 0x4751000ull +#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_H3_SECTION 0xE800 +#define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull +#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull +#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull +#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull +#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull +#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull +#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_BASE 0x4754000ull +#define DCORE3_RTR2_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_SECTION 0x3000 +#define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull +#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull +#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull +#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR2_SPECIAL_BASE 0x4754E80ull +#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull +#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR3_CTRL_BASE 0x4758000ull +#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull +#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_H3_BASE 0x4759000ull +#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_H3_SECTION 0xE800 +#define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull +#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull +#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull +#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull +#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull +#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull +#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_BASE 0x475C000ull +#define DCORE3_RTR3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_SECTION 0x3000 +#define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull +#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull +#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull +#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR3_SPECIAL_BASE 0x475CE80ull +#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull +#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR4_CTRL_BASE 0x4760000ull +#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull +#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_H3_BASE 0x4761000ull +#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_H3_SECTION 0xE800 +#define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull +#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull +#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull +#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull +#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull +#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull +#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_BASE 0x4764000ull +#define DCORE3_RTR4_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_SECTION 0x3000 +#define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull +#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull +#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull +#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR4_SPECIAL_BASE 0x4764E80ull +#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull +#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR5_CTRL_BASE 0x4768000ull +#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull +#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_H3_BASE 0x4769000ull +#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_H3_SECTION 0xE800 +#define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull +#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull +#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull +#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull +#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull +#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull +#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_BASE 0x476C000ull +#define DCORE3_RTR5_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_SECTION 0x3000 +#define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull +#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull +#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull +#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR5_SPECIAL_BASE 0x476CE80ull +#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull +#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR6_CTRL_BASE 0x4770000ull +#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull +#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_H3_BASE 0x4771000ull +#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_H3_SECTION 0xE800 +#define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull +#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull +#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull +#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull +#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull +#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull +#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_BASE 0x4774000ull +#define DCORE3_RTR6_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_SECTION 0x3000 +#define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull +#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull +#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull +#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR6_SPECIAL_BASE 0x4774E80ull +#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull +#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR7_CTRL_BASE 0x4778000ull +#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull +#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_H3_BASE 0x4779000ull +#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_H3_SECTION 0xE800 +#define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull +#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull +#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull +#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull +#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull +#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull +#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_BASE 0x477C000ull +#define DCORE3_RTR7_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_SECTION 0x3000 +#define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull +#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull +#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull +#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR7_SPECIAL_BASE 0x477CE80ull +#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull +#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_SRAM0_BANK_BASE 0x4780000ull +#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull +#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM0_RTR_BASE 0x4781000ull +#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull +#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM1_BANK_BASE 0x4788000ull +#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull +#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM1_RTR_BASE 0x4789000ull +#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull +#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM2_BANK_BASE 0x4790000ull +#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull +#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM2_RTR_BASE 0x4791000ull +#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull +#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM3_BANK_BASE 0x4798000ull +#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull +#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM3_RTR_BASE 0x4799000ull +#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull +#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM4_BANK_BASE 0x47A0000ull +#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull +#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM4_RTR_BASE 0x47A1000ull +#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull +#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM5_BANK_BASE 0x47A8000ull +#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull +#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM5_RTR_BASE 0x47A9000ull +#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull +#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM6_BANK_BASE 0x47B0000ull +#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull +#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM6_RTR_BASE 0x47B1000ull +#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull +#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM7_BANK_BASE 0x47B8000ull +#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull +#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM7_RTR_BASE 0x47B9000ull +#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull +#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull +#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull +#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_EDMA0_QM_BASE 0x47CA000ull +#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_SECTION 0x9000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull +#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull +#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull +#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull +#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull +#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA0_CORE_BASE 0x47CB000ull +#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull +#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull +#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull +#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull +#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull +#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull +#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull +#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_EDMA1_QM_BASE 0x47DA000ull +#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_SECTION 0x9000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47DA940ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47DA948ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47DA950ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47DA958ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47DA960ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47DA968ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47DA970ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47DA978ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x47DAB00ull +#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x47DAB80ull +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_DBG_HBW_BASE 0x47DAC00ull +#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_DBG_LBW_BASE 0x47DAC80ull +#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_CGM_BASE 0x47DAD80ull +#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_SPECIAL_BASE 0x47DAE80ull +#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA1_CORE_BASE 0x47DB000ull +#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x47DB800ull +#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE3_EDMA1_CORE_CTX_BASE 0x47DB860ull +#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x47DBE00ull +#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE3_EDMA1_CORE_SPECIAL_BASE 0x47DBE80ull +#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x47DC000ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x47DC200ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x47DC400ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x47DC600ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x47DC800ull +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x47DCA80ull +#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x47DCB00ull +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x47DCB80ull +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x47DCC00ull +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x47DCD80ull +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x47DCE80ull +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_DEC0_CMD_BASE 0x47E0000ull +#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC0_CMD_SECTION 0x1000 +#define mmDCORE3_DEC0_VSI_BASE 0x47E1000ull +#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC0_VSI_SECTION 0x1000 +#define mmDCORE3_DEC0_L2C_BASE 0x47E2000ull +#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC0_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_BASE 0x47E3000ull +#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47E3800ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47E3900ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47E3A00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47E3B00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x47E3C00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x47E3E80ull +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC0_CTRL_BASE 0x47E4000ull +#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE3_VDEC0_CTRL_SPECIAL_BASE 0x47E4E80ull +#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x47E5000ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x47E5200ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x47E5400ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x47E5600ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x47E5800ull +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x47E5A80ull +#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x47E5B00ull +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x47E5B80ull +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x47E5C00ull +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x47E5D80ull +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x47E5E80ull +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE3_DEC1_CMD_BASE 0x47F0000ull +#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC1_CMD_SECTION 0x1000 +#define mmDCORE3_DEC1_VSI_BASE 0x47F1000ull +#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC1_VSI_SECTION 0x1000 +#define mmDCORE3_DEC1_L2C_BASE 0x47F2000ull +#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC1_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_BASE 0x47F3000ull +#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47F3800ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47F3900ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47F3A00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47F3B00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x47F3C00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x47F3E80ull +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC1_CTRL_BASE 0x47F4000ull +#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE3_VDEC1_CTRL_SPECIAL_BASE 0x47F4E80ull +#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x47F5000ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x47F5200ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x47F5400ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x47F5600ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x47F5800ull +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x47F5A80ull +#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x47F5B00ull +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x47F5B80ull +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x47F5C00ull +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x47F5D80ull +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x47F5E80ull +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmGIC_BASE 0x4800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x4C01000ull +#define PCIE_WRAP_MAX_OFFSET 0x1000 +#define PCIE_WRAP_SECTION 0xE800 +#define mmPCIE_WRAP_SPECIAL_BASE 0x4C01E80ull +#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_WRAP_SPECIAL_SECTION 0x1800 +#define mmPCIE_DBI_BASE 0x4C02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x4C04000ull +#define PCIE_CORE_MAX_OFFSET 0x1000 +#define PCIE_CORE_SECTION 0xE800 +#define mmPCIE_CORE_SPECIAL_BASE 0x4C04E80ull +#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_CORE_SPECIAL_SECTION 0x2180 +#define mmPCIE_AUX_BASE 0x4C07000ull +#define PCIE_AUX_MAX_OFFSET 0x1000 +#define PCIE_AUX_SECTION 0xE800 +#define mmPCIE_AUX_SPECIAL_BASE 0x4C07E80ull +#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_AUX_SPECIAL_SECTION 0x8180 +#define mmPCIE_PHY_BASE 0x4C10000ull +#define PCIE_PHY_MAX_OFFSET 0x1000 +#define PCIE_PHY_SECTION 0xE800 +#define mmPCIE_PHY_SPECIAL_BASE 0x4C10E80ull +#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_PHY_SPECIAL_SECTION 0x2180 +#define mmPCIE_MSI_BASE 0x4C13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x1000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C14000ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C14200ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C14400ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C14600ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x4C14800ull +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x4C14A80ull +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x4C14B00ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x4C14B80ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x4C14C00ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x4C14D80ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x4C14E80ull +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C15000ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C15200ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C15400ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C15600ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x4C15800ull +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x4C15A80ull +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x4C15B00ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x4C15B80ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x4C15C00ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x4C15D80ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x4C15E80ull +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C16000ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C16200ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C16400ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C16600ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x4C16800ull +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x4C16A80ull +#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x4C16B00ull +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x4C16B80ull +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x4C16C00ull +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x4C16D80ull +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x4C16E80ull +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_MSIX_BASE 0x4C17000ull +#define PCIE_MSIX_MAX_OFFSET 0x4000 +#define PCIE_MSIX_SECTION 0x29000 +#define mmPSOC_I2C_M0_BASE 0x4C40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x4C41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x4C42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x4C43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x1000 +#define mmPSOC_QSPI_BASE 0x4C44000ull +#define PSOC_QSPI_MAX_OFFSET 0x1000 +#define PSOC_QSPI_SECTION 0x1000 +#define mmPSOC_UART_0_BASE 0x4C45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x4C46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x4C47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x4C48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x4C49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x4C4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_EFUSE_SECTION 0xE800 +#define mmPSOC_EFUSE_SPECIAL_BASE 0x4C4AE80ull +#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_EFUSE_SPECIAL_SECTION 0x1800 +#define mmPSOC_GLOBAL_CONF_BASE 0x4C4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000 +#define PSOC_GLOBAL_CONF_SECTION 0xE800 +#define mmPSOC_GLOBAL_CONF_SPECIAL_BASE 0x4C4BE80ull +#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO0_BASE 0x4C4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x4C4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x4C4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1000 +#define PSOC_BTL_SECTION 0xE800 +#define mmPSOC_BTL_SPECIAL_BASE 0x4C4EE80ull +#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_BTL_SPECIAL_SECTION 0x1800 +#define mmPSOC_CS_TRACE_BASE 0x4C4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1000 +#define PSOC_CS_TRACE_SECTION 0xE800 +#define mmPSOC_CS_TRACE_SPECIAL_BASE 0x4C4FE80ull +#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO2_BASE 0x4C50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x4C51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x2000 +#define mmPSOC_DFT_EFUSE_BASE 0x4C53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_DFT_EFUSE_SECTION 0xE800 +#define mmPSOC_DFT_EFUSE_SPECIAL_BASE 0x4C53E80ull +#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800 +#define mmPSOC_RPM_0_BASE 0x4C54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x1000 +#define PSOC_RPM_0_SECTION 0xE800 +#define mmPSOC_RPM_0_SPECIAL_BASE 0x4C54E80ull +#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_0_SPECIAL_SECTION 0x1800 +#define mmPSOC_RPM_1_BASE 0x4C55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x1000 +#define PSOC_RPM_1_SECTION 0xE800 +#define mmPSOC_RPM_1_SPECIAL_BASE 0x4C55E80ull +#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_1_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO4_BASE 0x4C56000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_GPIO5_BASE 0x4C57000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 +#define mmPSOC_PID_BASE 0x4C58000ull +#define PSOC_PID_MAX_OFFSET 0x1000 +#define PSOC_PID_SECTION 0xE800 +#define mmPSOC_PID_SPECIAL_BASE 0x4C58E80ull +#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PID_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_CFG_BASE 0x4C59000ull +#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CFG_SECTION 0xE800 +#define mmPSOC_ARC0_CFG_SPECIAL_BASE 0x4C59E80ull +#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5A000ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5A200ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5A400ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5A600ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x4C5A800ull +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_ARC0_MSTR_IF_AXUSER_BASE 0x4C5AA80ull +#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x4C5AB00ull +#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x4C5AB80ull +#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x4C5AC00ull +#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x4C5AD80ull +#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x4C5AE80ull +#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_AUX_BASE 0x4C5B000ull +#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC0_AUX_SECTION 0xE800 +#define mmPSOC_ARC0_AUX_SPECIAL_BASE 0x4C5BE80ull +#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_CFG_BASE 0x4C5C000ull +#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CFG_SECTION 0xE800 +#define mmPSOC_ARC1_CFG_SPECIAL_BASE 0x4C5CE80ull +#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5D000ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5D200ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5D400ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5D600ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x4C5D800ull +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_ARC1_MSTR_IF_AXUSER_BASE 0x4C5DA80ull +#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x4C5DB00ull +#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x4C5DB80ull +#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x4C5DC00ull +#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x4C5DD80ull +#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x4C5DE80ull +#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_AUX_BASE 0x4C5E000ull +#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC1_AUX_SECTION 0xE800 +#define mmPSOC_ARC1_AUX_SPECIAL_BASE 0x4C5EE80ull +#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180 +#define mmPSOC_SECURITY_BASE 0x4C60000ull +#define PSOC_SECURITY_MAX_OFFSET 0x1000 +#define PSOC_SECURITY_SECTION 0xE800 +#define mmPSOC_SECURITY_SPECIAL_BASE 0x4C60E80ull +#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SECURITY_SPECIAL_SECTION 0x1800 +#define mmJT_MSTR_IF_RR_SHRD_HBW_BASE 0x4C61000ull +#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_PRVT_HBW_BASE 0x4C61200ull +#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_SHRD_LBW_BASE 0x4C61400ull +#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_PRVT_LBW_BASE 0x4C61600ull +#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmJT_MSTR_IF_E2E_CRDT_BASE 0x4C61800ull +#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmJT_MSTR_IF_AXUSER_BASE 0x4C61A80ull +#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define JT_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmJT_MSTR_IF_DBG_HBW_BASE 0x4C61B00ull +#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmJT_MSTR_IF_DBG_LBW_BASE 0x4C61B80ull +#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmJT_MSTR_IF_CORE_HBW_BASE 0x4C61C00ull +#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmJT_MSTR_IF_CORE_LBW_BASE 0x4C61D80ull +#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmJT_MSTR_IF_SPECIAL_BASE 0x4C61E80ull +#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define JT_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSMI_MSTR_IF_RR_SHRD_HBW_BASE 0x4C62000ull +#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_PRVT_HBW_BASE 0x4C62200ull +#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_SHRD_LBW_BASE 0x4C62400ull +#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_PRVT_LBW_BASE 0x4C62600ull +#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_E2E_CRDT_BASE 0x4C62800ull +#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSMI_MSTR_IF_AXUSER_BASE 0x4C62A80ull +#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SMI_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSMI_MSTR_IF_DBG_HBW_BASE 0x4C62B00ull +#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSMI_MSTR_IF_DBG_LBW_BASE 0x4C62B80ull +#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSMI_MSTR_IF_CORE_HBW_BASE 0x4C62C00ull +#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSMI_MSTR_IF_CORE_LBW_BASE 0x4C62D80ull +#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSMI_MSTR_IF_SPECIAL_BASE 0x4C62E80ull +#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x4C63000ull +#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x4C63200ull +#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x4C63400ull +#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x4C63600ull +#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_E2E_CRDT_BASE 0x4C63800ull +#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmI2C_S_MSTR_IF_AXUSER_BASE 0x4C63A80ull +#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_DBG_HBW_BASE 0x4C63B00ull +#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_DBG_LBW_BASE 0x4C63B80ull +#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_CORE_HBW_BASE 0x4C63C00ull +#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmI2C_S_MSTR_IF_CORE_LBW_BASE 0x4C63D80ull +#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmI2C_S_MSTR_IF_SPECIAL_BASE 0x4C63E80ull +#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID0_BASE 0x4C64000ull +#define PSOC_SVID0_MAX_OFFSET 0x1000 +#define PSOC_SVID0_SECTION 0xE800 +#define mmPSOC_SVID0_SPECIAL_BASE 0x4C64E80ull +#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID0_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID1_BASE 0x4C65000ull +#define PSOC_SVID1_MAX_OFFSET 0x1000 +#define PSOC_SVID1_SECTION 0xE800 +#define mmPSOC_SVID1_SPECIAL_BASE 0x4C65E80ull +#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID1_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID2_BASE 0x4C66000ull +#define PSOC_SVID2_MAX_OFFSET 0x1000 +#define PSOC_SVID2_SECTION 0xE800 +#define mmPSOC_SVID2_SPECIAL_BASE 0x4C66E80ull +#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID2_SPECIAL_SECTION 0x5180 +#define mmPSOC_MME_PLL_CTRL_BASE 0x4C6C000ull +#define PSOC_MME_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_MME_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_MME_PLL_ASIF_SLV_BASE 0x4C6C360ull +#define PSOC_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_MME_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_MME_PLL_DIV_0_RLX_BASE 0x4C6C400ull +#define PSOC_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_MME_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_MME_PLL_DIV_1_RLX_BASE 0x4C6C800ull +#define PSOC_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_MME_PLL_DIV_2_RLX_BASE 0x4C6CA00ull +#define PSOC_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_MME_PLL_DIV_3_RLX_BASE 0x4C6CC00ull +#define PSOC_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_MME_PLL_SPECIAL_BASE 0x4C6CE80ull +#define PSOC_MME_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_MME_PLL_SPECIAL_SECTION 0x1800 +#define mmPSOC_CPU_PLL_CTRL_BASE 0x4C6D000ull +#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_CPU_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_CPU_PLL_ASIF_SLV_BASE 0x4C6D360ull +#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_CPU_PLL_DIV_0_RLX_BASE 0x4C6D400ull +#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_CPU_PLL_DIV_1_RLX_BASE 0x4C6D800ull +#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_CPU_PLL_DIV_2_RLX_BASE 0x4C6DA00ull +#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_CPU_PLL_DIV_3_RLX_BASE 0x4C6DC00ull +#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_CPU_PLL_SPECIAL_BASE 0x4C6DE80ull +#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800 +#define mmPSOC_VID_PLL_CTRL_BASE 0x4C6E000ull +#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_VID_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_VID_PLL_ASIF_SLV_BASE 0x4C6E360ull +#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_VID_PLL_DIV_0_RLX_BASE 0x4C6E400ull +#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_VID_PLL_DIV_1_RLX_BASE 0x4C6E800ull +#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_VID_PLL_DIV_2_RLX_BASE 0x4C6EA00ull +#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_VID_PLL_DIV_3_RLX_BASE 0x4C6EC00ull +#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_VID_PLL_SPECIAL_BASE 0x4C6EE80ull +#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180 +#define mmPSOC_RESET_CONF_BASE 0x4C74000ull +#define PSOC_RESET_CONF_MAX_OFFSET 0x1000 +#define PSOC_RESET_CONF_SECTION 0xE800 +#define mmPSOC_RESET_CONF_SPECIAL_BASE 0x4C74E80ull +#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800 +#define mmPSOC_DFT_APB_BASE 0x4C75000ull +#define PSOC_DFT_APB_MAX_OFFSET 0x8000 +#define PSOC_DFT_APB_SECTION 0x1000 +#define mmPSOC_AVS0_BASE 0x4C76000ull +#define PSOC_AVS0_MAX_OFFSET 0x1000 +#define PSOC_AVS0_SECTION 0xE800 +#define mmPSOC_AVS0_SPECIAL_BASE 0x4C76E80ull +#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS0_SPECIAL_SECTION 0x1800 +#define mmPSOC_AVS1_BASE 0x4C77000ull +#define PSOC_AVS1_MAX_OFFSET 0x1000 +#define PSOC_AVS1_SECTION 0xE800 +#define mmPSOC_AVS1_SPECIAL_BASE 0x4C77E80ull +#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS1_SPECIAL_SECTION 0x1800 +#define mmPSOC_AVS2_BASE 0x4C78000ull +#define PSOC_AVS2_MAX_OFFSET 0x1000 +#define PSOC_AVS2_SECTION 0xE800 +#define mmPSOC_AVS2_SPECIAL_BASE 0x4C78E80ull +#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS2_SPECIAL_SECTION 0x1800 +#define mmPSOC_PWM0_BASE 0x4C79000ull +#define PSOC_PWM0_MAX_OFFSET 0x1000 +#define PSOC_PWM0_SECTION 0xE800 +#define mmPSOC_PWM0_SPECIAL_BASE 0x4C79E80ull +#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM0_SPECIAL_SECTION 0x1800 +#define mmPSOC_PWM1_BASE 0x4C7A000ull +#define PSOC_PWM1_MAX_OFFSET 0x1000 +#define PSOC_PWM1_SECTION 0xE800 +#define mmPSOC_PWM1_SPECIAL_BASE 0x4C7AE80ull +#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM1_SPECIAL_SECTION 0x1800 +#define mmSVID0_AC_BASE 0x4C7B000ull +#define SVID0_AC_MAX_OFFSET 0x1000 +#define SVID0_AC_SECTION 0xE800 +#define mmSVID0_AC_SPECIAL_BASE 0x4C7BE80ull +#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID0_AC_SPECIAL_SECTION 0x1800 +#define mmSVID1_AC_BASE 0x4C7C000ull +#define SVID1_AC_MAX_OFFSET 0x1000 +#define SVID1_AC_SECTION 0xE800 +#define mmSVID1_AC_SPECIAL_BASE 0x4C7CE80ull +#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID1_AC_SPECIAL_SECTION 0x1800 +#define mmSVID2_AC_BASE 0x4C7D000ull +#define SVID2_AC_MAX_OFFSET 0x1000 +#define SVID2_AC_SECTION 0xE800 +#define mmSVID2_AC_SPECIAL_BASE 0x4C7DE80ull +#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID2_AC_SPECIAL_SECTION 0x1180 +#define mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x4C7F000ull +#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x4C7F200ull +#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x4C7F400ull +#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x4C7F600ull +#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_E2E_CRDT_BASE 0x4C7F800ull +#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_MSTR_IF_AXUSER_BASE 0x4C7FA80ull +#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_MSTR_IF_DBG_HBW_BASE 0x4C7FB00ull +#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_MSTR_IF_DBG_LBW_BASE 0x4C7FB80ull +#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_MSTR_IF_CORE_HBW_BASE 0x4C7FC00ull +#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_MSTR_IF_CORE_LBW_BASE 0x4C7FD80ull +#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_MSTR_IF_SPECIAL_BASE 0x4C7FE80ull +#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPDMA0_QM_ARC_DCCM_BASE 0x4C80000ull +#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA0_QM_ARC_DCCM_SECTION 0x8000 +#define mmPDMA0_QM_ARC_AUX_BASE 0x4C88000ull +#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmPDMA0_QM_ARC_AUX_SPECIAL_BASE 0x4C88E80ull +#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmPDMA0_QM_BASE 0x4C8A000ull +#define PDMA0_QM_MAX_OFFSET 0x1000 +#define PDMA0_QM_SECTION 0x9000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C8A900ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C8A908ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C8A910ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C8A918ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C8A920ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C8A928ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C8A930ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C8A938ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C8A940ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C8A948ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C8A950ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C8A958ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C8A960ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C8A968ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C8A970ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C8A978ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmPDMA0_QM_AXUSER_SECURED_BASE 0x4C8AB00ull +#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmPDMA0_QM_AXUSER_NONSECURED_BASE 0x4C8AB80ull +#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmPDMA0_QM_DBG_HBW_BASE 0x4C8AC00ull +#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmPDMA0_QM_DBG_LBW_BASE 0x4C8AC80ull +#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmPDMA0_QM_CGM_BASE 0x4C8AD80ull +#define PDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA0_QM_CGM_SECTION 0x1000 +#define mmPDMA0_QM_SPECIAL_BASE 0x4C8AE80ull +#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmPDMA0_CORE_BASE 0x4C8B000ull +#define PDMA0_CORE_MAX_OFFSET 0x1000 +#define PDMA0_CORE_SECTION 0x8000 +#define mmPDMA0_CORE_CTX_AXUSER_BASE 0x4C8B800ull +#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmPDMA0_CORE_CTX_BASE 0x4C8B860ull +#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA0_CORE_CTX_SECTION 0x5A00 +#define mmPDMA0_CORE_KDMA_CGM_BASE 0x4C8BE00ull +#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmPDMA0_CORE_SPECIAL_BASE 0x4C8BE80ull +#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C8C000ull +#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C8C200ull +#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C8C400ull +#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C8C600ull +#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_E2E_CRDT_BASE 0x4C8C800ull +#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPDMA0_MSTR_IF_AXUSER_BASE 0x4C8CA80ull +#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_DBG_HBW_BASE 0x4C8CB00ull +#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_DBG_LBW_BASE 0x4C8CB80ull +#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_CORE_HBW_BASE 0x4C8CC00ull +#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPDMA0_MSTR_IF_CORE_LBW_BASE 0x4C8CD80ull +#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPDMA0_MSTR_IF_SPECIAL_BASE 0x4C8CE80ull +#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmPDMA1_QM_ARC_DCCM_BASE 0x4C90000ull +#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA1_QM_ARC_DCCM_SECTION 0x8000 +#define mmPDMA1_QM_ARC_AUX_BASE 0x4C98000ull +#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmPDMA1_QM_ARC_AUX_SPECIAL_BASE 0x4C98E80ull +#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmPDMA1_QM_BASE 0x4C9A000ull +#define PDMA1_QM_MAX_OFFSET 0x1000 +#define PDMA1_QM_SECTION 0x9000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C9A900ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C9A908ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C9A910ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C9A918ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C9A920ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C9A928ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C9A930ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C9A938ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C9A940ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C9A948ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C9A950ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C9A958ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C9A960ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C9A968ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C9A970ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C9A978ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmPDMA1_QM_AXUSER_SECURED_BASE 0x4C9AB00ull +#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmPDMA1_QM_AXUSER_NONSECURED_BASE 0x4C9AB80ull +#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmPDMA1_QM_DBG_HBW_BASE 0x4C9AC00ull +#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmPDMA1_QM_DBG_LBW_BASE 0x4C9AC80ull +#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmPDMA1_QM_CGM_BASE 0x4C9AD80ull +#define PDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA1_QM_CGM_SECTION 0x1000 +#define mmPDMA1_QM_SPECIAL_BASE 0x4C9AE80ull +#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmPDMA1_CORE_BASE 0x4C9B000ull +#define PDMA1_CORE_MAX_OFFSET 0x1000 +#define PDMA1_CORE_SECTION 0x8000 +#define mmPDMA1_CORE_CTX_AXUSER_BASE 0x4C9B800ull +#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmPDMA1_CORE_CTX_BASE 0x4C9B860ull +#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA1_CORE_CTX_SECTION 0x5A00 +#define mmPDMA1_CORE_KDMA_CGM_BASE 0x4C9BE00ull +#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmPDMA1_CORE_SPECIAL_BASE 0x4C9BE80ull +#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmPDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C9C000ull +#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C9C200ull +#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C9C400ull +#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C9C600ull +#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_E2E_CRDT_BASE 0x4C9C800ull +#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPDMA1_MSTR_IF_AXUSER_BASE 0x4C9CA80ull +#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_DBG_HBW_BASE 0x4C9CB00ull +#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_DBG_LBW_BASE 0x4C9CB80ull +#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_CORE_HBW_BASE 0x4C9CC00ull +#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPDMA1_MSTR_IF_CORE_LBW_BASE 0x4C9CD80ull +#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPDMA1_MSTR_IF_SPECIAL_BASE 0x4C9CE80ull +#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmCPU_CA53_CFG_BASE 0x4CC0000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x1000 +#define CPU_CA53_CFG_SECTION 0xE800 +#define mmCPU_CA53_CFG_SPECIAL_BASE 0x4CC0E80ull +#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800 +#define mmCPU_IF_BASE 0x4CC1000ull +#define CPU_IF_MAX_OFFSET 0x1000 +#define CPU_IF_SECTION 0xE800 +#define mmCPU_IF_SPECIAL_BASE 0x4CC1E80ull +#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_IF_SPECIAL_SECTION 0x1800 +#define mmCPU_TIMESTAMP_BASE 0x4CC2000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x1000 +#define mmCPU_MSTR_IF_RR_SHRD_HBW_BASE 0x4CC3000ull +#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_PRVT_HBW_BASE 0x4CC3200ull +#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_SHRD_LBW_BASE 0x4CC3400ull +#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_PRVT_LBW_BASE 0x4CC3600ull +#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_E2E_CRDT_BASE 0x4CC3800ull +#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmCPU_MSTR_IF_AXUSER_BASE 0x4CC3A80ull +#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define CPU_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmCPU_MSTR_IF_DBG_HBW_BASE 0x4CC3B00ull +#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmCPU_MSTR_IF_DBG_LBW_BASE 0x4CC3B80ull +#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmCPU_MSTR_IF_CORE_HBW_BASE 0x4CC3C00ull +#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmCPU_MSTR_IF_CORE_LBW_BASE 0x4CC3D80ull +#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmCPU_MSTR_IF_SPECIAL_BASE 0x4CC3E80ull +#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180 +#define mmPMMU_HBW_MMU_BASE 0x4D00000ull +#define PMMU_HBW_MMU_MAX_OFFSET 0x1000 +#define PMMU_HBW_MMU_SECTION 0xE800 +#define mmPMMU_HBW_MMU_SPECIAL_BASE 0x4D00E80ull +#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800 +#define mmPMMU_HBW_STLB_BASE 0x4D01000ull +#define PMMU_HBW_STLB_MAX_OFFSET 0x1000 +#define PMMU_HBW_STLB_SECTION 0xE800 +#define mmPMMU_HBW_STLB_SPECIAL_BASE 0x4D01E80ull +#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800 +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x4D02000ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x4D02200ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x4D02400ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x4D02600ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x4D02800ull +#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPMMU_HBW_MSTR_IF_AXUSER_BASE 0x4D02A80ull +#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x4D02B00ull +#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x4D02B80ull +#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x4D02C00ull +#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x4D02D80ull +#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPMMU_HBW_MSTR_IF_SPECIAL_BASE 0x4D02E80ull +#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPMMU_PIF_BASE 0x4D03000ull +#define PMMU_PIF_MAX_OFFSET 0x1000 +#define PMMU_PIF_SECTION 0xE800 +#define mmPMMU_PIF_SPECIAL_BASE 0x4D03E80ull +#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_PIF_SPECIAL_SECTION 0x1800 +#define mmPMMU_MME_PLL_CTRL_BASE 0x4D04000ull +#define PMMU_MME_PLL_CTRL_MAX_OFFSET 0x3540 +#define PMMU_MME_PLL_CTRL_SECTION 0x3600 +#define mmPMMU_MME_PLL_ASIF_SLV_BASE 0x4D04360ull +#define PMMU_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PMMU_MME_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPMMU_MME_PLL_DIV_0_RLX_BASE 0x4D04400ull +#define PMMU_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PMMU_MME_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPMMU_MME_PLL_DIV_1_RLX_BASE 0x4D04800ull +#define PMMU_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPMMU_MME_PLL_DIV_2_RLX_BASE 0x4D04A00ull +#define PMMU_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPMMU_MME_PLL_DIV_3_RLX_BASE 0x4D04C00ull +#define PMMU_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPMMU_MME_PLL_SPECIAL_BASE 0x4D04E80ull +#define PMMU_MME_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_MME_PLL_SPECIAL_SECTION 0x1800 +#define mmPMMU_VID_PLL_CTRL_BASE 0x4D05000ull +#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PMMU_VID_PLL_CTRL_SECTION 0x3600 +#define mmPMMU_VID_PLL_ASIF_SLV_BASE 0x4D05360ull +#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPMMU_VID_PLL_DIV_0_RLX_BASE 0x4D05400ull +#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPMMU_VID_PLL_DIV_1_RLX_BASE 0x4D05800ull +#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPMMU_VID_PLL_DIV_2_RLX_BASE 0x4D05A00ull +#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPMMU_VID_PLL_DIV_3_RLX_BASE 0x4D05C00ull +#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPMMU_VID_PLL_SPECIAL_BASE 0x4D05E80ull +#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180 +#define mmXBAR_MID_0_BASE 0x4D40000ull +#define XBAR_MID_0_MAX_OFFSET 0x1000 +#define XBAR_MID_0_SECTION 0xE800 +#define mmXBAR_MID_0_SPECIAL_BASE 0x4D40E80ull +#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_DMA_PLL_CTRL_BASE 0x4D41000ull +#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D41360ull +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D41400ull +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D41800ull +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D41A00ull +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D41C00ull +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x4D41E80ull +#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_MMU_PLL_CTRL_BASE 0x4D42000ull +#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D42360ull +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D42400ull +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D42800ull +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D42A00ull +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D42C00ull +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x4D42E80ull +#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_IF_PLL_CTRL_BASE 0x4D43000ull +#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D43360ull +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D43400ull +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D43800ull +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D43A00ull +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D43C00ull +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x4D43E80ull +#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_MESH_PLL_CTRL_BASE 0x4D44000ull +#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D44360ull +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D44400ull +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D44800ull +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D44A00ull +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D44C00ull +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x4D44E80ull +#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180 +#define mmXBAR_EDGE_0_BASE 0x4D48000ull +#define XBAR_EDGE_0_MAX_OFFSET 0x1000 +#define XBAR_EDGE_0_SECTION 0xE800 +#define mmXBAR_EDGE_0_SPECIAL_BASE 0x4D48E80ull +#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_1_BASE 0x4D50000ull +#define XBAR_MID_1_MAX_OFFSET 0x1000 +#define XBAR_MID_1_SECTION 0xE800 +#define mmXBAR_MID_1_SPECIAL_BASE 0x4D50E80ull +#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_DMA_PLL_CTRL_BASE 0x4D51000ull +#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D51360ull +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D51400ull +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D51800ull +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D51A00ull +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D51C00ull +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x4D51E80ull +#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_MMU_PLL_CTRL_BASE 0x4D52000ull +#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D52360ull +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D52400ull +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D52800ull +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D52A00ull +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D52C00ull +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x4D52E80ull +#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_IF_PLL_CTRL_BASE 0x4D53000ull +#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D53360ull +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D53400ull +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D53800ull +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D53A00ull +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D53C00ull +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x4D53E80ull +#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_MESH_PLL_CTRL_BASE 0x4D54000ull +#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D54360ull +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D54400ull +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D54800ull +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D54A00ull +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D54C00ull +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x4D54E80ull +#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_HBM_PLL_CTRL_BASE 0x4D55000ull +#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D55360ull +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D55400ull +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D55800ull +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D55A00ull +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D55C00ull +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x4D55E80ull +#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 +#define mmXBAR_EDGE_1_BASE 0x4D58000ull +#define XBAR_EDGE_1_MAX_OFFSET 0x1000 +#define XBAR_EDGE_1_SECTION 0xE800 +#define mmXBAR_EDGE_1_SPECIAL_BASE 0x4D58E80ull +#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_2_BASE 0x4D60000ull +#define XBAR_MID_2_MAX_OFFSET 0x1000 +#define XBAR_MID_2_SECTION 0xE800 +#define mmXBAR_MID_2_SPECIAL_BASE 0x4D60E80ull +#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_DMA_PLL_CTRL_BASE 0x4D61000ull +#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D61360ull +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D61400ull +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D61800ull +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D61A00ull +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D61C00ull +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x4D61E80ull +#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_MMU_PLL_CTRL_BASE 0x4D62000ull +#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D62360ull +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D62400ull +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D62800ull +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D62A00ull +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D62C00ull +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x4D62E80ull +#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_IF_PLL_CTRL_BASE 0x4D63000ull +#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D63360ull +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D63400ull +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D63800ull +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D63A00ull +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D63C00ull +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x4D63E80ull +#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_BANK_PLL_CTRL_BASE 0x4D64000ull +#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D64360ull +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D64400ull +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D64800ull +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D64A00ull +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D64C00ull +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x4D64E80ull +#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_HBM_PLL_CTRL_BASE 0x4D65000ull +#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D65360ull +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D65400ull +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D65800ull +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D65A00ull +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D65C00ull +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x4D65E80ull +#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 +#define mmXBAR_EDGE_2_BASE 0x4D68000ull +#define XBAR_EDGE_2_MAX_OFFSET 0x1000 +#define XBAR_EDGE_2_SECTION 0xE800 +#define mmXBAR_EDGE_2_SPECIAL_BASE 0x4D68E80ull +#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_3_BASE 0x4D70000ull +#define XBAR_MID_3_MAX_OFFSET 0x1000 +#define XBAR_MID_3_SECTION 0xE800 +#define mmXBAR_MID_3_SPECIAL_BASE 0x4D70E80ull +#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_DMA_PLL_CTRL_BASE 0x4D71000ull +#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D71360ull +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D71400ull +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D71800ull +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D71A00ull +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D71C00ull +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x4D71E80ull +#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_MMU_PLL_CTRL_BASE 0x4D72000ull +#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D72360ull +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D72400ull +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D72800ull +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D72A00ull +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D72C00ull +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x4D72E80ull +#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_IF_PLL_CTRL_BASE 0x4D73000ull +#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D73360ull +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D73400ull +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D73800ull +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D73A00ull +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D73C00ull +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x4D73E80ull +#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 0x4D74000ull +#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D74360ull +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D74400ull +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D74800ull +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D74A00ull +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D74C00ull +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x4D74E80ull +#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180 +#define mmXBAR_EDGE_3_BASE 0x4D78000ull +#define XBAR_EDGE_3_MAX_OFFSET 0x1000 +#define XBAR_EDGE_3_SECTION 0xE800 +#define mmXBAR_EDGE_3_SPECIAL_BASE 0x4D78E80ull +#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180 +#define mmPCIE_PMA_0_BASE 0x4D80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x40000 +#define PCIE_PMA_0_SECTION 0x40000 +#define mmPCIE_PMA_1_BASE 0x4DC0000ull +#define PCIE_PMA_1_MAX_OFFSET 0x40000 +#define PCIE_PMA_1_SECTION 0x40000 +#define mmROT0_QM_ARC_DCCM_BASE 0x4E00000ull +#define ROT0_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define ROT0_QM_ARC_DCCM_SECTION 0x8000 +#define mmROT0_QM_ARC_AUX_BASE 0x4E08000ull +#define ROT0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define ROT0_QM_ARC_AUX_SECTION 0xE800 +#define mmROT0_QM_ARC_AUX_SPECIAL_BASE 0x4E08E80ull +#define ROT0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmROT0_QM_BASE 0x4E0A000ull +#define ROT0_QM_MAX_OFFSET 0x1000 +#define ROT0_QM_SECTION 0x9000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E0A900ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E0A908ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E0A910ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E0A918ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E0A920ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E0A928ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E0A930ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E0A938ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E0A940ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E0A948ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E0A950ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E0A958ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E0A960ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E0A968ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E0A970ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E0A978ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmROT0_QM_AXUSER_SECURED_BASE 0x4E0AB00ull +#define ROT0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define ROT0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmROT0_QM_AXUSER_NONSECURED_BASE 0x4E0AB80ull +#define ROT0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define ROT0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmROT0_QM_DBG_HBW_BASE 0x4E0AC00ull +#define ROT0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT0_QM_DBG_HBW_SECTION 0x8000 +#define mmROT0_QM_DBG_LBW_BASE 0x4E0AC80ull +#define ROT0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT0_QM_DBG_LBW_SECTION 0x1000 +#define mmROT0_QM_CGM_BASE 0x4E0AD80ull +#define ROT0_QM_CGM_MAX_OFFSET 0xC000 +#define ROT0_QM_CGM_SECTION 0x1000 +#define mmROT0_QM_SPECIAL_BASE 0x4E0AE80ull +#define ROT0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_QM_SPECIAL_SECTION 0x1800 +#define mmROT0_BASE 0x4E0B000ull +#define ROT0_MAX_OFFSET 0x1000 +#define ROT0_SECTION 0x1000 +#define mmROT0_DESC_BASE 0x4E0B100ull +#define ROT0_DESC_MAX_OFFSET 0x1080 +#define ROT0_DESC_SECTION 0xD800 +#define mmROT0_SPECIAL_BASE 0x4E0BE80ull +#define ROT0_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_SPECIAL_SECTION 0x1800 +#define mmROT0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E0C000ull +#define ROT0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ROT0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E0C200ull +#define ROT0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ROT0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E0C400ull +#define ROT0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ROT0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E0C600ull +#define ROT0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ROT0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_E2E_CRDT_BASE 0x4E0C800ull +#define ROT0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ROT0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmROT0_MSTR_IF_AXUSER_BASE 0x4E0CA80ull +#define ROT0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ROT0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmROT0_MSTR_IF_DBG_HBW_BASE 0x4E0CB00ull +#define ROT0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmROT0_MSTR_IF_DBG_LBW_BASE 0x4E0CB80ull +#define ROT0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmROT0_MSTR_IF_CORE_HBW_BASE 0x4E0CC00ull +#define ROT0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ROT0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmROT0_MSTR_IF_CORE_LBW_BASE 0x4E0CD80ull +#define ROT0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ROT0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmROT0_MSTR_IF_SPECIAL_BASE 0x4E0CE80ull +#define ROT0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmROT1_QM_ARC_DCCM_BASE 0x4E10000ull +#define ROT1_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define ROT1_QM_ARC_DCCM_SECTION 0x8000 +#define mmROT1_QM_ARC_AUX_BASE 0x4E18000ull +#define ROT1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define ROT1_QM_ARC_AUX_SECTION 0xE800 +#define mmROT1_QM_ARC_AUX_SPECIAL_BASE 0x4E18E80ull +#define ROT1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmROT1_QM_BASE 0x4E1A000ull +#define ROT1_QM_MAX_OFFSET 0x1000 +#define ROT1_QM_SECTION 0x9000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E1A900ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E1A908ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E1A910ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E1A918ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E1A920ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E1A928ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E1A930ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E1A938ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E1A940ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E1A948ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E1A950ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E1A958ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E1A960ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E1A968ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E1A970ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E1A978ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmROT1_QM_AXUSER_SECURED_BASE 0x4E1AB00ull +#define ROT1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define ROT1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmROT1_QM_AXUSER_NONSECURED_BASE 0x4E1AB80ull +#define ROT1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define ROT1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmROT1_QM_DBG_HBW_BASE 0x4E1AC00ull +#define ROT1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT1_QM_DBG_HBW_SECTION 0x8000 +#define mmROT1_QM_DBG_LBW_BASE 0x4E1AC80ull +#define ROT1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT1_QM_DBG_LBW_SECTION 0x1000 +#define mmROT1_QM_CGM_BASE 0x4E1AD80ull +#define ROT1_QM_CGM_MAX_OFFSET 0xC000 +#define ROT1_QM_CGM_SECTION 0x1000 +#define mmROT1_QM_SPECIAL_BASE 0x4E1AE80ull +#define ROT1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_QM_SPECIAL_SECTION 0x1800 +#define mmROT1_BASE 0x4E1B000ull +#define ROT1_MAX_OFFSET 0x1000 +#define ROT1_SECTION 0x1000 +#define mmROT1_DESC_BASE 0x4E1B100ull +#define ROT1_DESC_MAX_OFFSET 0x1080 +#define ROT1_DESC_SECTION 0xD800 +#define mmROT1_SPECIAL_BASE 0x4E1BE80ull +#define ROT1_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_SPECIAL_SECTION 0x1800 +#define mmROT1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E1C000ull +#define ROT1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ROT1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E1C200ull +#define ROT1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ROT1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E1C400ull +#define ROT1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ROT1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E1C600ull +#define ROT1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ROT1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_E2E_CRDT_BASE 0x4E1C800ull +#define ROT1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ROT1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmROT1_MSTR_IF_AXUSER_BASE 0x4E1CA80ull +#define ROT1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ROT1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmROT1_MSTR_IF_DBG_HBW_BASE 0x4E1CB00ull +#define ROT1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmROT1_MSTR_IF_DBG_LBW_BASE 0x4E1CB80ull +#define ROT1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmROT1_MSTR_IF_CORE_HBW_BASE 0x4E1CC00ull +#define ROT1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ROT1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmROT1_MSTR_IF_CORE_LBW_BASE 0x4E1CD80ull +#define ROT1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ROT1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmROT1_MSTR_IF_SPECIAL_BASE 0x4E1CE80ull +#define ROT1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E40000ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E40E80ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_RTR_H3_BASE 0x4E41000ull +#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E41E80ull +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E42000ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E42200ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E42400ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E42600ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E42800ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E42A80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E42B00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E42B80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E42C00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E42D80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E42E80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E43000ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E43400ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E43E80ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E44000ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E44E80ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_RTR_H3_BASE 0x4E45000ull +#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E45E80ull +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E46000ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E46200ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E46400ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E46600ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E46800ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E46A80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E46B00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E46B80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E46C00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E46D80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E46E80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E47000ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E47400ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E47E80ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x4E48000ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E48E80ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_RTR_H3_BASE 0x4E49000ull +#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E49E80ull +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E4A000ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E4A200ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E4A400ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E4A600ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E4A800ull +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E4AA80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E4AB00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E4AB80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E4AC00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E4AD80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E4AE80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E4B000ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E4B400ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E4BE80ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_BASE 0x4E4C000ull +#define SFT0_MAX_OFFSET 0x1000 +#define SFT0_SECTION 0xE800 +#define mmSFT0_SPECIAL_BASE 0x4E4CE80ull +#define SFT0_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_SPECIAL_SECTION 0x3180 +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E50000ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E50E80ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_RTR_H3_BASE 0x4E51000ull +#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E51E80ull +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E52000ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E52200ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E52400ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E52600ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E52800ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E52A80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E52B00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E52B80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E52C00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E52D80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E52E80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E53000ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E53400ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E53E80ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E54000ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E54E80ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_RTR_H3_BASE 0x4E55000ull +#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E55E80ull +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E56000ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E56200ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E56400ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E56600ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E56800ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E56A80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E56B00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E56B80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E56C00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E56D80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E56E80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E57000ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E57400ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E57E80ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x4E58000ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E58E80ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_RTR_H3_BASE 0x4E59000ull +#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E59E80ull +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E5A000ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E5A200ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E5A400ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E5A600ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E5A800ull +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E5AA80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E5AB00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E5AB80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E5AC00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E5AD80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E5AE80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E5B000ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E5B400ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E5BE80ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_BASE 0x4E5C000ull +#define SFT1_MAX_OFFSET 0x1000 +#define SFT1_SECTION 0xE800 +#define mmSFT1_SPECIAL_BASE 0x4E5CE80ull +#define SFT1_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_SPECIAL_SECTION 0x3180 +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E60000ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E60E80ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_RTR_H3_BASE 0x4E61000ull +#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E61E80ull +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E62000ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E62200ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E62400ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E62600ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E62800ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E62A80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E62B00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E62B80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E62C00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E62D80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E62E80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E63000ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E63400ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E63E80ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E64000ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E64E80ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_RTR_H3_BASE 0x4E65000ull +#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E65E80ull +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E66000ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E66200ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E66400ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E66600ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E66800ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E66A80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E66B00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E66B80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E66C00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E66D80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E66E80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E67000ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E67400ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E67E80ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x4E68000ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E68E80ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_RTR_H3_BASE 0x4E69000ull +#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E69E80ull +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E6A000ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E6A200ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E6A400ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E6A600ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E6A800ull +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E6AA80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E6AB00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E6AB80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E6AC00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E6AD80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E6AE80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E6B000ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E6B400ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E6BE80ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_BASE 0x4E6C000ull +#define SFT2_MAX_OFFSET 0x1000 +#define SFT2_SECTION 0xE800 +#define mmSFT2_SPECIAL_BASE 0x4E6CE80ull +#define SFT2_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_SPECIAL_SECTION 0x3180 +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E70000ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E70E80ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_RTR_H3_BASE 0x4E71000ull +#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E71E80ull +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E72000ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E72200ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E72400ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E72600ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E72800ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E72A80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E72B00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E72B80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E72C00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E72D80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E72E80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E73000ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E73400ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E73E80ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E74000ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E74E80ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_RTR_H3_BASE 0x4E75000ull +#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E75E80ull +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E76000ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E76200ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E76400ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E76600ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E76800ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E76A80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E76B00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E76B80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E76C00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E76D80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E76E80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E77000ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E77400ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E77E80ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x4E78000ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E78E80ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_RTR_H3_BASE 0x4E79000ull +#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E79E80ull +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E7A000ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E7A200ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E7A400ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E7A600ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E7A800ull +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E7AA80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E7AB00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E7AB80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E7AC00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E7AD80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E7AE80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E7B000ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E7B400ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E7BE80ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_BASE 0x4E7C000ull +#define SFT3_MAX_OFFSET 0x1000 +#define SFT3_SECTION 0xE800 +#define mmSFT3_SPECIAL_BASE 0x4E7CE80ull +#define SFT3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_SPECIAL_SECTION 0x4180 +#define mmARC_FARM_FARM_BASE 0x4E81000ull +#define ARC_FARM_FARM_MAX_OFFSET 0x1000 +#define ARC_FARM_FARM_SECTION 0xE800 +#define mmARC_FARM_FARM_SPECIAL_BASE 0x4E81E80ull +#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x4E82000ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x4E82200ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x4E82400ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x4E82600ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x4E82800ull +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x4E82A80ull +#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x4E82B00ull +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x4E82B80ull +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x4E82C00ull +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x4E82D80ull +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x4E82E80ull +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC0_AUX_BASE 0x4E88000ull +#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC0_AUX_SPECIAL_BASE 0x4E88E80ull +#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC0_DUP_ENG_BASE 0x4E89000ull +#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x4E89900ull +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x4E89E80ull +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180 +#define mmARC_FARM_KDMA_BASE 0x4E8B000ull +#define ARC_FARM_KDMA_MAX_OFFSET 0x1000 +#define ARC_FARM_KDMA_SECTION 0x8000 +#define mmARC_FARM_KDMA_CTX_AXUSER_BASE 0x4E8B800ull +#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000 +#define mmARC_FARM_KDMA_CTX_BASE 0x4E8B860ull +#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000 +#define ARC_FARM_KDMA_CTX_SECTION 0x5A00 +#define mmARC_FARM_KDMA_KDMA_CGM_BASE 0x4E8BE00ull +#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000 +#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000 +#define mmARC_FARM_KDMA_SPECIAL_BASE 0x4E8BE80ull +#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x4E8C000ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x4E8C200ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x4E8C400ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x4E8C600ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x4E8C800ull +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x4E8CA80ull +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x4E8CB00ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x4E8CB80ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x4E8CC00ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x4E8CD80ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x4E8CE80ull +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180 +#define mmARC_FARM_ARC0_ACP_ENG_BASE 0x4E8F000ull +#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x4E8FE80ull +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC0_DCCM0_BASE 0x4E90000ull +#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC0_DCCM1_BASE 0x4E98000ull +#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC1_AUX_BASE 0x4EA8000ull +#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC1_AUX_SPECIAL_BASE 0x4EA8E80ull +#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC1_DUP_ENG_BASE 0x4EA9000ull +#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x4EA9900ull +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x4EA9E80ull +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC1_ACP_ENG_BASE 0x4EAF000ull +#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x4EAFE80ull +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC1_DCCM0_BASE 0x4EB0000ull +#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC1_DCCM1_BASE 0x4EB8000ull +#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC2_AUX_BASE 0x4EC8000ull +#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC2_AUX_SPECIAL_BASE 0x4EC8E80ull +#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC2_DUP_ENG_BASE 0x4EC9000ull +#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x4EC9900ull +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x4EC9E80ull +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC2_ACP_ENG_BASE 0x4ECF000ull +#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x4ECFE80ull +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC2_DCCM0_BASE 0x4ED0000ull +#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC2_DCCM1_BASE 0x4ED8000ull +#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC3_AUX_BASE 0x4EE8000ull +#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC3_AUX_SPECIAL_BASE 0x4EE8E80ull +#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC3_DUP_ENG_BASE 0x4EE9000ull +#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x4EE9900ull +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x4EE9E80ull +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC3_ACP_ENG_BASE 0x4EEF000ull +#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x4EEFE80ull +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC3_DCCM0_BASE 0x4EF0000ull +#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC3_DCCM1_BASE 0x4EF8000ull +#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000 +#define mmPCIE_DEC0_CMD_BASE 0x4F00000ull +#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC0_CMD_SECTION 0x1000 +#define mmPCIE_DEC0_VSI_BASE 0x4F01000ull +#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC0_VSI_SECTION 0x1000 +#define mmPCIE_DEC0_L2C_BASE 0x4F02000ull +#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC0_L2C_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_BASE 0x4F03000ull +#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F03800ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F03900ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F03A00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F03B00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x4F03C00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmPCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x4F03E80ull +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC0_CTRL_BASE 0x4F04000ull +#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CTRL_SECTION 0xE800 +#define mmPCIE_VDEC0_CTRL_SPECIAL_BASE 0x4F04E80ull +#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4F05000ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4F05200ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4F05400ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4F05600ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x4F05800ull +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x4F05A80ull +#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x4F05B00ull +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x4F05B80ull +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x4F05C00ull +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x4F05D80ull +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x4F05E80ull +#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmPCIE_DEC1_CMD_BASE 0x4F10000ull +#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC1_CMD_SECTION 0x1000 +#define mmPCIE_DEC1_VSI_BASE 0x4F11000ull +#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC1_VSI_SECTION 0x1000 +#define mmPCIE_DEC1_L2C_BASE 0x4F12000ull +#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC1_L2C_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_BASE 0x4F13000ull +#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F13800ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F13900ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F13A00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F13B00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x4F13C00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmPCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x4F13E80ull +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC1_CTRL_BASE 0x4F14000ull +#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CTRL_SECTION 0xE800 +#define mmPCIE_VDEC1_CTRL_SPECIAL_BASE 0x4F14E80ull +#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4F15000ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4F15200ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4F15400ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4F15600ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x4F15800ull +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x4F15A80ull +#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x4F15B00ull +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x4F15B80ull +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x4F15C00ull +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x4F15D80ull +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x4F15E80ull +#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180 +#define mmDCORE0_XFT_BASE 0x4F40000ull +#define DCORE0_XFT_MAX_OFFSET 0x1000 +#define DCORE0_XFT_SECTION 0xE800 +#define mmDCORE0_XFT_SPECIAL_BASE 0x4F40E80ull +#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HBM_PLL_CTRL_BASE 0x4F41000ull +#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_HBM_PLL_ASIF_SLV_BASE 0x4F41360ull +#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_HBM_PLL_DIV_0_RLX_BASE 0x4F41400ull +#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_HBM_PLL_DIV_1_RLX_BASE 0x4F41800ull +#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_HBM_PLL_DIV_2_RLX_BASE 0x4F41A00ull +#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_HBM_PLL_DIV_3_RLX_BASE 0x4F41C00ull +#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_HBM_PLL_SPECIAL_BASE 0x4F41E80ull +#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC_PLL_CTRL_BASE 0x4F42000ull +#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_TPC_PLL_ASIF_SLV_BASE 0x4F42360ull +#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_TPC_PLL_DIV_0_RLX_BASE 0x4F42400ull +#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_TPC_PLL_DIV_1_RLX_BASE 0x4F42800ull +#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_TPC_PLL_DIV_2_RLX_BASE 0x4F42A00ull +#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_TPC_PLL_DIV_3_RLX_BASE 0x4F42C00ull +#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_TPC_PLL_SPECIAL_BASE 0x4F42E80ull +#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_PCI_PLL_CTRL_BASE 0x4F43000ull +#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_PCI_PLL_ASIF_SLV_BASE 0x4F43360ull +#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_PCI_PLL_DIV_0_RLX_BASE 0x4F43400ull +#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_PCI_PLL_DIV_1_RLX_BASE 0x4F43800ull +#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_PCI_PLL_DIV_2_RLX_BASE 0x4F43A00ull +#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_PCI_PLL_DIV_3_RLX_BASE 0x4F43C00ull +#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_PCI_PLL_SPECIAL_BASE 0x4F43E80ull +#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TSTDVS_BASE 0x4F45000ull +#define DCORE0_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE0_TSTDVS_SECTION 0x1000 +#define mmDCORE0_TS_WRAP_BASE 0x4F46000ull +#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE0_TS_WRAP_SECTION 0x2000 +#define mmDCORE0_TS_WRAP_ASIF_SLV_BASE 0x4F46200ull +#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE1_XFT_BASE 0x4F50000ull +#define DCORE1_XFT_MAX_OFFSET 0x1000 +#define DCORE1_XFT_SECTION 0xE800 +#define mmDCORE1_XFT_SPECIAL_BASE 0x4F50E80ull +#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HBM_PLL_CTRL_BASE 0x4F51000ull +#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_HBM_PLL_ASIF_SLV_BASE 0x4F51360ull +#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_HBM_PLL_DIV_0_RLX_BASE 0x4F51400ull +#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_HBM_PLL_DIV_1_RLX_BASE 0x4F51800ull +#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_HBM_PLL_DIV_2_RLX_BASE 0x4F51A00ull +#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_HBM_PLL_DIV_3_RLX_BASE 0x4F51C00ull +#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_HBM_PLL_SPECIAL_BASE 0x4F51E80ull +#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC_PLL_CTRL_BASE 0x4F52000ull +#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_TPC_PLL_ASIF_SLV_BASE 0x4F52360ull +#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_TPC_PLL_DIV_0_RLX_BASE 0x4F52400ull +#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_TPC_PLL_DIV_1_RLX_BASE 0x4F52800ull +#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_TPC_PLL_DIV_2_RLX_BASE 0x4F52A00ull +#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_TPC_PLL_DIV_3_RLX_BASE 0x4F52C00ull +#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_TPC_PLL_SPECIAL_BASE 0x4F52E80ull +#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_NIC_PLL_CTRL_BASE 0x4F53000ull +#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_NIC_PLL_ASIF_SLV_BASE 0x4F53360ull +#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_NIC_PLL_DIV_0_RLX_BASE 0x4F53400ull +#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_NIC_PLL_DIV_1_RLX_BASE 0x4F53800ull +#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_NIC_PLL_DIV_2_RLX_BASE 0x4F53A00ull +#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_NIC_PLL_DIV_3_RLX_BASE 0x4F53C00ull +#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_NIC_PLL_SPECIAL_BASE 0x4F53E80ull +#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TSTDVS_BASE 0x4F55000ull +#define DCORE1_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE1_TSTDVS_SECTION 0x1000 +#define mmDCORE1_TS_WRAP_BASE 0x4F56000ull +#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE1_TS_WRAP_SECTION 0x2000 +#define mmDCORE1_TS_WRAP_ASIF_SLV_BASE 0x4F56200ull +#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE2_XFT_BASE 0x4F60000ull +#define DCORE2_XFT_MAX_OFFSET 0x1000 +#define DCORE2_XFT_SECTION 0xE800 +#define mmDCORE2_XFT_SPECIAL_BASE 0x4F60E80ull +#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HBM_PLL_CTRL_BASE 0x4F61000ull +#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_HBM_PLL_ASIF_SLV_BASE 0x4F61360ull +#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_HBM_PLL_DIV_0_RLX_BASE 0x4F61400ull +#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_HBM_PLL_DIV_1_RLX_BASE 0x4F61800ull +#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_HBM_PLL_DIV_2_RLX_BASE 0x4F61A00ull +#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_HBM_PLL_DIV_3_RLX_BASE 0x4F61C00ull +#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_HBM_PLL_SPECIAL_BASE 0x4F61E80ull +#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC_PLL_CTRL_BASE 0x4F62000ull +#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_TPC_PLL_ASIF_SLV_BASE 0x4F62360ull +#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_TPC_PLL_DIV_0_RLX_BASE 0x4F62400ull +#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_TPC_PLL_DIV_1_RLX_BASE 0x4F62800ull +#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_TPC_PLL_DIV_2_RLX_BASE 0x4F62A00ull +#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_TPC_PLL_DIV_3_RLX_BASE 0x4F62C00ull +#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_TPC_PLL_SPECIAL_BASE 0x4F62E80ull +#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180 +#define mmDCORE2_TSTDVS_BASE 0x4F65000ull +#define DCORE2_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE2_TSTDVS_SECTION 0x1000 +#define mmDCORE2_TS_WRAP_BASE 0x4F66000ull +#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE2_TS_WRAP_SECTION 0x2000 +#define mmDCORE2_TS_WRAP_ASIF_SLV_BASE 0x4F66200ull +#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE3_XFT_BASE 0x4F70000ull +#define DCORE3_XFT_MAX_OFFSET 0x1000 +#define DCORE3_XFT_SECTION 0xE800 +#define mmDCORE3_XFT_SPECIAL_BASE 0x4F70E80ull +#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HBM_PLL_CTRL_BASE 0x4F71000ull +#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_HBM_PLL_ASIF_SLV_BASE 0x4F71360ull +#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_HBM_PLL_DIV_0_RLX_BASE 0x4F71400ull +#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_HBM_PLL_DIV_1_RLX_BASE 0x4F71800ull +#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_HBM_PLL_DIV_2_RLX_BASE 0x4F71A00ull +#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_HBM_PLL_DIV_3_RLX_BASE 0x4F71C00ull +#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_HBM_PLL_SPECIAL_BASE 0x4F71E80ull +#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC_PLL_CTRL_BASE 0x4F72000ull +#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_TPC_PLL_ASIF_SLV_BASE 0x4F72360ull +#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_TPC_PLL_DIV_0_RLX_BASE 0x4F72400ull +#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_TPC_PLL_DIV_1_RLX_BASE 0x4F72800ull +#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_TPC_PLL_DIV_2_RLX_BASE 0x4F72A00ull +#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_TPC_PLL_DIV_3_RLX_BASE 0x4F72C00ull +#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_TPC_PLL_SPECIAL_BASE 0x4F72E80ull +#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_NIC_PLL_CTRL_BASE 0x4F73000ull +#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_NIC_PLL_ASIF_SLV_BASE 0x4F73360ull +#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_NIC_PLL_DIV_0_RLX_BASE 0x4F73400ull +#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_NIC_PLL_DIV_1_RLX_BASE 0x4F73800ull +#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_NIC_PLL_DIV_2_RLX_BASE 0x4F73A00ull +#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_NIC_PLL_DIV_3_RLX_BASE 0x4F73C00ull +#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_NIC_PLL_SPECIAL_BASE 0x4F73E80ull +#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TSTDVS_BASE 0x4F75000ull +#define DCORE3_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE3_TSTDVS_SECTION 0x1000 +#define mmDCORE3_TS_WRAP_BASE 0x4F76000ull +#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE3_TS_WRAP_SECTION 0x2000 +#define mmDCORE3_TS_WRAP_ASIF_SLV_BASE 0x4F76200ull +#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmPCIE_PMA_2_BASE 0x4F80000ull +#define PCIE_PMA_2_MAX_OFFSET 0x40000 +#define PCIE_PMA_2_SECTION 0x40000 +#define mmPCIE_PMA_3_BASE 0x4FC0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x40000 +#define PCIE_PMA_3_SECTION 0x40000 +#define mmHBM0_MC0_BASE 0x5000000ull +#define HBM0_MC0_MAX_OFFSET 0x1000 +#define HBM0_MC0_SECTION 0xE800 +#define mmHBM0_MC0_SPECIAL_BASE 0x5000E80ull +#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST0_BASE 0x5001000ull +#define HBM0_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST0_SECTION 0xE800 +#define mmHBM0_MC0BIST0_SPECIAL_BASE 0x5001E80ull +#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST1_BASE 0x5002000ull +#define HBM0_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST1_SECTION 0xE800 +#define mmHBM0_MC0BIST1_SPECIAL_BASE 0x5002E80ull +#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST2_BASE 0x5003000ull +#define HBM0_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST2_SECTION 0xE800 +#define mmHBM0_MC0BIST2_SPECIAL_BASE 0x5003E80ull +#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST3_BASE 0x5004000ull +#define HBM0_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST3_SECTION 0xE800 +#define mmHBM0_MC0BIST3_SPECIAL_BASE 0x5004E80ull +#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST4_BASE 0x5005000ull +#define HBM0_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST4_SECTION 0xE800 +#define mmHBM0_MC0BIST4_SPECIAL_BASE 0x5005E80ull +#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST5_BASE 0x5006000ull +#define HBM0_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST5_SECTION 0xE800 +#define mmHBM0_MC0BIST5_SPECIAL_BASE 0x5006E80ull +#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST6_BASE 0x5007000ull +#define HBM0_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST6_SECTION 0xE800 +#define mmHBM0_MC0BIST6_SPECIAL_BASE 0x5007E80ull +#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST7_BASE 0x5008000ull +#define HBM0_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST7_SECTION 0xE800 +#define mmHBM0_MC0BIST7_SPECIAL_BASE 0x5008E80ull +#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST8_MEM_BASE 0x5009000ull +#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM0_MC0BIST8_MEM_SPECIAL_BASE 0x5009E80ull +#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM0_MC1_BASE 0x5020000ull +#define HBM0_MC1_MAX_OFFSET 0x1000 +#define HBM0_MC1_SECTION 0xE800 +#define mmHBM0_MC1_SPECIAL_BASE 0x5020E80ull +#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST0_BASE 0x5021000ull +#define HBM0_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST0_SECTION 0xE800 +#define mmHBM0_MC1BIST0_SPECIAL_BASE 0x5021E80ull +#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST1_BASE 0x5022000ull +#define HBM0_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST1_SECTION 0xE800 +#define mmHBM0_MC1BIST1_SPECIAL_BASE 0x5022E80ull +#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST2_BASE 0x5023000ull +#define HBM0_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST2_SECTION 0xE800 +#define mmHBM0_MC1BIST2_SPECIAL_BASE 0x5023E80ull +#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST3_BASE 0x5024000ull +#define HBM0_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST3_SECTION 0xE800 +#define mmHBM0_MC1BIST3_SPECIAL_BASE 0x5024E80ull +#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST4_BASE 0x5025000ull +#define HBM0_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST4_SECTION 0xE800 +#define mmHBM0_MC1BIST4_SPECIAL_BASE 0x5025E80ull +#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST5_BASE 0x5026000ull +#define HBM0_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST5_SECTION 0xE800 +#define mmHBM0_MC1BIST5_SPECIAL_BASE 0x5026E80ull +#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST6_BASE 0x5027000ull +#define HBM0_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST6_SECTION 0xE800 +#define mmHBM0_MC1BIST6_SPECIAL_BASE 0x5027E80ull +#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST7_BASE 0x5028000ull +#define HBM0_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST7_SECTION 0xE800 +#define mmHBM0_MC1BIST7_SPECIAL_BASE 0x5028E80ull +#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST8_MEM_BASE 0x5029000ull +#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM0_MC1BIST8_MEM_SPECIAL_BASE 0x5029E80ull +#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM0_PHY_BASE 0x5040000ull +#define HBM0_PHY_MAX_OFFSET 0x4000 +#define HBM0_PHY_SECTION 0x40000 +#define mmHBM1_MC0_BASE 0x5080000ull +#define HBM1_MC0_MAX_OFFSET 0x1000 +#define HBM1_MC0_SECTION 0xE800 +#define mmHBM1_MC0_SPECIAL_BASE 0x5080E80ull +#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST0_BASE 0x5081000ull +#define HBM1_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST0_SECTION 0xE800 +#define mmHBM1_MC0BIST0_SPECIAL_BASE 0x5081E80ull +#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST1_BASE 0x5082000ull +#define HBM1_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST1_SECTION 0xE800 +#define mmHBM1_MC0BIST1_SPECIAL_BASE 0x5082E80ull +#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST2_BASE 0x5083000ull +#define HBM1_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST2_SECTION 0xE800 +#define mmHBM1_MC0BIST2_SPECIAL_BASE 0x5083E80ull +#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST3_BASE 0x5084000ull +#define HBM1_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST3_SECTION 0xE800 +#define mmHBM1_MC0BIST3_SPECIAL_BASE 0x5084E80ull +#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST4_BASE 0x5085000ull +#define HBM1_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST4_SECTION 0xE800 +#define mmHBM1_MC0BIST4_SPECIAL_BASE 0x5085E80ull +#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST5_BASE 0x5086000ull +#define HBM1_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST5_SECTION 0xE800 +#define mmHBM1_MC0BIST5_SPECIAL_BASE 0x5086E80ull +#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST6_BASE 0x5087000ull +#define HBM1_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST6_SECTION 0xE800 +#define mmHBM1_MC0BIST6_SPECIAL_BASE 0x5087E80ull +#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST7_BASE 0x5088000ull +#define HBM1_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST7_SECTION 0xE800 +#define mmHBM1_MC0BIST7_SPECIAL_BASE 0x5088E80ull +#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST8_MEM_BASE 0x5089000ull +#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM1_MC0BIST8_MEM_SPECIAL_BASE 0x5089E80ull +#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM1_MC1_BASE 0x50A0000ull +#define HBM1_MC1_MAX_OFFSET 0x1000 +#define HBM1_MC1_SECTION 0xE800 +#define mmHBM1_MC1_SPECIAL_BASE 0x50A0E80ull +#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST0_BASE 0x50A1000ull +#define HBM1_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST0_SECTION 0xE800 +#define mmHBM1_MC1BIST0_SPECIAL_BASE 0x50A1E80ull +#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST1_BASE 0x50A2000ull +#define HBM1_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST1_SECTION 0xE800 +#define mmHBM1_MC1BIST1_SPECIAL_BASE 0x50A2E80ull +#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST2_BASE 0x50A3000ull +#define HBM1_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST2_SECTION 0xE800 +#define mmHBM1_MC1BIST2_SPECIAL_BASE 0x50A3E80ull +#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST3_BASE 0x50A4000ull +#define HBM1_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST3_SECTION 0xE800 +#define mmHBM1_MC1BIST3_SPECIAL_BASE 0x50A4E80ull +#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST4_BASE 0x50A5000ull +#define HBM1_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST4_SECTION 0xE800 +#define mmHBM1_MC1BIST4_SPECIAL_BASE 0x50A5E80ull +#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST5_BASE 0x50A6000ull +#define HBM1_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST5_SECTION 0xE800 +#define mmHBM1_MC1BIST5_SPECIAL_BASE 0x50A6E80ull +#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST6_BASE 0x50A7000ull +#define HBM1_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST6_SECTION 0xE800 +#define mmHBM1_MC1BIST6_SPECIAL_BASE 0x50A7E80ull +#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST7_BASE 0x50A8000ull +#define HBM1_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST7_SECTION 0xE800 +#define mmHBM1_MC1BIST7_SPECIAL_BASE 0x50A8E80ull +#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST8_MEM_BASE 0x50A9000ull +#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM1_MC1BIST8_MEM_SPECIAL_BASE 0x50A9E80ull +#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM1_PHY_BASE 0x50C0000ull +#define HBM1_PHY_MAX_OFFSET 0x4000 +#define HBM1_PHY_SECTION 0x40000 +#define mmHBM2_MC0_BASE 0x5100000ull +#define HBM2_MC0_MAX_OFFSET 0x1000 +#define HBM2_MC0_SECTION 0xE800 +#define mmHBM2_MC0_SPECIAL_BASE 0x5100E80ull +#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST0_BASE 0x5101000ull +#define HBM2_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST0_SECTION 0xE800 +#define mmHBM2_MC0BIST0_SPECIAL_BASE 0x5101E80ull +#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST1_BASE 0x5102000ull +#define HBM2_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST1_SECTION 0xE800 +#define mmHBM2_MC0BIST1_SPECIAL_BASE 0x5102E80ull +#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST2_BASE 0x5103000ull +#define HBM2_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST2_SECTION 0xE800 +#define mmHBM2_MC0BIST2_SPECIAL_BASE 0x5103E80ull +#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST3_BASE 0x5104000ull +#define HBM2_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST3_SECTION 0xE800 +#define mmHBM2_MC0BIST3_SPECIAL_BASE 0x5104E80ull +#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST4_BASE 0x5105000ull +#define HBM2_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST4_SECTION 0xE800 +#define mmHBM2_MC0BIST4_SPECIAL_BASE 0x5105E80ull +#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST5_BASE 0x5106000ull +#define HBM2_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST5_SECTION 0xE800 +#define mmHBM2_MC0BIST5_SPECIAL_BASE 0x5106E80ull +#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST6_BASE 0x5107000ull +#define HBM2_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST6_SECTION 0xE800 +#define mmHBM2_MC0BIST6_SPECIAL_BASE 0x5107E80ull +#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST7_BASE 0x5108000ull +#define HBM2_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST7_SECTION 0xE800 +#define mmHBM2_MC0BIST7_SPECIAL_BASE 0x5108E80ull +#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST8_MEM_BASE 0x5109000ull +#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM2_MC0BIST8_MEM_SPECIAL_BASE 0x5109E80ull +#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM2_MC1_BASE 0x5120000ull +#define HBM2_MC1_MAX_OFFSET 0x1000 +#define HBM2_MC1_SECTION 0xE800 +#define mmHBM2_MC1_SPECIAL_BASE 0x5120E80ull +#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST0_BASE 0x5121000ull +#define HBM2_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST0_SECTION 0xE800 +#define mmHBM2_MC1BIST0_SPECIAL_BASE 0x5121E80ull +#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST1_BASE 0x5122000ull +#define HBM2_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST1_SECTION 0xE800 +#define mmHBM2_MC1BIST1_SPECIAL_BASE 0x5122E80ull +#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST2_BASE 0x5123000ull +#define HBM2_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST2_SECTION 0xE800 +#define mmHBM2_MC1BIST2_SPECIAL_BASE 0x5123E80ull +#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST3_BASE 0x5124000ull +#define HBM2_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST3_SECTION 0xE800 +#define mmHBM2_MC1BIST3_SPECIAL_BASE 0x5124E80ull +#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST4_BASE 0x5125000ull +#define HBM2_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST4_SECTION 0xE800 +#define mmHBM2_MC1BIST4_SPECIAL_BASE 0x5125E80ull +#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST5_BASE 0x5126000ull +#define HBM2_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST5_SECTION 0xE800 +#define mmHBM2_MC1BIST5_SPECIAL_BASE 0x5126E80ull +#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST6_BASE 0x5127000ull +#define HBM2_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST6_SECTION 0xE800 +#define mmHBM2_MC1BIST6_SPECIAL_BASE 0x5127E80ull +#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST7_BASE 0x5128000ull +#define HBM2_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST7_SECTION 0xE800 +#define mmHBM2_MC1BIST7_SPECIAL_BASE 0x5128E80ull +#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST8_MEM_BASE 0x5129000ull +#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM2_MC1BIST8_MEM_SPECIAL_BASE 0x5129E80ull +#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM2_PHY_BASE 0x5140000ull +#define HBM2_PHY_MAX_OFFSET 0x4000 +#define HBM2_PHY_SECTION 0x40000 +#define mmHBM3_MC0_BASE 0x5180000ull +#define HBM3_MC0_MAX_OFFSET 0x1000 +#define HBM3_MC0_SECTION 0xE800 +#define mmHBM3_MC0_SPECIAL_BASE 0x5180E80ull +#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST0_BASE 0x5181000ull +#define HBM3_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST0_SECTION 0xE800 +#define mmHBM3_MC0BIST0_SPECIAL_BASE 0x5181E80ull +#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST1_BASE 0x5182000ull +#define HBM3_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST1_SECTION 0xE800 +#define mmHBM3_MC0BIST1_SPECIAL_BASE 0x5182E80ull +#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST2_BASE 0x5183000ull +#define HBM3_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST2_SECTION 0xE800 +#define mmHBM3_MC0BIST2_SPECIAL_BASE 0x5183E80ull +#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST3_BASE 0x5184000ull +#define HBM3_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST3_SECTION 0xE800 +#define mmHBM3_MC0BIST3_SPECIAL_BASE 0x5184E80ull +#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST4_BASE 0x5185000ull +#define HBM3_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST4_SECTION 0xE800 +#define mmHBM3_MC0BIST4_SPECIAL_BASE 0x5185E80ull +#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST5_BASE 0x5186000ull +#define HBM3_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST5_SECTION 0xE800 +#define mmHBM3_MC0BIST5_SPECIAL_BASE 0x5186E80ull +#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST6_BASE 0x5187000ull +#define HBM3_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST6_SECTION 0xE800 +#define mmHBM3_MC0BIST6_SPECIAL_BASE 0x5187E80ull +#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST7_BASE 0x5188000ull +#define HBM3_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST7_SECTION 0xE800 +#define mmHBM3_MC0BIST7_SPECIAL_BASE 0x5188E80ull +#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST8_MEM_BASE 0x5189000ull +#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM3_MC0BIST8_MEM_SPECIAL_BASE 0x5189E80ull +#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM3_MC1_BASE 0x51A0000ull +#define HBM3_MC1_MAX_OFFSET 0x1000 +#define HBM3_MC1_SECTION 0xE800 +#define mmHBM3_MC1_SPECIAL_BASE 0x51A0E80ull +#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST0_BASE 0x51A1000ull +#define HBM3_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST0_SECTION 0xE800 +#define mmHBM3_MC1BIST0_SPECIAL_BASE 0x51A1E80ull +#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST1_BASE 0x51A2000ull +#define HBM3_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST1_SECTION 0xE800 +#define mmHBM3_MC1BIST1_SPECIAL_BASE 0x51A2E80ull +#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST2_BASE 0x51A3000ull +#define HBM3_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST2_SECTION 0xE800 +#define mmHBM3_MC1BIST2_SPECIAL_BASE 0x51A3E80ull +#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST3_BASE 0x51A4000ull +#define HBM3_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST3_SECTION 0xE800 +#define mmHBM3_MC1BIST3_SPECIAL_BASE 0x51A4E80ull +#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST4_BASE 0x51A5000ull +#define HBM3_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST4_SECTION 0xE800 +#define mmHBM3_MC1BIST4_SPECIAL_BASE 0x51A5E80ull +#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST5_BASE 0x51A6000ull +#define HBM3_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST5_SECTION 0xE800 +#define mmHBM3_MC1BIST5_SPECIAL_BASE 0x51A6E80ull +#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST6_BASE 0x51A7000ull +#define HBM3_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST6_SECTION 0xE800 +#define mmHBM3_MC1BIST6_SPECIAL_BASE 0x51A7E80ull +#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST7_BASE 0x51A8000ull +#define HBM3_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST7_SECTION 0xE800 +#define mmHBM3_MC1BIST7_SPECIAL_BASE 0x51A8E80ull +#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST8_MEM_BASE 0x51A9000ull +#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM3_MC1BIST8_MEM_SPECIAL_BASE 0x51A9E80ull +#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM3_PHY_BASE 0x51C0000ull +#define HBM3_PHY_MAX_OFFSET 0x4000 +#define HBM3_PHY_SECTION 0x40000 +#define mmHBM4_MC0_BASE 0x5200000ull +#define HBM4_MC0_MAX_OFFSET 0x1000 +#define HBM4_MC0_SECTION 0xE800 +#define mmHBM4_MC0_SPECIAL_BASE 0x5200E80ull +#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST0_BASE 0x5201000ull +#define HBM4_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST0_SECTION 0xE800 +#define mmHBM4_MC0BIST0_SPECIAL_BASE 0x5201E80ull +#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST1_BASE 0x5202000ull +#define HBM4_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST1_SECTION 0xE800 +#define mmHBM4_MC0BIST1_SPECIAL_BASE 0x5202E80ull +#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST2_BASE 0x5203000ull +#define HBM4_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST2_SECTION 0xE800 +#define mmHBM4_MC0BIST2_SPECIAL_BASE 0x5203E80ull +#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST3_BASE 0x5204000ull +#define HBM4_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST3_SECTION 0xE800 +#define mmHBM4_MC0BIST3_SPECIAL_BASE 0x5204E80ull +#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST4_BASE 0x5205000ull +#define HBM4_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST4_SECTION 0xE800 +#define mmHBM4_MC0BIST4_SPECIAL_BASE 0x5205E80ull +#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST5_BASE 0x5206000ull +#define HBM4_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST5_SECTION 0xE800 +#define mmHBM4_MC0BIST5_SPECIAL_BASE 0x5206E80ull +#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST6_BASE 0x5207000ull +#define HBM4_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST6_SECTION 0xE800 +#define mmHBM4_MC0BIST6_SPECIAL_BASE 0x5207E80ull +#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST7_BASE 0x5208000ull +#define HBM4_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST7_SECTION 0xE800 +#define mmHBM4_MC0BIST7_SPECIAL_BASE 0x5208E80ull +#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST8_MEM_BASE 0x5209000ull +#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM4_MC0BIST8_MEM_SPECIAL_BASE 0x5209E80ull +#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM4_MC1_BASE 0x5220000ull +#define HBM4_MC1_MAX_OFFSET 0x1000 +#define HBM4_MC1_SECTION 0xE800 +#define mmHBM4_MC1_SPECIAL_BASE 0x5220E80ull +#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST0_BASE 0x5221000ull +#define HBM4_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST0_SECTION 0xE800 +#define mmHBM4_MC1BIST0_SPECIAL_BASE 0x5221E80ull +#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST1_BASE 0x5222000ull +#define HBM4_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST1_SECTION 0xE800 +#define mmHBM4_MC1BIST1_SPECIAL_BASE 0x5222E80ull +#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST2_BASE 0x5223000ull +#define HBM4_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST2_SECTION 0xE800 +#define mmHBM4_MC1BIST2_SPECIAL_BASE 0x5223E80ull +#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST3_BASE 0x5224000ull +#define HBM4_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST3_SECTION 0xE800 +#define mmHBM4_MC1BIST3_SPECIAL_BASE 0x5224E80ull +#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST4_BASE 0x5225000ull +#define HBM4_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST4_SECTION 0xE800 +#define mmHBM4_MC1BIST4_SPECIAL_BASE 0x5225E80ull +#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST5_BASE 0x5226000ull +#define HBM4_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST5_SECTION 0xE800 +#define mmHBM4_MC1BIST5_SPECIAL_BASE 0x5226E80ull +#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST6_BASE 0x5227000ull +#define HBM4_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST6_SECTION 0xE800 +#define mmHBM4_MC1BIST6_SPECIAL_BASE 0x5227E80ull +#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST7_BASE 0x5228000ull +#define HBM4_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST7_SECTION 0xE800 +#define mmHBM4_MC1BIST7_SPECIAL_BASE 0x5228E80ull +#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST8_MEM_BASE 0x5229000ull +#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM4_MC1BIST8_MEM_SPECIAL_BASE 0x5229E80ull +#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM4_PHY_BASE 0x5240000ull +#define HBM4_PHY_MAX_OFFSET 0x4000 +#define HBM4_PHY_SECTION 0x40000 +#define mmHBM5_MC0_BASE 0x5280000ull +#define HBM5_MC0_MAX_OFFSET 0x1000 +#define HBM5_MC0_SECTION 0xE800 +#define mmHBM5_MC0_SPECIAL_BASE 0x5280E80ull +#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST0_BASE 0x5281000ull +#define HBM5_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST0_SECTION 0xE800 +#define mmHBM5_MC0BIST0_SPECIAL_BASE 0x5281E80ull +#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST1_BASE 0x5282000ull +#define HBM5_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST1_SECTION 0xE800 +#define mmHBM5_MC0BIST1_SPECIAL_BASE 0x5282E80ull +#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST2_BASE 0x5283000ull +#define HBM5_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST2_SECTION 0xE800 +#define mmHBM5_MC0BIST2_SPECIAL_BASE 0x5283E80ull +#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST3_BASE 0x5284000ull +#define HBM5_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST3_SECTION 0xE800 +#define mmHBM5_MC0BIST3_SPECIAL_BASE 0x5284E80ull +#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST4_BASE 0x5285000ull +#define HBM5_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST4_SECTION 0xE800 +#define mmHBM5_MC0BIST4_SPECIAL_BASE 0x5285E80ull +#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST5_BASE 0x5286000ull +#define HBM5_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST5_SECTION 0xE800 +#define mmHBM5_MC0BIST5_SPECIAL_BASE 0x5286E80ull +#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST6_BASE 0x5287000ull +#define HBM5_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST6_SECTION 0xE800 +#define mmHBM5_MC0BIST6_SPECIAL_BASE 0x5287E80ull +#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST7_BASE 0x5288000ull +#define HBM5_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST7_SECTION 0xE800 +#define mmHBM5_MC0BIST7_SPECIAL_BASE 0x5288E80ull +#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST8_MEM_BASE 0x5289000ull +#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM5_MC0BIST8_MEM_SPECIAL_BASE 0x5289E80ull +#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM5_MC1_BASE 0x52A0000ull +#define HBM5_MC1_MAX_OFFSET 0x1000 +#define HBM5_MC1_SECTION 0xE800 +#define mmHBM5_MC1_SPECIAL_BASE 0x52A0E80ull +#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST0_BASE 0x52A1000ull +#define HBM5_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST0_SECTION 0xE800 +#define mmHBM5_MC1BIST0_SPECIAL_BASE 0x52A1E80ull +#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST1_BASE 0x52A2000ull +#define HBM5_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST1_SECTION 0xE800 +#define mmHBM5_MC1BIST1_SPECIAL_BASE 0x52A2E80ull +#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST2_BASE 0x52A3000ull +#define HBM5_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST2_SECTION 0xE800 +#define mmHBM5_MC1BIST2_SPECIAL_BASE 0x52A3E80ull +#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST3_BASE 0x52A4000ull +#define HBM5_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST3_SECTION 0xE800 +#define mmHBM5_MC1BIST3_SPECIAL_BASE 0x52A4E80ull +#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST4_BASE 0x52A5000ull +#define HBM5_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST4_SECTION 0xE800 +#define mmHBM5_MC1BIST4_SPECIAL_BASE 0x52A5E80ull +#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST5_BASE 0x52A6000ull +#define HBM5_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST5_SECTION 0xE800 +#define mmHBM5_MC1BIST5_SPECIAL_BASE 0x52A6E80ull +#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST6_BASE 0x52A7000ull +#define HBM5_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST6_SECTION 0xE800 +#define mmHBM5_MC1BIST6_SPECIAL_BASE 0x52A7E80ull +#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST7_BASE 0x52A8000ull +#define HBM5_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST7_SECTION 0xE800 +#define mmHBM5_MC1BIST7_SPECIAL_BASE 0x52A8E80ull +#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST8_MEM_BASE 0x52A9000ull +#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM5_MC1BIST8_MEM_SPECIAL_BASE 0x52A9E80ull +#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM5_PHY_BASE 0x52C0000ull +#define HBM5_PHY_MAX_OFFSET 0x4000 +#define HBM5_PHY_SECTION 0x140000 +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5400000ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5400080ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5400100ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5400180ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_0_SPECIAL_BASE 0x5400E80ull +#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5401000ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5401080ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5401100ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5401180ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_1_SPECIAL_BASE 0x5401E80ull +#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5402000ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5402080ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5402100ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5402180ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_2_SPECIAL_BASE 0x5402E80ull +#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5403000ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5403080ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5403100ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5403180ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_3_SPECIAL_BASE 0x5403E80ull +#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5404000ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5404080ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5404100ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5404180ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_4_SPECIAL_BASE 0x5404E80ull +#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5405000ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5405080ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5405100ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5405180ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_5_SPECIAL_BASE 0x5405E80ull +#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5406000ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5406080ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5406100ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5406180ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_6_SPECIAL_BASE 0x5406E80ull +#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5407000ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5407080ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5407100ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5407180ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_7_SPECIAL_BASE 0x5407E80ull +#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5408000ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5408080ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5408100ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5408180ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_8_SPECIAL_BASE 0x5408E80ull +#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5409000ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5409080ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5409100ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5409180ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_9_SPECIAL_BASE 0x5409E80ull +#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x540A000ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x540A080ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x540A100ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x540A180ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_10_SPECIAL_BASE 0x540AE80ull +#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x540B000ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x540B080ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x540B100ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x540B180ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_11_SPECIAL_BASE 0x540BE80ull +#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x540C000ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x540C080ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x540C100ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x540C180ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_12_SPECIAL_BASE 0x540CE80ull +#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x540D000ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x540D080ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x540D100ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x540D180ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_13_SPECIAL_BASE 0x540DE80ull +#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x540E000ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x540E080ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x540E100ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x540E180ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_14_SPECIAL_BASE 0x540EE80ull +#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM_DCCM0_BASE 0x5410000ull +#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM0_SECTION 0x8000 +#define mmNIC0_QM_ARC_AUX0_BASE 0x5418000ull +#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC0_QM_ARC_AUX0_SPECIAL_BASE 0x5418E80ull +#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM0_BASE 0x541A000ull +#define NIC0_QM0_MAX_OFFSET 0x1000 +#define NIC0_QM0_SECTION 0x9000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x541A900ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x541A908ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x541A910ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x541A918ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x541A920ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x541A928ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x541A930ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x541A938ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x541A940ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x541A948ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x541A950ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x541A958ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x541A960ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x541A968ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x541A970ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x541A978ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC0_QM0_AXUSER_SECURED_BASE 0x541AB00ull +#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC0_QM0_AXUSER_NONSECURED_BASE 0x541AB80ull +#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC0_QM0_DBG_HBW_BASE 0x541AC00ull +#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC0_QM0_DBG_LBW_BASE 0x541AC80ull +#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC0_QM0_CGM_BASE 0x541AD80ull +#define NIC0_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM0_CGM_SECTION 0x1000 +#define mmNIC0_QM0_SPECIAL_BASE 0x541AE80ull +#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC0_QPC0_BASE 0x541F000ull +#define NIC0_QPC0_MAX_OFFSET 0x1000 +#define NIC0_QPC0_SECTION 0x7200 +#define mmNIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x541F720ull +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x541F728ull +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x541F730ull +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x541F738ull +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x541F740ull +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x541F748ull +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x541F750ull +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x541F758ull +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x541F760ull +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x541F768ull +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x541F770ull +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x541F778ull +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x541F780ull +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x541F788ull +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x541F790ull +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x541F798ull +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x541F7A0ull +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x541F7A8ull +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x541F7B0ull +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x541F7B8ull +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x541F7C0ull +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x541F7C8ull +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x541F7D0ull +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x541F7D8ull +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x541F7E0ull +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x541F7E8ull +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x541F7F0ull +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x541F7F8ull +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x541F800ull +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x541F808ull +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x541F810ull +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x541F818ull +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC0_QPC0_AXUSER_CONG_QUE_BASE 0x541FB80ull +#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_RXWQE_BASE 0x541FBE0ull +#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x541FC40ull +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_DB_FIFO_BASE 0x541FCA0ull +#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x541FD00ull +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x541FD60ull +#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_QPC_RESP_BASE 0x541FDC0ull +#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_QPC_REQ_BASE 0x541FE20ull +#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC0_QPC0_SPECIAL_BASE 0x541FE80ull +#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5420000ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5420080ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5420100ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5420180ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_0_SPECIAL_BASE 0x5420E80ull +#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5421000ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5421080ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5421100ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5421180ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_1_SPECIAL_BASE 0x5421E80ull +#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5422000ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5422080ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5422100ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5422180ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_2_SPECIAL_BASE 0x5422E80ull +#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5423000ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5423080ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5423100ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5423180ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_3_SPECIAL_BASE 0x5423E80ull +#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5424000ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5424080ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5424100ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5424180ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_4_SPECIAL_BASE 0x5424E80ull +#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5425000ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5425080ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5425100ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5425180ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_5_SPECIAL_BASE 0x5425E80ull +#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5426000ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5426080ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5426100ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5426180ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_6_SPECIAL_BASE 0x5426E80ull +#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5427000ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5427080ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5427100ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5427180ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_7_SPECIAL_BASE 0x5427E80ull +#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5428000ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5428080ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5428100ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5428180ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_8_SPECIAL_BASE 0x5428E80ull +#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5429000ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5429080ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5429100ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5429180ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_9_SPECIAL_BASE 0x5429E80ull +#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x542A000ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x542A080ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x542A100ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x542A180ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_10_SPECIAL_BASE 0x542AE80ull +#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x542B000ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x542B080ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x542B100ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x542B180ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_11_SPECIAL_BASE 0x542BE80ull +#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x542C000ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x542C080ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x542C100ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x542C180ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_12_SPECIAL_BASE 0x542CE80ull +#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x542D000ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x542D080ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x542D100ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x542D180ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_13_SPECIAL_BASE 0x542DE80ull +#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x542E000ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x542E080ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x542E100ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x542E180ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_14_SPECIAL_BASE 0x542EE80ull +#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM_DCCM1_BASE 0x5430000ull +#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM1_SECTION 0x8000 +#define mmNIC0_QM_ARC_AUX1_BASE 0x5438000ull +#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC0_QM_ARC_AUX1_SPECIAL_BASE 0x5438E80ull +#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM1_BASE 0x543A000ull +#define NIC0_QM1_MAX_OFFSET 0x1000 +#define NIC0_QM1_SECTION 0x9000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x543A900ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x543A908ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x543A910ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x543A918ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x543A920ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x543A928ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x543A930ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x543A938ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x543A940ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x543A948ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x543A950ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x543A958ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x543A960ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x543A968ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x543A970ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x543A978ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC0_QM1_AXUSER_SECURED_BASE 0x543AB00ull +#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC0_QM1_AXUSER_NONSECURED_BASE 0x543AB80ull +#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC0_QM1_DBG_HBW_BASE 0x543AC00ull +#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC0_QM1_DBG_LBW_BASE 0x543AC80ull +#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC0_QM1_CGM_BASE 0x543AD80ull +#define NIC0_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM1_CGM_SECTION 0x1000 +#define mmNIC0_QM1_SPECIAL_BASE 0x543AE80ull +#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC0_QPC1_BASE 0x543F000ull +#define NIC0_QPC1_MAX_OFFSET 0x1000 +#define NIC0_QPC1_SECTION 0x7200 +#define mmNIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x543F720ull +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x543F728ull +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x543F730ull +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x543F738ull +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x543F740ull +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x543F748ull +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x543F750ull +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x543F758ull +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x543F760ull +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x543F768ull +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x543F770ull +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x543F778ull +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x543F780ull +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x543F788ull +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x543F790ull +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x543F798ull +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x543F7A0ull +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x543F7A8ull +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x543F7B0ull +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x543F7B8ull +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x543F7C0ull +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x543F7C8ull +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x543F7D0ull +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x543F7D8ull +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x543F7E0ull +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x543F7E8ull +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x543F7F0ull +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x543F7F8ull +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x543F800ull +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x543F808ull +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x543F810ull +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x543F818ull +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC0_QPC1_AXUSER_CONG_QUE_BASE 0x543FB80ull +#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_RXWQE_BASE 0x543FBE0ull +#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x543FC40ull +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_DB_FIFO_BASE 0x543FCA0ull +#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x543FD00ull +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x543FD60ull +#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_QPC_RESP_BASE 0x543FDC0ull +#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_QPC_REQ_BASE 0x543FE20ull +#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC0_QPC1_SPECIAL_BASE 0x543FE80ull +#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC0_TMR_BASE 0x5448000ull +#define NIC0_TMR_MAX_OFFSET 0x1000 +#define NIC0_TMR_SECTION 0xD600 +#define mmNIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5448D60ull +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC0_TMR_AXUSER_TMR_FIFO_BASE 0x5448DC0ull +#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC0_TMR_AXUSER_TMR_FSM_BASE 0x5448E20ull +#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC0_TMR_SPECIAL_BASE 0x5448E80ull +#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXB_CORE_BASE 0x5449000ull +#define NIC0_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC0_RXB_CORE_SECTION 0x6100 +#define mmNIC0_RXB_CORE_SCT_AWUSER_BASE 0x5449610ull +#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC0_RXB_CORE_SPECIAL_BASE 0x5449E80ull +#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE0_BASE 0x544A000ull +#define NIC0_RXE0_MAX_OFFSET 0x1000 +#define NIC0_RXE0_SECTION 0x9000 +#define mmNIC0_RXE0_WQE_ARUSER_BASE 0x544A900ull +#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC0_RXE0_SPECIAL_BASE 0x544AE80ull +#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE1_BASE 0x544B000ull +#define NIC0_RXE1_MAX_OFFSET 0x1000 +#define NIC0_RXE1_SECTION 0x9000 +#define mmNIC0_RXE1_WQE_ARUSER_BASE 0x544B900ull +#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC0_RXE1_SPECIAL_BASE 0x544BE80ull +#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x544C000ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x544C050ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x544C0A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x544C0F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x544C140ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x544C190ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x544C1E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x544C230ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x544C280ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x544C2D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x544C320ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x544C370ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x544C3C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x544C410ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x544C460ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x544C4B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x544C500ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x544C550ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x544C5A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x544C5F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x544C640ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x544C690ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x544C6E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x544C730ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x544C780ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x544C7D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x544C820ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x544C870ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x544C8C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x544C910ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x544C960ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x544C9B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC0_RXE0_AXUSER_SPECIAL_BASE 0x544CE80ull +#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x544D000ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x544D050ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x544D0A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x544D0F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x544D140ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x544D190ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x544D1E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x544D230ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x544D280ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x544D2D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x544D320ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x544D370ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x544D3C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x544D410ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x544D460ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x544D4B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x544D500ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x544D550ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x544D5A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x544D5F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x544D640ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x544D690ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x544D6E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x544D730ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x544D780ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x544D7D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x544D820ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x544D870ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x544D8C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x544D910ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x544D960ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x544D9B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC0_RXE1_AXUSER_SPECIAL_BASE 0x544DE80ull +#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC0_TXS0_BASE 0x5450000ull +#define NIC0_TXS0_MAX_OFFSET 0x1000 +#define NIC0_TXS0_SECTION 0xE800 +#define mmNIC0_TXS0_SPECIAL_BASE 0x5450E80ull +#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXS1_BASE 0x5451000ull +#define NIC0_TXS1_MAX_OFFSET 0x1000 +#define NIC0_TXS1_SECTION 0xE800 +#define mmNIC0_TXS1_SPECIAL_BASE 0x5451E80ull +#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXE0_BASE 0x5452000ull +#define NIC0_TXE0_MAX_OFFSET 0x1000 +#define NIC0_TXE0_SECTION 0xE800 +#define mmNIC0_TXE0_SPECIAL_BASE 0x5452E80ull +#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXE1_BASE 0x5453000ull +#define NIC0_TXE1_MAX_OFFSET 0x1000 +#define NIC0_TXE1_SECTION 0xE800 +#define mmNIC0_TXE1_SPECIAL_BASE 0x5453E80ull +#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXB_BASE 0x5454000ull +#define NIC0_TXB_MAX_OFFSET 0x1000 +#define NIC0_TXB_SECTION 0xE800 +#define mmNIC0_TXB_SPECIAL_BASE 0x5454E80ull +#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x5455000ull +#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x5455200ull +#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x5455400ull +#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x5455600ull +#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_E2E_CRDT_BASE 0x5455800ull +#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC0_MSTR_IF_AXUSER_BASE 0x5455A80ull +#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC0_MSTR_IF_DBG_HBW_BASE 0x5455B00ull +#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC0_MSTR_IF_DBG_LBW_BASE 0x5455B80ull +#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC0_MSTR_IF_CORE_HBW_BASE 0x5455C00ull +#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC0_MSTR_IF_CORE_LBW_BASE 0x5455D80ull +#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC0_MSTR_IF_SPECIAL_BASE 0x5455E80ull +#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC0_TX_AXUSER_BASE 0x5456000ull +#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_TX_AXUSER_SECTION 0x2000 +#define mmNIC0_SERDES0_BASE 0x5458000ull +#define NIC0_SERDES0_MAX_OFFSET 0x3E40 +#define NIC0_SERDES0_SECTION 0x4000 +#define mmNIC0_SERDES1_BASE 0x545C000ull +#define NIC0_SERDES1_MAX_OFFSET 0x3E40 +#define NIC0_SERDES1_SECTION 0x4000 +#define mmNIC0_PHY_BASE 0x5460000ull +#define NIC0_PHY_MAX_OFFSET 0x1000 +#define NIC0_PHY_SECTION 0xE800 +#define mmNIC0_PHY_SPECIAL_BASE 0x5460E80ull +#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT0_MAC_AUX_BASE 0x5468000ull +#define PRT0_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT0_MAC_AUX_SECTION 0xE800 +#define mmPRT0_MAC_AUX_SPECIAL_BASE 0x5468E80ull +#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT0_MAC_CORE_BASE 0x5469000ull +#define PRT0_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT0_MAC_CORE_SECTION 0xE800 +#define mmPRT0_MAC_CORE_SPECIAL_BASE 0x5469E80ull +#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC0_MAC_RS_FEC_BASE 0x546A000ull +#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC0_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC0_MAC_GLOB_STAT_CONTROL_REG_BASE 0x546B000ull +#define NIC0_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC0_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC0_MAC_GLOB_STAT_RX0_BASE 0x546B100ull +#define NIC0_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX1_BASE 0x546B18Cull +#define NIC0_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX2_BASE 0x546B218ull +#define NIC0_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX3_BASE 0x546B2A4ull +#define NIC0_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_TX0_BASE 0x546B330ull +#define NIC0_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX1_BASE 0x546B398ull +#define NIC0_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX2_BASE 0x546B400ull +#define NIC0_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX3_BASE 0x546B468ull +#define NIC0_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC0_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x546B800ull +#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC0_MAC_CH0_MAC_PCS_BASE 0x546C000ull +#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH0_MAC_128_BASE 0x546C400ull +#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH0_MAC_AN_BASE 0x546C800ull +#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH1_MAC_PCS_BASE 0x546D000ull +#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH1_MAC_128_BASE 0x546D400ull +#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH1_MAC_AN_BASE 0x546D800ull +#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH2_MAC_PCS_BASE 0x546E000ull +#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH2_MAC_128_BASE 0x546E400ull +#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH2_MAC_AN_BASE 0x546E800ull +#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH3_MAC_PCS_BASE 0x546F000ull +#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH3_MAC_128_BASE 0x546F400ull +#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH3_MAC_AN_BASE 0x546F800ull +#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5480000ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5480080ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5480100ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5480180ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_0_SPECIAL_BASE 0x5480E80ull +#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5481000ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5481080ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5481100ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5481180ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_1_SPECIAL_BASE 0x5481E80ull +#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5482000ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5482080ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5482100ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5482180ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_2_SPECIAL_BASE 0x5482E80ull +#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5483000ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5483080ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5483100ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5483180ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_3_SPECIAL_BASE 0x5483E80ull +#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5484000ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5484080ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5484100ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5484180ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_4_SPECIAL_BASE 0x5484E80ull +#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5485000ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5485080ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5485100ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5485180ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_5_SPECIAL_BASE 0x5485E80ull +#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5486000ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5486080ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5486100ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5486180ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_6_SPECIAL_BASE 0x5486E80ull +#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5487000ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5487080ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5487100ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5487180ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_7_SPECIAL_BASE 0x5487E80ull +#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5488000ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5488080ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5488100ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5488180ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_8_SPECIAL_BASE 0x5488E80ull +#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5489000ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5489080ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5489100ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5489180ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_9_SPECIAL_BASE 0x5489E80ull +#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x548A000ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x548A080ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x548A100ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x548A180ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_10_SPECIAL_BASE 0x548AE80ull +#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x548B000ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x548B080ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x548B100ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x548B180ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_11_SPECIAL_BASE 0x548BE80ull +#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x548C000ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x548C080ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x548C100ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x548C180ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_12_SPECIAL_BASE 0x548CE80ull +#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x548D000ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x548D080ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x548D100ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x548D180ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_13_SPECIAL_BASE 0x548DE80ull +#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x548E000ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x548E080ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x548E100ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x548E180ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_14_SPECIAL_BASE 0x548EE80ull +#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM_DCCM0_BASE 0x5490000ull +#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM0_SECTION 0x8000 +#define mmNIC1_QM_ARC_AUX0_BASE 0x5498000ull +#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC1_QM_ARC_AUX0_SPECIAL_BASE 0x5498E80ull +#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM0_BASE 0x549A000ull +#define NIC1_QM0_MAX_OFFSET 0x1000 +#define NIC1_QM0_SECTION 0x9000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x549A900ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x549A908ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x549A910ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x549A918ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x549A920ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x549A928ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x549A930ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x549A938ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x549A940ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x549A948ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x549A950ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x549A958ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x549A960ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x549A968ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x549A970ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x549A978ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC1_QM0_AXUSER_SECURED_BASE 0x549AB00ull +#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC1_QM0_AXUSER_NONSECURED_BASE 0x549AB80ull +#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC1_QM0_DBG_HBW_BASE 0x549AC00ull +#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC1_QM0_DBG_LBW_BASE 0x549AC80ull +#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC1_QM0_CGM_BASE 0x549AD80ull +#define NIC1_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM0_CGM_SECTION 0x1000 +#define mmNIC1_QM0_SPECIAL_BASE 0x549AE80ull +#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC1_QPC0_BASE 0x549F000ull +#define NIC1_QPC0_MAX_OFFSET 0x1000 +#define NIC1_QPC0_SECTION 0x7200 +#define mmNIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x549F720ull +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x549F728ull +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x549F730ull +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x549F738ull +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x549F740ull +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x549F748ull +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x549F750ull +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x549F758ull +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x549F760ull +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x549F768ull +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x549F770ull +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x549F778ull +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x549F780ull +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x549F788ull +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x549F790ull +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x549F798ull +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x549F7A0ull +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x549F7A8ull +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x549F7B0ull +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x549F7B8ull +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x549F7C0ull +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x549F7C8ull +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x549F7D0ull +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x549F7D8ull +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x549F7E0ull +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x549F7E8ull +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x549F7F0ull +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x549F7F8ull +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x549F800ull +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x549F808ull +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x549F810ull +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x549F818ull +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC1_QPC0_AXUSER_CONG_QUE_BASE 0x549FB80ull +#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_RXWQE_BASE 0x549FBE0ull +#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x549FC40ull +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_DB_FIFO_BASE 0x549FCA0ull +#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x549FD00ull +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x549FD60ull +#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_QPC_RESP_BASE 0x549FDC0ull +#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_QPC_REQ_BASE 0x549FE20ull +#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC1_QPC0_SPECIAL_BASE 0x549FE80ull +#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x54A0000ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x54A0080ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x54A0100ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x54A0180ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_0_SPECIAL_BASE 0x54A0E80ull +#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x54A1000ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x54A1080ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x54A1100ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x54A1180ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_1_SPECIAL_BASE 0x54A1E80ull +#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x54A2000ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x54A2080ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x54A2100ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x54A2180ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_2_SPECIAL_BASE 0x54A2E80ull +#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x54A3000ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x54A3080ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x54A3100ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x54A3180ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_3_SPECIAL_BASE 0x54A3E80ull +#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x54A4000ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x54A4080ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x54A4100ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x54A4180ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_4_SPECIAL_BASE 0x54A4E80ull +#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x54A5000ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x54A5080ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x54A5100ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x54A5180ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_5_SPECIAL_BASE 0x54A5E80ull +#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x54A6000ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x54A6080ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x54A6100ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x54A6180ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_6_SPECIAL_BASE 0x54A6E80ull +#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x54A7000ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x54A7080ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x54A7100ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x54A7180ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_7_SPECIAL_BASE 0x54A7E80ull +#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x54A8000ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x54A8080ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x54A8100ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x54A8180ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_8_SPECIAL_BASE 0x54A8E80ull +#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x54A9000ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x54A9080ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x54A9100ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x54A9180ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_9_SPECIAL_BASE 0x54A9E80ull +#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x54AA000ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x54AA080ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x54AA100ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x54AA180ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_10_SPECIAL_BASE 0x54AAE80ull +#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x54AB000ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x54AB080ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x54AB100ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x54AB180ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_11_SPECIAL_BASE 0x54ABE80ull +#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x54AC000ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x54AC080ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x54AC100ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x54AC180ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_12_SPECIAL_BASE 0x54ACE80ull +#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x54AD000ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x54AD080ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x54AD100ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x54AD180ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_13_SPECIAL_BASE 0x54ADE80ull +#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x54AE000ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x54AE080ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x54AE100ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x54AE180ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_14_SPECIAL_BASE 0x54AEE80ull +#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM_DCCM1_BASE 0x54B0000ull +#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM1_SECTION 0x8000 +#define mmNIC1_QM_ARC_AUX1_BASE 0x54B8000ull +#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC1_QM_ARC_AUX1_SPECIAL_BASE 0x54B8E80ull +#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM1_BASE 0x54BA000ull +#define NIC1_QM1_MAX_OFFSET 0x1000 +#define NIC1_QM1_SECTION 0x9000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x54BA900ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x54BA908ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x54BA910ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x54BA918ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x54BA920ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x54BA928ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x54BA930ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x54BA938ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x54BA940ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x54BA948ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x54BA950ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x54BA958ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x54BA960ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x54BA968ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x54BA970ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x54BA978ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC1_QM1_AXUSER_SECURED_BASE 0x54BAB00ull +#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC1_QM1_AXUSER_NONSECURED_BASE 0x54BAB80ull +#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC1_QM1_DBG_HBW_BASE 0x54BAC00ull +#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC1_QM1_DBG_LBW_BASE 0x54BAC80ull +#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC1_QM1_CGM_BASE 0x54BAD80ull +#define NIC1_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM1_CGM_SECTION 0x1000 +#define mmNIC1_QM1_SPECIAL_BASE 0x54BAE80ull +#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC1_QPC1_BASE 0x54BF000ull +#define NIC1_QPC1_MAX_OFFSET 0x1000 +#define NIC1_QPC1_SECTION 0x7200 +#define mmNIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x54BF720ull +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x54BF728ull +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x54BF730ull +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x54BF738ull +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x54BF740ull +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x54BF748ull +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x54BF750ull +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x54BF758ull +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x54BF760ull +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x54BF768ull +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x54BF770ull +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x54BF778ull +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x54BF780ull +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x54BF788ull +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x54BF790ull +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x54BF798ull +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x54BF7A0ull +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x54BF7A8ull +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x54BF7B0ull +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x54BF7B8ull +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x54BF7C0ull +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x54BF7C8ull +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x54BF7D0ull +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x54BF7D8ull +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x54BF7E0ull +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x54BF7E8ull +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x54BF7F0ull +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x54BF7F8ull +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x54BF800ull +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x54BF808ull +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x54BF810ull +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x54BF818ull +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC1_QPC1_AXUSER_CONG_QUE_BASE 0x54BFB80ull +#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_RXWQE_BASE 0x54BFBE0ull +#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x54BFC40ull +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_DB_FIFO_BASE 0x54BFCA0ull +#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x54BFD00ull +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x54BFD60ull +#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_QPC_RESP_BASE 0x54BFDC0ull +#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_QPC_REQ_BASE 0x54BFE20ull +#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC1_QPC1_SPECIAL_BASE 0x54BFE80ull +#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC1_TMR_BASE 0x54C8000ull +#define NIC1_TMR_MAX_OFFSET 0x1000 +#define NIC1_TMR_SECTION 0xD600 +#define mmNIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x54C8D60ull +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC1_TMR_AXUSER_TMR_FIFO_BASE 0x54C8DC0ull +#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC1_TMR_AXUSER_TMR_FSM_BASE 0x54C8E20ull +#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC1_TMR_SPECIAL_BASE 0x54C8E80ull +#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXB_CORE_BASE 0x54C9000ull +#define NIC1_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC1_RXB_CORE_SECTION 0x6100 +#define mmNIC1_RXB_CORE_SCT_AWUSER_BASE 0x54C9610ull +#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC1_RXB_CORE_SPECIAL_BASE 0x54C9E80ull +#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE0_BASE 0x54CA000ull +#define NIC1_RXE0_MAX_OFFSET 0x1000 +#define NIC1_RXE0_SECTION 0x9000 +#define mmNIC1_RXE0_WQE_ARUSER_BASE 0x54CA900ull +#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC1_RXE0_SPECIAL_BASE 0x54CAE80ull +#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE1_BASE 0x54CB000ull +#define NIC1_RXE1_MAX_OFFSET 0x1000 +#define NIC1_RXE1_SECTION 0x9000 +#define mmNIC1_RXE1_WQE_ARUSER_BASE 0x54CB900ull +#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC1_RXE1_SPECIAL_BASE 0x54CBE80ull +#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x54CC000ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x54CC050ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x54CC0A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x54CC0F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x54CC140ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x54CC190ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x54CC1E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x54CC230ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x54CC280ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x54CC2D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x54CC320ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x54CC370ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x54CC3C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x54CC410ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x54CC460ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x54CC4B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x54CC500ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x54CC550ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x54CC5A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x54CC5F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x54CC640ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x54CC690ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x54CC6E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x54CC730ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x54CC780ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x54CC7D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x54CC820ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x54CC870ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x54CC8C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x54CC910ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x54CC960ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x54CC9B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC1_RXE0_AXUSER_SPECIAL_BASE 0x54CCE80ull +#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x54CD000ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x54CD050ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x54CD0A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x54CD0F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x54CD140ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x54CD190ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x54CD1E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x54CD230ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x54CD280ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x54CD2D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x54CD320ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x54CD370ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x54CD3C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x54CD410ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x54CD460ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x54CD4B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x54CD500ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x54CD550ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x54CD5A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x54CD5F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x54CD640ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x54CD690ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x54CD6E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x54CD730ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x54CD780ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x54CD7D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x54CD820ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x54CD870ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x54CD8C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x54CD910ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x54CD960ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x54CD9B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC1_RXE1_AXUSER_SPECIAL_BASE 0x54CDE80ull +#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC1_TXS0_BASE 0x54D0000ull +#define NIC1_TXS0_MAX_OFFSET 0x1000 +#define NIC1_TXS0_SECTION 0xE800 +#define mmNIC1_TXS0_SPECIAL_BASE 0x54D0E80ull +#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXS1_BASE 0x54D1000ull +#define NIC1_TXS1_MAX_OFFSET 0x1000 +#define NIC1_TXS1_SECTION 0xE800 +#define mmNIC1_TXS1_SPECIAL_BASE 0x54D1E80ull +#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXE0_BASE 0x54D2000ull +#define NIC1_TXE0_MAX_OFFSET 0x1000 +#define NIC1_TXE0_SECTION 0xE800 +#define mmNIC1_TXE0_SPECIAL_BASE 0x54D2E80ull +#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXE1_BASE 0x54D3000ull +#define NIC1_TXE1_MAX_OFFSET 0x1000 +#define NIC1_TXE1_SECTION 0xE800 +#define mmNIC1_TXE1_SPECIAL_BASE 0x54D3E80ull +#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXB_BASE 0x54D4000ull +#define NIC1_TXB_MAX_OFFSET 0x1000 +#define NIC1_TXB_SECTION 0xE800 +#define mmNIC1_TXB_SPECIAL_BASE 0x54D4E80ull +#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x54D5000ull +#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x54D5200ull +#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x54D5400ull +#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x54D5600ull +#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_E2E_CRDT_BASE 0x54D5800ull +#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC1_MSTR_IF_AXUSER_BASE 0x54D5A80ull +#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC1_MSTR_IF_DBG_HBW_BASE 0x54D5B00ull +#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC1_MSTR_IF_DBG_LBW_BASE 0x54D5B80ull +#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC1_MSTR_IF_CORE_HBW_BASE 0x54D5C00ull +#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC1_MSTR_IF_CORE_LBW_BASE 0x54D5D80ull +#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC1_MSTR_IF_SPECIAL_BASE 0x54D5E80ull +#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC1_TX_AXUSER_BASE 0x54D6000ull +#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_TX_AXUSER_SECTION 0x2000 +#define mmNIC1_SERDES0_BASE 0x54D8000ull +#define NIC1_SERDES0_MAX_OFFSET 0x3E40 +#define NIC1_SERDES0_SECTION 0x4000 +#define mmNIC1_SERDES1_BASE 0x54DC000ull +#define NIC1_SERDES1_MAX_OFFSET 0x3E40 +#define NIC1_SERDES1_SECTION 0x4000 +#define mmNIC1_PHY_BASE 0x54E0000ull +#define NIC1_PHY_MAX_OFFSET 0x1000 +#define NIC1_PHY_SECTION 0xE800 +#define mmNIC1_PHY_SPECIAL_BASE 0x54E0E80ull +#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT1_MAC_AUX_BASE 0x54E8000ull +#define PRT1_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT1_MAC_AUX_SECTION 0xE800 +#define mmPRT1_MAC_AUX_SPECIAL_BASE 0x54E8E80ull +#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT1_MAC_CORE_BASE 0x54E9000ull +#define PRT1_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT1_MAC_CORE_SECTION 0xE800 +#define mmPRT1_MAC_CORE_SPECIAL_BASE 0x54E9E80ull +#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC1_MAC_RS_FEC_BASE 0x54EA000ull +#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC1_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC1_MAC_GLOB_STAT_CONTROL_REG_BASE 0x54EB000ull +#define NIC1_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC1_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC1_MAC_GLOB_STAT_RX0_BASE 0x54EB100ull +#define NIC1_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX1_BASE 0x54EB18Cull +#define NIC1_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX2_BASE 0x54EB218ull +#define NIC1_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX3_BASE 0x54EB2A4ull +#define NIC1_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_TX0_BASE 0x54EB330ull +#define NIC1_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX1_BASE 0x54EB398ull +#define NIC1_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX2_BASE 0x54EB400ull +#define NIC1_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX3_BASE 0x54EB468ull +#define NIC1_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC1_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x54EB800ull +#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC1_MAC_CH0_MAC_PCS_BASE 0x54EC000ull +#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH0_MAC_128_BASE 0x54EC400ull +#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH0_MAC_AN_BASE 0x54EC800ull +#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH1_MAC_PCS_BASE 0x54ED000ull +#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH1_MAC_128_BASE 0x54ED400ull +#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH1_MAC_AN_BASE 0x54ED800ull +#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH2_MAC_PCS_BASE 0x54EE000ull +#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH2_MAC_128_BASE 0x54EE400ull +#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH2_MAC_AN_BASE 0x54EE800ull +#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH3_MAC_PCS_BASE 0x54EF000ull +#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH3_MAC_128_BASE 0x54EF400ull +#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH3_MAC_AN_BASE 0x54EF800ull +#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5500000ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5500080ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5500100ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5500180ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_0_SPECIAL_BASE 0x5500E80ull +#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5501000ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5501080ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5501100ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5501180ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_1_SPECIAL_BASE 0x5501E80ull +#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5502000ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5502080ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5502100ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5502180ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_2_SPECIAL_BASE 0x5502E80ull +#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5503000ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5503080ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5503100ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5503180ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_3_SPECIAL_BASE 0x5503E80ull +#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5504000ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5504080ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5504100ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5504180ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_4_SPECIAL_BASE 0x5504E80ull +#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5505000ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5505080ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5505100ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5505180ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_5_SPECIAL_BASE 0x5505E80ull +#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5506000ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5506080ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5506100ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5506180ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_6_SPECIAL_BASE 0x5506E80ull +#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5507000ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5507080ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5507100ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5507180ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_7_SPECIAL_BASE 0x5507E80ull +#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5508000ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5508080ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5508100ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5508180ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_8_SPECIAL_BASE 0x5508E80ull +#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5509000ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5509080ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5509100ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5509180ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_9_SPECIAL_BASE 0x5509E80ull +#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x550A000ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x550A080ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x550A100ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x550A180ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_10_SPECIAL_BASE 0x550AE80ull +#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x550B000ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x550B080ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x550B100ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x550B180ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_11_SPECIAL_BASE 0x550BE80ull +#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x550C000ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x550C080ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x550C100ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x550C180ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_12_SPECIAL_BASE 0x550CE80ull +#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x550D000ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x550D080ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x550D100ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x550D180ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_13_SPECIAL_BASE 0x550DE80ull +#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x550E000ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x550E080ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x550E100ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x550E180ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_14_SPECIAL_BASE 0x550EE80ull +#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM_DCCM0_BASE 0x5510000ull +#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM0_SECTION 0x8000 +#define mmNIC2_QM_ARC_AUX0_BASE 0x5518000ull +#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC2_QM_ARC_AUX0_SPECIAL_BASE 0x5518E80ull +#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM0_BASE 0x551A000ull +#define NIC2_QM0_MAX_OFFSET 0x1000 +#define NIC2_QM0_SECTION 0x9000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x551A900ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x551A908ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x551A910ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x551A918ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x551A920ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x551A928ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x551A930ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x551A938ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x551A940ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x551A948ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x551A950ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x551A958ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x551A960ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x551A968ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x551A970ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x551A978ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC2_QM0_AXUSER_SECURED_BASE 0x551AB00ull +#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC2_QM0_AXUSER_NONSECURED_BASE 0x551AB80ull +#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC2_QM0_DBG_HBW_BASE 0x551AC00ull +#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC2_QM0_DBG_LBW_BASE 0x551AC80ull +#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC2_QM0_CGM_BASE 0x551AD80ull +#define NIC2_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM0_CGM_SECTION 0x1000 +#define mmNIC2_QM0_SPECIAL_BASE 0x551AE80ull +#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC2_QPC0_BASE 0x551F000ull +#define NIC2_QPC0_MAX_OFFSET 0x1000 +#define NIC2_QPC0_SECTION 0x7200 +#define mmNIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x551F720ull +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x551F728ull +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x551F730ull +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x551F738ull +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x551F740ull +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x551F748ull +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x551F750ull +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x551F758ull +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x551F760ull +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x551F768ull +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x551F770ull +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x551F778ull +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x551F780ull +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x551F788ull +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x551F790ull +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x551F798ull +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x551F7A0ull +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x551F7A8ull +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x551F7B0ull +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x551F7B8ull +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x551F7C0ull +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x551F7C8ull +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x551F7D0ull +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x551F7D8ull +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x551F7E0ull +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x551F7E8ull +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x551F7F0ull +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x551F7F8ull +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x551F800ull +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x551F808ull +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x551F810ull +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x551F818ull +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC2_QPC0_AXUSER_CONG_QUE_BASE 0x551FB80ull +#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_RXWQE_BASE 0x551FBE0ull +#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x551FC40ull +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_DB_FIFO_BASE 0x551FCA0ull +#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x551FD00ull +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x551FD60ull +#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_QPC_RESP_BASE 0x551FDC0ull +#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_QPC_REQ_BASE 0x551FE20ull +#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC2_QPC0_SPECIAL_BASE 0x551FE80ull +#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5520000ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5520080ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5520100ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5520180ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_0_SPECIAL_BASE 0x5520E80ull +#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5521000ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5521080ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5521100ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5521180ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_1_SPECIAL_BASE 0x5521E80ull +#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5522000ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5522080ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5522100ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5522180ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_2_SPECIAL_BASE 0x5522E80ull +#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5523000ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5523080ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5523100ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5523180ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_3_SPECIAL_BASE 0x5523E80ull +#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5524000ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5524080ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5524100ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5524180ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_4_SPECIAL_BASE 0x5524E80ull +#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5525000ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5525080ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5525100ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5525180ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_5_SPECIAL_BASE 0x5525E80ull +#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5526000ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5526080ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5526100ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5526180ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_6_SPECIAL_BASE 0x5526E80ull +#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5527000ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5527080ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5527100ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5527180ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_7_SPECIAL_BASE 0x5527E80ull +#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5528000ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5528080ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5528100ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5528180ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_8_SPECIAL_BASE 0x5528E80ull +#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5529000ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5529080ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5529100ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5529180ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_9_SPECIAL_BASE 0x5529E80ull +#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x552A000ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x552A080ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x552A100ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x552A180ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_10_SPECIAL_BASE 0x552AE80ull +#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x552B000ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x552B080ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x552B100ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x552B180ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_11_SPECIAL_BASE 0x552BE80ull +#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x552C000ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x552C080ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x552C100ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x552C180ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_12_SPECIAL_BASE 0x552CE80ull +#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x552D000ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x552D080ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x552D100ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x552D180ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_13_SPECIAL_BASE 0x552DE80ull +#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x552E000ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x552E080ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x552E100ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x552E180ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_14_SPECIAL_BASE 0x552EE80ull +#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM_DCCM1_BASE 0x5530000ull +#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM1_SECTION 0x8000 +#define mmNIC2_QM_ARC_AUX1_BASE 0x5538000ull +#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC2_QM_ARC_AUX1_SPECIAL_BASE 0x5538E80ull +#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM1_BASE 0x553A000ull +#define NIC2_QM1_MAX_OFFSET 0x1000 +#define NIC2_QM1_SECTION 0x9000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x553A900ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x553A908ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x553A910ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x553A918ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x553A920ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x553A928ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x553A930ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x553A938ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x553A940ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x553A948ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x553A950ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x553A958ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x553A960ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x553A968ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x553A970ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x553A978ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC2_QM1_AXUSER_SECURED_BASE 0x553AB00ull +#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC2_QM1_AXUSER_NONSECURED_BASE 0x553AB80ull +#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC2_QM1_DBG_HBW_BASE 0x553AC00ull +#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC2_QM1_DBG_LBW_BASE 0x553AC80ull +#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC2_QM1_CGM_BASE 0x553AD80ull +#define NIC2_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM1_CGM_SECTION 0x1000 +#define mmNIC2_QM1_SPECIAL_BASE 0x553AE80ull +#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC2_QPC1_BASE 0x553F000ull +#define NIC2_QPC1_MAX_OFFSET 0x1000 +#define NIC2_QPC1_SECTION 0x7200 +#define mmNIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x553F720ull +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x553F728ull +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x553F730ull +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x553F738ull +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x553F740ull +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x553F748ull +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x553F750ull +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x553F758ull +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x553F760ull +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x553F768ull +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x553F770ull +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x553F778ull +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x553F780ull +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x553F788ull +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x553F790ull +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x553F798ull +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x553F7A0ull +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x553F7A8ull +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x553F7B0ull +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x553F7B8ull +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x553F7C0ull +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x553F7C8ull +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x553F7D0ull +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x553F7D8ull +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x553F7E0ull +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x553F7E8ull +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x553F7F0ull +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x553F7F8ull +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x553F800ull +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x553F808ull +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x553F810ull +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x553F818ull +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC2_QPC1_AXUSER_CONG_QUE_BASE 0x553FB80ull +#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_RXWQE_BASE 0x553FBE0ull +#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x553FC40ull +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_DB_FIFO_BASE 0x553FCA0ull +#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x553FD00ull +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x553FD60ull +#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_QPC_RESP_BASE 0x553FDC0ull +#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_QPC_REQ_BASE 0x553FE20ull +#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC2_QPC1_SPECIAL_BASE 0x553FE80ull +#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC2_TMR_BASE 0x5548000ull +#define NIC2_TMR_MAX_OFFSET 0x1000 +#define NIC2_TMR_SECTION 0xD600 +#define mmNIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5548D60ull +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC2_TMR_AXUSER_TMR_FIFO_BASE 0x5548DC0ull +#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC2_TMR_AXUSER_TMR_FSM_BASE 0x5548E20ull +#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC2_TMR_SPECIAL_BASE 0x5548E80ull +#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXB_CORE_BASE 0x5549000ull +#define NIC2_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC2_RXB_CORE_SECTION 0x6100 +#define mmNIC2_RXB_CORE_SCT_AWUSER_BASE 0x5549610ull +#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC2_RXB_CORE_SPECIAL_BASE 0x5549E80ull +#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE0_BASE 0x554A000ull +#define NIC2_RXE0_MAX_OFFSET 0x1000 +#define NIC2_RXE0_SECTION 0x9000 +#define mmNIC2_RXE0_WQE_ARUSER_BASE 0x554A900ull +#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC2_RXE0_SPECIAL_BASE 0x554AE80ull +#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE1_BASE 0x554B000ull +#define NIC2_RXE1_MAX_OFFSET 0x1000 +#define NIC2_RXE1_SECTION 0x9000 +#define mmNIC2_RXE1_WQE_ARUSER_BASE 0x554B900ull +#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC2_RXE1_SPECIAL_BASE 0x554BE80ull +#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x554C000ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x554C050ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x554C0A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x554C0F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x554C140ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x554C190ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x554C1E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x554C230ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x554C280ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x554C2D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x554C320ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x554C370ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x554C3C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x554C410ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x554C460ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x554C4B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x554C500ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x554C550ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x554C5A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x554C5F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x554C640ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x554C690ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x554C6E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x554C730ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x554C780ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x554C7D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x554C820ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x554C870ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x554C8C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x554C910ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x554C960ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x554C9B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC2_RXE0_AXUSER_SPECIAL_BASE 0x554CE80ull +#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x554D000ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x554D050ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x554D0A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x554D0F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x554D140ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x554D190ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x554D1E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x554D230ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x554D280ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x554D2D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x554D320ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x554D370ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x554D3C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x554D410ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x554D460ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x554D4B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x554D500ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x554D550ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x554D5A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x554D5F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x554D640ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x554D690ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x554D6E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x554D730ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x554D780ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x554D7D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x554D820ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x554D870ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x554D8C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x554D910ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x554D960ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x554D9B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC2_RXE1_AXUSER_SPECIAL_BASE 0x554DE80ull +#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC2_TXS0_BASE 0x5550000ull +#define NIC2_TXS0_MAX_OFFSET 0x1000 +#define NIC2_TXS0_SECTION 0xE800 +#define mmNIC2_TXS0_SPECIAL_BASE 0x5550E80ull +#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXS1_BASE 0x5551000ull +#define NIC2_TXS1_MAX_OFFSET 0x1000 +#define NIC2_TXS1_SECTION 0xE800 +#define mmNIC2_TXS1_SPECIAL_BASE 0x5551E80ull +#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXE0_BASE 0x5552000ull +#define NIC2_TXE0_MAX_OFFSET 0x1000 +#define NIC2_TXE0_SECTION 0xE800 +#define mmNIC2_TXE0_SPECIAL_BASE 0x5552E80ull +#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXE1_BASE 0x5553000ull +#define NIC2_TXE1_MAX_OFFSET 0x1000 +#define NIC2_TXE1_SECTION 0xE800 +#define mmNIC2_TXE1_SPECIAL_BASE 0x5553E80ull +#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXB_BASE 0x5554000ull +#define NIC2_TXB_MAX_OFFSET 0x1000 +#define NIC2_TXB_SECTION 0xE800 +#define mmNIC2_TXB_SPECIAL_BASE 0x5554E80ull +#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x5555000ull +#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x5555200ull +#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x5555400ull +#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x5555600ull +#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_E2E_CRDT_BASE 0x5555800ull +#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC2_MSTR_IF_AXUSER_BASE 0x5555A80ull +#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC2_MSTR_IF_DBG_HBW_BASE 0x5555B00ull +#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC2_MSTR_IF_DBG_LBW_BASE 0x5555B80ull +#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC2_MSTR_IF_CORE_HBW_BASE 0x5555C00ull +#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC2_MSTR_IF_CORE_LBW_BASE 0x5555D80ull +#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC2_MSTR_IF_SPECIAL_BASE 0x5555E80ull +#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC2_TX_AXUSER_BASE 0x5556000ull +#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_TX_AXUSER_SECTION 0x2000 +#define mmNIC2_SERDES0_BASE 0x5558000ull +#define NIC2_SERDES0_MAX_OFFSET 0x3E40 +#define NIC2_SERDES0_SECTION 0x4000 +#define mmNIC2_SERDES1_BASE 0x555C000ull +#define NIC2_SERDES1_MAX_OFFSET 0x3E40 +#define NIC2_SERDES1_SECTION 0x4000 +#define mmNIC2_PHY_BASE 0x5560000ull +#define NIC2_PHY_MAX_OFFSET 0x1000 +#define NIC2_PHY_SECTION 0xE800 +#define mmNIC2_PHY_SPECIAL_BASE 0x5560E80ull +#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT2_MAC_AUX_BASE 0x5568000ull +#define PRT2_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT2_MAC_AUX_SECTION 0xE800 +#define mmPRT2_MAC_AUX_SPECIAL_BASE 0x5568E80ull +#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT2_MAC_CORE_BASE 0x5569000ull +#define PRT2_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT2_MAC_CORE_SECTION 0xE800 +#define mmPRT2_MAC_CORE_SPECIAL_BASE 0x5569E80ull +#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC2_MAC_RS_FEC_BASE 0x556A000ull +#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC2_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC2_MAC_GLOB_STAT_CONTROL_REG_BASE 0x556B000ull +#define NIC2_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC2_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC2_MAC_GLOB_STAT_RX0_BASE 0x556B100ull +#define NIC2_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX1_BASE 0x556B18Cull +#define NIC2_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX2_BASE 0x556B218ull +#define NIC2_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX3_BASE 0x556B2A4ull +#define NIC2_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_TX0_BASE 0x556B330ull +#define NIC2_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX1_BASE 0x556B398ull +#define NIC2_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX2_BASE 0x556B400ull +#define NIC2_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX3_BASE 0x556B468ull +#define NIC2_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC2_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x556B800ull +#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC2_MAC_CH0_MAC_PCS_BASE 0x556C000ull +#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH0_MAC_128_BASE 0x556C400ull +#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH0_MAC_AN_BASE 0x556C800ull +#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH1_MAC_PCS_BASE 0x556D000ull +#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH1_MAC_128_BASE 0x556D400ull +#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH1_MAC_AN_BASE 0x556D800ull +#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH2_MAC_PCS_BASE 0x556E000ull +#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH2_MAC_128_BASE 0x556E400ull +#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH2_MAC_AN_BASE 0x556E800ull +#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH3_MAC_PCS_BASE 0x556F000ull +#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH3_MAC_128_BASE 0x556F400ull +#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH3_MAC_AN_BASE 0x556F800ull +#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5580000ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5580080ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5580100ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5580180ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_0_SPECIAL_BASE 0x5580E80ull +#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5581000ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5581080ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5581100ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5581180ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_1_SPECIAL_BASE 0x5581E80ull +#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5582000ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5582080ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5582100ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5582180ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_2_SPECIAL_BASE 0x5582E80ull +#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5583000ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5583080ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5583100ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5583180ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_3_SPECIAL_BASE 0x5583E80ull +#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5584000ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5584080ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5584100ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5584180ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_4_SPECIAL_BASE 0x5584E80ull +#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5585000ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5585080ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5585100ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5585180ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_5_SPECIAL_BASE 0x5585E80ull +#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5586000ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5586080ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5586100ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5586180ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_6_SPECIAL_BASE 0x5586E80ull +#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5587000ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5587080ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5587100ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5587180ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_7_SPECIAL_BASE 0x5587E80ull +#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5588000ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5588080ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5588100ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5588180ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_8_SPECIAL_BASE 0x5588E80ull +#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5589000ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5589080ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5589100ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5589180ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_9_SPECIAL_BASE 0x5589E80ull +#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x558A000ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x558A080ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x558A100ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x558A180ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_10_SPECIAL_BASE 0x558AE80ull +#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x558B000ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x558B080ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x558B100ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x558B180ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_11_SPECIAL_BASE 0x558BE80ull +#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x558C000ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x558C080ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x558C100ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x558C180ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_12_SPECIAL_BASE 0x558CE80ull +#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x558D000ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x558D080ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x558D100ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x558D180ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_13_SPECIAL_BASE 0x558DE80ull +#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x558E000ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x558E080ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x558E100ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x558E180ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_14_SPECIAL_BASE 0x558EE80ull +#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM_DCCM0_BASE 0x5590000ull +#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM0_SECTION 0x8000 +#define mmNIC3_QM_ARC_AUX0_BASE 0x5598000ull +#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC3_QM_ARC_AUX0_SPECIAL_BASE 0x5598E80ull +#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM0_BASE 0x559A000ull +#define NIC3_QM0_MAX_OFFSET 0x1000 +#define NIC3_QM0_SECTION 0x9000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x559A900ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x559A908ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x559A910ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x559A918ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x559A920ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x559A928ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x559A930ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x559A938ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x559A940ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x559A948ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x559A950ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x559A958ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x559A960ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x559A968ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x559A970ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x559A978ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC3_QM0_AXUSER_SECURED_BASE 0x559AB00ull +#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC3_QM0_AXUSER_NONSECURED_BASE 0x559AB80ull +#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC3_QM0_DBG_HBW_BASE 0x559AC00ull +#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC3_QM0_DBG_LBW_BASE 0x559AC80ull +#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC3_QM0_CGM_BASE 0x559AD80ull +#define NIC3_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM0_CGM_SECTION 0x1000 +#define mmNIC3_QM0_SPECIAL_BASE 0x559AE80ull +#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC3_QPC0_BASE 0x559F000ull +#define NIC3_QPC0_MAX_OFFSET 0x1000 +#define NIC3_QPC0_SECTION 0x7200 +#define mmNIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x559F720ull +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x559F728ull +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x559F730ull +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x559F738ull +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x559F740ull +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x559F748ull +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x559F750ull +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x559F758ull +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x559F760ull +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x559F768ull +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x559F770ull +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x559F778ull +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x559F780ull +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x559F788ull +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x559F790ull +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x559F798ull +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x559F7A0ull +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x559F7A8ull +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x559F7B0ull +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x559F7B8ull +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x559F7C0ull +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x559F7C8ull +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x559F7D0ull +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x559F7D8ull +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x559F7E0ull +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x559F7E8ull +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x559F7F0ull +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x559F7F8ull +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x559F800ull +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x559F808ull +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x559F810ull +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x559F818ull +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC3_QPC0_AXUSER_CONG_QUE_BASE 0x559FB80ull +#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_RXWQE_BASE 0x559FBE0ull +#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x559FC40ull +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_DB_FIFO_BASE 0x559FCA0ull +#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x559FD00ull +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x559FD60ull +#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_QPC_RESP_BASE 0x559FDC0ull +#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_QPC_REQ_BASE 0x559FE20ull +#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC3_QPC0_SPECIAL_BASE 0x559FE80ull +#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x55A0000ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x55A0080ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x55A0100ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x55A0180ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_0_SPECIAL_BASE 0x55A0E80ull +#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x55A1000ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x55A1080ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x55A1100ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x55A1180ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_1_SPECIAL_BASE 0x55A1E80ull +#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x55A2000ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x55A2080ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x55A2100ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x55A2180ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_2_SPECIAL_BASE 0x55A2E80ull +#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x55A3000ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x55A3080ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x55A3100ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x55A3180ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_3_SPECIAL_BASE 0x55A3E80ull +#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x55A4000ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x55A4080ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x55A4100ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x55A4180ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_4_SPECIAL_BASE 0x55A4E80ull +#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x55A5000ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x55A5080ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x55A5100ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x55A5180ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_5_SPECIAL_BASE 0x55A5E80ull +#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x55A6000ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x55A6080ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x55A6100ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x55A6180ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_6_SPECIAL_BASE 0x55A6E80ull +#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x55A7000ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x55A7080ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x55A7100ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x55A7180ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_7_SPECIAL_BASE 0x55A7E80ull +#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x55A8000ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x55A8080ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x55A8100ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x55A8180ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_8_SPECIAL_BASE 0x55A8E80ull +#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x55A9000ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x55A9080ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x55A9100ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x55A9180ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_9_SPECIAL_BASE 0x55A9E80ull +#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x55AA000ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x55AA080ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x55AA100ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x55AA180ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_10_SPECIAL_BASE 0x55AAE80ull +#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x55AB000ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x55AB080ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x55AB100ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x55AB180ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_11_SPECIAL_BASE 0x55ABE80ull +#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x55AC000ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x55AC080ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x55AC100ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x55AC180ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_12_SPECIAL_BASE 0x55ACE80ull +#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x55AD000ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x55AD080ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x55AD100ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x55AD180ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_13_SPECIAL_BASE 0x55ADE80ull +#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x55AE000ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x55AE080ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x55AE100ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x55AE180ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_14_SPECIAL_BASE 0x55AEE80ull +#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM_DCCM1_BASE 0x55B0000ull +#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM1_SECTION 0x8000 +#define mmNIC3_QM_ARC_AUX1_BASE 0x55B8000ull +#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC3_QM_ARC_AUX1_SPECIAL_BASE 0x55B8E80ull +#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM1_BASE 0x55BA000ull +#define NIC3_QM1_MAX_OFFSET 0x1000 +#define NIC3_QM1_SECTION 0x9000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x55BA900ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x55BA908ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x55BA910ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x55BA918ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x55BA920ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x55BA928ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x55BA930ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x55BA938ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x55BA940ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x55BA948ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x55BA950ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x55BA958ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x55BA960ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x55BA968ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x55BA970ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x55BA978ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC3_QM1_AXUSER_SECURED_BASE 0x55BAB00ull +#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC3_QM1_AXUSER_NONSECURED_BASE 0x55BAB80ull +#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC3_QM1_DBG_HBW_BASE 0x55BAC00ull +#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC3_QM1_DBG_LBW_BASE 0x55BAC80ull +#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC3_QM1_CGM_BASE 0x55BAD80ull +#define NIC3_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM1_CGM_SECTION 0x1000 +#define mmNIC3_QM1_SPECIAL_BASE 0x55BAE80ull +#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC3_QPC1_BASE 0x55BF000ull +#define NIC3_QPC1_MAX_OFFSET 0x1000 +#define NIC3_QPC1_SECTION 0x7200 +#define mmNIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x55BF720ull +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x55BF728ull +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x55BF730ull +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x55BF738ull +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x55BF740ull +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x55BF748ull +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x55BF750ull +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x55BF758ull +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x55BF760ull +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x55BF768ull +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x55BF770ull +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x55BF778ull +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x55BF780ull +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x55BF788ull +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x55BF790ull +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x55BF798ull +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x55BF7A0ull +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x55BF7A8ull +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x55BF7B0ull +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x55BF7B8ull +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x55BF7C0ull +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x55BF7C8ull +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x55BF7D0ull +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x55BF7D8ull +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x55BF7E0ull +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x55BF7E8ull +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x55BF7F0ull +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x55BF7F8ull +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x55BF800ull +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x55BF808ull +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x55BF810ull +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x55BF818ull +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC3_QPC1_AXUSER_CONG_QUE_BASE 0x55BFB80ull +#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_RXWQE_BASE 0x55BFBE0ull +#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x55BFC40ull +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_DB_FIFO_BASE 0x55BFCA0ull +#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x55BFD00ull +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x55BFD60ull +#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_QPC_RESP_BASE 0x55BFDC0ull +#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_QPC_REQ_BASE 0x55BFE20ull +#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC3_QPC1_SPECIAL_BASE 0x55BFE80ull +#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC3_TMR_BASE 0x55C8000ull +#define NIC3_TMR_MAX_OFFSET 0x1000 +#define NIC3_TMR_SECTION 0xD600 +#define mmNIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x55C8D60ull +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC3_TMR_AXUSER_TMR_FIFO_BASE 0x55C8DC0ull +#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC3_TMR_AXUSER_TMR_FSM_BASE 0x55C8E20ull +#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC3_TMR_SPECIAL_BASE 0x55C8E80ull +#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXB_CORE_BASE 0x55C9000ull +#define NIC3_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC3_RXB_CORE_SECTION 0x6100 +#define mmNIC3_RXB_CORE_SCT_AWUSER_BASE 0x55C9610ull +#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC3_RXB_CORE_SPECIAL_BASE 0x55C9E80ull +#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE0_BASE 0x55CA000ull +#define NIC3_RXE0_MAX_OFFSET 0x1000 +#define NIC3_RXE0_SECTION 0x9000 +#define mmNIC3_RXE0_WQE_ARUSER_BASE 0x55CA900ull +#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC3_RXE0_SPECIAL_BASE 0x55CAE80ull +#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE1_BASE 0x55CB000ull +#define NIC3_RXE1_MAX_OFFSET 0x1000 +#define NIC3_RXE1_SECTION 0x9000 +#define mmNIC3_RXE1_WQE_ARUSER_BASE 0x55CB900ull +#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC3_RXE1_SPECIAL_BASE 0x55CBE80ull +#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x55CC000ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x55CC050ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x55CC0A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x55CC0F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x55CC140ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x55CC190ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x55CC1E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x55CC230ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x55CC280ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x55CC2D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x55CC320ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x55CC370ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x55CC3C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x55CC410ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x55CC460ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x55CC4B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x55CC500ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x55CC550ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x55CC5A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x55CC5F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x55CC640ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x55CC690ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x55CC6E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x55CC730ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x55CC780ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x55CC7D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x55CC820ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x55CC870ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x55CC8C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x55CC910ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x55CC960ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x55CC9B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC3_RXE0_AXUSER_SPECIAL_BASE 0x55CCE80ull +#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x55CD000ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x55CD050ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x55CD0A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x55CD0F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x55CD140ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x55CD190ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x55CD1E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x55CD230ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x55CD280ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x55CD2D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x55CD320ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x55CD370ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x55CD3C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x55CD410ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x55CD460ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x55CD4B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x55CD500ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x55CD550ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x55CD5A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x55CD5F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x55CD640ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x55CD690ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x55CD6E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x55CD730ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x55CD780ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x55CD7D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x55CD820ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x55CD870ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x55CD8C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x55CD910ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x55CD960ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x55CD9B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC3_RXE1_AXUSER_SPECIAL_BASE 0x55CDE80ull +#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC3_TXS0_BASE 0x55D0000ull +#define NIC3_TXS0_MAX_OFFSET 0x1000 +#define NIC3_TXS0_SECTION 0xE800 +#define mmNIC3_TXS0_SPECIAL_BASE 0x55D0E80ull +#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXS1_BASE 0x55D1000ull +#define NIC3_TXS1_MAX_OFFSET 0x1000 +#define NIC3_TXS1_SECTION 0xE800 +#define mmNIC3_TXS1_SPECIAL_BASE 0x55D1E80ull +#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXE0_BASE 0x55D2000ull +#define NIC3_TXE0_MAX_OFFSET 0x1000 +#define NIC3_TXE0_SECTION 0xE800 +#define mmNIC3_TXE0_SPECIAL_BASE 0x55D2E80ull +#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXE1_BASE 0x55D3000ull +#define NIC3_TXE1_MAX_OFFSET 0x1000 +#define NIC3_TXE1_SECTION 0xE800 +#define mmNIC3_TXE1_SPECIAL_BASE 0x55D3E80ull +#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXB_BASE 0x55D4000ull +#define NIC3_TXB_MAX_OFFSET 0x1000 +#define NIC3_TXB_SECTION 0xE800 +#define mmNIC3_TXB_SPECIAL_BASE 0x55D4E80ull +#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x55D5000ull +#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x55D5200ull +#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x55D5400ull +#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x55D5600ull +#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_E2E_CRDT_BASE 0x55D5800ull +#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC3_MSTR_IF_AXUSER_BASE 0x55D5A80ull +#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC3_MSTR_IF_DBG_HBW_BASE 0x55D5B00ull +#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC3_MSTR_IF_DBG_LBW_BASE 0x55D5B80ull +#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC3_MSTR_IF_CORE_HBW_BASE 0x55D5C00ull +#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC3_MSTR_IF_CORE_LBW_BASE 0x55D5D80ull +#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC3_MSTR_IF_SPECIAL_BASE 0x55D5E80ull +#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC3_TX_AXUSER_BASE 0x55D6000ull +#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_TX_AXUSER_SECTION 0x2000 +#define mmNIC3_SERDES0_BASE 0x55D8000ull +#define NIC3_SERDES0_MAX_OFFSET 0x3E40 +#define NIC3_SERDES0_SECTION 0x4000 +#define mmNIC3_SERDES1_BASE 0x55DC000ull +#define NIC3_SERDES1_MAX_OFFSET 0x3E40 +#define NIC3_SERDES1_SECTION 0x4000 +#define mmNIC3_PHY_BASE 0x55E0000ull +#define NIC3_PHY_MAX_OFFSET 0x1000 +#define NIC3_PHY_SECTION 0xE800 +#define mmNIC3_PHY_SPECIAL_BASE 0x55E0E80ull +#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT3_MAC_AUX_BASE 0x55E8000ull +#define PRT3_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT3_MAC_AUX_SECTION 0xE800 +#define mmPRT3_MAC_AUX_SPECIAL_BASE 0x55E8E80ull +#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT3_MAC_CORE_BASE 0x55E9000ull +#define PRT3_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT3_MAC_CORE_SECTION 0xE800 +#define mmPRT3_MAC_CORE_SPECIAL_BASE 0x55E9E80ull +#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC3_MAC_RS_FEC_BASE 0x55EA000ull +#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC3_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC3_MAC_GLOB_STAT_CONTROL_REG_BASE 0x55EB000ull +#define NIC3_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC3_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC3_MAC_GLOB_STAT_RX0_BASE 0x55EB100ull +#define NIC3_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX1_BASE 0x55EB18Cull +#define NIC3_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX2_BASE 0x55EB218ull +#define NIC3_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX3_BASE 0x55EB2A4ull +#define NIC3_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_TX0_BASE 0x55EB330ull +#define NIC3_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX1_BASE 0x55EB398ull +#define NIC3_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX2_BASE 0x55EB400ull +#define NIC3_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX3_BASE 0x55EB468ull +#define NIC3_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC3_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x55EB800ull +#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC3_MAC_CH0_MAC_PCS_BASE 0x55EC000ull +#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH0_MAC_128_BASE 0x55EC400ull +#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH0_MAC_AN_BASE 0x55EC800ull +#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH1_MAC_PCS_BASE 0x55ED000ull +#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH1_MAC_128_BASE 0x55ED400ull +#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH1_MAC_AN_BASE 0x55ED800ull +#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH2_MAC_PCS_BASE 0x55EE000ull +#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH2_MAC_128_BASE 0x55EE400ull +#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH2_MAC_AN_BASE 0x55EE800ull +#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH3_MAC_PCS_BASE 0x55EF000ull +#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH3_MAC_128_BASE 0x55EF400ull +#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH3_MAC_AN_BASE 0x55EF800ull +#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5600000ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5600080ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5600100ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5600180ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_0_SPECIAL_BASE 0x5600E80ull +#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5601000ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5601080ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5601100ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5601180ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_1_SPECIAL_BASE 0x5601E80ull +#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5602000ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5602080ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5602100ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5602180ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_2_SPECIAL_BASE 0x5602E80ull +#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5603000ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5603080ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5603100ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5603180ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_3_SPECIAL_BASE 0x5603E80ull +#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5604000ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5604080ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5604100ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5604180ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_4_SPECIAL_BASE 0x5604E80ull +#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5605000ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5605080ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5605100ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5605180ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_5_SPECIAL_BASE 0x5605E80ull +#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5606000ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5606080ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5606100ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5606180ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_6_SPECIAL_BASE 0x5606E80ull +#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5607000ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5607080ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5607100ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5607180ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_7_SPECIAL_BASE 0x5607E80ull +#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5608000ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5608080ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5608100ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5608180ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_8_SPECIAL_BASE 0x5608E80ull +#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5609000ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5609080ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5609100ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5609180ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_9_SPECIAL_BASE 0x5609E80ull +#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x560A000ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x560A080ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x560A100ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x560A180ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_10_SPECIAL_BASE 0x560AE80ull +#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x560B000ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x560B080ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x560B100ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x560B180ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_11_SPECIAL_BASE 0x560BE80ull +#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x560C000ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x560C080ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x560C100ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x560C180ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_12_SPECIAL_BASE 0x560CE80ull +#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x560D000ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x560D080ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x560D100ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x560D180ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_13_SPECIAL_BASE 0x560DE80ull +#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x560E000ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x560E080ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x560E100ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x560E180ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_14_SPECIAL_BASE 0x560EE80ull +#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM_DCCM0_BASE 0x5610000ull +#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM0_SECTION 0x8000 +#define mmNIC4_QM_ARC_AUX0_BASE 0x5618000ull +#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC4_QM_ARC_AUX0_SPECIAL_BASE 0x5618E80ull +#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM0_BASE 0x561A000ull +#define NIC4_QM0_MAX_OFFSET 0x1000 +#define NIC4_QM0_SECTION 0x9000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x561A900ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x561A908ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x561A910ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x561A918ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x561A920ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x561A928ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x561A930ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x561A938ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x561A940ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x561A948ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x561A950ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x561A958ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x561A960ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x561A968ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x561A970ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x561A978ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC4_QM0_AXUSER_SECURED_BASE 0x561AB00ull +#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC4_QM0_AXUSER_NONSECURED_BASE 0x561AB80ull +#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC4_QM0_DBG_HBW_BASE 0x561AC00ull +#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC4_QM0_DBG_LBW_BASE 0x561AC80ull +#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC4_QM0_CGM_BASE 0x561AD80ull +#define NIC4_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM0_CGM_SECTION 0x1000 +#define mmNIC4_QM0_SPECIAL_BASE 0x561AE80ull +#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC4_QPC0_BASE 0x561F000ull +#define NIC4_QPC0_MAX_OFFSET 0x1000 +#define NIC4_QPC0_SECTION 0x7200 +#define mmNIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x561F720ull +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x561F728ull +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x561F730ull +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x561F738ull +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x561F740ull +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x561F748ull +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x561F750ull +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x561F758ull +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x561F760ull +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x561F768ull +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x561F770ull +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x561F778ull +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x561F780ull +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x561F788ull +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x561F790ull +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x561F798ull +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x561F7A0ull +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x561F7A8ull +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x561F7B0ull +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x561F7B8ull +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x561F7C0ull +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x561F7C8ull +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x561F7D0ull +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x561F7D8ull +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x561F7E0ull +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x561F7E8ull +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x561F7F0ull +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x561F7F8ull +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x561F800ull +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x561F808ull +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x561F810ull +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x561F818ull +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC4_QPC0_AXUSER_CONG_QUE_BASE 0x561FB80ull +#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_RXWQE_BASE 0x561FBE0ull +#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x561FC40ull +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_DB_FIFO_BASE 0x561FCA0ull +#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x561FD00ull +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x561FD60ull +#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_QPC_RESP_BASE 0x561FDC0ull +#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_QPC_REQ_BASE 0x561FE20ull +#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC4_QPC0_SPECIAL_BASE 0x561FE80ull +#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5620000ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5620080ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5620100ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5620180ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_0_SPECIAL_BASE 0x5620E80ull +#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5621000ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5621080ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5621100ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5621180ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_1_SPECIAL_BASE 0x5621E80ull +#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5622000ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5622080ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5622100ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5622180ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_2_SPECIAL_BASE 0x5622E80ull +#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5623000ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5623080ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5623100ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5623180ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_3_SPECIAL_BASE 0x5623E80ull +#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5624000ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5624080ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5624100ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5624180ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_4_SPECIAL_BASE 0x5624E80ull +#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5625000ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5625080ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5625100ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5625180ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_5_SPECIAL_BASE 0x5625E80ull +#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5626000ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5626080ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5626100ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5626180ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_6_SPECIAL_BASE 0x5626E80ull +#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5627000ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5627080ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5627100ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5627180ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_7_SPECIAL_BASE 0x5627E80ull +#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5628000ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5628080ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5628100ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5628180ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_8_SPECIAL_BASE 0x5628E80ull +#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5629000ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5629080ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5629100ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5629180ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_9_SPECIAL_BASE 0x5629E80ull +#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x562A000ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x562A080ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x562A100ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x562A180ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_10_SPECIAL_BASE 0x562AE80ull +#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x562B000ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x562B080ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x562B100ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x562B180ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_11_SPECIAL_BASE 0x562BE80ull +#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x562C000ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x562C080ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x562C100ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x562C180ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_12_SPECIAL_BASE 0x562CE80ull +#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x562D000ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x562D080ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x562D100ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x562D180ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_13_SPECIAL_BASE 0x562DE80ull +#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x562E000ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x562E080ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x562E100ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x562E180ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_14_SPECIAL_BASE 0x562EE80ull +#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM_DCCM1_BASE 0x5630000ull +#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM1_SECTION 0x8000 +#define mmNIC4_QM_ARC_AUX1_BASE 0x5638000ull +#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC4_QM_ARC_AUX1_SPECIAL_BASE 0x5638E80ull +#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM1_BASE 0x563A000ull +#define NIC4_QM1_MAX_OFFSET 0x1000 +#define NIC4_QM1_SECTION 0x9000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x563A900ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x563A908ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x563A910ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x563A918ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x563A920ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x563A928ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x563A930ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x563A938ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x563A940ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x563A948ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x563A950ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x563A958ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x563A960ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x563A968ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x563A970ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x563A978ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC4_QM1_AXUSER_SECURED_BASE 0x563AB00ull +#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC4_QM1_AXUSER_NONSECURED_BASE 0x563AB80ull +#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC4_QM1_DBG_HBW_BASE 0x563AC00ull +#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC4_QM1_DBG_LBW_BASE 0x563AC80ull +#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC4_QM1_CGM_BASE 0x563AD80ull +#define NIC4_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM1_CGM_SECTION 0x1000 +#define mmNIC4_QM1_SPECIAL_BASE 0x563AE80ull +#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC4_QPC1_BASE 0x563F000ull +#define NIC4_QPC1_MAX_OFFSET 0x1000 +#define NIC4_QPC1_SECTION 0x7200 +#define mmNIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x563F720ull +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x563F728ull +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x563F730ull +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x563F738ull +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x563F740ull +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x563F748ull +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x563F750ull +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x563F758ull +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x563F760ull +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x563F768ull +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x563F770ull +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x563F778ull +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x563F780ull +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x563F788ull +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x563F790ull +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x563F798ull +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x563F7A0ull +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x563F7A8ull +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x563F7B0ull +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x563F7B8ull +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x563F7C0ull +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x563F7C8ull +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x563F7D0ull +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x563F7D8ull +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x563F7E0ull +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x563F7E8ull +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x563F7F0ull +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x563F7F8ull +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x563F800ull +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x563F808ull +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x563F810ull +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x563F818ull +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC4_QPC1_AXUSER_CONG_QUE_BASE 0x563FB80ull +#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_RXWQE_BASE 0x563FBE0ull +#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x563FC40ull +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_DB_FIFO_BASE 0x563FCA0ull +#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x563FD00ull +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x563FD60ull +#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_QPC_RESP_BASE 0x563FDC0ull +#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_QPC_REQ_BASE 0x563FE20ull +#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC4_QPC1_SPECIAL_BASE 0x563FE80ull +#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC4_TMR_BASE 0x5648000ull +#define NIC4_TMR_MAX_OFFSET 0x1000 +#define NIC4_TMR_SECTION 0xD600 +#define mmNIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5648D60ull +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC4_TMR_AXUSER_TMR_FIFO_BASE 0x5648DC0ull +#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC4_TMR_AXUSER_TMR_FSM_BASE 0x5648E20ull +#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC4_TMR_SPECIAL_BASE 0x5648E80ull +#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXB_CORE_BASE 0x5649000ull +#define NIC4_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC4_RXB_CORE_SECTION 0x6100 +#define mmNIC4_RXB_CORE_SCT_AWUSER_BASE 0x5649610ull +#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC4_RXB_CORE_SPECIAL_BASE 0x5649E80ull +#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE0_BASE 0x564A000ull +#define NIC4_RXE0_MAX_OFFSET 0x1000 +#define NIC4_RXE0_SECTION 0x9000 +#define mmNIC4_RXE0_WQE_ARUSER_BASE 0x564A900ull +#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC4_RXE0_SPECIAL_BASE 0x564AE80ull +#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE1_BASE 0x564B000ull +#define NIC4_RXE1_MAX_OFFSET 0x1000 +#define NIC4_RXE1_SECTION 0x9000 +#define mmNIC4_RXE1_WQE_ARUSER_BASE 0x564B900ull +#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC4_RXE1_SPECIAL_BASE 0x564BE80ull +#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x564C000ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x564C050ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x564C0A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x564C0F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x564C140ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x564C190ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x564C1E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x564C230ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x564C280ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x564C2D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x564C320ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x564C370ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x564C3C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x564C410ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x564C460ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x564C4B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x564C500ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x564C550ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x564C5A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x564C5F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x564C640ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x564C690ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x564C6E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x564C730ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x564C780ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x564C7D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x564C820ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x564C870ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x564C8C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x564C910ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x564C960ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x564C9B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC4_RXE0_AXUSER_SPECIAL_BASE 0x564CE80ull +#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x564D000ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x564D050ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x564D0A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x564D0F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x564D140ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x564D190ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x564D1E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x564D230ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x564D280ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x564D2D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x564D320ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x564D370ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x564D3C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x564D410ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x564D460ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x564D4B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x564D500ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x564D550ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x564D5A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x564D5F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x564D640ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x564D690ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x564D6E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x564D730ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x564D780ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x564D7D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x564D820ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x564D870ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x564D8C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x564D910ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x564D960ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x564D9B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC4_RXE1_AXUSER_SPECIAL_BASE 0x564DE80ull +#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC4_TXS0_BASE 0x5650000ull +#define NIC4_TXS0_MAX_OFFSET 0x1000 +#define NIC4_TXS0_SECTION 0xE800 +#define mmNIC4_TXS0_SPECIAL_BASE 0x5650E80ull +#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXS1_BASE 0x5651000ull +#define NIC4_TXS1_MAX_OFFSET 0x1000 +#define NIC4_TXS1_SECTION 0xE800 +#define mmNIC4_TXS1_SPECIAL_BASE 0x5651E80ull +#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXE0_BASE 0x5652000ull +#define NIC4_TXE0_MAX_OFFSET 0x1000 +#define NIC4_TXE0_SECTION 0xE800 +#define mmNIC4_TXE0_SPECIAL_BASE 0x5652E80ull +#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXE1_BASE 0x5653000ull +#define NIC4_TXE1_MAX_OFFSET 0x1000 +#define NIC4_TXE1_SECTION 0xE800 +#define mmNIC4_TXE1_SPECIAL_BASE 0x5653E80ull +#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXB_BASE 0x5654000ull +#define NIC4_TXB_MAX_OFFSET 0x1000 +#define NIC4_TXB_SECTION 0xE800 +#define mmNIC4_TXB_SPECIAL_BASE 0x5654E80ull +#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x5655000ull +#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x5655200ull +#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x5655400ull +#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x5655600ull +#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_E2E_CRDT_BASE 0x5655800ull +#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC4_MSTR_IF_AXUSER_BASE 0x5655A80ull +#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC4_MSTR_IF_DBG_HBW_BASE 0x5655B00ull +#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC4_MSTR_IF_DBG_LBW_BASE 0x5655B80ull +#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC4_MSTR_IF_CORE_HBW_BASE 0x5655C00ull +#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC4_MSTR_IF_CORE_LBW_BASE 0x5655D80ull +#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC4_MSTR_IF_SPECIAL_BASE 0x5655E80ull +#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC4_TX_AXUSER_BASE 0x5656000ull +#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_TX_AXUSER_SECTION 0x2000 +#define mmNIC4_SERDES0_BASE 0x5658000ull +#define NIC4_SERDES0_MAX_OFFSET 0x3E40 +#define NIC4_SERDES0_SECTION 0x4000 +#define mmNIC4_SERDES1_BASE 0x565C000ull +#define NIC4_SERDES1_MAX_OFFSET 0x3E40 +#define NIC4_SERDES1_SECTION 0x4000 +#define mmNIC4_PHY_BASE 0x5660000ull +#define NIC4_PHY_MAX_OFFSET 0x1000 +#define NIC4_PHY_SECTION 0xE800 +#define mmNIC4_PHY_SPECIAL_BASE 0x5660E80ull +#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT4_MAC_AUX_BASE 0x5668000ull +#define PRT4_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT4_MAC_AUX_SECTION 0xE800 +#define mmPRT4_MAC_AUX_SPECIAL_BASE 0x5668E80ull +#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT4_MAC_CORE_BASE 0x5669000ull +#define PRT4_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT4_MAC_CORE_SECTION 0xE800 +#define mmPRT4_MAC_CORE_SPECIAL_BASE 0x5669E80ull +#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC4_MAC_RS_FEC_BASE 0x566A000ull +#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC4_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC4_MAC_GLOB_STAT_CONTROL_REG_BASE 0x566B000ull +#define NIC4_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC4_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC4_MAC_GLOB_STAT_RX0_BASE 0x566B100ull +#define NIC4_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX1_BASE 0x566B18Cull +#define NIC4_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX2_BASE 0x566B218ull +#define NIC4_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX3_BASE 0x566B2A4ull +#define NIC4_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_TX0_BASE 0x566B330ull +#define NIC4_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX1_BASE 0x566B398ull +#define NIC4_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX2_BASE 0x566B400ull +#define NIC4_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX3_BASE 0x566B468ull +#define NIC4_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC4_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x566B800ull +#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC4_MAC_CH0_MAC_PCS_BASE 0x566C000ull +#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH0_MAC_128_BASE 0x566C400ull +#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH0_MAC_AN_BASE 0x566C800ull +#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH1_MAC_PCS_BASE 0x566D000ull +#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH1_MAC_128_BASE 0x566D400ull +#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH1_MAC_AN_BASE 0x566D800ull +#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH2_MAC_PCS_BASE 0x566E000ull +#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH2_MAC_128_BASE 0x566E400ull +#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH2_MAC_AN_BASE 0x566E800ull +#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH3_MAC_PCS_BASE 0x566F000ull +#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH3_MAC_128_BASE 0x566F400ull +#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH3_MAC_AN_BASE 0x566F800ull +#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5680000ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5680080ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5680100ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5680180ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_0_SPECIAL_BASE 0x5680E80ull +#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5681000ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5681080ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5681100ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5681180ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_1_SPECIAL_BASE 0x5681E80ull +#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5682000ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5682080ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5682100ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5682180ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_2_SPECIAL_BASE 0x5682E80ull +#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5683000ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5683080ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5683100ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5683180ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_3_SPECIAL_BASE 0x5683E80ull +#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5684000ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5684080ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5684100ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5684180ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_4_SPECIAL_BASE 0x5684E80ull +#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5685000ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5685080ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5685100ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5685180ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_5_SPECIAL_BASE 0x5685E80ull +#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5686000ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5686080ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5686100ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5686180ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_6_SPECIAL_BASE 0x5686E80ull +#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5687000ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5687080ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5687100ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5687180ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_7_SPECIAL_BASE 0x5687E80ull +#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5688000ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5688080ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5688100ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5688180ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_8_SPECIAL_BASE 0x5688E80ull +#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5689000ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5689080ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5689100ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5689180ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_9_SPECIAL_BASE 0x5689E80ull +#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x568A000ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x568A080ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x568A100ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x568A180ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_10_SPECIAL_BASE 0x568AE80ull +#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x568B000ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x568B080ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x568B100ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x568B180ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_11_SPECIAL_BASE 0x568BE80ull +#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x568C000ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x568C080ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x568C100ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x568C180ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_12_SPECIAL_BASE 0x568CE80ull +#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x568D000ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x568D080ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x568D100ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x568D180ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_13_SPECIAL_BASE 0x568DE80ull +#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x568E000ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x568E080ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x568E100ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x568E180ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_14_SPECIAL_BASE 0x568EE80ull +#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM_DCCM0_BASE 0x5690000ull +#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM0_SECTION 0x8000 +#define mmNIC5_QM_ARC_AUX0_BASE 0x5698000ull +#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC5_QM_ARC_AUX0_SPECIAL_BASE 0x5698E80ull +#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM0_BASE 0x569A000ull +#define NIC5_QM0_MAX_OFFSET 0x1000 +#define NIC5_QM0_SECTION 0x9000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x569A900ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x569A908ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x569A910ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x569A918ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x569A920ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x569A928ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x569A930ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x569A938ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x569A940ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x569A948ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x569A950ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x569A958ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x569A960ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x569A968ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x569A970ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x569A978ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC5_QM0_AXUSER_SECURED_BASE 0x569AB00ull +#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC5_QM0_AXUSER_NONSECURED_BASE 0x569AB80ull +#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC5_QM0_DBG_HBW_BASE 0x569AC00ull +#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC5_QM0_DBG_LBW_BASE 0x569AC80ull +#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC5_QM0_CGM_BASE 0x569AD80ull +#define NIC5_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM0_CGM_SECTION 0x1000 +#define mmNIC5_QM0_SPECIAL_BASE 0x569AE80ull +#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC5_QPC0_BASE 0x569F000ull +#define NIC5_QPC0_MAX_OFFSET 0x1000 +#define NIC5_QPC0_SECTION 0x7200 +#define mmNIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x569F720ull +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x569F728ull +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x569F730ull +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x569F738ull +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x569F740ull +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x569F748ull +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x569F750ull +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x569F758ull +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x569F760ull +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x569F768ull +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x569F770ull +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x569F778ull +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x569F780ull +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x569F788ull +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x569F790ull +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x569F798ull +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x569F7A0ull +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x569F7A8ull +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x569F7B0ull +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x569F7B8ull +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x569F7C0ull +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x569F7C8ull +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x569F7D0ull +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x569F7D8ull +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x569F7E0ull +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x569F7E8ull +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x569F7F0ull +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x569F7F8ull +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x569F800ull +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x569F808ull +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x569F810ull +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x569F818ull +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC5_QPC0_AXUSER_CONG_QUE_BASE 0x569FB80ull +#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_RXWQE_BASE 0x569FBE0ull +#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x569FC40ull +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_DB_FIFO_BASE 0x569FCA0ull +#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x569FD00ull +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x569FD60ull +#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_QPC_RESP_BASE 0x569FDC0ull +#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_QPC_REQ_BASE 0x569FE20ull +#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC5_QPC0_SPECIAL_BASE 0x569FE80ull +#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x56A0000ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x56A0080ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x56A0100ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x56A0180ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_0_SPECIAL_BASE 0x56A0E80ull +#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x56A1000ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x56A1080ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x56A1100ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x56A1180ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_1_SPECIAL_BASE 0x56A1E80ull +#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x56A2000ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x56A2080ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x56A2100ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x56A2180ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_2_SPECIAL_BASE 0x56A2E80ull +#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x56A3000ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x56A3080ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x56A3100ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x56A3180ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_3_SPECIAL_BASE 0x56A3E80ull +#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x56A4000ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x56A4080ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x56A4100ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x56A4180ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_4_SPECIAL_BASE 0x56A4E80ull +#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x56A5000ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x56A5080ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x56A5100ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x56A5180ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_5_SPECIAL_BASE 0x56A5E80ull +#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x56A6000ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x56A6080ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x56A6100ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x56A6180ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_6_SPECIAL_BASE 0x56A6E80ull +#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x56A7000ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x56A7080ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x56A7100ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x56A7180ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_7_SPECIAL_BASE 0x56A7E80ull +#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x56A8000ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x56A8080ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x56A8100ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x56A8180ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_8_SPECIAL_BASE 0x56A8E80ull +#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x56A9000ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x56A9080ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x56A9100ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x56A9180ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_9_SPECIAL_BASE 0x56A9E80ull +#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x56AA000ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x56AA080ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x56AA100ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x56AA180ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_10_SPECIAL_BASE 0x56AAE80ull +#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x56AB000ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x56AB080ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x56AB100ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x56AB180ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_11_SPECIAL_BASE 0x56ABE80ull +#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x56AC000ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x56AC080ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x56AC100ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x56AC180ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_12_SPECIAL_BASE 0x56ACE80ull +#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x56AD000ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x56AD080ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x56AD100ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x56AD180ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_13_SPECIAL_BASE 0x56ADE80ull +#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x56AE000ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x56AE080ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x56AE100ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x56AE180ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_14_SPECIAL_BASE 0x56AEE80ull +#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM_DCCM1_BASE 0x56B0000ull +#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM1_SECTION 0x8000 +#define mmNIC5_QM_ARC_AUX1_BASE 0x56B8000ull +#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC5_QM_ARC_AUX1_SPECIAL_BASE 0x56B8E80ull +#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM1_BASE 0x56BA000ull +#define NIC5_QM1_MAX_OFFSET 0x1000 +#define NIC5_QM1_SECTION 0x9000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x56BA900ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x56BA908ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x56BA910ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x56BA918ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x56BA920ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x56BA928ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x56BA930ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x56BA938ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x56BA940ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x56BA948ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x56BA950ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x56BA958ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x56BA960ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x56BA968ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x56BA970ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x56BA978ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC5_QM1_AXUSER_SECURED_BASE 0x56BAB00ull +#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC5_QM1_AXUSER_NONSECURED_BASE 0x56BAB80ull +#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC5_QM1_DBG_HBW_BASE 0x56BAC00ull +#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC5_QM1_DBG_LBW_BASE 0x56BAC80ull +#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC5_QM1_CGM_BASE 0x56BAD80ull +#define NIC5_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM1_CGM_SECTION 0x1000 +#define mmNIC5_QM1_SPECIAL_BASE 0x56BAE80ull +#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC5_QPC1_BASE 0x56BF000ull +#define NIC5_QPC1_MAX_OFFSET 0x1000 +#define NIC5_QPC1_SECTION 0x7200 +#define mmNIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x56BF720ull +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x56BF728ull +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x56BF730ull +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x56BF738ull +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x56BF740ull +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x56BF748ull +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x56BF750ull +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x56BF758ull +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x56BF760ull +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x56BF768ull +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x56BF770ull +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x56BF778ull +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x56BF780ull +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x56BF788ull +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x56BF790ull +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x56BF798ull +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x56BF7A0ull +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x56BF7A8ull +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x56BF7B0ull +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x56BF7B8ull +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x56BF7C0ull +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x56BF7C8ull +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x56BF7D0ull +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x56BF7D8ull +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x56BF7E0ull +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x56BF7E8ull +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x56BF7F0ull +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x56BF7F8ull +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x56BF800ull +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x56BF808ull +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x56BF810ull +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x56BF818ull +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC5_QPC1_AXUSER_CONG_QUE_BASE 0x56BFB80ull +#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_RXWQE_BASE 0x56BFBE0ull +#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x56BFC40ull +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_DB_FIFO_BASE 0x56BFCA0ull +#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x56BFD00ull +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x56BFD60ull +#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_QPC_RESP_BASE 0x56BFDC0ull +#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_QPC_REQ_BASE 0x56BFE20ull +#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC5_QPC1_SPECIAL_BASE 0x56BFE80ull +#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC5_TMR_BASE 0x56C8000ull +#define NIC5_TMR_MAX_OFFSET 0x1000 +#define NIC5_TMR_SECTION 0xD600 +#define mmNIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x56C8D60ull +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC5_TMR_AXUSER_TMR_FIFO_BASE 0x56C8DC0ull +#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC5_TMR_AXUSER_TMR_FSM_BASE 0x56C8E20ull +#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC5_TMR_SPECIAL_BASE 0x56C8E80ull +#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXB_CORE_BASE 0x56C9000ull +#define NIC5_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC5_RXB_CORE_SECTION 0x6100 +#define mmNIC5_RXB_CORE_SCT_AWUSER_BASE 0x56C9610ull +#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC5_RXB_CORE_SPECIAL_BASE 0x56C9E80ull +#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE0_BASE 0x56CA000ull +#define NIC5_RXE0_MAX_OFFSET 0x1000 +#define NIC5_RXE0_SECTION 0x9000 +#define mmNIC5_RXE0_WQE_ARUSER_BASE 0x56CA900ull +#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC5_RXE0_SPECIAL_BASE 0x56CAE80ull +#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE1_BASE 0x56CB000ull +#define NIC5_RXE1_MAX_OFFSET 0x1000 +#define NIC5_RXE1_SECTION 0x9000 +#define mmNIC5_RXE1_WQE_ARUSER_BASE 0x56CB900ull +#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC5_RXE1_SPECIAL_BASE 0x56CBE80ull +#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x56CC000ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x56CC050ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x56CC0A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x56CC0F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x56CC140ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x56CC190ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x56CC1E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x56CC230ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x56CC280ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x56CC2D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x56CC320ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x56CC370ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x56CC3C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x56CC410ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x56CC460ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x56CC4B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x56CC500ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x56CC550ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x56CC5A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x56CC5F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x56CC640ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x56CC690ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x56CC6E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x56CC730ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x56CC780ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x56CC7D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x56CC820ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x56CC870ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x56CC8C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x56CC910ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x56CC960ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x56CC9B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC5_RXE0_AXUSER_SPECIAL_BASE 0x56CCE80ull +#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x56CD000ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x56CD050ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x56CD0A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x56CD0F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x56CD140ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x56CD190ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x56CD1E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x56CD230ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x56CD280ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x56CD2D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x56CD320ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x56CD370ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x56CD3C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x56CD410ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x56CD460ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x56CD4B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x56CD500ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x56CD550ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x56CD5A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x56CD5F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x56CD640ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x56CD690ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x56CD6E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x56CD730ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x56CD780ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x56CD7D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x56CD820ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x56CD870ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x56CD8C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x56CD910ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x56CD960ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x56CD9B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC5_RXE1_AXUSER_SPECIAL_BASE 0x56CDE80ull +#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC5_TXS0_BASE 0x56D0000ull +#define NIC5_TXS0_MAX_OFFSET 0x1000 +#define NIC5_TXS0_SECTION 0xE800 +#define mmNIC5_TXS0_SPECIAL_BASE 0x56D0E80ull +#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXS1_BASE 0x56D1000ull +#define NIC5_TXS1_MAX_OFFSET 0x1000 +#define NIC5_TXS1_SECTION 0xE800 +#define mmNIC5_TXS1_SPECIAL_BASE 0x56D1E80ull +#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXE0_BASE 0x56D2000ull +#define NIC5_TXE0_MAX_OFFSET 0x1000 +#define NIC5_TXE0_SECTION 0xE800 +#define mmNIC5_TXE0_SPECIAL_BASE 0x56D2E80ull +#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXE1_BASE 0x56D3000ull +#define NIC5_TXE1_MAX_OFFSET 0x1000 +#define NIC5_TXE1_SECTION 0xE800 +#define mmNIC5_TXE1_SPECIAL_BASE 0x56D3E80ull +#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXB_BASE 0x56D4000ull +#define NIC5_TXB_MAX_OFFSET 0x1000 +#define NIC5_TXB_SECTION 0xE800 +#define mmNIC5_TXB_SPECIAL_BASE 0x56D4E80ull +#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x56D5000ull +#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x56D5200ull +#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x56D5400ull +#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x56D5600ull +#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_E2E_CRDT_BASE 0x56D5800ull +#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC5_MSTR_IF_AXUSER_BASE 0x56D5A80ull +#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC5_MSTR_IF_DBG_HBW_BASE 0x56D5B00ull +#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC5_MSTR_IF_DBG_LBW_BASE 0x56D5B80ull +#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC5_MSTR_IF_CORE_HBW_BASE 0x56D5C00ull +#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC5_MSTR_IF_CORE_LBW_BASE 0x56D5D80ull +#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC5_MSTR_IF_SPECIAL_BASE 0x56D5E80ull +#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC5_TX_AXUSER_BASE 0x56D6000ull +#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_TX_AXUSER_SECTION 0x2000 +#define mmNIC5_SERDES0_BASE 0x56D8000ull +#define NIC5_SERDES0_MAX_OFFSET 0x3E40 +#define NIC5_SERDES0_SECTION 0x4000 +#define mmNIC5_SERDES1_BASE 0x56DC000ull +#define NIC5_SERDES1_MAX_OFFSET 0x3E40 +#define NIC5_SERDES1_SECTION 0x4000 +#define mmNIC5_PHY_BASE 0x56E0000ull +#define NIC5_PHY_MAX_OFFSET 0x1000 +#define NIC5_PHY_SECTION 0xE800 +#define mmNIC5_PHY_SPECIAL_BASE 0x56E0E80ull +#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT5_MAC_AUX_BASE 0x56E8000ull +#define PRT5_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT5_MAC_AUX_SECTION 0xE800 +#define mmPRT5_MAC_AUX_SPECIAL_BASE 0x56E8E80ull +#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT5_MAC_CORE_BASE 0x56E9000ull +#define PRT5_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT5_MAC_CORE_SECTION 0xE800 +#define mmPRT5_MAC_CORE_SPECIAL_BASE 0x56E9E80ull +#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC5_MAC_RS_FEC_BASE 0x56EA000ull +#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC5_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC5_MAC_GLOB_STAT_CONTROL_REG_BASE 0x56EB000ull +#define NIC5_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC5_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC5_MAC_GLOB_STAT_RX0_BASE 0x56EB100ull +#define NIC5_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX1_BASE 0x56EB18Cull +#define NIC5_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX2_BASE 0x56EB218ull +#define NIC5_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX3_BASE 0x56EB2A4ull +#define NIC5_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_TX0_BASE 0x56EB330ull +#define NIC5_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX1_BASE 0x56EB398ull +#define NIC5_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX2_BASE 0x56EB400ull +#define NIC5_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX3_BASE 0x56EB468ull +#define NIC5_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC5_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x56EB800ull +#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC5_MAC_CH0_MAC_PCS_BASE 0x56EC000ull +#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH0_MAC_128_BASE 0x56EC400ull +#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH0_MAC_AN_BASE 0x56EC800ull +#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH1_MAC_PCS_BASE 0x56ED000ull +#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH1_MAC_128_BASE 0x56ED400ull +#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH1_MAC_AN_BASE 0x56ED800ull +#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH2_MAC_PCS_BASE 0x56EE000ull +#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH2_MAC_128_BASE 0x56EE400ull +#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH2_MAC_AN_BASE 0x56EE800ull +#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH3_MAC_PCS_BASE 0x56EF000ull +#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH3_MAC_128_BASE 0x56EF400ull +#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH3_MAC_AN_BASE 0x56EF800ull +#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5700000ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5700080ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5700100ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5700180ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_0_SPECIAL_BASE 0x5700E80ull +#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5701000ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5701080ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5701100ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5701180ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_1_SPECIAL_BASE 0x5701E80ull +#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5702000ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5702080ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5702100ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5702180ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_2_SPECIAL_BASE 0x5702E80ull +#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5703000ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5703080ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5703100ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5703180ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_3_SPECIAL_BASE 0x5703E80ull +#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5704000ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5704080ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5704100ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5704180ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_4_SPECIAL_BASE 0x5704E80ull +#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5705000ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5705080ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5705100ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5705180ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_5_SPECIAL_BASE 0x5705E80ull +#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5706000ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5706080ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5706100ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5706180ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_6_SPECIAL_BASE 0x5706E80ull +#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5707000ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5707080ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5707100ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5707180ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_7_SPECIAL_BASE 0x5707E80ull +#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5708000ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5708080ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5708100ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5708180ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_8_SPECIAL_BASE 0x5708E80ull +#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5709000ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5709080ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5709100ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5709180ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_9_SPECIAL_BASE 0x5709E80ull +#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x570A000ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x570A080ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x570A100ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x570A180ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_10_SPECIAL_BASE 0x570AE80ull +#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x570B000ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x570B080ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x570B100ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x570B180ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_11_SPECIAL_BASE 0x570BE80ull +#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x570C000ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x570C080ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x570C100ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x570C180ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_12_SPECIAL_BASE 0x570CE80ull +#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x570D000ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x570D080ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x570D100ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x570D180ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_13_SPECIAL_BASE 0x570DE80ull +#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x570E000ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x570E080ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x570E100ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x570E180ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_14_SPECIAL_BASE 0x570EE80ull +#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM_DCCM0_BASE 0x5710000ull +#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM0_SECTION 0x8000 +#define mmNIC6_QM_ARC_AUX0_BASE 0x5718000ull +#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC6_QM_ARC_AUX0_SPECIAL_BASE 0x5718E80ull +#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM0_BASE 0x571A000ull +#define NIC6_QM0_MAX_OFFSET 0x1000 +#define NIC6_QM0_SECTION 0x9000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x571A900ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x571A908ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x571A910ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x571A918ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x571A920ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x571A928ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x571A930ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x571A938ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x571A940ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x571A948ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x571A950ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x571A958ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x571A960ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x571A968ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x571A970ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x571A978ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC6_QM0_AXUSER_SECURED_BASE 0x571AB00ull +#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC6_QM0_AXUSER_NONSECURED_BASE 0x571AB80ull +#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC6_QM0_DBG_HBW_BASE 0x571AC00ull +#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC6_QM0_DBG_LBW_BASE 0x571AC80ull +#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC6_QM0_CGM_BASE 0x571AD80ull +#define NIC6_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM0_CGM_SECTION 0x1000 +#define mmNIC6_QM0_SPECIAL_BASE 0x571AE80ull +#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC6_QPC0_BASE 0x571F000ull +#define NIC6_QPC0_MAX_OFFSET 0x1000 +#define NIC6_QPC0_SECTION 0x7200 +#define mmNIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x571F720ull +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x571F728ull +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x571F730ull +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x571F738ull +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x571F740ull +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x571F748ull +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x571F750ull +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x571F758ull +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x571F760ull +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x571F768ull +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x571F770ull +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x571F778ull +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x571F780ull +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x571F788ull +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x571F790ull +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x571F798ull +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x571F7A0ull +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x571F7A8ull +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x571F7B0ull +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x571F7B8ull +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x571F7C0ull +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x571F7C8ull +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x571F7D0ull +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x571F7D8ull +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x571F7E0ull +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x571F7E8ull +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x571F7F0ull +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x571F7F8ull +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x571F800ull +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x571F808ull +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x571F810ull +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x571F818ull +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC6_QPC0_AXUSER_CONG_QUE_BASE 0x571FB80ull +#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_RXWQE_BASE 0x571FBE0ull +#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x571FC40ull +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_DB_FIFO_BASE 0x571FCA0ull +#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x571FD00ull +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x571FD60ull +#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_QPC_RESP_BASE 0x571FDC0ull +#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_QPC_REQ_BASE 0x571FE20ull +#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC6_QPC0_SPECIAL_BASE 0x571FE80ull +#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5720000ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5720080ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5720100ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5720180ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_0_SPECIAL_BASE 0x5720E80ull +#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5721000ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5721080ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5721100ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5721180ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_1_SPECIAL_BASE 0x5721E80ull +#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5722000ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5722080ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5722100ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5722180ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_2_SPECIAL_BASE 0x5722E80ull +#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5723000ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5723080ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5723100ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5723180ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_3_SPECIAL_BASE 0x5723E80ull +#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5724000ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5724080ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5724100ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5724180ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_4_SPECIAL_BASE 0x5724E80ull +#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5725000ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5725080ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5725100ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5725180ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_5_SPECIAL_BASE 0x5725E80ull +#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5726000ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5726080ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5726100ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5726180ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_6_SPECIAL_BASE 0x5726E80ull +#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5727000ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5727080ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5727100ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5727180ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_7_SPECIAL_BASE 0x5727E80ull +#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5728000ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5728080ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5728100ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5728180ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_8_SPECIAL_BASE 0x5728E80ull +#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5729000ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5729080ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5729100ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5729180ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_9_SPECIAL_BASE 0x5729E80ull +#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x572A000ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x572A080ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x572A100ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x572A180ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_10_SPECIAL_BASE 0x572AE80ull +#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x572B000ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x572B080ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x572B100ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x572B180ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_11_SPECIAL_BASE 0x572BE80ull +#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x572C000ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x572C080ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x572C100ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x572C180ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_12_SPECIAL_BASE 0x572CE80ull +#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x572D000ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x572D080ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x572D100ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x572D180ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_13_SPECIAL_BASE 0x572DE80ull +#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x572E000ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x572E080ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x572E100ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x572E180ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_14_SPECIAL_BASE 0x572EE80ull +#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM_DCCM1_BASE 0x5730000ull +#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM1_SECTION 0x8000 +#define mmNIC6_QM_ARC_AUX1_BASE 0x5738000ull +#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC6_QM_ARC_AUX1_SPECIAL_BASE 0x5738E80ull +#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM1_BASE 0x573A000ull +#define NIC6_QM1_MAX_OFFSET 0x1000 +#define NIC6_QM1_SECTION 0x9000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x573A900ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x573A908ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x573A910ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x573A918ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x573A920ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x573A928ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x573A930ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x573A938ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x573A940ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x573A948ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x573A950ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x573A958ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x573A960ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x573A968ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x573A970ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x573A978ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC6_QM1_AXUSER_SECURED_BASE 0x573AB00ull +#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC6_QM1_AXUSER_NONSECURED_BASE 0x573AB80ull +#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC6_QM1_DBG_HBW_BASE 0x573AC00ull +#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC6_QM1_DBG_LBW_BASE 0x573AC80ull +#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC6_QM1_CGM_BASE 0x573AD80ull +#define NIC6_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM1_CGM_SECTION 0x1000 +#define mmNIC6_QM1_SPECIAL_BASE 0x573AE80ull +#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC6_QPC1_BASE 0x573F000ull +#define NIC6_QPC1_MAX_OFFSET 0x1000 +#define NIC6_QPC1_SECTION 0x7200 +#define mmNIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x573F720ull +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x573F728ull +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x573F730ull +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x573F738ull +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x573F740ull +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x573F748ull +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x573F750ull +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x573F758ull +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x573F760ull +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x573F768ull +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x573F770ull +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x573F778ull +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x573F780ull +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x573F788ull +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x573F790ull +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x573F798ull +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x573F7A0ull +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x573F7A8ull +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x573F7B0ull +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x573F7B8ull +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x573F7C0ull +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x573F7C8ull +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x573F7D0ull +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x573F7D8ull +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x573F7E0ull +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x573F7E8ull +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x573F7F0ull +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x573F7F8ull +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x573F800ull +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x573F808ull +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x573F810ull +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x573F818ull +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC6_QPC1_AXUSER_CONG_QUE_BASE 0x573FB80ull +#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_RXWQE_BASE 0x573FBE0ull +#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x573FC40ull +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_DB_FIFO_BASE 0x573FCA0ull +#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x573FD00ull +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x573FD60ull +#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_QPC_RESP_BASE 0x573FDC0ull +#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_QPC_REQ_BASE 0x573FE20ull +#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC6_QPC1_SPECIAL_BASE 0x573FE80ull +#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC6_TMR_BASE 0x5748000ull +#define NIC6_TMR_MAX_OFFSET 0x1000 +#define NIC6_TMR_SECTION 0xD600 +#define mmNIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5748D60ull +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC6_TMR_AXUSER_TMR_FIFO_BASE 0x5748DC0ull +#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC6_TMR_AXUSER_TMR_FSM_BASE 0x5748E20ull +#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC6_TMR_SPECIAL_BASE 0x5748E80ull +#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXB_CORE_BASE 0x5749000ull +#define NIC6_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC6_RXB_CORE_SECTION 0x6100 +#define mmNIC6_RXB_CORE_SCT_AWUSER_BASE 0x5749610ull +#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC6_RXB_CORE_SPECIAL_BASE 0x5749E80ull +#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE0_BASE 0x574A000ull +#define NIC6_RXE0_MAX_OFFSET 0x1000 +#define NIC6_RXE0_SECTION 0x9000 +#define mmNIC6_RXE0_WQE_ARUSER_BASE 0x574A900ull +#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC6_RXE0_SPECIAL_BASE 0x574AE80ull +#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE1_BASE 0x574B000ull +#define NIC6_RXE1_MAX_OFFSET 0x1000 +#define NIC6_RXE1_SECTION 0x9000 +#define mmNIC6_RXE1_WQE_ARUSER_BASE 0x574B900ull +#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC6_RXE1_SPECIAL_BASE 0x574BE80ull +#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x574C000ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x574C050ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x574C0A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x574C0F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x574C140ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x574C190ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x574C1E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x574C230ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x574C280ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x574C2D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x574C320ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x574C370ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x574C3C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x574C410ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x574C460ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x574C4B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x574C500ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x574C550ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x574C5A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x574C5F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x574C640ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x574C690ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x574C6E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x574C730ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x574C780ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x574C7D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x574C820ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x574C870ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x574C8C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x574C910ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x574C960ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x574C9B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC6_RXE0_AXUSER_SPECIAL_BASE 0x574CE80ull +#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x574D000ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x574D050ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x574D0A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x574D0F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x574D140ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x574D190ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x574D1E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x574D230ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x574D280ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x574D2D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x574D320ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x574D370ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x574D3C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x574D410ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x574D460ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x574D4B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x574D500ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x574D550ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x574D5A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x574D5F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x574D640ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x574D690ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x574D6E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x574D730ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x574D780ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x574D7D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x574D820ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x574D870ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x574D8C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x574D910ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x574D960ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x574D9B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC6_RXE1_AXUSER_SPECIAL_BASE 0x574DE80ull +#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC6_TXS0_BASE 0x5750000ull +#define NIC6_TXS0_MAX_OFFSET 0x1000 +#define NIC6_TXS0_SECTION 0xE800 +#define mmNIC6_TXS0_SPECIAL_BASE 0x5750E80ull +#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXS1_BASE 0x5751000ull +#define NIC6_TXS1_MAX_OFFSET 0x1000 +#define NIC6_TXS1_SECTION 0xE800 +#define mmNIC6_TXS1_SPECIAL_BASE 0x5751E80ull +#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXE0_BASE 0x5752000ull +#define NIC6_TXE0_MAX_OFFSET 0x1000 +#define NIC6_TXE0_SECTION 0xE800 +#define mmNIC6_TXE0_SPECIAL_BASE 0x5752E80ull +#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXE1_BASE 0x5753000ull +#define NIC6_TXE1_MAX_OFFSET 0x1000 +#define NIC6_TXE1_SECTION 0xE800 +#define mmNIC6_TXE1_SPECIAL_BASE 0x5753E80ull +#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXB_BASE 0x5754000ull +#define NIC6_TXB_MAX_OFFSET 0x1000 +#define NIC6_TXB_SECTION 0xE800 +#define mmNIC6_TXB_SPECIAL_BASE 0x5754E80ull +#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x5755000ull +#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x5755200ull +#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x5755400ull +#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x5755600ull +#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_E2E_CRDT_BASE 0x5755800ull +#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC6_MSTR_IF_AXUSER_BASE 0x5755A80ull +#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC6_MSTR_IF_DBG_HBW_BASE 0x5755B00ull +#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC6_MSTR_IF_DBG_LBW_BASE 0x5755B80ull +#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC6_MSTR_IF_CORE_HBW_BASE 0x5755C00ull +#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC6_MSTR_IF_CORE_LBW_BASE 0x5755D80ull +#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC6_MSTR_IF_SPECIAL_BASE 0x5755E80ull +#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC6_TX_AXUSER_BASE 0x5756000ull +#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_TX_AXUSER_SECTION 0x2000 +#define mmNIC6_SERDES0_BASE 0x5758000ull +#define NIC6_SERDES0_MAX_OFFSET 0x3E40 +#define NIC6_SERDES0_SECTION 0x4000 +#define mmNIC6_SERDES1_BASE 0x575C000ull +#define NIC6_SERDES1_MAX_OFFSET 0x3E40 +#define NIC6_SERDES1_SECTION 0x4000 +#define mmNIC6_PHY_BASE 0x5760000ull +#define NIC6_PHY_MAX_OFFSET 0x1000 +#define NIC6_PHY_SECTION 0xE800 +#define mmNIC6_PHY_SPECIAL_BASE 0x5760E80ull +#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT6_MAC_AUX_BASE 0x5768000ull +#define PRT6_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT6_MAC_AUX_SECTION 0xE800 +#define mmPRT6_MAC_AUX_SPECIAL_BASE 0x5768E80ull +#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT6_MAC_CORE_BASE 0x5769000ull +#define PRT6_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT6_MAC_CORE_SECTION 0xE800 +#define mmPRT6_MAC_CORE_SPECIAL_BASE 0x5769E80ull +#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC6_MAC_RS_FEC_BASE 0x576A000ull +#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC6_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC6_MAC_GLOB_STAT_CONTROL_REG_BASE 0x576B000ull +#define NIC6_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC6_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC6_MAC_GLOB_STAT_RX0_BASE 0x576B100ull +#define NIC6_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX1_BASE 0x576B18Cull +#define NIC6_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX2_BASE 0x576B218ull +#define NIC6_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX3_BASE 0x576B2A4ull +#define NIC6_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_TX0_BASE 0x576B330ull +#define NIC6_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX1_BASE 0x576B398ull +#define NIC6_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX2_BASE 0x576B400ull +#define NIC6_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX3_BASE 0x576B468ull +#define NIC6_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC6_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x576B800ull +#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC6_MAC_CH0_MAC_PCS_BASE 0x576C000ull +#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH0_MAC_128_BASE 0x576C400ull +#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH0_MAC_AN_BASE 0x576C800ull +#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH1_MAC_PCS_BASE 0x576D000ull +#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH1_MAC_128_BASE 0x576D400ull +#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH1_MAC_AN_BASE 0x576D800ull +#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH2_MAC_PCS_BASE 0x576E000ull +#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH2_MAC_128_BASE 0x576E400ull +#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH2_MAC_AN_BASE 0x576E800ull +#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH3_MAC_PCS_BASE 0x576F000ull +#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH3_MAC_128_BASE 0x576F400ull +#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH3_MAC_AN_BASE 0x576F800ull +#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5780000ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5780080ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5780100ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5780180ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_0_SPECIAL_BASE 0x5780E80ull +#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5781000ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5781080ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5781100ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5781180ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_1_SPECIAL_BASE 0x5781E80ull +#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5782000ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5782080ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5782100ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5782180ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_2_SPECIAL_BASE 0x5782E80ull +#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5783000ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5783080ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5783100ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5783180ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_3_SPECIAL_BASE 0x5783E80ull +#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5784000ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5784080ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5784100ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5784180ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_4_SPECIAL_BASE 0x5784E80ull +#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5785000ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5785080ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5785100ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5785180ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_5_SPECIAL_BASE 0x5785E80ull +#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5786000ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5786080ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5786100ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5786180ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_6_SPECIAL_BASE 0x5786E80ull +#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5787000ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5787080ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5787100ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5787180ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_7_SPECIAL_BASE 0x5787E80ull +#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5788000ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5788080ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5788100ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5788180ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_8_SPECIAL_BASE 0x5788E80ull +#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5789000ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5789080ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5789100ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5789180ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_9_SPECIAL_BASE 0x5789E80ull +#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x578A000ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x578A080ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x578A100ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x578A180ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_10_SPECIAL_BASE 0x578AE80ull +#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x578B000ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x578B080ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x578B100ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x578B180ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_11_SPECIAL_BASE 0x578BE80ull +#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x578C000ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x578C080ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x578C100ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x578C180ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_12_SPECIAL_BASE 0x578CE80ull +#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x578D000ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x578D080ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x578D100ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x578D180ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_13_SPECIAL_BASE 0x578DE80ull +#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x578E000ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x578E080ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x578E100ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x578E180ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_14_SPECIAL_BASE 0x578EE80ull +#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM_DCCM0_BASE 0x5790000ull +#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM0_SECTION 0x8000 +#define mmNIC7_QM_ARC_AUX0_BASE 0x5798000ull +#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC7_QM_ARC_AUX0_SPECIAL_BASE 0x5798E80ull +#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM0_BASE 0x579A000ull +#define NIC7_QM0_MAX_OFFSET 0x1000 +#define NIC7_QM0_SECTION 0x9000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x579A900ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x579A908ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x579A910ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x579A918ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x579A920ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x579A928ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x579A930ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x579A938ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x579A940ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x579A948ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x579A950ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x579A958ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x579A960ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x579A968ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x579A970ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x579A978ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC7_QM0_AXUSER_SECURED_BASE 0x579AB00ull +#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC7_QM0_AXUSER_NONSECURED_BASE 0x579AB80ull +#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC7_QM0_DBG_HBW_BASE 0x579AC00ull +#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC7_QM0_DBG_LBW_BASE 0x579AC80ull +#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC7_QM0_CGM_BASE 0x579AD80ull +#define NIC7_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM0_CGM_SECTION 0x1000 +#define mmNIC7_QM0_SPECIAL_BASE 0x579AE80ull +#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC7_QPC0_BASE 0x579F000ull +#define NIC7_QPC0_MAX_OFFSET 0x1000 +#define NIC7_QPC0_SECTION 0x7200 +#define mmNIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x579F720ull +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x579F728ull +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x579F730ull +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x579F738ull +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x579F740ull +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x579F748ull +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x579F750ull +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x579F758ull +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x579F760ull +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x579F768ull +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x579F770ull +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x579F778ull +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x579F780ull +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x579F788ull +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x579F790ull +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x579F798ull +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x579F7A0ull +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x579F7A8ull +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x579F7B0ull +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x579F7B8ull +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x579F7C0ull +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x579F7C8ull +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x579F7D0ull +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x579F7D8ull +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x579F7E0ull +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x579F7E8ull +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x579F7F0ull +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x579F7F8ull +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x579F800ull +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x579F808ull +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x579F810ull +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x579F818ull +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC7_QPC0_AXUSER_CONG_QUE_BASE 0x579FB80ull +#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_RXWQE_BASE 0x579FBE0ull +#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x579FC40ull +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_DB_FIFO_BASE 0x579FCA0ull +#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x579FD00ull +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x579FD60ull +#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_QPC_RESP_BASE 0x579FDC0ull +#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_QPC_REQ_BASE 0x579FE20ull +#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC7_QPC0_SPECIAL_BASE 0x579FE80ull +#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x57A0000ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x57A0080ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x57A0100ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x57A0180ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_0_SPECIAL_BASE 0x57A0E80ull +#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x57A1000ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x57A1080ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x57A1100ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x57A1180ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_1_SPECIAL_BASE 0x57A1E80ull +#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x57A2000ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x57A2080ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x57A2100ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x57A2180ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_2_SPECIAL_BASE 0x57A2E80ull +#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x57A3000ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x57A3080ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x57A3100ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x57A3180ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_3_SPECIAL_BASE 0x57A3E80ull +#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x57A4000ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x57A4080ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x57A4100ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x57A4180ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_4_SPECIAL_BASE 0x57A4E80ull +#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x57A5000ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x57A5080ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x57A5100ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x57A5180ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_5_SPECIAL_BASE 0x57A5E80ull +#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x57A6000ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x57A6080ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x57A6100ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x57A6180ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_6_SPECIAL_BASE 0x57A6E80ull +#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x57A7000ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x57A7080ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x57A7100ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x57A7180ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_7_SPECIAL_BASE 0x57A7E80ull +#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x57A8000ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x57A8080ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x57A8100ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x57A8180ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_8_SPECIAL_BASE 0x57A8E80ull +#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x57A9000ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x57A9080ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x57A9100ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x57A9180ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_9_SPECIAL_BASE 0x57A9E80ull +#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x57AA000ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x57AA080ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x57AA100ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x57AA180ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_10_SPECIAL_BASE 0x57AAE80ull +#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x57AB000ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x57AB080ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x57AB100ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x57AB180ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_11_SPECIAL_BASE 0x57ABE80ull +#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x57AC000ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x57AC080ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x57AC100ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x57AC180ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_12_SPECIAL_BASE 0x57ACE80ull +#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x57AD000ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x57AD080ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x57AD100ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x57AD180ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_13_SPECIAL_BASE 0x57ADE80ull +#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x57AE000ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x57AE080ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x57AE100ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x57AE180ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_14_SPECIAL_BASE 0x57AEE80ull +#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM_DCCM1_BASE 0x57B0000ull +#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM1_SECTION 0x8000 +#define mmNIC7_QM_ARC_AUX1_BASE 0x57B8000ull +#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC7_QM_ARC_AUX1_SPECIAL_BASE 0x57B8E80ull +#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM1_BASE 0x57BA000ull +#define NIC7_QM1_MAX_OFFSET 0x1000 +#define NIC7_QM1_SECTION 0x9000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x57BA900ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x57BA908ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x57BA910ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x57BA918ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x57BA920ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x57BA928ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x57BA930ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x57BA938ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x57BA940ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x57BA948ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x57BA950ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x57BA958ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x57BA960ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x57BA968ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x57BA970ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x57BA978ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC7_QM1_AXUSER_SECURED_BASE 0x57BAB00ull +#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC7_QM1_AXUSER_NONSECURED_BASE 0x57BAB80ull +#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC7_QM1_DBG_HBW_BASE 0x57BAC00ull +#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC7_QM1_DBG_LBW_BASE 0x57BAC80ull +#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC7_QM1_CGM_BASE 0x57BAD80ull +#define NIC7_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM1_CGM_SECTION 0x1000 +#define mmNIC7_QM1_SPECIAL_BASE 0x57BAE80ull +#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC7_QPC1_BASE 0x57BF000ull +#define NIC7_QPC1_MAX_OFFSET 0x1000 +#define NIC7_QPC1_SECTION 0x7200 +#define mmNIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x57BF720ull +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x57BF728ull +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x57BF730ull +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x57BF738ull +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x57BF740ull +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x57BF748ull +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x57BF750ull +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x57BF758ull +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x57BF760ull +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x57BF768ull +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x57BF770ull +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x57BF778ull +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x57BF780ull +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x57BF788ull +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x57BF790ull +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x57BF798ull +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x57BF7A0ull +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x57BF7A8ull +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x57BF7B0ull +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x57BF7B8ull +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x57BF7C0ull +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x57BF7C8ull +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x57BF7D0ull +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x57BF7D8ull +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x57BF7E0ull +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x57BF7E8ull +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x57BF7F0ull +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x57BF7F8ull +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x57BF800ull +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x57BF808ull +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x57BF810ull +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x57BF818ull +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC7_QPC1_AXUSER_CONG_QUE_BASE 0x57BFB80ull +#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_RXWQE_BASE 0x57BFBE0ull +#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x57BFC40ull +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_DB_FIFO_BASE 0x57BFCA0ull +#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x57BFD00ull +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x57BFD60ull +#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_QPC_RESP_BASE 0x57BFDC0ull +#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_QPC_REQ_BASE 0x57BFE20ull +#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC7_QPC1_SPECIAL_BASE 0x57BFE80ull +#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC7_TMR_BASE 0x57C8000ull +#define NIC7_TMR_MAX_OFFSET 0x1000 +#define NIC7_TMR_SECTION 0xD600 +#define mmNIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x57C8D60ull +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC7_TMR_AXUSER_TMR_FIFO_BASE 0x57C8DC0ull +#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC7_TMR_AXUSER_TMR_FSM_BASE 0x57C8E20ull +#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC7_TMR_SPECIAL_BASE 0x57C8E80ull +#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXB_CORE_BASE 0x57C9000ull +#define NIC7_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC7_RXB_CORE_SECTION 0x6100 +#define mmNIC7_RXB_CORE_SCT_AWUSER_BASE 0x57C9610ull +#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC7_RXB_CORE_SPECIAL_BASE 0x57C9E80ull +#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE0_BASE 0x57CA000ull +#define NIC7_RXE0_MAX_OFFSET 0x1000 +#define NIC7_RXE0_SECTION 0x9000 +#define mmNIC7_RXE0_WQE_ARUSER_BASE 0x57CA900ull +#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC7_RXE0_SPECIAL_BASE 0x57CAE80ull +#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE1_BASE 0x57CB000ull +#define NIC7_RXE1_MAX_OFFSET 0x1000 +#define NIC7_RXE1_SECTION 0x9000 +#define mmNIC7_RXE1_WQE_ARUSER_BASE 0x57CB900ull +#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC7_RXE1_SPECIAL_BASE 0x57CBE80ull +#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x57CC000ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x57CC050ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x57CC0A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x57CC0F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x57CC140ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x57CC190ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x57CC1E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x57CC230ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x57CC280ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x57CC2D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x57CC320ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x57CC370ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x57CC3C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x57CC410ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x57CC460ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x57CC4B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x57CC500ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x57CC550ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x57CC5A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x57CC5F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x57CC640ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x57CC690ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x57CC6E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x57CC730ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x57CC780ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x57CC7D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x57CC820ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x57CC870ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x57CC8C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x57CC910ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x57CC960ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x57CC9B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC7_RXE0_AXUSER_SPECIAL_BASE 0x57CCE80ull +#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x57CD000ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x57CD050ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x57CD0A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x57CD0F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x57CD140ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x57CD190ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x57CD1E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x57CD230ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x57CD280ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x57CD2D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x57CD320ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x57CD370ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x57CD3C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x57CD410ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x57CD460ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x57CD4B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x57CD500ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x57CD550ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x57CD5A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x57CD5F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x57CD640ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x57CD690ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x57CD6E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x57CD730ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x57CD780ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x57CD7D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x57CD820ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x57CD870ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x57CD8C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x57CD910ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x57CD960ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x57CD9B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC7_RXE1_AXUSER_SPECIAL_BASE 0x57CDE80ull +#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC7_TXS0_BASE 0x57D0000ull +#define NIC7_TXS0_MAX_OFFSET 0x1000 +#define NIC7_TXS0_SECTION 0xE800 +#define mmNIC7_TXS0_SPECIAL_BASE 0x57D0E80ull +#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXS1_BASE 0x57D1000ull +#define NIC7_TXS1_MAX_OFFSET 0x1000 +#define NIC7_TXS1_SECTION 0xE800 +#define mmNIC7_TXS1_SPECIAL_BASE 0x57D1E80ull +#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXE0_BASE 0x57D2000ull +#define NIC7_TXE0_MAX_OFFSET 0x1000 +#define NIC7_TXE0_SECTION 0xE800 +#define mmNIC7_TXE0_SPECIAL_BASE 0x57D2E80ull +#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXE1_BASE 0x57D3000ull +#define NIC7_TXE1_MAX_OFFSET 0x1000 +#define NIC7_TXE1_SECTION 0xE800 +#define mmNIC7_TXE1_SPECIAL_BASE 0x57D3E80ull +#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXB_BASE 0x57D4000ull +#define NIC7_TXB_MAX_OFFSET 0x1000 +#define NIC7_TXB_SECTION 0xE800 +#define mmNIC7_TXB_SPECIAL_BASE 0x57D4E80ull +#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x57D5000ull +#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x57D5200ull +#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x57D5400ull +#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x57D5600ull +#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_E2E_CRDT_BASE 0x57D5800ull +#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC7_MSTR_IF_AXUSER_BASE 0x57D5A80ull +#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC7_MSTR_IF_DBG_HBW_BASE 0x57D5B00ull +#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC7_MSTR_IF_DBG_LBW_BASE 0x57D5B80ull +#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC7_MSTR_IF_CORE_HBW_BASE 0x57D5C00ull +#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC7_MSTR_IF_CORE_LBW_BASE 0x57D5D80ull +#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC7_MSTR_IF_SPECIAL_BASE 0x57D5E80ull +#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC7_TX_AXUSER_BASE 0x57D6000ull +#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_TX_AXUSER_SECTION 0x2000 +#define mmNIC7_SERDES0_BASE 0x57D8000ull +#define NIC7_SERDES0_MAX_OFFSET 0x3E40 +#define NIC7_SERDES0_SECTION 0x4000 +#define mmNIC7_SERDES1_BASE 0x57DC000ull +#define NIC7_SERDES1_MAX_OFFSET 0x3E40 +#define NIC7_SERDES1_SECTION 0x4000 +#define mmNIC7_PHY_BASE 0x57E0000ull +#define NIC7_PHY_MAX_OFFSET 0x1000 +#define NIC7_PHY_SECTION 0xE800 +#define mmNIC7_PHY_SPECIAL_BASE 0x57E0E80ull +#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT7_MAC_AUX_BASE 0x57E8000ull +#define PRT7_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT7_MAC_AUX_SECTION 0xE800 +#define mmPRT7_MAC_AUX_SPECIAL_BASE 0x57E8E80ull +#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT7_MAC_CORE_BASE 0x57E9000ull +#define PRT7_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT7_MAC_CORE_SECTION 0xE800 +#define mmPRT7_MAC_CORE_SPECIAL_BASE 0x57E9E80ull +#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC7_MAC_RS_FEC_BASE 0x57EA000ull +#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC7_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC7_MAC_GLOB_STAT_CONTROL_REG_BASE 0x57EB000ull +#define NIC7_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC7_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC7_MAC_GLOB_STAT_RX0_BASE 0x57EB100ull +#define NIC7_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX1_BASE 0x57EB18Cull +#define NIC7_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX2_BASE 0x57EB218ull +#define NIC7_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX3_BASE 0x57EB2A4ull +#define NIC7_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_TX0_BASE 0x57EB330ull +#define NIC7_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX1_BASE 0x57EB398ull +#define NIC7_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX2_BASE 0x57EB400ull +#define NIC7_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX3_BASE 0x57EB468ull +#define NIC7_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC7_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x57EB800ull +#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC7_MAC_CH0_MAC_PCS_BASE 0x57EC000ull +#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH0_MAC_128_BASE 0x57EC400ull +#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH0_MAC_AN_BASE 0x57EC800ull +#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH1_MAC_PCS_BASE 0x57ED000ull +#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH1_MAC_128_BASE 0x57ED400ull +#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH1_MAC_AN_BASE 0x57ED800ull +#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH2_MAC_PCS_BASE 0x57EE000ull +#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH2_MAC_128_BASE 0x57EE400ull +#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH2_MAC_AN_BASE 0x57EE800ull +#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH3_MAC_PCS_BASE 0x57EF000ull +#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH3_MAC_128_BASE 0x57EF400ull +#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH3_MAC_AN_BASE 0x57EF800ull +#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5800000ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5800080ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5800100ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5800180ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_0_SPECIAL_BASE 0x5800E80ull +#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5801000ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5801080ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5801100ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5801180ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_1_SPECIAL_BASE 0x5801E80ull +#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5802000ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5802080ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5802100ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5802180ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_2_SPECIAL_BASE 0x5802E80ull +#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5803000ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5803080ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5803100ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5803180ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_3_SPECIAL_BASE 0x5803E80ull +#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5804000ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5804080ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5804100ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5804180ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_4_SPECIAL_BASE 0x5804E80ull +#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5805000ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5805080ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5805100ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5805180ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_5_SPECIAL_BASE 0x5805E80ull +#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5806000ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5806080ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5806100ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5806180ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_6_SPECIAL_BASE 0x5806E80ull +#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5807000ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5807080ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5807100ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5807180ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_7_SPECIAL_BASE 0x5807E80ull +#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5808000ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5808080ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5808100ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5808180ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_8_SPECIAL_BASE 0x5808E80ull +#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5809000ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5809080ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5809100ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5809180ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_9_SPECIAL_BASE 0x5809E80ull +#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x580A000ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x580A080ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x580A100ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x580A180ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_10_SPECIAL_BASE 0x580AE80ull +#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x580B000ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x580B080ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x580B100ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x580B180ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_11_SPECIAL_BASE 0x580BE80ull +#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x580C000ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x580C080ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x580C100ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x580C180ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_12_SPECIAL_BASE 0x580CE80ull +#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x580D000ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x580D080ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x580D100ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x580D180ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_13_SPECIAL_BASE 0x580DE80ull +#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x580E000ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x580E080ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x580E100ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x580E180ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_14_SPECIAL_BASE 0x580EE80ull +#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM_DCCM0_BASE 0x5810000ull +#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM0_SECTION 0x8000 +#define mmNIC8_QM_ARC_AUX0_BASE 0x5818000ull +#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC8_QM_ARC_AUX0_SPECIAL_BASE 0x5818E80ull +#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM0_BASE 0x581A000ull +#define NIC8_QM0_MAX_OFFSET 0x1000 +#define NIC8_QM0_SECTION 0x9000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x581A900ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x581A908ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x581A910ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x581A918ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x581A920ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x581A928ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x581A930ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x581A938ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x581A940ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x581A948ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x581A950ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x581A958ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x581A960ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x581A968ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x581A970ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x581A978ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC8_QM0_AXUSER_SECURED_BASE 0x581AB00ull +#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC8_QM0_AXUSER_NONSECURED_BASE 0x581AB80ull +#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC8_QM0_DBG_HBW_BASE 0x581AC00ull +#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC8_QM0_DBG_LBW_BASE 0x581AC80ull +#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC8_QM0_CGM_BASE 0x581AD80ull +#define NIC8_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM0_CGM_SECTION 0x1000 +#define mmNIC8_QM0_SPECIAL_BASE 0x581AE80ull +#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC8_QPC0_BASE 0x581F000ull +#define NIC8_QPC0_MAX_OFFSET 0x1000 +#define NIC8_QPC0_SECTION 0x7200 +#define mmNIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x581F720ull +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x581F728ull +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x581F730ull +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x581F738ull +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x581F740ull +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x581F748ull +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x581F750ull +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x581F758ull +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x581F760ull +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x581F768ull +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x581F770ull +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x581F778ull +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x581F780ull +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x581F788ull +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x581F790ull +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x581F798ull +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x581F7A0ull +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x581F7A8ull +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x581F7B0ull +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x581F7B8ull +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x581F7C0ull +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x581F7C8ull +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x581F7D0ull +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x581F7D8ull +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x581F7E0ull +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x581F7E8ull +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x581F7F0ull +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x581F7F8ull +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x581F800ull +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x581F808ull +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x581F810ull +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x581F818ull +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC8_QPC0_AXUSER_CONG_QUE_BASE 0x581FB80ull +#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_RXWQE_BASE 0x581FBE0ull +#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x581FC40ull +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_DB_FIFO_BASE 0x581FCA0ull +#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x581FD00ull +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x581FD60ull +#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_QPC_RESP_BASE 0x581FDC0ull +#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_QPC_REQ_BASE 0x581FE20ull +#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC8_QPC0_SPECIAL_BASE 0x581FE80ull +#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5820000ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5820080ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5820100ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5820180ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_0_SPECIAL_BASE 0x5820E80ull +#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5821000ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5821080ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5821100ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5821180ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_1_SPECIAL_BASE 0x5821E80ull +#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5822000ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5822080ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5822100ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5822180ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_2_SPECIAL_BASE 0x5822E80ull +#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5823000ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5823080ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5823100ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5823180ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_3_SPECIAL_BASE 0x5823E80ull +#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5824000ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5824080ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5824100ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5824180ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_4_SPECIAL_BASE 0x5824E80ull +#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5825000ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5825080ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5825100ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5825180ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_5_SPECIAL_BASE 0x5825E80ull +#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5826000ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5826080ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5826100ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5826180ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_6_SPECIAL_BASE 0x5826E80ull +#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5827000ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5827080ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5827100ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5827180ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_7_SPECIAL_BASE 0x5827E80ull +#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5828000ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5828080ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5828100ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5828180ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_8_SPECIAL_BASE 0x5828E80ull +#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5829000ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5829080ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5829100ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5829180ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_9_SPECIAL_BASE 0x5829E80ull +#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x582A000ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x582A080ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x582A100ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x582A180ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_10_SPECIAL_BASE 0x582AE80ull +#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x582B000ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x582B080ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x582B100ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x582B180ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_11_SPECIAL_BASE 0x582BE80ull +#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x582C000ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x582C080ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x582C100ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x582C180ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_12_SPECIAL_BASE 0x582CE80ull +#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x582D000ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x582D080ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x582D100ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x582D180ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_13_SPECIAL_BASE 0x582DE80ull +#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x582E000ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x582E080ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x582E100ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x582E180ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_14_SPECIAL_BASE 0x582EE80ull +#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM_DCCM1_BASE 0x5830000ull +#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM1_SECTION 0x8000 +#define mmNIC8_QM_ARC_AUX1_BASE 0x5838000ull +#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC8_QM_ARC_AUX1_SPECIAL_BASE 0x5838E80ull +#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM1_BASE 0x583A000ull +#define NIC8_QM1_MAX_OFFSET 0x1000 +#define NIC8_QM1_SECTION 0x9000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x583A900ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x583A908ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x583A910ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x583A918ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x583A920ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x583A928ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x583A930ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x583A938ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x583A940ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x583A948ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x583A950ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x583A958ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x583A960ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x583A968ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x583A970ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x583A978ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC8_QM1_AXUSER_SECURED_BASE 0x583AB00ull +#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC8_QM1_AXUSER_NONSECURED_BASE 0x583AB80ull +#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC8_QM1_DBG_HBW_BASE 0x583AC00ull +#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC8_QM1_DBG_LBW_BASE 0x583AC80ull +#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC8_QM1_CGM_BASE 0x583AD80ull +#define NIC8_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM1_CGM_SECTION 0x1000 +#define mmNIC8_QM1_SPECIAL_BASE 0x583AE80ull +#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC8_QPC1_BASE 0x583F000ull +#define NIC8_QPC1_MAX_OFFSET 0x1000 +#define NIC8_QPC1_SECTION 0x7200 +#define mmNIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x583F720ull +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x583F728ull +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x583F730ull +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x583F738ull +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x583F740ull +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x583F748ull +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x583F750ull +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x583F758ull +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x583F760ull +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x583F768ull +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x583F770ull +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x583F778ull +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x583F780ull +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x583F788ull +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x583F790ull +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x583F798ull +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x583F7A0ull +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x583F7A8ull +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x583F7B0ull +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x583F7B8ull +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x583F7C0ull +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x583F7C8ull +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x583F7D0ull +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x583F7D8ull +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x583F7E0ull +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x583F7E8ull +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x583F7F0ull +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x583F7F8ull +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x583F800ull +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x583F808ull +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x583F810ull +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x583F818ull +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC8_QPC1_AXUSER_CONG_QUE_BASE 0x583FB80ull +#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_RXWQE_BASE 0x583FBE0ull +#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x583FC40ull +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_DB_FIFO_BASE 0x583FCA0ull +#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x583FD00ull +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x583FD60ull +#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_QPC_RESP_BASE 0x583FDC0ull +#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_QPC_REQ_BASE 0x583FE20ull +#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC8_QPC1_SPECIAL_BASE 0x583FE80ull +#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC8_TMR_BASE 0x5848000ull +#define NIC8_TMR_MAX_OFFSET 0x1000 +#define NIC8_TMR_SECTION 0xD600 +#define mmNIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5848D60ull +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC8_TMR_AXUSER_TMR_FIFO_BASE 0x5848DC0ull +#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC8_TMR_AXUSER_TMR_FSM_BASE 0x5848E20ull +#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC8_TMR_SPECIAL_BASE 0x5848E80ull +#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXB_CORE_BASE 0x5849000ull +#define NIC8_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC8_RXB_CORE_SECTION 0x6100 +#define mmNIC8_RXB_CORE_SCT_AWUSER_BASE 0x5849610ull +#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC8_RXB_CORE_SPECIAL_BASE 0x5849E80ull +#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE0_BASE 0x584A000ull +#define NIC8_RXE0_MAX_OFFSET 0x1000 +#define NIC8_RXE0_SECTION 0x9000 +#define mmNIC8_RXE0_WQE_ARUSER_BASE 0x584A900ull +#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC8_RXE0_SPECIAL_BASE 0x584AE80ull +#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE1_BASE 0x584B000ull +#define NIC8_RXE1_MAX_OFFSET 0x1000 +#define NIC8_RXE1_SECTION 0x9000 +#define mmNIC8_RXE1_WQE_ARUSER_BASE 0x584B900ull +#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC8_RXE1_SPECIAL_BASE 0x584BE80ull +#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x584C000ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x584C050ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x584C0A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x584C0F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x584C140ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x584C190ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x584C1E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x584C230ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x584C280ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x584C2D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x584C320ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x584C370ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x584C3C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x584C410ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x584C460ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x584C4B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x584C500ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x584C550ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x584C5A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x584C5F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x584C640ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x584C690ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x584C6E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x584C730ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x584C780ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x584C7D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x584C820ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x584C870ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x584C8C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x584C910ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x584C960ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x584C9B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC8_RXE0_AXUSER_SPECIAL_BASE 0x584CE80ull +#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x584D000ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x584D050ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x584D0A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x584D0F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x584D140ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x584D190ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x584D1E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x584D230ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x584D280ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x584D2D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x584D320ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x584D370ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x584D3C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x584D410ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x584D460ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x584D4B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x584D500ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x584D550ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x584D5A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x584D5F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x584D640ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x584D690ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x584D6E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x584D730ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x584D780ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x584D7D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x584D820ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x584D870ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x584D8C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x584D910ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x584D960ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x584D9B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC8_RXE1_AXUSER_SPECIAL_BASE 0x584DE80ull +#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC8_TXS0_BASE 0x5850000ull +#define NIC8_TXS0_MAX_OFFSET 0x1000 +#define NIC8_TXS0_SECTION 0xE800 +#define mmNIC8_TXS0_SPECIAL_BASE 0x5850E80ull +#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXS1_BASE 0x5851000ull +#define NIC8_TXS1_MAX_OFFSET 0x1000 +#define NIC8_TXS1_SECTION 0xE800 +#define mmNIC8_TXS1_SPECIAL_BASE 0x5851E80ull +#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXE0_BASE 0x5852000ull +#define NIC8_TXE0_MAX_OFFSET 0x1000 +#define NIC8_TXE0_SECTION 0xE800 +#define mmNIC8_TXE0_SPECIAL_BASE 0x5852E80ull +#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXE1_BASE 0x5853000ull +#define NIC8_TXE1_MAX_OFFSET 0x1000 +#define NIC8_TXE1_SECTION 0xE800 +#define mmNIC8_TXE1_SPECIAL_BASE 0x5853E80ull +#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXB_BASE 0x5854000ull +#define NIC8_TXB_MAX_OFFSET 0x1000 +#define NIC8_TXB_SECTION 0xE800 +#define mmNIC8_TXB_SPECIAL_BASE 0x5854E80ull +#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x5855000ull +#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x5855200ull +#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x5855400ull +#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x5855600ull +#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_E2E_CRDT_BASE 0x5855800ull +#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC8_MSTR_IF_AXUSER_BASE 0x5855A80ull +#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC8_MSTR_IF_DBG_HBW_BASE 0x5855B00ull +#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC8_MSTR_IF_DBG_LBW_BASE 0x5855B80ull +#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC8_MSTR_IF_CORE_HBW_BASE 0x5855C00ull +#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC8_MSTR_IF_CORE_LBW_BASE 0x5855D80ull +#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC8_MSTR_IF_SPECIAL_BASE 0x5855E80ull +#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC8_TX_AXUSER_BASE 0x5856000ull +#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_TX_AXUSER_SECTION 0x2000 +#define mmNIC8_SERDES0_BASE 0x5858000ull +#define NIC8_SERDES0_MAX_OFFSET 0x3E40 +#define NIC8_SERDES0_SECTION 0x4000 +#define mmNIC8_SERDES1_BASE 0x585C000ull +#define NIC8_SERDES1_MAX_OFFSET 0x3E40 +#define NIC8_SERDES1_SECTION 0x4000 +#define mmNIC8_PHY_BASE 0x5860000ull +#define NIC8_PHY_MAX_OFFSET 0x1000 +#define NIC8_PHY_SECTION 0xE800 +#define mmNIC8_PHY_SPECIAL_BASE 0x5860E80ull +#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT8_MAC_AUX_BASE 0x5868000ull +#define PRT8_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT8_MAC_AUX_SECTION 0xE800 +#define mmPRT8_MAC_AUX_SPECIAL_BASE 0x5868E80ull +#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT8_MAC_CORE_BASE 0x5869000ull +#define PRT8_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT8_MAC_CORE_SECTION 0xE800 +#define mmPRT8_MAC_CORE_SPECIAL_BASE 0x5869E80ull +#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC8_MAC_RS_FEC_BASE 0x586A000ull +#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC8_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC8_MAC_GLOB_STAT_CONTROL_REG_BASE 0x586B000ull +#define NIC8_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC8_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC8_MAC_GLOB_STAT_RX0_BASE 0x586B100ull +#define NIC8_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX1_BASE 0x586B18Cull +#define NIC8_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX2_BASE 0x586B218ull +#define NIC8_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX3_BASE 0x586B2A4ull +#define NIC8_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_TX0_BASE 0x586B330ull +#define NIC8_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX1_BASE 0x586B398ull +#define NIC8_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX2_BASE 0x586B400ull +#define NIC8_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX3_BASE 0x586B468ull +#define NIC8_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC8_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x586B800ull +#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC8_MAC_CH0_MAC_PCS_BASE 0x586C000ull +#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH0_MAC_128_BASE 0x586C400ull +#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH0_MAC_AN_BASE 0x586C800ull +#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH1_MAC_PCS_BASE 0x586D000ull +#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH1_MAC_128_BASE 0x586D400ull +#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH1_MAC_AN_BASE 0x586D800ull +#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH2_MAC_PCS_BASE 0x586E000ull +#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH2_MAC_128_BASE 0x586E400ull +#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH2_MAC_AN_BASE 0x586E800ull +#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH3_MAC_PCS_BASE 0x586F000ull +#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH3_MAC_128_BASE 0x586F400ull +#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH3_MAC_AN_BASE 0x586F800ull +#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5880000ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5880080ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5880100ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5880180ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_0_SPECIAL_BASE 0x5880E80ull +#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5881000ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5881080ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5881100ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5881180ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_1_SPECIAL_BASE 0x5881E80ull +#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5882000ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5882080ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5882100ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5882180ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_2_SPECIAL_BASE 0x5882E80ull +#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5883000ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5883080ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5883100ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5883180ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_3_SPECIAL_BASE 0x5883E80ull +#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5884000ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5884080ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5884100ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5884180ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_4_SPECIAL_BASE 0x5884E80ull +#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5885000ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5885080ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5885100ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5885180ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_5_SPECIAL_BASE 0x5885E80ull +#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5886000ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5886080ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5886100ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5886180ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_6_SPECIAL_BASE 0x5886E80ull +#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5887000ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5887080ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5887100ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5887180ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_7_SPECIAL_BASE 0x5887E80ull +#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5888000ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5888080ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5888100ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5888180ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_8_SPECIAL_BASE 0x5888E80ull +#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5889000ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5889080ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5889100ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5889180ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_9_SPECIAL_BASE 0x5889E80ull +#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x588A000ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x588A080ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x588A100ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x588A180ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_10_SPECIAL_BASE 0x588AE80ull +#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x588B000ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x588B080ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x588B100ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x588B180ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_11_SPECIAL_BASE 0x588BE80ull +#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x588C000ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x588C080ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x588C100ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x588C180ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_12_SPECIAL_BASE 0x588CE80ull +#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x588D000ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x588D080ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x588D100ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x588D180ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_13_SPECIAL_BASE 0x588DE80ull +#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x588E000ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x588E080ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x588E100ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x588E180ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_14_SPECIAL_BASE 0x588EE80ull +#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM_DCCM0_BASE 0x5890000ull +#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM0_SECTION 0x8000 +#define mmNIC9_QM_ARC_AUX0_BASE 0x5898000ull +#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC9_QM_ARC_AUX0_SPECIAL_BASE 0x5898E80ull +#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM0_BASE 0x589A000ull +#define NIC9_QM0_MAX_OFFSET 0x1000 +#define NIC9_QM0_SECTION 0x9000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x589A900ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x589A908ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x589A910ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x589A918ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x589A920ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x589A928ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x589A930ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x589A938ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x589A940ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x589A948ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x589A950ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x589A958ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x589A960ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x589A968ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x589A970ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x589A978ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC9_QM0_AXUSER_SECURED_BASE 0x589AB00ull +#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC9_QM0_AXUSER_NONSECURED_BASE 0x589AB80ull +#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC9_QM0_DBG_HBW_BASE 0x589AC00ull +#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC9_QM0_DBG_LBW_BASE 0x589AC80ull +#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC9_QM0_CGM_BASE 0x589AD80ull +#define NIC9_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM0_CGM_SECTION 0x1000 +#define mmNIC9_QM0_SPECIAL_BASE 0x589AE80ull +#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC9_QPC0_BASE 0x589F000ull +#define NIC9_QPC0_MAX_OFFSET 0x1000 +#define NIC9_QPC0_SECTION 0x7200 +#define mmNIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x589F720ull +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x589F728ull +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x589F730ull +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x589F738ull +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x589F740ull +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x589F748ull +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x589F750ull +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x589F758ull +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x589F760ull +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x589F768ull +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x589F770ull +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x589F778ull +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x589F780ull +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x589F788ull +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x589F790ull +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x589F798ull +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x589F7A0ull +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x589F7A8ull +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x589F7B0ull +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x589F7B8ull +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x589F7C0ull +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x589F7C8ull +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x589F7D0ull +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x589F7D8ull +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x589F7E0ull +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x589F7E8ull +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x589F7F0ull +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x589F7F8ull +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x589F800ull +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x589F808ull +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x589F810ull +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x589F818ull +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC9_QPC0_AXUSER_CONG_QUE_BASE 0x589FB80ull +#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_RXWQE_BASE 0x589FBE0ull +#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x589FC40ull +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_DB_FIFO_BASE 0x589FCA0ull +#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x589FD00ull +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x589FD60ull +#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_QPC_RESP_BASE 0x589FDC0ull +#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_QPC_REQ_BASE 0x589FE20ull +#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC9_QPC0_SPECIAL_BASE 0x589FE80ull +#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x58A0000ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x58A0080ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x58A0100ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x58A0180ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_0_SPECIAL_BASE 0x58A0E80ull +#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x58A1000ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x58A1080ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x58A1100ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x58A1180ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_1_SPECIAL_BASE 0x58A1E80ull +#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x58A2000ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x58A2080ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x58A2100ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x58A2180ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_2_SPECIAL_BASE 0x58A2E80ull +#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x58A3000ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x58A3080ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x58A3100ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x58A3180ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_3_SPECIAL_BASE 0x58A3E80ull +#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x58A4000ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x58A4080ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x58A4100ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x58A4180ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_4_SPECIAL_BASE 0x58A4E80ull +#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x58A5000ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x58A5080ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x58A5100ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x58A5180ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_5_SPECIAL_BASE 0x58A5E80ull +#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x58A6000ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x58A6080ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x58A6100ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x58A6180ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_6_SPECIAL_BASE 0x58A6E80ull +#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x58A7000ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x58A7080ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x58A7100ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x58A7180ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_7_SPECIAL_BASE 0x58A7E80ull +#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x58A8000ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x58A8080ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x58A8100ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x58A8180ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_8_SPECIAL_BASE 0x58A8E80ull +#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x58A9000ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x58A9080ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x58A9100ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x58A9180ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_9_SPECIAL_BASE 0x58A9E80ull +#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x58AA000ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x58AA080ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x58AA100ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x58AA180ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_10_SPECIAL_BASE 0x58AAE80ull +#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x58AB000ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x58AB080ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x58AB100ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x58AB180ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_11_SPECIAL_BASE 0x58ABE80ull +#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x58AC000ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x58AC080ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x58AC100ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x58AC180ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_12_SPECIAL_BASE 0x58ACE80ull +#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x58AD000ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x58AD080ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x58AD100ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x58AD180ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_13_SPECIAL_BASE 0x58ADE80ull +#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x58AE000ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x58AE080ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x58AE100ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x58AE180ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_14_SPECIAL_BASE 0x58AEE80ull +#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM_DCCM1_BASE 0x58B0000ull +#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM1_SECTION 0x8000 +#define mmNIC9_QM_ARC_AUX1_BASE 0x58B8000ull +#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC9_QM_ARC_AUX1_SPECIAL_BASE 0x58B8E80ull +#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM1_BASE 0x58BA000ull +#define NIC9_QM1_MAX_OFFSET 0x1000 +#define NIC9_QM1_SECTION 0x9000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x58BA900ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x58BA908ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x58BA910ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x58BA918ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x58BA920ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x58BA928ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x58BA930ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x58BA938ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x58BA940ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x58BA948ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x58BA950ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x58BA958ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x58BA960ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x58BA968ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x58BA970ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x58BA978ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC9_QM1_AXUSER_SECURED_BASE 0x58BAB00ull +#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC9_QM1_AXUSER_NONSECURED_BASE 0x58BAB80ull +#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC9_QM1_DBG_HBW_BASE 0x58BAC00ull +#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC9_QM1_DBG_LBW_BASE 0x58BAC80ull +#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC9_QM1_CGM_BASE 0x58BAD80ull +#define NIC9_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM1_CGM_SECTION 0x1000 +#define mmNIC9_QM1_SPECIAL_BASE 0x58BAE80ull +#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC9_QPC1_BASE 0x58BF000ull +#define NIC9_QPC1_MAX_OFFSET 0x1000 +#define NIC9_QPC1_SECTION 0x7200 +#define mmNIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x58BF720ull +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x58BF728ull +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x58BF730ull +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x58BF738ull +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x58BF740ull +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x58BF748ull +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x58BF750ull +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x58BF758ull +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x58BF760ull +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x58BF768ull +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x58BF770ull +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x58BF778ull +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x58BF780ull +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x58BF788ull +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x58BF790ull +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x58BF798ull +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x58BF7A0ull +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x58BF7A8ull +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x58BF7B0ull +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x58BF7B8ull +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x58BF7C0ull +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x58BF7C8ull +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x58BF7D0ull +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x58BF7D8ull +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x58BF7E0ull +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x58BF7E8ull +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x58BF7F0ull +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x58BF7F8ull +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x58BF800ull +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x58BF808ull +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x58BF810ull +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x58BF818ull +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC9_QPC1_AXUSER_CONG_QUE_BASE 0x58BFB80ull +#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_RXWQE_BASE 0x58BFBE0ull +#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x58BFC40ull +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_DB_FIFO_BASE 0x58BFCA0ull +#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x58BFD00ull +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x58BFD60ull +#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_QPC_RESP_BASE 0x58BFDC0ull +#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_QPC_REQ_BASE 0x58BFE20ull +#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC9_QPC1_SPECIAL_BASE 0x58BFE80ull +#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC9_TMR_BASE 0x58C8000ull +#define NIC9_TMR_MAX_OFFSET 0x1000 +#define NIC9_TMR_SECTION 0xD600 +#define mmNIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x58C8D60ull +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC9_TMR_AXUSER_TMR_FIFO_BASE 0x58C8DC0ull +#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC9_TMR_AXUSER_TMR_FSM_BASE 0x58C8E20ull +#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC9_TMR_SPECIAL_BASE 0x58C8E80ull +#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXB_CORE_BASE 0x58C9000ull +#define NIC9_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC9_RXB_CORE_SECTION 0x6100 +#define mmNIC9_RXB_CORE_SCT_AWUSER_BASE 0x58C9610ull +#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC9_RXB_CORE_SPECIAL_BASE 0x58C9E80ull +#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE0_BASE 0x58CA000ull +#define NIC9_RXE0_MAX_OFFSET 0x1000 +#define NIC9_RXE0_SECTION 0x9000 +#define mmNIC9_RXE0_WQE_ARUSER_BASE 0x58CA900ull +#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC9_RXE0_SPECIAL_BASE 0x58CAE80ull +#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE1_BASE 0x58CB000ull +#define NIC9_RXE1_MAX_OFFSET 0x1000 +#define NIC9_RXE1_SECTION 0x9000 +#define mmNIC9_RXE1_WQE_ARUSER_BASE 0x58CB900ull +#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC9_RXE1_SPECIAL_BASE 0x58CBE80ull +#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x58CC000ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x58CC050ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x58CC0A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x58CC0F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x58CC140ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x58CC190ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x58CC1E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x58CC230ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x58CC280ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x58CC2D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x58CC320ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x58CC370ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x58CC3C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x58CC410ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x58CC460ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x58CC4B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x58CC500ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x58CC550ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x58CC5A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x58CC5F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x58CC640ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x58CC690ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x58CC6E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x58CC730ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x58CC780ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x58CC7D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x58CC820ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x58CC870ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x58CC8C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x58CC910ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x58CC960ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x58CC9B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC9_RXE0_AXUSER_SPECIAL_BASE 0x58CCE80ull +#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x58CD000ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x58CD050ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x58CD0A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x58CD0F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x58CD140ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x58CD190ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x58CD1E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x58CD230ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x58CD280ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x58CD2D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x58CD320ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x58CD370ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x58CD3C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x58CD410ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x58CD460ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x58CD4B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x58CD500ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x58CD550ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x58CD5A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x58CD5F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x58CD640ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x58CD690ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x58CD6E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x58CD730ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x58CD780ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x58CD7D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x58CD820ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x58CD870ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x58CD8C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x58CD910ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x58CD960ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x58CD9B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC9_RXE1_AXUSER_SPECIAL_BASE 0x58CDE80ull +#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC9_TXS0_BASE 0x58D0000ull +#define NIC9_TXS0_MAX_OFFSET 0x1000 +#define NIC9_TXS0_SECTION 0xE800 +#define mmNIC9_TXS0_SPECIAL_BASE 0x58D0E80ull +#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXS1_BASE 0x58D1000ull +#define NIC9_TXS1_MAX_OFFSET 0x1000 +#define NIC9_TXS1_SECTION 0xE800 +#define mmNIC9_TXS1_SPECIAL_BASE 0x58D1E80ull +#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXE0_BASE 0x58D2000ull +#define NIC9_TXE0_MAX_OFFSET 0x1000 +#define NIC9_TXE0_SECTION 0xE800 +#define mmNIC9_TXE0_SPECIAL_BASE 0x58D2E80ull +#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXE1_BASE 0x58D3000ull +#define NIC9_TXE1_MAX_OFFSET 0x1000 +#define NIC9_TXE1_SECTION 0xE800 +#define mmNIC9_TXE1_SPECIAL_BASE 0x58D3E80ull +#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXB_BASE 0x58D4000ull +#define NIC9_TXB_MAX_OFFSET 0x1000 +#define NIC9_TXB_SECTION 0xE800 +#define mmNIC9_TXB_SPECIAL_BASE 0x58D4E80ull +#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x58D5000ull +#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x58D5200ull +#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x58D5400ull +#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x58D5600ull +#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_E2E_CRDT_BASE 0x58D5800ull +#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC9_MSTR_IF_AXUSER_BASE 0x58D5A80ull +#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC9_MSTR_IF_DBG_HBW_BASE 0x58D5B00ull +#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC9_MSTR_IF_DBG_LBW_BASE 0x58D5B80ull +#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC9_MSTR_IF_CORE_HBW_BASE 0x58D5C00ull +#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC9_MSTR_IF_CORE_LBW_BASE 0x58D5D80ull +#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC9_MSTR_IF_SPECIAL_BASE 0x58D5E80ull +#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC9_TX_AXUSER_BASE 0x58D6000ull +#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_TX_AXUSER_SECTION 0x2000 +#define mmNIC9_SERDES0_BASE 0x58D8000ull +#define NIC9_SERDES0_MAX_OFFSET 0x3E40 +#define NIC9_SERDES0_SECTION 0x4000 +#define mmNIC9_SERDES1_BASE 0x58DC000ull +#define NIC9_SERDES1_MAX_OFFSET 0x3E40 +#define NIC9_SERDES1_SECTION 0x4000 +#define mmNIC9_PHY_BASE 0x58E0000ull +#define NIC9_PHY_MAX_OFFSET 0x1000 +#define NIC9_PHY_SECTION 0xE800 +#define mmNIC9_PHY_SPECIAL_BASE 0x58E0E80ull +#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT9_MAC_AUX_BASE 0x58E8000ull +#define PRT9_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT9_MAC_AUX_SECTION 0xE800 +#define mmPRT9_MAC_AUX_SPECIAL_BASE 0x58E8E80ull +#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT9_MAC_CORE_BASE 0x58E9000ull +#define PRT9_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT9_MAC_CORE_SECTION 0xE800 +#define mmPRT9_MAC_CORE_SPECIAL_BASE 0x58E9E80ull +#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC9_MAC_RS_FEC_BASE 0x58EA000ull +#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC9_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC9_MAC_GLOB_STAT_CONTROL_REG_BASE 0x58EB000ull +#define NIC9_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC9_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC9_MAC_GLOB_STAT_RX0_BASE 0x58EB100ull +#define NIC9_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX1_BASE 0x58EB18Cull +#define NIC9_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX2_BASE 0x58EB218ull +#define NIC9_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX3_BASE 0x58EB2A4ull +#define NIC9_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_TX0_BASE 0x58EB330ull +#define NIC9_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX1_BASE 0x58EB398ull +#define NIC9_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX2_BASE 0x58EB400ull +#define NIC9_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX3_BASE 0x58EB468ull +#define NIC9_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC9_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x58EB800ull +#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC9_MAC_CH0_MAC_PCS_BASE 0x58EC000ull +#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH0_MAC_128_BASE 0x58EC400ull +#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH0_MAC_AN_BASE 0x58EC800ull +#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH1_MAC_PCS_BASE 0x58ED000ull +#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH1_MAC_128_BASE 0x58ED400ull +#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH1_MAC_AN_BASE 0x58ED800ull +#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH2_MAC_PCS_BASE 0x58EE000ull +#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH2_MAC_128_BASE 0x58EE400ull +#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH2_MAC_AN_BASE 0x58EE800ull +#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH3_MAC_PCS_BASE 0x58EF000ull +#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH3_MAC_128_BASE 0x58EF400ull +#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH3_MAC_AN_BASE 0x58EF800ull +#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5900000ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5900080ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5900100ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5900180ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_0_SPECIAL_BASE 0x5900E80ull +#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5901000ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5901080ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5901100ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5901180ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_1_SPECIAL_BASE 0x5901E80ull +#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5902000ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5902080ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5902100ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5902180ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_2_SPECIAL_BASE 0x5902E80ull +#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5903000ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5903080ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5903100ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5903180ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_3_SPECIAL_BASE 0x5903E80ull +#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5904000ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5904080ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5904100ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5904180ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_4_SPECIAL_BASE 0x5904E80ull +#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5905000ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5905080ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5905100ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5905180ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_5_SPECIAL_BASE 0x5905E80ull +#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5906000ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5906080ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5906100ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5906180ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_6_SPECIAL_BASE 0x5906E80ull +#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5907000ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5907080ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5907100ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5907180ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_7_SPECIAL_BASE 0x5907E80ull +#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5908000ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5908080ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5908100ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5908180ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_8_SPECIAL_BASE 0x5908E80ull +#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5909000ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5909080ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5909100ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5909180ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_9_SPECIAL_BASE 0x5909E80ull +#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x590A000ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x590A080ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x590A100ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x590A180ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_10_SPECIAL_BASE 0x590AE80ull +#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x590B000ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x590B080ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x590B100ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x590B180ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_11_SPECIAL_BASE 0x590BE80ull +#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x590C000ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x590C080ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x590C100ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x590C180ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_12_SPECIAL_BASE 0x590CE80ull +#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x590D000ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x590D080ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x590D100ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x590D180ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_13_SPECIAL_BASE 0x590DE80ull +#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x590E000ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x590E080ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x590E100ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x590E180ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_14_SPECIAL_BASE 0x590EE80ull +#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM_DCCM0_BASE 0x5910000ull +#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM0_SECTION 0x8000 +#define mmNIC10_QM_ARC_AUX0_BASE 0x5918000ull +#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC10_QM_ARC_AUX0_SPECIAL_BASE 0x5918E80ull +#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM0_BASE 0x591A000ull +#define NIC10_QM0_MAX_OFFSET 0x1000 +#define NIC10_QM0_SECTION 0x9000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x591A900ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x591A908ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x591A910ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x591A918ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x591A920ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x591A928ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x591A930ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x591A938ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x591A940ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x591A948ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x591A950ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x591A958ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x591A960ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x591A968ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x591A970ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x591A978ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC10_QM0_AXUSER_SECURED_BASE 0x591AB00ull +#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC10_QM0_AXUSER_NONSECURED_BASE 0x591AB80ull +#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC10_QM0_DBG_HBW_BASE 0x591AC00ull +#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC10_QM0_DBG_LBW_BASE 0x591AC80ull +#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC10_QM0_CGM_BASE 0x591AD80ull +#define NIC10_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM0_CGM_SECTION 0x1000 +#define mmNIC10_QM0_SPECIAL_BASE 0x591AE80ull +#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC10_QPC0_BASE 0x591F000ull +#define NIC10_QPC0_MAX_OFFSET 0x1000 +#define NIC10_QPC0_SECTION 0x7200 +#define mmNIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x591F720ull +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x591F728ull +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x591F730ull +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x591F738ull +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x591F740ull +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x591F748ull +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x591F750ull +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x591F758ull +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x591F760ull +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x591F768ull +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x591F770ull +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x591F778ull +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x591F780ull +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x591F788ull +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x591F790ull +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x591F798ull +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x591F7A0ull +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x591F7A8ull +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x591F7B0ull +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x591F7B8ull +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x591F7C0ull +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x591F7C8ull +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x591F7D0ull +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x591F7D8ull +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x591F7E0ull +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x591F7E8ull +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x591F7F0ull +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x591F7F8ull +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x591F800ull +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x591F808ull +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x591F810ull +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x591F818ull +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC10_QPC0_AXUSER_CONG_QUE_BASE 0x591FB80ull +#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_RXWQE_BASE 0x591FBE0ull +#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x591FC40ull +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_DB_FIFO_BASE 0x591FCA0ull +#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x591FD00ull +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x591FD60ull +#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_QPC_RESP_BASE 0x591FDC0ull +#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_QPC_REQ_BASE 0x591FE20ull +#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC10_QPC0_SPECIAL_BASE 0x591FE80ull +#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5920000ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5920080ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5920100ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5920180ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_0_SPECIAL_BASE 0x5920E80ull +#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5921000ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5921080ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5921100ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5921180ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_1_SPECIAL_BASE 0x5921E80ull +#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5922000ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5922080ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5922100ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5922180ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_2_SPECIAL_BASE 0x5922E80ull +#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5923000ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5923080ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5923100ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5923180ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_3_SPECIAL_BASE 0x5923E80ull +#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5924000ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5924080ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5924100ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5924180ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_4_SPECIAL_BASE 0x5924E80ull +#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5925000ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5925080ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5925100ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5925180ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_5_SPECIAL_BASE 0x5925E80ull +#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5926000ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5926080ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5926100ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5926180ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_6_SPECIAL_BASE 0x5926E80ull +#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5927000ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5927080ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5927100ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5927180ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_7_SPECIAL_BASE 0x5927E80ull +#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5928000ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5928080ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5928100ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5928180ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_8_SPECIAL_BASE 0x5928E80ull +#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5929000ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5929080ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5929100ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5929180ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_9_SPECIAL_BASE 0x5929E80ull +#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x592A000ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x592A080ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x592A100ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x592A180ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_10_SPECIAL_BASE 0x592AE80ull +#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x592B000ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x592B080ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x592B100ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x592B180ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_11_SPECIAL_BASE 0x592BE80ull +#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x592C000ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x592C080ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x592C100ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x592C180ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_12_SPECIAL_BASE 0x592CE80ull +#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x592D000ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x592D080ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x592D100ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x592D180ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_13_SPECIAL_BASE 0x592DE80ull +#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x592E000ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x592E080ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x592E100ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x592E180ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_14_SPECIAL_BASE 0x592EE80ull +#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM_DCCM1_BASE 0x5930000ull +#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM1_SECTION 0x8000 +#define mmNIC10_QM_ARC_AUX1_BASE 0x5938000ull +#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC10_QM_ARC_AUX1_SPECIAL_BASE 0x5938E80ull +#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM1_BASE 0x593A000ull +#define NIC10_QM1_MAX_OFFSET 0x1000 +#define NIC10_QM1_SECTION 0x9000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x593A900ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x593A908ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x593A910ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x593A918ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x593A920ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x593A928ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x593A930ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x593A938ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x593A940ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x593A948ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x593A950ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x593A958ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x593A960ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x593A968ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x593A970ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x593A978ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC10_QM1_AXUSER_SECURED_BASE 0x593AB00ull +#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC10_QM1_AXUSER_NONSECURED_BASE 0x593AB80ull +#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC10_QM1_DBG_HBW_BASE 0x593AC00ull +#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC10_QM1_DBG_LBW_BASE 0x593AC80ull +#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC10_QM1_CGM_BASE 0x593AD80ull +#define NIC10_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM1_CGM_SECTION 0x1000 +#define mmNIC10_QM1_SPECIAL_BASE 0x593AE80ull +#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC10_QPC1_BASE 0x593F000ull +#define NIC10_QPC1_MAX_OFFSET 0x1000 +#define NIC10_QPC1_SECTION 0x7200 +#define mmNIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x593F720ull +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x593F728ull +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x593F730ull +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x593F738ull +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x593F740ull +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x593F748ull +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x593F750ull +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x593F758ull +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x593F760ull +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x593F768ull +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x593F770ull +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x593F778ull +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x593F780ull +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x593F788ull +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x593F790ull +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x593F798ull +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x593F7A0ull +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x593F7A8ull +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x593F7B0ull +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x593F7B8ull +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x593F7C0ull +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x593F7C8ull +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x593F7D0ull +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x593F7D8ull +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x593F7E0ull +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x593F7E8ull +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x593F7F0ull +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x593F7F8ull +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x593F800ull +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x593F808ull +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x593F810ull +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x593F818ull +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC10_QPC1_AXUSER_CONG_QUE_BASE 0x593FB80ull +#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_RXWQE_BASE 0x593FBE0ull +#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x593FC40ull +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_DB_FIFO_BASE 0x593FCA0ull +#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x593FD00ull +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x593FD60ull +#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_QPC_RESP_BASE 0x593FDC0ull +#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_QPC_REQ_BASE 0x593FE20ull +#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC10_QPC1_SPECIAL_BASE 0x593FE80ull +#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC10_TMR_BASE 0x5948000ull +#define NIC10_TMR_MAX_OFFSET 0x1000 +#define NIC10_TMR_SECTION 0xD600 +#define mmNIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5948D60ull +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC10_TMR_AXUSER_TMR_FIFO_BASE 0x5948DC0ull +#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC10_TMR_AXUSER_TMR_FSM_BASE 0x5948E20ull +#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC10_TMR_SPECIAL_BASE 0x5948E80ull +#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXB_CORE_BASE 0x5949000ull +#define NIC10_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC10_RXB_CORE_SECTION 0x6100 +#define mmNIC10_RXB_CORE_SCT_AWUSER_BASE 0x5949610ull +#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC10_RXB_CORE_SPECIAL_BASE 0x5949E80ull +#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE0_BASE 0x594A000ull +#define NIC10_RXE0_MAX_OFFSET 0x1000 +#define NIC10_RXE0_SECTION 0x9000 +#define mmNIC10_RXE0_WQE_ARUSER_BASE 0x594A900ull +#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC10_RXE0_SPECIAL_BASE 0x594AE80ull +#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE1_BASE 0x594B000ull +#define NIC10_RXE1_MAX_OFFSET 0x1000 +#define NIC10_RXE1_SECTION 0x9000 +#define mmNIC10_RXE1_WQE_ARUSER_BASE 0x594B900ull +#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC10_RXE1_SPECIAL_BASE 0x594BE80ull +#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x594C000ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x594C050ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x594C0A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x594C0F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x594C140ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x594C190ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x594C1E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x594C230ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x594C280ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x594C2D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x594C320ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x594C370ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x594C3C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x594C410ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x594C460ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x594C4B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x594C500ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x594C550ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x594C5A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x594C5F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x594C640ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x594C690ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x594C6E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x594C730ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x594C780ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x594C7D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x594C820ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x594C870ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x594C8C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x594C910ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x594C960ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x594C9B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC10_RXE0_AXUSER_SPECIAL_BASE 0x594CE80ull +#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x594D000ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x594D050ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x594D0A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x594D0F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x594D140ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x594D190ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x594D1E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x594D230ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x594D280ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x594D2D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x594D320ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x594D370ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x594D3C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x594D410ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x594D460ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x594D4B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x594D500ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x594D550ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x594D5A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x594D5F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x594D640ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x594D690ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x594D6E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x594D730ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x594D780ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x594D7D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x594D820ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x594D870ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x594D8C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x594D910ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x594D960ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x594D9B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC10_RXE1_AXUSER_SPECIAL_BASE 0x594DE80ull +#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC10_TXS0_BASE 0x5950000ull +#define NIC10_TXS0_MAX_OFFSET 0x1000 +#define NIC10_TXS0_SECTION 0xE800 +#define mmNIC10_TXS0_SPECIAL_BASE 0x5950E80ull +#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXS1_BASE 0x5951000ull +#define NIC10_TXS1_MAX_OFFSET 0x1000 +#define NIC10_TXS1_SECTION 0xE800 +#define mmNIC10_TXS1_SPECIAL_BASE 0x5951E80ull +#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXE0_BASE 0x5952000ull +#define NIC10_TXE0_MAX_OFFSET 0x1000 +#define NIC10_TXE0_SECTION 0xE800 +#define mmNIC10_TXE0_SPECIAL_BASE 0x5952E80ull +#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXE1_BASE 0x5953000ull +#define NIC10_TXE1_MAX_OFFSET 0x1000 +#define NIC10_TXE1_SECTION 0xE800 +#define mmNIC10_TXE1_SPECIAL_BASE 0x5953E80ull +#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXB_BASE 0x5954000ull +#define NIC10_TXB_MAX_OFFSET 0x1000 +#define NIC10_TXB_SECTION 0xE800 +#define mmNIC10_TXB_SPECIAL_BASE 0x5954E80ull +#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x5955000ull +#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x5955200ull +#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x5955400ull +#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x5955600ull +#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_E2E_CRDT_BASE 0x5955800ull +#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC10_MSTR_IF_AXUSER_BASE 0x5955A80ull +#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC10_MSTR_IF_DBG_HBW_BASE 0x5955B00ull +#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC10_MSTR_IF_DBG_LBW_BASE 0x5955B80ull +#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC10_MSTR_IF_CORE_HBW_BASE 0x5955C00ull +#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC10_MSTR_IF_CORE_LBW_BASE 0x5955D80ull +#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC10_MSTR_IF_SPECIAL_BASE 0x5955E80ull +#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC10_TX_AXUSER_BASE 0x5956000ull +#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_TX_AXUSER_SECTION 0x2000 +#define mmNIC10_SERDES0_BASE 0x5958000ull +#define NIC10_SERDES0_MAX_OFFSET 0x3E40 +#define NIC10_SERDES0_SECTION 0x4000 +#define mmNIC10_SERDES1_BASE 0x595C000ull +#define NIC10_SERDES1_MAX_OFFSET 0x3E40 +#define NIC10_SERDES1_SECTION 0x4000 +#define mmNIC10_PHY_BASE 0x5960000ull +#define NIC10_PHY_MAX_OFFSET 0x1000 +#define NIC10_PHY_SECTION 0xE800 +#define mmNIC10_PHY_SPECIAL_BASE 0x5960E80ull +#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT10_MAC_AUX_BASE 0x5968000ull +#define PRT10_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT10_MAC_AUX_SECTION 0xE800 +#define mmPRT10_MAC_AUX_SPECIAL_BASE 0x5968E80ull +#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT10_MAC_CORE_BASE 0x5969000ull +#define PRT10_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT10_MAC_CORE_SECTION 0xE800 +#define mmPRT10_MAC_CORE_SPECIAL_BASE 0x5969E80ull +#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC10_MAC_RS_FEC_BASE 0x596A000ull +#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC10_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC10_MAC_GLOB_STAT_CONTROL_REG_BASE 0x596B000ull +#define NIC10_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC10_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC10_MAC_GLOB_STAT_RX0_BASE 0x596B100ull +#define NIC10_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX1_BASE 0x596B18Cull +#define NIC10_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX2_BASE 0x596B218ull +#define NIC10_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX3_BASE 0x596B2A4ull +#define NIC10_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_TX0_BASE 0x596B330ull +#define NIC10_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX1_BASE 0x596B398ull +#define NIC10_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX2_BASE 0x596B400ull +#define NIC10_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX3_BASE 0x596B468ull +#define NIC10_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC10_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x596B800ull +#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC10_MAC_CH0_MAC_PCS_BASE 0x596C000ull +#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH0_MAC_128_BASE 0x596C400ull +#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH0_MAC_AN_BASE 0x596C800ull +#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH1_MAC_PCS_BASE 0x596D000ull +#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH1_MAC_128_BASE 0x596D400ull +#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH1_MAC_AN_BASE 0x596D800ull +#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH2_MAC_PCS_BASE 0x596E000ull +#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH2_MAC_128_BASE 0x596E400ull +#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH2_MAC_AN_BASE 0x596E800ull +#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH3_MAC_PCS_BASE 0x596F000ull +#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH3_MAC_128_BASE 0x596F400ull +#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH3_MAC_AN_BASE 0x596F800ull +#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5980000ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5980080ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5980100ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5980180ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_0_SPECIAL_BASE 0x5980E80ull +#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5981000ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5981080ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5981100ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5981180ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_1_SPECIAL_BASE 0x5981E80ull +#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5982000ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5982080ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5982100ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5982180ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_2_SPECIAL_BASE 0x5982E80ull +#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5983000ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5983080ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5983100ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5983180ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_3_SPECIAL_BASE 0x5983E80ull +#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5984000ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5984080ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5984100ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5984180ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_4_SPECIAL_BASE 0x5984E80ull +#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5985000ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5985080ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5985100ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5985180ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_5_SPECIAL_BASE 0x5985E80ull +#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5986000ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5986080ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5986100ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5986180ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_6_SPECIAL_BASE 0x5986E80ull +#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5987000ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5987080ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5987100ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5987180ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_7_SPECIAL_BASE 0x5987E80ull +#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5988000ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5988080ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5988100ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5988180ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_8_SPECIAL_BASE 0x5988E80ull +#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5989000ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5989080ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5989100ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5989180ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_9_SPECIAL_BASE 0x5989E80ull +#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x598A000ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x598A080ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x598A100ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x598A180ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_10_SPECIAL_BASE 0x598AE80ull +#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x598B000ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x598B080ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x598B100ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x598B180ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_11_SPECIAL_BASE 0x598BE80ull +#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x598C000ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x598C080ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x598C100ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x598C180ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_12_SPECIAL_BASE 0x598CE80ull +#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x598D000ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x598D080ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x598D100ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x598D180ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_13_SPECIAL_BASE 0x598DE80ull +#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x598E000ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x598E080ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x598E100ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x598E180ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_14_SPECIAL_BASE 0x598EE80ull +#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM_DCCM0_BASE 0x5990000ull +#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM0_SECTION 0x8000 +#define mmNIC11_QM_ARC_AUX0_BASE 0x5998000ull +#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC11_QM_ARC_AUX0_SPECIAL_BASE 0x5998E80ull +#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM0_BASE 0x599A000ull +#define NIC11_QM0_MAX_OFFSET 0x1000 +#define NIC11_QM0_SECTION 0x9000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x599A900ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x599A908ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x599A910ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x599A918ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x599A920ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x599A928ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x599A930ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x599A938ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x599A940ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x599A948ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x599A950ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x599A958ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x599A960ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x599A968ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x599A970ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x599A978ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC11_QM0_AXUSER_SECURED_BASE 0x599AB00ull +#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC11_QM0_AXUSER_NONSECURED_BASE 0x599AB80ull +#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC11_QM0_DBG_HBW_BASE 0x599AC00ull +#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC11_QM0_DBG_LBW_BASE 0x599AC80ull +#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC11_QM0_CGM_BASE 0x599AD80ull +#define NIC11_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM0_CGM_SECTION 0x1000 +#define mmNIC11_QM0_SPECIAL_BASE 0x599AE80ull +#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC11_QPC0_BASE 0x599F000ull +#define NIC11_QPC0_MAX_OFFSET 0x1000 +#define NIC11_QPC0_SECTION 0x7200 +#define mmNIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x599F720ull +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x599F728ull +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x599F730ull +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x599F738ull +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x599F740ull +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x599F748ull +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x599F750ull +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x599F758ull +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x599F760ull +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x599F768ull +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x599F770ull +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x599F778ull +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x599F780ull +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x599F788ull +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x599F790ull +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x599F798ull +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x599F7A0ull +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x599F7A8ull +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x599F7B0ull +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x599F7B8ull +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x599F7C0ull +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x599F7C8ull +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x599F7D0ull +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x599F7D8ull +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x599F7E0ull +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x599F7E8ull +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x599F7F0ull +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x599F7F8ull +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x599F800ull +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x599F808ull +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x599F810ull +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x599F818ull +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC11_QPC0_AXUSER_CONG_QUE_BASE 0x599FB80ull +#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_RXWQE_BASE 0x599FBE0ull +#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x599FC40ull +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_DB_FIFO_BASE 0x599FCA0ull +#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x599FD00ull +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x599FD60ull +#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_QPC_RESP_BASE 0x599FDC0ull +#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_QPC_REQ_BASE 0x599FE20ull +#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC11_QPC0_SPECIAL_BASE 0x599FE80ull +#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x59A0000ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x59A0080ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x59A0100ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x59A0180ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_0_SPECIAL_BASE 0x59A0E80ull +#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x59A1000ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x59A1080ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x59A1100ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x59A1180ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_1_SPECIAL_BASE 0x59A1E80ull +#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x59A2000ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x59A2080ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x59A2100ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x59A2180ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_2_SPECIAL_BASE 0x59A2E80ull +#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x59A3000ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x59A3080ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x59A3100ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x59A3180ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_3_SPECIAL_BASE 0x59A3E80ull +#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x59A4000ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x59A4080ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x59A4100ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x59A4180ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_4_SPECIAL_BASE 0x59A4E80ull +#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x59A5000ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x59A5080ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x59A5100ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x59A5180ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_5_SPECIAL_BASE 0x59A5E80ull +#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x59A6000ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x59A6080ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x59A6100ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x59A6180ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_6_SPECIAL_BASE 0x59A6E80ull +#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x59A7000ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x59A7080ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x59A7100ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x59A7180ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_7_SPECIAL_BASE 0x59A7E80ull +#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x59A8000ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x59A8080ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x59A8100ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x59A8180ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_8_SPECIAL_BASE 0x59A8E80ull +#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x59A9000ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x59A9080ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x59A9100ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x59A9180ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_9_SPECIAL_BASE 0x59A9E80ull +#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x59AA000ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x59AA080ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x59AA100ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x59AA180ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_10_SPECIAL_BASE 0x59AAE80ull +#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x59AB000ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x59AB080ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x59AB100ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x59AB180ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_11_SPECIAL_BASE 0x59ABE80ull +#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x59AC000ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x59AC080ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x59AC100ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x59AC180ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_12_SPECIAL_BASE 0x59ACE80ull +#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x59AD000ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x59AD080ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x59AD100ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x59AD180ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_13_SPECIAL_BASE 0x59ADE80ull +#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x59AE000ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x59AE080ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x59AE100ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x59AE180ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_14_SPECIAL_BASE 0x59AEE80ull +#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM_DCCM1_BASE 0x59B0000ull +#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM1_SECTION 0x8000 +#define mmNIC11_QM_ARC_AUX1_BASE 0x59B8000ull +#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC11_QM_ARC_AUX1_SPECIAL_BASE 0x59B8E80ull +#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM1_BASE 0x59BA000ull +#define NIC11_QM1_MAX_OFFSET 0x1000 +#define NIC11_QM1_SECTION 0x9000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x59BA900ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x59BA908ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x59BA910ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x59BA918ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x59BA920ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x59BA928ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x59BA930ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x59BA938ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x59BA940ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x59BA948ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x59BA950ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x59BA958ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x59BA960ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x59BA968ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x59BA970ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x59BA978ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC11_QM1_AXUSER_SECURED_BASE 0x59BAB00ull +#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC11_QM1_AXUSER_NONSECURED_BASE 0x59BAB80ull +#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC11_QM1_DBG_HBW_BASE 0x59BAC00ull +#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC11_QM1_DBG_LBW_BASE 0x59BAC80ull +#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC11_QM1_CGM_BASE 0x59BAD80ull +#define NIC11_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM1_CGM_SECTION 0x1000 +#define mmNIC11_QM1_SPECIAL_BASE 0x59BAE80ull +#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC11_QPC1_BASE 0x59BF000ull +#define NIC11_QPC1_MAX_OFFSET 0x1000 +#define NIC11_QPC1_SECTION 0x7200 +#define mmNIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x59BF720ull +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x59BF728ull +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x59BF730ull +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x59BF738ull +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x59BF740ull +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x59BF748ull +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x59BF750ull +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x59BF758ull +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x59BF760ull +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x59BF768ull +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x59BF770ull +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x59BF778ull +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x59BF780ull +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x59BF788ull +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x59BF790ull +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x59BF798ull +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x59BF7A0ull +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x59BF7A8ull +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x59BF7B0ull +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x59BF7B8ull +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x59BF7C0ull +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x59BF7C8ull +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x59BF7D0ull +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x59BF7D8ull +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x59BF7E0ull +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x59BF7E8ull +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x59BF7F0ull +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x59BF7F8ull +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x59BF800ull +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x59BF808ull +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x59BF810ull +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x59BF818ull +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC11_QPC1_AXUSER_CONG_QUE_BASE 0x59BFB80ull +#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_RXWQE_BASE 0x59BFBE0ull +#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x59BFC40ull +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_DB_FIFO_BASE 0x59BFCA0ull +#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x59BFD00ull +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x59BFD60ull +#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_QPC_RESP_BASE 0x59BFDC0ull +#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_QPC_REQ_BASE 0x59BFE20ull +#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC11_QPC1_SPECIAL_BASE 0x59BFE80ull +#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC11_TMR_BASE 0x59C8000ull +#define NIC11_TMR_MAX_OFFSET 0x1000 +#define NIC11_TMR_SECTION 0xD600 +#define mmNIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x59C8D60ull +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC11_TMR_AXUSER_TMR_FIFO_BASE 0x59C8DC0ull +#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC11_TMR_AXUSER_TMR_FSM_BASE 0x59C8E20ull +#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC11_TMR_SPECIAL_BASE 0x59C8E80ull +#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXB_CORE_BASE 0x59C9000ull +#define NIC11_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC11_RXB_CORE_SECTION 0x6100 +#define mmNIC11_RXB_CORE_SCT_AWUSER_BASE 0x59C9610ull +#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC11_RXB_CORE_SPECIAL_BASE 0x59C9E80ull +#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE0_BASE 0x59CA000ull +#define NIC11_RXE0_MAX_OFFSET 0x1000 +#define NIC11_RXE0_SECTION 0x9000 +#define mmNIC11_RXE0_WQE_ARUSER_BASE 0x59CA900ull +#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC11_RXE0_SPECIAL_BASE 0x59CAE80ull +#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE1_BASE 0x59CB000ull +#define NIC11_RXE1_MAX_OFFSET 0x1000 +#define NIC11_RXE1_SECTION 0x9000 +#define mmNIC11_RXE1_WQE_ARUSER_BASE 0x59CB900ull +#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC11_RXE1_SPECIAL_BASE 0x59CBE80ull +#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x59CC000ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x59CC050ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x59CC0A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x59CC0F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x59CC140ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x59CC190ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x59CC1E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x59CC230ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x59CC280ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x59CC2D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x59CC320ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x59CC370ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x59CC3C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x59CC410ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x59CC460ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x59CC4B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x59CC500ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x59CC550ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x59CC5A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x59CC5F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x59CC640ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x59CC690ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x59CC6E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x59CC730ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x59CC780ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x59CC7D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x59CC820ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x59CC870ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x59CC8C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x59CC910ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x59CC960ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x59CC9B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC11_RXE0_AXUSER_SPECIAL_BASE 0x59CCE80ull +#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x59CD000ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x59CD050ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x59CD0A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x59CD0F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x59CD140ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x59CD190ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x59CD1E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x59CD230ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x59CD280ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x59CD2D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x59CD320ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x59CD370ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x59CD3C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x59CD410ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x59CD460ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x59CD4B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x59CD500ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x59CD550ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x59CD5A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x59CD5F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x59CD640ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x59CD690ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x59CD6E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x59CD730ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x59CD780ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x59CD7D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x59CD820ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x59CD870ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x59CD8C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x59CD910ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x59CD960ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x59CD9B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC11_RXE1_AXUSER_SPECIAL_BASE 0x59CDE80ull +#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC11_TXS0_BASE 0x59D0000ull +#define NIC11_TXS0_MAX_OFFSET 0x1000 +#define NIC11_TXS0_SECTION 0xE800 +#define mmNIC11_TXS0_SPECIAL_BASE 0x59D0E80ull +#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXS1_BASE 0x59D1000ull +#define NIC11_TXS1_MAX_OFFSET 0x1000 +#define NIC11_TXS1_SECTION 0xE800 +#define mmNIC11_TXS1_SPECIAL_BASE 0x59D1E80ull +#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXE0_BASE 0x59D2000ull +#define NIC11_TXE0_MAX_OFFSET 0x1000 +#define NIC11_TXE0_SECTION 0xE800 +#define mmNIC11_TXE0_SPECIAL_BASE 0x59D2E80ull +#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXE1_BASE 0x59D3000ull +#define NIC11_TXE1_MAX_OFFSET 0x1000 +#define NIC11_TXE1_SECTION 0xE800 +#define mmNIC11_TXE1_SPECIAL_BASE 0x59D3E80ull +#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXB_BASE 0x59D4000ull +#define NIC11_TXB_MAX_OFFSET 0x1000 +#define NIC11_TXB_SECTION 0xE800 +#define mmNIC11_TXB_SPECIAL_BASE 0x59D4E80ull +#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x59D5000ull +#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x59D5200ull +#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x59D5400ull +#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x59D5600ull +#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_E2E_CRDT_BASE 0x59D5800ull +#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC11_MSTR_IF_AXUSER_BASE 0x59D5A80ull +#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC11_MSTR_IF_DBG_HBW_BASE 0x59D5B00ull +#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC11_MSTR_IF_DBG_LBW_BASE 0x59D5B80ull +#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC11_MSTR_IF_CORE_HBW_BASE 0x59D5C00ull +#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC11_MSTR_IF_CORE_LBW_BASE 0x59D5D80ull +#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC11_MSTR_IF_SPECIAL_BASE 0x59D5E80ull +#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC11_TX_AXUSER_BASE 0x59D6000ull +#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_TX_AXUSER_SECTION 0x2000 +#define mmNIC11_SERDES0_BASE 0x59D8000ull +#define NIC11_SERDES0_MAX_OFFSET 0x3E40 +#define NIC11_SERDES0_SECTION 0x4000 +#define mmNIC11_SERDES1_BASE 0x59DC000ull +#define NIC11_SERDES1_MAX_OFFSET 0x3E40 +#define NIC11_SERDES1_SECTION 0x4000 +#define mmNIC11_PHY_BASE 0x59E0000ull +#define NIC11_PHY_MAX_OFFSET 0x1000 +#define NIC11_PHY_SECTION 0xE800 +#define mmNIC11_PHY_SPECIAL_BASE 0x59E0E80ull +#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT11_MAC_AUX_BASE 0x59E8000ull +#define PRT11_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT11_MAC_AUX_SECTION 0xE800 +#define mmPRT11_MAC_AUX_SPECIAL_BASE 0x59E8E80ull +#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT11_MAC_CORE_BASE 0x59E9000ull +#define PRT11_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT11_MAC_CORE_SECTION 0xE800 +#define mmPRT11_MAC_CORE_SPECIAL_BASE 0x59E9E80ull +#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC11_MAC_RS_FEC_BASE 0x59EA000ull +#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC11_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC11_MAC_GLOB_STAT_CONTROL_REG_BASE 0x59EB000ull +#define NIC11_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC11_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC11_MAC_GLOB_STAT_RX0_BASE 0x59EB100ull +#define NIC11_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX1_BASE 0x59EB18Cull +#define NIC11_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX2_BASE 0x59EB218ull +#define NIC11_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX3_BASE 0x59EB2A4ull +#define NIC11_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_TX0_BASE 0x59EB330ull +#define NIC11_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX1_BASE 0x59EB398ull +#define NIC11_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX2_BASE 0x59EB400ull +#define NIC11_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX3_BASE 0x59EB468ull +#define NIC11_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC11_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x59EB800ull +#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC11_MAC_CH0_MAC_PCS_BASE 0x59EC000ull +#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH0_MAC_128_BASE 0x59EC400ull +#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH0_MAC_AN_BASE 0x59EC800ull +#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH1_MAC_PCS_BASE 0x59ED000ull +#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH1_MAC_128_BASE 0x59ED400ull +#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH1_MAC_AN_BASE 0x59ED800ull +#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH2_MAC_PCS_BASE 0x59EE000ull +#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH2_MAC_128_BASE 0x59EE400ull +#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH2_MAC_AN_BASE 0x59EE800ull +#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH3_MAC_PCS_BASE 0x59EF000ull +#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH3_MAC_128_BASE 0x59EF400ull +#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH3_MAC_AN_BASE 0x59EF800ull +#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800 +#define mmDCORE0_ROM_TABLE_L_BASE 0x6000000ull +#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE0_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE0_HMMU0_CS_ROM_TBL_BASE 0x6080000ull +#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_STM_BASE 0x6081000ull +#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_CTI_BASE 0x6082000ull +#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_ETF_BASE 0x6083000ull +#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_SPMU_BASE 0x6084000ull +#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_CTI_BASE 0x6085000ull +#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_USER_CTI_BASE 0x6086000ull +#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_0_BASE 0x6087000ull +#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_1_BASE 0x6088000ull +#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_3_BASE 0x6089000ull +#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_2_BASE 0x608A000ull +#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_4_BASE 0x608B000ull +#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU1_CS_ROM_TBL_BASE 0x6090000ull +#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_STM_BASE 0x6091000ull +#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_CTI_BASE 0x6092000ull +#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_ETF_BASE 0x6093000ull +#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_SPMU_BASE 0x6094000ull +#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_CTI_BASE 0x6095000ull +#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_USER_CTI_BASE 0x6096000ull +#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_0_BASE 0x6097000ull +#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_1_BASE 0x6098000ull +#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_3_BASE 0x6099000ull +#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_2_BASE 0x609A000ull +#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_4_BASE 0x609B000ull +#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU2_CS_ROM_TBL_BASE 0x60A0000ull +#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_STM_BASE 0x60A1000ull +#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_CTI_BASE 0x60A2000ull +#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_ETF_BASE 0x60A3000ull +#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_SPMU_BASE 0x60A4000ull +#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_CTI_BASE 0x60A5000ull +#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_USER_CTI_BASE 0x60A6000ull +#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_0_BASE 0x60A7000ull +#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_1_BASE 0x60A8000ull +#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_3_BASE 0x60A9000ull +#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_2_BASE 0x60AA000ull +#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_4_BASE 0x60AB000ull +#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU3_CS_ROM_TBL_BASE 0x60B0000ull +#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_STM_BASE 0x60B1000ull +#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_CTI_BASE 0x60B2000ull +#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_ETF_BASE 0x60B3000ull +#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_SPMU_BASE 0x60B4000ull +#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_CTI_BASE 0x60B5000ull +#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_USER_CTI_BASE 0x60B6000ull +#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_0_BASE 0x60B7000ull +#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_1_BASE 0x60B8000ull +#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_3_BASE 0x60B9000ull +#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_2_BASE 0x60BA000ull +#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_4_BASE 0x60BB000ull +#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE0_MME_CTRL_ROM_TABLE_BASE 0x60C0000ull +#define DCORE0_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_STM_BASE 0x60C1000ull +#define DCORE0_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI_BASE 0x60C2000ull +#define DCORE0_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_ETF_BASE 0x60C3000ull +#define DCORE0_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_SPMU_BASE 0x60C4000ull +#define DCORE0_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI0_BASE 0x60C5000ull +#define DCORE0_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI1_BASE 0x60C6000ull +#define DCORE0_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON0_BASE 0x60C7000ull +#define DCORE0_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON1_BASE 0x60C8000ull +#define DCORE0_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON2_BASE 0x60C9000ull +#define DCORE0_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON3_BASE 0x60CA000ull +#define DCORE0_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_ARC_RTT_BASE 0x60CB000ull +#define DCORE0_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE0_MME_SBTE0_ROM_TBL_BASE 0x60D0000ull +#define DCORE0_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_STM_BASE 0x60D1000ull +#define DCORE0_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI_BASE 0x60D2000ull +#define DCORE0_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_ETF_BASE 0x60D3000ull +#define DCORE0_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_SPMU_BASE 0x60D4000ull +#define DCORE0_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI0_BASE 0x60D5000ull +#define DCORE0_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI1_BASE 0x60D6000ull +#define DCORE0_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_BMON0_BASE 0x60D7000ull +#define DCORE0_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_ROM_TBL_BASE 0x60D8000ull +#define DCORE0_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_STM_BASE 0x60D9000ull +#define DCORE0_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI_BASE 0x60DA000ull +#define DCORE0_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_ETF_BASE 0x60DB000ull +#define DCORE0_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_SPMU_BASE 0x60DC000ull +#define DCORE0_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI0_BASE 0x60DD000ull +#define DCORE0_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI1_BASE 0x60DE000ull +#define DCORE0_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_BMON0_BASE 0x60DF000ull +#define DCORE0_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_ROM_TBL_BASE 0x60E0000ull +#define DCORE0_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_STM_BASE 0x60E1000ull +#define DCORE0_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI_BASE 0x60E2000ull +#define DCORE0_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_ETF_BASE 0x60E3000ull +#define DCORE0_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_SPMU_BASE 0x60E4000ull +#define DCORE0_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI0_BASE 0x60E5000ull +#define DCORE0_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI1_BASE 0x60E6000ull +#define DCORE0_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_BMON0_BASE 0x60E7000ull +#define DCORE0_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_ROM_TBL_BASE 0x60E8000ull +#define DCORE0_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_STM_BASE 0x60E9000ull +#define DCORE0_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI_BASE 0x60EA000ull +#define DCORE0_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_ETF_BASE 0x60EB000ull +#define DCORE0_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_SPMU_BASE 0x60EC000ull +#define DCORE0_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI0_BASE 0x60ED000ull +#define DCORE0_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI1_BASE 0x60EE000ull +#define DCORE0_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_BMON0_BASE 0x60EF000ull +#define DCORE0_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_ROM_TBL_BASE 0x60F0000ull +#define DCORE0_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_STM_BASE 0x60F1000ull +#define DCORE0_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI_BASE 0x60F2000ull +#define DCORE0_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_ETF_BASE 0x60F3000ull +#define DCORE0_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_SPMU_BASE 0x60F4000ull +#define DCORE0_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI0_BASE 0x60F5000ull +#define DCORE0_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI1_BASE 0x60F6000ull +#define DCORE0_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_BMON0_BASE 0x60F7000ull +#define DCORE0_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE0_MME_ACC_CS_ROM_TBL_BASE 0x6100000ull +#define DCORE0_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_ACC_STM_BASE 0x6101000ull +#define DCORE0_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI_BASE 0x6102000ull +#define DCORE0_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE0_MME_ACC_ETF_BASE 0x6103000ull +#define DCORE0_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE0_MME_ACC_SPMU_BASE 0x6104000ull +#define DCORE0_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI0_BASE 0x6105000ull +#define DCORE0_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI1_BASE 0x6106000ull +#define DCORE0_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_ACC_BMON0_BASE 0x6107000ull +#define DCORE0_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_ACC_BMON1_BASE 0x6108000ull +#define DCORE0_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE0_SM_CS_DBG_ROM_TBL_BASE 0x6110000ull +#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_SM_STM_BASE 0x6111000ull +#define DCORE0_SM_STM_MAX_OFFSET 0x1000 +#define DCORE0_SM_STM_SECTION 0x1000 +#define mmDCORE0_SM_CTI_BASE 0x6112000ull +#define DCORE0_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_CTI_SECTION 0x1000 +#define mmDCORE0_SM_ETF_BASE 0x6113000ull +#define DCORE0_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE0_SM_ETF_SECTION 0x1000 +#define mmDCORE0_SM_SPMU_BASE 0x6114000ull +#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_SM_SPMU_SECTION 0x1000 +#define mmDCORE0_SM_BMON_CTI_BASE 0x6115000ull +#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_SM_USER_CTI_BASE 0x6116000ull +#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE0_SM_BMON_BASE 0x6117000ull +#define DCORE0_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_SECTION 0x1000 +#define mmDCORE0_SM_BMON1_BASE 0x6118000ull +#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON1_SECTION 0x18000 +#define mmDCORE0_XFT_FUNNEL_BASE 0x6130000ull +#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE0_TFT0_FUNNEL_BASE 0x6138000ull +#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TFT1_FUNNEL_BASE 0x6139000ull +#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TFT2_FUNNEL_BASE 0x613A000ull +#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE0_RTR0_FUNNEL_BASE 0x6141000ull +#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR1_FUNNEL_BASE 0x6149000ull +#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR2_FUNNEL_BASE 0x6151000ull +#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR3_FUNNEL_BASE 0x6159000ull +#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR4_FUNNEL_BASE 0x6161000ull +#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF0_FUNNEL_BASE 0x6165000ull +#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR5_FUNNEL_BASE 0x6169000ull +#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF1_FUNNEL_BASE 0x616D000ull +#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR6_FUNNEL_BASE 0x6171000ull +#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF2_FUNNEL_BASE 0x6175000ull +#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR7_FUNNEL_BASE 0x6179000ull +#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF3_FUNNEL_BASE 0x617D000ull +#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF3_FUNNEL_SECTION 0x43000 +#define mmDCORE0_EDMA0_CS_ROM_TBL_BASE 0x61C0000ull +#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_STM_BASE 0x61C1000ull +#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_CTI_BASE 0x61C2000ull +#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_ETF_BASE 0x61C3000ull +#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_SPMU_BASE 0x61C4000ull +#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_CTI_BASE 0x61C5000ull +#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_USER_CTI_BASE 0x61C6000ull +#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_0_BASE 0x61C7000ull +#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_1_BASE 0x61C8000ull +#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_ARC_RTT_BASE 0x61C9000ull +#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE0_EDMA1_CS_ROM_TBL_BASE 0x61D0000ull +#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_STM_BASE 0x61D1000ull +#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_CTI_BASE 0x61D2000ull +#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_ETF_BASE 0x61D3000ull +#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_SPMU_BASE 0x61D4000ull +#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_CTI_BASE 0x61D5000ull +#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_USER_CTI_BASE 0x61D6000ull +#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_0_BASE 0x61D7000ull +#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_1_BASE 0x61D8000ull +#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_ARC_RTT_BASE 0x61D9000ull +#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE0_VDEC0_CS_ROM_TBL_BASE 0x61E0000ull +#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_STM_BASE 0x61E1000ull +#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_CTI_BASE 0x61E2000ull +#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_ETF_BASE 0x61E3000ull +#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_SPMU_BASE 0x61E4000ull +#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_CTI_BASE 0x61E5000ull +#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_USER_CTI_BASE 0x61E6000ull +#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_0_BASE 0x61E7000ull +#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_1_BASE 0x61E8000ull +#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_2_BASE 0x61E9000ull +#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE0_VDEC1_CS_ROM_TBL_BASE 0x61F0000ull +#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_STM_BASE 0x61F1000ull +#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_CTI_BASE 0x61F2000ull +#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_ETF_BASE 0x61F3000ull +#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_SPMU_BASE 0x61F4000ull +#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_CTI_BASE 0x61F5000ull +#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_USER_CTI_BASE 0x61F6000ull +#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_0_BASE 0x61F7000ull +#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_1_BASE 0x61F8000ull +#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_2_BASE 0x61F9000ull +#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE1_ROM_TABLE_L_BASE 0x6200000ull +#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE1_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE1_HMMU0_CS_ROM_TBL_BASE 0x6280000ull +#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_STM_BASE 0x6281000ull +#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_CTI_BASE 0x6282000ull +#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_ETF_BASE 0x6283000ull +#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_SPMU_BASE 0x6284000ull +#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_CTI_BASE 0x6285000ull +#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_USER_CTI_BASE 0x6286000ull +#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_0_BASE 0x6287000ull +#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_1_BASE 0x6288000ull +#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_3_BASE 0x6289000ull +#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_2_BASE 0x628A000ull +#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_4_BASE 0x628B000ull +#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU1_CS_ROM_TBL_BASE 0x6290000ull +#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_STM_BASE 0x6291000ull +#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_CTI_BASE 0x6292000ull +#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_ETF_BASE 0x6293000ull +#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_SPMU_BASE 0x6294000ull +#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_CTI_BASE 0x6295000ull +#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_USER_CTI_BASE 0x6296000ull +#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_0_BASE 0x6297000ull +#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_1_BASE 0x6298000ull +#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_3_BASE 0x6299000ull +#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_2_BASE 0x629A000ull +#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_4_BASE 0x629B000ull +#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU2_CS_ROM_TBL_BASE 0x62A0000ull +#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_STM_BASE 0x62A1000ull +#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_CTI_BASE 0x62A2000ull +#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_ETF_BASE 0x62A3000ull +#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_SPMU_BASE 0x62A4000ull +#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_CTI_BASE 0x62A5000ull +#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_USER_CTI_BASE 0x62A6000ull +#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_0_BASE 0x62A7000ull +#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_1_BASE 0x62A8000ull +#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_3_BASE 0x62A9000ull +#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_2_BASE 0x62AA000ull +#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_4_BASE 0x62AB000ull +#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU3_CS_ROM_TBL_BASE 0x62B0000ull +#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_STM_BASE 0x62B1000ull +#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_CTI_BASE 0x62B2000ull +#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_ETF_BASE 0x62B3000ull +#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_SPMU_BASE 0x62B4000ull +#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_CTI_BASE 0x62B5000ull +#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_USER_CTI_BASE 0x62B6000ull +#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_0_BASE 0x62B7000ull +#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_1_BASE 0x62B8000ull +#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_3_BASE 0x62B9000ull +#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_2_BASE 0x62BA000ull +#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_4_BASE 0x62BB000ull +#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE1_MME_CTRL_ROM_TABLE_BASE 0x62C0000ull +#define DCORE1_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_STM_BASE 0x62C1000ull +#define DCORE1_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI_BASE 0x62C2000ull +#define DCORE1_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_ETF_BASE 0x62C3000ull +#define DCORE1_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_SPMU_BASE 0x62C4000ull +#define DCORE1_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI0_BASE 0x62C5000ull +#define DCORE1_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI1_BASE 0x62C6000ull +#define DCORE1_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON0_BASE 0x62C7000ull +#define DCORE1_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON1_BASE 0x62C8000ull +#define DCORE1_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON2_BASE 0x62C9000ull +#define DCORE1_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON3_BASE 0x62CA000ull +#define DCORE1_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_ARC_RTT_BASE 0x62CB000ull +#define DCORE1_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE1_MME_SBTE0_ROM_TBL_BASE 0x62D0000ull +#define DCORE1_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_STM_BASE 0x62D1000ull +#define DCORE1_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI_BASE 0x62D2000ull +#define DCORE1_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_ETF_BASE 0x62D3000ull +#define DCORE1_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_SPMU_BASE 0x62D4000ull +#define DCORE1_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI0_BASE 0x62D5000ull +#define DCORE1_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI1_BASE 0x62D6000ull +#define DCORE1_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_BMON0_BASE 0x62D7000ull +#define DCORE1_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_ROM_TBL_BASE 0x62D8000ull +#define DCORE1_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_STM_BASE 0x62D9000ull +#define DCORE1_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI_BASE 0x62DA000ull +#define DCORE1_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_ETF_BASE 0x62DB000ull +#define DCORE1_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_SPMU_BASE 0x62DC000ull +#define DCORE1_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI0_BASE 0x62DD000ull +#define DCORE1_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI1_BASE 0x62DE000ull +#define DCORE1_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_BMON0_BASE 0x62DF000ull +#define DCORE1_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_ROM_TBL_BASE 0x62E0000ull +#define DCORE1_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_STM_BASE 0x62E1000ull +#define DCORE1_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI_BASE 0x62E2000ull +#define DCORE1_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_ETF_BASE 0x62E3000ull +#define DCORE1_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_SPMU_BASE 0x62E4000ull +#define DCORE1_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI0_BASE 0x62E5000ull +#define DCORE1_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI1_BASE 0x62E6000ull +#define DCORE1_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_BMON0_BASE 0x62E7000ull +#define DCORE1_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_ROM_TBL_BASE 0x62E8000ull +#define DCORE1_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_STM_BASE 0x62E9000ull +#define DCORE1_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI_BASE 0x62EA000ull +#define DCORE1_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_ETF_BASE 0x62EB000ull +#define DCORE1_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_SPMU_BASE 0x62EC000ull +#define DCORE1_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI0_BASE 0x62ED000ull +#define DCORE1_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI1_BASE 0x62EE000ull +#define DCORE1_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_BMON0_BASE 0x62EF000ull +#define DCORE1_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_ROM_TBL_BASE 0x62F0000ull +#define DCORE1_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_STM_BASE 0x62F1000ull +#define DCORE1_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI_BASE 0x62F2000ull +#define DCORE1_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_ETF_BASE 0x62F3000ull +#define DCORE1_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_SPMU_BASE 0x62F4000ull +#define DCORE1_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI0_BASE 0x62F5000ull +#define DCORE1_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI1_BASE 0x62F6000ull +#define DCORE1_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_BMON0_BASE 0x62F7000ull +#define DCORE1_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE1_MME_ACC_CS_ROM_TBL_BASE 0x6300000ull +#define DCORE1_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_ACC_STM_BASE 0x6301000ull +#define DCORE1_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI_BASE 0x6302000ull +#define DCORE1_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE1_MME_ACC_ETF_BASE 0x6303000ull +#define DCORE1_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE1_MME_ACC_SPMU_BASE 0x6304000ull +#define DCORE1_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI0_BASE 0x6305000ull +#define DCORE1_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI1_BASE 0x6306000ull +#define DCORE1_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_ACC_BMON0_BASE 0x6307000ull +#define DCORE1_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_ACC_BMON1_BASE 0x6308000ull +#define DCORE1_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE1_SM_CS_DBG_ROM_TBL_BASE 0x6310000ull +#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_SM_STM_BASE 0x6311000ull +#define DCORE1_SM_STM_MAX_OFFSET 0x1000 +#define DCORE1_SM_STM_SECTION 0x1000 +#define mmDCORE1_SM_CTI_BASE 0x6312000ull +#define DCORE1_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_CTI_SECTION 0x1000 +#define mmDCORE1_SM_ETF_BASE 0x6313000ull +#define DCORE1_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE1_SM_ETF_SECTION 0x1000 +#define mmDCORE1_SM_SPMU_BASE 0x6314000ull +#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_SM_SPMU_SECTION 0x1000 +#define mmDCORE1_SM_BMON_CTI_BASE 0x6315000ull +#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_SM_USER_CTI_BASE 0x6316000ull +#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE1_SM_BMON_BASE 0x6317000ull +#define DCORE1_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_SECTION 0x1000 +#define mmDCORE1_SM_BMON1_BASE 0x6318000ull +#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON1_SECTION 0x18000 +#define mmDCORE1_XFT_FUNNEL_BASE 0x6330000ull +#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE1_TFT0_FUNNEL_BASE 0x6338000ull +#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TFT1_FUNNEL_BASE 0x6339000ull +#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TFT2_FUNNEL_BASE 0x633A000ull +#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE1_RTR0_FUNNEL_BASE 0x6341000ull +#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF0_FUNNEL_BASE 0x6345000ull +#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR1_FUNNEL_BASE 0x6349000ull +#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF1_FUNNEL_BASE 0x634D000ull +#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR2_FUNNEL_BASE 0x6351000ull +#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF2_FUNNEL_BASE 0x6355000ull +#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR3_FUNNEL_BASE 0x6359000ull +#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF3_FUNNEL_BASE 0x635D000ull +#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF3_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR4_FUNNEL_BASE 0x6361000ull +#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR5_FUNNEL_BASE 0x6369000ull +#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR6_FUNNEL_BASE 0x6371000ull +#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR7_FUNNEL_BASE 0x6379000ull +#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_FUNNEL_SECTION 0x47000 +#define mmDCORE1_EDMA0_CS_ROM_TBL_BASE 0x63C0000ull +#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_STM_BASE 0x63C1000ull +#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_CTI_BASE 0x63C2000ull +#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_ETF_BASE 0x63C3000ull +#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_SPMU_BASE 0x63C4000ull +#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_CTI_BASE 0x63C5000ull +#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_USER_CTI_BASE 0x63C6000ull +#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_0_BASE 0x63C7000ull +#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_1_BASE 0x63C8000ull +#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_ARC_RTT_BASE 0x63C9000ull +#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE1_EDMA1_CS_ROM_TBL_BASE 0x63D0000ull +#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_STM_BASE 0x63D1000ull +#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_CTI_BASE 0x63D2000ull +#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_ETF_BASE 0x63D3000ull +#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_SPMU_BASE 0x63D4000ull +#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_CTI_BASE 0x63D5000ull +#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_USER_CTI_BASE 0x63D6000ull +#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_0_BASE 0x63D7000ull +#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_1_BASE 0x63D8000ull +#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_ARC_RTT_BASE 0x63D9000ull +#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE1_VDEC0_CS_ROM_TBL_BASE 0x63E0000ull +#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_STM_BASE 0x63E1000ull +#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_CTI_BASE 0x63E2000ull +#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_ETF_BASE 0x63E3000ull +#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_SPMU_BASE 0x63E4000ull +#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_CTI_BASE 0x63E5000ull +#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_USER_CTI_BASE 0x63E6000ull +#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_0_BASE 0x63E7000ull +#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_1_BASE 0x63E8000ull +#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_2_BASE 0x63E9000ull +#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE1_VDEC1_CS_ROM_TBL_BASE 0x63F0000ull +#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_STM_BASE 0x63F1000ull +#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_CTI_BASE 0x63F2000ull +#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_ETF_BASE 0x63F3000ull +#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_SPMU_BASE 0x63F4000ull +#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_CTI_BASE 0x63F5000ull +#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_USER_CTI_BASE 0x63F6000ull +#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_0_BASE 0x63F7000ull +#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_1_BASE 0x63F8000ull +#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_2_BASE 0x63F9000ull +#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE2_ROM_TABLE_L_BASE 0x6400000ull +#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE2_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE2_HMMU0_CS_ROM_TBL_BASE 0x6480000ull +#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_STM_BASE 0x6481000ull +#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_CTI_BASE 0x6482000ull +#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_ETF_BASE 0x6483000ull +#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_SPMU_BASE 0x6484000ull +#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_CTI_BASE 0x6485000ull +#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_USER_CTI_BASE 0x6486000ull +#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_0_BASE 0x6487000ull +#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_1_BASE 0x6488000ull +#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_3_BASE 0x6489000ull +#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_2_BASE 0x648A000ull +#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_4_BASE 0x648B000ull +#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU1_CS_ROM_TBL_BASE 0x6490000ull +#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_STM_BASE 0x6491000ull +#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_CTI_BASE 0x6492000ull +#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_ETF_BASE 0x6493000ull +#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_SPMU_BASE 0x6494000ull +#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_CTI_BASE 0x6495000ull +#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_USER_CTI_BASE 0x6496000ull +#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_0_BASE 0x6497000ull +#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_1_BASE 0x6498000ull +#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_3_BASE 0x6499000ull +#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_2_BASE 0x649A000ull +#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_4_BASE 0x649B000ull +#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU2_CS_ROM_TBL_BASE 0x64A0000ull +#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_STM_BASE 0x64A1000ull +#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_CTI_BASE 0x64A2000ull +#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_ETF_BASE 0x64A3000ull +#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_SPMU_BASE 0x64A4000ull +#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_CTI_BASE 0x64A5000ull +#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_USER_CTI_BASE 0x64A6000ull +#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_0_BASE 0x64A7000ull +#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_1_BASE 0x64A8000ull +#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_3_BASE 0x64A9000ull +#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_2_BASE 0x64AA000ull +#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_4_BASE 0x64AB000ull +#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU3_CS_ROM_TBL_BASE 0x64B0000ull +#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_STM_BASE 0x64B1000ull +#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_CTI_BASE 0x64B2000ull +#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_ETF_BASE 0x64B3000ull +#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_SPMU_BASE 0x64B4000ull +#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_CTI_BASE 0x64B5000ull +#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_USER_CTI_BASE 0x64B6000ull +#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_0_BASE 0x64B7000ull +#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_1_BASE 0x64B8000ull +#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_3_BASE 0x64B9000ull +#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_2_BASE 0x64BA000ull +#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_4_BASE 0x64BB000ull +#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE2_MME_CTRL_ROM_TABLE_BASE 0x64C0000ull +#define DCORE2_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_STM_BASE 0x64C1000ull +#define DCORE2_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI_BASE 0x64C2000ull +#define DCORE2_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_ETF_BASE 0x64C3000ull +#define DCORE2_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_SPMU_BASE 0x64C4000ull +#define DCORE2_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI0_BASE 0x64C5000ull +#define DCORE2_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI1_BASE 0x64C6000ull +#define DCORE2_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON0_BASE 0x64C7000ull +#define DCORE2_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON1_BASE 0x64C8000ull +#define DCORE2_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON2_BASE 0x64C9000ull +#define DCORE2_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON3_BASE 0x64CA000ull +#define DCORE2_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_ARC_RTT_BASE 0x64CB000ull +#define DCORE2_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE2_MME_SBTE0_ROM_TBL_BASE 0x64D0000ull +#define DCORE2_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_STM_BASE 0x64D1000ull +#define DCORE2_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI_BASE 0x64D2000ull +#define DCORE2_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_ETF_BASE 0x64D3000ull +#define DCORE2_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_SPMU_BASE 0x64D4000ull +#define DCORE2_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI0_BASE 0x64D5000ull +#define DCORE2_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI1_BASE 0x64D6000ull +#define DCORE2_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_BMON0_BASE 0x64D7000ull +#define DCORE2_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_ROM_TBL_BASE 0x64D8000ull +#define DCORE2_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_STM_BASE 0x64D9000ull +#define DCORE2_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI_BASE 0x64DA000ull +#define DCORE2_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_ETF_BASE 0x64DB000ull +#define DCORE2_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_SPMU_BASE 0x64DC000ull +#define DCORE2_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI0_BASE 0x64DD000ull +#define DCORE2_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI1_BASE 0x64DE000ull +#define DCORE2_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_BMON0_BASE 0x64DF000ull +#define DCORE2_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_ROM_TBL_BASE 0x64E0000ull +#define DCORE2_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_STM_BASE 0x64E1000ull +#define DCORE2_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI_BASE 0x64E2000ull +#define DCORE2_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_ETF_BASE 0x64E3000ull +#define DCORE2_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_SPMU_BASE 0x64E4000ull +#define DCORE2_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI0_BASE 0x64E5000ull +#define DCORE2_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI1_BASE 0x64E6000ull +#define DCORE2_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_BMON0_BASE 0x64E7000ull +#define DCORE2_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_ROM_TBL_BASE 0x64E8000ull +#define DCORE2_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_STM_BASE 0x64E9000ull +#define DCORE2_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI_BASE 0x64EA000ull +#define DCORE2_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_ETF_BASE 0x64EB000ull +#define DCORE2_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_SPMU_BASE 0x64EC000ull +#define DCORE2_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI0_BASE 0x64ED000ull +#define DCORE2_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI1_BASE 0x64EE000ull +#define DCORE2_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_BMON0_BASE 0x64EF000ull +#define DCORE2_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_ROM_TBL_BASE 0x64F0000ull +#define DCORE2_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_STM_BASE 0x64F1000ull +#define DCORE2_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI_BASE 0x64F2000ull +#define DCORE2_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_ETF_BASE 0x64F3000ull +#define DCORE2_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_SPMU_BASE 0x64F4000ull +#define DCORE2_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI0_BASE 0x64F5000ull +#define DCORE2_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI1_BASE 0x64F6000ull +#define DCORE2_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_BMON0_BASE 0x64F7000ull +#define DCORE2_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE2_MME_ACC_CS_ROM_TBL_BASE 0x6500000ull +#define DCORE2_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_ACC_STM_BASE 0x6501000ull +#define DCORE2_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI_BASE 0x6502000ull +#define DCORE2_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE2_MME_ACC_ETF_BASE 0x6503000ull +#define DCORE2_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE2_MME_ACC_SPMU_BASE 0x6504000ull +#define DCORE2_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI0_BASE 0x6505000ull +#define DCORE2_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI1_BASE 0x6506000ull +#define DCORE2_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_ACC_BMON0_BASE 0x6507000ull +#define DCORE2_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_ACC_BMON1_BASE 0x6508000ull +#define DCORE2_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE2_SM_CS_DBG_ROM_TBL_BASE 0x6510000ull +#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_SM_STM_BASE 0x6511000ull +#define DCORE2_SM_STM_MAX_OFFSET 0x1000 +#define DCORE2_SM_STM_SECTION 0x1000 +#define mmDCORE2_SM_CTI_BASE 0x6512000ull +#define DCORE2_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_CTI_SECTION 0x1000 +#define mmDCORE2_SM_ETF_BASE 0x6513000ull +#define DCORE2_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE2_SM_ETF_SECTION 0x1000 +#define mmDCORE2_SM_SPMU_BASE 0x6514000ull +#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_SM_SPMU_SECTION 0x1000 +#define mmDCORE2_SM_BMON_CTI_BASE 0x6515000ull +#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_SM_USER_CTI_BASE 0x6516000ull +#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE2_SM_BMON_BASE 0x6517000ull +#define DCORE2_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_SECTION 0x1000 +#define mmDCORE2_SM_BMON1_BASE 0x6518000ull +#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON1_SECTION 0x18000 +#define mmDCORE2_XFT_FUNNEL_BASE 0x6530000ull +#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE2_TFT0_FUNNEL_BASE 0x6538000ull +#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TFT1_FUNNEL_BASE 0x6539000ull +#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TFT2_FUNNEL_BASE 0x653A000ull +#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE2_RTR0_FUNNEL_BASE 0x6541000ull +#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR1_FUNNEL_BASE 0x6549000ull +#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR2_FUNNEL_BASE 0x6551000ull +#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR3_FUNNEL_BASE 0x6559000ull +#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR4_FUNNEL_BASE 0x6561000ull +#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF0_FUNNEL_BASE 0x6565000ull +#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR5_FUNNEL_BASE 0x6569000ull +#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF1_FUNNEL_BASE 0x656D000ull +#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR6_FUNNEL_BASE 0x6571000ull +#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF2_FUNNEL_BASE 0x6575000ull +#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR7_FUNNEL_BASE 0x6579000ull +#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF3_FUNNEL_BASE 0x657D000ull +#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF3_FUNNEL_SECTION 0x43000 +#define mmDCORE2_EDMA0_CS_ROM_TBL_BASE 0x65C0000ull +#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_STM_BASE 0x65C1000ull +#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_CTI_BASE 0x65C2000ull +#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_ETF_BASE 0x65C3000ull +#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_SPMU_BASE 0x65C4000ull +#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_CTI_BASE 0x65C5000ull +#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_USER_CTI_BASE 0x65C6000ull +#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_0_BASE 0x65C7000ull +#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_1_BASE 0x65C8000ull +#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_ARC_RTT_BASE 0x65C9000ull +#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE2_EDMA1_CS_ROM_TBL_BASE 0x65D0000ull +#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_STM_BASE 0x65D1000ull +#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_CTI_BASE 0x65D2000ull +#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_ETF_BASE 0x65D3000ull +#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_SPMU_BASE 0x65D4000ull +#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_CTI_BASE 0x65D5000ull +#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_USER_CTI_BASE 0x65D6000ull +#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_0_BASE 0x65D7000ull +#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_1_BASE 0x65D8000ull +#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_ARC_RTT_BASE 0x65D9000ull +#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE2_VDEC0_CS_ROM_TBL_BASE 0x65E0000ull +#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_STM_BASE 0x65E1000ull +#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_CTI_BASE 0x65E2000ull +#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_ETF_BASE 0x65E3000ull +#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_SPMU_BASE 0x65E4000ull +#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_CTI_BASE 0x65E5000ull +#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_USER_CTI_BASE 0x65E6000ull +#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_0_BASE 0x65E7000ull +#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_1_BASE 0x65E8000ull +#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_2_BASE 0x65E9000ull +#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE2_VDEC1_CS_ROM_TBL_BASE 0x65F0000ull +#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_STM_BASE 0x65F1000ull +#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_CTI_BASE 0x65F2000ull +#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_ETF_BASE 0x65F3000ull +#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_SPMU_BASE 0x65F4000ull +#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_CTI_BASE 0x65F5000ull +#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_USER_CTI_BASE 0x65F6000ull +#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_0_BASE 0x65F7000ull +#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_1_BASE 0x65F8000ull +#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_2_BASE 0x65F9000ull +#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE3_ROM_TABLE_L_BASE 0x6600000ull +#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE3_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE3_HMMU0_CS_ROM_TBL_BASE 0x6680000ull +#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_STM_BASE 0x6681000ull +#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_CTI_BASE 0x6682000ull +#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_ETF_BASE 0x6683000ull +#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_SPMU_BASE 0x6684000ull +#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_CTI_BASE 0x6685000ull +#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_USER_CTI_BASE 0x6686000ull +#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_0_BASE 0x6687000ull +#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_1_BASE 0x6688000ull +#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_3_BASE 0x6689000ull +#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_2_BASE 0x668A000ull +#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_4_BASE 0x668B000ull +#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU1_CS_ROM_TBL_BASE 0x6690000ull +#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_STM_BASE 0x6691000ull +#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_CTI_BASE 0x6692000ull +#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_ETF_BASE 0x6693000ull +#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_SPMU_BASE 0x6694000ull +#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_CTI_BASE 0x6695000ull +#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_USER_CTI_BASE 0x6696000ull +#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_0_BASE 0x6697000ull +#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_1_BASE 0x6698000ull +#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_3_BASE 0x6699000ull +#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_2_BASE 0x669A000ull +#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_4_BASE 0x669B000ull +#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU2_CS_ROM_TBL_BASE 0x66A0000ull +#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_STM_BASE 0x66A1000ull +#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_CTI_BASE 0x66A2000ull +#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_ETF_BASE 0x66A3000ull +#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_SPMU_BASE 0x66A4000ull +#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_CTI_BASE 0x66A5000ull +#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_USER_CTI_BASE 0x66A6000ull +#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_0_BASE 0x66A7000ull +#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_1_BASE 0x66A8000ull +#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_3_BASE 0x66A9000ull +#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_2_BASE 0x66AA000ull +#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_4_BASE 0x66AB000ull +#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU3_CS_ROM_TBL_BASE 0x66B0000ull +#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_STM_BASE 0x66B1000ull +#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_CTI_BASE 0x66B2000ull +#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_ETF_BASE 0x66B3000ull +#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_SPMU_BASE 0x66B4000ull +#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_CTI_BASE 0x66B5000ull +#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_USER_CTI_BASE 0x66B6000ull +#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_0_BASE 0x66B7000ull +#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_1_BASE 0x66B8000ull +#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_3_BASE 0x66B9000ull +#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_2_BASE 0x66BA000ull +#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_4_BASE 0x66BB000ull +#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE3_MME_CTRL_ROM_TABLE_BASE 0x66C0000ull +#define DCORE3_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_STM_BASE 0x66C1000ull +#define DCORE3_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI_BASE 0x66C2000ull +#define DCORE3_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_ETF_BASE 0x66C3000ull +#define DCORE3_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_SPMU_BASE 0x66C4000ull +#define DCORE3_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI0_BASE 0x66C5000ull +#define DCORE3_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI1_BASE 0x66C6000ull +#define DCORE3_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON0_BASE 0x66C7000ull +#define DCORE3_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON1_BASE 0x66C8000ull +#define DCORE3_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON2_BASE 0x66C9000ull +#define DCORE3_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON3_BASE 0x66CA000ull +#define DCORE3_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_ARC_RTT_BASE 0x66CB000ull +#define DCORE3_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE3_MME_SBTE0_ROM_TBL_BASE 0x66D0000ull +#define DCORE3_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_STM_BASE 0x66D1000ull +#define DCORE3_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI_BASE 0x66D2000ull +#define DCORE3_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_ETF_BASE 0x66D3000ull +#define DCORE3_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_SPMU_BASE 0x66D4000ull +#define DCORE3_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI0_BASE 0x66D5000ull +#define DCORE3_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI1_BASE 0x66D6000ull +#define DCORE3_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_BMON0_BASE 0x66D7000ull +#define DCORE3_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_ROM_TBL_BASE 0x66D8000ull +#define DCORE3_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_STM_BASE 0x66D9000ull +#define DCORE3_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI_BASE 0x66DA000ull +#define DCORE3_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_ETF_BASE 0x66DB000ull +#define DCORE3_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_SPMU_BASE 0x66DC000ull +#define DCORE3_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI0_BASE 0x66DD000ull +#define DCORE3_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI1_BASE 0x66DE000ull +#define DCORE3_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_BMON0_BASE 0x66DF000ull +#define DCORE3_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_ROM_TBL_BASE 0x66E0000ull +#define DCORE3_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_STM_BASE 0x66E1000ull +#define DCORE3_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI_BASE 0x66E2000ull +#define DCORE3_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_ETF_BASE 0x66E3000ull +#define DCORE3_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_SPMU_BASE 0x66E4000ull +#define DCORE3_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI0_BASE 0x66E5000ull +#define DCORE3_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI1_BASE 0x66E6000ull +#define DCORE3_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_BMON0_BASE 0x66E7000ull +#define DCORE3_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_ROM_TBL_BASE 0x66E8000ull +#define DCORE3_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_STM_BASE 0x66E9000ull +#define DCORE3_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI_BASE 0x66EA000ull +#define DCORE3_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_ETF_BASE 0x66EB000ull +#define DCORE3_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_SPMU_BASE 0x66EC000ull +#define DCORE3_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI0_BASE 0x66ED000ull +#define DCORE3_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI1_BASE 0x66EE000ull +#define DCORE3_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_BMON0_BASE 0x66EF000ull +#define DCORE3_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_ROM_TBL_BASE 0x66F0000ull +#define DCORE3_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_STM_BASE 0x66F1000ull +#define DCORE3_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI_BASE 0x66F2000ull +#define DCORE3_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_ETF_BASE 0x66F3000ull +#define DCORE3_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_SPMU_BASE 0x66F4000ull +#define DCORE3_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI0_BASE 0x66F5000ull +#define DCORE3_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI1_BASE 0x66F6000ull +#define DCORE3_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_BMON0_BASE 0x66F7000ull +#define DCORE3_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE3_MME_ACC_CS_ROM_TBL_BASE 0x6700000ull +#define DCORE3_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_ACC_STM_BASE 0x6701000ull +#define DCORE3_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI_BASE 0x6702000ull +#define DCORE3_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE3_MME_ACC_ETF_BASE 0x6703000ull +#define DCORE3_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE3_MME_ACC_SPMU_BASE 0x6704000ull +#define DCORE3_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI0_BASE 0x6705000ull +#define DCORE3_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI1_BASE 0x6706000ull +#define DCORE3_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_ACC_BMON0_BASE 0x6707000ull +#define DCORE3_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_ACC_BMON1_BASE 0x6708000ull +#define DCORE3_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE3_SM_CS_DBG_ROM_TBL_BASE 0x6710000ull +#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_SM_STM_BASE 0x6711000ull +#define DCORE3_SM_STM_MAX_OFFSET 0x1000 +#define DCORE3_SM_STM_SECTION 0x1000 +#define mmDCORE3_SM_CTI_BASE 0x6712000ull +#define DCORE3_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_CTI_SECTION 0x1000 +#define mmDCORE3_SM_ETF_BASE 0x6713000ull +#define DCORE3_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE3_SM_ETF_SECTION 0x1000 +#define mmDCORE3_SM_SPMU_BASE 0x6714000ull +#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_SM_SPMU_SECTION 0x1000 +#define mmDCORE3_SM_BMON_CTI_BASE 0x6715000ull +#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_SM_USER_CTI_BASE 0x6716000ull +#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE3_SM_BMON_BASE 0x6717000ull +#define DCORE3_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_SECTION 0x1000 +#define mmDCORE3_SM_BMON1_BASE 0x6718000ull +#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON1_SECTION 0x18000 +#define mmDCORE3_XFT_FUNNEL_BASE 0x6730000ull +#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE3_TFT0_FUNNEL_BASE 0x6738000ull +#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TFT1_FUNNEL_BASE 0x6739000ull +#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TFT2_FUNNEL_BASE 0x673A000ull +#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE3_RTR0_FUNNEL_BASE 0x6741000ull +#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF0_FUNNEL_BASE 0x6745000ull +#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR1_FUNNEL_BASE 0x6749000ull +#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF1_FUNNEL_BASE 0x674D000ull +#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR2_FUNNEL_BASE 0x6751000ull +#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF2_FUNNEL_BASE 0x6755000ull +#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR3_FUNNEL_BASE 0x6759000ull +#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF3_FUNNEL_BASE 0x675D000ull +#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF3_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR4_FUNNEL_BASE 0x6761000ull +#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR5_FUNNEL_BASE 0x6769000ull +#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR6_FUNNEL_BASE 0x6771000ull +#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR7_FUNNEL_BASE 0x6779000ull +#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_FUNNEL_SECTION 0x47000 +#define mmDCORE3_EDMA0_CS_ROM_TBL_BASE 0x67C0000ull +#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_STM_BASE 0x67C1000ull +#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_CTI_BASE 0x67C2000ull +#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_ETF_BASE 0x67C3000ull +#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_SPMU_BASE 0x67C4000ull +#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_CTI_BASE 0x67C5000ull +#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_USER_CTI_BASE 0x67C6000ull +#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_0_BASE 0x67C7000ull +#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_1_BASE 0x67C8000ull +#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_ARC_RTT_BASE 0x67C9000ull +#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE3_EDMA1_CS_ROM_TBL_BASE 0x67D0000ull +#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_STM_BASE 0x67D1000ull +#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_CTI_BASE 0x67D2000ull +#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_ETF_BASE 0x67D3000ull +#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_SPMU_BASE 0x67D4000ull +#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_CTI_BASE 0x67D5000ull +#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_USER_CTI_BASE 0x67D6000ull +#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_0_BASE 0x67D7000ull +#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_1_BASE 0x67D8000ull +#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_ARC_RTT_BASE 0x67D9000ull +#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE3_VDEC0_CS_ROM_TBL_BASE 0x67E0000ull +#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_STM_BASE 0x67E1000ull +#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_CTI_BASE 0x67E2000ull +#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_ETF_BASE 0x67E3000ull +#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_SPMU_BASE 0x67E4000ull +#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_CTI_BASE 0x67E5000ull +#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_USER_CTI_BASE 0x67E6000ull +#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_0_BASE 0x67E7000ull +#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_1_BASE 0x67E8000ull +#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_2_BASE 0x67E9000ull +#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE3_VDEC1_CS_ROM_TBL_BASE 0x67F0000ull +#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_STM_BASE 0x67F1000ull +#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_CTI_BASE 0x67F2000ull +#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_ETF_BASE 0x67F3000ull +#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_SPMU_BASE 0x67F4000ull +#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_CTI_BASE 0x67F5000ull +#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_USER_CTI_BASE 0x67F6000ull +#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_0_BASE 0x67F7000ull +#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_1_BASE 0x67F8000ull +#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_2_BASE 0x67F9000ull +#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_2_SECTION 0x7000 +#define mmCA53_BASE 0x6800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x6C00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x6C01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x6C02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x6C03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x6C04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x6C05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x2000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x6C07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x6C08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x6C09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x6C0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x36000 +#define mmTOP_ROM_TABLE_BASE 0x6C40000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x1000 +#define mmPSOC_CTI_BASE 0x6C41000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x6C42000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x6C43000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x6C44000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x6C45000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x6C46000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xA000 +#define mmPSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x6C50000ull +#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPSOC_ARC0_CS_STM_BASE 0x6C51000ull +#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_STM_SECTION 0x1000 +#define mmPSOC_ARC0_CS_CTI_BASE 0x6C52000ull +#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_CS_ETF_BASE 0x6C53000ull +#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_ETF_SECTION 0x1000 +#define mmPSOC_ARC0_CS_SPMU_BASE 0x6C54000ull +#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_SPMU_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_CTI_BASE 0x6C55000ull +#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_USER_CTI_BASE 0x6C56000ull +#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_USER_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_0_BASE 0x6C57000ull +#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_0_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_1_BASE 0x6C58000ull +#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_1_SECTION 0x6000 +#define mmPSOC_ARC0_RTT_BASE 0x6C5E000ull +#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC0_RTT_SECTION 0x1000 +#define mmPSOC_ARC0_FUNNEL_BASE 0x6C5F000ull +#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_FUNNEL_SECTION 0x1000 +#define mmPSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x6C60000ull +#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPSOC_ARC1_CS_STM_BASE 0x6C61000ull +#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_STM_SECTION 0x1000 +#define mmPSOC_ARC1_CS_CTI_BASE 0x6C62000ull +#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_CS_ETF_BASE 0x6C63000ull +#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_ETF_SECTION 0x1000 +#define mmPSOC_ARC1_CS_SPMU_BASE 0x6C64000ull +#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_SPMU_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_CTI_BASE 0x6C65000ull +#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_USER_CTI_BASE 0x6C66000ull +#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_USER_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_0_BASE 0x6C67000ull +#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_0_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_1_BASE 0x6C68000ull +#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_1_SECTION 0x6000 +#define mmPSOC_ARC1_RTT_BASE 0x6C6E000ull +#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC1_RTT_SECTION 0x1000 +#define mmPSOC_ARC1_FUNNEL_BASE 0x6C6F000ull +#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_FUNNEL_SECTION 0x1000 +#define mmPSOC_ARC0_CTI0_BASE 0x6C70000ull +#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI0_SECTION 0x1000 +#define mmPSOC_ARC0_CTI1_BASE 0x6C71000ull +#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI1_SECTION 0x1000 +#define mmPSOC_ARC0_CTI2_BASE 0x6C72000ull +#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI2_SECTION 0x1000 +#define mmPSOC_ARC0_CTI3_BASE 0x6C73000ull +#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI3_SECTION 0x1000 +#define mmPSOC_ARC1_CTI0_BASE 0x6C74000ull +#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI0_SECTION 0x1000 +#define mmPSOC_ARC1_CTI1_BASE 0x6C75000ull +#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI1_SECTION 0x1000 +#define mmPSOC_ARC1_CTI2_BASE 0x6C76000ull +#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI2_SECTION 0x1000 +#define mmPSOC_ARC1_CTI3_BASE 0x6C77000ull +#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI3_SECTION 0x9000 +#define mmPDMA0_CS_ROM_TBL_BASE 0x6C80000ull +#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmPDMA0_CS_STM_BASE 0x6C81000ull +#define PDMA0_CS_STM_MAX_OFFSET 0x1000 +#define PDMA0_CS_STM_SECTION 0x1000 +#define mmPDMA0_CS_CTI_BASE 0x6C82000ull +#define PDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA0_CS_CTI_SECTION 0x1000 +#define mmPDMA0_CS_ETF_BASE 0x6C83000ull +#define PDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA0_CS_ETF_SECTION 0x1000 +#define mmPDMA0_CS_SPMU_BASE 0x6C84000ull +#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA0_CS_SPMU_SECTION 0x1000 +#define mmPDMA0_BMON_CTI_BASE 0x6C85000ull +#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA0_BMON_CTI_SECTION 0x1000 +#define mmPDMA0_USER_CTI_BASE 0x6C86000ull +#define PDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA0_USER_CTI_SECTION 0x1000 +#define mmPDMA0_BMON_0_BASE 0x6C87000ull +#define PDMA0_BMON_0_MAX_OFFSET 0x1000 +#define PDMA0_BMON_0_SECTION 0x1000 +#define mmPDMA0_BMON_1_BASE 0x6C88000ull +#define PDMA0_BMON_1_MAX_OFFSET 0x1000 +#define PDMA0_BMON_1_SECTION 0x1000 +#define mmPDMA0_QM_ARC_RTT_BASE 0x6C89000ull +#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmPDMA1_CS_ROM_TBL_BASE 0x6C90000ull +#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmPDMA1_CS_STM_BASE 0x6C91000ull +#define PDMA1_CS_STM_MAX_OFFSET 0x1000 +#define PDMA1_CS_STM_SECTION 0x1000 +#define mmPDMA1_CS_CTI_BASE 0x6C92000ull +#define PDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA1_CS_CTI_SECTION 0x1000 +#define mmPDMA1_CS_ETF_BASE 0x6C93000ull +#define PDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA1_CS_ETF_SECTION 0x1000 +#define mmPDMA1_CS_SPMU_BASE 0x6C94000ull +#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA1_CS_SPMU_SECTION 0x1000 +#define mmPDMA1_BMON_CTI_BASE 0x6C95000ull +#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA1_BMON_CTI_SECTION 0x1000 +#define mmPDMA1_USER_CTI_BASE 0x6C96000ull +#define PDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA1_USER_CTI_SECTION 0x1000 +#define mmPDMA1_BMON_0_BASE 0x6C97000ull +#define PDMA1_BMON_0_MAX_OFFSET 0x1000 +#define PDMA1_BMON_0_SECTION 0x1000 +#define mmPDMA1_BMON_1_BASE 0x6C98000ull +#define PDMA1_BMON_1_MAX_OFFSET 0x1000 +#define PDMA1_BMON_1_SECTION 0x1000 +#define mmPDMA1_QM_ARC_RTT_BASE 0x6C99000ull +#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmXDMA_FUNNEL_BASE 0x6CA0000ull +#define XDMA_FUNNEL_MAX_OFFSET 0x1000 +#define XDMA_FUNNEL_SECTION 0x21000 +#define mmCPU_ETF_0_BASE 0x6CC1000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x6CC2000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x6CC4000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x6CC5000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x6CC6000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x6CC7000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x6CC8000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x6CC9000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x6CCA000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x36000 +#define mmPMMU_CS_DBG_ROM_TBL_BASE 0x6D00000ull +#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPMMU_CS_STM_BASE 0x6D01000ull +#define PMMU_CS_STM_MAX_OFFSET 0x1000 +#define PMMU_CS_STM_SECTION 0x1000 +#define mmPMMU_CS_CTI_BASE 0x6D02000ull +#define PMMU_CS_CTI_MAX_OFFSET 0x1000 +#define PMMU_CS_CTI_SECTION 0x1000 +#define mmPMMU_CS_ETF_BASE 0x6D03000ull +#define PMMU_CS_ETF_MAX_OFFSET 0x1000 +#define PMMU_CS_ETF_SECTION 0x1000 +#define mmPMMU_CS_SPMU_BASE 0x6D04000ull +#define PMMU_CS_SPMU_MAX_OFFSET 0x1000 +#define PMMU_CS_SPMU_SECTION 0x1000 +#define mmPMMU_BMON_CTI_BASE 0x6D05000ull +#define PMMU_BMON_CTI_MAX_OFFSET 0x1000 +#define PMMU_BMON_CTI_SECTION 0x1000 +#define mmPMMU_USER_CTI_BASE 0x6D06000ull +#define PMMU_USER_CTI_MAX_OFFSET 0x1000 +#define PMMU_USER_CTI_SECTION 0x1000 +#define mmPMMU_BMON_0_BASE 0x6D07000ull +#define PMMU_BMON_0_MAX_OFFSET 0x1000 +#define PMMU_BMON_0_SECTION 0x1000 +#define mmPMMU_BMON_1_BASE 0x6D08000ull +#define PMMU_BMON_1_MAX_OFFSET 0x1000 +#define PMMU_BMON_1_SECTION 0x1000 +#define mmPMMU_BMON_2_BASE 0x6D09000ull +#define PMMU_BMON_2_MAX_OFFSET 0x1000 +#define PMMU_BMON_2_SECTION 0x1000 +#define mmPMMU_BMON_3_BASE 0x6D0A000ull +#define PMMU_BMON_3_MAX_OFFSET 0x1000 +#define PMMU_BMON_3_SECTION 0x1000 +#define mmPMMU_BMON_4_BASE 0x6D0B000ull +#define PMMU_BMON_4_MAX_OFFSET 0x1000 +#define PMMU_BMON_4_SECTION 0x1000 +#define mmPMMU_FUNNEL_BASE 0x6D0C000ull +#define PMMU_FUNNEL_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_SECTION 0x1000 +#define mmPMMU_FUNNEL_DEC_BASE 0x6D0D000ull +#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_DEC_SECTION 0x33000 +#define mmDCORE0_XBAR_MID_FUNNEL_BASE 0x6D40000ull +#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE0_XBAR_EDGE_FUNNEL_BASE 0x6D48000ull +#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE1_XBAR_MID_FUNNEL_BASE 0x6D50000ull +#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE1_XBAR_EDGE_FUNNEL_BASE 0x6D58000ull +#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE2_XBAR_MID_FUNNEL_BASE 0x6D60000ull +#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE2_XBAR_EDGE_FUNNEL_BASE 0x6D68000ull +#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE3_XBAR_MID_FUNNEL_BASE 0x6D70000ull +#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE3_XBAR_EDGE_FUNNEL_BASE 0x6D78000ull +#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000 +#define mmROT0_CS_ROM_TBL_BASE 0x6E00000ull +#define ROT0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ROT0_CS_ROM_TBL_SECTION 0x1000 +#define mmROT0_CS_STM_BASE 0x6E01000ull +#define ROT0_CS_STM_MAX_OFFSET 0x1000 +#define ROT0_CS_STM_SECTION 0x1000 +#define mmROT0_CS_CTI_BASE 0x6E02000ull +#define ROT0_CS_CTI_MAX_OFFSET 0x1000 +#define ROT0_CS_CTI_SECTION 0x1000 +#define mmROT0_CS_ETF_BASE 0x6E03000ull +#define ROT0_CS_ETF_MAX_OFFSET 0x1000 +#define ROT0_CS_ETF_SECTION 0x1000 +#define mmROT0_CS_SPMU_BASE 0x6E04000ull +#define ROT0_CS_SPMU_MAX_OFFSET 0x1000 +#define ROT0_CS_SPMU_SECTION 0x1000 +#define mmROT0_BMON_CTI_BASE 0x6E05000ull +#define ROT0_BMON_CTI_MAX_OFFSET 0x1000 +#define ROT0_BMON_CTI_SECTION 0x1000 +#define mmROT0_USER_CTI_BASE 0x6E06000ull +#define ROT0_USER_CTI_MAX_OFFSET 0x1000 +#define ROT0_USER_CTI_SECTION 0x1000 +#define mmROT0_BMON_0_BASE 0x6E07000ull +#define ROT0_BMON_0_MAX_OFFSET 0x1000 +#define ROT0_BMON_0_SECTION 0x1000 +#define mmROT0_BMON_1_BASE 0x6E08000ull +#define ROT0_BMON_1_MAX_OFFSET 0x1000 +#define ROT0_BMON_1_SECTION 0x1000 +#define mmROT0_BMON_2_BASE 0x6E09000ull +#define ROT0_BMON_2_MAX_OFFSET 0x1000 +#define ROT0_BMON_2_SECTION 0x1000 +#define mmROT0_BMON_3_BASE 0x6E0A000ull +#define ROT0_BMON_3_MAX_OFFSET 0x1000 +#define ROT0_BMON_3_SECTION 0x1000 +#define mmROT0_ARC_RTT_BASE 0x6E0B000ull +#define ROT0_ARC_RTT_MAX_OFFSET 0x1400 +#define ROT0_ARC_RTT_SECTION 0x5000 +#define mmROT1_CS_ROM_TBL_BASE 0x6E10000ull +#define ROT1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ROT1_CS_ROM_TBL_SECTION 0x1000 +#define mmROT1_CS_STM_BASE 0x6E11000ull +#define ROT1_CS_STM_MAX_OFFSET 0x1000 +#define ROT1_CS_STM_SECTION 0x1000 +#define mmROT1_CS_CTI_BASE 0x6E12000ull +#define ROT1_CS_CTI_MAX_OFFSET 0x1000 +#define ROT1_CS_CTI_SECTION 0x1000 +#define mmROT1_CS_ETF_BASE 0x6E13000ull +#define ROT1_CS_ETF_MAX_OFFSET 0x1000 +#define ROT1_CS_ETF_SECTION 0x1000 +#define mmROT1_CS_SPMU_BASE 0x6E14000ull +#define ROT1_CS_SPMU_MAX_OFFSET 0x1000 +#define ROT1_CS_SPMU_SECTION 0x1000 +#define mmROT1_BMON_CTI_BASE 0x6E15000ull +#define ROT1_BMON_CTI_MAX_OFFSET 0x1000 +#define ROT1_BMON_CTI_SECTION 0x1000 +#define mmROT1_USER_CTI_BASE 0x6E16000ull +#define ROT1_USER_CTI_MAX_OFFSET 0x1000 +#define ROT1_USER_CTI_SECTION 0x1000 +#define mmROT1_BMON_0_BASE 0x6E17000ull +#define ROT1_BMON_0_MAX_OFFSET 0x1000 +#define ROT1_BMON_0_SECTION 0x1000 +#define mmROT1_BMON_1_BASE 0x6E18000ull +#define ROT1_BMON_1_MAX_OFFSET 0x1000 +#define ROT1_BMON_1_SECTION 0x1000 +#define mmROT1_BMON_2_BASE 0x6E19000ull +#define ROT1_BMON_2_MAX_OFFSET 0x1000 +#define ROT1_BMON_2_SECTION 0x1000 +#define mmROT1_BMON_3_BASE 0x6E1A000ull +#define ROT1_BMON_3_MAX_OFFSET 0x1000 +#define ROT1_BMON_3_SECTION 0x1000 +#define mmROT1_ARC_RTT_BASE 0x6E1B000ull +#define ROT1_ARC_RTT_MAX_OFFSET 0x1400 +#define ROT1_ARC_RTT_SECTION 0x65000 +#define mmARC_FARM_ARC0_RTT_BASE 0x6E80000ull +#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC0_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC1_RTT_BASE 0x6E81000ull +#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC1_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC2_RTT_BASE 0x6E82000ull +#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC2_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC3_RTT_BASE 0x6E83000ull +#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC3_RTT_SECTION 0xD000 +#define mmARC_FARM_CS_ROM_TBL_BASE 0x6E90000ull +#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000 +#define mmARC_FARM_CS_STM_BASE 0x6E91000ull +#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_STM_SECTION 0x1000 +#define mmARC_FARM_CS_CTI_BASE 0x6E92000ull +#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_CTI_SECTION 0x1000 +#define mmARC_FARM_CS_ETF_BASE 0x6E93000ull +#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ETF_SECTION 0x1000 +#define mmARC_FARM_CS_SPMU_BASE 0x6E94000ull +#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_SPMU_SECTION 0x1000 +#define mmARC_FARM_BMON_CTI_BASE 0x6E95000ull +#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_CTI_SECTION 0x1000 +#define mmARC_FARM_USER_CTI_BASE 0x6E96000ull +#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_USER_CTI_SECTION 0x1000 +#define mmARC_FARM_BMON_0_BASE 0x6E97000ull +#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_0_SECTION 0x1000 +#define mmARC_FARM_BMON_1_BASE 0x6E98000ull +#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_1_SECTION 0x1000 +#define mmARC_FARM_BMON_2_BASE 0x6E99000ull +#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_2_SECTION 0x1000 +#define mmARC_FARM_BMON_3_BASE 0x6E9A000ull +#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_3_SECTION 0x1000 +#define mmARC_FARM_CTI_BASE 0x6E9B000ull +#define ARC_FARM_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CTI_SECTION 0x1000 +#define mmARC_FARM_FUNNEL_BASE 0x6E9C000ull +#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000 +#define ARC_FARM_FUNNEL_SECTION 0x4000 +#define mmKDMA_CS_ROM_TBL_BASE 0x6EA0000ull +#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define KDMA_CS_ROM_TBL_SECTION 0x1000 +#define mmKDMA_CS_STM_BASE 0x6EA1000ull +#define KDMA_CS_STM_MAX_OFFSET 0x1000 +#define KDMA_CS_STM_SECTION 0x1000 +#define mmKDMA_CS_CTI_BASE 0x6EA2000ull +#define KDMA_CS_CTI_MAX_OFFSET 0x1000 +#define KDMA_CS_CTI_SECTION 0x1000 +#define mmKDMA_CS_ETF_BASE 0x6EA3000ull +#define KDMA_CS_ETF_MAX_OFFSET 0x1000 +#define KDMA_CS_ETF_SECTION 0x1000 +#define mmKDMA_CS_SPMU_BASE 0x6EA4000ull +#define KDMA_CS_SPMU_MAX_OFFSET 0x1000 +#define KDMA_CS_SPMU_SECTION 0x1000 +#define mmKDMA_BMON_CTI_BASE 0x6EA5000ull +#define KDMA_BMON_CTI_MAX_OFFSET 0x1000 +#define KDMA_BMON_CTI_SECTION 0x1000 +#define mmKDMA_USER_CTI_BASE 0x6EA6000ull +#define KDMA_USER_CTI_MAX_OFFSET 0x1000 +#define KDMA_USER_CTI_SECTION 0x1000 +#define mmKDMA_BMON_0_BASE 0x6EA7000ull +#define KDMA_BMON_0_MAX_OFFSET 0x1000 +#define KDMA_BMON_0_SECTION 0x1000 +#define mmKDMA_BMON_1_BASE 0x6EA8000ull +#define KDMA_BMON_1_MAX_OFFSET 0x1000 +#define KDMA_BMON_1_SECTION 0x1000 +#define mmKDMA_BMON_2_BASE 0x6EA9000ull +#define KDMA_BMON_2_MAX_OFFSET 0x1000 +#define KDMA_BMON_2_SECTION 0x1000 +#define mmKDMA_BMON_3_BASE 0x6EAA000ull +#define KDMA_BMON_3_MAX_OFFSET 0x1000 +#define KDMA_BMON_3_SECTION 0x56000 +#define mmPCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x6F00000ull +#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_STM_BASE 0x6F01000ull +#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_STM_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_CTI_BASE 0x6F02000ull +#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_ETF_BASE 0x6F03000ull +#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_ETF_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_SPMU_BASE 0x6F04000ull +#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_CTI_BASE 0x6F05000ull +#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_USER_CTI_BASE 0x6F06000ull +#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_USER_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_0_BASE 0x6F07000ull +#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_0_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_1_BASE 0x6F08000ull +#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_1_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_2_BASE 0x6F09000ull +#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_2_SECTION 0x7000 +#define mmPCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x6F10000ull +#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_STM_BASE 0x6F11000ull +#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_STM_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_CTI_BASE 0x6F12000ull +#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_ETF_BASE 0x6F13000ull +#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_ETF_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_SPMU_BASE 0x6F14000ull +#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_CTI_BASE 0x6F15000ull +#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_USER_CTI_BASE 0x6F16000ull +#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_USER_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_0_BASE 0x6F17000ull +#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_0_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_1_BASE 0x6F18000ull +#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_1_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_2_BASE 0x6F19000ull +#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_2_SECTION 0xF7000 +#define mmHBM0_MC0_CS_DBG_ROM_TBL_BASE 0x7010000ull +#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM0_MC0_CS_STM_BASE 0x7011000ull +#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_STM_SECTION 0x1000 +#define mmHBM0_MC0_CS_CTI_BASE 0x7012000ull +#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM0_MC0_CS_ETF_BASE 0x7013000ull +#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM0_MC0_CS_SPMU_BASE 0x7014000ull +#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM0_MC0_BMON_CTI_BASE 0x7015000ull +#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM0_MC0_USER_CTI_BASE 0x7016000ull +#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM0_MC0_FUNNEL_BASE 0x7020000ull +#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM0_MC1_CS_DBG_ROM_TBL_BASE 0x7050000ull +#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM0_MC1_CS_STM_BASE 0x7051000ull +#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_STM_SECTION 0x1000 +#define mmHBM0_MC1_CS_CTI_BASE 0x7052000ull +#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM0_MC1_CS_ETF_BASE 0x7053000ull +#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM0_MC1_CS_SPMU_BASE 0x7054000ull +#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM0_MC1_BMON_CTI_BASE 0x7055000ull +#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM0_MC1_USER_CTI_BASE 0x7056000ull +#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM0_MC1_FUNNEL_BASE 0x7060000ull +#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM1_MC0_CS_DBG_ROM_TBL_BASE 0x7090000ull +#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM1_MC0_CS_STM_BASE 0x7091000ull +#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_STM_SECTION 0x1000 +#define mmHBM1_MC0_CS_CTI_BASE 0x7092000ull +#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM1_MC0_CS_ETF_BASE 0x7093000ull +#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM1_MC0_CS_SPMU_BASE 0x7094000ull +#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM1_MC0_BMON_CTI_BASE 0x7095000ull +#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM1_MC0_USER_CTI_BASE 0x7096000ull +#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM1_MC0_FUNNEL_BASE 0x70A0000ull +#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM1_MC1_CS_DBG_ROM_TBL_BASE 0x70D0000ull +#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM1_MC1_CS_STM_BASE 0x70D1000ull +#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_STM_SECTION 0x1000 +#define mmHBM1_MC1_CS_CTI_BASE 0x70D2000ull +#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM1_MC1_CS_ETF_BASE 0x70D3000ull +#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM1_MC1_CS_SPMU_BASE 0x70D4000ull +#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM1_MC1_BMON_CTI_BASE 0x70D5000ull +#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM1_MC1_USER_CTI_BASE 0x70D6000ull +#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM1_MC1_FUNNEL_BASE 0x70E0000ull +#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM2_MC0_CS_DBG_ROM_TBL_BASE 0x7110000ull +#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM2_MC0_CS_STM_BASE 0x7111000ull +#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_STM_SECTION 0x1000 +#define mmHBM2_MC0_CS_CTI_BASE 0x7112000ull +#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM2_MC0_CS_ETF_BASE 0x7113000ull +#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM2_MC0_CS_SPMU_BASE 0x7114000ull +#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM2_MC0_BMON_CTI_BASE 0x7115000ull +#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM2_MC0_USER_CTI_BASE 0x7116000ull +#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM2_MC0_FUNNEL_BASE 0x7120000ull +#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM2_MC1_CS_DBG_ROM_TBL_BASE 0x7150000ull +#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM2_MC1_CS_STM_BASE 0x7151000ull +#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_STM_SECTION 0x1000 +#define mmHBM2_MC1_CS_CTI_BASE 0x7152000ull +#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM2_MC1_CS_ETF_BASE 0x7153000ull +#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM2_MC1_CS_SPMU_BASE 0x7154000ull +#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM2_MC1_BMON_CTI_BASE 0x7155000ull +#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM2_MC1_USER_CTI_BASE 0x7156000ull +#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM2_MC1_FUNNEL_BASE 0x7160000ull +#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM3_MC0_CS_DBG_ROM_TBL_BASE 0x7190000ull +#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM3_MC0_CS_STM_BASE 0x7191000ull +#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_STM_SECTION 0x1000 +#define mmHBM3_MC0_CS_CTI_BASE 0x7192000ull +#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM3_MC0_CS_ETF_BASE 0x7193000ull +#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM3_MC0_CS_SPMU_BASE 0x7194000ull +#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM3_MC0_BMON_CTI_BASE 0x7195000ull +#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM3_MC0_USER_CTI_BASE 0x7196000ull +#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM3_MC0_FUNNEL_BASE 0x71A0000ull +#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM3_MC1_CS_DBG_ROM_TBL_BASE 0x71D0000ull +#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM3_MC1_CS_STM_BASE 0x71D1000ull +#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_STM_SECTION 0x1000 +#define mmHBM3_MC1_CS_CTI_BASE 0x71D2000ull +#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM3_MC1_CS_ETF_BASE 0x71D3000ull +#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM3_MC1_CS_SPMU_BASE 0x71D4000ull +#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM3_MC1_BMON_CTI_BASE 0x71D5000ull +#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM3_MC1_USER_CTI_BASE 0x71D6000ull +#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM3_MC1_FUNNEL_BASE 0x71E0000ull +#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM4_MC0_CS_DBG_ROM_TBL_BASE 0x7210000ull +#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM4_MC0_CS_STM_BASE 0x7211000ull +#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_STM_SECTION 0x1000 +#define mmHBM4_MC0_CS_CTI_BASE 0x7212000ull +#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM4_MC0_CS_ETF_BASE 0x7213000ull +#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM4_MC0_CS_SPMU_BASE 0x7214000ull +#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM4_MC0_BMON_CTI_BASE 0x7215000ull +#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM4_MC0_USER_CTI_BASE 0x7216000ull +#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM4_MC0_FUNNEL_BASE 0x7220000ull +#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM4_MC1_CS_DBG_ROM_TBL_BASE 0x7250000ull +#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM4_MC1_CS_STM_BASE 0x7251000ull +#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_STM_SECTION 0x1000 +#define mmHBM4_MC1_CS_CTI_BASE 0x7252000ull +#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM4_MC1_CS_ETF_BASE 0x7253000ull +#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM4_MC1_CS_SPMU_BASE 0x7254000ull +#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM4_MC1_BMON_CTI_BASE 0x7255000ull +#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM4_MC1_USER_CTI_BASE 0x7256000ull +#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM4_MC1_FUNNEL_BASE 0x7260000ull +#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM5_MC0_CS_DBG_ROM_TBL_BASE 0x7290000ull +#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM5_MC0_CS_STM_BASE 0x7291000ull +#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_STM_SECTION 0x1000 +#define mmHBM5_MC0_CS_CTI_BASE 0x7292000ull +#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM5_MC0_CS_ETF_BASE 0x7293000ull +#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM5_MC0_CS_SPMU_BASE 0x7294000ull +#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM5_MC0_BMON_CTI_BASE 0x7295000ull +#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM5_MC0_USER_CTI_BASE 0x7296000ull +#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM5_MC0_FUNNEL_BASE 0x72A0000ull +#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM5_MC1_CS_DBG_ROM_TBL_BASE 0x72D0000ull +#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM5_MC1_CS_STM_BASE 0x72D1000ull +#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_STM_SECTION 0x1000 +#define mmHBM5_MC1_CS_CTI_BASE 0x72D2000ull +#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM5_MC1_CS_ETF_BASE 0x72D3000ull +#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM5_MC1_CS_SPMU_BASE 0x72D4000ull +#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM5_MC1_BMON_CTI_BASE 0x72D5000ull +#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM5_MC1_USER_CTI_BASE 0x72D6000ull +#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM5_MC1_FUNNEL_BASE 0x72E0000ull +#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC1_FUNNEL_SECTION 0x20000 +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7300000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC0_DBG_STM_0_BASE 0x7301000ull +#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_0_SECTION 0x1000 +#define mmNIC0_DBG_CTI_0_BASE 0x7302000ull +#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_ETF_0_BASE 0x7303000ull +#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_0_SECTION 0x1000 +#define mmNIC0_DBG_SPMU_0_BASE 0x7304000ull +#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC0_DBG_USER_CTI_0_BASE 0x7305000ull +#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON_CTI_0_BASE 0x7306000ull +#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON0_0_BASE 0x7307000ull +#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON1_0_BASE 0x7308000ull +#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON2_0_BASE 0x7309000ull +#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC0_DBG_ARC_RTT0_BASE 0x7310000ull +#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7320000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC0_DBG_STM_1_BASE 0x7321000ull +#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_1_SECTION 0x1000 +#define mmNIC0_DBG_CTI_1_BASE 0x7322000ull +#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_ETF_1_BASE 0x7323000ull +#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_1_SECTION 0x1000 +#define mmNIC0_DBG_SPMU_1_BASE 0x7324000ull +#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC0_DBG_USER_CTI_1_BASE 0x7325000ull +#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON_CTI_1_BASE 0x7326000ull +#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON0_1_BASE 0x7327000ull +#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON1_1_BASE 0x7328000ull +#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON2_1_BASE 0x7329000ull +#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC0_DBG_ARC_RTT1_BASE 0x7330000ull +#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC0_DBG_FUNNEL_TX_BASE 0x7338000ull +#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC0_DBG_FUNNEL_NCH_BASE 0x7339000ull +#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7340000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC1_DBG_STM_0_BASE 0x7341000ull +#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_0_SECTION 0x1000 +#define mmNIC1_DBG_CTI_0_BASE 0x7342000ull +#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_ETF_0_BASE 0x7343000ull +#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_0_SECTION 0x1000 +#define mmNIC1_DBG_SPMU_0_BASE 0x7344000ull +#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC1_DBG_USER_CTI_0_BASE 0x7345000ull +#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON_CTI_0_BASE 0x7346000ull +#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON0_0_BASE 0x7347000ull +#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON1_0_BASE 0x7348000ull +#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON2_0_BASE 0x7349000ull +#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC1_DBG_ARC_RTT0_BASE 0x7350000ull +#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7360000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC1_DBG_STM_1_BASE 0x7361000ull +#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_1_SECTION 0x1000 +#define mmNIC1_DBG_CTI_1_BASE 0x7362000ull +#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_ETF_1_BASE 0x7363000ull +#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_1_SECTION 0x1000 +#define mmNIC1_DBG_SPMU_1_BASE 0x7364000ull +#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC1_DBG_USER_CTI_1_BASE 0x7365000ull +#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON_CTI_1_BASE 0x7366000ull +#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON0_1_BASE 0x7367000ull +#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON1_1_BASE 0x7368000ull +#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON2_1_BASE 0x7369000ull +#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC1_DBG_ARC_RTT1_BASE 0x7370000ull +#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC1_DBG_FUNNEL_TX_BASE 0x7378000ull +#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC1_DBG_FUNNEL_NCH_BASE 0x7379000ull +#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7380000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC2_DBG_STM_0_BASE 0x7381000ull +#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_0_SECTION 0x1000 +#define mmNIC2_DBG_CTI_0_BASE 0x7382000ull +#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_ETF_0_BASE 0x7383000ull +#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_0_SECTION 0x1000 +#define mmNIC2_DBG_SPMU_0_BASE 0x7384000ull +#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC2_DBG_USER_CTI_0_BASE 0x7385000ull +#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON_CTI_0_BASE 0x7386000ull +#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON0_0_BASE 0x7387000ull +#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON1_0_BASE 0x7388000ull +#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON2_0_BASE 0x7389000ull +#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC2_DBG_ARC_RTT0_BASE 0x7390000ull +#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73A0000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC2_DBG_STM_1_BASE 0x73A1000ull +#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_1_SECTION 0x1000 +#define mmNIC2_DBG_CTI_1_BASE 0x73A2000ull +#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_ETF_1_BASE 0x73A3000ull +#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_1_SECTION 0x1000 +#define mmNIC2_DBG_SPMU_1_BASE 0x73A4000ull +#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC2_DBG_USER_CTI_1_BASE 0x73A5000ull +#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON_CTI_1_BASE 0x73A6000ull +#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON0_1_BASE 0x73A7000ull +#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON1_1_BASE 0x73A8000ull +#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON2_1_BASE 0x73A9000ull +#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC2_DBG_ARC_RTT1_BASE 0x73B0000ull +#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC2_DBG_FUNNEL_TX_BASE 0x73B8000ull +#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC2_DBG_FUNNEL_NCH_BASE 0x73B9000ull +#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x73C0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC3_DBG_STM_0_BASE 0x73C1000ull +#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_0_SECTION 0x1000 +#define mmNIC3_DBG_CTI_0_BASE 0x73C2000ull +#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_ETF_0_BASE 0x73C3000ull +#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_0_SECTION 0x1000 +#define mmNIC3_DBG_SPMU_0_BASE 0x73C4000ull +#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC3_DBG_USER_CTI_0_BASE 0x73C5000ull +#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON_CTI_0_BASE 0x73C6000ull +#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON0_0_BASE 0x73C7000ull +#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON1_0_BASE 0x73C8000ull +#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON2_0_BASE 0x73C9000ull +#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC3_DBG_ARC_RTT0_BASE 0x73D0000ull +#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73E0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC3_DBG_STM_1_BASE 0x73E1000ull +#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_1_SECTION 0x1000 +#define mmNIC3_DBG_CTI_1_BASE 0x73E2000ull +#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_ETF_1_BASE 0x73E3000ull +#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_1_SECTION 0x1000 +#define mmNIC3_DBG_SPMU_1_BASE 0x73E4000ull +#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC3_DBG_USER_CTI_1_BASE 0x73E5000ull +#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON_CTI_1_BASE 0x73E6000ull +#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON0_1_BASE 0x73E7000ull +#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON1_1_BASE 0x73E8000ull +#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON2_1_BASE 0x73E9000ull +#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC3_DBG_ARC_RTT1_BASE 0x73F0000ull +#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC3_DBG_FUNNEL_TX_BASE 0x73F8000ull +#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC3_DBG_FUNNEL_NCH_BASE 0x73F9000ull +#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7400000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC4_DBG_STM_0_BASE 0x7401000ull +#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_0_SECTION 0x1000 +#define mmNIC4_DBG_CTI_0_BASE 0x7402000ull +#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_ETF_0_BASE 0x7403000ull +#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_0_SECTION 0x1000 +#define mmNIC4_DBG_SPMU_0_BASE 0x7404000ull +#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC4_DBG_USER_CTI_0_BASE 0x7405000ull +#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON_CTI_0_BASE 0x7406000ull +#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON0_0_BASE 0x7407000ull +#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON1_0_BASE 0x7408000ull +#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON2_0_BASE 0x7409000ull +#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC4_DBG_ARC_RTT0_BASE 0x7410000ull +#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7420000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC4_DBG_STM_1_BASE 0x7421000ull +#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_1_SECTION 0x1000 +#define mmNIC4_DBG_CTI_1_BASE 0x7422000ull +#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_ETF_1_BASE 0x7423000ull +#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_1_SECTION 0x1000 +#define mmNIC4_DBG_SPMU_1_BASE 0x7424000ull +#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC4_DBG_USER_CTI_1_BASE 0x7425000ull +#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON_CTI_1_BASE 0x7426000ull +#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON0_1_BASE 0x7427000ull +#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON1_1_BASE 0x7428000ull +#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON2_1_BASE 0x7429000ull +#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC4_DBG_ARC_RTT1_BASE 0x7430000ull +#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC4_DBG_FUNNEL_TX_BASE 0x7438000ull +#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC4_DBG_FUNNEL_NCH_BASE 0x7439000ull +#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7440000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC5_DBG_STM_0_BASE 0x7441000ull +#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_0_SECTION 0x1000 +#define mmNIC5_DBG_CTI_0_BASE 0x7442000ull +#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_ETF_0_BASE 0x7443000ull +#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_0_SECTION 0x1000 +#define mmNIC5_DBG_SPMU_0_BASE 0x7444000ull +#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC5_DBG_USER_CTI_0_BASE 0x7445000ull +#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON_CTI_0_BASE 0x7446000ull +#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON0_0_BASE 0x7447000ull +#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON1_0_BASE 0x7448000ull +#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON2_0_BASE 0x7449000ull +#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC5_DBG_ARC_RTT0_BASE 0x7450000ull +#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7460000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC5_DBG_STM_1_BASE 0x7461000ull +#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_1_SECTION 0x1000 +#define mmNIC5_DBG_CTI_1_BASE 0x7462000ull +#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_ETF_1_BASE 0x7463000ull +#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_1_SECTION 0x1000 +#define mmNIC5_DBG_SPMU_1_BASE 0x7464000ull +#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC5_DBG_USER_CTI_1_BASE 0x7465000ull +#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON_CTI_1_BASE 0x7466000ull +#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON0_1_BASE 0x7467000ull +#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON1_1_BASE 0x7468000ull +#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON2_1_BASE 0x7469000ull +#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC5_DBG_ARC_RTT1_BASE 0x7470000ull +#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC5_DBG_FUNNEL_TX_BASE 0x7478000ull +#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC5_DBG_FUNNEL_NCH_BASE 0x7479000ull +#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7480000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC6_DBG_STM_0_BASE 0x7481000ull +#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_0_SECTION 0x1000 +#define mmNIC6_DBG_CTI_0_BASE 0x7482000ull +#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_ETF_0_BASE 0x7483000ull +#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_0_SECTION 0x1000 +#define mmNIC6_DBG_SPMU_0_BASE 0x7484000ull +#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC6_DBG_USER_CTI_0_BASE 0x7485000ull +#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON_CTI_0_BASE 0x7486000ull +#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON0_0_BASE 0x7487000ull +#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON1_0_BASE 0x7488000ull +#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON2_0_BASE 0x7489000ull +#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC6_DBG_ARC_RTT0_BASE 0x7490000ull +#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74A0000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC6_DBG_STM_1_BASE 0x74A1000ull +#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_1_SECTION 0x1000 +#define mmNIC6_DBG_CTI_1_BASE 0x74A2000ull +#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_ETF_1_BASE 0x74A3000ull +#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_1_SECTION 0x1000 +#define mmNIC6_DBG_SPMU_1_BASE 0x74A4000ull +#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC6_DBG_USER_CTI_1_BASE 0x74A5000ull +#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON_CTI_1_BASE 0x74A6000ull +#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON0_1_BASE 0x74A7000ull +#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON1_1_BASE 0x74A8000ull +#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON2_1_BASE 0x74A9000ull +#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC6_DBG_ARC_RTT1_BASE 0x74B0000ull +#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC6_DBG_FUNNEL_TX_BASE 0x74B8000ull +#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC6_DBG_FUNNEL_NCH_BASE 0x74B9000ull +#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x74C0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC7_DBG_STM_0_BASE 0x74C1000ull +#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_0_SECTION 0x1000 +#define mmNIC7_DBG_CTI_0_BASE 0x74C2000ull +#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_ETF_0_BASE 0x74C3000ull +#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_0_SECTION 0x1000 +#define mmNIC7_DBG_SPMU_0_BASE 0x74C4000ull +#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC7_DBG_USER_CTI_0_BASE 0x74C5000ull +#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON_CTI_0_BASE 0x74C6000ull +#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON0_0_BASE 0x74C7000ull +#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON1_0_BASE 0x74C8000ull +#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON2_0_BASE 0x74C9000ull +#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC7_DBG_ARC_RTT0_BASE 0x74D0000ull +#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74E0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC7_DBG_STM_1_BASE 0x74E1000ull +#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_1_SECTION 0x1000 +#define mmNIC7_DBG_CTI_1_BASE 0x74E2000ull +#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_ETF_1_BASE 0x74E3000ull +#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_1_SECTION 0x1000 +#define mmNIC7_DBG_SPMU_1_BASE 0x74E4000ull +#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC7_DBG_USER_CTI_1_BASE 0x74E5000ull +#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON_CTI_1_BASE 0x74E6000ull +#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON0_1_BASE 0x74E7000ull +#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON1_1_BASE 0x74E8000ull +#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON2_1_BASE 0x74E9000ull +#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC7_DBG_ARC_RTT1_BASE 0x74F0000ull +#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC7_DBG_FUNNEL_TX_BASE 0x74F8000ull +#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC7_DBG_FUNNEL_NCH_BASE 0x74F9000ull +#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7500000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC8_DBG_STM_0_BASE 0x7501000ull +#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_0_SECTION 0x1000 +#define mmNIC8_DBG_CTI_0_BASE 0x7502000ull +#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_ETF_0_BASE 0x7503000ull +#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_0_SECTION 0x1000 +#define mmNIC8_DBG_SPMU_0_BASE 0x7504000ull +#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC8_DBG_USER_CTI_0_BASE 0x7505000ull +#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON_CTI_0_BASE 0x7506000ull +#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON0_0_BASE 0x7507000ull +#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON1_0_BASE 0x7508000ull +#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON2_0_BASE 0x7509000ull +#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC8_DBG_ARC_RTT0_BASE 0x7510000ull +#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7520000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC8_DBG_STM_1_BASE 0x7521000ull +#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_1_SECTION 0x1000 +#define mmNIC8_DBG_CTI_1_BASE 0x7522000ull +#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_ETF_1_BASE 0x7523000ull +#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_1_SECTION 0x1000 +#define mmNIC8_DBG_SPMU_1_BASE 0x7524000ull +#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC8_DBG_USER_CTI_1_BASE 0x7525000ull +#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON_CTI_1_BASE 0x7526000ull +#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON0_1_BASE 0x7527000ull +#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON1_1_BASE 0x7528000ull +#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON2_1_BASE 0x7529000ull +#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC8_DBG_ARC_RTT1_BASE 0x7530000ull +#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC8_DBG_FUNNEL_TX_BASE 0x7538000ull +#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC8_DBG_FUNNEL_NCH_BASE 0x7539000ull +#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7540000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC9_DBG_STM_0_BASE 0x7541000ull +#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_0_SECTION 0x1000 +#define mmNIC9_DBG_CTI_0_BASE 0x7542000ull +#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_ETF_0_BASE 0x7543000ull +#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_0_SECTION 0x1000 +#define mmNIC9_DBG_SPMU_0_BASE 0x7544000ull +#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC9_DBG_USER_CTI_0_BASE 0x7545000ull +#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON_CTI_0_BASE 0x7546000ull +#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON0_0_BASE 0x7547000ull +#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON1_0_BASE 0x7548000ull +#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON2_0_BASE 0x7549000ull +#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC9_DBG_ARC_RTT0_BASE 0x7550000ull +#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7560000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC9_DBG_STM_1_BASE 0x7561000ull +#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_1_SECTION 0x1000 +#define mmNIC9_DBG_CTI_1_BASE 0x7562000ull +#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_ETF_1_BASE 0x7563000ull +#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_1_SECTION 0x1000 +#define mmNIC9_DBG_SPMU_1_BASE 0x7564000ull +#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC9_DBG_USER_CTI_1_BASE 0x7565000ull +#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON_CTI_1_BASE 0x7566000ull +#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON0_1_BASE 0x7567000ull +#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON1_1_BASE 0x7568000ull +#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON2_1_BASE 0x7569000ull +#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC9_DBG_ARC_RTT1_BASE 0x7570000ull +#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC9_DBG_FUNNEL_TX_BASE 0x7578000ull +#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC9_DBG_FUNNEL_NCH_BASE 0x7579000ull +#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7580000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC10_DBG_STM_0_BASE 0x7581000ull +#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_0_SECTION 0x1000 +#define mmNIC10_DBG_CTI_0_BASE 0x7582000ull +#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_ETF_0_BASE 0x7583000ull +#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_0_SECTION 0x1000 +#define mmNIC10_DBG_SPMU_0_BASE 0x7584000ull +#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC10_DBG_USER_CTI_0_BASE 0x7585000ull +#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON_CTI_0_BASE 0x7586000ull +#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON0_0_BASE 0x7587000ull +#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON1_0_BASE 0x7588000ull +#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON2_0_BASE 0x7589000ull +#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC10_DBG_ARC_RTT0_BASE 0x7590000ull +#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75A0000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC10_DBG_STM_1_BASE 0x75A1000ull +#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_1_SECTION 0x1000 +#define mmNIC10_DBG_CTI_1_BASE 0x75A2000ull +#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_ETF_1_BASE 0x75A3000ull +#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_1_SECTION 0x1000 +#define mmNIC10_DBG_SPMU_1_BASE 0x75A4000ull +#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC10_DBG_USER_CTI_1_BASE 0x75A5000ull +#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON_CTI_1_BASE 0x75A6000ull +#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON0_1_BASE 0x75A7000ull +#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON1_1_BASE 0x75A8000ull +#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON2_1_BASE 0x75A9000ull +#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC10_DBG_ARC_RTT1_BASE 0x75B0000ull +#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC10_DBG_FUNNEL_TX_BASE 0x75B8000ull +#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC10_DBG_FUNNEL_NCH_BASE 0x75B9000ull +#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x75C0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC11_DBG_STM_0_BASE 0x75C1000ull +#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_0_SECTION 0x1000 +#define mmNIC11_DBG_CTI_0_BASE 0x75C2000ull +#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_ETF_0_BASE 0x75C3000ull +#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_0_SECTION 0x1000 +#define mmNIC11_DBG_SPMU_0_BASE 0x75C4000ull +#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC11_DBG_USER_CTI_0_BASE 0x75C5000ull +#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON_CTI_0_BASE 0x75C6000ull +#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON0_0_BASE 0x75C7000ull +#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON1_0_BASE 0x75C8000ull +#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON2_0_BASE 0x75C9000ull +#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC11_DBG_ARC_RTT0_BASE 0x75D0000ull +#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75E0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC11_DBG_STM_1_BASE 0x75E1000ull +#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_1_SECTION 0x1000 +#define mmNIC11_DBG_CTI_1_BASE 0x75E2000ull +#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_ETF_1_BASE 0x75E3000ull +#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_1_SECTION 0x1000 +#define mmNIC11_DBG_SPMU_1_BASE 0x75E4000ull +#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC11_DBG_USER_CTI_1_BASE 0x75E5000ull +#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON_CTI_1_BASE 0x75E6000ull +#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON0_1_BASE 0x75E7000ull +#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON1_1_BASE 0x75E8000ull +#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON2_1_BASE 0x75E9000ull +#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC11_DBG_ARC_RTT1_BASE 0x75F0000ull +#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC11_DBG_FUNNEL_TX_BASE 0x75F8000ull +#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC11_DBG_FUNNEL_NCH_BASE 0x75F9000ull +#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 + +#endif /* GAUDI2_BLOCKS_LINUX_DRIVER_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h new file mode 100644 index 000000000..6aa1b1412 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h @@ -0,0 +1,552 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GAUDI2_REGS_H_ +#define ASIC_REG_GAUDI2_REGS_H_ + +#include "gaudi2_blocks_linux_driver.h" +#include "psoc_reset_conf_regs.h" +#include "psoc_global_conf_regs.h" +#include "cpu_if_regs.h" +#include "pcie_aux_regs.h" +#include "pcie_dbi_regs.h" +#include "pcie_wrap_regs.h" +#include "pmmu_hbw_stlb_regs.h" +#include "psoc_timestamp_regs.h" +#include "psoc_etr_regs.h" +#include "xbar_edge_0_regs.h" +#include "xbar_mid_0_regs.h" +#include "arc_farm_kdma_regs.h" +#include "arc_farm_kdma_ctx_regs.h" +#include "arc_farm_kdma_kdma_cgm_regs.h" +#include "arc_farm_arc0_aux_regs.h" +#include "arc_farm_arc0_acp_eng_regs.h" +#include "arc_farm_kdma_ctx_axuser_regs.h" +#include "arc_farm_arc0_dup_eng_axuser_regs.h" +#include "arc_farm_arc0_dup_eng_regs.h" +#include "dcore0_sync_mngr_objs_regs.h" +#include "dcore0_sync_mngr_glbl_regs.h" +#include "dcore0_sync_mngr_mstr_if_axuser_regs.h" +#include "pdma0_qm_arc_aux_regs.h" +#include "pdma0_core_ctx_regs.h" +#include "pdma0_core_regs.h" +#include "pdma0_qm_axuser_secured_regs.h" +#include "pdma0_qm_regs.h" +#include "pdma0_qm_cgm_regs.h" +#include "pdma0_core_ctx_axuser_regs.h" +#include "pdma1_core_ctx_axuser_regs.h" +#include "pdma0_qm_axuser_nonsecured_regs.h" +#include "pdma1_qm_axuser_nonsecured_regs.h" +#include "dcore0_tpc0_qm_regs.h" +#include "dcore0_tpc0_qm_cgm_regs.h" +#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h" +#include "dcore0_tpc0_qm_arc_aux_regs.h" +#include "dcore0_tpc0_cfg_regs.h" +#include "dcore0_tpc0_cfg_qm_regs.h" +#include "dcore0_tpc0_cfg_axuser_regs.h" +#include "dcore0_tpc0_cfg_qm_sync_object_regs.h" +#include "dcore0_tpc0_cfg_kernel_regs.h" +#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h" +#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h" +#include "dcore0_tpc0_cfg_special_regs.h" +#include "dcore0_tpc0_eml_funnel_regs.h" +#include "dcore0_tpc0_eml_etf_regs.h" +#include "dcore0_tpc0_eml_stm_regs.h" +#include "dcore0_tpc0_eml_busmon_0_regs.h" +#include "dcore0_tpc0_eml_spmu_regs.h" +#include "pmmu_pif_regs.h" +#include "dcore0_edma0_qm_cgm_regs.h" +#include "dcore0_edma0_core_regs.h" +#include "dcore0_edma0_qm_regs.h" +#include "dcore0_edma0_qm_arc_aux_regs.h" +#include "dcore0_edma0_core_ctx_regs.h" +#include "dcore0_edma0_core_ctx_axuser_regs.h" +#include "dcore0_edma0_qm_axuser_nonsecured_regs.h" +#include "dcore0_edma1_core_ctx_axuser_regs.h" +#include "dcore0_edma1_qm_axuser_nonsecured_regs.h" +#include "dcore0_hmmu0_stlb_regs.h" +#include "dcore0_hmmu0_mmu_regs.h" +#include "rot0_qm_regs.h" +#include "rot0_qm_cgm_regs.h" +#include "rot0_qm_arc_aux_regs.h" +#include "rot0_regs.h" +#include "rot0_desc_regs.h" +#include "rot0_qm_axuser_nonsecured_regs.h" +#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h" +#include "dcore0_rtr0_ctrl_regs.h" +#include "dcore0_dec0_cmd_regs.h" +#include "dcore0_vdec0_brdg_ctrl_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" +#include "dcore0_vdec0_ctrl_special_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" +#include "pcie_dec0_cmd_regs.h" +#include "pcie_vdec0_brdg_ctrl_regs.h" +#include "pcie_vdec0_ctrl_special_regs.h" +#include "dcore0_mme_qm_regs.h" +#include "dcore0_mme_qm_arc_aux_regs.h" +#include "dcore0_mme_qm_axuser_secured_regs.h" +#include "dcore0_mme_qm_cgm_regs.h" +#include "dcore0_mme_qm_arc_acp_eng_regs.h" +#include "dcore0_mme_qm_axuser_nonsecured_regs.h" +#include "dcore0_mme_qm_arc_dup_eng_regs.h" +#include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h" +#include "dcore0_mme_sbte0_mstr_if_axuser_regs.h" +#include "dcore0_mme_wb0_mstr_if_axuser_regs.h" +#include "dcore0_mme_acc_regs.h" +#include "dcore0_mme_ctrl_lo_regs.h" +#include "dcore1_mme_ctrl_lo_regs.h" +#include "dcore3_mme_ctrl_lo_regs.h" +#include "dcore0_mme_ctrl_lo_mme_axuser_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h" +#include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h" +#include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h" +#include "pcie_wrap_special_regs.h" + +#include "pdma0_qm_masks.h" +#include "pdma0_core_masks.h" +#include "pdma0_core_special_masks.h" +#include "psoc_global_conf_masks.h" +#include "psoc_reset_conf_masks.h" +#include "arc_farm_kdma_masks.h" +#include "arc_farm_kdma_ctx_masks.h" +#include "arc_farm_arc0_aux_masks.h" +#include "arc_farm_kdma_ctx_axuser_masks.h" +#include "dcore0_sync_mngr_objs_masks.h" +#include "dcore0_sync_mngr_glbl_masks.h" +#include "dcore0_sync_mngr_mstr_if_axuser_masks.h" +#include "dcore0_tpc0_cfg_masks.h" +#include "dcore0_mme_ctrl_lo_masks.h" +#include "dcore0_mme_sbte0_masks.h" +#include "dcore0_edma0_qm_masks.h" +#include "dcore0_edma0_core_masks.h" +#include "dcore0_hmmu0_stlb_masks.h" +#include "dcore0_hmmu0_mmu_masks.h" +#include "dcore0_dec0_cmd_masks.h" +#include "dcore0_vdec0_brdg_ctrl_masks.h" +#include "pcie_dec0_cmd_masks.h" +#include "pcie_vdec0_brdg_ctrl_masks.h" +#include "rot0_masks.h" +#include "pmmu_hbw_stlb_masks.h" +#include "psoc_etr_masks.h" + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 + +#define SM_OBJS_PROT_BITS_OFFS 0x14000 + +#define DCORE_OFFSET (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE) +#define DCORE_EDMA_OFFSET (mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE) +#define DCORE_TPC_OFFSET (mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE) +#define DCORE_DEC_OFFSET (mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE) +#define DCORE_HMMU_OFFSET (mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE) +#define NIC_QM_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE) +#define PDMA_OFFSET (mmPDMA1_QM_BASE - mmPDMA0_QM_BASE) +#define ROT_OFFSET (mmROT1_BASE - mmROT0_BASE) + +#define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \ + (mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) + +#define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \ + (mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) + +#define TPC_CFG_STALL_OFFSET (mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_STALL_ON_ERR_OFFSET (mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_TPC_INTR_MASK_OFFSET (mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_MSS_CONFIG_OFFSET (mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE) + +#define MME_ACC_INTR_MASK_OFFSET (mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_WR_AXI_AGG_COUT0_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_WR_AXI_AGG_COUT1_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_POLY_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_SEED_SEL_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \ + (mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE) + +#define DMA_CORE_CFG_0_OFFSET (mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_CFG_1_OFFSET (mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_PROT_OFFSET (mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_ADDR_LO_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_ADDR_HI_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_WDATA_OFFSET (mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE) + +#define QM_PQ_BASE_LO_0_OFFSET (mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQ_BASE_HI_0_OFFSET (mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_PQ_SIZE_0_OFFSET (mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE) +#define QM_PQ_PI_0_OFFSET (mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE) +#define QM_PQ_CI_0_OFFSET (mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE) +#define QM_CP_FENCE0_CNT_0_OFFSET (mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE) + +#define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE) + +#define QM_CP_CFG_OFFSET (mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE) +#define QM_PQC_HBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQC_HBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_PQC_SIZE_0_OFFSET (mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE) +#define QM_PQC_PI_0_OFFSET (mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_WDATA_0_OFFSET (mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_ADDR_LO_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE) +#define QM_PQC_CFG_OFFSET (mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE) +#define QM_ARB_CFG_0_OFFSET (mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG0_OFFSET (mmPDMA0_QM_GLBL_CFG0 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG1_OFFSET (mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG2_OFFSET (mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE) +#define QM_GLBL_PROT_OFFSET (mmPDMA0_QM_GLBL_PROT - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_CFG_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_CFG1_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_ADDR_HI_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_WDATA_OFFSET (mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE) +#define QM_ARB_ERR_MSG_EN_OFFSET (mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE) +#define QM_ARB_SLV_CHOISE_WDT_OFFSET (mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE) +#define QM_FENCE2_OFFSET (mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE) +#define QM_SEI_STATUS_OFFSET (mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE) + +#define SFT_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) +#define SFT_IF_RTR_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) + +#define ARC_HALT_REQ_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE) +#define ARC_HALT_ACK_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE) + +#define ARC_REGION_CFG_OFFSET(region) \ + (mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE) + +#define ARC_DCCM_UPPER_EN_OFFSET \ + (mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE) + +#define PCIE_VDEC_OFFSET \ + (mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_MME_SBTE_OFFSET \ + (mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_MME_WB_OFFSET \ + (mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_RTR_OFFSET \ + (mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_VDEC_OFFSET \ + (mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define MMU_OFFSET(REG) (REG - mmDCORE0_HMMU0_MMU_BASE) +#define MMU_BYPASS_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS) +#define MMU_SPI_SEI_MASK_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK) +#define MMU_SPI_SEI_CAUSE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE) +#define MMU_ENABLE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE) +#define MMU_DDR_RANGE_REG_ENABLE MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE) +#define MMU_RR_SEC_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0) +#define MMU_RR_SEC_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0) +#define MMU_RR_SEC_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0) +#define MMU_RR_SEC_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0) +#define MMU_RR_PRIV_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0) +#define MMU_RR_PRIV_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0) +#define MMU_RR_PRIV_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0) +#define MMU_RR_PRIV_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0) +#define MMU_INTERRUPT_CLR_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR) + +#define STLB_OFFSET(REG) (REG - mmDCORE0_HMMU0_STLB_BASE) +#define STLB_BUSY_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY) +#define STLB_ASID_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID) +#define STLB_HOP0_PA43_12_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12) +#define STLB_HOP0_PA63_44_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44) +#define STLB_HOP_CONFIGURATION_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION) +#define STLB_INV_ALL_START_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START) +#define STLB_SRAM_INIT_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT) +#define STLB_SET_THRESHOLD_HOP3_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3) +#define STLB_SET_THRESHOLD_HOP2_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2) +#define STLB_SET_THRESHOLD_HOP1_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1) +#define STLB_SET_THRESHOLD_HOP0_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0) +#define STLB_RANGE_INV_START_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB) +#define STLB_RANGE_INV_START_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB) +#define STLB_RANGE_INV_END_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB) +#define STLB_RANGE_INV_END_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB) + +#define STLB_LL_LOOKUP_MASK_63_32_OFFSET \ + STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32) + +#define STLB_RANGE_CACHE_INVALIDATION_OFFSET \ + STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION) + +/* RTR CTR RAZWI related offsets */ +#define RTR_MSTR_IF_OFFSET (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) + +#define RTR_LBW_MSTR_IF_OFFSET \ + (mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw addr high */ +#define DEC_RAZWI_HBW_AW_ADDR_HI \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw addr low */ +#define DEC_RAZWI_HBW_AW_ADDR_LO \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw set */ +#define DEC_RAZWI_HBW_AW_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar addr high */ +#define DEC_RAZWI_HBW_AR_ADDR_HI \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar addr low */ +#define DEC_RAZWI_HBW_AR_ADDR_LO \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar set */ +#define DEC_RAZWI_HBW_AR_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw aw addr */ +#define DEC_RAZWI_LBW_AW_ADDR \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw aw set */ +#define DEC_RAZWI_LBW_AW_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw ar addr */ +#define DEC_RAZWI_LBW_AR_ADDR \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw ar set */ +#define DEC_RAZWI_LBW_AR_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured shared hbw aw addr high */ +#define RR_SHRD_HBW_AW_RAZWI_HI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw aw addr low */ +#define RR_SHRD_HBW_AW_RAZWI_LO \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw ar addr high */ +#define RR_SHRD_HBW_AR_RAZWI_HI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw ar addr low */ +#define RR_SHRD_HBW_AR_RAZWI_LO \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared aw XY coordinates */ +#define RR_SHRD_HBW_AW_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared ar XY coordinates */ +#define RR_SHRD_HBW_AR_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI hbw shared occurred due to write access */ +#define RR_SHRD_HBW_AW_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI hbw shared occurred due to read access */ +#define RR_SHRD_HBW_AR_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw aw addr */ +#define RR_SHRD_LBW_AW_RAZWI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw ar addr */ +#define RR_SHRD_LBW_AR_RAZWI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw aw XY coordinates */ +#define RR_SHRD_LBW_AW_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw ar XY coordinates */ +#define RR_SHRD_LBW_AR_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI lbw shared occurred due to write access */ +#define RR_SHRD_LBW_AW_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI lbw shared occurred due to read access */ +#define RR_SHRD_LBW_AR_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE) +#define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE) +#define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) +#define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) + +#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR \ + (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_NRM_MSIX_LBW_WDATA \ + (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR \ + (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA \ + (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MIN_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MAX_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MIN_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MAX_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET \ + (mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE) + +#define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET \ + (mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE) + +#define HBM_MC_SPI_TEMP_PIN_CHG_MASK BIT(0) +#define HBM_MC_SPI_THR_ENG_MASK BIT(1) +#define HBM_MC_SPI_THR_DIS_ENG_MASK BIT(2) +#define HBM_MC_SPI_IEEE1500_COMP_MASK BIT(3) +#define HBM_MC_SPI_IEEE1500_PAUSED_MASK BIT(4) + +#include "nic0_qpc0_regs.h" +#include "nic0_qm0_regs.h" +#include "nic0_qm_arc_aux0_regs.h" +#include "nic0_qm0_cgm_regs.h" +#include "nic0_umr0_0_completion_queue_ci_1_regs.h" +#include "nic0_umr0_0_unsecure_doorbell0_regs.h" + +#define NIC_OFFSET (mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define NIC_UMR_OFFSET \ + (mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE) + +#endif /* ASIC_REG_GAUDI2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h new file mode 100644 index 000000000..d49906a68 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_CGM_REGS_H_ +#define ASIC_REG_NIC0_QM0_CGM_REGS_H_ + +/* + ***************************************** + * NIC0_QM0_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmNIC0_QM0_CGM_CFG 0x541AD80 + +#define mmNIC0_QM0_CGM_STS 0x541AD84 + +#define mmNIC0_QM0_CGM_CFG1 0x541AD88 + +#endif /* ASIC_REG_NIC0_QM0_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h new file mode 100644 index 000000000..acb19c1cd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_REGS_H_ +#define ASIC_REG_NIC0_QM0_REGS_H_ + +/* + ***************************************** + * NIC0_QM0 + * (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC0_QM0_GLBL_CFG0 0x541A000 + +#define mmNIC0_QM0_GLBL_CFG1 0x541A004 + +#define mmNIC0_QM0_GLBL_CFG2 0x541A008 + +#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C + +#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010 + +#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014 + +#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018 + +#define mmNIC0_QM0_GLBL_STS0 0x541A01C + +#define mmNIC0_QM0_GLBL_STS1 0x541A020 + +#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024 + +#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028 + +#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C + +#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030 + +#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048 + +#define mmNIC0_QM0_GLBL_PROT 0x541A04C + +#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050 + +#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054 + +#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058 + +#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C + +#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060 + +#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064 + +#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068 + +#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C + +#define mmNIC0_QM0_PQ_SIZE_0 0x541A070 + +#define mmNIC0_QM0_PQ_SIZE_1 0x541A074 + +#define mmNIC0_QM0_PQ_SIZE_2 0x541A078 + +#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C + +#define mmNIC0_QM0_PQ_PI_0 0x541A080 + +#define mmNIC0_QM0_PQ_PI_1 0x541A084 + +#define mmNIC0_QM0_PQ_PI_2 0x541A088 + +#define mmNIC0_QM0_PQ_PI_3 0x541A08C + +#define mmNIC0_QM0_PQ_CI_0 0x541A090 + +#define mmNIC0_QM0_PQ_CI_1 0x541A094 + +#define mmNIC0_QM0_PQ_CI_2 0x541A098 + +#define mmNIC0_QM0_PQ_CI_3 0x541A09C + +#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0 + +#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4 + +#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8 + +#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC + +#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0 + +#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4 + +#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8 + +#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC + +#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0 + +#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4 + +#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8 + +#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC + +#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0 + +#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4 + +#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8 + +#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC + +#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0 + +#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4 + +#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8 + +#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC + +#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0 + +#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4 + +#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8 + +#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC + +#define mmNIC0_QM0_CQ_STS0_3 0x541A100 + +#define mmNIC0_QM0_CQ_STS0_4 0x541A104 + +#define mmNIC0_QM0_CQ_CFG1_0 0x541A108 + +#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C + +#define mmNIC0_QM0_CQ_CFG1_2 0x541A110 + +#define mmNIC0_QM0_CQ_CFG1_3 0x541A114 + +#define mmNIC0_QM0_CQ_CFG1_4 0x541A118 + +#define mmNIC0_QM0_CQ_STS1_0 0x541A11C + +#define mmNIC0_QM0_CQ_STS1_1 0x541A120 + +#define mmNIC0_QM0_CQ_STS1_2 0x541A124 + +#define mmNIC0_QM0_CQ_STS1_3 0x541A128 + +#define mmNIC0_QM0_CQ_STS1_4 0x541A12C + +#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150 + +#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154 + +#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158 + +#define mmNIC0_QM0_CQ_CTL_0 0x541A15C + +#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160 + +#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164 + +#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168 + +#define mmNIC0_QM0_CQ_CTL_1 0x541A16C + +#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170 + +#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174 + +#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178 + +#define mmNIC0_QM0_CQ_CTL_2 0x541A17C + +#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180 + +#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184 + +#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188 + +#define mmNIC0_QM0_CQ_CTL_3 0x541A18C + +#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190 + +#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194 + +#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198 + +#define mmNIC0_QM0_CQ_CTL_4 0x541A19C + +#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0 + +#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4 + +#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8 + +#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC + +#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC + +#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC + +#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC + +#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0 + +#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4 + +#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC + +#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC + +#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC + +#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC + +#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0 + +#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4 + +#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8 + +#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC + +#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0 + +#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4 + +#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8 + +#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC + +#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300 + +#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304 + +#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308 + +#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C + +#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310 + +#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314 + +#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318 + +#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C + +#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320 + +#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324 + +#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328 + +#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C + +#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350 + +#define mmNIC0_QM0_CP_STS_0 0x541A368 + +#define mmNIC0_QM0_CP_STS_1 0x541A36C + +#define mmNIC0_QM0_CP_STS_2 0x541A370 + +#define mmNIC0_QM0_CP_STS_3 0x541A374 + +#define mmNIC0_QM0_CP_STS_4 0x541A378 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0 + +#define mmNIC0_QM0_CP_PRED_0 0x541A3A4 + +#define mmNIC0_QM0_CP_PRED_1 0x541A3A8 + +#define mmNIC0_QM0_CP_PRED_2 0x541A3AC + +#define mmNIC0_QM0_CP_PRED_3 0x541A3B0 + +#define mmNIC0_QM0_CP_PRED_4 0x541A3B4 + +#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8 + +#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC + +#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0 + +#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4 + +#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8 + +#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC + +#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0 + +#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4 + +#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8 + +#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0 + +#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4 + +#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8 + +#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC + +#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400 + +#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404 + +#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408 + +#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C + +#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410 + +#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414 + +#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438 + +#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C + +#define mmNIC0_QM0_PQC_SIZE_1 0x541A440 + +#define mmNIC0_QM0_PQC_SIZE_2 0x541A444 + +#define mmNIC0_QM0_PQC_SIZE_3 0x541A448 + +#define mmNIC0_QM0_PQC_PI_0 0x541A44C + +#define mmNIC0_QM0_PQC_PI_1 0x541A450 + +#define mmNIC0_QM0_PQC_PI_2 0x541A454 + +#define mmNIC0_QM0_PQC_PI_3 0x541A458 + +#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C + +#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460 + +#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464 + +#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488 + +#define mmNIC0_QM0_PQC_CFG 0x541A48C + +#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490 + +#define mmNIC0_QM0_ARB_MASK 0x541A4A0 + +#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4 + +#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8 + +#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC + +#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0 + +#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C + +#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710 + +#define mmNIC0_QM0_ARB_SLV_ID 0x541A714 + +#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718 + +#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744 + +#define mmNIC0_QM0_ARB_BASE_LO 0x541A754 + +#define mmNIC0_QM0_ARB_BASE_HI 0x541A758 + +#define mmNIC0_QM0_ARB_STATE_STS 0x541A780 + +#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784 + +#define mmNIC0_QM0_ARB_MSG_STS 0x541A788 + +#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C + +#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C + +#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0 + +#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4 + +#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC + +#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800 + +#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808 + +#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C + +#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810 + +#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C + +#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820 + +#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824 + +#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C + +#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848 + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858 + +#define mmNIC0_QM0_ADDR_OVRD 0x541A85C + +#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860 + +#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864 + +#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868 + +#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C + +#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874 + +#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878 + +#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C + +#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880 + +#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884 + +#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888 + +#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C + +#define mmNIC0_QM0_CP_CFG 0x541A890 + +#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894 + +#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898 + +#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4 + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8 + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0 + +#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC + +#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0 + +#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4 + +#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8 + +#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0 + +#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4 + +#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8 + +#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC + +#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E0 + +#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E4 + +#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E8 + +#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC + +#define mmNIC0_QM0_SEI_STATUS 0x541A8F0 + +#define mmNIC0_QM0_SEI_MASK 0x541A8F4 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD00 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD04 + +#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD08 + +#define mmNIC0_QM0_L2H_MASK_LO 0x541AD14 + +#define mmNIC0_QM0_L2H_MASK_HI 0x541AD18 + +#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C + +#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD20 + +#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD24 + +#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD28 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD30 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD34 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD38 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C + +#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD40 + +#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD44 + +#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD48 + +#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C + +#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD60 + +#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD64 + +#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD68 + +#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C + +#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD70 + +#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h new file mode 100644 index 000000000..5f380a44d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ +#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ + +/* + ***************************************** + * NIC0_QM_ARC_AUX0 + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100 + +#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104 + +#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108 + +#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C + +#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110 + +#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114 + +#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118 + +#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C + +#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120 + +#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124 + +#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128 + +#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C + +#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130 + +#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134 + +#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138 + +#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C + +#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140 + +#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144 + +#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150 + +#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154 + +#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158 + +#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C + +#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160 + +#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164 + +#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168 + +#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C + +#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170 + +#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174 + +#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178 + +#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_3 0x54181A8 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_4 0x54181AC + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_5 0x54181B0 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_6 0x54181B4 + +#define mmNIC0_QM_ARC_AUX0_ARC_CBU_AWCACHE_OVR 0x54181B8 + +#define mmNIC0_QM_ARC_AUX0_ARC_LBU_AWCACHE_OVR 0x54181BC + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_0 0x54181C0 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_1 0x54181C4 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_2 0x54181C8 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_3 0x54181CC + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_4 0x54181D0 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_5 0x54181D4 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_6 0x54181D8 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_7 0x54181DC + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_0 0x54181E0 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_1 0x54181E4 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_2 0x54181E8 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_3 0x54181EC + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_4 0x54181F0 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_5 0x54181F4 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_6 0x54181F8 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_7 0x54181FC + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_0 0x5418200 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_1 0x5418204 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_2 0x5418208 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_3 0x541820C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_4 0x5418210 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_5 0x5418214 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_6 0x5418218 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_7 0x541821C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_8 0x5418220 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_9 0x5418224 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_10 0x5418228 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_11 0x541822C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_12 0x5418230 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_13 0x5418234 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_14 0x5418238 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_15 0x541823C + +#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_0 0x5418280 + +#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_1 0x5418284 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_STS 0x5418290 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_CLR 0x5418294 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_MASK 0x5418298 + +#define mmNIC0_QM_ARC_AUX0_ARC_EXCPTN_CAUSE 0x541829C + +#define mmNIC0_QM_ARC_AUX0_SEI_INTR_HALT_EN 0x54182A0 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_HALT_MASK 0x54182A4 + +#define mmNIC0_QM_ARC_AUX0_QMAN_SEI_INTR_HALT_MASK 0x54182A8 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_STS 0x54182B0 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_CLR 0x54182B4 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_MASK 0x54182B8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_ERR_ADDR 0x54182BC + +#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_SYNDROME 0x54182C0 + +#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_ERR_ADDR 0x54182C4 + +#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_SYNDROME 0x54182C8 + +#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_ERR_ADDR 0x54182CC + +#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_SYNDROME 0x54182D0 + +#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_AWADDR_ERR 0x54182E0 + +#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_ARADDR_ERR 0x54182E4 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_BRESP 0x54182E8 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_RRESP 0x54182EC + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXLEN 0x54182F0 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXSIZE 0x54182F4 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0 0x5418300 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_1 0x5418304 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_2 0x5418308 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_3 0x541830C + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_4 0x5418310 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_5 0x5418314 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_6 0x5418318 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_7 0x541831C + +#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_WR_CNT 0x5418320 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_WR_CNT 0x5418324 + +#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_RD_CNT 0x5418328 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_RD_CNT 0x541832C + +#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_WR_CNT 0x5418330 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_WR_CNT 0x5418334 + +#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_RD_CNT 0x5418338 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT 0x541833C + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR 0x5418350 + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR_EN 0x5418354 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR 0x5418358 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR_EN 0x541835C + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR 0x5418360 + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR_EN 0x5418364 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR 0x5418368 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR_EN 0x541836C + +#define mmNIC0_QM_ARC_AUX0_CBU_AXCACHE_OVR 0x5418370 + +#define mmNIC0_QM_ARC_AUX0_CBU_LOCK_OVR 0x5418374 + +#define mmNIC0_QM_ARC_AUX0_CBU_PROT_OVR 0x5418378 + +#define mmNIC0_QM_ARC_AUX0_CBU_MAX_OUTSTANDING 0x541837C + +#define mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN 0x5418380 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORCE_RSP_OK 0x5418384 + +#define mmNIC0_QM_ARC_AUX0_CBU_NO_WR_INFLIGHT 0x541838C + +#define mmNIC0_QM_ARC_AUX0_CBU_SEI_INTR_ID 0x5418390 + +#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR 0x5418400 + +#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR_EN 0x5418404 + +#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR 0x5418408 + +#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR_EN 0x541840C + +#define mmNIC0_QM_ARC_AUX0_LBU_AXCACHE_OVR 0x5418420 + +#define mmNIC0_QM_ARC_AUX0_LBU_LOCK_OVR 0x5418424 + +#define mmNIC0_QM_ARC_AUX0_LBU_PROT_OVR 0x5418428 + +#define mmNIC0_QM_ARC_AUX0_LBU_MAX_OUTSTANDING 0x541842C + +#define mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN 0x5418430 + +#define mmNIC0_QM_ARC_AUX0_LBU_FORCE_RSP_OK 0x5418434 + +#define mmNIC0_QM_ARC_AUX0_LBU_NO_WR_INFLIGHT 0x541843C + +#define mmNIC0_QM_ARC_AUX0_LBU_SEI_INTR_ID 0x5418440 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0 0x5418500 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_1 0x5418504 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_2 0x5418508 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_3 0x541850C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_4 0x5418510 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_5 0x5418514 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_6 0x5418518 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_7 0x541851C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_0 0x5418520 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_1 0x5418524 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_2 0x5418528 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_3 0x541852C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_4 0x5418530 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_5 0x5418534 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_6 0x5418538 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_7 0x541853C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_0 0x5418540 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_1 0x5418544 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_2 0x5418548 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_3 0x541854C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_4 0x5418550 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_5 0x5418554 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_6 0x5418558 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_7 0x541855C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_0 0x5418560 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_1 0x5418564 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_2 0x5418568 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_3 0x541856C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_4 0x5418570 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_5 0x5418574 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_6 0x5418578 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_7 0x541857C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_0 0x5418580 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_1 0x5418584 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_2 0x5418588 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_3 0x541858C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_4 0x5418590 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_5 0x5418594 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_6 0x5418598 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_7 0x541859C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_0 0x54185A0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_1 0x54185A4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_2 0x54185A8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_3 0x54185AC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_4 0x54185B0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_5 0x54185B4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_6 0x54185B8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_7 0x54185BC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_0 0x54185C0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_1 0x54185C4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_2 0x54185C8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_3 0x54185CC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_4 0x54185D0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_5 0x54185D4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_6 0x54185D8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_7 0x54185DC + +#define mmNIC0_QM_ARC_AUX0_GENERAL_Q_VLD_ENTRY_MASK 0x54185E0 + +#define mmNIC0_QM_ARC_AUX0_NIC_Q_VLD_ENTRY_MASK 0x54185E4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_DROP_EN 0x5418620 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_WARN_MSG 0x5418624 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG 0x5418628 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWPROT 0x5418630 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWUSER 0x5418634 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWBURST 0x5418638 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWLOCK 0x541863C + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWCACHE 0x5418640 + +#define mmNIC0_QM_ARC_AUX0_DCCM_WRR_ARB_WEIGHT 0x5418644 + +#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_FULL_CFG 0x5418648 + +#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT 0x541864C + +#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_IFIFO_SHADOW_CI 0x5418650 + +#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x5418654 + +#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_SHADOW_CI 0x5418658 + +#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI 0x541865C + +#define mmNIC0_QM_ARC_AUX0_AUX2APB_PROT 0x5418700 + +#define mmNIC0_QM_ARC_AUX0_LBW_FORK_WIN_EN 0x5418704 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR0 0x5418708 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK0 0x541870C + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR1 0x5418710 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK1 0x5418714 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR0 0x5418718 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK0 0x541871C + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR1 0x5418720 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK1 0x5418724 + +#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR0 0x5418728 + +#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR1 0x541872C + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_LBW_FORK_MASK 0x5418730 + +#define mmNIC0_QM_ARC_AUX0_ARC_DUP_ENG_LBW_FORK_ADDR 0x5418734 + +#define mmNIC0_QM_ARC_AUX0_ARC_ACP_ENG_LBW_FORK_ADDR 0x5418738 + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_VIRTUAL_ADDR 0x541873C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_WIN_EN 0x5418740 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_LSB 0x5418750 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_MSB 0x5418754 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_LSB 0x5418758 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_MSB 0x541875C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_LSB 0x5418760 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_MSB 0x5418764 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_LSB 0x5418768 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_MSB 0x541876C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_LSB 0x5418770 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_MSB 0x5418774 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_LSB 0x5418778 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_MSB 0x541877C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_LSB 0x5418780 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_MSB 0x5418784 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_LSB 0x5418788 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_MSB 0x541878C + +#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_LSB 0x5418790 + +#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_MSB 0x5418794 + +#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_BRESP 0x5418798 + +#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_RRESP 0x541879C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_0 0x5418800 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_1 0x5418804 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_2 0x5418808 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_3 0x541880C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_4 0x5418810 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_5 0x5418814 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_6 0x5418818 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_7 0x541881C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_8 0x5418820 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_9 0x5418824 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_10 0x5418828 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_11 0x541882C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_12 0x5418830 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_13 0x5418834 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_14 0x5418838 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_15 0x541883C + +#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_AWADDR_ERR 0x5418840 + +#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_ARADDR_ERR 0x5418844 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_BRESP 0x5418848 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_RRESP 0x541884C + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_EN 0x5418850 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_SECURE_REGION 0x5418854 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT 0x5418900 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_CTL 0x5418904 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR_MSK 0x5418908 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR 0x541890C + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_BUSER 0x5418910 + +#define mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN 0x5418920 + +#endif /* ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h new file mode 100644 index 000000000..eaee29da4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h @@ -0,0 +1,905 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QPC0_REGS_H_ +#define ASIC_REG_NIC0_QPC0_REGS_H_ + +/* + ***************************************** + * NIC0_QPC0 + * (Prototype: NIC_QPC) + ***************************************** + */ + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000 + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004 + +#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008 + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010 + +#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020 + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024 + +#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028 + +#define mmNIC0_QPC0_AXI_PROT 0x541F030 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038 + +#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040 + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044 + +#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048 + +#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050 + +#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054 + +#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058 + +#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C + +#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060 + +#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064 + +#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068 + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070 + +#define mmNIC0_QPC0_GW_BUSY 0x541F080 + +#define mmNIC0_QPC0_GW_CTRL 0x541F084 + +#define mmNIC0_QPC0_GW_DATA_0 0x541F08C + +#define mmNIC0_QPC0_GW_DATA_1 0x541F090 + +#define mmNIC0_QPC0_GW_DATA_2 0x541F094 + +#define mmNIC0_QPC0_GW_DATA_3 0x541F098 + +#define mmNIC0_QPC0_GW_DATA_4 0x541F09C + +#define mmNIC0_QPC0_GW_DATA_5 0x541F0A0 + +#define mmNIC0_QPC0_GW_DATA_6 0x541F0A4 + +#define mmNIC0_QPC0_GW_DATA_7 0x541F0A8 + +#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC + +#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0 + +#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4 + +#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8 + +#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC + +#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0 + +#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4 + +#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8 + +#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC + +#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0 + +#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4 + +#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8 + +#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC + +#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0 + +#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4 + +#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8 + +#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC + +#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0 + +#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4 + +#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8 + +#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC + +#define mmNIC0_QPC0_GW_DATA_29 0x541F100 + +#define mmNIC0_QPC0_GW_DATA_30 0x541F104 + +#define mmNIC0_QPC0_GW_DATA_31 0x541F108 + +#define mmNIC0_QPC0_GW_MASK_0 0x541F124 + +#define mmNIC0_QPC0_GW_MASK_1 0x541F128 + +#define mmNIC0_QPC0_GW_MASK_2 0x541F12C + +#define mmNIC0_QPC0_GW_MASK_3 0x541F130 + +#define mmNIC0_QPC0_GW_MASK_4 0x541F134 + +#define mmNIC0_QPC0_GW_MASK_5 0x541F138 + +#define mmNIC0_QPC0_GW_MASK_6 0x541F13C + +#define mmNIC0_QPC0_GW_MASK_7 0x541F140 + +#define mmNIC0_QPC0_GW_MASK_8 0x541F144 + +#define mmNIC0_QPC0_GW_MASK_9 0x541F148 + +#define mmNIC0_QPC0_GW_MASK_10 0x541F14C + +#define mmNIC0_QPC0_GW_MASK_11 0x541F150 + +#define mmNIC0_QPC0_GW_MASK_12 0x541F154 + +#define mmNIC0_QPC0_GW_MASK_13 0x541F158 + +#define mmNIC0_QPC0_GW_MASK_14 0x541F15C + +#define mmNIC0_QPC0_GW_MASK_15 0x541F160 + +#define mmNIC0_QPC0_GW_MASK_16 0x541F164 + +#define mmNIC0_QPC0_GW_MASK_17 0x541F168 + +#define mmNIC0_QPC0_GW_MASK_18 0x541F16C + +#define mmNIC0_QPC0_GW_MASK_19 0x541F170 + +#define mmNIC0_QPC0_GW_MASK_20 0x541F174 + +#define mmNIC0_QPC0_GW_MASK_21 0x541F178 + +#define mmNIC0_QPC0_GW_MASK_22 0x541F17C + +#define mmNIC0_QPC0_GW_MASK_23 0x541F180 + +#define mmNIC0_QPC0_GW_MASK_24 0x541F184 + +#define mmNIC0_QPC0_GW_MASK_25 0x541F188 + +#define mmNIC0_QPC0_GW_MASK_26 0x541F18C + +#define mmNIC0_QPC0_GW_MASK_27 0x541F190 + +#define mmNIC0_QPC0_GW_MASK_28 0x541F194 + +#define mmNIC0_QPC0_GW_MASK_29 0x541F198 + +#define mmNIC0_QPC0_GW_MASK_30 0x541F19C + +#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0 + +#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC + +#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200 + +#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204 + +#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208 + +#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC + +#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC + +#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC + +#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC + +#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300 + +#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304 + +#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308 + +#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC + +#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC + +#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC + +#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400 + +#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404 + +#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408 + +#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C + +#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410 + +#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414 + +#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418 + +#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C + +#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420 + +#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424 + +#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428 + +#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C + +#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430 + +#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434 + +#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438 + +#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C + +#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440 + +#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444 + +#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448 + +#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C + +#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450 + +#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454 + +#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458 + +#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C + +#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460 + +#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464 + +#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468 + +#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C + +#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470 + +#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474 + +#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478 + +#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C + +#define mmNIC0_QPC0_DBG_INDICATION 0x541F480 + +#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484 + +#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488 + +#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C + +#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490 + +#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494 + +#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498 + +#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C + +#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0 + +#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC + +#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC + +#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC + +#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC + +#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC + +#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500 + +#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C + +#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648 + +#define mmNIC0_QPC0_DBG_CFG 0x541F64C + +#define mmNIC0_QPC0_RES_RING0_PI 0x541F650 + +#define mmNIC0_QPC0_RES_RING0_CI 0x541F654 + +#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658 + +#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C + +#define mmNIC0_QPC0_RES_RING1_CI 0x541F660 + +#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664 + +#define mmNIC0_QPC0_RES_RING2_PI 0x541F668 + +#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C + +#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670 + +#define mmNIC0_QPC0_RES_RING3_PI 0x541F674 + +#define mmNIC0_QPC0_RES_RING3_CI 0x541F678 + +#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C + +#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680 + +#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684 + +#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688 + +#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C + +#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690 + +#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694 + +#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698 + +#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C + +#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8 + +#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700 + +#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704 + +#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708 + +#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C + +#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834 + +#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838 + +#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C + +#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C + +#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850 + +#define mmNIC0_QPC0_LBW_PROT 0x541F858 + +#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C + +#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8 + +#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC + +#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0 + +#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C + +#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980 + +#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984 + +#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988 + +#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C + +#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990 + +#define mmNIC0_QPC0_WTD_CONFIG 0x541F994 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0 + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8 + +#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC + +#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8 + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0 + +#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4 + +#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8 + +#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0 + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4 + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8 + +#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54 + +#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8 + +#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h new file mode 100644 index 000000000..2153319a5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ +#define ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ + +/* + ***************************************** + * NIC0_UMR0_0_COMPLETION_QUEUE_CI_1 + * (Prototype: COMPLETION_QUEUE_CI) + ***************************************** + */ + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_NUMBER 0x5400180 + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX 0x5400184 + +#endif /* ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h new file mode 100644 index 000000000..de8eac74c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ +#define ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ + +/* + ***************************************** + * NIC0_UMR0_0_UNSECURE_DOORBELL0 + * (Prototype: NIC_UNSEC_DBELL) + ***************************************** + */ + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 0x5400000 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_SECOND32 0x5400004 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_THIRD32 0x5400008 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FOURTH32 0x540000C + +#endif /* ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h new file mode 100644 index 000000000..44182fc18 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_AUX_REGS_H_ +#define ASIC_REG_PCIE_AUX_REGS_H_ + +/* + ***************************************** + * PCIE_AUX + * (Prototype: PCIE_AUX) + ***************************************** + */ + +#define mmPCIE_AUX_APB_TIMEOUT 0x4C07004 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_0 0x4C07008 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_1 0x4C0700C + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_2 0x4C07010 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_3 0x4C07014 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_4 0x4C07018 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_5 0x4C0701C + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_6 0x4C07020 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_7 0x4C07024 + +#define mmPCIE_AUX_PHY_INIT 0x4C07100 + +#define mmPCIE_AUX_LTR_MAX_LATENCY 0x4C07138 + +#define mmPCIE_AUX_BAR0_START_L 0x4C07160 + +#define mmPCIE_AUX_BAR0_START_H 0x4C07164 + +#define mmPCIE_AUX_BAR1_START 0x4C07168 + +#define mmPCIE_AUX_BAR2_START_L 0x4C0716C + +#define mmPCIE_AUX_BAR2_START_H 0x4C07170 + +#define mmPCIE_AUX_BAR3_START 0x4C07174 + +#define mmPCIE_AUX_BAR4_START_L 0x4C07178 + +#define mmPCIE_AUX_BAR4_START_H 0x4C0717C + +#define mmPCIE_AUX_BAR5_START 0x4C07180 + +#define mmPCIE_AUX_BAR0_LIMIT_L 0x4C07184 + +#define mmPCIE_AUX_BAR0_LIMIT_H 0x4C07188 + +#define mmPCIE_AUX_BAR1_LIMIT 0x4C0718C + +#define mmPCIE_AUX_BAR2_LIMIT_L 0x4C07190 + +#define mmPCIE_AUX_BAR2_LIMIT_H 0x4C07194 + +#define mmPCIE_AUX_BAR3_LIMIT 0x4C07198 + +#define mmPCIE_AUX_BAR4_LIMIT_L 0x4C0719C + +#define mmPCIE_AUX_BAR4_LIMIT_H 0x4C07200 + +#define mmPCIE_AUX_BAR5_LIMIT 0x4C07204 + +#define mmPCIE_AUX_BUS_MASTER_EN 0x4C07208 + +#define mmPCIE_AUX_MEM_SPACE_EN 0x4C0720C + +#define mmPCIE_AUX_MAX_RD_REQ_SIZE 0x4C07210 + +#define mmPCIE_AUX_MAX_PAYLOAD_SIZE 0x4C07214 + +#define mmPCIE_AUX_EXT_TAG_EN 0x4C07218 + +#define mmPCIE_AUX_RCB 0x4C0721C + +#define mmPCIE_AUX_PM_NO_SOFT_RST 0x4C07220 + +#define mmPCIE_AUX_PBUS_NUM 0x4C07224 + +#define mmPCIE_AUX_PBUS_DEV_NUM 0x4C07228 + +#define mmPCIE_AUX_NO_SNOOP_EN 0x4C0722C + +#define mmPCIE_AUX_RELAX_ORDER_EN 0x4C07230 + +#define mmPCIE_AUX_HP_SLOT_CTRL_ACCESS 0x4C07234 + +#define mmPCIE_AUX_DLL_STATE_CHGED_EN 0x4C07238 + +#define mmPCIE_AUX_CMP_CPLED_INT_EN 0x4C0723C + +#define mmPCIE_AUX_HP_INT_EN 0x4C07340 + +#define mmPCIE_AUX_PRE_DET_CHGEN_EN 0x4C07344 + +#define mmPCIE_AUX_MRL_SENSOR_CHGED_EN 0x4C07348 + +#define mmPCIE_AUX_PWR_FAULT_DET_EN 0x4C0734C + +#define mmPCIE_AUX_ATTEN_BUTTON_PRESSED_EN 0x4C07350 + +#define mmPCIE_AUX_PF_FLR_ACTIVE 0x4C07360 + +#define mmPCIE_AUX_PF_FLR_DONE 0x4C07364 + +#define mmPCIE_AUX_FLR_INT 0x4C07390 + +#define mmPCIE_AUX_FLR_CTRL 0x4C07394 + +#define mmPCIE_AUX_LTR_M_EN 0x4C073B0 + +#define mmPCIE_AUX_LTSSM_EN 0x4C07428 + +#define mmPCIE_AUX_SYS_INTR 0x4C07440 + +#define mmPCIE_AUX_INT_DISABLE 0x4C07444 + +#define mmPCIE_AUX_SMLH_LINK_UP 0x4C07448 + +#define mmPCIE_AUX_PM_CURR_STATE 0x4C07450 + +#define mmPCIE_AUX_RDLH_LINK_UP 0x4C07458 + +#define mmPCIE_AUX_BRDG_SLV_XFER_PENDING 0x4C0745C + +#define mmPCIE_AUX_BRDG_DBI_XFER_PENDING 0x4C07460 + +#define mmPCIE_AUX_AUTO_SP_DIS 0x4C07478 + +#define mmPCIE_AUX_DBI 0x4C07490 + +#define mmPCIE_AUX_DBI_32 0x4C07494 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_0 0x4C074A4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_1 0x4C074A8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_2 0x4C074AC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_3 0x4C074B0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_4 0x4C074B4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_5 0x4C074B8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_6 0x4C074BC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_7 0x4C074C0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_8 0x4C074C4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_9 0x4C074C8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_10 0x4C074CC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_11 0x4C074D0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_12 0x4C074D4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_13 0x4C074D8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_14 0x4C074DC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_15 0x4C074E0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_16 0x4C074E4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_17 0x4C074E8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_18 0x4C074EC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_19 0x4C074F0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_20 0x4C074F4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_21 0x4C074F8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_22 0x4C074FC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_23 0x4C07500 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_24 0x4C07504 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_25 0x4C07508 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_26 0x4C0750C + +#define mmPCIE_AUX_DIAG_STATUS_BUS_27 0x4C07510 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_28 0x4C07514 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_0 0x4C07640 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_1 0x4C07644 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_2 0x4C07648 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_3 0x4C0764C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_4 0x4C07650 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_5 0x4C07654 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_6 0x4C07658 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_7 0x4C0765C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_8 0x4C07660 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_9 0x4C07664 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_10 0x4C07668 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_11 0x4C0766C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_12 0x4C07670 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_13 0x4C07674 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_14 0x4C07678 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_15 0x4C0767C + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_0 0x4C07744 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_1 0x4C07748 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_2 0x4C0774C + +#define mmPCIE_AUX_APP_RAS_DES_TBA_CTRL 0x4C07774 + +#define mmPCIE_AUX_PM_MASTER_STATE 0x4C07838 + +#define mmPCIE_AUX_PM_SLAVE_STATE 0x4C0783C + +#define mmPCIE_AUX_PM_DSTATE 0x4C07840 + +#define mmPCIE_AUX_PM_PME_EN 0x4C07844 + +#define mmPCIE_AUX_PM_LINKST_IN_L0S 0x4C07848 + +#define mmPCIE_AUX_PM_LINKST_IN_L1 0x4C0784C + +#define mmPCIE_AUX_PM_LINKST_IN_L2 0x4C07850 + +#define mmPCIE_AUX_PM_LINKST_L2_EXIT 0x4C07854 + +#define mmPCIE_AUX_PM_STATUS 0x4C07858 + +#define mmPCIE_AUX_APP_READY_ENTER_L23 0x4C0785C + +#define mmPCIE_AUX_APP_XFER_PENDING 0x4C07860 + +#define mmPCIE_AUX_APP_REQ_L1 0x4C07930 + +#define mmPCIE_AUX_AUX_PM_EN 0x4C07934 + +#define mmPCIE_AUX_APPS_PM_XMT_PME 0x4C07938 + +#define mmPCIE_AUX_OUTBAND_PWRUP_CMD 0x4C07940 + +#define mmPCIE_AUX_PERST 0x4C079B8 + +#define mmPCIE_AUX_DBI_RO_WR_DISABLE 0x4C079BC + +#define mmPCIE_AUX_HOLD_PHY_RST 0x4C079C0 + +#define mmPCIE_AUX_TLP_INTERNAL_ERR_REP 0x4C079C4 + +#define mmPCIE_AUX_APP_SRIS_MODE 0x4C079C8 + +#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR 0x4C079CC + +#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR_MASK 0x4C079D0 + +#endif /* ASIC_REG_PCIE_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h new file mode 100644 index 000000000..cc5842ec6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h @@ -0,0 +1,422 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DBI_REGS_H_ +#define ASIC_REG_PCIE_DBI_REGS_H_ + +/* + ***************************************** + * PCIE_DBI + * (Prototype: PCIE_DBI) + ***************************************** + */ + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000 + +#define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004 + +#define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008 + +#define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C + +#define mmPCIE_DBI_BAR0_REG 0x4C02010 + +#define mmPCIE_DBI_BAR1_REG 0x4C02014 + +#define mmPCIE_DBI_BAR2_REG 0x4C02018 + +#define mmPCIE_DBI_BAR3_REG 0x4C0201C + +#define mmPCIE_DBI_BAR4_REG 0x4C02020 + +#define mmPCIE_DBI_BAR5_REG 0x4C02024 + +#define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028 + +#define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C + +#define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030 + +#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034 + +#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG \ +0x4C0203C + +#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040 + +#define mmPCIE_DBI_CON_STATUS_REG 0x4C02044 + +#define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050 + +#define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054 + +#define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058 + +#define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C + +#define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060 + +#define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064 + +#define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070 + +#define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074 + +#define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078 + +#define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C + +#define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080 + +#define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094 + +#define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098 + +#define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C + +#define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0 + +#define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0 + +#define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4 + +#define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8 + +#define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100 + +#define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104 + +#define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108 + +#define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C + +#define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110 + +#define mmPCIE_DBI_CORR_ERR_MASK_OFF 0x4C02114 + +#define mmPCIE_DBI_ADV_ERR_CAP_CTRL_OFF 0x4C02118 + +#define mmPCIE_DBI_HDR_LOG_0_OFF 0x4C0211C + +#define mmPCIE_DBI_HDR_LOG_1_OFF 0x4C02120 + +#define mmPCIE_DBI_HDR_LOG_2_OFF 0x4C02124 + +#define mmPCIE_DBI_HDR_LOG_3_OFF 0x4C02128 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_1_OFF 0x4C02138 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_2_OFF 0x4C0213C + +#define mmPCIE_DBI_TLP_PREFIX_LOG_3_OFF 0x4C02140 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_4_OFF 0x4C02144 + +#define mmPCIE_DBI_SPCIE_CAP_HEADER_REG 0x4C02148 + +#define mmPCIE_DBI_LINK_CONTROL3_REG 0x4C0214C + +#define mmPCIE_DBI_LANE_ERR_STATUS_REG 0x4C02150 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_0CH_REG 0x4C02154 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_10H_REG 0x4C02158 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_14H_REG 0x4C0215C + +#define mmPCIE_DBI_SPCIE_CAP_OFF_18H_REG 0x4C02160 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_1CH_REG 0x4C02164 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_20H_REG 0x4C02168 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_24H_REG 0x4C0216C + +#define mmPCIE_DBI_SPCIE_CAP_OFF_28H_REG 0x4C02170 + +#define mmPCIE_DBI_PL16G_EXT_CAP_HDR_REG 0x4C02178 + +#define mmPCIE_DBI_PL16G_CAPABILITY_REG 0x4C0217C + +#define mmPCIE_DBI_PL16G_CONTROL_REG 0x4C02180 + +#define mmPCIE_DBI_PL16G_STATUS_REG 0x4C02184 + +#define mmPCIE_DBI_PL16G_LC_DPAR_STATUS_REG 0x4C02188 + +#define mmPCIE_DBI_PL16G_FIRST_RETIMER_DPAR_STATUS_REG 0x4C0218C + +#define mmPCIE_DBI_PL16G_SECOND_RETIMER_DPAR_STATUS_REG 0x4C02190 + +#define mmPCIE_DBI_PL16G_CAP_OFF_20H_REG 0x4C02198 + +#define mmPCIE_DBI_PL16G_CAP_OFF_24H_REG 0x4C0219C + +#define mmPCIE_DBI_PL16G_CAP_OFF_28H_REG 0x4C021A0 + +#define mmPCIE_DBI_PL16G_CAP_OFF_2CH_REG 0x4C021A4 + +#define mmPCIE_DBI_MARGIN_EXT_CAP_HDR_REG 0x4C021A8 + +#define mmPCIE_DBI_MARGIN_PORT_CAPABILITIES_STATUS_REG 0x4C021AC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS0_REG 0x4C021B0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS1_REG 0x4C021B4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS2_REG 0x4C021B8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS3_REG 0x4C021BC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS4_REG 0x4C021C0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS5_REG 0x4C021C4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS6_REG 0x4C021C8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS7_REG 0x4C021CC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS8_REG 0x4C021D0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS9_REG 0x4C021D4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS10_REG 0x4C021D8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS11_REG 0x4C021DC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS12_REG 0x4C021E0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS13_REG 0x4C021E4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS14_REG 0x4C021E8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS15_REG 0x4C021EC + +#define mmPCIE_DBI_LTR_CAP_HDR_REG 0x4C021F0 + +#define mmPCIE_DBI_LTR_LATENCY_REG 0x4C021F4 + +#define mmPCIE_DBI_RAS_DES_CAP_HEADER_REG 0x4C021F8 + +#define mmPCIE_DBI_VENDOR_SPECIFIC_HEADER_REG 0x4C021FC + +#define mmPCIE_DBI_EVENT_COUNTER_CONTROL_REG 0x4C02200 + +#define mmPCIE_DBI_EVENT_COUNTER_DATA_REG 0x4C02204 + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_CONTROL_REG 0x4C02208 + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_REG 0x4C0220C + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_63_32_REG 0x4C02210 + +#define mmPCIE_DBI_EINJ_ENABLE_REG 0x4C02228 + +#define mmPCIE_DBI_EINJ0_CRC_REG 0x4C0222C + +#define mmPCIE_DBI_EINJ1_SEQNUM_REG 0x4C02230 + +#define mmPCIE_DBI_EINJ2_DLLP_REG 0x4C02234 + +#define mmPCIE_DBI_EINJ3_SYMBOL_REG 0x4C02238 + +#define mmPCIE_DBI_EINJ4_FC_REG 0x4C0223C + +#define mmPCIE_DBI_EINJ5_SP_TLP_REG 0x4C02240 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H0_REG 0x4C02244 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H1_REG 0x4C02248 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H2_REG 0x4C0224C + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H3_REG 0x4C02250 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H0_REG 0x4C02254 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H1_REG 0x4C02258 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H2_REG 0x4C0225C + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H3_REG 0x4C02260 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H0_REG 0x4C02264 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H1_REG 0x4C02268 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H2_REG 0x4C0226C + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H3_REG 0x4C02270 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H0_REG 0x4C02274 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H1_REG 0x4C02278 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H2_REG 0x4C0227C + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H3_REG 0x4C02280 + +#define mmPCIE_DBI_EINJ6_TLP_REG 0x4C02284 + +#define mmPCIE_DBI_SD_CONTROL1_REG 0x4C02298 + +#define mmPCIE_DBI_SD_CONTROL2_REG 0x4C0229C + +#define mmPCIE_DBI_SD_STATUS_L1LANE_REG 0x4C022A8 + +#define mmPCIE_DBI_SD_STATUS_L1LTSSM_REG 0x4C022AC + +#define mmPCIE_DBI_SD_STATUS_PM_REG 0x4C022B0 + +#define mmPCIE_DBI_SD_STATUS_L2_REG 0x4C022B4 + +#define mmPCIE_DBI_SD_STATUS_L3FC_REG 0x4C022B8 + +#define mmPCIE_DBI_SD_STATUS_L3_REG 0x4C022BC + +#define mmPCIE_DBI_SD_EQ_CONTROL1_REG 0x4C022C8 + +#define mmPCIE_DBI_SD_EQ_CONTROL2_REG 0x4C022CC + +#define mmPCIE_DBI_SD_EQ_CONTROL3_REG 0x4C022D0 + +#define mmPCIE_DBI_SD_EQ_STATUS1_REG 0x4C022D8 + +#define mmPCIE_DBI_SD_EQ_STATUS2_REG 0x4C022DC + +#define mmPCIE_DBI_SD_EQ_STATUS3_REG 0x4C022E0 + +#define mmPCIE_DBI_DATA_LINK_FEATURE_EXT_HDR_OFF 0x4C022F8 + +#define mmPCIE_DBI_DATA_LINK_FEATURE_CAP_OFF 0x4C022FC + +#define mmPCIE_DBI_DATA_LINK_FEATURE_STATUS_OFF 0x4C02300 + +#define mmPCIE_DBI_ACK_LATENCY_TIMER_OFF 0x4C02700 + +#define mmPCIE_DBI_VENDOR_SPEC_DLLP_OFF 0x4C02704 + +#define mmPCIE_DBI_PORT_FORCE_OFF 0x4C02708 + +#define mmPCIE_DBI_ACK_F_ASPM_CTRL_OFF 0x4C0270C + +#define mmPCIE_DBI_PORT_LINK_CTRL_OFF 0x4C02710 + +#define mmPCIE_DBI_LANE_SKEW_OFF 0x4C02714 + +#define mmPCIE_DBI_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x4C02718 + +#define mmPCIE_DBI_SYMBOL_TIMER_FILTER_1_OFF 0x4C0271C + +#define mmPCIE_DBI_FILTER_MASK_2_OFF 0x4C02720 + +#define mmPCIE_DBI_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF 0x4C02724 + +#define mmPCIE_DBI_PL_DEBUG0_OFF 0x4C02728 + +#define mmPCIE_DBI_PL_DEBUG1_OFF 0x4C0272C + +#define mmPCIE_DBI_TX_P_FC_CREDIT_STATUS_OFF 0x4C02730 + +#define mmPCIE_DBI_TX_NP_FC_CREDIT_STATUS_OFF 0x4C02734 + +#define mmPCIE_DBI_TX_CPL_FC_CREDIT_STATUS_OFF 0x4C02738 + +#define mmPCIE_DBI_QUEUE_STATUS_OFF 0x4C0273C + +#define mmPCIE_DBI_VC_TX_ARBI_1_OFF 0x4C02740 + +#define mmPCIE_DBI_VC_TX_ARBI_2_OFF 0x4C02744 + +#define mmPCIE_DBI_VC0_P_RX_Q_CTRL_OFF 0x4C02748 + +#define mmPCIE_DBI_VC0_NP_RX_Q_CTRL_OFF 0x4C0274C + +#define mmPCIE_DBI_VC0_CPL_RX_Q_CTRL_OFF 0x4C02750 + +#define mmPCIE_DBI_GEN2_CTRL_OFF 0x4C0280C + +#define mmPCIE_DBI_PHY_STATUS_OFF 0x4C02810 + +#define mmPCIE_DBI_PHY_CONTROL_OFF 0x4C02814 + +#define mmPCIE_DBI_TRGT_MAP_CTRL_OFF 0x4C0281C + +#define mmPCIE_DBI_CLOCK_GATING_CTRL_OFF 0x4C0288C + +#define mmPCIE_DBI_GEN3_RELATED_OFF 0x4C02890 + +#define mmPCIE_DBI_GEN3_EQ_CONTROL_OFF 0x4C028A8 + +#define mmPCIE_DBI_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x4C028AC + +#define mmPCIE_DBI_ORDER_RULE_CTRL_OFF 0x4C028B4 + +#define mmPCIE_DBI_PIPE_LOOPBACK_CONTROL_OFF 0x4C028B8 + +#define mmPCIE_DBI_MISC_CONTROL_1_OFF 0x4C028BC + +#define mmPCIE_DBI_MULTI_LANE_CONTROL_OFF 0x4C028C0 + +#define mmPCIE_DBI_PHY_INTEROP_CTRL_OFF 0x4C028C4 + +#define mmPCIE_DBI_TRGT_CPL_LUT_DELETE_ENTRY_OFF 0x4C028C8 + +#define mmPCIE_DBI_LINK_FLUSH_CONTROL_OFF 0x4C028CC + +#define mmPCIE_DBI_AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x4C028D0 + +#define mmPCIE_DBI_AMBA_LINK_TIMEOUT_OFF 0x4C028D4 + +#define mmPCIE_DBI_AMBA_ORDERING_CTRL_OFF 0x4C028D8 + +#define mmPCIE_DBI_COHERENCY_CONTROL_1_OFF 0x4C028E0 + +#define mmPCIE_DBI_COHERENCY_CONTROL_2_OFF 0x4C028E4 + +#define mmPCIE_DBI_COHERENCY_CONTROL_3_OFF 0x4C028E8 + +#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_LOW_OFF 0x4C028F0 + +#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_HIGH_OFF 0x4C028F4 + +#define mmPCIE_DBI_PCIE_VERSION_NUMBER_OFF 0x4C028F8 + +#define mmPCIE_DBI_PCIE_VERSION_TYPE_OFF 0x4C028FC + +#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF 0x4C02940 + +#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_HIGH_OFF 0x4C02944 + +#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0x4C02948 + +#define mmPCIE_DBI_MSIX_RAM_CTRL_OFF 0x4C0294C + +#define mmPCIE_DBI_PL_LTR_LATENCY_OFF 0x4C02B30 + +#define mmPCIE_DBI_AUX_CLK_FREQ_OFF 0x4C02B40 + +#define mmPCIE_DBI_POWERDOWN_CTRL_STATUS_OFF 0x4C02B48 + +#define mmPCIE_DBI_PHY_VIEWPORT_CTLSTS_OFF 0x4C02B70 + +#define mmPCIE_DBI_PHY_VIEWPORT_DATA_OFF 0x4C02B74 + +#define mmPCIE_DBI_GEN4_LANE_MARGINING_1_OFF 0x4C02B80 + +#define mmPCIE_DBI_GEN4_LANE_MARGINING_2_OFF 0x4C02B84 + +#define mmPCIE_DBI_PIPE_RELATED_OFF 0x4C02B90 + +#define mmPCIE_DBI_RX_SERIALIZATION_Q_CTRL_OFF 0x4C02C00 + +#endif /* ASIC_REG_PCIE_DBI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h new file mode 100644 index 000000000..2b5af010c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ +#define ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ + +/* + ***************************************** + * PCIE_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +/* PCIE_DEC0_CMD_SWREG0 */ +#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG1 */ +#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG2 */ +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG3 */ +#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG4 */ +#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG5 */ +#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG6 */ +#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG7 */ +#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG8 */ +#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG9 */ +#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG10 */ +#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG11 */ +#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG12 */ +#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG13 */ +#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG14 */ +#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG15 */ +#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 +#define PCIE_DEC0_CMD_SWREG15_RSV_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 + +/* PCIE_DEC0_CMD_SWREG16 */ +#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG16_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG17 */ +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG17_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG18 */ +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG18_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG19 */ +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 + +/* PCIE_DEC0_CMD_SWREG20 */ +#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG21 */ +#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG22 */ +#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG22_RSV_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG23 */ +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 +#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 +#define PCIE_DEC0_CMD_SWREG23_RSV_SHIFT 24 +#define PCIE_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 +#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 +#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 + +/* PCIE_DEC0_CMD_SWREG24 */ +#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG25 */ +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG26 */ +#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG64 */ +#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG65 */ +#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG66 */ +#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG67 */ +#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h new file mode 100644 index 000000000..dc7d3f6a4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_ +#define ASIC_REG_PCIE_DEC0_CMD_REGS_H_ + +/* + ***************************************** + * PCIE_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +#define mmPCIE_DEC0_CMD_SWREG0 0x4F00000 + +#define mmPCIE_DEC0_CMD_SWREG1 0x4F00004 + +#define mmPCIE_DEC0_CMD_SWREG2 0x4F00008 + +#define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C + +#define mmPCIE_DEC0_CMD_SWREG4 0x4F00010 + +#define mmPCIE_DEC0_CMD_SWREG5 0x4F00014 + +#define mmPCIE_DEC0_CMD_SWREG6 0x4F00018 + +#define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C + +#define mmPCIE_DEC0_CMD_SWREG8 0x4F00020 + +#define mmPCIE_DEC0_CMD_SWREG9 0x4F00024 + +#define mmPCIE_DEC0_CMD_SWREG10 0x4F00028 + +#define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C + +#define mmPCIE_DEC0_CMD_SWREG12 0x4F00030 + +#define mmPCIE_DEC0_CMD_SWREG13 0x4F00034 + +#define mmPCIE_DEC0_CMD_SWREG14 0x4F00038 + +#define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C + +#define mmPCIE_DEC0_CMD_SWREG16 0x4F00040 + +#define mmPCIE_DEC0_CMD_SWREG17 0x4F00044 + +#define mmPCIE_DEC0_CMD_SWREG18 0x4F00048 + +#define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C + +#define mmPCIE_DEC0_CMD_SWREG20 0x4F00050 + +#define mmPCIE_DEC0_CMD_SWREG21 0x4F00054 + +#define mmPCIE_DEC0_CMD_SWREG22 0x4F00058 + +#define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C + +#define mmPCIE_DEC0_CMD_SWREG24 0x4F00060 + +#define mmPCIE_DEC0_CMD_SWREG25 0x4F00064 + +#define mmPCIE_DEC0_CMD_SWREG26 0x4F00068 + +#define mmPCIE_DEC0_CMD_SWREG64 0x4F00100 + +#define mmPCIE_DEC0_CMD_SWREG65 0x4F00104 + +#define mmPCIE_DEC0_CMD_SWREG66 0x4F00108 + +#define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C + +#endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h new file mode 100644 index 000000000..242c6525b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x4F03C00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x4F03C04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x4F03C08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x4F03C0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x4F03C10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x4F03C14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x4F03C18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x4F03C1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x4F03C20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x4F03C24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x4F03C28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x4F03C30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x4F03C34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x4F03C38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x4F03C3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x4F03C40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x4F03C44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x4F03C48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x4F03C4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h new file mode 100644 index 000000000..98d035463 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x4F03B00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x4F03B04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x4F03B08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x4F03B0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x4F03B10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x4F03B14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x4F03B18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x4F03B1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x4F03B20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x4F03B24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x4F03B28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x4F03B30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x4F03B34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x4F03B38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x4F03B3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x4F03B40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x4F03B44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x4F03B48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x4F03B4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h new file mode 100644 index 000000000..33ef37619 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x4F03900 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x4F03904 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x4F03908 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x4F0390C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x4F03910 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x4F03914 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x4F03918 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x4F0391C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x4F03920 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x4F03924 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x4F03928 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x4F03930 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x4F03934 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x4F03938 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x4F0393C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x4F03940 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x4F03944 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x4F03948 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x4F0394C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h new file mode 100644 index 000000000..c4587d5d6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x4F03A00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x4F03A04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x4F03A08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x4F03A0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x4F03A10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x4F03A14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x4F03A18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x4F03A1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x4F03A20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x4F03A24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x4F03A28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x4F03A30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x4F03A34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x4F03A38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x4F03A3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x4F03A40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x4F03A44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x4F03A48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x4F03A4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h new file mode 100644 index 000000000..35349ad37 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x4F03800 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x4F03804 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x4F03808 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x4F0380C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x4F03810 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x4F03814 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x4F03818 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x4F0381C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x4F03820 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x4F03824 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x4F03828 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x4F03830 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x4F03834 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x4F03838 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x4F0383C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x4F03840 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x4F03844 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x4F03848 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x4F0384C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h new file mode 100644 index 000000000..d29837883 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +/* PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE */ +#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_IDLE_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_GRACEFUL */ +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 + +/* PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR */ +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 + +/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \ +0x100 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 + +/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 + +/* PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 + +/* PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC + +/* PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h new file mode 100644 index 000000000..c7badd212 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_CGM_DISABLE 0x4F03100 + +#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_MASK 0x4F03104 + +#define mmPCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x4F03108 + +#define mmPCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x4F0310C + +#define mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL 0x4F03110 + +#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x4F03114 + +#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR 0x4F03120 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x4F03124 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x4F03128 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x4F0312C + +#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x4F03130 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x4F03134 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x4F03138 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x4F03160 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x4F03170 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x4F03180 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x4F03190 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x4F031A0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x4F031A4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x4F031B0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x4F031B4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x4F031C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x4F031C4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x4F031D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x4F03200 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x4F03230 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x4F03260 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x4F03270 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x4F03280 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x4F03290 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x4F03294 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x4F032A0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x4F032A4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x4F032B0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x4F032B4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x4F032C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x4F032C4 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x4F032D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x4F03300 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x4F03310 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x4F03320 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x4F03330 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x4F03334 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x4F03338 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x4F03340 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x4F03350 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x4F03360 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x4F03380 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x4F03390 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x4F03394 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x4F033C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x4F033D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x4F033E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x4F03400 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x4F03410 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x4F03420 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x4F03430 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x4F03434 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x4F03438 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x4F03440 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x4F03450 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x4F03460 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x4F03480 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x4F03490 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x4F03494 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x4F034C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x4F034D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x4F034E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x4F03500 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x4F03510 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x4F03520 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x4F03530 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x4F03534 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x4F03538 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x4F03540 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x4F03550 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x4F03560 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x4F03580 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x4F03590 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x4F03594 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x4F035C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x4F035D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x4F035E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x4F03600 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x4F03610 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x4F03620 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x4F03630 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x4F03634 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x4F03638 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x4F03640 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x4F03650 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x4F03660 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x4F03680 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x4F03690 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x4F03694 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x4F036C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x4F036D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x4F036E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x4F03700 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x4F03704 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x4F03708 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x4F0370C + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x4F03714 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x4F03718 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x4F0371C + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x4F03720 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x4F03724 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x4F03728 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x4F0372C + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x4F03730 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x4F03734 + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h new file mode 100644 index 000000000..491b0cd93 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_CTRL_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x4F04E80 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x4F04E84 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x4F04E88 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x4F04E8C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x4F04E90 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x4F04E94 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x4F04E98 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x4F04E9C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x4F04EA0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x4F04EA4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x4F04EA8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x4F04EAC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x4F04EB0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x4F04EB4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x4F04EB8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x4F04EBC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x4F04EC0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x4F04EC4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x4F04EC8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x4F04ECC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x4F04ED0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x4F04ED4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x4F04ED8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x4F04EDC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x4F04EE0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x4F04EE4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x4F04EE8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x4F04EEC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x4F04EF0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x4F04EF4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x4F04EF8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x4F04EFC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x4F04F00 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x4F04F04 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x4F04F0C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x4F04F10 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x4F04F14 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x4F04F18 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4F04F1C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x4F04F20 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x4F04F24 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_RM 0x4F04F28 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x4F04F40 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x4F04F44 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x4F04F48 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x4F04F60 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x4F04F64 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x4F04F68 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x4F04F6C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x4F04F80 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x4F04F84 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x4F04F88 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x4F04F8C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x4F04F90 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x4F04F94 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x4F04F98 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x4F04F9C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x4F04FA0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x4F04FA4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x4F04FA8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x4F04FAC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x4F04FB0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x4F04FB4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x4F04FB8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x4F04FBC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x4F04FC0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x4F04FC4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x4F04FC8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x4F04FCC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x4F04FD0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x4F04FD4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x4F04FD8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x4F04FDC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x4F04FE0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x4F04FE4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x4F04FE8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x4F04FEC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x4F04FF0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x4F04FF4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x4F04FF8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x4F04FFC + +#endif /* ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h new file mode 100644 index 000000000..a09422f2f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h @@ -0,0 +1,601 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_WRAP_REGS_H_ +#define ASIC_REG_PCIE_WRAP_REGS_H_ + +/* + ***************************************** + * PCIE_WRAP + * (Prototype: PCIE_WRAP) + ***************************************** + */ + +#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_0 0x4C01000 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_1 0x4C01004 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_0 0x4C01008 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_1 0x4C0100C + +#define mmPCIE_WRAP_INTR_GEN_MASK_TIMER 0x4C01010 + +#define mmPCIE_WRAP_INTR_GEN_MASK_CTRL 0x4C01014 + +#define mmPCIE_WRAP_MSIX_DOORBELL_OFF_ADDR 0x4C01018 + +#define mmPCIE_WRAP_MSIX_MASK_CTRL 0x4C0101C + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_0 0x4C01020 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_1 0x4C01024 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_0 0x4C01028 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_1 0x4C0102C + +#define mmPCIE_WRAP_PHY_FW_SRAM_CFG_ADDR 0x4C01030 + +#define mmPCIE_WRAP_MSIX_GW 0x4C01034 + +#define mmPCIE_WRAP_MSIX_GW_VEC 0x4C01038 + +#define mmPCIE_WRAP_MSIX_GW_INTR 0x4C0103C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_0 0x4C01040 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_1 0x4C01044 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_2 0x4C01048 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_3 0x4C0104C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_4 0x4C01050 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_5 0x4C01054 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_6 0x4C01058 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_7 0x4C0105C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_8 0x4C01060 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_9 0x4C01064 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_10 0x4C01068 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_11 0x4C0106C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_12 0x4C01070 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_13 0x4C01074 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_14 0x4C01078 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_15 0x4C0107C + +#define mmPCIE_WRAP_VUART_RX_0 0x4C01100 + +#define mmPCIE_WRAP_VUART_RX_1 0x4C01104 + +#define mmPCIE_WRAP_VUART_RX_2 0x4C01108 + +#define mmPCIE_WRAP_VUART_TX_0 0x4C0110C + +#define mmPCIE_WRAP_VUART_TX_1 0x4C01110 + +#define mmPCIE_WRAP_VUART_TX_2 0x4C01114 + +#define mmPCIE_WRAP_MSI_GW_BLOCK 0x4C01120 + +#define mmPCIE_WRAP_PHY_FW_FSM_SIZE 0x4C0120C + +#define mmPCIE_WRAP_HOST_ACCESS_TERMINATION 0x4C01210 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_CTRL 0x4C01214 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_0 0x4C01218 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_1 0x4C0121C + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_INTR 0x4C01220 + +#define mmPCIE_WRAP_OUTBOUND_ADDR_LSB 0x4C01224 + +#define mmPCIE_WRAP_LBW_WSTRB_OVRD 0x4C01228 + +#define mmPCIE_WRAP_LBW_GW_ADDR_0 0x4C01304 + +#define mmPCIE_WRAP_LBW_GW_ADDR_1 0x4C01308 + +#define mmPCIE_WRAP_LBW_GW_ADDR_2 0x4C0130C + +#define mmPCIE_WRAP_LBW_GW_ADDR_3 0x4C01310 + +#define mmPCIE_WRAP_LBW_GW_ADDR_4 0x4C01314 + +#define mmPCIE_WRAP_LBW_GW_ADDR_5 0x4C01318 + +#define mmPCIE_WRAP_LBW_GW_ADDR_6 0x4C0131C + +#define mmPCIE_WRAP_LBW_GW_ADDR_7 0x4C01320 + +#define mmPCIE_WRAP_LBW_GW_DATA_0 0x4C01324 + +#define mmPCIE_WRAP_LBW_GW_DATA_1 0x4C01328 + +#define mmPCIE_WRAP_LBW_GW_DATA_2 0x4C0132C + +#define mmPCIE_WRAP_LBW_GW_DATA_3 0x4C01330 + +#define mmPCIE_WRAP_LBW_GW_DATA_4 0x4C01334 + +#define mmPCIE_WRAP_LBW_GW_DATA_5 0x4C01338 + +#define mmPCIE_WRAP_LBW_GW_DATA_6 0x4C0133C + +#define mmPCIE_WRAP_LBW_GW_DATA_7 0x4C01340 + +#define mmPCIE_WRAP_LBW_GW_GO_0 0x4C01344 + +#define mmPCIE_WRAP_LBW_GW_GO_1 0x4C01348 + +#define mmPCIE_WRAP_LBW_GW_GO_2 0x4C0134C + +#define mmPCIE_WRAP_LBW_GW_GO_3 0x4C01350 + +#define mmPCIE_WRAP_LBW_GW_GO_4 0x4C01354 + +#define mmPCIE_WRAP_LBW_GW_GO_5 0x4C01358 + +#define mmPCIE_WRAP_LBW_GW_GO_6 0x4C0135C + +#define mmPCIE_WRAP_LBW_GW_GO_7 0x4C01360 + +#define mmPCIE_WRAP_LBW_GW_STATUS_0 0x4C01364 + +#define mmPCIE_WRAP_LBW_GW_STATUS_1 0x4C01368 + +#define mmPCIE_WRAP_LBW_GW_STATUS_2 0x4C0136C + +#define mmPCIE_WRAP_LBW_GW_STATUS_3 0x4C01370 + +#define mmPCIE_WRAP_LBW_GW_STATUS_4 0x4C01374 + +#define mmPCIE_WRAP_LBW_GW_STATUS_5 0x4C01378 + +#define mmPCIE_WRAP_LBW_GW_STATUS_6 0x4C0137C + +#define mmPCIE_WRAP_LBW_GW_STATUS_7 0x4C01380 + +#define mmPCIE_WRAP_OUTBOUND_OUTSTANDING 0x4C013F4 + +#define mmPCIE_WRAP_MASK_REQ 0x4C01404 + +#define mmPCIE_WRAP_ONE_IN_FLIGHT 0x4C01408 + +#define mmPCIE_WRAP_IND_AWPROT 0x4C0140C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO 0x4C01500 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_0 0x4C01504 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_1 0x4C01508 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_P_TAG 0x4C0150C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_ATU_BYPAS 0x4C01510 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_FUNC_NUM 0x4C01514 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_ACT 0x4C01518 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_NUM 0x4C0151C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_TLPPRFX 0x4C01520 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO 0x4C01524 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_TLPPRFX 0x4C01528 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_ATU_BYP 0x4C0152C + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_FUNC_NUM 0x4C01530 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_ACT 0x4C01534 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_NUM 0x4C01538 + +#define mmPCIE_WRAP_MESO_FIFO_CTRL_0 0x4C01640 + +#define mmPCIE_WRAP_MESO_FIFO_CTRL_1 0x4C01644 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_0 0x4C01648 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_1 0x4C0164C + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_0 0x4C01650 + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_1 0x4C01654 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_0 0x4C01658 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_1 0x4C0165C + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_0 0x4C01660 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_1 0x4C01664 + +#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_0 0x4C01668 + +#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_1 0x4C0166C + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_0 0x4C01670 + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_1 0x4C01674 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_0 0x4C01678 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_1 0x4C0167C + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_0 0x4C01680 + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_1 0x4C01684 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_0 0x4C01688 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_1 0x4C0168C + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_0 0x4C01690 + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_1 0x4C01694 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_0 0x4C01698 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_1 0x4C0169C + +#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_0 0x4C016A0 + +#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_1 0x4C016A4 + +#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_0 0x4C016A8 + +#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_1 0x4C016AC + +#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_0 0x4C016B0 + +#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_1 0x4C016B4 + +#define mmPCIE_WRAP_P2P_TABLE_0 0x4C01900 + +#define mmPCIE_WRAP_P2P_TABLE_1 0x4C01904 + +#define mmPCIE_WRAP_P2P_TABLE_2 0x4C01908 + +#define mmPCIE_WRAP_P2P_TABLE_3 0x4C0190C + +#define mmPCIE_WRAP_P2P_TABLE_4 0x4C01910 + +#define mmPCIE_WRAP_P2P_TABLE_5 0x4C01914 + +#define mmPCIE_WRAP_P2P_TABLE_6 0x4C01918 + +#define mmPCIE_WRAP_P2P_TABLE_7 0x4C0191C + +#define mmPCIE_WRAP_P2P_TABLE_8 0x4C01920 + +#define mmPCIE_WRAP_P2P_TABLE_9 0x4C01924 + +#define mmPCIE_WRAP_P2P_TABLE_10 0x4C01928 + +#define mmPCIE_WRAP_P2P_TABLE_11 0x4C0192C + +#define mmPCIE_WRAP_P2P_TABLE_12 0x4C01930 + +#define mmPCIE_WRAP_P2P_TABLE_13 0x4C01934 + +#define mmPCIE_WRAP_P2P_TABLE_14 0x4C01938 + +#define mmPCIE_WRAP_P2P_TABLE_15 0x4C0193C + +#define mmPCIE_WRAP_P2P_TABLE_16 0x4C01940 + +#define mmPCIE_WRAP_P2P_TABLE_17 0x4C01944 + +#define mmPCIE_WRAP_P2P_TABLE_18 0x4C01948 + +#define mmPCIE_WRAP_P2P_TABLE_19 0x4C0194C + +#define mmPCIE_WRAP_P2P_TABLE_20 0x4C01950 + +#define mmPCIE_WRAP_P2P_TABLE_21 0x4C01954 + +#define mmPCIE_WRAP_P2P_TABLE_22 0x4C01958 + +#define mmPCIE_WRAP_P2P_TABLE_23 0x4C0195C + +#define mmPCIE_WRAP_P2P_TABLE_24 0x4C01960 + +#define mmPCIE_WRAP_P2P_TABLE_25 0x4C01964 + +#define mmPCIE_WRAP_P2P_TABLE_26 0x4C01968 + +#define mmPCIE_WRAP_P2P_TABLE_27 0x4C0196C + +#define mmPCIE_WRAP_P2P_TABLE_28 0x4C01970 + +#define mmPCIE_WRAP_P2P_TABLE_29 0x4C01974 + +#define mmPCIE_WRAP_P2P_TABLE_30 0x4C01978 + +#define mmPCIE_WRAP_P2P_TABLE_31 0x4C0197C + +#define mmPCIE_WRAP_P2P_TABLE_32 0x4C01980 + +#define mmPCIE_WRAP_P2P_TABLE_33 0x4C01984 + +#define mmPCIE_WRAP_P2P_TABLE_34 0x4C01988 + +#define mmPCIE_WRAP_P2P_TABLE_35 0x4C0198C + +#define mmPCIE_WRAP_P2P_TABLE_36 0x4C01990 + +#define mmPCIE_WRAP_P2P_TABLE_37 0x4C01994 + +#define mmPCIE_WRAP_P2P_TABLE_38 0x4C01998 + +#define mmPCIE_WRAP_P2P_TABLE_39 0x4C0199C + +#define mmPCIE_WRAP_P2P_TABLE_40 0x4C019A0 + +#define mmPCIE_WRAP_P2P_TABLE_41 0x4C019A4 + +#define mmPCIE_WRAP_P2P_TABLE_42 0x4C019A8 + +#define mmPCIE_WRAP_P2P_TABLE_43 0x4C019AC + +#define mmPCIE_WRAP_P2P_TABLE_44 0x4C019B0 + +#define mmPCIE_WRAP_P2P_TABLE_45 0x4C019B4 + +#define mmPCIE_WRAP_P2P_TABLE_46 0x4C019B8 + +#define mmPCIE_WRAP_P2P_TABLE_47 0x4C019BC + +#define mmPCIE_WRAP_P2P_TABLE_48 0x4C019C0 + +#define mmPCIE_WRAP_P2P_TABLE_49 0x4C019C4 + +#define mmPCIE_WRAP_P2P_TABLE_50 0x4C019C8 + +#define mmPCIE_WRAP_P2P_TABLE_51 0x4C019CC + +#define mmPCIE_WRAP_P2P_TABLE_52 0x4C019D0 + +#define mmPCIE_WRAP_P2P_TABLE_53 0x4C019D4 + +#define mmPCIE_WRAP_P2P_TABLE_54 0x4C019D8 + +#define mmPCIE_WRAP_P2P_TABLE_55 0x4C019DC + +#define mmPCIE_WRAP_P2P_TABLE_56 0x4C019E0 + +#define mmPCIE_WRAP_P2P_TABLE_57 0x4C019E4 + +#define mmPCIE_WRAP_P2P_TABLE_58 0x4C019E8 + +#define mmPCIE_WRAP_P2P_TABLE_59 0x4C019EC + +#define mmPCIE_WRAP_P2P_TABLE_60 0x4C019F0 + +#define mmPCIE_WRAP_P2P_TABLE_61 0x4C019F4 + +#define mmPCIE_WRAP_P2P_TABLE_62 0x4C019F8 + +#define mmPCIE_WRAP_P2P_TABLE_63 0x4C019FC + +#define mmPCIE_WRAP_P2P_EN 0x4C01A00 + +#define mmPCIE_WRAP_P2P_REQ_ID 0x4C01A04 + +#define mmPCIE_WRAP_P2P_INTR 0x4C01A08 + +#define mmPCIE_WRAP_P2P_TERMINATE_RESP 0x4C01A0C + +#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CTRL 0x4C01A10 + +#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CNT 0x4C01A14 + +#define mmPCIE_WRAP_CPU_HOT_RST 0x4C01AE0 + +#define mmPCIE_WRAP_LBW_AXI_SPLIT_MAX_OUTSTAN 0x4C01B2C + +#define mmPCIE_WRAP_AXI_SPLIT_NO_WR_INFLIGHT 0x4C01B30 + +#define mmPCIE_WRAP_PCIE_WR_BUF 0x4C01B34 + +#define mmPCIE_WRAP_PCIE_CACHE_OVR 0x4C01B38 + +#define mmPCIE_WRAP_PCIE_LOCK_OVR 0x4C01B3C + +#define mmPCIE_WRAP_PCIE_PROT_OVR 0x4C01B40 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_0 0x4C01B44 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_1 0x4C01B48 + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_0 0x4C01B4C + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_1 0x4C01B50 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_0 0x4C01B54 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_1 0x4C01B58 + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_0 0x4C01B5C + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_1 0x4C01B60 + +#define mmPCIE_WRAP_PCIE_MAX_OUTSTAND 0x4C01B64 + +#define mmPCIE_WRAP_PCIE_MST_IN 0x4C01B68 + +#define mmPCIE_WRAP_PCIE_RSP_OK 0x4C01B6C + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_0 0x4C01B70 + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_1 0x4C01B74 + +#define mmPCIE_WRAP_AXI_DRAIN_MSTR_IF_CFG_0 0x4C01B7C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_0 0x4C01B80 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_1 0x4C01B84 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_2 0x4C01B88 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_3 0x4C01B8C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_4 0x4C01B90 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_5 0x4C01B94 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_6 0x4C01B98 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_7 0x4C01B9C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_8 0x4C01BA0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_9 0x4C01BA4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_10 0x4C01BA8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_11 0x4C01BAC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_12 0x4C01BB0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_13 0x4C01BB4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_14 0x4C01BB8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_15 0x4C01BBC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_16 0x4C01BC0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_17 0x4C01BC4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_18 0x4C01BC8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_19 0x4C01BCC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_20 0x4C01BD0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_21 0x4C01BD4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_22 0x4C01BD8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_23 0x4C01BDC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_24 0x4C01BE0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_25 0x4C01BE4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_26 0x4C01BE8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_27 0x4C01BEC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_28 0x4C01BF0 + +#define mmPCIE_WRAP_AXI_DRAIN_ACTIVE 0x4C01D48 + +#define mmPCIE_WRAP_AXI_DRAIN_IND 0x4C01D4C + +#define mmPCIE_WRAP_HBW_DRAIN_TIMEOUT 0x4C01D50 + +#define mmPCIE_WRAP_HBW_DRAIN_CFG 0x4C01D54 + +#define mmPCIE_WRAP_LBW_DRAIN_TIMEOUT 0x4C01D58 + +#define mmPCIE_WRAP_LBW_DRAIN_CFG 0x4C01D5C + +#define mmPCIE_WRAP_LBW_DRAIN_DELAY_EN_CNT 0x4C01D60 + +#define mmPCIE_WRAP_PHY_FW_FSM 0x4C01D64 + +#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_L 0x4C01D68 + +#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_H 0x4C01D6C + +#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_L 0x4C01D70 + +#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_H 0x4C01D74 + +#define mmPCIE_WRAP_SPMU_INTR 0x4C01DE4 + +#define mmPCIE_WRAP_AXI_INTR 0x4C01DE8 + +#define mmPCIE_WRAP_PCIE_IC_SEI_INTR_IND 0x4C01DEC + +#define mmPCIE_WRAP_PMMU_RTR_CFG 0x4C01DF0 + +#define mmPCIE_WRAP_PSOC_RST_CTRL 0x4C01DF4 + +#define mmPCIE_WRAP_PSOC_BOOT_MNG_DONE 0x4C01DF8 + +#define mmPCIE_WRAP_ASID_MOD_CTRL 0x4C01DFC + +#define mmPCIE_WRAP_ASID_MOD_ADDR_L_0 0x4C01E00 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_L_1 0x4C01E04 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_H_0 0x4C01E08 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_H_1 0x4C01E0C + +#define mmPCIE_WRAP_CS_TRACE_AXI_CTRL 0x4C01E10 + +#define mmPCIE_WRAP_FLR_FSM_CTRL 0x4C01E14 + +#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_0 0x4C01E18 + +#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_1 0x4C01E1C + +#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_0 0x4C01E20 + +#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_1 0x4C01E24 + +#define mmPCIE_WRAP_HBW_DRAIN_STAMP 0x4C01E28 + +#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_0 0x4C01E2C + +#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_1 0x4C01E30 + +#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_0 0x4C01E34 + +#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_1 0x4C01E38 + +#define mmPCIE_WRAP_LBW_DRAIN_STAMP 0x4C01E3C + +#define mmPCIE_WRAP_EXTMEM_HBM_LOC 0x4C01E40 + +#define mmPCIE_WRAP_EXTMEM_PC_LOC 0x4C01E44 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM 0x4C01E48 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_PC 0x4C01E4C + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_NUM 0x4C01E50 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_MAP 0x4C01E54 + +#endif /* ASIC_REG_PCIE_WRAP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h new file mode 100644 index 000000000..46558e7a7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ +#define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ + +/* + ***************************************** + * PCIE_WRAP_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC + +#define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00 + +#define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04 + +#define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10 + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14 + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18 + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20 + +#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_ADDR 0x4C01F24 + +#define mmPCIE_WRAP_SPECIAL_MEM_RM 0x4C01F28 + +#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_MASK 0x4C01F40 + +#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_ADDR 0x4C01F44 + +#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_CAUSE 0x4C01F48 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0 0x4C01F60 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_1 0x4C01F64 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_2 0x4C01F68 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_3 0x4C01F6C + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_0 0x4C01F80 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_1 0x4C01F84 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_2 0x4C01F88 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_3 0x4C01F8C + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_4 0x4C01F90 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_5 0x4C01F94 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_6 0x4C01F98 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_7 0x4C01F9C + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_8 0x4C01FA0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_9 0x4C01FA4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_10 0x4C01FA8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_11 0x4C01FAC + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_12 0x4C01FB0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_13 0x4C01FB4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_14 0x4C01FB8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_15 0x4C01FBC + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_16 0x4C01FC0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_17 0x4C01FC4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_18 0x4C01FC8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_19 0x4C01FCC + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_20 0x4C01FD0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_21 0x4C01FD4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_22 0x4C01FD8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_23 0x4C01FDC + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_24 0x4C01FE0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_25 0x4C01FE4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_26 0x4C01FE8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_27 0x4C01FEC + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_28 0x4C01FF0 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_29 0x4C01FF4 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_30 0x4C01FF8 + +#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_31 0x4C01FFC + +#endif /* ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h new file mode 100644 index 000000000..bacbe4c6f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_CORE_CTX_AXUSER_HB_ASID 0x4C8B800 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x4C8B804 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C8B808 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C8B80C + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C8B810 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C8B814 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_QOS 0x4C8B818 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RSVD 0x4C8B81C + +#define mmPDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C8B820 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_CORE 0x4C8B824 + +#define mmPDMA0_CORE_CTX_AXUSER_E2E_COORD 0x4C8B828 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C8B830 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C8B834 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C8B838 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C8B83C + +#define mmPDMA0_CORE_CTX_AXUSER_LB_COORD 0x4C8B840 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_LOCK 0x4C8B844 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_RSVD 0x4C8B848 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_OVRD 0x4C8B84C + +#endif /* ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h new file mode 100644 index 000000000..02b57f07c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_CTX_REGS_H_ +#define ASIC_REG_PDMA0_CORE_CTX_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmPDMA0_CORE_CTX_RATE_LIM_TKN 0x4C8B860 + +#define mmPDMA0_CORE_CTX_PWRLP 0x4C8B864 + +#define mmPDMA0_CORE_CTX_TE_NUMROWS 0x4C8B868 + +#define mmPDMA0_CORE_CTX_IDX 0x4C8B86C + +#define mmPDMA0_CORE_CTX_IDX_INC 0x4C8B870 + +#define mmPDMA0_CORE_CTX_CTRL 0x4C8B874 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_0 0x4C8B878 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_1 0x4C8B87C + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_1 0x4C8B880 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_2 0x4C8B884 + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_2 0x4C8B888 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_3 0x4C8B88C + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_3 0x4C8B890 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_4 0x4C8B894 + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_4 0x4C8B898 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_1 0x4C8B89C + +#define mmPDMA0_CORE_CTX_DST_STRIDE_1 0x4C8B8A0 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_2 0x4C8B8A4 + +#define mmPDMA0_CORE_CTX_DST_STRIDE_2 0x4C8B8A8 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_3 0x4C8B8AC + +#define mmPDMA0_CORE_CTX_DST_STRIDE_3 0x4C8B8B0 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_4 0x4C8B8B4 + +#define mmPDMA0_CORE_CTX_DST_STRIDE_4 0x4C8B8B8 + +#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x4C8B8BC + +#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x4C8B8C0 + +#define mmPDMA0_CORE_CTX_WR_COMP_WDATA 0x4C8B8C4 + +#define mmPDMA0_CORE_CTX_SRC_OFFSET_LO 0x4C8B8C8 + +#define mmPDMA0_CORE_CTX_SRC_OFFSET_HI 0x4C8B8CC + +#define mmPDMA0_CORE_CTX_DST_OFFSET_LO 0x4C8B8D0 + +#define mmPDMA0_CORE_CTX_DST_OFFSET_HI 0x4C8B8D4 + +#define mmPDMA0_CORE_CTX_SRC_BASE_LO 0x4C8B8D8 + +#define mmPDMA0_CORE_CTX_SRC_BASE_HI 0x4C8B8DC + +#define mmPDMA0_CORE_CTX_DST_BASE_LO 0x4C8B8E0 + +#define mmPDMA0_CORE_CTX_DST_BASE_HI 0x4C8B8E4 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_0 0x4C8B8E8 + +#define mmPDMA0_CORE_CTX_COMMIT 0x4C8B8EC + +#endif /* ASIC_REG_PDMA0_CORE_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h new file mode 100644 index 000000000..909cda03c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_MASKS_H_ +#define ASIC_REG_PDMA0_CORE_MASKS_H_ + +/* + ***************************************** + * PDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* PDMA0_CORE_CFG_0 */ +#define PDMA0_CORE_CFG_0_EN_SHIFT 0 +#define PDMA0_CORE_CFG_0_EN_MASK 0x1 + +/* PDMA0_CORE_CFG_1 */ +#define PDMA0_CORE_CFG_1_HALT_SHIFT 0 +#define PDMA0_CORE_CFG_1_HALT_MASK 0x1 +#define PDMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2 + +/* PDMA0_CORE_PROT */ +#define PDMA0_CORE_PROT_VAL_SHIFT 0 +#define PDMA0_CORE_PROT_VAL_MASK 0x1 +#define PDMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* PDMA0_CORE_CKG */ +#define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 +#define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 +#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define PDMA0_CORE_CKG_TE_SHIFT 2 +#define PDMA0_CORE_CKG_TE_MASK 0x4 + +/* PDMA0_CORE_RD_GLBL */ +#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* PDMA0_CORE_RD_HBW_MAX_OUTSTAND */ +#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* PDMA0_CORE_RD_HBW_MAX_SIZE */ +#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* PDMA0_CORE_RD_HBW_ARCACHE */ +#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_RD_HBW_INFLIGHTS */ +#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_RD_HBW_RATE_LIM_CFG */ +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_RD_LBW_MAX_OUTSTAND */ +#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* PDMA0_CORE_RD_LBW_MAX_SIZE */ +#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* PDMA0_CORE_RD_LBW_ARCACHE */ +#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_RD_LBW_INFLIGHTS */ +#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_RD_LBW_RATE_LIM_CFG */ +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_HBW_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* PDMA0_CORE_WR_HBW_MAX_AWID */ +#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* PDMA0_CORE_WR_HBW_AWCACHE */ +#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_WR_HBW_INFLIGHTS */ +#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_WR_HBW_RATE_LIM_CFG */ +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_LBW_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* PDMA0_CORE_WR_LBW_MAX_AWID */ +#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* PDMA0_CORE_WR_LBW_AWCACHE */ +#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_WR_LBW_INFLIGHTS */ +#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_WR_LBW_RATE_LIM_CFG */ +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_COMP_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* PDMA0_CORE_WR_COMP_AWUSER */ +#define PDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 +#define PDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERR_CFG */ +#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* PDMA0_CORE_ERR_CAUSE */ +#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* PDMA0_CORE_ERRMSG_ADDR_LO */ +#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERRMSG_ADDR_HI */ +#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERRMSG_WDATA */ +#define PDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS0 */ +#define PDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define PDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define PDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define PDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define PDMA0_CORE_STS0_BUSY_SHIFT 31 +#define PDMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* PDMA0_CORE_STS1 */ +#define PDMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define PDMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* PDMA0_CORE_STS_RD_CTX_SEL */ +#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* PDMA0_CORE_STS_RD_CTX_SIZE */ +#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_BASE_LO */ +#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_BASE_HI */ +#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_ID */ +#define PDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_LB_AXI_ADDR */ +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_CTX_SEL */ +#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* PDMA0_CORE_STS_WR_CTX_SIZE */ +#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_BASE_LO */ +#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_BASE_HI */ +#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_ID */ +#define PDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_LB_AXI_ADDR */ +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* PDMA0_CORE_PWRLP_CFG */ +#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define PDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 +#define PDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 + +/* PDMA0_CORE_PWRLP_STS */ +#define PDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 +#define PDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F +#define PDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 +#define PDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 +#define PDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 +#define PDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 +#define PDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 +#define PDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 +#define PDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 +#define PDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 +#define PDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 +#define PDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 + +/* PDMA0_CORE_DBG_DESC_CNT */ +#define PDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_DBG_STS */ +#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define PDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define PDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define PDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define PDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define PDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define PDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define PDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 +#define PDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 +#define PDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 +#define PDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* PDMA0_CORE_DBG_BUF_STS */ +#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* PDMA0_CORE_DBG_RD_DESC_ID */ +#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_DBG_WR_DESC_ID */ +#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_APB_DMA_LBW_BASE */ +#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* PDMA0_CORE_APB_MSTR_IF_LBW_BASE */ +#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* PDMA0_CORE_E2E_CRED_ASYNC_CFG */ +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* PDMA0_CORE_DBG_APB_ENABLER */ +#define PDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 +#define PDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* PDMA0_CORE_L2H_CMPR_LO */ +#define PDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 +#define PDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_CORE_L2H_CMPR_HI */ +#define PDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_L2H_MASK_LO */ +#define PDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 +#define PDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_CORE_L2H_MASK_HI */ +#define PDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 +#define PDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_IDLE_IND_MASK */ +#define PDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* PDMA0_CORE_APB_ENABLER */ +#define PDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 +#define PDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_PDMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h new file mode 100644 index 000000000..84079b507 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_REGS_H_ +#define ASIC_REG_PDMA0_CORE_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmPDMA0_CORE_CFG_0 0x4C8B000 + +#define mmPDMA0_CORE_CFG_1 0x4C8B004 + +#define mmPDMA0_CORE_PROT 0x4C8B008 + +#define mmPDMA0_CORE_CKG 0x4C8B00C + +#define mmPDMA0_CORE_RD_GLBL 0x4C8B07C + +#define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080 + +#define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084 + +#define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088 + +#define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090 + +#define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094 + +#define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0 + +#define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4 + +#define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8 + +#define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0 + +#define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4 + +#define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100 + +#define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104 + +#define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108 + +#define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C + +#define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110 + +#define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140 + +#define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144 + +#define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148 + +#define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C + +#define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150 + +#define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180 + +#define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184 + +#define mmPDMA0_CORE_ERR_CFG 0x4C8B300 + +#define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304 + +#define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308 + +#define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C + +#define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310 + +#define mmPDMA0_CORE_STS0 0x4C8B380 + +#define mmPDMA0_CORE_STS1 0x4C8B384 + +#define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400 + +#define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404 + +#define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408 + +#define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C + +#define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410 + +#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414 + +#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418 + +#define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C + +#define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420 + +#define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424 + +#define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428 + +#define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C + +#define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430 + +#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434 + +#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438 + +#define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C + +#define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700 + +#define mmPDMA0_CORE_PWRLP_STS 0x4C8B704 + +#define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710 + +#define mmPDMA0_CORE_DBG_STS 0x4C8B714 + +#define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718 + +#define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720 + +#define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724 + +#define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728 + +#define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C + +#define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730 + +#define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C + +#define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20 + +#define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24 + +#define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28 + +#define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C + +#define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30 + +#define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34 + +#endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h new file mode 100644 index 000000000..15d257e38 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ +#define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ + +/* + ***************************************** + * PDMA0_CORE_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +/* PDMA0_CORE_SPECIAL_GLBL_PRIV */ +#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_MEM_GW_DATA */ +#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_MEM_GW_REQ */ +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT 22 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT 30 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT 31 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000 + +/* PDMA0_CORE_SPECIAL_MEM_NUMOF */ +#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK 0xFF + +/* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF + +/* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF + +/* PDMA0_CORE_SPECIAL_MEM_RM */ +#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_GLBL_SPARE */ +#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_SEC */ +#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h new file mode 100644 index 000000000..9b1cb609d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x4C88100 + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x4C88104 + +#define mmPDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x4C88108 + +#define mmPDMA0_QM_ARC_AUX_DBG_MODE 0x4C8810C + +#define mmPDMA0_QM_ARC_AUX_CLUSTER_NUM 0x4C88110 + +#define mmPDMA0_QM_ARC_AUX_ARC_NUM 0x4C88114 + +#define mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x4C88118 + +#define mmPDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4C8811C + +#define mmPDMA0_QM_ARC_AUX_CTI_AP_STS 0x4C88120 + +#define mmPDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4C88124 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST 0x4C88128 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST_REQ 0x4C8812C + +#define mmPDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4C88130 + +#define mmPDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4C88134 + +#define mmPDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4C88138 + +#define mmPDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4C8813C + +#define mmPDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x4C88140 + +#define mmPDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x4C88144 + +#define mmPDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4C88150 + +#define mmPDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4C88154 + +#define mmPDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4C88158 + +#define mmPDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4C8815C + +#define mmPDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4C88160 + +#define mmPDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4C88164 + +#define mmPDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4C88168 + +#define mmPDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4C8816C + +#define mmPDMA0_QM_ARC_AUX_HBM0_OFFSET 0x4C88170 + +#define mmPDMA0_QM_ARC_AUX_HBM1_OFFSET 0x4C88174 + +#define mmPDMA0_QM_ARC_AUX_HBM2_OFFSET 0x4C88178 + +#define mmPDMA0_QM_ARC_AUX_HBM3_OFFSET 0x4C8817C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4C88180 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4C88184 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4C88188 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4C8818C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4C88190 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4C88194 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4C88198 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4C8819C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4C881A0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4C881A4 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4C881A8 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4C881AC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4C881B0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4C881B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4C881B8 + +#define mmPDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4C881BC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x4C881C0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x4C881C4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x4C881C8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x4C881CC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x4C881D0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x4C881D4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x4C881D8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x4C881DC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_0 0x4C881E0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_1 0x4C881E4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_2 0x4C881E8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_3 0x4C881EC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_4 0x4C881F0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_5 0x4C881F4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_6 0x4C881F8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_7 0x4C881FC + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_0 0x4C88200 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_1 0x4C88204 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_2 0x4C88208 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_3 0x4C8820C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_4 0x4C88210 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_5 0x4C88214 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_6 0x4C88218 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_7 0x4C8821C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_8 0x4C88220 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_9 0x4C88224 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_10 0x4C88228 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_11 0x4C8822C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_12 0x4C88230 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_13 0x4C88234 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_14 0x4C88238 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_15 0x4C8823C + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4C88280 + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4C88284 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4C88290 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4C88294 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4C88298 + +#define mmPDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4C8829C + +#define mmPDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4C882A0 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4C882A4 + +#define mmPDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4C882A8 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4C882B0 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4C882B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4C882B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4C882BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4C882C0 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4C882C4 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4C882C8 + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4C882CC + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4C882D0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4C882E0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4C882E4 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4C882E8 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4C882EC + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4C882F0 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4C882F4 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x4C88300 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x4C88304 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x4C88308 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x4C8830C + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x4C88310 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x4C88314 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x4C88318 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x4C8831C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4C88320 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4C88324 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4C88328 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4C8832C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4C88330 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4C88334 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4C88338 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4C8833C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4C88350 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4C88354 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4C88358 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4C8835C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4C88360 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4C88364 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4C88368 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4C8836C + +#define mmPDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4C88370 + +#define mmPDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x4C88374 + +#define mmPDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x4C88378 + +#define mmPDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4C8837C + +#define mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4C88380 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4C88384 + +#define mmPDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4C8838C + +#define mmPDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4C88390 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4C88400 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4C88404 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4C88408 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4C8840C + +#define mmPDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4C88420 + +#define mmPDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x4C88424 + +#define mmPDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x4C88428 + +#define mmPDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4C8842C + +#define mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4C88430 + +#define mmPDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4C88434 + +#define mmPDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4C8843C + +#define mmPDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4C88440 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4C88500 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4C88504 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4C88508 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4C8850C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4C88510 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4C88514 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4C88518 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4C8851C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4C88520 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4C88524 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4C88528 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4C8852C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4C88530 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4C88534 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4C88538 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4C8853C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4C88540 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4C88544 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4C88548 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4C8854C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4C88550 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4C88554 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4C88558 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4C8855C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4C88560 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4C88564 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4C88568 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4C8856C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4C88570 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4C88574 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4C88578 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4C8857C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4C88580 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4C88584 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4C88588 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4C8858C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4C88590 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4C88594 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4C88598 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4C8859C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4C885A0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4C885A4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4C885A8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4C885AC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4C885B0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4C885B4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4C885B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4C885BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4C885C0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4C885C4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4C885C8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4C885CC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4C885D0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4C885D4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4C885D8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4C885DC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4C885E0 + +#define mmPDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4C885E4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4C88620 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4C88624 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4C88628 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4C88630 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4C88634 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4C88638 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4C8863C + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4C88640 + +#define mmPDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4C88644 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4C88648 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4C8864C + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4C88650 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4C88654 + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4C88658 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4C8865C + +#define mmPDMA0_QM_ARC_AUX_AUX2APB_PROT 0x4C88700 + +#define mmPDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4C88704 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4C88708 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4C8870C + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4C88710 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4C88714 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4C88718 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4C8871C + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4C88720 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4C88724 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4C88728 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4C8872C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4C88730 + +#define mmPDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4C88734 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4C88738 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4C8873C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4C88740 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4C88750 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4C88754 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4C88758 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4C8875C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4C88760 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4C88764 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4C88768 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4C8876C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4C88770 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4C88774 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4C88778 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4C8877C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4C88780 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4C88784 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4C88788 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4C8878C + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4C88790 + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4C88794 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4C88798 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4C8879C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4C88800 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4C88804 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4C88808 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4C8880C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4C88810 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4C88814 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4C88818 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4C8881C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4C88820 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4C88824 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4C88828 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4C8882C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4C88830 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4C88834 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4C88838 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4C8883C + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4C88840 + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4C88844 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4C88848 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4C8884C + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4C88850 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4C88854 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4C88900 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4C88904 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4C88908 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4C8890C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4C88910 + +#define mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4C88920 + +#endif /* ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..d2e0756ec --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x4C8AB80 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C8AB84 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C8AB88 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C8AB8C + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C8AB90 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C8AB94 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x4C8AB98 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x4C8AB9C + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C8ABA0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x4C8ABA4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x4C8ABA8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C8ABB0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C8ABB4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C8ABB8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C8ABBC + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x4C8ABC0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x4C8ABC4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x4C8ABC8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x4C8ABCC + +#endif /* ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h new file mode 100644 index 000000000..8bf0516b8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ +#define ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_AXUSER_SECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_QM_AXUSER_SECURED_HB_ASID 0x4C8AB00 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_MMU_BP 0x4C8AB04 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x4C8AB08 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_NO_SNOOP 0x4C8AB0C + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x4C8AB10 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x4C8AB14 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_QOS 0x4C8AB18 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RSVD 0x4C8AB1C + +#define mmPDMA0_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x4C8AB20 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_CORE 0x4C8AB24 + +#define mmPDMA0_QM_AXUSER_SECURED_E2E_COORD 0x4C8AB28 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x4C8AB30 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x4C8AB34 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x4C8AB38 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x4C8AB3C + +#define mmPDMA0_QM_AXUSER_SECURED_LB_COORD 0x4C8AB40 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_LOCK 0x4C8AB44 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_RSVD 0x4C8AB48 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_OVRD 0x4C8AB4C + +#endif /* ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h new file mode 100644 index 000000000..96c0ce176 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_CGM_REGS_H_ +#define ASIC_REG_PDMA0_QM_CGM_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmPDMA0_QM_CGM_CFG 0x4C8AD80 + +#define mmPDMA0_QM_CGM_STS 0x4C8AD84 + +#define mmPDMA0_QM_CGM_CFG1 0x4C8AD88 + +#endif /* ASIC_REG_PDMA0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h new file mode 100644 index 000000000..b79cae8f5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h @@ -0,0 +1,1165 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_MASKS_H_ +#define ASIC_REG_PDMA0_QM_MASKS_H_ + +/* + ***************************************** + * PDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +/* PDMA0_QM_GLBL_CFG0 */ +#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 +#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 +#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 + +/* PDMA0_QM_GLBL_CFG1 */ +#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* PDMA0_QM_GLBL_CFG2 */ +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 + +/* PDMA0_QM_GLBL_ERR_CFG */ +#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* PDMA0_QM_GLBL_ERR_CFG1 */ +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 + +/* PDMA0_QM_GLBL_ERR_ARC_HALT_EN */ +#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF + +/* PDMA0_QM_GLBL_AXCACHE */ +#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 +#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF +#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 +#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 + +/* PDMA0_QM_GLBL_STS0 */ +#define PDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define PDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define PDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define PDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define PDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define PDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* PDMA0_QM_GLBL_STS1 */ +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 + +/* PDMA0_QM_GLBL_ERR_STS */ +#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 + +/* PDMA0_QM_GLBL_ERR_STS_4 */ +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* PDMA0_QM_GLBL_ERR_MSG_EN */ +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 + +/* PDMA0_QM_GLBL_ERR_MSG_EN_4 */ +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* PDMA0_QM_GLBL_PROT */ +#define PDMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define PDMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define PDMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define PDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define PDMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define PDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define PDMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define PDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 +#define PDMA0_QM_GLBL_PROT_PQC_SHIFT 16 +#define PDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 +#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 +#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 +#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 +#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 +#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 +#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 +#define PDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 +#define PDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 +#define PDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 +#define PDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 + +/* PDMA0_QM_PQ_BASE_LO */ +#define PDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_BASE_HI */ +#define PDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_SIZE */ +#define PDMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_PQ_SIZE_VAL_MASK 0x1F + +/* PDMA0_QM_PQ_PI */ +#define PDMA0_QM_PQ_PI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_CI */ +#define PDMA0_QM_PQ_CI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_CFG0 */ +#define PDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 +#define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 + +/* PDMA0_QM_PQ_CFG1 */ +#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_PQ_STS0 */ +#define PDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_PQ_STS1 */ +#define PDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_PQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_PQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_CQ_CFG0 */ +#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* PDMA0_QM_CQ_STS0 */ +#define PDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_CQ_CFG1 */ +#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_CQ_STS1 */ +#define PDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_CQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_CQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_CQ_PTR_LO_0 */ +#define PDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_0 */ +#define PDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_0 */ +#define PDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_0 */ +#define PDMA0_QM_CQ_CTL_0_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_1 */ +#define PDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_1 */ +#define PDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_1 */ +#define PDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_1 */ +#define PDMA0_QM_CQ_CTL_1_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_2 */ +#define PDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_2 */ +#define PDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_2 */ +#define PDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_2 */ +#define PDMA0_QM_CQ_CTL_2_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_3 */ +#define PDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_3 */ +#define PDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_3 */ +#define PDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_3 */ +#define PDMA0_QM_CQ_CTL_3_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_4 */ +#define PDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_4 */ +#define PDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_4 */ +#define PDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_4 */ +#define PDMA0_QM_CQ_CTL_4_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_TSIZE_STS */ +#define PDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_LO_STS */ +#define PDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_STS */ +#define PDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_STS */ +#define PDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 +#define PDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 +#define PDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 +#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* PDMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_FENCE0_RDATA */ +#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE1_RDATA */ +#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE2_RDATA */ +#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE3_RDATA */ +#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE0_CNT */ +#define PDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE1_CNT */ +#define PDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE2_CNT */ +#define PDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE3_CNT */ +#define PDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_BARRIER_CFG */ +#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_STS */ +#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF +#define PDMA0_QM_CP_STS_ERDY_SHIFT 8 +#define PDMA0_QM_CP_STS_ERDY_MASK 0x100 +#define PDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 +#define PDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 +#define PDMA0_QM_CP_STS_MRDY_SHIFT 10 +#define PDMA0_QM_CP_STS_MRDY_MASK 0x400 +#define PDMA0_QM_CP_STS_SW_STOP_SHIFT 11 +#define PDMA0_QM_CP_STS_SW_STOP_MASK 0x800 +#define PDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 +#define PDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 +#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 +#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 +#define PDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 +#define PDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 +#define PDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 +#define PDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 + +/* PDMA0_QM_CP_CURRENT_INST_LO */ +#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_CURRENT_INST_HI */ +#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_PRED */ +#define PDMA0_QM_CP_PRED_VAL_SHIFT 0 +#define PDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_PRED_UPEN */ +#define PDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 +#define PDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_DBG_0 */ +#define PDMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define PDMA0_QM_CP_DBG_0_CS_MASK 0x1F +#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 +#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 +#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 +#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 +#define PDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 +#define PDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 +#define PDMA0_QM_CP_DBG_0_STALL_SHIFT 8 +#define PDMA0_QM_CP_DBG_0_STALL_MASK 0x100 + +/* PDMA0_QM_CP_CPDMA_UP_CRED */ +#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 +#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 +#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 +#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 + +/* PDMA0_QM_CP_IN_DATA_LO */ +#define PDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_IN_DATA_HI */ +#define PDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_HBW_BASE_LO */ +#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_HBW_BASE_HI */ +#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_SIZE */ +#define PDMA0_QM_PQC_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_PI */ +#define PDMA0_QM_PQC_PI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_WDATA */ +#define PDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_BASE_LO */ +#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_BASE_HI */ +#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_CFG */ +#define PDMA0_QM_PQC_CFG_EN_SHIFT 0 +#define PDMA0_QM_PQC_CFG_EN_MASK 0x1 +#define PDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 +#define PDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 + +/* PDMA0_QM_PQC_SECURE_PUSH_IND */ +#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* PDMA0_QM_ARB_MASK */ +#define PDMA0_QM_ARB_MASK_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MASK_VAL_MASK 0xF + +/* PDMA0_QM_ARB_CFG_0 */ +#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 +#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 +#define PDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define PDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define PDMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define PDMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 +#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 + +/* PDMA0_QM_ARB_CHOICE_Q_PUSH */ +#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 +#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_WRR_WEIGHT */ +#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF + +/* PDMA0_QM_ARB_CFG_1 */ +#define PDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define PDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* PDMA0_QM_ARB_MST_AVAIL_CRED */ +#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MST_CRED_INC */ +#define PDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ +#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_SLAVE_EN */ +#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_SLAVE_EN_1 */ +#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_CHOICE_WDT */ +#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_ID */ +#define PDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MST_QUIET_PER */ +#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* PDMA0_QM_ARB_BASE_LO */ +#define PDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_BASE_HI */ +#define PDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_STATE_STS */ +#define PDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_CHOICE_FULLNESS_STS */ +#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MSG_STS */ +#define PDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define PDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ +#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_ERR_CAUSE */ +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 +#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* PDMA0_QM_ARB_ERR_MSG_EN */ +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 +#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* PDMA0_QM_ARB_ERR_STS_DRP */ +#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_MST_CRED_STS */ +#define PDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F +#define PDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 +#define PDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 + +/* PDMA0_QM_ARB_MST_CRED_STS_1 */ +#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F +#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 +#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 + +/* PDMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 + +/* PDMA0_QM_ARC_CQ_CFG0 */ +#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* PDMA0_QM_ARC_CQ_CFG1 */ +#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_ARC_CQ_PTR_LO */ +#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_HI */ +#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_TSIZE */ +#define PDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL */ +#define PDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 +#define PDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 + +/* PDMA0_QM_ARC_CQ_IFIFO_STS */ +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* PDMA0_QM_ARC_CQ_STS0 */ +#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_ARC_CQ_STS1 */ +#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_ARC_CQ_TSIZE_STS */ +#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_LO_STS */ +#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_HI_STS */ +#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_WR_ARC_ADDR_HI */ +#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_WR_ARC_ADDR_LO */ +#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_MSG_BASE_HI */ +#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_MSG_BASE_LO */ +#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ADDR_OVRD */ +#define PDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 +#define PDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF + +/* PDMA0_QM_CQ_IFIFO_CI */ +#define PDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_CI */ +#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_CI */ +#define PDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_CI */ +#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_CFG */ +#define PDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 +#define PDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 +#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 +#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 + +/* PDMA0_QM_CP_EXT_SWITCH */ +#define PDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 +#define PDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 + +/* PDMA0_QM_CP_SWITCH_WD_SET */ +#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 +#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_SWITCH_WD */ +#define PDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 +#define PDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_LB_ADDR_BASE_LO */ +#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_LB_ADDR_BASE_HI */ +#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_BASE_ADDR_HI */ +#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_BASE_ADDR_LO */ +#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ +#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_BASE_ADDR_HI */ +#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_BASE_ADDR_LO */ +#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ +#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* PDMA0_QM_PQC_STS_0 */ +#define PDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 +#define PDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF +#define PDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 +#define PDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 + +/* PDMA0_QM_PQC_STS_1 */ +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 + +/* PDMA0_QM_SEI_STATUS */ +#define PDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 +#define PDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 +#define PDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 +#define PDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 + +/* PDMA0_QM_SEI_MASK */ +#define PDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 +#define PDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 +#define PDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 +#define PDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 + +/* PDMA0_QM_GLBL_ERR_ADDR_LO */ +#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_GLBL_ERR_ADDR_HI */ +#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_GLBL_ERR_WDATA */ +#define PDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_L2H_MASK_LO */ +#define PDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 +#define PDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_QM_L2H_MASK_HI */ +#define PDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 +#define PDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_L2H_CMPR_LO */ +#define PDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 +#define PDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_QM_L2H_CMPR_HI */ +#define PDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 +#define PDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_LOCAL_RANGE_BASE */ +#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* PDMA0_QM_LOCAL_RANGE_SIZE */ +#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* PDMA0_QM_IND_GW_APB_CFG */ +#define PDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define PDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define PDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* PDMA0_QM_IND_GW_APB_WDATA */ +#define PDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_IND_GW_APB_RDATA */ +#define PDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_IND_GW_APB_STATUS */ +#define PDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define PDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define PDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* PDMA0_QM_PERF_CNT_FREE_LO */ +#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_FREE_HI */ +#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_IDLE_LO */ +#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_IDLE_HI */ +#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_CFG */ +#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 +#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF +#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 +#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 +#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 +#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 +#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 +#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 +#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 +#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 +#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 +#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 + +#endif /* ASIC_REG_PDMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h new file mode 100644 index 000000000..77d803c93 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_REGS_H_ +#define ASIC_REG_PDMA0_QM_REGS_H_ + +/* + ***************************************** + * PDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmPDMA0_QM_GLBL_CFG0 0x4C8A000 + +#define mmPDMA0_QM_GLBL_CFG1 0x4C8A004 + +#define mmPDMA0_QM_GLBL_CFG2 0x4C8A008 + +#define mmPDMA0_QM_GLBL_ERR_CFG 0x4C8A00C + +#define mmPDMA0_QM_GLBL_ERR_CFG1 0x4C8A010 + +#define mmPDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x4C8A014 + +#define mmPDMA0_QM_GLBL_AXCACHE 0x4C8A018 + +#define mmPDMA0_QM_GLBL_STS0 0x4C8A01C + +#define mmPDMA0_QM_GLBL_STS1 0x4C8A020 + +#define mmPDMA0_QM_GLBL_ERR_STS_0 0x4C8A024 + +#define mmPDMA0_QM_GLBL_ERR_STS_1 0x4C8A028 + +#define mmPDMA0_QM_GLBL_ERR_STS_2 0x4C8A02C + +#define mmPDMA0_QM_GLBL_ERR_STS_3 0x4C8A030 + +#define mmPDMA0_QM_GLBL_ERR_STS_4 0x4C8A034 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_0 0x4C8A038 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_1 0x4C8A03C + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_2 0x4C8A040 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_3 0x4C8A044 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_4 0x4C8A048 + +#define mmPDMA0_QM_GLBL_PROT 0x4C8A04C + +#define mmPDMA0_QM_PQ_BASE_LO_0 0x4C8A050 + +#define mmPDMA0_QM_PQ_BASE_LO_1 0x4C8A054 + +#define mmPDMA0_QM_PQ_BASE_LO_2 0x4C8A058 + +#define mmPDMA0_QM_PQ_BASE_LO_3 0x4C8A05C + +#define mmPDMA0_QM_PQ_BASE_HI_0 0x4C8A060 + +#define mmPDMA0_QM_PQ_BASE_HI_1 0x4C8A064 + +#define mmPDMA0_QM_PQ_BASE_HI_2 0x4C8A068 + +#define mmPDMA0_QM_PQ_BASE_HI_3 0x4C8A06C + +#define mmPDMA0_QM_PQ_SIZE_0 0x4C8A070 + +#define mmPDMA0_QM_PQ_SIZE_1 0x4C8A074 + +#define mmPDMA0_QM_PQ_SIZE_2 0x4C8A078 + +#define mmPDMA0_QM_PQ_SIZE_3 0x4C8A07C + +#define mmPDMA0_QM_PQ_PI_0 0x4C8A080 + +#define mmPDMA0_QM_PQ_PI_1 0x4C8A084 + +#define mmPDMA0_QM_PQ_PI_2 0x4C8A088 + +#define mmPDMA0_QM_PQ_PI_3 0x4C8A08C + +#define mmPDMA0_QM_PQ_CI_0 0x4C8A090 + +#define mmPDMA0_QM_PQ_CI_1 0x4C8A094 + +#define mmPDMA0_QM_PQ_CI_2 0x4C8A098 + +#define mmPDMA0_QM_PQ_CI_3 0x4C8A09C + +#define mmPDMA0_QM_PQ_CFG0_0 0x4C8A0A0 + +#define mmPDMA0_QM_PQ_CFG0_1 0x4C8A0A4 + +#define mmPDMA0_QM_PQ_CFG0_2 0x4C8A0A8 + +#define mmPDMA0_QM_PQ_CFG0_3 0x4C8A0AC + +#define mmPDMA0_QM_PQ_CFG1_0 0x4C8A0B0 + +#define mmPDMA0_QM_PQ_CFG1_1 0x4C8A0B4 + +#define mmPDMA0_QM_PQ_CFG1_2 0x4C8A0B8 + +#define mmPDMA0_QM_PQ_CFG1_3 0x4C8A0BC + +#define mmPDMA0_QM_PQ_STS0_0 0x4C8A0C0 + +#define mmPDMA0_QM_PQ_STS0_1 0x4C8A0C4 + +#define mmPDMA0_QM_PQ_STS0_2 0x4C8A0C8 + +#define mmPDMA0_QM_PQ_STS0_3 0x4C8A0CC + +#define mmPDMA0_QM_PQ_STS1_0 0x4C8A0D0 + +#define mmPDMA0_QM_PQ_STS1_1 0x4C8A0D4 + +#define mmPDMA0_QM_PQ_STS1_2 0x4C8A0D8 + +#define mmPDMA0_QM_PQ_STS1_3 0x4C8A0DC + +#define mmPDMA0_QM_CQ_CFG0_0 0x4C8A0E0 + +#define mmPDMA0_QM_CQ_CFG0_1 0x4C8A0E4 + +#define mmPDMA0_QM_CQ_CFG0_2 0x4C8A0E8 + +#define mmPDMA0_QM_CQ_CFG0_3 0x4C8A0EC + +#define mmPDMA0_QM_CQ_CFG0_4 0x4C8A0F0 + +#define mmPDMA0_QM_CQ_STS0_0 0x4C8A0F4 + +#define mmPDMA0_QM_CQ_STS0_1 0x4C8A0F8 + +#define mmPDMA0_QM_CQ_STS0_2 0x4C8A0FC + +#define mmPDMA0_QM_CQ_STS0_3 0x4C8A100 + +#define mmPDMA0_QM_CQ_STS0_4 0x4C8A104 + +#define mmPDMA0_QM_CQ_CFG1_0 0x4C8A108 + +#define mmPDMA0_QM_CQ_CFG1_1 0x4C8A10C + +#define mmPDMA0_QM_CQ_CFG1_2 0x4C8A110 + +#define mmPDMA0_QM_CQ_CFG1_3 0x4C8A114 + +#define mmPDMA0_QM_CQ_CFG1_4 0x4C8A118 + +#define mmPDMA0_QM_CQ_STS1_0 0x4C8A11C + +#define mmPDMA0_QM_CQ_STS1_1 0x4C8A120 + +#define mmPDMA0_QM_CQ_STS1_2 0x4C8A124 + +#define mmPDMA0_QM_CQ_STS1_3 0x4C8A128 + +#define mmPDMA0_QM_CQ_STS1_4 0x4C8A12C + +#define mmPDMA0_QM_CQ_PTR_LO_0 0x4C8A150 + +#define mmPDMA0_QM_CQ_PTR_HI_0 0x4C8A154 + +#define mmPDMA0_QM_CQ_TSIZE_0 0x4C8A158 + +#define mmPDMA0_QM_CQ_CTL_0 0x4C8A15C + +#define mmPDMA0_QM_CQ_PTR_LO_1 0x4C8A160 + +#define mmPDMA0_QM_CQ_PTR_HI_1 0x4C8A164 + +#define mmPDMA0_QM_CQ_TSIZE_1 0x4C8A168 + +#define mmPDMA0_QM_CQ_CTL_1 0x4C8A16C + +#define mmPDMA0_QM_CQ_PTR_LO_2 0x4C8A170 + +#define mmPDMA0_QM_CQ_PTR_HI_2 0x4C8A174 + +#define mmPDMA0_QM_CQ_TSIZE_2 0x4C8A178 + +#define mmPDMA0_QM_CQ_CTL_2 0x4C8A17C + +#define mmPDMA0_QM_CQ_PTR_LO_3 0x4C8A180 + +#define mmPDMA0_QM_CQ_PTR_HI_3 0x4C8A184 + +#define mmPDMA0_QM_CQ_TSIZE_3 0x4C8A188 + +#define mmPDMA0_QM_CQ_CTL_3 0x4C8A18C + +#define mmPDMA0_QM_CQ_PTR_LO_4 0x4C8A190 + +#define mmPDMA0_QM_CQ_PTR_HI_4 0x4C8A194 + +#define mmPDMA0_QM_CQ_TSIZE_4 0x4C8A198 + +#define mmPDMA0_QM_CQ_CTL_4 0x4C8A19C + +#define mmPDMA0_QM_CQ_TSIZE_STS_0 0x4C8A1A0 + +#define mmPDMA0_QM_CQ_TSIZE_STS_1 0x4C8A1A4 + +#define mmPDMA0_QM_CQ_TSIZE_STS_2 0x4C8A1A8 + +#define mmPDMA0_QM_CQ_TSIZE_STS_3 0x4C8A1AC + +#define mmPDMA0_QM_CQ_TSIZE_STS_4 0x4C8A1B0 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_0 0x4C8A1B4 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_1 0x4C8A1B8 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_2 0x4C8A1BC + +#define mmPDMA0_QM_CQ_PTR_LO_STS_3 0x4C8A1C0 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_4 0x4C8A1C4 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_0 0x4C8A1C8 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_1 0x4C8A1CC + +#define mmPDMA0_QM_CQ_PTR_HI_STS_2 0x4C8A1D0 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_3 0x4C8A1D4 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_4 0x4C8A1D8 + +#define mmPDMA0_QM_CQ_IFIFO_STS_0 0x4C8A1DC + +#define mmPDMA0_QM_CQ_IFIFO_STS_1 0x4C8A1E0 + +#define mmPDMA0_QM_CQ_IFIFO_STS_2 0x4C8A1E4 + +#define mmPDMA0_QM_CQ_IFIFO_STS_3 0x4C8A1E8 + +#define mmPDMA0_QM_CQ_IFIFO_STS_4 0x4C8A1EC + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4C8A1F0 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4C8A1F4 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4C8A1F8 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4C8A1FC + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4C8A200 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4C8A204 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4C8A208 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4C8A20C + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4C8A210 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4C8A214 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4C8A218 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4C8A21C + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4C8A220 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4C8A224 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4C8A228 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4C8A22C + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4C8A230 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4C8A234 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4C8A238 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4C8A23C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4C8A240 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4C8A244 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4C8A248 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4C8A24C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4C8A250 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4C8A254 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4C8A258 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4C8A25C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4C8A260 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4C8A264 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4C8A268 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4C8A26C + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4C8A270 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4C8A274 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4C8A278 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4C8A27C + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4C8A280 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4C8A284 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4C8A288 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4C8A28C + +#define mmPDMA0_QM_CP_FENCE0_RDATA_0 0x4C8A290 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_1 0x4C8A294 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_2 0x4C8A298 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_3 0x4C8A29C + +#define mmPDMA0_QM_CP_FENCE0_RDATA_4 0x4C8A2A0 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_0 0x4C8A2A4 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_1 0x4C8A2A8 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_2 0x4C8A2AC + +#define mmPDMA0_QM_CP_FENCE1_RDATA_3 0x4C8A2B0 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_4 0x4C8A2B4 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_0 0x4C8A2B8 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_1 0x4C8A2BC + +#define mmPDMA0_QM_CP_FENCE2_RDATA_2 0x4C8A2C0 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_3 0x4C8A2C4 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_4 0x4C8A2C8 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_0 0x4C8A2CC + +#define mmPDMA0_QM_CP_FENCE3_RDATA_1 0x4C8A2D0 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_2 0x4C8A2D4 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_3 0x4C8A2D8 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_4 0x4C8A2DC + +#define mmPDMA0_QM_CP_FENCE0_CNT_0 0x4C8A2E0 + +#define mmPDMA0_QM_CP_FENCE0_CNT_1 0x4C8A2E4 + +#define mmPDMA0_QM_CP_FENCE0_CNT_2 0x4C8A2E8 + +#define mmPDMA0_QM_CP_FENCE0_CNT_3 0x4C8A2EC + +#define mmPDMA0_QM_CP_FENCE0_CNT_4 0x4C8A2F0 + +#define mmPDMA0_QM_CP_FENCE1_CNT_0 0x4C8A2F4 + +#define mmPDMA0_QM_CP_FENCE1_CNT_1 0x4C8A2F8 + +#define mmPDMA0_QM_CP_FENCE1_CNT_2 0x4C8A2FC + +#define mmPDMA0_QM_CP_FENCE1_CNT_3 0x4C8A300 + +#define mmPDMA0_QM_CP_FENCE1_CNT_4 0x4C8A304 + +#define mmPDMA0_QM_CP_FENCE2_CNT_0 0x4C8A308 + +#define mmPDMA0_QM_CP_FENCE2_CNT_1 0x4C8A30C + +#define mmPDMA0_QM_CP_FENCE2_CNT_2 0x4C8A310 + +#define mmPDMA0_QM_CP_FENCE2_CNT_3 0x4C8A314 + +#define mmPDMA0_QM_CP_FENCE2_CNT_4 0x4C8A318 + +#define mmPDMA0_QM_CP_FENCE3_CNT_0 0x4C8A31C + +#define mmPDMA0_QM_CP_FENCE3_CNT_1 0x4C8A320 + +#define mmPDMA0_QM_CP_FENCE3_CNT_2 0x4C8A324 + +#define mmPDMA0_QM_CP_FENCE3_CNT_3 0x4C8A328 + +#define mmPDMA0_QM_CP_FENCE3_CNT_4 0x4C8A32C + +#define mmPDMA0_QM_CP_BARRIER_CFG 0x4C8A330 + +#define mmPDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4C8A334 + +#define mmPDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4C8A338 + +#define mmPDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x4C8A33C + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4C8A340 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4C8A344 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4C8A348 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4C8A34C + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4C8A350 + +#define mmPDMA0_QM_CP_STS_0 0x4C8A368 + +#define mmPDMA0_QM_CP_STS_1 0x4C8A36C + +#define mmPDMA0_QM_CP_STS_2 0x4C8A370 + +#define mmPDMA0_QM_CP_STS_3 0x4C8A374 + +#define mmPDMA0_QM_CP_STS_4 0x4C8A378 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_0 0x4C8A37C + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_1 0x4C8A380 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_2 0x4C8A384 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_3 0x4C8A388 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_4 0x4C8A38C + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_0 0x4C8A390 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_1 0x4C8A394 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_2 0x4C8A398 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_3 0x4C8A39C + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_4 0x4C8A3A0 + +#define mmPDMA0_QM_CP_PRED_0 0x4C8A3A4 + +#define mmPDMA0_QM_CP_PRED_1 0x4C8A3A8 + +#define mmPDMA0_QM_CP_PRED_2 0x4C8A3AC + +#define mmPDMA0_QM_CP_PRED_3 0x4C8A3B0 + +#define mmPDMA0_QM_CP_PRED_4 0x4C8A3B4 + +#define mmPDMA0_QM_CP_PRED_UPEN_0 0x4C8A3B8 + +#define mmPDMA0_QM_CP_PRED_UPEN_1 0x4C8A3BC + +#define mmPDMA0_QM_CP_PRED_UPEN_2 0x4C8A3C0 + +#define mmPDMA0_QM_CP_PRED_UPEN_3 0x4C8A3C4 + +#define mmPDMA0_QM_CP_PRED_UPEN_4 0x4C8A3C8 + +#define mmPDMA0_QM_CP_DBG_0_0 0x4C8A3CC + +#define mmPDMA0_QM_CP_DBG_0_1 0x4C8A3D0 + +#define mmPDMA0_QM_CP_DBG_0_2 0x4C8A3D4 + +#define mmPDMA0_QM_CP_DBG_0_3 0x4C8A3D8 + +#define mmPDMA0_QM_CP_DBG_0_4 0x4C8A3DC + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_0 0x4C8A3E0 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_1 0x4C8A3E4 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_2 0x4C8A3E8 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_3 0x4C8A3EC + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_4 0x4C8A3F0 + +#define mmPDMA0_QM_CP_IN_DATA_LO_0 0x4C8A3F4 + +#define mmPDMA0_QM_CP_IN_DATA_LO_1 0x4C8A3F8 + +#define mmPDMA0_QM_CP_IN_DATA_LO_2 0x4C8A3FC + +#define mmPDMA0_QM_CP_IN_DATA_LO_3 0x4C8A400 + +#define mmPDMA0_QM_CP_IN_DATA_LO_4 0x4C8A404 + +#define mmPDMA0_QM_CP_IN_DATA_HI_0 0x4C8A408 + +#define mmPDMA0_QM_CP_IN_DATA_HI_1 0x4C8A40C + +#define mmPDMA0_QM_CP_IN_DATA_HI_2 0x4C8A410 + +#define mmPDMA0_QM_CP_IN_DATA_HI_3 0x4C8A414 + +#define mmPDMA0_QM_CP_IN_DATA_HI_4 0x4C8A418 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_0 0x4C8A41C + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_1 0x4C8A420 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_2 0x4C8A424 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_3 0x4C8A428 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_0 0x4C8A42C + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_1 0x4C8A430 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_2 0x4C8A434 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_3 0x4C8A438 + +#define mmPDMA0_QM_PQC_SIZE_0 0x4C8A43C + +#define mmPDMA0_QM_PQC_SIZE_1 0x4C8A440 + +#define mmPDMA0_QM_PQC_SIZE_2 0x4C8A444 + +#define mmPDMA0_QM_PQC_SIZE_3 0x4C8A448 + +#define mmPDMA0_QM_PQC_PI_0 0x4C8A44C + +#define mmPDMA0_QM_PQC_PI_1 0x4C8A450 + +#define mmPDMA0_QM_PQC_PI_2 0x4C8A454 + +#define mmPDMA0_QM_PQC_PI_3 0x4C8A458 + +#define mmPDMA0_QM_PQC_LBW_WDATA_0 0x4C8A45C + +#define mmPDMA0_QM_PQC_LBW_WDATA_1 0x4C8A460 + +#define mmPDMA0_QM_PQC_LBW_WDATA_2 0x4C8A464 + +#define mmPDMA0_QM_PQC_LBW_WDATA_3 0x4C8A468 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_0 0x4C8A46C + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_1 0x4C8A470 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_2 0x4C8A474 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_3 0x4C8A478 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_0 0x4C8A47C + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_1 0x4C8A480 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_2 0x4C8A484 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_3 0x4C8A488 + +#define mmPDMA0_QM_PQC_CFG 0x4C8A48C + +#define mmPDMA0_QM_PQC_SECURE_PUSH_IND 0x4C8A490 + +#define mmPDMA0_QM_ARB_MASK 0x4C8A4A0 + +#define mmPDMA0_QM_ARB_CFG_0 0x4C8A4A4 + +#define mmPDMA0_QM_ARB_CHOICE_Q_PUSH 0x4C8A4A8 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_0 0x4C8A4AC + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_1 0x4C8A4B0 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_2 0x4C8A4B4 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_3 0x4C8A4B8 + +#define mmPDMA0_QM_ARB_CFG_1 0x4C8A4BC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_0 0x4C8A4C0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_1 0x4C8A4C4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_2 0x4C8A4C8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_3 0x4C8A4CC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_4 0x4C8A4D0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_5 0x4C8A4D4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_6 0x4C8A4D8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_7 0x4C8A4DC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_8 0x4C8A4E0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_9 0x4C8A4E4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_10 0x4C8A4E8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_11 0x4C8A4EC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_12 0x4C8A4F0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_13 0x4C8A4F4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_14 0x4C8A4F8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_15 0x4C8A4FC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_16 0x4C8A500 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_17 0x4C8A504 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_18 0x4C8A508 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_19 0x4C8A50C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_20 0x4C8A510 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_21 0x4C8A514 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_22 0x4C8A518 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_23 0x4C8A51C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_24 0x4C8A520 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_25 0x4C8A524 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_26 0x4C8A528 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_27 0x4C8A52C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_28 0x4C8A530 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_29 0x4C8A534 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_30 0x4C8A538 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_31 0x4C8A53C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_32 0x4C8A540 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_33 0x4C8A544 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_34 0x4C8A548 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_35 0x4C8A54C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_36 0x4C8A550 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_37 0x4C8A554 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_38 0x4C8A558 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_39 0x4C8A55C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_40 0x4C8A560 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_41 0x4C8A564 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_42 0x4C8A568 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_43 0x4C8A56C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_44 0x4C8A570 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_45 0x4C8A574 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_46 0x4C8A578 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_47 0x4C8A57C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_48 0x4C8A580 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_49 0x4C8A584 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_50 0x4C8A588 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_51 0x4C8A58C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_52 0x4C8A590 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_53 0x4C8A594 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_54 0x4C8A598 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_55 0x4C8A59C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_56 0x4C8A5A0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_57 0x4C8A5A4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_58 0x4C8A5A8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_59 0x4C8A5AC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_60 0x4C8A5B0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_61 0x4C8A5B4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_62 0x4C8A5B8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_63 0x4C8A5BC + +#define mmPDMA0_QM_ARB_MST_CRED_INC 0x4C8A5E0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4C8A5E4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4C8A5E8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4C8A5EC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4C8A5F0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4C8A5F4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4C8A5F8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4C8A5FC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4C8A600 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4C8A604 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4C8A608 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4C8A60C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4C8A610 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4C8A614 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4C8A618 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4C8A61C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4C8A620 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4C8A624 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4C8A628 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4C8A62C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4C8A630 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4C8A634 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4C8A638 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4C8A63C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4C8A640 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4C8A644 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4C8A648 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4C8A64C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4C8A650 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4C8A654 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4C8A658 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4C8A65C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4C8A660 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4C8A664 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4C8A668 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4C8A66C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4C8A670 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4C8A674 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4C8A678 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4C8A67C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4C8A680 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4C8A684 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4C8A688 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4C8A68C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4C8A690 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4C8A694 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4C8A698 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4C8A69C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4C8A6A0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4C8A6A4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4C8A6A8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4C8A6AC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4C8A6B0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4C8A6B4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4C8A6B8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4C8A6BC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4C8A6C0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4C8A6C4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4C8A6C8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4C8A6CC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4C8A6D0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4C8A6D4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4C8A6D8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4C8A6DC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4C8A6E0 + +#define mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4C8A704 + +#define mmPDMA0_QM_ARB_MST_SLAVE_EN 0x4C8A708 + +#define mmPDMA0_QM_ARB_MST_SLAVE_EN_1 0x4C8A70C + +#define mmPDMA0_QM_ARB_SLV_CHOICE_WDT 0x4C8A710 + +#define mmPDMA0_QM_ARB_SLV_ID 0x4C8A714 + +#define mmPDMA0_QM_ARB_MST_QUIET_PER 0x4C8A718 + +#define mmPDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x4C8A744 + +#define mmPDMA0_QM_ARB_BASE_LO 0x4C8A754 + +#define mmPDMA0_QM_ARB_BASE_HI 0x4C8A758 + +#define mmPDMA0_QM_ARB_STATE_STS 0x4C8A780 + +#define mmPDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x4C8A784 + +#define mmPDMA0_QM_ARB_MSG_STS 0x4C8A788 + +#define mmPDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4C8A78C + +#define mmPDMA0_QM_ARB_ERR_CAUSE 0x4C8A79C + +#define mmPDMA0_QM_ARB_ERR_MSG_EN 0x4C8A7A0 + +#define mmPDMA0_QM_ARB_ERR_STS_DRP 0x4C8A7A8 + +#define mmPDMA0_QM_ARB_MST_CRED_STS 0x4C8A7B0 + +#define mmPDMA0_QM_ARB_MST_CRED_STS_1 0x4C8A7B4 + +#define mmPDMA0_QM_CSMR_STRICT_PRIO_CFG 0x4C8A7FC + +#define mmPDMA0_QM_ARC_CQ_CFG0 0x4C8A800 + +#define mmPDMA0_QM_ARC_CQ_CFG1 0x4C8A804 + +#define mmPDMA0_QM_ARC_CQ_PTR_LO 0x4C8A808 + +#define mmPDMA0_QM_ARC_CQ_PTR_HI 0x4C8A80C + +#define mmPDMA0_QM_ARC_CQ_TSIZE 0x4C8A810 + +#define mmPDMA0_QM_ARC_CQ_CTL 0x4C8A814 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_STS 0x4C8A81C + +#define mmPDMA0_QM_ARC_CQ_STS0 0x4C8A820 + +#define mmPDMA0_QM_ARC_CQ_STS1 0x4C8A824 + +#define mmPDMA0_QM_ARC_CQ_TSIZE_STS 0x4C8A828 + +#define mmPDMA0_QM_ARC_CQ_PTR_LO_STS 0x4C8A82C + +#define mmPDMA0_QM_ARC_CQ_PTR_HI_STS 0x4C8A830 + +#define mmPDMA0_QM_CP_WR_ARC_ADDR_HI 0x4C8A834 + +#define mmPDMA0_QM_CP_WR_ARC_ADDR_LO 0x4C8A838 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4C8A83C + +#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4C8A840 + +#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4C8A844 + +#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4C8A848 + +#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x4C8A84C + +#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x4C8A850 + +#define mmPDMA0_QM_CQ_CTL_MSG_BASE_HI 0x4C8A854 + +#define mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 0x4C8A858 + +#define mmPDMA0_QM_ADDR_OVRD 0x4C8A85C + +#define mmPDMA0_QM_CQ_IFIFO_CI_0 0x4C8A860 + +#define mmPDMA0_QM_CQ_IFIFO_CI_1 0x4C8A864 + +#define mmPDMA0_QM_CQ_IFIFO_CI_2 0x4C8A868 + +#define mmPDMA0_QM_CQ_IFIFO_CI_3 0x4C8A86C + +#define mmPDMA0_QM_CQ_IFIFO_CI_4 0x4C8A870 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_CI 0x4C8A874 + +#define mmPDMA0_QM_CQ_CTL_CI_0 0x4C8A878 + +#define mmPDMA0_QM_CQ_CTL_CI_1 0x4C8A87C + +#define mmPDMA0_QM_CQ_CTL_CI_2 0x4C8A880 + +#define mmPDMA0_QM_CQ_CTL_CI_3 0x4C8A884 + +#define mmPDMA0_QM_CQ_CTL_CI_4 0x4C8A888 + +#define mmPDMA0_QM_ARC_CQ_CTL_CI 0x4C8A88C + +#define mmPDMA0_QM_CP_CFG 0x4C8A890 + +#define mmPDMA0_QM_CP_EXT_SWITCH 0x4C8A894 + +#define mmPDMA0_QM_CP_SWITCH_WD_SET 0x4C8A898 + +#define mmPDMA0_QM_CP_SWITCH_WD 0x4C8A89C + +#define mmPDMA0_QM_ARC_LB_ADDR_BASE_LO 0x4C8A8A4 + +#define mmPDMA0_QM_ARC_LB_ADDR_BASE_HI 0x4C8A8A8 + +#define mmPDMA0_QM_ENGINE_BASE_ADDR_HI 0x4C8A8AC + +#define mmPDMA0_QM_ENGINE_BASE_ADDR_LO 0x4C8A8B0 + +#define mmPDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x4C8A8B4 + +#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4C8A8B8 + +#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4C8A8BC + +#define mmPDMA0_QM_QM_BASE_ADDR_HI 0x4C8A8C0 + +#define mmPDMA0_QM_QM_BASE_ADDR_LO 0x4C8A8C4 + +#define mmPDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x4C8A8C8 + +#define mmPDMA0_QM_PQC_STS_0_0 0x4C8A8D0 + +#define mmPDMA0_QM_PQC_STS_0_1 0x4C8A8D4 + +#define mmPDMA0_QM_PQC_STS_0_2 0x4C8A8D8 + +#define mmPDMA0_QM_PQC_STS_0_3 0x4C8A8DC + +#define mmPDMA0_QM_PQC_STS_1_0 0x4C8A8E0 + +#define mmPDMA0_QM_PQC_STS_1_1 0x4C8A8E4 + +#define mmPDMA0_QM_PQC_STS_1_2 0x4C8A8E8 + +#define mmPDMA0_QM_PQC_STS_1_3 0x4C8A8EC + +#define mmPDMA0_QM_SEI_STATUS 0x4C8A8F0 + +#define mmPDMA0_QM_SEI_MASK 0x4C8A8F4 + +#define mmPDMA0_QM_GLBL_ERR_ADDR_LO 0x4C8AD00 + +#define mmPDMA0_QM_GLBL_ERR_ADDR_HI 0x4C8AD04 + +#define mmPDMA0_QM_GLBL_ERR_WDATA 0x4C8AD08 + +#define mmPDMA0_QM_L2H_MASK_LO 0x4C8AD14 + +#define mmPDMA0_QM_L2H_MASK_HI 0x4C8AD18 + +#define mmPDMA0_QM_L2H_CMPR_LO 0x4C8AD1C + +#define mmPDMA0_QM_L2H_CMPR_HI 0x4C8AD20 + +#define mmPDMA0_QM_LOCAL_RANGE_BASE 0x4C8AD24 + +#define mmPDMA0_QM_LOCAL_RANGE_SIZE 0x4C8AD28 + +#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x4C8AD30 + +#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x4C8AD34 + +#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x4C8AD38 + +#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x4C8AD3C + +#define mmPDMA0_QM_IND_GW_APB_CFG 0x4C8AD40 + +#define mmPDMA0_QM_IND_GW_APB_WDATA 0x4C8AD44 + +#define mmPDMA0_QM_IND_GW_APB_RDATA 0x4C8AD48 + +#define mmPDMA0_QM_IND_GW_APB_STATUS 0x4C8AD4C + +#define mmPDMA0_QM_PERF_CNT_FREE_LO 0x4C8AD60 + +#define mmPDMA0_QM_PERF_CNT_FREE_HI 0x4C8AD64 + +#define mmPDMA0_QM_PERF_CNT_IDLE_LO 0x4C8AD68 + +#define mmPDMA0_QM_PERF_CNT_IDLE_HI 0x4C8AD6C + +#define mmPDMA0_QM_PERF_CNT_CFG 0x4C8AD70 + +#endif /* ASIC_REG_PDMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h new file mode 100644 index 000000000..ccc6dfd22 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * PDMA1_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA1_CORE_CTX_AXUSER_HB_ASID 0x4C9B800 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x4C9B804 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C9B808 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C9B80C + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C9B810 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C9B814 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_QOS 0x4C9B818 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RSVD 0x4C9B81C + +#define mmPDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C9B820 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_CORE 0x4C9B824 + +#define mmPDMA1_CORE_CTX_AXUSER_E2E_COORD 0x4C9B828 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C9B830 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C9B834 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C9B838 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C9B83C + +#define mmPDMA1_CORE_CTX_AXUSER_LB_COORD 0x4C9B840 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_LOCK 0x4C9B844 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_RSVD 0x4C9B848 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_OVRD 0x4C9B84C + +#endif /* ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..5fd72d050 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * PDMA1_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x4C9AB80 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C9AB84 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C9AB88 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C9AB8C + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C9AB90 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C9AB94 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x4C9AB98 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x4C9AB9C + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C9ABA0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x4C9ABA4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x4C9ABA8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C9ABB0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C9ABB4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C9ABB8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C9ABBC + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x4C9ABC0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x4C9ABC4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x4C9ABC8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x4C9ABCC + +#endif /* ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h new file mode 100644 index 000000000..0276506ea --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h @@ -0,0 +1,334 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_HBW_STLB_MASKS_H_ +#define ASIC_REG_PMMU_HBW_STLB_MASKS_H_ + +/* + ***************************************** + * PMMU_HBW_STLB + * (Prototype: STLB) + ***************************************** + */ + +/* PMMU_HBW_STLB_BUSY */ +#define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0 +#define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_ASID */ +#define PMMU_HBW_STLB_ASID_ASID_SHIFT 0 +#define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF + +/* PMMU_HBW_STLB_HOP0_PA43_12 */ +#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 +#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_HOP0_PA63_44 */ +#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 +#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF + +/* PMMU_HBW_STLB_CACHE_INV */ +#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* PMMU_HBW_STLB_CACHE_INV_BASE_39_8 */ +#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_CACHE_INV_BASE_63_40 */ +#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF + +/* PMMU_HBW_STLB_STLB_FEATURE_EN */ +#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 + +/* PMMU_HBW_STLB_STLB_AXI_CACHE */ +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* PMMU_HBW_STLB_HOP_CONFIGURATION */ +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000 + +/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_INV_ALL_START */ +#define PMMU_HBW_STLB_INV_ALL_START_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_ALL_START_R_MASK 0x1 + +/* PMMU_HBW_STLB_INV_ALL_SET */ +#define PMMU_HBW_STLB_INV_ALL_SET_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_ALL_SET_R_MASK 0xFF + +/* PMMU_HBW_STLB_INV_PS */ +#define PMMU_HBW_STLB_INV_PS_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_PS_R_MASK 0x3 + +/* PMMU_HBW_STLB_INV_CONSUMER_INDEX */ +#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* PMMU_HBW_STLB_INV_HIT_COUNT */ +#define PMMU_HBW_STLB_INV_HIT_COUNT_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* PMMU_HBW_STLB_INV_SET */ +#define PMMU_HBW_STLB_INV_SET_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_SET_R_MASK 0xFF + +/* PMMU_HBW_STLB_SRAM_INIT */ +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +/* PMMU_HBW_STLB_MEM_CACHE_INVALIDATION */ + +/* PMMU_HBW_STLB_MEM_CACHE_INV_STATUS */ +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 + +/* PMMU_HBW_STLB_MEM_CACHE_BASE_38_7 */ +#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_MEM_CACHE_BASE_63_39 */ +#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF + +/* PMMU_HBW_STLB_MEM_CACHE_CONFIG */ +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP5 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP4 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP3 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP2 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP1 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP0 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR */ + +/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK */ +#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 +#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 + +/* PMMU_HBW_STLB_MEM_L0_CACHE_CFG */ +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 + +/* PMMU_HBW_STLB_MEM_READ_ARPROT */ +#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_MASK 0x7 + +/* PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION */ +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ +0x1 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC + +/* PMMU_HBW_STLB_RANGE_INV_START_LSB */ +#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_START_MSB */ +#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_END_LSB */ +#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_END_MSB */ +#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF + +/* PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL */ +#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF + +#endif /* ASIC_REG_PMMU_HBW_STLB_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h new file mode 100644 index 000000000..87c66c08e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_HBW_STLB_REGS_H_ +#define ASIC_REG_PMMU_HBW_STLB_REGS_H_ + +/* + ***************************************** + * PMMU_HBW_STLB + * (Prototype: STLB) + ***************************************** + */ + +#define mmPMMU_HBW_STLB_BUSY 0x4D01000 + +#define mmPMMU_HBW_STLB_ASID 0x4D01004 + +#define mmPMMU_HBW_STLB_HOP0_PA43_12 0x4D01008 + +#define mmPMMU_HBW_STLB_HOP0_PA63_44 0x4D0100C + +#define mmPMMU_HBW_STLB_CACHE_INV 0x4D01010 + +#define mmPMMU_HBW_STLB_CACHE_INV_BASE_39_8 0x4D01014 + +#define mmPMMU_HBW_STLB_CACHE_INV_BASE_63_40 0x4D01018 + +#define mmPMMU_HBW_STLB_STLB_FEATURE_EN 0x4D0101C + +#define mmPMMU_HBW_STLB_STLB_AXI_CACHE 0x4D01020 + +#define mmPMMU_HBW_STLB_HOP_CONFIGURATION 0x4D01024 + +#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4D01028 + +#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x4D0102C + +#define mmPMMU_HBW_STLB_INV_ALL_START 0x4D01034 + +#define mmPMMU_HBW_STLB_INV_ALL_SET 0x4D01038 + +#define mmPMMU_HBW_STLB_INV_PS 0x4D0103C + +#define mmPMMU_HBW_STLB_INV_CONSUMER_INDEX 0x4D01040 + +#define mmPMMU_HBW_STLB_INV_HIT_COUNT 0x4D01044 + +#define mmPMMU_HBW_STLB_INV_SET 0x4D01048 + +#define mmPMMU_HBW_STLB_SRAM_INIT 0x4D0104C + +#define mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION 0x4D01050 + +#define mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS 0x4D01054 + +#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_38_7 0x4D01058 + +#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_63_39 0x4D0105C + +#define mmPMMU_HBW_STLB_MEM_CACHE_CONFIG 0x4D01060 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP5 0x4D01064 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP4 0x4D01068 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP3 0x4D0106C + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP2 0x4D01070 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP1 0x4D01074 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP0 0x4D01078 + +#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR 0x4D0107C + +#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK 0x4D01080 + +#define mmPMMU_HBW_STLB_MEM_L0_CACHE_CFG 0x4D01084 + +#define mmPMMU_HBW_STLB_MEM_READ_ARPROT 0x4D01088 + +#define mmPMMU_HBW_STLB_RANGE_CACHE_INVALIDATION 0x4D0108C + +#define mmPMMU_HBW_STLB_RANGE_INV_START_LSB 0x4D01090 + +#define mmPMMU_HBW_STLB_RANGE_INV_START_MSB 0x4D01094 + +#define mmPMMU_HBW_STLB_RANGE_INV_END_LSB 0x4D01098 + +#define mmPMMU_HBW_STLB_RANGE_INV_END_MSB 0x4D0109C + +#define mmPMMU_HBW_STLB_ASID_SCRAMBLER_CTRL 0x4D01100 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4D01104 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4D01108 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x4D0110C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4D01110 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4D01114 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4D01118 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x4D0111C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4D01120 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4D01124 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4D01128 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 0x4D0112C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 0x4D01130 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 0x4D01134 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 0x4D01138 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 0x4D0113C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 0x4D01140 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 0x4D01144 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 0x4D01148 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 0x4D0114C + +#endif /* ASIC_REG_PMMU_HBW_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h new file mode 100644 index 000000000..dd1279373 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_PIF_REGS_H_ +#define ASIC_REG_PMMU_PIF_REGS_H_ + +/* + ***************************************** + * PMMU_PIF + * (Prototype: PIF) + ***************************************** + */ + +#define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D03000 + +#define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D03004 + +#define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D03008 + +#define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C + +#define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D03010 + +#define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D03014 + +#define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D03018 + +#define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C + +#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D03020 + +#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D03024 + +#define mmPMMU_PIF_ARB_TYPE 0x4D03028 + +#define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C + +#define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D03030 + +#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D03034 + +#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D03038 + +#define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C + +#define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D03040 + +#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D03044 + +#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D03048 + +#define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C + +#define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D03050 + +#define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D03054 + +#define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D03058 + +#define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C + +#define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D03060 + +#define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D03070 + +#define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D03080 + +#define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D03084 + +#define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D03090 + +#define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D03094 + +#define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D03100 + +#define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D03104 + +#define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D03200 + +#define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D03204 + +#define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D03208 + +#define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C + +#define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D03210 + +#define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D03214 + +#define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218 + +#define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C + +#define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220 + +#define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224 + +#define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228 + +#define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C + +#define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230 + +#define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234 + +#define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300 + +#define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304 + +#define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308 + +#define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C + +#define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310 + +#define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314 + +#define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318 + +#define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C + +#define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320 + +#define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324 + +#endif /* ASIC_REG_PMMU_PIF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h new file mode 100644 index 000000000..42e67c105 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_MASKS_H_ +#define ASIC_REG_PSOC_ETR_MASKS_H_ + +/* + ***************************************** + * PSOC_ETR + * (Prototype: ETR) + ***************************************** + */ + +/* PSOC_ETR_RSZ */ +#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 +#define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF + +/* PSOC_ETR_STS */ +#define PSOC_ETR_STS_FULL_SHIFT 0 +#define PSOC_ETR_STS_FULL_MASK 0x1 +#define PSOC_ETR_STS_TRIGGERED_SHIFT 1 +#define PSOC_ETR_STS_TRIGGERED_MASK 0x2 +#define PSOC_ETR_STS_TMCREADY_SHIFT 2 +#define PSOC_ETR_STS_TMCREADY_MASK 0x4 +#define PSOC_ETR_STS_FTEMPTY_SHIFT 3 +#define PSOC_ETR_STS_FTEMPTY_MASK 0x8 +#define PSOC_ETR_STS_EMPTY_SHIFT 4 +#define PSOC_ETR_STS_EMPTY_MASK 0x10 +#define PSOC_ETR_STS_MEMERR_SHIFT 5 +#define PSOC_ETR_STS_MEMERR_MASK 0x20 + +/* PSOC_ETR_RRD */ +#define PSOC_ETR_RRD_RRD_SHIFT 0 +#define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF + +/* PSOC_ETR_RRP */ +#define PSOC_ETR_RRP_RRP_SHIFT 0 +#define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF + +/* PSOC_ETR_RWP */ +#define PSOC_ETR_RWP_RWP_SHIFT 0 +#define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF + +/* PSOC_ETR_TRG */ +#define PSOC_ETR_TRG_TRG_SHIFT 0 +#define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF + +/* PSOC_ETR_CTL */ +#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0 +#define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1 + +/* PSOC_ETR_RWD */ +#define PSOC_ETR_RWD_RWD_SHIFT 0 +#define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF + +/* PSOC_ETR_MODE */ +#define PSOC_ETR_MODE_MODE_SHIFT 0 +#define PSOC_ETR_MODE_MODE_MASK 0x3 + +/* PSOC_ETR_LBUFLEVEL */ +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0 +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_CBUFLEVEL */ +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0 +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_BUFWM */ +#define PSOC_ETR_BUFWM_BUFWM_SHIFT 0 +#define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF + +/* PSOC_ETR_RRPHI */ +#define PSOC_ETR_RRPHI_RRPHI_SHIFT 0 +#define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF + +/* PSOC_ETR_RWPHI */ +#define PSOC_ETR_RWPHI_RWPHI_SHIFT 0 +#define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF + +/* PSOC_ETR_AXICTL */ +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0 +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80 +#define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8 +#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 + +/* PSOC_ETR_DBALO */ +#define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0 +#define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF + +/* PSOC_ETR_DBAHI */ +#define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0 +#define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF + +/* PSOC_ETR_FFSR */ +#define PSOC_ETR_FFSR_FLINPROG_SHIFT 0 +#define PSOC_ETR_FFSR_FLINPROG_MASK 0x1 +#define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1 +#define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2 + +/* PSOC_ETR_FFCR */ +#define PSOC_ETR_FFCR_ENFT_SHIFT 0 +#define PSOC_ETR_FFCR_ENFT_MASK 0x1 +#define PSOC_ETR_FFCR_ENTI_SHIFT 1 +#define PSOC_ETR_FFCR_ENTI_MASK 0x2 +#define PSOC_ETR_FFCR_FONFLIN_SHIFT 4 +#define PSOC_ETR_FFCR_FONFLIN_MASK 0x10 +#define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5 +#define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20 +#define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6 +#define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200 +#define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10 +#define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400 +#define PSOC_ETR_FFCR_STOPONFL_SHIFT 12 +#define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000 + +/* PSOC_ETR_PSCR */ +#define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0 +#define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F + +/* PSOC_ETR_ITMISCOP0 */ +#define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0 +#define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1 +#define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1 +#define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2 + +/* PSOC_ETR_ITTRFLIN */ +#define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0 +#define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2 + +/* PSOC_ETR_ITATBDATA0 */ +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100 + +/* PSOC_ETR_ITATBCTR2 */ +#define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0 +#define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4 + +/* PSOC_ETR_ITATBCTR1 */ +#define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F + +/* PSOC_ETR_ITATBCTR0 */ +#define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700 + +/* PSOC_ETR_ITCTRL */ +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0 +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1 + +/* PSOC_ETR_CLAIMSET */ +#define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0 +#define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF + +/* PSOC_ETR_CLAIMCLR */ +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0 +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF + +/* PSOC_ETR_LAR */ +#define PSOC_ETR_LAR_ACCESS_W_SHIFT 0 +#define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF + +/* PSOC_ETR_LSR */ +#define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0 +#define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1 +#define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1 +#define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2 +#define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2 +#define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4 + +/* PSOC_ETR_AUTHSTATUS */ +#define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0 +#define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3 +#define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2 +#define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC +#define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4 +#define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30 +#define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6 +#define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0 + +/* PSOC_ETR_DEVID */ +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0 +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F +#define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5 +#define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20 +#define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6 +#define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0 +#define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8 +#define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700 +#define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11 +#define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800 + +/* PSOC_ETR_DEVTYPE */ +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0 +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF +#define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4 +#define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0 + +/* PSOC_ETR_PERIPHID4 */ +#define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0 +#define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4 +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0 + +/* PSOC_ETR_PERIPHID5 */ +#define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0 +#define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID6 */ +#define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0 +#define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID7 */ +#define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0 +#define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID0 */ +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0 +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF + +/* PSOC_ETR_PERIPHID1 */ +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0 +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4 +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0 + +/* PSOC_ETR_PERIPHID2 */ +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0 +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7 +#define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3 +#define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8 +#define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4 +#define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0 + +/* PSOC_ETR_PERIPHID3 */ +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0 +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF +#define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4 +#define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0 + +/* PSOC_ETR_COMPID0 */ +#define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID1 */ +#define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF +#define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4 +#define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0 + +/* PSOC_ETR_COMPID2 */ +#define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID3 */ +#define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF + +#endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000..980a3e005 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR + * (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x6C44004 + +#define mmPSOC_ETR_STS 0x6C4400C + +#define mmPSOC_ETR_RRD 0x6C44010 + +#define mmPSOC_ETR_RRP 0x6C44014 + +#define mmPSOC_ETR_RWP 0x6C44018 + +#define mmPSOC_ETR_TRG 0x6C4401C + +#define mmPSOC_ETR_CTL 0x6C44020 + +#define mmPSOC_ETR_RWD 0x6C44024 + +#define mmPSOC_ETR_MODE 0x6C44028 + +#define mmPSOC_ETR_LBUFLEVEL 0x6C4402C + +#define mmPSOC_ETR_CBUFLEVEL 0x6C44030 + +#define mmPSOC_ETR_BUFWM 0x6C44034 + +#define mmPSOC_ETR_RRPHI 0x6C44038 + +#define mmPSOC_ETR_RWPHI 0x6C4403C + +#define mmPSOC_ETR_AXICTL 0x6C44110 + +#define mmPSOC_ETR_DBALO 0x6C44118 + +#define mmPSOC_ETR_DBAHI 0x6C4411C + +#define mmPSOC_ETR_FFSR 0x6C44300 + +#define mmPSOC_ETR_FFCR 0x6C44304 + +#define mmPSOC_ETR_PSCR 0x6C44308 + +#define mmPSOC_ETR_ITMISCOP0 0x6C44EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x6C44EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x6C44EEC + +#define mmPSOC_ETR_ITATBCTR2 0x6C44EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x6C44EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x6C44EF8 + +#define mmPSOC_ETR_ITCTRL 0x6C44F00 + +#define mmPSOC_ETR_CLAIMSET 0x6C44FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x6C44FA4 + +#define mmPSOC_ETR_LAR 0x6C44FB0 + +#define mmPSOC_ETR_LSR 0x6C44FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x6C44FB8 + +#define mmPSOC_ETR_DEVID 0x6C44FC8 + +#define mmPSOC_ETR_DEVTYPE 0x6C44FCC + +#define mmPSOC_ETR_PERIPHID4 0x6C44FD0 + +#define mmPSOC_ETR_PERIPHID5 0x6C44FD4 + +#define mmPSOC_ETR_PERIPHID6 0x6C44FD8 + +#define mmPSOC_ETR_PERIPHID7 0x6C44FDC + +#define mmPSOC_ETR_PERIPHID0 0x6C44FE0 + +#define mmPSOC_ETR_PERIPHID1 0x6C44FE4 + +#define mmPSOC_ETR_PERIPHID2 0x6C44FE8 + +#define mmPSOC_ETR_PERIPHID3 0x6C44FEC + +#define mmPSOC_ETR_COMPID0 0x6C44FF0 + +#define mmPSOC_ETR_COMPID1 0x6C44FF4 + +#define mmPSOC_ETR_COMPID2 0x6C44FF8 + +#define mmPSOC_ETR_COMPID3 0x6C44FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000..9be3d656d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,1406 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF + * (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F + +/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */ +#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_SPI */ +#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_MASK 0x300 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_SHIFT 10 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_MASK 0xC00 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_SHIFT 12 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_MASK 0x3000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_SHIFT 14 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_MASK 0xC000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_SHIFT 16 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_MASK 0x30000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_SHIFT 18 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_MASK 0xC0000 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST */ +#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PHY_STABLE */ +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_OVR */ +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ETR_FLUSH */ +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ANY_RST */ +#define PSOC_GLOBAL_CONF_ANY_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ANY_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_SHIFT 16 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_RAZWI_INTERRUPT */ +#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RAZWI_MASK_INFO */ +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK 0x1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT 1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK 0x2 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT 2 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK 0x4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT 4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK 0x3FF0 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT 16 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK 0xFFFF0000 + +/* PSOC_GLOBAL_CONF_BTL_PROT */ +#define PSOC_GLOBAL_CONF_BTL_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_BTL_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_BTL_ADDR_EXT */ +#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_MASK 0xFFFFF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RESET_DELAYS */ +#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_SHIFT 0 +#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_MASK 0xFFFF +#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_SHIFT 16 +#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_MASK 0xFFFF0000 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TRACE_ADDR */ +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0xFFFFFF + +/* PSOC_GLOBAL_CONF_SMB_ALERT_CTRL */ +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_MASK 0xFF +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_SHIFT 8 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_SHIFT 16 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_MASK 0xFF0000 + +/* PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL */ +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_TRACE_AXPROT */ +#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ARC_WD_INTR */ +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_MASK 0x3 + +/* PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_DBG_APB_CTRL */ +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_MASK 0x1 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_SHIFT 1 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_DMA_BAUDR */ +#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_AWPROT */ +#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_SPI_DMA_AWUSER */ +#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_MASK 0x3FFF0 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_SHIFT 18 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_MASK 0xFFFC0000 + +/* PSOC_GLOBAL_CONF_SPI_DMA_STATUS */ +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_MASK 0x3FFF0 + +/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L */ +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H */ +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_MASK 0x10 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_SHIFT 8 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_SHIFT 16 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_MASK 0xFF0000 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_SHIFT 24 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_MASK 0xFF000000 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_MASK 0xFF0 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MSTR_IF */ +#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_MASK 0x1 +#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_SHIFT 1 +#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_MASK 0x2 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL */ +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_MASK 0xFF +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_SHIFT 8 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_SHIFT 16 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2 */ +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_MASK 0xF0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_MASK 0xF000 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_SHIFT 16 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_MASK 0xC +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_MASK 0x3FFF00 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_MASK 0x400000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_SHIFT 23 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_MASK 0x800000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_SHIFT 24 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_MASK 0x1F000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_SHIFT 29 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_MASK 0x20000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_SHIFT 30 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_MASK 0xC0000000 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_MASK 0x7C +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_MASK 0x380 + +/* PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS */ +#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BSAC_CTRL */ +#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_SHIFT 1 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_MASK 0x2 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_SHIFT 4 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_MASK 0x10 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_SHIFT 5 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_MASK 0x20 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_SHIFT 6 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_MASK 0x40 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_SHIFT 8 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_MASK 0x300 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_SHIFT 10 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_MASK 0xC00 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_SHIFT 12 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_MASK 0x3000 + +/* PSOC_GLOBAL_CONF_BSAC_ADDR */ +#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_MASK 0xFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_DATA */ +#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_MASK 0xFFFFFFF +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_SHIFT 28 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_MASK 0x10000000 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_SHIFT 29 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_MASK 0x20000000 + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_DATA */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_MASK */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_IMG */ +#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_SHIFT 1 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_MASK 0x2 +#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_SHIFT 2 +#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_MASK 0x4 +#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_SHIFT 6 +#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_MASK 0x40 +#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_SHIFT 7 +#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_MASK 0x80 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100 +#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_SHIFT 9 +#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200 +#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_SHIFT 10 +#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_MASK 0x400 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_MASK 0x2 +#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_SHIFT 2 +#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_MASK 0x4 +#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_SHIFT 3 +#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_MASK 0x8 +#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_SHIFT 4 +#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_MASK 0x10 +#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_SHIFT 5 +#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_MASK 0x20 +#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_SHIFT 6 +#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_MASK 0x40 +#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_SHIFT 7 +#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_MASK 0x80 +#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_SHIFT 8 +#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_STATE */ +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL */ +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_MASK 0x1 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_TPC_ISO */ +#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_MASK 0x1FFFFFF + +/* PSOC_GLOBAL_CONF_VDEC_ISO */ +#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_MASK 0x3FF + +/* PSOC_GLOBAL_CONF_NIC_ISO */ +#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_MASK 0xFFF + +/* PSOC_GLOBAL_CONF_MME_ISO */ +#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_SHIFT 0 +#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_MASK 0x3F +#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_SHIFT 6 +#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_SHIFT 12 +#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_MASK 0x3F000 +#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_SHIFT 18 +#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_MASK 0xFC0000 + +/* PSOC_GLOBAL_CONF_EDMA_ISO */ +#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_MASK 0xFF + +/* PSOC_GLOBAL_CONF_HBM_ISO */ +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_MASK 0xFFF +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_SHIFT 16 +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_MASK 0x3F0000 + +/* PSOC_GLOBAL_CONF_XBAR_EDGE_ISO */ +#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_MASK 0xF + +/* PSOC_GLOBAL_CONF_HIF_HMMU_ISO */ +#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_MASK 0xFFF +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_MASK 0x7000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_MASK 0x10000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_SHIFT 17 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_MASK 0x20000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_SHIFT 18 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_MASK 0x40000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_MASK 0x3F00000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_MASK 0x10 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_SHIFT 5 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_MASK 0x20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_SHIFT 6 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_MASK 0x40 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_SHIFT 7 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_MASK 0x80 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_SHIFT 9 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_MASK 0xFFF000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_SHIFT 24 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_MASK 0x3F000000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_SHIFT 31 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_MASK 0x10 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_SHIFT 5 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_MASK 0x20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_SHIFT 6 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_MASK 0x40 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_SHIFT 7 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_MASK 0x80 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_SHIFT 9 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_MASK 0x3F +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_MASK 0x1F00 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_MASK 0x3F0000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_CFG */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_MASK 0x1F +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_MASK 0x1F00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_MASK 0xF0000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_SHIFT 31 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_MASK 0xF +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_MASK 0xF0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_MASK 0xF00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_MASK 0xF000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_MASK 0xF0000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_MASK 0xF00000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_SHIFT 24 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_MASK 0xF000000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_MASK 0x3FF00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_MASK 0x3FF00000 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_SMI_ACCESS_EN */ +#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN */ +#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRAM_PERM_SEL */ +#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SCRAM_POLY_H3 */ +#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_MASK 0x1FFFFFFF + +/* PSOC_GLOBAL_CONF_CORE_MODE */ +#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_EXTMEM_ID_LOC */ +#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_SHIFT 24 +#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_MASK 0x3F000000 + +/* PSOC_GLOBAL_CONF_LBW_USER_CTRL */ +#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_STM_ID */ +#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_MASK 0x3F + +/* PSOC_GLOBAL_CONF_ADC */ +#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0xF + +/* PSOC_GLOBAL_CONF_ADC_INT_MASK */ +#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_SAMPLES */ +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_MASK 0x1F +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_SHIFT 8 +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_MASK 0x1F00 + +/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_MASK 0x30 + +/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_PID_SEL */ +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_MASK 0x3 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_MASK 0x30 + +/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_CH_SEL */ +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_MASK 0xFF +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_SHIFT 8 +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_MASK 0x300 + +/* PSOC_GLOBAL_CONF_ADC_WRITE_ADDR */ +#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL */ +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_MASK 0x1000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_SHIFT 13 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_MASK 0x2000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_SHIFT 14 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_MASK 0x4000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_SHIFT 15 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_MASK 0x8000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_SHIFT 16 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_MASK 0x3 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_SHIFT 4 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_MASK 0xF0 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_MASK 0x1 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_SHIFT 4 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_MASK 0x10 + +/* PSOC_GLOBAL_CONF_RST_OUT_CTRL */ +#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_STATUS */ +#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL2 */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_MASK 0xFFFF +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_SHIFT 16 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_MASK 0x3F0000 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_SHIFT 24 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_MASK 0x3F000000 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_SHIFT 31 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_MEM_CPY_CONST */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_CFG */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_MASK 0x7 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_MASK 0x700 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_MASK 0x70000 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_MASK 0x7000000 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_MASK 0xFF +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_MASK 0xFF0000 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_MASK 0xFF000000 + +/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD */ +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN */ +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD */ +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN */ +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 */ +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0x7FFFFF00 + +/* PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 */ +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0xFFFFF00 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_CPY_PROT */ +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_ISOLATE_INPUTS */ +#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL */ +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_SHIFT 1 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_MASK 0x6 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_SHIFT 5 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_MASK 0x60 + +/* PSOC_GLOBAL_CONF_ARC_JT_SEL */ +#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PLL_DUMP_CRTL */ +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_MASK 0x3F +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_MEM_CPY_AXUSER */ +#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_AXUSER */ +#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_MASK 0x3F +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK \ +0xFC0000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK \ +0x3F000000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_MASK 0x3F +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_MASK 0x1000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK \ +0x4000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT \ +16 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK \ +0xFF0000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT \ +0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK \ +0xFFFF +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT \ +16 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK \ +0xFFFF0000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_MASK 0x7 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_SHIFT 3 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_MASK 0x38 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_MASK 0x1C0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_SHIFT 9 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_MASK 0xE00 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_MASK 0x7000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_SHIFT 15 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_MASK 0x38000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_SHIFT 4 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_MASK 0x30 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_SHIFT 9 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_MASK 0x1000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_SHIFT 13 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_MASK 0x2000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_INTR */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK */ +#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_DFT_APB_CONTROL */ +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_SHIFT 0 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_MASK 0x1 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_SHIFT 1 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_MASK 0xFFFE +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_SHIFT 16 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_MASK 0xFFFF0000 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000..48980fa8e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,1337 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF + * (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0x4C4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0x4C4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0x4C4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0x4C4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0x4C4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0x4C4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0x4C4B028 + +#define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY 0x4C4B02C + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0x4C4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0x4C4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0x4C4B038 + +#define mmPSOC_GLOBAL_CONF_QSPI_SPI 0x4C4B03C + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0x4C4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0x4C4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0x4C4B048 + +#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0x4C4B04C + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0x4C4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0x4C4B054 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0x4C4B058 + +#define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST 0x4C4B05C + +#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0x4C4B060 + +#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0x4C4B064 + +#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0x4C4B068 + +#define mmPSOC_GLOBAL_CONF_ANY_RST 0x4C4B06C + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0x4C4B070 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0x4C4B074 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0x4C4B078 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0x4C4B07C + +#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0x4C4B080 + +#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0x4C4B084 + +#define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT 0x4C4B088 + +#define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO 0x4C4B08C + +#define mmPSOC_GLOBAL_CONF_BTL_PROT 0x4C4B090 + +#define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT 0x4C4B094 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0x4C4B098 + +#define mmPSOC_GLOBAL_CONF_RESET_DELAYS 0x4C4B09C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0x4C4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0x4C4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0x4C4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0x4C4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0x4C4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0x4C4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0x4C4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0x4C4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0x4C4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0x4C4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0x4C4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0x4C4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0x4C4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0x4C4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0x4C4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0x4C4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0x4C4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0x4C4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0x4C4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0x4C4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0x4C4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0x4C4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0x4C4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0x4C4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0x4C4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0x4C4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0x4C4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0x4C4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0x4C4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0x4C4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0x4C4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0x4C4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0x4C4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0x4C4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0x4C4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0x4C4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0x4C4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0x4C4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0x4C4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0x4C4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0x4C4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0x4C4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0x4C4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0x4C4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0x4C4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0x4C4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0x4C4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0x4C4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0x4C4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0x4C4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0x4C4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0x4C4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0x4C4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0x4C4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0x4C4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0x4C4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0x4C4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0x4C4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0x4C4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0x4C4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0x4C4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0x4C4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0x4C4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0x4C4B27C + +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0x4C4B300 + +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0x4C4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0x4C4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0x4C4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0x4C4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0x4C4B314 + +#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0x4C4B320 + +#define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL 0x4C4B324 + +#define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE 0x4C4B328 + +#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR 0x4C4B32C + +#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL 0x4C4B330 + +#define mmPSOC_GLOBAL_CONF_TRACE_AXPROT 0x4C4B334 + +#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0x4C4B338 + +#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0x4C4B33C + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0x4C4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0x4C4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0x4C4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0x4C4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0x4C4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0x4C4B360 + +#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR 0x4C4B368 + +#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK 0x4C4B36C + +#define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL 0x4C4B370 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR 0x4C4B374 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT 0x4C4B378 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER 0x4C4B37C + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL 0x4C4B380 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS 0x4C4B384 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L 0x4C4B388 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H 0x4C4B38C + +#define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL 0x4C4B3A0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL 0x4C4B3B0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L 0x4C4B3B4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H 0x4C4B3B8 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L 0x4C4B3BC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H 0x4C4B3C0 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L 0x4C4B3C4 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H 0x4C4B3CC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS 0x4C4B3D0 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS 0x4C4B3D4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR 0x4C4B3D8 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR 0x4C4B3DC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK 0x4C4B3E0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE 0x4C4B3E4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR 0x4C4B3E8 + +#define mmPSOC_GLOBAL_CONF_MSTR_IF 0x4C4B3F0 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0x4C4B400 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 0x4C4B404 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 0x4C4B408 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 0x4C4B40C + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 0x4C4B410 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0x4C4B420 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L 0x4C4B430 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H 0x4C4B434 + +#define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS 0x4C4B438 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0x4C4B44C + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0x4C4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0x4C4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0x4C4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0x4C4B45C + +#define mmPSOC_GLOBAL_CONF_BSAC_CTRL 0x4C4B4C0 + +#define mmPSOC_GLOBAL_CONF_BSAC_ADDR 0x4C4B4C4 + +#define mmPSOC_GLOBAL_CONF_BSAC_DATA 0x4C4B4C8 + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL 0x4C4B4CC + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA 0x4C4B4D0 + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK 0x4C4B4D4 + +#define mmPSOC_GLOBAL_CONF_BTL_IMG 0x4C4B4E0 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0x4C4B4E4 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0x4C4B4E8 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0x4C4B4F0 + +#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0x4C4B4F4 + +#define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL 0x4C4B4F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0x4C4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0x4C4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0x4C4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0x4C4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0x4C4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0x4C4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0x4C4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0x4C4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0x4C4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0x4C4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0x4C4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0x4C4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0x4C4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0x4C4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0x4C4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0x4C4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0x4C4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0x4C4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0x4C4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0x4C4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0x4C4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0x4C4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0x4C4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0x4C4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0x4C4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0x4C4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0x4C4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0x4C4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0x4C4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0x4C4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0x4C4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0x4C4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0x4C4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0x4C4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0x4C4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0x4C4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0x4C4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0x4C4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0x4C4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0x4C4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0x4C4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0x4C4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0x4C4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0x4C4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0x4C4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0x4C4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0x4C4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0x4C4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0x4C4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0x4C4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0x4C4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0x4C4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0x4C4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0x4C4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0x4C4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0x4C4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0x4C4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0x4C4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0x4C4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0x4C4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0x4C4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0x4C4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0x4C4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0x4C4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0x4C4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0x4C4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0x4C4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0x4C4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0x4C4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0x4C4B614 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0x4C4B618 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0x4C4B61C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0x4C4B620 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0x4C4B624 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0x4C4B628 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0x4C4B62C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0x4C4B630 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0x4C4B634 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0x4C4B638 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0x4C4B63C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0x4C4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0x4C4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0x4C4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0x4C4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0x4C4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0x4C4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0x4C4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0x4C4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0x4C4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0x4C4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 0x4C4B668 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 0x4C4B66C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 0x4C4B670 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 0x4C4B674 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0x4C4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0x4C4B694 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0x4C4B698 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0x4C4B69C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0x4C4B6A0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0x4C4B6A4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0x4C4B6A8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0x4C4B6AC + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0x4C4B6B0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0x4C4B6B4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0x4C4B6B8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0x4C4B6BC + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0x4C4B710 + +#define mmPSOC_GLOBAL_CONF_TPC_ISO 0x4C4B760 + +#define mmPSOC_GLOBAL_CONF_VDEC_ISO 0x4C4B764 + +#define mmPSOC_GLOBAL_CONF_NIC_ISO 0x4C4B768 + +#define mmPSOC_GLOBAL_CONF_MME_ISO 0x4C4B76C + +#define mmPSOC_GLOBAL_CONF_EDMA_ISO 0x4C4B770 + +#define mmPSOC_GLOBAL_CONF_HBM_ISO 0x4C4B774 + +#define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO 0x4C4B778 + +#define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO 0x4C4B77C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 0x4C4B780 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 0x4C4B784 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 0x4C4B788 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 0x4C4B78C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 0x4C4B790 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 0x4C4B794 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 0x4C4B798 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 0x4C4B79C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 0x4C4B7A0 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 0x4C4B7A4 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 0x4C4B7A8 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 0x4C4B7AC + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 0x4C4B7B0 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 0x4C4B7B4 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS 0x4C4B7B8 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG 0x4C4B7C0 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT 0x4C4B7C4 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR 0x4C4B7C8 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG 0x4C4B7CC + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 0x4C4B7D0 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 0x4C4B7D4 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 0x4C4B7D8 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 0x4C4B7DC + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 0x4C4B7E0 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 0x4C4B7E4 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 0x4C4B7E8 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 0x4C4B7EC + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 0x4C4B7F0 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 0x4C4B7F4 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 0x4C4B7F8 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 0x4C4B7FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0x4C4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0x4C4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0x4C4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0x4C4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0x4C4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0x4C4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0x4C4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0x4C4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0x4C4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0x4C4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0x4C4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0x4C4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0x4C4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0x4C4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0x4C4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0x4C4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0x4C4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0x4C4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0x4C4B848 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0x4C4B84C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0x4C4B850 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0x4C4B854 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0x4C4B858 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0x4C4B85C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0x4C4B860 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0x4C4B864 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0x4C4B868 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0x4C4B86C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0x4C4B870 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0x4C4B874 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0x4C4B878 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0x4C4B87C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0x4C4B880 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0x4C4B884 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0x4C4B888 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0x4C4B88C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0x4C4B890 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0x4C4B894 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0x4C4B898 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0x4C4B89C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0x4C4B8A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0x4C4B8A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0x4C4B8A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0x4C4B8AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0x4C4B8B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0x4C4B8B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0x4C4B8B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0x4C4B8BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0x4C4B8C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0x4C4B8C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0x4C4B8C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0x4C4B8CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0x4C4B8D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0x4C4B8D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0x4C4B8D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0x4C4B8DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0x4C4B8E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0x4C4B8E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0x4C4B8E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0x4C4B8EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0x4C4B8F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0x4C4B8F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0x4C4B8F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0x4C4B8FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0x4C4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0x4C4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0x4C4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0x4C4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0x4C4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0x4C4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0x4C4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0x4C4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0x4C4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0x4C4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0x4C4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0x4C4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0x4C4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0x4C4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0x4C4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0x4C4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0x4C4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0x4C4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0x4C4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0x4C4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0x4C4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0x4C4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0x4C4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0x4C4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0x4C4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0x4C4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0x4C4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0x4C4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0x4C4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0x4C4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0x4C4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0x4C4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0x4C4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0x4C4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0x4C4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0x4C4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0x4C4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0x4C4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0x4C4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0x4C4B99C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0x4C4B9A0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0x4C4B9A4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0x4C4B9A8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0x4C4B9AC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0x4C4B9B0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0x4C4B9B4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0x4C4B9B8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0x4C4B9BC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0x4C4B9C0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0x4C4B9C4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0x4C4B9C8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0x4C4B9CC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0x4C4B9D0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0x4C4B9D4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0x4C4B9D8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0x4C4B9DC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0x4C4B9E0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0x4C4B9E4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0x4C4B9E8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0x4C4B9EC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0x4C4B9F0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0x4C4B9F4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0x4C4B9F8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0x4C4B9FC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0x4C4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0x4C4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0x4C4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0x4C4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0x4C4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0x4C4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0x4C4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0x4C4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0x4C4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0x4C4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0x4C4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0x4C4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0x4C4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0x4C4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0x4C4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0x4C4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0x4C4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0x4C4BA44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0x4C4BA48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0x4C4BA4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0x4C4BA50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0x4C4BA54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0x4C4BA58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0x4C4BA5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0x4C4BA60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0x4C4BA64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0x4C4BA68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0x4C4BA6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0x4C4BA70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0x4C4BA74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0x4C4BA78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0x4C4BA7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0x4C4BA80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0x4C4BA84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0x4C4BA88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0x4C4BA8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0x4C4BA90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0x4C4BA94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0x4C4BA98 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0x4C4BA9C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0x4C4BAA0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0x4C4BAA4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0x4C4BAA8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0x4C4BAAC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0x4C4BAB0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0x4C4BAB4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0x4C4BAB8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0x4C4BABC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0x4C4BAC0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0x4C4BAC4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0x4C4BAC8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0x4C4BACC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0x4C4BAD0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0x4C4BAD4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0x4C4BAD8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0x4C4BADC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0x4C4BAE0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0x4C4BAE4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0x4C4BAE8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0x4C4BAEC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0x4C4BAF0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0x4C4BAF4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0x4C4BAF8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0x4C4BAFC + +#define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN 0x4C4BB00 + +#define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN 0x4C4BB38 + +#define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL 0x4C4BB3C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 0x4C4BB40 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 0x4C4BB44 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 0x4C4BB48 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 0x4C4BB4C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 0x4C4BB50 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 0x4C4BB54 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 0x4C4BB58 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 0x4C4BB5C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 0x4C4BB60 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 0x4C4BB64 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 0x4C4BB68 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 0x4C4BB6C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 0x4C4BB70 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 0x4C4BB74 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 0x4C4BB78 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 0x4C4BB7C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 0x4C4BB80 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 0x4C4BB84 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 0x4C4BB88 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 0x4C4BB8C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 0x4C4BB90 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 0x4C4BB94 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 0x4C4BB98 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 0x4C4BB9C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 0x4C4BBA0 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 0x4C4BBA4 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 0x4C4BBA8 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 0x4C4BBAC + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 0x4C4BBB0 + +#define mmPSOC_GLOBAL_CONF_CORE_MODE 0x4C4BBB4 + +#define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC 0x4C4BBB8 + +#define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL 0x4C4BBC0 + +#define mmPSOC_GLOBAL_CONF_ADC_STM_ID 0x4C4BBFC + +#define mmPSOC_GLOBAL_CONF_ADC_0 0x4C4BC00 + +#define mmPSOC_GLOBAL_CONF_ADC_1 0x4C4BC04 + +#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 0x4C4BC10 + +#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 0x4C4BC14 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 0x4C4BC20 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 0x4C4BC24 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 0x4C4BC30 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 0x4C4BC34 + +#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 0x4C4BC40 + +#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 0x4C4BC44 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 0x4C4BC50 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 0x4C4BC54 + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 0x4C4BC60 + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 0x4C4BC64 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 0x4C4BC70 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 0x4C4BC74 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 0x4C4BC80 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 0x4C4BC84 + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 0x4C4BC90 + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 0x4C4BC94 + +#define mmPSOC_GLOBAL_CONF_ADC_PID_SEL 0x4C4BC98 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 0x4C4BCA0 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 0x4C4BCA4 + +#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 0x4C4BCA8 + +#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 0x4C4BCAC + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 0x4C4BCC0 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 0x4C4BCC4 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 0x4C4BCC8 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 0x4C4BCCC + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 0x4C4BCD0 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 0x4C4BCD4 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 0x4C4BCD8 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 0x4C4BCDC + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 0x4C4BCE0 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 0x4C4BCE4 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 0x4C4BCE8 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 0x4C4BCEC + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 0x4C4BCF0 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 0x4C4BCF4 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 0x4C4BCF8 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 0x4C4BCFC + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 0x4C4BD00 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 0x4C4BD04 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 0x4C4BD08 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 0x4C4BD0C + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 0x4C4BD10 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 0x4C4BD14 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 0x4C4BD18 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 0x4C4BD1C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL 0x4C4BD24 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L 0x4C4BD28 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H 0x4C4BD2C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L 0x4C4BD30 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H 0x4C4BD34 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L 0x4C4BD38 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H 0x4C4BD3C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L 0x4C4BD40 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H 0x4C4BD44 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L 0x4C4BD48 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H 0x4C4BD4C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L 0x4C4BD50 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H 0x4C4BD54 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L 0x4C4BD58 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H 0x4C4BD5C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L 0x4C4BD60 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H 0x4C4BD64 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL 0x4C4BD80 + +#define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL 0x4C4BD84 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL 0x4C4BD90 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS 0x4C4BD94 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H 0x4C4BD98 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L 0x4C4BD9C + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H 0x4C4BDA0 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L 0x4C4BDA4 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 0x4C4BDA8 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST 0x4C4BDAC + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H 0x4C4BDB0 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L 0x4C4BDB4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG 0x4C4BDC0 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 0x4C4BDC4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 0x4C4BDC8 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 0x4C4BDCC + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 0x4C4BDD0 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 0x4C4BDD4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 0x4C4BDD8 + +#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD 0x4C4BDE0 + +#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN 0x4C4BDE4 + +#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD 0x4C4BDE8 + +#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN 0x4C4BDEC + +#define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 0x4C4BDF0 + +#define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 0x4C4BDF4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR 0x4C4BDF8 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT 0x4C4BE08 + +#define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS 0x4C4BE10 + +#define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL 0x4C4BE14 + +#define mmPSOC_GLOBAL_CONF_ARC_JT_SEL 0x4C4BE28 + +#define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL 0x4C4BE2C + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER 0x4C4BE30 + +#define mmPSOC_GLOBAL_CONF_BTL_AXUSER 0x4C4BE34 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 0x4C4BE38 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 0x4C4BE40 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 0x4C4BE44 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 0x4C4BE48 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL 0x4C4BE4C + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT 0x4C4BE50 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR 0x4C4BE54 + +#define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK 0x4C4BE58 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE 0x4C4BE60 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR 0x4C4BE64 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK 0x4C4BE68 + +#define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL 0x4C4BE70 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h new file mode 100644 index 000000000..e0cf35226 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h @@ -0,0 +1,2321 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_ +#define ASIC_REG_PSOC_RESET_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_RESET_CONF + * (Prototype: PSOC_RESET_CONF) + ***************************************** + */ + +/* PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_FW_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_WD_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_SW_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_FW_RST_CFG */ +#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_WD_RST_CFG */ +#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_SW_RST_CFG */ +#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_ARC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_FW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_WD_RST_CFG */ +#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SIF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_FW_RST_CFG */ +#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_WD_RST_CFG */ +#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_SW_RST_CFG */ +#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_FW_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_WD_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_SW_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_FW_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_WD_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_SW_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_FW_RST_CFG */ +#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_WD_RST_CFG */ +#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_SW_RST_CFG */ +#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_FW_RST_CFG */ +#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_WD_RST_CFG */ +#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_SW_RST_CFG */ +#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_FW_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_WD_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_SW_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_FW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_WD_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_SW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_FW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_WD_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_SW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_FW_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_WD_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_SW_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TPC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_FW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_WD_RST_CFG */ +#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_SW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_FW_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_WD_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_MNL_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_FLR_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_SW_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_FW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_WD_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_SW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_FW_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_WD_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_SW_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_FW_RST_CFG */ +#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_WD_RST_CFG */ +#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_SW_RST_CFG */ +#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_FW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_WD_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_SW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_NIC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_SOFT_RST */ +#define PSOC_RESET_CONF_SOFT_RST_IND_SHIFT 0 +#define PSOC_RESET_CONF_SOFT_RST_IND_MASK 0x1 + +/* PSOC_RESET_CONF_SW_ALL_RST */ +#define PSOC_RESET_CONF_SW_ALL_RST_IND_SHIFT 0 +#define PSOC_RESET_CONF_SW_ALL_RST_IND_MASK 0x1 + +/* PSOC_RESET_CONF_UNIT_RST_N */ +#define PSOC_RESET_CONF_UNIT_RST_N_IND_SHIFT 0 +#define PSOC_RESET_CONF_UNIT_RST_N_IND_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_UNIT_RST */ +#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_UNIT_RST */ +#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_ARC_UNIT_RST */ +#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SIF_UNIT_RST */ +#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_UNIT_RST */ +#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_TPC_DIV_UNIT_RST */ +#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_MASK 0x1F + +/* PSOC_RESET_CONF_HBM_DIV_UNIT_RST */ +#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_MASK 0x3F + +/* PSOC_RESET_CONF_PMMU_UNIT_RST */ +#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PM_UNIT_RST */ +#define PSOC_RESET_CONF_PM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_UNIT_RST */ +#define PSOC_RESET_CONF_TS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_UNIT_RST */ +#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_PLL_L_UNIT_RST */ +#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_H_UNIT_RST */ +#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_MME_EUS_UNIT_RST */ +#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_UNIT_RST */ +#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TPC_UNIT_RST */ +#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_HIF_HMMU_UNIT_RST */ +#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_UNIT_RST */ +#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_DDMA_UNIT_RST */ +#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_MASK 0xFF + +/* PSOC_RESET_CONF_KDMA_UNIT_RST */ +#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PDMA_UNIT_RST */ +#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SS_UNIT_RST */ +#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ROTATOR_UNIT_RST */ +#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SM_UNIT_RST */ +#define PSOC_RESET_CONF_SM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST */ +#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_HBM_MC_UNIT_RST */ +#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_MASK 0x3F + +/* PSOC_RESET_CONF_NIC_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_CH_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_MASK 0x7 + +/* PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +#endif /* ASIC_REG_PSOC_RESET_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h new file mode 100644 index 000000000..6a89624f0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h @@ -0,0 +1,989 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_RESET_CONF_REGS_H_ +#define ASIC_REG_PSOC_RESET_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_RESET_CONF + * (Prototype: PSOC_RESET_CONF) + ***************************************** + */ + +#define mmPSOC_RESET_CONF_PSOC_PRSTN_RST_CFG 0x4C74000 + +#define mmPSOC_RESET_CONF_PSOC_SOFT_RST_CFG 0x4C74004 + +#define mmPSOC_RESET_CONF_PSOC_FW_RST_CFG 0x4C74008 + +#define mmPSOC_RESET_CONF_PSOC_WD_RST_CFG 0x4C7400C + +#define mmPSOC_RESET_CONF_PSOC_MNL_RST_CFG 0x4C74010 + +#define mmPSOC_RESET_CONF_PSOC_FLR_RST_CFG 0x4C74014 + +#define mmPSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG 0x4C74018 + +#define mmPSOC_RESET_CONF_PSOC_SW_RST_CFG 0x4C7401C + +#define mmPSOC_RESET_CONF_CPU_PRSTN_RST_CFG 0x4C74020 + +#define mmPSOC_RESET_CONF_CPU_SOFT_RST_CFG 0x4C74024 + +#define mmPSOC_RESET_CONF_CPU_FW_RST_CFG 0x4C74028 + +#define mmPSOC_RESET_CONF_CPU_WD_RST_CFG 0x4C7402C + +#define mmPSOC_RESET_CONF_CPU_MNL_RST_CFG 0x4C74030 + +#define mmPSOC_RESET_CONF_CPU_FLR_RST_CFG 0x4C74034 + +#define mmPSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG 0x4C74038 + +#define mmPSOC_RESET_CONF_CPU_SW_RST_CFG 0x4C7403C + +#define mmPSOC_RESET_CONF_ARC_PRSTN_RST_CFG 0x4C74040 + +#define mmPSOC_RESET_CONF_ARC_SOFT_RST_CFG 0x4C74044 + +#define mmPSOC_RESET_CONF_ARC_FW_RST_CFG 0x4C74048 + +#define mmPSOC_RESET_CONF_ARC_WD_RST_CFG 0x4C7404C + +#define mmPSOC_RESET_CONF_ARC_MNL_RST_CFG 0x4C74050 + +#define mmPSOC_RESET_CONF_ARC_FLR_RST_CFG 0x4C74054 + +#define mmPSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG 0x4C74058 + +#define mmPSOC_RESET_CONF_ARC_SW_RST_CFG 0x4C7405C + +#define mmPSOC_RESET_CONF_SIF_PRSTN_RST_CFG 0x4C74060 + +#define mmPSOC_RESET_CONF_SIF_SOFT_RST_CFG 0x4C74064 + +#define mmPSOC_RESET_CONF_SIF_FW_RST_CFG 0x4C74068 + +#define mmPSOC_RESET_CONF_SIF_WD_RST_CFG 0x4C7406C + +#define mmPSOC_RESET_CONF_SIF_MNL_RST_CFG 0x4C74070 + +#define mmPSOC_RESET_CONF_SIF_FLR_RST_CFG 0x4C74074 + +#define mmPSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG 0x4C74078 + +#define mmPSOC_RESET_CONF_SIF_SW_RST_CFG 0x4C7407C + +#define mmPSOC_RESET_CONF_SRAM_PRSTN_RST_CFG 0x4C74080 + +#define mmPSOC_RESET_CONF_SRAM_SOFT_RST_CFG 0x4C74084 + +#define mmPSOC_RESET_CONF_SRAM_FW_RST_CFG 0x4C74088 + +#define mmPSOC_RESET_CONF_SRAM_WD_RST_CFG 0x4C7408C + +#define mmPSOC_RESET_CONF_SRAM_MNL_RST_CFG 0x4C74090 + +#define mmPSOC_RESET_CONF_SRAM_FLR_RST_CFG 0x4C74094 + +#define mmPSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG 0x4C74098 + +#define mmPSOC_RESET_CONF_SRAM_SW_RST_CFG 0x4C7409C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG 0x4C740A0 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG 0x4C740A4 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG 0x4C740A8 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG 0x4C740AC + +#define mmPSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG 0x4C740B0 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG 0x4C740B4 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG 0x4C740B8 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG 0x4C740BC + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG 0x4C740C0 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG 0x4C740C4 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG 0x4C740C8 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG 0x4C740CC + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG 0x4C740D0 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG 0x4C740D4 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG 0x4C740D8 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG 0x4C740DC + +#define mmPSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG 0x4C740E0 + +#define mmPSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG 0x4C740E4 + +#define mmPSOC_RESET_CONF_PCIE_IF_FW_RST_CFG 0x4C740E8 + +#define mmPSOC_RESET_CONF_PCIE_IF_WD_RST_CFG 0x4C740EC + +#define mmPSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG 0x4C740F0 + +#define mmPSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG 0x4C740F4 + +#define mmPSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG 0x4C740F8 + +#define mmPSOC_RESET_CONF_PCIE_IF_SW_RST_CFG 0x4C740FC + +#define mmPSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG 0x4C74100 + +#define mmPSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG 0x4C74104 + +#define mmPSOC_RESET_CONF_TPC_DIV_FW_RST_CFG 0x4C74108 + +#define mmPSOC_RESET_CONF_TPC_DIV_WD_RST_CFG 0x4C7410C + +#define mmPSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG 0x4C74110 + +#define mmPSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG 0x4C74114 + +#define mmPSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG 0x4C74118 + +#define mmPSOC_RESET_CONF_TPC_DIV_SW_RST_CFG 0x4C7411C + +#define mmPSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG 0x4C74120 + +#define mmPSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG 0x4C74124 + +#define mmPSOC_RESET_CONF_HBM_DIV_FW_RST_CFG 0x4C74128 + +#define mmPSOC_RESET_CONF_HBM_DIV_WD_RST_CFG 0x4C7412C + +#define mmPSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG 0x4C74130 + +#define mmPSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG 0x4C74134 + +#define mmPSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG 0x4C74138 + +#define mmPSOC_RESET_CONF_HBM_DIV_SW_RST_CFG 0x4C7413C + +#define mmPSOC_RESET_CONF_PMMU_PRSTN_RST_CFG 0x4C74140 + +#define mmPSOC_RESET_CONF_PMMU_SOFT_RST_CFG 0x4C74144 + +#define mmPSOC_RESET_CONF_PMMU_FW_RST_CFG 0x4C74148 + +#define mmPSOC_RESET_CONF_PMMU_WD_RST_CFG 0x4C7414C + +#define mmPSOC_RESET_CONF_PMMU_MNL_RST_CFG 0x4C74150 + +#define mmPSOC_RESET_CONF_PMMU_FLR_RST_CFG 0x4C74154 + +#define mmPSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG 0x4C74158 + +#define mmPSOC_RESET_CONF_PMMU_SW_RST_CFG 0x4C7415C + +#define mmPSOC_RESET_CONF_PM_PRSTN_RST_CFG 0x4C74160 + +#define mmPSOC_RESET_CONF_PM_SOFT_RST_CFG 0x4C74164 + +#define mmPSOC_RESET_CONF_PM_FW_RST_CFG 0x4C74168 + +#define mmPSOC_RESET_CONF_PM_WD_RST_CFG 0x4C7416C + +#define mmPSOC_RESET_CONF_PM_MNL_RST_CFG 0x4C74170 + +#define mmPSOC_RESET_CONF_PM_FLR_RST_CFG 0x4C74174 + +#define mmPSOC_RESET_CONF_PM_ECC_DERR_RST_CFG 0x4C74178 + +#define mmPSOC_RESET_CONF_PM_SW_RST_CFG 0x4C7417C + +#define mmPSOC_RESET_CONF_TS_PRSTN_RST_CFG 0x4C74180 + +#define mmPSOC_RESET_CONF_TS_SOFT_RST_CFG 0x4C74184 + +#define mmPSOC_RESET_CONF_TS_FW_RST_CFG 0x4C74188 + +#define mmPSOC_RESET_CONF_TS_WD_RST_CFG 0x4C7418C + +#define mmPSOC_RESET_CONF_TS_MNL_RST_CFG 0x4C74190 + +#define mmPSOC_RESET_CONF_TS_FLR_RST_CFG 0x4C74194 + +#define mmPSOC_RESET_CONF_TS_ECC_DERR_RST_CFG 0x4C74198 + +#define mmPSOC_RESET_CONF_TS_SW_RST_CFG 0x4C7419C + +#define mmPSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG 0x4C741A0 + +#define mmPSOC_RESET_CONF_TS_IF_SOFT_RST_CFG 0x4C741A4 + +#define mmPSOC_RESET_CONF_TS_IF_FW_RST_CFG 0x4C741A8 + +#define mmPSOC_RESET_CONF_TS_IF_WD_RST_CFG 0x4C741AC + +#define mmPSOC_RESET_CONF_TS_IF_MNL_RST_CFG 0x4C741B0 + +#define mmPSOC_RESET_CONF_TS_IF_FLR_RST_CFG 0x4C741B4 + +#define mmPSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG 0x4C741B8 + +#define mmPSOC_RESET_CONF_TS_IF_SW_RST_CFG 0x4C741BC + +#define mmPSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG 0x4C741C0 + +#define mmPSOC_RESET_CONF_PLL_L_SOFT_RST_CFG 0x4C741C4 + +#define mmPSOC_RESET_CONF_PLL_L_FW_RST_CFG 0x4C741C8 + +#define mmPSOC_RESET_CONF_PLL_L_WD_RST_CFG 0x4C741CC + +#define mmPSOC_RESET_CONF_PLL_L_MNL_RST_CFG 0x4C741D0 + +#define mmPSOC_RESET_CONF_PLL_L_FLR_RST_CFG 0x4C741D4 + +#define mmPSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG 0x4C741D8 + +#define mmPSOC_RESET_CONF_PLL_L_SW_RST_CFG 0x4C741DC + +#define mmPSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG 0x4C741E0 + +#define mmPSOC_RESET_CONF_PLL_H_SOFT_RST_CFG 0x4C741E4 + +#define mmPSOC_RESET_CONF_PLL_H_FW_RST_CFG 0x4C741E8 + +#define mmPSOC_RESET_CONF_PLL_H_WD_RST_CFG 0x4C741EC + +#define mmPSOC_RESET_CONF_PLL_H_MNL_RST_CFG 0x4C741F0 + +#define mmPSOC_RESET_CONF_PLL_H_FLR_RST_CFG 0x4C741F4 + +#define mmPSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG 0x4C741F8 + +#define mmPSOC_RESET_CONF_PLL_H_SW_RST_CFG 0x4C741FC + +#define mmPSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG 0x4C74200 + +#define mmPSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG 0x4C74204 + +#define mmPSOC_RESET_CONF_MME_EUS_FW_RST_CFG 0x4C74208 + +#define mmPSOC_RESET_CONF_MME_EUS_WD_RST_CFG 0x4C7420C + +#define mmPSOC_RESET_CONF_MME_EUS_MNL_RST_CFG 0x4C74210 + +#define mmPSOC_RESET_CONF_MME_EUS_FLR_RST_CFG 0x4C74214 + +#define mmPSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG 0x4C74218 + +#define mmPSOC_RESET_CONF_MME_EUS_SW_RST_CFG 0x4C7421C + +#define mmPSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG 0x4C74220 + +#define mmPSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG 0x4C74224 + +#define mmPSOC_RESET_CONF_MSS_CLS_FW_RST_CFG 0x4C74228 + +#define mmPSOC_RESET_CONF_MSS_CLS_WD_RST_CFG 0x4C7422C + +#define mmPSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG 0x4C74230 + +#define mmPSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG 0x4C74234 + +#define mmPSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG 0x4C74238 + +#define mmPSOC_RESET_CONF_MSS_CLS_SW_RST_CFG 0x4C7423C + +#define mmPSOC_RESET_CONF_TPC_PRSTN_RST_CFG 0x4C74240 + +#define mmPSOC_RESET_CONF_TPC_SOFT_RST_CFG 0x4C74244 + +#define mmPSOC_RESET_CONF_TPC_FW_RST_CFG 0x4C74248 + +#define mmPSOC_RESET_CONF_TPC_WD_RST_CFG 0x4C7424C + +#define mmPSOC_RESET_CONF_TPC_MNL_RST_CFG 0x4C74250 + +#define mmPSOC_RESET_CONF_TPC_FLR_RST_CFG 0x4C74254 + +#define mmPSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG 0x4C74258 + +#define mmPSOC_RESET_CONF_TPC_SW_RST_CFG 0x4C7425C + +#define mmPSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG 0x4C74260 + +#define mmPSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG 0x4C74264 + +#define mmPSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG 0x4C74268 + +#define mmPSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG 0x4C7426C + +#define mmPSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG 0x4C74270 + +#define mmPSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG 0x4C74274 + +#define mmPSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG 0x4C74278 + +#define mmPSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG 0x4C7427C + +#define mmPSOC_RESET_CONF_XBAR_PRSTN_RST_CFG 0x4C74280 + +#define mmPSOC_RESET_CONF_XBAR_SOFT_RST_CFG 0x4C74284 + +#define mmPSOC_RESET_CONF_XBAR_FW_RST_CFG 0x4C74288 + +#define mmPSOC_RESET_CONF_XBAR_WD_RST_CFG 0x4C7428C + +#define mmPSOC_RESET_CONF_XBAR_MNL_RST_CFG 0x4C74290 + +#define mmPSOC_RESET_CONF_XBAR_FLR_RST_CFG 0x4C74294 + +#define mmPSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG 0x4C74298 + +#define mmPSOC_RESET_CONF_XBAR_SW_RST_CFG 0x4C7429C + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG 0x4C742A0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG 0x4C742A4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG 0x4C742A8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG 0x4C742AC + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG 0x4C742B0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG 0x4C742B4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG 0x4C742B8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG 0x4C742BC + +#define mmPSOC_RESET_CONF_DDMA_PRSTN_RST_CFG 0x4C742C0 + +#define mmPSOC_RESET_CONF_DDMA_SOFT_RST_CFG 0x4C742C4 + +#define mmPSOC_RESET_CONF_DDMA_FW_RST_CFG 0x4C742C8 + +#define mmPSOC_RESET_CONF_DDMA_WD_RST_CFG 0x4C742CC + +#define mmPSOC_RESET_CONF_DDMA_MNL_RST_CFG 0x4C742D0 + +#define mmPSOC_RESET_CONF_DDMA_FLR_RST_CFG 0x4C742D4 + +#define mmPSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG 0x4C742D8 + +#define mmPSOC_RESET_CONF_DDMA_SW_RST_CFG 0x4C742DC + +#define mmPSOC_RESET_CONF_KDMA_PRSTN_RST_CFG 0x4C742E0 + +#define mmPSOC_RESET_CONF_KDMA_SOFT_RST_CFG 0x4C742E4 + +#define mmPSOC_RESET_CONF_KDMA_FW_RST_CFG 0x4C742E8 + +#define mmPSOC_RESET_CONF_KDMA_WD_RST_CFG 0x4C742EC + +#define mmPSOC_RESET_CONF_KDMA_MNL_RST_CFG 0x4C742F0 + +#define mmPSOC_RESET_CONF_KDMA_FLR_RST_CFG 0x4C742F4 + +#define mmPSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG 0x4C742F8 + +#define mmPSOC_RESET_CONF_KDMA_SW_RST_CFG 0x4C742FC + +#define mmPSOC_RESET_CONF_PDMA_PRSTN_RST_CFG 0x4C74300 + +#define mmPSOC_RESET_CONF_PDMA_SOFT_RST_CFG 0x4C74304 + +#define mmPSOC_RESET_CONF_PDMA_FW_RST_CFG 0x4C74308 + +#define mmPSOC_RESET_CONF_PDMA_WD_RST_CFG 0x4C7430C + +#define mmPSOC_RESET_CONF_PDMA_MNL_RST_CFG 0x4C74310 + +#define mmPSOC_RESET_CONF_PDMA_FLR_RST_CFG 0x4C74314 + +#define mmPSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG 0x4C74318 + +#define mmPSOC_RESET_CONF_PDMA_SW_RST_CFG 0x4C7431C + +#define mmPSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG 0x4C74320 + +#define mmPSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG 0x4C74324 + +#define mmPSOC_RESET_CONF_ARC_SS_FW_RST_CFG 0x4C74328 + +#define mmPSOC_RESET_CONF_ARC_SS_WD_RST_CFG 0x4C7432C + +#define mmPSOC_RESET_CONF_ARC_SS_MNL_RST_CFG 0x4C74330 + +#define mmPSOC_RESET_CONF_ARC_SS_FLR_RST_CFG 0x4C74334 + +#define mmPSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG 0x4C74338 + +#define mmPSOC_RESET_CONF_ARC_SS_SW_RST_CFG 0x4C7433C + +#define mmPSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG 0x4C74340 + +#define mmPSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG 0x4C74344 + +#define mmPSOC_RESET_CONF_ROTATOR_FW_RST_CFG 0x4C74348 + +#define mmPSOC_RESET_CONF_ROTATOR_WD_RST_CFG 0x4C7434C + +#define mmPSOC_RESET_CONF_ROTATOR_MNL_RST_CFG 0x4C74350 + +#define mmPSOC_RESET_CONF_ROTATOR_FLR_RST_CFG 0x4C74354 + +#define mmPSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG 0x4C74358 + +#define mmPSOC_RESET_CONF_ROTATOR_SW_RST_CFG 0x4C7435C + +#define mmPSOC_RESET_CONF_SM_PRSTN_RST_CFG 0x4C74360 + +#define mmPSOC_RESET_CONF_SM_SOFT_RST_CFG 0x4C74364 + +#define mmPSOC_RESET_CONF_SM_FW_RST_CFG 0x4C74368 + +#define mmPSOC_RESET_CONF_SM_WD_RST_CFG 0x4C7436C + +#define mmPSOC_RESET_CONF_SM_MNL_RST_CFG 0x4C74370 + +#define mmPSOC_RESET_CONF_SM_FLR_RST_CFG 0x4C74374 + +#define mmPSOC_RESET_CONF_SM_ECC_DERR_RST_CFG 0x4C74378 + +#define mmPSOC_RESET_CONF_SM_SW_RST_CFG 0x4C7437C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG 0x4C74380 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG 0x4C74384 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG 0x4C74388 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG 0x4C7438C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG 0x4C74390 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG 0x4C74394 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG 0x4C74398 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG 0x4C7439C + +#define mmPSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG 0x4C743A0 + +#define mmPSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG 0x4C743A4 + +#define mmPSOC_RESET_CONF_HBM_MC_FW_RST_CFG 0x4C743A8 + +#define mmPSOC_RESET_CONF_HBM_MC_WD_RST_CFG 0x4C743AC + +#define mmPSOC_RESET_CONF_HBM_MC_MNL_RST_CFG 0x4C743B0 + +#define mmPSOC_RESET_CONF_HBM_MC_FLR_RST_CFG 0x4C743B4 + +#define mmPSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG 0x4C743B8 + +#define mmPSOC_RESET_CONF_HBM_MC_SW_RST_CFG 0x4C743BC + +#define mmPSOC_RESET_CONF_NIC_PRSTN_RST_CFG 0x4C743C0 + +#define mmPSOC_RESET_CONF_NIC_SOFT_RST_CFG 0x4C743C4 + +#define mmPSOC_RESET_CONF_NIC_FW_RST_CFG 0x4C743C8 + +#define mmPSOC_RESET_CONF_NIC_WD_RST_CFG 0x4C743CC + +#define mmPSOC_RESET_CONF_NIC_MNL_RST_CFG 0x4C743D0 + +#define mmPSOC_RESET_CONF_NIC_FLR_RST_CFG 0x4C743D4 + +#define mmPSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG 0x4C743D8 + +#define mmPSOC_RESET_CONF_NIC_SW_RST_CFG 0x4C743DC + +#define mmPSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG 0x4C743E0 + +#define mmPSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG 0x4C743E4 + +#define mmPSOC_RESET_CONF_NIC_PRT_FW_RST_CFG 0x4C743E8 + +#define mmPSOC_RESET_CONF_NIC_PRT_WD_RST_CFG 0x4C743EC + +#define mmPSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG 0x4C743F0 + +#define mmPSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG 0x4C743F4 + +#define mmPSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG 0x4C743F8 + +#define mmPSOC_RESET_CONF_NIC_PRT_SW_RST_CFG 0x4C743FC + +#define mmPSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG 0x4C74400 + +#define mmPSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG 0x4C74404 + +#define mmPSOC_RESET_CONF_NIC_CH_FW_RST_CFG 0x4C74408 + +#define mmPSOC_RESET_CONF_NIC_CH_WD_RST_CFG 0x4C7440C + +#define mmPSOC_RESET_CONF_NIC_CH_MNL_RST_CFG 0x4C74410 + +#define mmPSOC_RESET_CONF_NIC_CH_FLR_RST_CFG 0x4C74414 + +#define mmPSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG 0x4C74418 + +#define mmPSOC_RESET_CONF_NIC_CH_SW_RST_CFG 0x4C7441C + +#define mmPSOC_RESET_CONF_SOFT_RST 0x4C74800 + +#define mmPSOC_RESET_CONF_SW_ALL_RST 0x4C74804 + +#define mmPSOC_RESET_CONF_UNIT_RST_N 0x4C74808 + +#define mmPSOC_RESET_CONF_PSOC_UNIT_RST 0x4C7480C + +#define mmPSOC_RESET_CONF_CPU_UNIT_RST 0x4C74810 + +#define mmPSOC_RESET_CONF_ARC_UNIT_RST 0x4C74814 + +#define mmPSOC_RESET_CONF_SIF_UNIT_RST 0x4C74818 + +#define mmPSOC_RESET_CONF_SRAM_UNIT_RST 0x4C7481C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_UNIT_RST 0x4C74820 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST 0x4C74824 + +#define mmPSOC_RESET_CONF_PCIE_IF_UNIT_RST 0x4C74828 + +#define mmPSOC_RESET_CONF_TPC_DIV_UNIT_RST 0x4C7482C + +#define mmPSOC_RESET_CONF_HBM_DIV_UNIT_RST 0x4C74830 + +#define mmPSOC_RESET_CONF_PMMU_UNIT_RST 0x4C74834 + +#define mmPSOC_RESET_CONF_PM_UNIT_RST 0x4C74838 + +#define mmPSOC_RESET_CONF_TS_UNIT_RST 0x4C7483C + +#define mmPSOC_RESET_CONF_TS_IF_UNIT_RST 0x4C74840 + +#define mmPSOC_RESET_CONF_PLL_L_UNIT_RST 0x4C74844 + +#define mmPSOC_RESET_CONF_PLL_H_UNIT_RST 0x4C74848 + +#define mmPSOC_RESET_CONF_MME_EUS_UNIT_RST 0x4C7484C + +#define mmPSOC_RESET_CONF_MSS_CLS_UNIT_RST 0x4C74850 + +#define mmPSOC_RESET_CONF_TPC_UNIT_RST 0x4C74854 + +#define mmPSOC_RESET_CONF_HIF_HMMU_UNIT_RST 0x4C74858 + +#define mmPSOC_RESET_CONF_XBAR_UNIT_RST 0x4C7485C + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST 0x4C74860 + +#define mmPSOC_RESET_CONF_DDMA_UNIT_RST 0x4C74864 + +#define mmPSOC_RESET_CONF_KDMA_UNIT_RST 0x4C74868 + +#define mmPSOC_RESET_CONF_PDMA_UNIT_RST 0x4C7486C + +#define mmPSOC_RESET_CONF_ARC_SS_UNIT_RST 0x4C74870 + +#define mmPSOC_RESET_CONF_ROTATOR_UNIT_RST 0x4C74874 + +#define mmPSOC_RESET_CONF_SM_UNIT_RST 0x4C74878 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_UNIT_RST 0x4C7487C + +#define mmPSOC_RESET_CONF_HBM_MC_UNIT_RST 0x4C74880 + +#define mmPSOC_RESET_CONF_NIC_UNIT_RST 0x4C74884 + +#define mmPSOC_RESET_CONF_NIC_PRT_UNIT_RST 0x4C74888 + +#define mmPSOC_RESET_CONF_NIC_CH_UNIT_RST 0x4C7488C + +#define mmPSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL 0x4C74B00 + +#define mmPSOC_RESET_CONF_CPU_0_CLK_RST_CTRL 0x4C74B04 + +#define mmPSOC_RESET_CONF_ARC_0_CLK_RST_CTRL 0x4C74B08 + +#define mmPSOC_RESET_CONF_ARC_1_CLK_RST_CTRL 0x4C74B0C + +#define mmPSOC_RESET_CONF_SIF_0_CLK_RST_CTRL 0x4C74B10 + +#define mmPSOC_RESET_CONF_SIF_1_CLK_RST_CTRL 0x4C74B14 + +#define mmPSOC_RESET_CONF_SIF_2_CLK_RST_CTRL 0x4C74B18 + +#define mmPSOC_RESET_CONF_SIF_3_CLK_RST_CTRL 0x4C74B1C + +#define mmPSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL 0x4C74B20 + +#define mmPSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL 0x4C74B24 + +#define mmPSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL 0x4C74B28 + +#define mmPSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL 0x4C74B2C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL 0x4C74B30 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL 0x4C74B34 + +#define mmPSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL 0x4C74B38 + +#define mmPSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL 0x4C74B3C + +#define mmPSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL 0x4C74B40 + +#define mmPSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL 0x4C74B44 + +#define mmPSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL 0x4C74B48 + +#define mmPSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL 0x4C74B4C + +#define mmPSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL 0x4C74B50 + +#define mmPSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL 0x4C74B54 + +#define mmPSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL 0x4C74B58 + +#define mmPSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL 0x4C74B5C + +#define mmPSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL 0x4C74B60 + +#define mmPSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL 0x4C74B64 + +#define mmPSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL 0x4C74B68 + +#define mmPSOC_RESET_CONF_PM_0_CLK_RST_CTRL 0x4C74B6C + +#define mmPSOC_RESET_CONF_PM_1_CLK_RST_CTRL 0x4C74B70 + +#define mmPSOC_RESET_CONF_PM_2_CLK_RST_CTRL 0x4C74B74 + +#define mmPSOC_RESET_CONF_PM_3_CLK_RST_CTRL 0x4C74B78 + +#define mmPSOC_RESET_CONF_TS_0_CLK_RST_CTRL 0x4C74B7C + +#define mmPSOC_RESET_CONF_TS_1_CLK_RST_CTRL 0x4C74B80 + +#define mmPSOC_RESET_CONF_TS_2_CLK_RST_CTRL 0x4C74B84 + +#define mmPSOC_RESET_CONF_TS_3_CLK_RST_CTRL 0x4C74B88 + +#define mmPSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL 0x4C74B8C + +#define mmPSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL 0x4C74B90 + +#define mmPSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL 0x4C74B94 + +#define mmPSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL 0x4C74B98 + +#define mmPSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL 0x4C74B9C + +#define mmPSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL 0x4C74BA0 + +#define mmPSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL 0x4C74BA4 + +#define mmPSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL 0x4C74BA8 + +#define mmPSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL 0x4C74BAC + +#define mmPSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL 0x4C74BB0 + +#define mmPSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL 0x4C74BB4 + +#define mmPSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL 0x4C74BB8 + +#define mmPSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL 0x4C74BBC + +#define mmPSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL 0x4C74BC0 + +#define mmPSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL 0x4C74BC4 + +#define mmPSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL 0x4C74BC8 + +#define mmPSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL 0x4C74BCC + +#define mmPSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL 0x4C74BD0 + +#define mmPSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL 0x4C74BD4 + +#define mmPSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL 0x4C74BD8 + +#define mmPSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL 0x4C74BDC + +#define mmPSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL 0x4C74BE0 + +#define mmPSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL 0x4C74BE4 + +#define mmPSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL 0x4C74BE8 + +#define mmPSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL 0x4C74BEC + +#define mmPSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL 0x4C74BF0 + +#define mmPSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL 0x4C74BF4 + +#define mmPSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL 0x4C74BF8 + +#define mmPSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL 0x4C74BFC + +#define mmPSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL 0x4C74C00 + +#define mmPSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL 0x4C74C04 + +#define mmPSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL 0x4C74C08 + +#define mmPSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL 0x4C74C0C + +#define mmPSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL 0x4C74C10 + +#define mmPSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL 0x4C74C14 + +#define mmPSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL 0x4C74C18 + +#define mmPSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL 0x4C74C1C + +#define mmPSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL 0x4C74C20 + +#define mmPSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL 0x4C74C24 + +#define mmPSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL 0x4C74C28 + +#define mmPSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL 0x4C74C2C + +#define mmPSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL 0x4C74C30 + +#define mmPSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL 0x4C74C34 + +#define mmPSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL 0x4C74C38 + +#define mmPSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL 0x4C74C3C + +#define mmPSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL 0x4C74C40 + +#define mmPSOC_RESET_CONF_TPC_0_CLK_RST_CTRL 0x4C74C44 + +#define mmPSOC_RESET_CONF_TPC_1_CLK_RST_CTRL 0x4C74C48 + +#define mmPSOC_RESET_CONF_TPC_2_CLK_RST_CTRL 0x4C74C4C + +#define mmPSOC_RESET_CONF_TPC_3_CLK_RST_CTRL 0x4C74C50 + +#define mmPSOC_RESET_CONF_TPC_4_CLK_RST_CTRL 0x4C74C54 + +#define mmPSOC_RESET_CONF_TPC_5_CLK_RST_CTRL 0x4C74C58 + +#define mmPSOC_RESET_CONF_TPC_6_CLK_RST_CTRL 0x4C74C5C + +#define mmPSOC_RESET_CONF_TPC_7_CLK_RST_CTRL 0x4C74C60 + +#define mmPSOC_RESET_CONF_TPC_8_CLK_RST_CTRL 0x4C74C64 + +#define mmPSOC_RESET_CONF_TPC_9_CLK_RST_CTRL 0x4C74C68 + +#define mmPSOC_RESET_CONF_TPC_10_CLK_RST_CTRL 0x4C74C6C + +#define mmPSOC_RESET_CONF_TPC_11_CLK_RST_CTRL 0x4C74C70 + +#define mmPSOC_RESET_CONF_TPC_12_CLK_RST_CTRL 0x4C74C74 + +#define mmPSOC_RESET_CONF_TPC_13_CLK_RST_CTRL 0x4C74C78 + +#define mmPSOC_RESET_CONF_TPC_14_CLK_RST_CTRL 0x4C74C7C + +#define mmPSOC_RESET_CONF_TPC_15_CLK_RST_CTRL 0x4C74C80 + +#define mmPSOC_RESET_CONF_TPC_16_CLK_RST_CTRL 0x4C74C84 + +#define mmPSOC_RESET_CONF_TPC_17_CLK_RST_CTRL 0x4C74C88 + +#define mmPSOC_RESET_CONF_TPC_18_CLK_RST_CTRL 0x4C74C8C + +#define mmPSOC_RESET_CONF_TPC_19_CLK_RST_CTRL 0x4C74C90 + +#define mmPSOC_RESET_CONF_TPC_20_CLK_RST_CTRL 0x4C74C94 + +#define mmPSOC_RESET_CONF_TPC_21_CLK_RST_CTRL 0x4C74C98 + +#define mmPSOC_RESET_CONF_TPC_22_CLK_RST_CTRL 0x4C74C9C + +#define mmPSOC_RESET_CONF_TPC_23_CLK_RST_CTRL 0x4C74CA0 + +#define mmPSOC_RESET_CONF_TPC_24_CLK_RST_CTRL 0x4C74CA4 + +#define mmPSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL 0x4C74CA8 + +#define mmPSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL 0x4C74CAC + +#define mmPSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL 0x4C74CB0 + +#define mmPSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL 0x4C74CB4 + +#define mmPSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL 0x4C74CB8 + +#define mmPSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL 0x4C74CBC + +#define mmPSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL 0x4C74CC0 + +#define mmPSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL 0x4C74CC4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL 0x4C74CC8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL 0x4C74CCC + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL 0x4C74CD0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL 0x4C74CD4 + +#define mmPSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL 0x4C74CD8 + +#define mmPSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL 0x4C74CDC + +#define mmPSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL 0x4C74CE0 + +#define mmPSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL 0x4C74CE4 + +#define mmPSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL 0x4C74CE8 + +#define mmPSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL 0x4C74CEC + +#define mmPSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL 0x4C74CF0 + +#define mmPSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL 0x4C74CF4 + +#define mmPSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL 0x4C74CF8 + +#define mmPSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL 0x4C74CFC + +#define mmPSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL 0x4C74D00 + +#define mmPSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL 0x4C74D04 + +#define mmPSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL 0x4C74D08 + +#define mmPSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL 0x4C74D0C + +#define mmPSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL 0x4C74D10 + +#define mmPSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL 0x4C74D14 + +#define mmPSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL 0x4C74D18 + +#define mmPSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL 0x4C74D1C + +#define mmPSOC_RESET_CONF_SM_0_CLK_RST_CTRL 0x4C74D20 + +#define mmPSOC_RESET_CONF_SM_1_CLK_RST_CTRL 0x4C74D24 + +#define mmPSOC_RESET_CONF_SM_2_CLK_RST_CTRL 0x4C74D28 + +#define mmPSOC_RESET_CONF_SM_3_CLK_RST_CTRL 0x4C74D2C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL 0x4C74D30 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL 0x4C74D34 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL 0x4C74D38 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL 0x4C74D3C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL 0x4C74D40 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL 0x4C74D44 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL 0x4C74D48 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL 0x4C74D4C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL 0x4C74D50 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL 0x4C74D54 + +#define mmPSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL 0x4C74D58 + +#define mmPSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL 0x4C74D5C + +#define mmPSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL 0x4C74D60 + +#define mmPSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL 0x4C74D64 + +#define mmPSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL 0x4C74D68 + +#define mmPSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL 0x4C74D6C + +#define mmPSOC_RESET_CONF_NIC_0_CLK_RST_CTRL 0x4C74D70 + +#define mmPSOC_RESET_CONF_NIC_1_CLK_RST_CTRL 0x4C74D74 + +#define mmPSOC_RESET_CONF_NIC_2_CLK_RST_CTRL 0x4C74D78 + +#define mmPSOC_RESET_CONF_NIC_3_CLK_RST_CTRL 0x4C74D7C + +#define mmPSOC_RESET_CONF_NIC_4_CLK_RST_CTRL 0x4C74D80 + +#define mmPSOC_RESET_CONF_NIC_5_CLK_RST_CTRL 0x4C74D84 + +#define mmPSOC_RESET_CONF_NIC_6_CLK_RST_CTRL 0x4C74D88 + +#define mmPSOC_RESET_CONF_NIC_7_CLK_RST_CTRL 0x4C74D8C + +#define mmPSOC_RESET_CONF_NIC_8_CLK_RST_CTRL 0x4C74D90 + +#define mmPSOC_RESET_CONF_NIC_9_CLK_RST_CTRL 0x4C74D94 + +#define mmPSOC_RESET_CONF_NIC_10_CLK_RST_CTRL 0x4C74D98 + +#define mmPSOC_RESET_CONF_NIC_11_CLK_RST_CTRL 0x4C74D9C + +#define mmPSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL 0x4C74DA0 + +#define mmPSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL 0x4C74DA4 + +#define mmPSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL 0x4C74DA8 + +#define mmPSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL 0x4C74DAC + +#define mmPSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL 0x4C74DB0 + +#define mmPSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL 0x4C74DB4 + +#define mmPSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL 0x4C74DB8 + +#define mmPSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL 0x4C74DBC + +#define mmPSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL 0x4C74DC0 + +#define mmPSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL 0x4C74DC4 + +#define mmPSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL 0x4C74DC8 + +#define mmPSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL 0x4C74DCC + +#define mmPSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL 0x4C74DD0 + +#define mmPSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL 0x4C74DD4 + +#define mmPSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL 0x4C74DD8 + +#endif /* ASIC_REG_PSOC_RESET_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000..699becc28 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP + * (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0x4C49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0x4C49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0x4C49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0x4C4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0x4C49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0x4C49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0x4C49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0x4C49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0x4C49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0x4C49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0x4C49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0x4C49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0x4C49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0x4C49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0x4C49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0x4C49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0x4C49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h new file mode 100644 index 000000000..79320320e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_DESC_REGS_H_ +#define ASIC_REG_ROT0_DESC_REGS_H_ + +/* + ***************************************** + * ROT0_DESC + * (Prototype: ROT_DESC) + ***************************************** + */ + +#define mmROT0_DESC_CONTEXT_ID 0x4E0B100 + +#define mmROT0_DESC_IN_IMG_START_ADDR_L 0x4E0B104 + +#define mmROT0_DESC_IN_IMG_START_ADDR_H 0x4E0B108 + +#define mmROT0_DESC_OUT_IMG_START_ADDR_L 0x4E0B10C + +#define mmROT0_DESC_OUT_IMG_START_ADDR_H 0x4E0B110 + +#define mmROT0_DESC_CFG 0x4E0B114 + +#define mmROT0_DESC_IM_READ_SLOPE 0x4E0B118 + +#define mmROT0_DESC_SIN_D 0x4E0B11C + +#define mmROT0_DESC_COS_D 0x4E0B120 + +#define mmROT0_DESC_IN_IMG 0x4E0B124 + +#define mmROT0_DESC_IN_STRIDE 0x4E0B128 + +#define mmROT0_DESC_IN_STRIPE 0x4E0B12C + +#define mmROT0_DESC_IN_CENTER 0x4E0B130 + +#define mmROT0_DESC_OUT_IMG 0x4E0B134 + +#define mmROT0_DESC_OUT_STRIDE 0x4E0B138 + +#define mmROT0_DESC_OUT_STRIPE 0x4E0B13C + +#define mmROT0_DESC_OUT_CENTER 0x4E0B140 + +#define mmROT0_DESC_BACKGROUND 0x4E0B144 + +#define mmROT0_DESC_CPL_MSG_EN 0x4E0B148 + +#define mmROT0_DESC_IDLE_STATE 0x4E0B14C + +#define mmROT0_DESC_CPL_MSG_ADDR 0x4E0B150 + +#define mmROT0_DESC_CPL_MSG_DATA 0x4E0B154 + +#define mmROT0_DESC_CPL_MSG_AWUSER 0x4E0B158 + +#define mmROT0_DESC_X_I_START_OFFSET 0x4E0B15C + +#define mmROT0_DESC_X_I_START_OFFSET_FLIP 0x4E0B160 + +#define mmROT0_DESC_X_I_FIRST 0x4E0B164 + +#define mmROT0_DESC_Y_I_FIRST 0x4E0B168 + +#define mmROT0_DESC_Y_I 0x4E0B16C + +#define mmROT0_DESC_OUT_STRIPE_SIZE 0x4E0B170 + +#define mmROT0_DESC_RSB_CFG_0 0x4E0B174 + +#define mmROT0_DESC_RSB_PAD_VAL 0x4E0B178 + +#define mmROT0_DESC_HBW_ARUSER_HI 0x4E0B17C + +#define mmROT0_DESC_HBW_ARUSER_LO 0x4E0B180 + +#define mmROT0_DESC_HBW_AWUSER_HI 0x4E0B184 + +#define mmROT0_DESC_HBW_AWUSER_LO 0x4E0B188 + +#define mmROT0_DESC_OWM_CFG 0x4E0B18C + +#define mmROT0_DESC_CTRL_CFG 0x4E0B190 + +#define mmROT0_DESC_PIXEL_PAD 0x4E0B194 + +#define mmROT0_DESC_PREC_SHIFT 0x4E0B198 + +#define mmROT0_DESC_MAX_VAL 0x4E0B19C + +#define mmROT0_DESC_A0_M11 0x4E0B1A0 + +#define mmROT0_DESC_A1_M12 0x4E0B1A4 + +#define mmROT0_DESC_A2 0x4E0B1A8 + +#define mmROT0_DESC_B0_M21 0x4E0B1AC + +#define mmROT0_DESC_B1_M22 0x4E0B1B0 + +#define mmROT0_DESC_B2 0x4E0B1B4 + +#define mmROT0_DESC_C0 0x4E0B1B8 + +#define mmROT0_DESC_C1 0x4E0B1BC + +#define mmROT0_DESC_C2 0x4E0B1C0 + +#define mmROT0_DESC_D0 0x4E0B1C4 + +#define mmROT0_DESC_D1 0x4E0B1C8 + +#define mmROT0_DESC_D2 0x4E0B1CC + +#define mmROT0_DESC_INV_PROC_SIZE_M_1 0x4E0B1D0 + +#define mmROT0_DESC_MESH_IMG_START_ADDR_L 0x4E0B1D4 + +#define mmROT0_DESC_MESH_IMG_START_ADDR_H 0x4E0B1D8 + +#define mmROT0_DESC_MESH_IMG 0x4E0B1DC + +#define mmROT0_DESC_MESH_STRIDE 0x4E0B1E0 + +#define mmROT0_DESC_MESH_STRIPE 0x4E0B1E4 + +#define mmROT0_DESC_MESH_CTRL 0x4E0B1E8 + +#define mmROT0_DESC_MESH_GH 0x4E0B1EC + +#define mmROT0_DESC_MESH_GV 0x4E0B1F0 + +#define mmROT0_DESC_MRSB_CFG_0 0x4E0B1F4 + +#define mmROT0_DESC_MRSB_PAD_VAL 0x4E0B1F8 + +#define mmROT0_DESC_BUF_CFG 0x4E0B1FC + +#define mmROT0_DESC_CID_OFFSET 0x4E0B200 + +#define mmROT0_DESC_PUSH_DESC 0x4E0B204 + +#endif /* ASIC_REG_ROT0_DESC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h new file mode 100644 index 000000000..f2e739ede --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_MASKS_H_ +#define ASIC_REG_ROT0_MASKS_H_ + +/* + ***************************************** + * ROT0 + * (Prototype: ROTATOR) + ***************************************** + */ + +/* ROT0_KMD_MODE */ +#define ROT0_KMD_MODE_EN_SHIFT 0 +#define ROT0_KMD_MODE_EN_MASK 0x1 + +/* ROT0_CPL_QUEUE_EN */ +#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0 +#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1 + +/* ROT0_CPL_QUEUE_ADDR_L */ +#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_ADDR_H */ +#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_DATA */ +#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_AWUSER */ +#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_AXI */ +#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0 +#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF +#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4 +#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70 + +/* ROT0_CPL_MSG_THRESHOLD */ +#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0 +#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F + +/* ROT0_CPL_MSG_AXI */ +#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0 +#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF +#define ROT0_CPL_MSG_AXI_PROT_SHIFT 4 +#define ROT0_CPL_MSG_AXI_PROT_MASK 0x70 + +/* ROT0_AXI_WB */ +#define ROT0_AXI_WB_CACHE_SHIFT 0 +#define ROT0_AXI_WB_CACHE_MASK 0xF +#define ROT0_AXI_WB_PROT_SHIFT 4 +#define ROT0_AXI_WB_PROT_MASK 0x70 + +/* ROT0_ERR_CFG */ +#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0 +#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1 + +/* ROT0_ERR_STATUS */ +#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0 +#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1 +#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1 +#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2 +#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2 +#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4 +#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3 +#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8 +#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4 +#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10 + +/* ROT0_WBC_MAX_OUTSTANDING */ +#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0 +#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF + +/* ROT0_WBC_RL */ +#define ROT0_WBC_RL_SATURATION_SHIFT 0 +#define ROT0_WBC_RL_SATURATION_MASK 0xFF +#define ROT0_WBC_RL_TIMEOUT_SHIFT 8 +#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_WBC_RL_RST_TOKEN_SHIFT 16 +#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_WBC_INFLIGHTS */ +#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF + +/* ROT0_WBC_INFO */ +#define ROT0_WBC_INFO_EMPTY_SHIFT 0 +#define ROT0_WBC_INFO_EMPTY_MASK 0x1 +#define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_WBC_MON */ +#define ROT0_WBC_MON_CNT_SHIFT 0 +#define ROT0_WBC_MON_CNT_MASK 0x1 +#define ROT0_WBC_MON_TS_SHIFT 8 +#define ROT0_WBC_MON_TS_MASK 0x300 +#define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16 +#define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000 + +/* ROT0_RSB_CAM_MAX_SIZE */ +#define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0 +#define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF +#define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16 +#define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* ROT0_RSB_CFG */ +#define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0 +#define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1 +#define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1 +#define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2 + +/* ROT0_RSB_MAX_OS */ +#define ROT0_RSB_MAX_OS_VAL_SHIFT 0 +#define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF + +/* ROT0_RSB_RL */ +#define ROT0_RSB_RL_SATURATION_SHIFT 0 +#define ROT0_RSB_RL_SATURATION_MASK 0xFF +#define ROT0_RSB_RL_TIMEOUT_SHIFT 8 +#define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_RSB_RL_RST_TOKEN_SHIFT 16 +#define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_RSB_INFLIGHTS */ +#define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ROT0_RSB_OCCUPANCY */ +#define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0 +#define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF + +/* ROT0_RSB_INFO */ +#define ROT0_RSB_INFO_EMPTY_SHIFT 0 +#define ROT0_RSB_INFO_EMPTY_MASK 0x1 +#define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_RSB_MON */ +#define ROT0_RSB_MON_CNT_SHIFT 0 +#define ROT0_RSB_MON_CNT_MASK 0x1FFF +#define ROT0_RSB_MON_TS_SHIFT 16 +#define ROT0_RSB_MON_TS_MASK 0x30000 + +/* ROT0_RSB_MON_CONTEXT_ID */ +#define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0 +#define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ROT0_MSS_HALT */ +#define ROT0_MSS_HALT_VAL_SHIFT 0 +#define ROT0_MSS_HALT_VAL_MASK 0x7 + +/* ROT0_MSS_SEI_STATUS */ +#define ROT0_MSS_SEI_STATUS_I0_SHIFT 0 +#define ROT0_MSS_SEI_STATUS_I0_MASK 0x1 +#define ROT0_MSS_SEI_STATUS_I1_SHIFT 1 +#define ROT0_MSS_SEI_STATUS_I1_MASK 0x2 +#define ROT0_MSS_SEI_STATUS_I2_SHIFT 2 +#define ROT0_MSS_SEI_STATUS_I2_MASK 0x4 +#define ROT0_MSS_SEI_STATUS_I3_SHIFT 3 +#define ROT0_MSS_SEI_STATUS_I3_MASK 0x8 +#define ROT0_MSS_SEI_STATUS_I4_SHIFT 4 +#define ROT0_MSS_SEI_STATUS_I4_MASK 0x10 +#define ROT0_MSS_SEI_STATUS_I5_SHIFT 5 +#define ROT0_MSS_SEI_STATUS_I5_MASK 0x20 +#define ROT0_MSS_SEI_STATUS_I6_SHIFT 6 +#define ROT0_MSS_SEI_STATUS_I6_MASK 0x40 +#define ROT0_MSS_SEI_STATUS_I7_SHIFT 7 +#define ROT0_MSS_SEI_STATUS_I7_MASK 0x80 +#define ROT0_MSS_SEI_STATUS_I8_SHIFT 8 +#define ROT0_MSS_SEI_STATUS_I8_MASK 0x100 +#define ROT0_MSS_SEI_STATUS_I9_SHIFT 9 +#define ROT0_MSS_SEI_STATUS_I9_MASK 0x200 +#define ROT0_MSS_SEI_STATUS_I10_SHIFT 10 +#define ROT0_MSS_SEI_STATUS_I10_MASK 0x400 +#define ROT0_MSS_SEI_STATUS_I11_SHIFT 11 +#define ROT0_MSS_SEI_STATUS_I11_MASK 0x800 +#define ROT0_MSS_SEI_STATUS_I12_SHIFT 12 +#define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000 +#define ROT0_MSS_SEI_STATUS_I13_SHIFT 13 +#define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000 +#define ROT0_MSS_SEI_STATUS_I14_SHIFT 14 +#define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000 +#define ROT0_MSS_SEI_STATUS_I15_SHIFT 15 +#define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000 +#define ROT0_MSS_SEI_STATUS_I16_SHIFT 16 +#define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000 +#define ROT0_MSS_SEI_STATUS_I17_SHIFT 17 +#define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000 +#define ROT0_MSS_SEI_STATUS_I18_SHIFT 18 +#define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000 +#define ROT0_MSS_SEI_STATUS_I19_SHIFT 19 +#define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000 +#define ROT0_MSS_SEI_STATUS_I20_SHIFT 20 +#define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000 +#define ROT0_MSS_SEI_STATUS_I21_SHIFT 21 +#define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000 + +/* ROT0_MSS_SEI_MASK */ +#define ROT0_MSS_SEI_MASK_VAL_SHIFT 0 +#define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF + +/* ROT0_MSS_SPI_STATUS */ +#define ROT0_MSS_SPI_STATUS_I0_SHIFT 0 +#define ROT0_MSS_SPI_STATUS_I0_MASK 0x1 +#define ROT0_MSS_SPI_STATUS_I1_SHIFT 1 +#define ROT0_MSS_SPI_STATUS_I1_MASK 0x2 +#define ROT0_MSS_SPI_STATUS_I2_SHIFT 2 +#define ROT0_MSS_SPI_STATUS_I2_MASK 0x4 +#define ROT0_MSS_SPI_STATUS_I3_SHIFT 3 +#define ROT0_MSS_SPI_STATUS_I3_MASK 0x8 +#define ROT0_MSS_SPI_STATUS_I4_SHIFT 4 +#define ROT0_MSS_SPI_STATUS_I4_MASK 0x10 +#define ROT0_MSS_SPI_STATUS_I5_SHIFT 5 +#define ROT0_MSS_SPI_STATUS_I5_MASK 0x20 +#define ROT0_MSS_SPI_STATUS_I6_SHIFT 6 +#define ROT0_MSS_SPI_STATUS_I6_MASK 0x40 +#define ROT0_MSS_SPI_STATUS_I7_SHIFT 7 +#define ROT0_MSS_SPI_STATUS_I7_MASK 0x80 + +/* ROT0_MSS_SPI_MASK */ +#define ROT0_MSS_SPI_MASK_VAL_SHIFT 0 +#define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF + +/* ROT0_DISABLE_PAD_CALC */ +#define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0 +#define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3 + +/* ROT0_QMAN_CFG */ +#define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0 +#define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1 + +/* ROT0_CLK_EN */ +#define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10 +#define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5 +#define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20 + +/* ROT0_MRSB_CAM_MAX_SIZE */ +#define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0 +#define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF +#define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16 +#define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* ROT0_MRSB_CFG */ +#define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0 +#define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1 +#define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1 +#define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2 + +/* ROT0_MRSB_MAX_OS */ +#define ROT0_MRSB_MAX_OS_VAL_SHIFT 0 +#define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF + +/* ROT0_MRSB_RL */ +#define ROT0_MRSB_RL_SATURATION_SHIFT 0 +#define ROT0_MRSB_RL_SATURATION_MASK 0xFF +#define ROT0_MRSB_RL_TIMEOUT_SHIFT 8 +#define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16 +#define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_MRSB_INFLIGHTS */ +#define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ROT0_MRSB_OCCUPANCY */ +#define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0 +#define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF + +/* ROT0_MRSB_INFO */ +#define ROT0_MRSB_INFO_EMPTY_SHIFT 0 +#define ROT0_MRSB_INFO_EMPTY_MASK 0x1 +#define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_MRSB_MON */ +#define ROT0_MRSB_MON_CNT_SHIFT 0 +#define ROT0_MRSB_MON_CNT_MASK 0x1FFF +#define ROT0_MRSB_MON_TS_SHIFT 16 +#define ROT0_MRSB_MON_TS_MASK 0x30000 + +/* ROT0_MRSB_MON_CONTEXT_ID */ +#define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0 +#define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ROT0_MSS_STS */ +#define ROT0_MSS_STS_IS_HALT_SHIFT 0 +#define ROT0_MSS_STS_IS_HALT_MASK 0x1 + +#endif /* ASIC_REG_ROT0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h new file mode 100644 index 000000000..e83daa33d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * ROT0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100 + +#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104 + +#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108 + +#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C + +#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110 + +#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114 + +#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118 + +#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C + +#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120 + +#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124 + +#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128 + +#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C + +#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130 + +#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134 + +#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138 + +#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C + +#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140 + +#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144 + +#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150 + +#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154 + +#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158 + +#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C + +#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160 + +#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164 + +#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168 + +#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C + +#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170 + +#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174 + +#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178 + +#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E081A8 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E081AC + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E081B0 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E081B4 + +#define mmROT0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4E081B8 + +#define mmROT0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4E081BC + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_0 0x4E081C0 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_1 0x4E081C4 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_2 0x4E081C8 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_3 0x4E081CC + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_4 0x4E081D0 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_5 0x4E081D4 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_6 0x4E081D8 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_7 0x4E081DC + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_0 0x4E081E0 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_1 0x4E081E4 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_2 0x4E081E8 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_3 0x4E081EC + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_4 0x4E081F0 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_5 0x4E081F4 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_6 0x4E081F8 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_7 0x4E081FC + +#define mmROT0_QM_ARC_AUX_SW_INTR_0 0x4E08200 + +#define mmROT0_QM_ARC_AUX_SW_INTR_1 0x4E08204 + +#define mmROT0_QM_ARC_AUX_SW_INTR_2 0x4E08208 + +#define mmROT0_QM_ARC_AUX_SW_INTR_3 0x4E0820C + +#define mmROT0_QM_ARC_AUX_SW_INTR_4 0x4E08210 + +#define mmROT0_QM_ARC_AUX_SW_INTR_5 0x4E08214 + +#define mmROT0_QM_ARC_AUX_SW_INTR_6 0x4E08218 + +#define mmROT0_QM_ARC_AUX_SW_INTR_7 0x4E0821C + +#define mmROT0_QM_ARC_AUX_SW_INTR_8 0x4E08220 + +#define mmROT0_QM_ARC_AUX_SW_INTR_9 0x4E08224 + +#define mmROT0_QM_ARC_AUX_SW_INTR_10 0x4E08228 + +#define mmROT0_QM_ARC_AUX_SW_INTR_11 0x4E0822C + +#define mmROT0_QM_ARC_AUX_SW_INTR_12 0x4E08230 + +#define mmROT0_QM_ARC_AUX_SW_INTR_13 0x4E08234 + +#define mmROT0_QM_ARC_AUX_SW_INTR_14 0x4E08238 + +#define mmROT0_QM_ARC_AUX_SW_INTR_15 0x4E0823C + +#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4E08280 + +#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4E08284 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4E08290 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4E08294 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4E08298 + +#define mmROT0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4E0829C + +#define mmROT0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4E082A0 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4E082A4 + +#define mmROT0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E082A8 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4E082B0 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4E082B4 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4E082B8 + +#define mmROT0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4E082BC + +#define mmROT0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4E082C0 + +#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4E082C4 + +#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4E082C8 + +#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4E082CC + +#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4E082D0 + +#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E082E0 + +#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E082E4 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4E082E8 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4E082EC + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E082F0 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E082F4 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_0 0x4E08300 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_1 0x4E08304 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_2 0x4E08308 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_3 0x4E0830C + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_4 0x4E08310 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_5 0x4E08314 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_6 0x4E08318 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_7 0x4E0831C + +#define mmROT0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4E08320 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4E08324 + +#define mmROT0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4E08328 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4E0832C + +#define mmROT0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4E08330 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4E08334 + +#define mmROT0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4E08338 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4E0833C + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4E08350 + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4E08354 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4E08358 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4E0835C + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4E08360 + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E08364 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4E08368 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E0836C + +#define mmROT0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4E08370 + +#define mmROT0_QM_ARC_AUX_CBU_LOCK_OVR 0x4E08374 + +#define mmROT0_QM_ARC_AUX_CBU_PROT_OVR 0x4E08378 + +#define mmROT0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4E0837C + +#define mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4E08380 + +#define mmROT0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4E08384 + +#define mmROT0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4E0838C + +#define mmROT0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4E08390 + +#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4E08400 + +#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4E08404 + +#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4E08408 + +#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4E0840C + +#define mmROT0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4E08420 + +#define mmROT0_QM_ARC_AUX_LBU_LOCK_OVR 0x4E08424 + +#define mmROT0_QM_ARC_AUX_LBU_PROT_OVR 0x4E08428 + +#define mmROT0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4E0842C + +#define mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4E08430 + +#define mmROT0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4E08434 + +#define mmROT0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4E0843C + +#define mmROT0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4E08440 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E08500 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E08504 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E08508 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E0850C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E08510 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E08514 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E08518 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E0851C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4E08520 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4E08524 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4E08528 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4E0852C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4E08530 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4E08534 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4E08538 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4E0853C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4E08540 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4E08544 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4E08548 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4E0854C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4E08550 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4E08554 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4E08558 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4E0855C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4E08560 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4E08564 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4E08568 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4E0856C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4E08570 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4E08574 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4E08578 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4E0857C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E08580 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E08584 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E08588 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E0858C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E08590 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E08594 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E08598 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E0859C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E085A0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E085A4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E085A8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E085AC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E085B0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E085B4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E085B8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E085BC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E085C0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E085C4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E085C8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E085CC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E085D0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E085D4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E085D8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E085DC + +#define mmROT0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E085E0 + +#define mmROT0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E085E4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4E08620 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4E08624 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4E08628 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4E08630 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4E08634 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4E08638 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4E0863C + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4E08640 + +#define mmROT0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4E08644 + +#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E08648 + +#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E0864C + +#define mmROT0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E08650 + +#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E08654 + +#define mmROT0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4E08658 + +#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E0865C + +#define mmROT0_QM_ARC_AUX_AUX2APB_PROT 0x4E08700 + +#define mmROT0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4E08704 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E08708 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E0870C + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E08710 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E08714 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E08718 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E0871C + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E08720 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E08724 + +#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E08728 + +#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E0872C + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E08730 + +#define mmROT0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E08734 + +#define mmROT0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E08738 + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E0873C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4E08740 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E08750 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E08754 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E08758 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E0875C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E08760 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E08764 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E08768 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E0876C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E08770 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E08774 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E08778 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E0877C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E08780 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E08784 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E08788 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E0878C + +#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E08790 + +#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E08794 + +#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4E08798 + +#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4E0879C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4E08800 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4E08804 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4E08808 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4E0880C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4E08810 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4E08814 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4E08818 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4E0881C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4E08820 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4E08824 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4E08828 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4E0882C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4E08830 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4E08834 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4E08838 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4E0883C + +#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E08840 + +#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E08844 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E08848 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E0884C + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4E08850 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4E08854 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E08900 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4E08904 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E08908 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4E0890C + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4E08910 + +#define mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4E08920 + +#endif /* ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000..8e040a2ef --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * ROT0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmROT0_QM_AXUSER_NONSECURED_HB_ASID 0x4E0AB80 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4E0AB84 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4E0AB88 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4E0AB8C + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4E0AB90 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4E0AB94 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_QOS 0x4E0AB98 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RSVD 0x4E0AB9C + +#define mmROT0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4E0ABA0 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_CORE 0x4E0ABA4 + +#define mmROT0_QM_AXUSER_NONSECURED_E2E_COORD 0x4E0ABA8 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4E0ABB0 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4E0ABB4 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4E0ABB8 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4E0ABBC + +#define mmROT0_QM_AXUSER_NONSECURED_LB_COORD 0x4E0ABC0 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_LOCK 0x4E0ABC4 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_RSVD 0x4E0ABC8 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_OVRD 0x4E0ABCC + +#endif /* ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h new file mode 100644 index 000000000..077ae2347 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_CGM_REGS_H_ +#define ASIC_REG_ROT0_QM_CGM_REGS_H_ + +/* + ***************************************** + * ROT0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmROT0_QM_CGM_CFG 0x4E0AD80 + +#define mmROT0_QM_CGM_STS 0x4E0AD84 + +#define mmROT0_QM_CGM_CFG1 0x4E0AD88 + +#endif /* ASIC_REG_ROT0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h new file mode 100644 index 000000000..de3c85510 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_REGS_H_ +#define ASIC_REG_ROT0_QM_REGS_H_ + +/* + ***************************************** + * ROT0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmROT0_QM_GLBL_CFG0 0x4E0A000 + +#define mmROT0_QM_GLBL_CFG1 0x4E0A004 + +#define mmROT0_QM_GLBL_CFG2 0x4E0A008 + +#define mmROT0_QM_GLBL_ERR_CFG 0x4E0A00C + +#define mmROT0_QM_GLBL_ERR_CFG1 0x4E0A010 + +#define mmROT0_QM_GLBL_ERR_ARC_HALT_EN 0x4E0A014 + +#define mmROT0_QM_GLBL_AXCACHE 0x4E0A018 + +#define mmROT0_QM_GLBL_STS0 0x4E0A01C + +#define mmROT0_QM_GLBL_STS1 0x4E0A020 + +#define mmROT0_QM_GLBL_ERR_STS_0 0x4E0A024 + +#define mmROT0_QM_GLBL_ERR_STS_1 0x4E0A028 + +#define mmROT0_QM_GLBL_ERR_STS_2 0x4E0A02C + +#define mmROT0_QM_GLBL_ERR_STS_3 0x4E0A030 + +#define mmROT0_QM_GLBL_ERR_STS_4 0x4E0A034 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_0 0x4E0A038 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_1 0x4E0A03C + +#define mmROT0_QM_GLBL_ERR_MSG_EN_2 0x4E0A040 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_3 0x4E0A044 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_4 0x4E0A048 + +#define mmROT0_QM_GLBL_PROT 0x4E0A04C + +#define mmROT0_QM_PQ_BASE_LO_0 0x4E0A050 + +#define mmROT0_QM_PQ_BASE_LO_1 0x4E0A054 + +#define mmROT0_QM_PQ_BASE_LO_2 0x4E0A058 + +#define mmROT0_QM_PQ_BASE_LO_3 0x4E0A05C + +#define mmROT0_QM_PQ_BASE_HI_0 0x4E0A060 + +#define mmROT0_QM_PQ_BASE_HI_1 0x4E0A064 + +#define mmROT0_QM_PQ_BASE_HI_2 0x4E0A068 + +#define mmROT0_QM_PQ_BASE_HI_3 0x4E0A06C + +#define mmROT0_QM_PQ_SIZE_0 0x4E0A070 + +#define mmROT0_QM_PQ_SIZE_1 0x4E0A074 + +#define mmROT0_QM_PQ_SIZE_2 0x4E0A078 + +#define mmROT0_QM_PQ_SIZE_3 0x4E0A07C + +#define mmROT0_QM_PQ_PI_0 0x4E0A080 + +#define mmROT0_QM_PQ_PI_1 0x4E0A084 + +#define mmROT0_QM_PQ_PI_2 0x4E0A088 + +#define mmROT0_QM_PQ_PI_3 0x4E0A08C + +#define mmROT0_QM_PQ_CI_0 0x4E0A090 + +#define mmROT0_QM_PQ_CI_1 0x4E0A094 + +#define mmROT0_QM_PQ_CI_2 0x4E0A098 + +#define mmROT0_QM_PQ_CI_3 0x4E0A09C + +#define mmROT0_QM_PQ_CFG0_0 0x4E0A0A0 + +#define mmROT0_QM_PQ_CFG0_1 0x4E0A0A4 + +#define mmROT0_QM_PQ_CFG0_2 0x4E0A0A8 + +#define mmROT0_QM_PQ_CFG0_3 0x4E0A0AC + +#define mmROT0_QM_PQ_CFG1_0 0x4E0A0B0 + +#define mmROT0_QM_PQ_CFG1_1 0x4E0A0B4 + +#define mmROT0_QM_PQ_CFG1_2 0x4E0A0B8 + +#define mmROT0_QM_PQ_CFG1_3 0x4E0A0BC + +#define mmROT0_QM_PQ_STS0_0 0x4E0A0C0 + +#define mmROT0_QM_PQ_STS0_1 0x4E0A0C4 + +#define mmROT0_QM_PQ_STS0_2 0x4E0A0C8 + +#define mmROT0_QM_PQ_STS0_3 0x4E0A0CC + +#define mmROT0_QM_PQ_STS1_0 0x4E0A0D0 + +#define mmROT0_QM_PQ_STS1_1 0x4E0A0D4 + +#define mmROT0_QM_PQ_STS1_2 0x4E0A0D8 + +#define mmROT0_QM_PQ_STS1_3 0x4E0A0DC + +#define mmROT0_QM_CQ_CFG0_0 0x4E0A0E0 + +#define mmROT0_QM_CQ_CFG0_1 0x4E0A0E4 + +#define mmROT0_QM_CQ_CFG0_2 0x4E0A0E8 + +#define mmROT0_QM_CQ_CFG0_3 0x4E0A0EC + +#define mmROT0_QM_CQ_CFG0_4 0x4E0A0F0 + +#define mmROT0_QM_CQ_STS0_0 0x4E0A0F4 + +#define mmROT0_QM_CQ_STS0_1 0x4E0A0F8 + +#define mmROT0_QM_CQ_STS0_2 0x4E0A0FC + +#define mmROT0_QM_CQ_STS0_3 0x4E0A100 + +#define mmROT0_QM_CQ_STS0_4 0x4E0A104 + +#define mmROT0_QM_CQ_CFG1_0 0x4E0A108 + +#define mmROT0_QM_CQ_CFG1_1 0x4E0A10C + +#define mmROT0_QM_CQ_CFG1_2 0x4E0A110 + +#define mmROT0_QM_CQ_CFG1_3 0x4E0A114 + +#define mmROT0_QM_CQ_CFG1_4 0x4E0A118 + +#define mmROT0_QM_CQ_STS1_0 0x4E0A11C + +#define mmROT0_QM_CQ_STS1_1 0x4E0A120 + +#define mmROT0_QM_CQ_STS1_2 0x4E0A124 + +#define mmROT0_QM_CQ_STS1_3 0x4E0A128 + +#define mmROT0_QM_CQ_STS1_4 0x4E0A12C + +#define mmROT0_QM_CQ_PTR_LO_0 0x4E0A150 + +#define mmROT0_QM_CQ_PTR_HI_0 0x4E0A154 + +#define mmROT0_QM_CQ_TSIZE_0 0x4E0A158 + +#define mmROT0_QM_CQ_CTL_0 0x4E0A15C + +#define mmROT0_QM_CQ_PTR_LO_1 0x4E0A160 + +#define mmROT0_QM_CQ_PTR_HI_1 0x4E0A164 + +#define mmROT0_QM_CQ_TSIZE_1 0x4E0A168 + +#define mmROT0_QM_CQ_CTL_1 0x4E0A16C + +#define mmROT0_QM_CQ_PTR_LO_2 0x4E0A170 + +#define mmROT0_QM_CQ_PTR_HI_2 0x4E0A174 + +#define mmROT0_QM_CQ_TSIZE_2 0x4E0A178 + +#define mmROT0_QM_CQ_CTL_2 0x4E0A17C + +#define mmROT0_QM_CQ_PTR_LO_3 0x4E0A180 + +#define mmROT0_QM_CQ_PTR_HI_3 0x4E0A184 + +#define mmROT0_QM_CQ_TSIZE_3 0x4E0A188 + +#define mmROT0_QM_CQ_CTL_3 0x4E0A18C + +#define mmROT0_QM_CQ_PTR_LO_4 0x4E0A190 + +#define mmROT0_QM_CQ_PTR_HI_4 0x4E0A194 + +#define mmROT0_QM_CQ_TSIZE_4 0x4E0A198 + +#define mmROT0_QM_CQ_CTL_4 0x4E0A19C + +#define mmROT0_QM_CQ_TSIZE_STS_0 0x4E0A1A0 + +#define mmROT0_QM_CQ_TSIZE_STS_1 0x4E0A1A4 + +#define mmROT0_QM_CQ_TSIZE_STS_2 0x4E0A1A8 + +#define mmROT0_QM_CQ_TSIZE_STS_3 0x4E0A1AC + +#define mmROT0_QM_CQ_TSIZE_STS_4 0x4E0A1B0 + +#define mmROT0_QM_CQ_PTR_LO_STS_0 0x4E0A1B4 + +#define mmROT0_QM_CQ_PTR_LO_STS_1 0x4E0A1B8 + +#define mmROT0_QM_CQ_PTR_LO_STS_2 0x4E0A1BC + +#define mmROT0_QM_CQ_PTR_LO_STS_3 0x4E0A1C0 + +#define mmROT0_QM_CQ_PTR_LO_STS_4 0x4E0A1C4 + +#define mmROT0_QM_CQ_PTR_HI_STS_0 0x4E0A1C8 + +#define mmROT0_QM_CQ_PTR_HI_STS_1 0x4E0A1CC + +#define mmROT0_QM_CQ_PTR_HI_STS_2 0x4E0A1D0 + +#define mmROT0_QM_CQ_PTR_HI_STS_3 0x4E0A1D4 + +#define mmROT0_QM_CQ_PTR_HI_STS_4 0x4E0A1D8 + +#define mmROT0_QM_CQ_IFIFO_STS_0 0x4E0A1DC + +#define mmROT0_QM_CQ_IFIFO_STS_1 0x4E0A1E0 + +#define mmROT0_QM_CQ_IFIFO_STS_2 0x4E0A1E4 + +#define mmROT0_QM_CQ_IFIFO_STS_3 0x4E0A1E8 + +#define mmROT0_QM_CQ_IFIFO_STS_4 0x4E0A1EC + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4E0A1F0 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4E0A1F4 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4E0A1F8 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4E0A1FC + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4E0A200 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4E0A204 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4E0A208 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4E0A20C + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4E0A210 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4E0A214 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4E0A218 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4E0A21C + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4E0A220 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4E0A224 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4E0A228 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4E0A22C + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4E0A230 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4E0A234 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4E0A238 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4E0A23C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4E0A240 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4E0A244 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4E0A248 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4E0A24C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4E0A250 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4E0A254 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4E0A258 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4E0A25C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4E0A260 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4E0A264 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4E0A268 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4E0A26C + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4E0A270 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4E0A274 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4E0A278 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4E0A27C + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4E0A280 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4E0A284 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4E0A288 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4E0A28C + +#define mmROT0_QM_CP_FENCE0_RDATA_0 0x4E0A290 + +#define mmROT0_QM_CP_FENCE0_RDATA_1 0x4E0A294 + +#define mmROT0_QM_CP_FENCE0_RDATA_2 0x4E0A298 + +#define mmROT0_QM_CP_FENCE0_RDATA_3 0x4E0A29C + +#define mmROT0_QM_CP_FENCE0_RDATA_4 0x4E0A2A0 + +#define mmROT0_QM_CP_FENCE1_RDATA_0 0x4E0A2A4 + +#define mmROT0_QM_CP_FENCE1_RDATA_1 0x4E0A2A8 + +#define mmROT0_QM_CP_FENCE1_RDATA_2 0x4E0A2AC + +#define mmROT0_QM_CP_FENCE1_RDATA_3 0x4E0A2B0 + +#define mmROT0_QM_CP_FENCE1_RDATA_4 0x4E0A2B4 + +#define mmROT0_QM_CP_FENCE2_RDATA_0 0x4E0A2B8 + +#define mmROT0_QM_CP_FENCE2_RDATA_1 0x4E0A2BC + +#define mmROT0_QM_CP_FENCE2_RDATA_2 0x4E0A2C0 + +#define mmROT0_QM_CP_FENCE2_RDATA_3 0x4E0A2C4 + +#define mmROT0_QM_CP_FENCE2_RDATA_4 0x4E0A2C8 + +#define mmROT0_QM_CP_FENCE3_RDATA_0 0x4E0A2CC + +#define mmROT0_QM_CP_FENCE3_RDATA_1 0x4E0A2D0 + +#define mmROT0_QM_CP_FENCE3_RDATA_2 0x4E0A2D4 + +#define mmROT0_QM_CP_FENCE3_RDATA_3 0x4E0A2D8 + +#define mmROT0_QM_CP_FENCE3_RDATA_4 0x4E0A2DC + +#define mmROT0_QM_CP_FENCE0_CNT_0 0x4E0A2E0 + +#define mmROT0_QM_CP_FENCE0_CNT_1 0x4E0A2E4 + +#define mmROT0_QM_CP_FENCE0_CNT_2 0x4E0A2E8 + +#define mmROT0_QM_CP_FENCE0_CNT_3 0x4E0A2EC + +#define mmROT0_QM_CP_FENCE0_CNT_4 0x4E0A2F0 + +#define mmROT0_QM_CP_FENCE1_CNT_0 0x4E0A2F4 + +#define mmROT0_QM_CP_FENCE1_CNT_1 0x4E0A2F8 + +#define mmROT0_QM_CP_FENCE1_CNT_2 0x4E0A2FC + +#define mmROT0_QM_CP_FENCE1_CNT_3 0x4E0A300 + +#define mmROT0_QM_CP_FENCE1_CNT_4 0x4E0A304 + +#define mmROT0_QM_CP_FENCE2_CNT_0 0x4E0A308 + +#define mmROT0_QM_CP_FENCE2_CNT_1 0x4E0A30C + +#define mmROT0_QM_CP_FENCE2_CNT_2 0x4E0A310 + +#define mmROT0_QM_CP_FENCE2_CNT_3 0x4E0A314 + +#define mmROT0_QM_CP_FENCE2_CNT_4 0x4E0A318 + +#define mmROT0_QM_CP_FENCE3_CNT_0 0x4E0A31C + +#define mmROT0_QM_CP_FENCE3_CNT_1 0x4E0A320 + +#define mmROT0_QM_CP_FENCE3_CNT_2 0x4E0A324 + +#define mmROT0_QM_CP_FENCE3_CNT_3 0x4E0A328 + +#define mmROT0_QM_CP_FENCE3_CNT_4 0x4E0A32C + +#define mmROT0_QM_CP_BARRIER_CFG 0x4E0A330 + +#define mmROT0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4E0A334 + +#define mmROT0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4E0A338 + +#define mmROT0_QM_CP_LDMA_TSIZE_OFFSET 0x4E0A33C + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4E0A340 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4E0A344 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4E0A348 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4E0A34C + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4E0A350 + +#define mmROT0_QM_CP_STS_0 0x4E0A368 + +#define mmROT0_QM_CP_STS_1 0x4E0A36C + +#define mmROT0_QM_CP_STS_2 0x4E0A370 + +#define mmROT0_QM_CP_STS_3 0x4E0A374 + +#define mmROT0_QM_CP_STS_4 0x4E0A378 + +#define mmROT0_QM_CP_CURRENT_INST_LO_0 0x4E0A37C + +#define mmROT0_QM_CP_CURRENT_INST_LO_1 0x4E0A380 + +#define mmROT0_QM_CP_CURRENT_INST_LO_2 0x4E0A384 + +#define mmROT0_QM_CP_CURRENT_INST_LO_3 0x4E0A388 + +#define mmROT0_QM_CP_CURRENT_INST_LO_4 0x4E0A38C + +#define mmROT0_QM_CP_CURRENT_INST_HI_0 0x4E0A390 + +#define mmROT0_QM_CP_CURRENT_INST_HI_1 0x4E0A394 + +#define mmROT0_QM_CP_CURRENT_INST_HI_2 0x4E0A398 + +#define mmROT0_QM_CP_CURRENT_INST_HI_3 0x4E0A39C + +#define mmROT0_QM_CP_CURRENT_INST_HI_4 0x4E0A3A0 + +#define mmROT0_QM_CP_PRED_0 0x4E0A3A4 + +#define mmROT0_QM_CP_PRED_1 0x4E0A3A8 + +#define mmROT0_QM_CP_PRED_2 0x4E0A3AC + +#define mmROT0_QM_CP_PRED_3 0x4E0A3B0 + +#define mmROT0_QM_CP_PRED_4 0x4E0A3B4 + +#define mmROT0_QM_CP_PRED_UPEN_0 0x4E0A3B8 + +#define mmROT0_QM_CP_PRED_UPEN_1 0x4E0A3BC + +#define mmROT0_QM_CP_PRED_UPEN_2 0x4E0A3C0 + +#define mmROT0_QM_CP_PRED_UPEN_3 0x4E0A3C4 + +#define mmROT0_QM_CP_PRED_UPEN_4 0x4E0A3C8 + +#define mmROT0_QM_CP_DBG_0_0 0x4E0A3CC + +#define mmROT0_QM_CP_DBG_0_1 0x4E0A3D0 + +#define mmROT0_QM_CP_DBG_0_2 0x4E0A3D4 + +#define mmROT0_QM_CP_DBG_0_3 0x4E0A3D8 + +#define mmROT0_QM_CP_DBG_0_4 0x4E0A3DC + +#define mmROT0_QM_CP_CPDMA_UP_CRED_0 0x4E0A3E0 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_1 0x4E0A3E4 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_2 0x4E0A3E8 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_3 0x4E0A3EC + +#define mmROT0_QM_CP_CPDMA_UP_CRED_4 0x4E0A3F0 + +#define mmROT0_QM_CP_IN_DATA_LO_0 0x4E0A3F4 + +#define mmROT0_QM_CP_IN_DATA_LO_1 0x4E0A3F8 + +#define mmROT0_QM_CP_IN_DATA_LO_2 0x4E0A3FC + +#define mmROT0_QM_CP_IN_DATA_LO_3 0x4E0A400 + +#define mmROT0_QM_CP_IN_DATA_LO_4 0x4E0A404 + +#define mmROT0_QM_CP_IN_DATA_HI_0 0x4E0A408 + +#define mmROT0_QM_CP_IN_DATA_HI_1 0x4E0A40C + +#define mmROT0_QM_CP_IN_DATA_HI_2 0x4E0A410 + +#define mmROT0_QM_CP_IN_DATA_HI_3 0x4E0A414 + +#define mmROT0_QM_CP_IN_DATA_HI_4 0x4E0A418 + +#define mmROT0_QM_PQC_HBW_BASE_LO_0 0x4E0A41C + +#define mmROT0_QM_PQC_HBW_BASE_LO_1 0x4E0A420 + +#define mmROT0_QM_PQC_HBW_BASE_LO_2 0x4E0A424 + +#define mmROT0_QM_PQC_HBW_BASE_LO_3 0x4E0A428 + +#define mmROT0_QM_PQC_HBW_BASE_HI_0 0x4E0A42C + +#define mmROT0_QM_PQC_HBW_BASE_HI_1 0x4E0A430 + +#define mmROT0_QM_PQC_HBW_BASE_HI_2 0x4E0A434 + +#define mmROT0_QM_PQC_HBW_BASE_HI_3 0x4E0A438 + +#define mmROT0_QM_PQC_SIZE_0 0x4E0A43C + +#define mmROT0_QM_PQC_SIZE_1 0x4E0A440 + +#define mmROT0_QM_PQC_SIZE_2 0x4E0A444 + +#define mmROT0_QM_PQC_SIZE_3 0x4E0A448 + +#define mmROT0_QM_PQC_PI_0 0x4E0A44C + +#define mmROT0_QM_PQC_PI_1 0x4E0A450 + +#define mmROT0_QM_PQC_PI_2 0x4E0A454 + +#define mmROT0_QM_PQC_PI_3 0x4E0A458 + +#define mmROT0_QM_PQC_LBW_WDATA_0 0x4E0A45C + +#define mmROT0_QM_PQC_LBW_WDATA_1 0x4E0A460 + +#define mmROT0_QM_PQC_LBW_WDATA_2 0x4E0A464 + +#define mmROT0_QM_PQC_LBW_WDATA_3 0x4E0A468 + +#define mmROT0_QM_PQC_LBW_BASE_LO_0 0x4E0A46C + +#define mmROT0_QM_PQC_LBW_BASE_LO_1 0x4E0A470 + +#define mmROT0_QM_PQC_LBW_BASE_LO_2 0x4E0A474 + +#define mmROT0_QM_PQC_LBW_BASE_LO_3 0x4E0A478 + +#define mmROT0_QM_PQC_LBW_BASE_HI_0 0x4E0A47C + +#define mmROT0_QM_PQC_LBW_BASE_HI_1 0x4E0A480 + +#define mmROT0_QM_PQC_LBW_BASE_HI_2 0x4E0A484 + +#define mmROT0_QM_PQC_LBW_BASE_HI_3 0x4E0A488 + +#define mmROT0_QM_PQC_CFG 0x4E0A48C + +#define mmROT0_QM_PQC_SECURE_PUSH_IND 0x4E0A490 + +#define mmROT0_QM_ARB_MASK 0x4E0A4A0 + +#define mmROT0_QM_ARB_CFG_0 0x4E0A4A4 + +#define mmROT0_QM_ARB_CHOICE_Q_PUSH 0x4E0A4A8 + +#define mmROT0_QM_ARB_WRR_WEIGHT_0 0x4E0A4AC + +#define mmROT0_QM_ARB_WRR_WEIGHT_1 0x4E0A4B0 + +#define mmROT0_QM_ARB_WRR_WEIGHT_2 0x4E0A4B4 + +#define mmROT0_QM_ARB_WRR_WEIGHT_3 0x4E0A4B8 + +#define mmROT0_QM_ARB_CFG_1 0x4E0A4BC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_0 0x4E0A4C0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_1 0x4E0A4C4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_2 0x4E0A4C8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_3 0x4E0A4CC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_4 0x4E0A4D0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_5 0x4E0A4D4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_6 0x4E0A4D8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_7 0x4E0A4DC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_8 0x4E0A4E0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_9 0x4E0A4E4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_10 0x4E0A4E8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_11 0x4E0A4EC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_12 0x4E0A4F0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_13 0x4E0A4F4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_14 0x4E0A4F8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_15 0x4E0A4FC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_16 0x4E0A500 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_17 0x4E0A504 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_18 0x4E0A508 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_19 0x4E0A50C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_20 0x4E0A510 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_21 0x4E0A514 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_22 0x4E0A518 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_23 0x4E0A51C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_24 0x4E0A520 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_25 0x4E0A524 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_26 0x4E0A528 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_27 0x4E0A52C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_28 0x4E0A530 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_29 0x4E0A534 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_30 0x4E0A538 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_31 0x4E0A53C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_32 0x4E0A540 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_33 0x4E0A544 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_34 0x4E0A548 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_35 0x4E0A54C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_36 0x4E0A550 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_37 0x4E0A554 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_38 0x4E0A558 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_39 0x4E0A55C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_40 0x4E0A560 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_41 0x4E0A564 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_42 0x4E0A568 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_43 0x4E0A56C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_44 0x4E0A570 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_45 0x4E0A574 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_46 0x4E0A578 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_47 0x4E0A57C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_48 0x4E0A580 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_49 0x4E0A584 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_50 0x4E0A588 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_51 0x4E0A58C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_52 0x4E0A590 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_53 0x4E0A594 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_54 0x4E0A598 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_55 0x4E0A59C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_56 0x4E0A5A0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_57 0x4E0A5A4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_58 0x4E0A5A8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_59 0x4E0A5AC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_60 0x4E0A5B0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_61 0x4E0A5B4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_62 0x4E0A5B8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_63 0x4E0A5BC + +#define mmROT0_QM_ARB_MST_CRED_INC 0x4E0A5E0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4E0A5E4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4E0A5E8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4E0A5EC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4E0A5F0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4E0A5F4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4E0A5F8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4E0A5FC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4E0A600 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4E0A604 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4E0A608 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4E0A60C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4E0A610 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4E0A614 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4E0A618 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4E0A61C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4E0A620 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4E0A624 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4E0A628 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4E0A62C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4E0A630 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4E0A634 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4E0A638 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4E0A63C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4E0A640 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4E0A644 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4E0A648 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4E0A64C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4E0A650 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4E0A654 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4E0A658 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4E0A65C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4E0A660 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4E0A664 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4E0A668 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4E0A66C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4E0A670 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4E0A674 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4E0A678 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4E0A67C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4E0A680 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4E0A684 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4E0A688 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4E0A68C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4E0A690 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4E0A694 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4E0A698 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4E0A69C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4E0A6A0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4E0A6A4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4E0A6A8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4E0A6AC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4E0A6B0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4E0A6B4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4E0A6B8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4E0A6BC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4E0A6C0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4E0A6C4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4E0A6C8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4E0A6CC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4E0A6D0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4E0A6D4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4E0A6D8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4E0A6DC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4E0A6E0 + +#define mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4E0A704 + +#define mmROT0_QM_ARB_MST_SLAVE_EN 0x4E0A708 + +#define mmROT0_QM_ARB_MST_SLAVE_EN_1 0x4E0A70C + +#define mmROT0_QM_ARB_SLV_CHOICE_WDT 0x4E0A710 + +#define mmROT0_QM_ARB_SLV_ID 0x4E0A714 + +#define mmROT0_QM_ARB_MST_QUIET_PER 0x4E0A718 + +#define mmROT0_QM_ARB_MSG_MAX_INFLIGHT 0x4E0A744 + +#define mmROT0_QM_ARB_BASE_LO 0x4E0A754 + +#define mmROT0_QM_ARB_BASE_HI 0x4E0A758 + +#define mmROT0_QM_ARB_STATE_STS 0x4E0A780 + +#define mmROT0_QM_ARB_CHOICE_FULLNESS_STS 0x4E0A784 + +#define mmROT0_QM_ARB_MSG_STS 0x4E0A788 + +#define mmROT0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4E0A78C + +#define mmROT0_QM_ARB_ERR_CAUSE 0x4E0A79C + +#define mmROT0_QM_ARB_ERR_MSG_EN 0x4E0A7A0 + +#define mmROT0_QM_ARB_ERR_STS_DRP 0x4E0A7A8 + +#define mmROT0_QM_ARB_MST_CRED_STS 0x4E0A7B0 + +#define mmROT0_QM_ARB_MST_CRED_STS_1 0x4E0A7B4 + +#define mmROT0_QM_CSMR_STRICT_PRIO_CFG 0x4E0A7FC + +#define mmROT0_QM_ARC_CQ_CFG0 0x4E0A800 + +#define mmROT0_QM_ARC_CQ_CFG1 0x4E0A804 + +#define mmROT0_QM_ARC_CQ_PTR_LO 0x4E0A808 + +#define mmROT0_QM_ARC_CQ_PTR_HI 0x4E0A80C + +#define mmROT0_QM_ARC_CQ_TSIZE 0x4E0A810 + +#define mmROT0_QM_ARC_CQ_CTL 0x4E0A814 + +#define mmROT0_QM_ARC_CQ_IFIFO_STS 0x4E0A81C + +#define mmROT0_QM_ARC_CQ_STS0 0x4E0A820 + +#define mmROT0_QM_ARC_CQ_STS1 0x4E0A824 + +#define mmROT0_QM_ARC_CQ_TSIZE_STS 0x4E0A828 + +#define mmROT0_QM_ARC_CQ_PTR_LO_STS 0x4E0A82C + +#define mmROT0_QM_ARC_CQ_PTR_HI_STS 0x4E0A830 + +#define mmROT0_QM_CP_WR_ARC_ADDR_HI 0x4E0A834 + +#define mmROT0_QM_CP_WR_ARC_ADDR_LO 0x4E0A838 + +#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4E0A83C + +#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4E0A840 + +#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4E0A844 + +#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4E0A848 + +#define mmROT0_QM_CQ_IFIFO_MSG_BASE_HI 0x4E0A84C + +#define mmROT0_QM_CQ_IFIFO_MSG_BASE_LO 0x4E0A850 + +#define mmROT0_QM_CQ_CTL_MSG_BASE_HI 0x4E0A854 + +#define mmROT0_QM_CQ_CTL_MSG_BASE_LO 0x4E0A858 + +#define mmROT0_QM_ADDR_OVRD 0x4E0A85C + +#define mmROT0_QM_CQ_IFIFO_CI_0 0x4E0A860 + +#define mmROT0_QM_CQ_IFIFO_CI_1 0x4E0A864 + +#define mmROT0_QM_CQ_IFIFO_CI_2 0x4E0A868 + +#define mmROT0_QM_CQ_IFIFO_CI_3 0x4E0A86C + +#define mmROT0_QM_CQ_IFIFO_CI_4 0x4E0A870 + +#define mmROT0_QM_ARC_CQ_IFIFO_CI 0x4E0A874 + +#define mmROT0_QM_CQ_CTL_CI_0 0x4E0A878 + +#define mmROT0_QM_CQ_CTL_CI_1 0x4E0A87C + +#define mmROT0_QM_CQ_CTL_CI_2 0x4E0A880 + +#define mmROT0_QM_CQ_CTL_CI_3 0x4E0A884 + +#define mmROT0_QM_CQ_CTL_CI_4 0x4E0A888 + +#define mmROT0_QM_ARC_CQ_CTL_CI 0x4E0A88C + +#define mmROT0_QM_CP_CFG 0x4E0A890 + +#define mmROT0_QM_CP_EXT_SWITCH 0x4E0A894 + +#define mmROT0_QM_CP_SWITCH_WD_SET 0x4E0A898 + +#define mmROT0_QM_CP_SWITCH_WD 0x4E0A89C + +#define mmROT0_QM_ARC_LB_ADDR_BASE_LO 0x4E0A8A4 + +#define mmROT0_QM_ARC_LB_ADDR_BASE_HI 0x4E0A8A8 + +#define mmROT0_QM_ENGINE_BASE_ADDR_HI 0x4E0A8AC + +#define mmROT0_QM_ENGINE_BASE_ADDR_LO 0x4E0A8B0 + +#define mmROT0_QM_ENGINE_ADDR_RANGE_SIZE 0x4E0A8B4 + +#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4E0A8B8 + +#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4E0A8BC + +#define mmROT0_QM_QM_BASE_ADDR_HI 0x4E0A8C0 + +#define mmROT0_QM_QM_BASE_ADDR_LO 0x4E0A8C4 + +#define mmROT0_QM_ARC_PQC_SECURE_PUSH_IND 0x4E0A8C8 + +#define mmROT0_QM_PQC_STS_0_0 0x4E0A8D0 + +#define mmROT0_QM_PQC_STS_0_1 0x4E0A8D4 + +#define mmROT0_QM_PQC_STS_0_2 0x4E0A8D8 + +#define mmROT0_QM_PQC_STS_0_3 0x4E0A8DC + +#define mmROT0_QM_PQC_STS_1_0 0x4E0A8E0 + +#define mmROT0_QM_PQC_STS_1_1 0x4E0A8E4 + +#define mmROT0_QM_PQC_STS_1_2 0x4E0A8E8 + +#define mmROT0_QM_PQC_STS_1_3 0x4E0A8EC + +#define mmROT0_QM_SEI_STATUS 0x4E0A8F0 + +#define mmROT0_QM_SEI_MASK 0x4E0A8F4 + +#define mmROT0_QM_GLBL_ERR_ADDR_LO 0x4E0AD00 + +#define mmROT0_QM_GLBL_ERR_ADDR_HI 0x4E0AD04 + +#define mmROT0_QM_GLBL_ERR_WDATA 0x4E0AD08 + +#define mmROT0_QM_L2H_MASK_LO 0x4E0AD14 + +#define mmROT0_QM_L2H_MASK_HI 0x4E0AD18 + +#define mmROT0_QM_L2H_CMPR_LO 0x4E0AD1C + +#define mmROT0_QM_L2H_CMPR_HI 0x4E0AD20 + +#define mmROT0_QM_LOCAL_RANGE_BASE 0x4E0AD24 + +#define mmROT0_QM_LOCAL_RANGE_SIZE 0x4E0AD28 + +#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_1 0x4E0AD30 + +#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_0 0x4E0AD34 + +#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_1 0x4E0AD38 + +#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_0 0x4E0AD3C + +#define mmROT0_QM_IND_GW_APB_CFG 0x4E0AD40 + +#define mmROT0_QM_IND_GW_APB_WDATA 0x4E0AD44 + +#define mmROT0_QM_IND_GW_APB_RDATA 0x4E0AD48 + +#define mmROT0_QM_IND_GW_APB_STATUS 0x4E0AD4C + +#define mmROT0_QM_PERF_CNT_FREE_LO 0x4E0AD60 + +#define mmROT0_QM_PERF_CNT_FREE_HI 0x4E0AD64 + +#define mmROT0_QM_PERF_CNT_IDLE_LO 0x4E0AD68 + +#define mmROT0_QM_PERF_CNT_IDLE_HI 0x4E0AD6C + +#define mmROT0_QM_PERF_CNT_CFG 0x4E0AD70 + +#endif /* ASIC_REG_ROT0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h new file mode 100644 index 000000000..7d85dc555 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_REGS_H_ +#define ASIC_REG_ROT0_REGS_H_ + +/* + ***************************************** + * ROT0 + * (Prototype: ROTATOR) + ***************************************** + */ + +#define mmROT0_KMD_MODE 0x4E0B000 + +#define mmROT0_CPL_QUEUE_EN 0x4E0B004 + +#define mmROT0_CPL_QUEUE_ADDR_L 0x4E0B008 + +#define mmROT0_CPL_QUEUE_ADDR_H 0x4E0B00C + +#define mmROT0_CPL_QUEUE_DATA 0x4E0B010 + +#define mmROT0_CPL_QUEUE_AWUSER 0x4E0B014 + +#define mmROT0_CPL_QUEUE_AXI 0x4E0B018 + +#define mmROT0_CPL_MSG_THRESHOLD 0x4E0B020 + +#define mmROT0_CPL_MSG_AXI 0x4E0B024 + +#define mmROT0_AXI_WB 0x4E0B028 + +#define mmROT0_ERR_CFG 0x4E0B02C + +#define mmROT0_ERR_STATUS 0x4E0B030 + +#define mmROT0_WBC_MAX_OUTSTANDING 0x4E0B038 + +#define mmROT0_WBC_RL 0x4E0B03C + +#define mmROT0_WBC_INFLIGHTS 0x4E0B040 + +#define mmROT0_WBC_INFO 0x4E0B044 + +#define mmROT0_WBC_MON 0x4E0B048 + +#define mmROT0_RSB_CAM_MAX_SIZE 0x4E0B04C + +#define mmROT0_RSB_CFG 0x4E0B050 + +#define mmROT0_RSB_MAX_OS 0x4E0B054 + +#define mmROT0_RSB_RL 0x4E0B058 + +#define mmROT0_RSB_INFLIGHTS 0x4E0B05C + +#define mmROT0_RSB_OCCUPANCY 0x4E0B060 + +#define mmROT0_RSB_INFO 0x4E0B064 + +#define mmROT0_RSB_MON 0x4E0B068 + +#define mmROT0_RSB_MON_CONTEXT_ID 0x4E0B06C + +#define mmROT0_MSS_HALT 0x4E0B070 + +#define mmROT0_MSS_SEI_STATUS 0x4E0B074 + +#define mmROT0_MSS_SEI_MASK 0x4E0B078 + +#define mmROT0_MSS_SPI_STATUS 0x4E0B07C + +#define mmROT0_MSS_SPI_MASK 0x4E0B080 + +#define mmROT0_DISABLE_PAD_CALC 0x4E0B084 + +#define mmROT0_QMAN_CFG 0x4E0B088 + +#define mmROT0_CLK_EN 0x4E0B08C + +#define mmROT0_MRSB_CAM_MAX_SIZE 0x4E0B090 + +#define mmROT0_MRSB_CFG 0x4E0B094 + +#define mmROT0_MRSB_MAX_OS 0x4E0B098 + +#define mmROT0_MRSB_RL 0x4E0B09C + +#define mmROT0_MRSB_INFLIGHTS 0x4E0B0A0 + +#define mmROT0_MRSB_OCCUPANCY 0x4E0B0A4 + +#define mmROT0_MRSB_INFO 0x4E0B0A8 + +#define mmROT0_MRSB_MON 0x4E0B0AC + +#define mmROT0_MRSB_MON_CONTEXT_ID 0x4E0B0B0 + +#define mmROT0_MSS_STS 0x4E0B0B4 + +#endif /* ASIC_REG_ROT0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h new file mode 100644 index 000000000..e8aebd7f5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_ +#define ASIC_REG_XBAR_EDGE_0_REGS_H_ + +/* + ***************************************** + * XBAR_EDGE_0 + * (Prototype: XBAR) + ***************************************** + */ + +#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000 + +#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004 + +#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008 + +#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C + +#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010 + +#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014 + +#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018 + +#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C + +#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020 + +#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024 + +#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028 + +#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C + +#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030 + +#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034 + +#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038 + +#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C + +#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040 + +#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044 + +#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048 + +#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C + +#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080 + +#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084 + +#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088 + +#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C + +#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090 + +#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094 + +#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098 + +#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C + +#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0 + +#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4 + +#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8 + +#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC + +#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0 + +#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4 + +#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8 + +#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC + +#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0 + +#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4 + +#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8 + +#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC + +#define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0 + +#define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4 + +#define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100 + +#define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104 + +#define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108 + +#define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C + +#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110 + +#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114 + +#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120 + +#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124 + +#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128 + +#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C + +#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130 + +#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134 + +#define mmXBAR_EDGE_0_RL_RD_0 0x4D48140 + +#define mmXBAR_EDGE_0_RL_RD_1 0x4D48144 + +#define mmXBAR_EDGE_0_RL_RD_2 0x4D48148 + +#define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C + +#define mmXBAR_EDGE_0_RL_RD_4 0x4D48150 + +#define mmXBAR_EDGE_0_RL_RD_5 0x4D48154 + +#define mmXBAR_EDGE_0_RL_RD_6 0x4D48158 + +#define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C + +#define mmXBAR_EDGE_0_RL_RD_8 0x4D48160 + +#define mmXBAR_EDGE_0_RL_RD_9 0x4D48164 + +#define mmXBAR_EDGE_0_RL_RD_10 0x4D48168 + +#define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C + +#define mmXBAR_EDGE_0_RL_WR_0 0x4D48180 + +#define mmXBAR_EDGE_0_RL_WR_1 0x4D48184 + +#define mmXBAR_EDGE_0_RL_WR_2 0x4D48188 + +#define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C + +#define mmXBAR_EDGE_0_RL_WR_4 0x4D48190 + +#define mmXBAR_EDGE_0_RL_WR_5 0x4D48194 + +#define mmXBAR_EDGE_0_RL_WR_6 0x4D48198 + +#define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C + +#define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0 + +#define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4 + +#define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8 + +#define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0 + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4 + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8 + +#define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC + +#define mmXBAR_EDGE_0_UPSCALE 0x4D481C0 + +#define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC + +#endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h new file mode 100644 index 000000000..3d39d1a94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_XBAR_MID_0_REGS_H_ +#define ASIC_REG_XBAR_MID_0_REGS_H_ + +/* + ***************************************** + * XBAR_MID_0 + * (Prototype: XBAR) + ***************************************** + */ + +#define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000 + +#define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004 + +#define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008 + +#define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C + +#define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010 + +#define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014 + +#define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018 + +#define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C + +#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020 + +#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024 + +#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028 + +#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C + +#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030 + +#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034 + +#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038 + +#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C + +#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040 + +#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044 + +#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048 + +#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C + +#define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080 + +#define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084 + +#define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088 + +#define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C + +#define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090 + +#define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094 + +#define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098 + +#define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C + +#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0 + +#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4 + +#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8 + +#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC + +#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0 + +#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4 + +#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8 + +#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC + +#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0 + +#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4 + +#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8 + +#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC + +#define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0 + +#define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4 + +#define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100 + +#define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104 + +#define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108 + +#define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C + +#define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110 + +#define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114 + +#define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120 + +#define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124 + +#define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128 + +#define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C + +#define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130 + +#define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134 + +#define mmXBAR_MID_0_RL_RD_0 0x4D40140 + +#define mmXBAR_MID_0_RL_RD_1 0x4D40144 + +#define mmXBAR_MID_0_RL_RD_2 0x4D40148 + +#define mmXBAR_MID_0_RL_RD_3 0x4D4014C + +#define mmXBAR_MID_0_RL_RD_4 0x4D40150 + +#define mmXBAR_MID_0_RL_RD_5 0x4D40154 + +#define mmXBAR_MID_0_RL_RD_6 0x4D40158 + +#define mmXBAR_MID_0_RL_RD_7 0x4D4015C + +#define mmXBAR_MID_0_RL_RD_8 0x4D40160 + +#define mmXBAR_MID_0_RL_RD_9 0x4D40164 + +#define mmXBAR_MID_0_RL_RD_10 0x4D40168 + +#define mmXBAR_MID_0_RL_RD_11 0x4D4016C + +#define mmXBAR_MID_0_RL_WR_0 0x4D40180 + +#define mmXBAR_MID_0_RL_WR_1 0x4D40184 + +#define mmXBAR_MID_0_RL_WR_2 0x4D40188 + +#define mmXBAR_MID_0_RL_WR_3 0x4D4018C + +#define mmXBAR_MID_0_RL_WR_4 0x4D40190 + +#define mmXBAR_MID_0_RL_WR_5 0x4D40194 + +#define mmXBAR_MID_0_RL_WR_6 0x4D40198 + +#define mmXBAR_MID_0_RL_WR_7 0x4D4019C + +#define mmXBAR_MID_0_RL_WR_8 0x4D401A0 + +#define mmXBAR_MID_0_RL_WR_9 0x4D401A4 + +#define mmXBAR_MID_0_RL_WR_10 0x4D401A8 + +#define mmXBAR_MID_0_RL_WR_11 0x4D401AC + +#define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0 + +#define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4 + +#define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8 + +#define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC + +#define mmXBAR_MID_0_UPSCALE 0x4D401C0 + +#define mmXBAR_MID_0_DOWN_CONV 0x4D401C4 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC + +#endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2.h new file mode 100644 index 000000000..5b4f9e108 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_H +#define GAUDI2_H + +#define SRAM_CFG_BAR_ID 0 +#define MSIX_BAR_ID 2 +#define DRAM_BAR_ID 4 + +/* Refers to CFG_REGION_SIZE, BAR0_RSRVD_SIZE and SRAM_SIZE */ +#define CFG_BAR_SIZE 0x10000000ull /* 256MB */ + +#define MSIX_BAR_SIZE 0x4000ull /* 16KB */ + +#define CFG_BASE 0x1000007FF8000000ull +#define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/ +#define CFG_REGION_SIZE 0xC000000ull /* 192MB */ + +#define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */ +#define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */ +#define STM_FLASH_SIZE 0x2000000ull /* 32MB */ + +#define SPI_FLASH_BASE_ADDR 0x1000007FF6000000ull +#define SPI_FLASH_SIZE 0x1000000ull /* 16MB */ + +#define SCRATCHPAD_SRAM_ADDR 0x1000007FF7FE0000ull +#define SCRATCHPAD_SRAM_SIZE 0x10000ull /* 64KB */ + +#define PCIE_FW_SRAM_ADDR 0x1000007FF7FF0000ull +#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ + +#define BAR0_RSRVD_BASE_ADDR 0x1000FFFFFC000000ull +#define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */ + +#define SRAM_BASE_ADDR 0x1000FFFFFD000000ull +#define SRAM_SIZE 0x3000000ull /* 48MB */ + +#define DRAM_PHYS_BASE 0x1001000000000000ull + +/* every hint address is masked accordingly */ +#define DRAM_VA_HINT_MASK 0xFFFFFFFFFFFFull /* 48bit mask */ + +#define HOST_PHYS_BASE_0 0x0000000000000000ull +#define HOST_PHYS_SIZE_0 0x0100000000000000ull /* 64PB (56 bits) */ + +#define HOST_PHYS_BASE_1 0xFF00000000000000ull +#define HOST_PHYS_SIZE_1 0x0100000000000000ull /* 64PB (56 bits) */ + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START 0x1001500000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END 0x10016FFFFFFFFFFFull + +#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START 0xFFF077FFFFFF0000ull +#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_END 0xFFF077FFFFFFFFFFull + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_START 0xFFF0780000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END 0xFFF07FFFFFFFFFFFull + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START 0xFFF0F80000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END 0xFFF0FFFFFFFFFFFFull + +#define GAUDI2_MSIX_ENTRIES 512 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 2 + +#define NUM_ARC_CPUS 69 + +/* Every ARC cpu in the system contains a single DCCM block + * except MME and Scheduler ARCs which contain 2 DCCM blocks + */ +#define ARC_DCCM_BLOCK_SIZE 0x8000 + +#define NUM_OF_DCORES 4 +#define NUM_OF_SFT 4 +#define NUM_OF_PSOC_ARC 2 +#define NUM_OF_SCHEDULER_ARC 6 + +#define NUM_OF_PQ_PER_QMAN 4 +#define NUM_OF_CQ_PER_QMAN 5 +#define NUM_OF_CP_PER_QMAN 5 +#define NUM_OF_EDMA_PER_DCORE 2 +#define NUM_OF_HIF_PER_DCORE 4 +#define NUM_OF_PDMA 2 +#define NUM_OF_TPC_PER_DCORE 6 +#define NUM_DCORE0_TPC 7 +#define NUM_DCORE1_TPC NUM_OF_TPC_PER_DCORE +#define NUM_DCORE2_TPC NUM_OF_TPC_PER_DCORE +#define NUM_DCORE3_TPC NUM_OF_TPC_PER_DCORE +#define NUM_OF_DEC_PER_DCORE 2 +#define NUM_OF_ROT 2 +#define NUM_OF_HMMU_PER_DCORE 4 +#define NUM_OF_MME_PER_DCORE 1 +#define NUM_OF_MME_SBTE_PER_DCORE 5 +#define NUM_OF_MME_WB_PER_DCORE 2 +#define NUM_OF_RTR_PER_DCORE 8 +#define NUM_OF_VDEC_PER_DCORE 2 +#define NUM_OF_IF_RTR_PER_SFT 3 +#define NUM_OF_PCIE_VDEC 2 +#define NUM_OF_ARC_FARMS_ARC 4 +#define NUM_OF_XBAR 4 + +#define TPC_NUM_OF_KERNEL_TENSORS 16 +#define TPC_NUM_OF_QM_TENSORS 16 + +#define MME_NUM_OF_LFSR_SEEDS 256 + +#define NIC_NUMBER_OF_MACROS 12 + +#define NIC_NUMBER_OF_QM_PER_MACRO 2 + +#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) + +#define NIC_MAX_NUMBER_OF_PORTS (NIC_NUMBER_OF_ENGINES * 2) + +#define DEVICE_CACHE_LINE_SIZE 128 + +#endif /* GAUDI2_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h new file mode 100644 index 000000000..34406770a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h @@ -0,0 +1,963 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI2_ASYNC_EVENTS_H_ +#define __GAUDI2_ASYNC_EVENTS_H_ + +enum gaudi2_async_event_id { + GAUDI2_EVENT_PCIE_CORE_SERR = 32, + GAUDI2_EVENT_PCIE_CORE_DERR = 33, + GAUDI2_EVENT_PCIE_IF_SERR = 34, + GAUDI2_EVENT_PCIE_IF_DERR = 35, + GAUDI2_EVENT_PCIE_PHY_SERR = 36, + GAUDI2_EVENT_PCIE_PHY_DERR = 37, + GAUDI2_EVENT_TPC0_ECC_SERR = 38, + GAUDI2_EVENT_TPC1_ECC_SERR = 39, + GAUDI2_EVENT_TPC2_ECC_SERR = 40, + GAUDI2_EVENT_TPC3_ECC_SERR = 41, + GAUDI2_EVENT_TPC4_ECC_SERR = 42, + GAUDI2_EVENT_TPC5_ECC_SERR = 43, + GAUDI2_EVENT_TPC6_ECC_SERR = 44, + GAUDI2_EVENT_TPC7_ECC_SERR = 45, + GAUDI2_EVENT_TPC8_ECC_SERR = 46, + GAUDI2_EVENT_TPC9_ECC_SERR = 47, + GAUDI2_EVENT_TPC10_ECC_SERR = 48, + GAUDI2_EVENT_TPC11_ECC_SERR = 49, + GAUDI2_EVENT_TPC12_ECC_SERR = 50, + GAUDI2_EVENT_TPC13_ECC_SERR = 51, + GAUDI2_EVENT_TPC14_ECC_SERR = 52, + GAUDI2_EVENT_TPC15_ECC_SERR = 53, + GAUDI2_EVENT_TPC16_ECC_SERR = 54, + GAUDI2_EVENT_TPC17_ECC_SERR = 55, + GAUDI2_EVENT_TPC18_ECC_SERR = 56, + GAUDI2_EVENT_TPC19_ECC_SERR = 57, + GAUDI2_EVENT_TPC20_ECC_SERR = 58, + GAUDI2_EVENT_TPC21_ECC_SERR = 59, + GAUDI2_EVENT_TPC22_ECC_SERR = 60, + GAUDI2_EVENT_TPC23_ECC_SERR = 61, + GAUDI2_EVENT_TPC24_ECC_SERR = 62, + GAUDI2_EVENT_TPC0_ECC_DERR = 63, + GAUDI2_EVENT_TPC1_ECC_DERR = 64, + GAUDI2_EVENT_TPC2_ECC_DERR = 65, + GAUDI2_EVENT_TPC3_ECC_DERR = 66, + GAUDI2_EVENT_TPC4_ECC_DERR = 67, + GAUDI2_EVENT_TPC5_ECC_DERR = 68, + GAUDI2_EVENT_TPC6_ECC_DERR = 69, + GAUDI2_EVENT_TPC7_ECC_DERR = 70, + GAUDI2_EVENT_TPC8_ECC_DERR = 71, + GAUDI2_EVENT_TPC9_ECC_DERR = 72, + GAUDI2_EVENT_TPC10_ECC_DERR = 73, + GAUDI2_EVENT_TPC11_ECC_DERR = 74, + GAUDI2_EVENT_TPC12_ECC_DERR = 75, + GAUDI2_EVENT_TPC13_ECC_DERR = 76, + GAUDI2_EVENT_TPC14_ECC_DERR = 77, + GAUDI2_EVENT_TPC15_ECC_DERR = 78, + GAUDI2_EVENT_TPC16_ECC_DERR = 79, + GAUDI2_EVENT_TPC17_ECC_DERR = 80, + GAUDI2_EVENT_TPC18_ECC_DERR = 81, + GAUDI2_EVENT_TPC19_ECC_DERR = 82, + GAUDI2_EVENT_TPC20_ECC_DERR = 83, + GAUDI2_EVENT_TPC21_ECC_DERR = 84, + GAUDI2_EVENT_TPC22_ECC_DERR = 85, + GAUDI2_EVENT_TPC23_ECC_DERR = 86, + GAUDI2_EVENT_TPC24_ECC_DERR = 87, + GAUDI2_EVENT_MME0_SBTE0_ECC_SERR = 88, + GAUDI2_EVENT_MME0_SBTE1_ECC_SERR = 89, + GAUDI2_EVENT_MME0_SBTE2_ECC_SERR = 90, + GAUDI2_EVENT_MME0_SBTE3_ECC_SERR = 91, + GAUDI2_EVENT_MME0_SBTE4_ECC_SERR = 92, + GAUDI2_EVENT_MME0_CTRL_ECC_SERR = 93, + GAUDI2_EVENT_MME0_WAP_ECC_SERR = 94, + GAUDI2_EVENT_MME1_SBTE0_ECC_SERR = 95, + GAUDI2_EVENT_MME1_SBTE1_ECC_SERR = 96, + GAUDI2_EVENT_MME1_SBTE2_ECC_SERR = 97, + GAUDI2_EVENT_MME1_SBTE3_ECC_SERR = 98, + GAUDI2_EVENT_MME1_SBTE4_ECC_SERR = 99, + GAUDI2_EVENT_MME1_CTRL_ECC_SERR = 100, + GAUDI2_EVENT_MME1_WAP_ECC_SERR = 101, + GAUDI2_EVENT_MME2_SBTE0_ECC_SERR = 102, + GAUDI2_EVENT_MME2_SBTE1_ECC_SERR = 103, + GAUDI2_EVENT_MME2_SBTE2_ECC_SERR = 104, + GAUDI2_EVENT_MME2_SBTE3_ECC_SERR = 105, + GAUDI2_EVENT_MME2_SBTE4_ECC_SERR = 106, + GAUDI2_EVENT_MME2_CTRL_ECC_SERR = 107, + GAUDI2_EVENT_MME2_WAP_ECC_SERR = 108, + GAUDI2_EVENT_MME3_SBTE0_ECC_SERR = 109, + GAUDI2_EVENT_MME3_SBTE1_ECC_SERR = 110, + GAUDI2_EVENT_MME3_SBTE2_ECC_SERR = 111, + GAUDI2_EVENT_MME3_SBTE3_ECC_SERR = 112, + GAUDI2_EVENT_MME3_SBTE4_ECC_SERR = 113, + GAUDI2_EVENT_MME3_CTRL_ECC_SERR = 114, + GAUDI2_EVENT_MME3_WAP_ECC_SERR = 115, + GAUDI2_EVENT_MME0_SBTE0_ECC_DERR = 116, + GAUDI2_EVENT_MME0_SBTE1_ECC_DERR = 117, + GAUDI2_EVENT_MME0_SBTE2_ECC_DERR = 118, + GAUDI2_EVENT_MME0_SBTE3_ECC_DERR = 119, + GAUDI2_EVENT_MME0_SBTE4_ECC_DERR = 120, + GAUDI2_EVENT_MME0_CTRL_ECC_DERR = 121, + GAUDI2_EVENT_MME0_WAP_ECC_DERR = 122, + GAUDI2_EVENT_MME1_SBTE0_ECC_DERR = 123, + GAUDI2_EVENT_MME1_SBTE1_ECC_DERR = 124, + GAUDI2_EVENT_MME1_SBTE2_ECC_DERR = 125, + GAUDI2_EVENT_MME1_SBTE3_ECC_DERR = 126, + GAUDI2_EVENT_MME1_SBTE4_ECC_DERR = 127, + GAUDI2_EVENT_MME1_CTRL_ECC_DERR = 128, + GAUDI2_EVENT_MME1_WAP_ECC_DERR = 129, + GAUDI2_EVENT_MME2_SBTE0_ECC_DERR = 130, + GAUDI2_EVENT_MME2_SBTE1_ECC_DERR = 131, + GAUDI2_EVENT_MME2_SBTE2_ECC_DERR = 132, + GAUDI2_EVENT_MME2_SBTE3_ECC_DERR = 133, + GAUDI2_EVENT_MME2_SBTE4_ECC_DERR = 134, + GAUDI2_EVENT_MME2_CTRL_ECC_DERR = 135, + GAUDI2_EVENT_MME2_WAP_ECC_DERR = 136, + GAUDI2_EVENT_MME3_SBTE0_ECC_DERR = 137, + GAUDI2_EVENT_MME3_SBTE1_ECC_DERR = 138, + GAUDI2_EVENT_MME3_SBTE2_ECC_DERR = 139, + GAUDI2_EVENT_MME3_SBTE3_ECC_DERR = 140, + GAUDI2_EVENT_MME3_SBTE4_ECC_DERR = 141, + GAUDI2_EVENT_MME3_CTRL_ECC_DERR = 142, + GAUDI2_EVENT_MME3_WAP_ECC_DERR = 143, + GAUDI2_EVENT_HDMA2_ECC_SERR = 144, + GAUDI2_EVENT_HDMA3_ECC_SERR = 145, + GAUDI2_EVENT_HDMA0_ECC_SERR = 146, + GAUDI2_EVENT_HDMA1_ECC_SERR = 147, + GAUDI2_EVENT_HDMA6_ECC_SERR = 148, + GAUDI2_EVENT_HDMA7_ECC_SERR = 149, + GAUDI2_EVENT_HDMA4_ECC_SERR = 150, + GAUDI2_EVENT_HDMA5_ECC_SERR = 151, + GAUDI2_EVENT_HDMA2_ECC_DERR = 152, + GAUDI2_EVENT_HDMA3_ECC_DERR = 153, + GAUDI2_EVENT_HDMA0_ECC_DERR = 154, + GAUDI2_EVENT_HDMA1_ECC_DERR = 155, + GAUDI2_EVENT_HDMA6_ECC_DERR = 156, + GAUDI2_EVENT_HDMA7_ECC_DERR = 157, + GAUDI2_EVENT_HDMA4_ECC_DERR = 158, + GAUDI2_EVENT_HDMA5_ECC_DERR = 159, + GAUDI2_EVENT_KDMA0_ECC_SERR = 160, + GAUDI2_EVENT_PDMA0_ECC_SERR = 161, + GAUDI2_EVENT_PDMA1_ECC_SERR = 162, + GAUDI2_EVENT_KDMA0_ECC_DERR = 163, + GAUDI2_EVENT_PDMA0_ECC_DERR = 164, + GAUDI2_EVENT_PDMA1_ECC_DERR = 165, + GAUDI2_EVENT_CPU_IF_ECC_SERR = 166, + GAUDI2_EVENT_CPU_IF_ECC_DERR = 167, + GAUDI2_EVENT_PSOC_MEM_SERR = 168, + GAUDI2_EVENT_PSOC_MEM_DERR = 169, + GAUDI2_EVENT_SRAM0_ECC_SERR = 170, + GAUDI2_EVENT_SRAM1_ECC_SERR = 171, + GAUDI2_EVENT_SRAM2_ECC_SERR = 172, + GAUDI2_EVENT_SRAM3_ECC_SERR = 173, + GAUDI2_EVENT_SRAM4_ECC_SERR = 174, + GAUDI2_EVENT_SRAM5_ECC_SERR = 175, + GAUDI2_EVENT_SRAM6_ECC_SERR = 176, + GAUDI2_EVENT_SRAM7_ECC_SERR = 177, + GAUDI2_EVENT_SRAM8_ECC_SERR = 178, + GAUDI2_EVENT_SRAM9_ECC_SERR = 179, + GAUDI2_EVENT_SRAM10_ECC_SERR = 180, + GAUDI2_EVENT_SRAM11_ECC_SERR = 181, + GAUDI2_EVENT_SRAM12_ECC_SERR = 182, + GAUDI2_EVENT_SRAM13_ECC_SERR = 183, + GAUDI2_EVENT_SRAM14_ECC_SERR = 184, + GAUDI2_EVENT_SRAM15_ECC_SERR = 185, + GAUDI2_EVENT_SRAM16_ECC_SERR = 186, + GAUDI2_EVENT_SRAM17_ECC_SERR = 187, + GAUDI2_EVENT_SRAM18_ECC_SERR = 188, + GAUDI2_EVENT_SRAM19_ECC_SERR = 189, + GAUDI2_EVENT_SRAM20_ECC_SERR = 190, + GAUDI2_EVENT_SRAM21_ECC_SERR = 191, + GAUDI2_EVENT_SRAM22_ECC_SERR = 192, + GAUDI2_EVENT_SRAM23_ECC_SERR = 193, + GAUDI2_EVENT_SRAM24_ECC_SERR = 194, + GAUDI2_EVENT_SRAM25_ECC_SERR = 195, + GAUDI2_EVENT_SRAM26_ECC_SERR = 196, + GAUDI2_EVENT_SRAM27_ECC_SERR = 197, + GAUDI2_EVENT_SRAM28_ECC_SERR = 198, + GAUDI2_EVENT_SRAM29_ECC_SERR = 199, + GAUDI2_EVENT_SRAM30_ECC_SERR = 200, + GAUDI2_EVENT_SRAM31_ECC_SERR = 201, + GAUDI2_EVENT_SRAM0_ECC_DERR = 202, + GAUDI2_EVENT_SRAM1_ECC_DERR = 203, + GAUDI2_EVENT_SRAM2_ECC_DERR = 204, + GAUDI2_EVENT_SRAM3_ECC_DERR = 205, + GAUDI2_EVENT_SRAM4_ECC_DERR = 206, + GAUDI2_EVENT_SRAM5_ECC_DERR = 207, + GAUDI2_EVENT_SRAM6_ECC_DERR = 208, + GAUDI2_EVENT_SRAM7_ECC_DERR = 209, + GAUDI2_EVENT_SRAM8_ECC_DERR = 210, + GAUDI2_EVENT_SRAM9_ECC_DERR = 211, + GAUDI2_EVENT_SRAM10_ECC_DERR = 212, + GAUDI2_EVENT_SRAM11_ECC_DERR = 213, + GAUDI2_EVENT_SRAM12_ECC_DERR = 214, + GAUDI2_EVENT_SRAM13_ECC_DERR = 215, + GAUDI2_EVENT_SRAM14_ECC_DERR = 216, + GAUDI2_EVENT_SRAM15_ECC_DERR = 217, + GAUDI2_EVENT_SRAM16_ECC_DERR = 218, + GAUDI2_EVENT_SRAM17_ECC_DERR = 219, + GAUDI2_EVENT_SRAM18_ECC_DERR = 220, + GAUDI2_EVENT_SRAM19_ECC_DERR = 221, + GAUDI2_EVENT_SRAM20_ECC_DERR = 222, + GAUDI2_EVENT_SRAM21_ECC_DERR = 223, + GAUDI2_EVENT_SRAM22_ECC_DERR = 224, + GAUDI2_EVENT_SRAM23_ECC_DERR = 225, + GAUDI2_EVENT_SRAM24_ECC_DERR = 226, + GAUDI2_EVENT_SRAM25_ECC_DERR = 227, + GAUDI2_EVENT_SRAM26_ECC_DERR = 228, + GAUDI2_EVENT_SRAM27_ECC_DERR = 229, + GAUDI2_EVENT_SRAM28_ECC_DERR = 230, + GAUDI2_EVENT_SRAM29_ECC_DERR = 231, + GAUDI2_EVENT_SRAM30_ECC_DERR = 232, + GAUDI2_EVENT_SRAM31_ECC_DERR = 233, + GAUDI2_EVENT_CPU_GIC500 = 234, + GAUDI2_EVENT_HBM_0_MC0_ECC_SERR = 235, + GAUDI2_EVENT_HBM_1_MC0_ECC_SERR = 236, + GAUDI2_EVENT_HBM_2_MC0_ECC_SERR = 237, + GAUDI2_EVENT_HBM_3_MC0_ECC_SERR = 238, + GAUDI2_EVENT_HBM_4_MC0_ECC_SERR = 239, + GAUDI2_EVENT_HBM_5_MC0_ECC_SERR = 240, + GAUDI2_EVENT_HBM_0_MC1_ECC_SERR = 241, + GAUDI2_EVENT_HBM_1_MC1_ECC_SERR = 242, + GAUDI2_EVENT_HBM_2_MC1_ECC_SERR = 243, + GAUDI2_EVENT_HBM_3_MC1_ECC_SERR = 244, + GAUDI2_EVENT_HBM_4_MC1_ECC_SERR = 245, + GAUDI2_EVENT_HBM_5_MC1_ECC_SERR = 246, + GAUDI2_EVENT_HBM_0_MC0_ECC_DERR = 247, + GAUDI2_EVENT_HBM_1_MC0_ECC_DERR = 248, + GAUDI2_EVENT_HBM_2_MC0_ECC_DERR = 249, + GAUDI2_EVENT_HBM_3_MC0_ECC_DERR = 250, + GAUDI2_EVENT_HBM_4_MC0_ECC_DERR = 251, + GAUDI2_EVENT_HBM_5_MC0_ECC_DERR = 252, + GAUDI2_EVENT_HBM_0_MC1_ECC_DERR = 253, + GAUDI2_EVENT_HBM_1_MC1_ECC_DERR = 254, + GAUDI2_EVENT_HBM_2_MC1_ECC_DERR = 255, + GAUDI2_EVENT_HBM_3_MC1_ECC_DERR = 256, + GAUDI2_EVENT_HBM_4_MC1_ECC_DERR = 257, + GAUDI2_EVENT_HBM_5_MC1_ECC_DERR = 258, + GAUDI2_EVENT_HMMU_0_ECC_SERR = 259, + GAUDI2_EVENT_HMMU_1_ECC_SERR = 260, + GAUDI2_EVENT_HMMU_2_ECC_SERR = 261, + GAUDI2_EVENT_HMMU_3_ECC_SERR = 262, + GAUDI2_EVENT_HMMU_8_ECC_SERR = 263, + GAUDI2_EVENT_HMMU_9_ECC_SERR = 264, + GAUDI2_EVENT_HMMU_10_ECC_SERR = 265, + GAUDI2_EVENT_HMMU_11_ECC_SERR = 266, + GAUDI2_EVENT_HMMU_7_ECC_SERR = 267, + GAUDI2_EVENT_HMMU_6_ECC_SERR = 268, + GAUDI2_EVENT_HMMU_5_ECC_SERR = 269, + GAUDI2_EVENT_HMMU_4_ECC_SERR = 270, + GAUDI2_EVENT_HMMU_15_ECC_SERR = 271, + GAUDI2_EVENT_HMMU_14_ECC_SERR = 272, + GAUDI2_EVENT_HMMU_13_ECC_SERR = 273, + GAUDI2_EVENT_HMMU_12_ECC_SERR = 274, + GAUDI2_EVENT_HMMU_0_ECC_DERR = 275, + GAUDI2_EVENT_HMMU_1_ECC_DERR = 276, + GAUDI2_EVENT_HMMU_2_ECC_DERR = 277, + GAUDI2_EVENT_HMMU_3_ECC_DERR = 278, + GAUDI2_EVENT_HMMU_8_ECC_DERR = 279, + GAUDI2_EVENT_HMMU_9_ECC_DERR = 280, + GAUDI2_EVENT_HMMU_10_ECC_DERR = 281, + GAUDI2_EVENT_HMMU_11_ECC_DERR = 282, + GAUDI2_EVENT_HMMU_7_ECC_DERR = 283, + GAUDI2_EVENT_HMMU_6_ECC_DERR = 284, + GAUDI2_EVENT_HMMU_5_ECC_DERR = 285, + GAUDI2_EVENT_HMMU_4_ECC_DERR = 286, + GAUDI2_EVENT_HMMU_15_ECC_DERR = 287, + GAUDI2_EVENT_HMMU_14_ECC_DERR = 288, + GAUDI2_EVENT_HMMU_13_ECC_DERR = 289, + GAUDI2_EVENT_HMMU_12_ECC_DERR = 290, + GAUDI2_EVENT_PMMU_ECC_SERR_0 = 291, + GAUDI2_EVENT_PMMU_ECC_DERR_0 = 292, + GAUDI2_EVENT_DEC0_VCD_ECC_SERR = 295, + GAUDI2_EVENT_DEC1_VCD_ECC_SERR = 296, + GAUDI2_EVENT_DEC2_VCD_ECC_SERR = 297, + GAUDI2_EVENT_DEC3_VCD_ECC_SERR = 298, + GAUDI2_EVENT_DEC4_VCD_ECC_SERR = 299, + GAUDI2_EVENT_DEC5_VCD_ECC_SERR = 300, + GAUDI2_EVENT_DEC6_VCD_ECC_SERR = 301, + GAUDI2_EVENT_DEC7_VCD_ECC_SERR = 302, + GAUDI2_EVENT_DEC8_VCD_ECC_SERR = 303, + GAUDI2_EVENT_DEC9_VCD_ECC_SERR = 304, + GAUDI2_EVENT_DEC0_L2C_ECC_SERR = 305, + GAUDI2_EVENT_DEC1_L2C_ECC_SERR = 306, + GAUDI2_EVENT_DEC2_L2C_ECC_SERR = 307, + GAUDI2_EVENT_DEC3_L2C_ECC_SERR = 308, + GAUDI2_EVENT_DEC4_L2C_ECC_SERR = 309, + GAUDI2_EVENT_DEC5_L2C_ECC_SERR = 310, + GAUDI2_EVENT_DEC6_L2C_ECC_SERR = 311, + GAUDI2_EVENT_DEC7_L2C_ECC_SERR = 312, + GAUDI2_EVENT_DEC8_L2C_ECC_SERR = 313, + GAUDI2_EVENT_DEC9_L2C_ECC_SERR = 314, + GAUDI2_EVENT_DEC0_VCD_ECC_DERR = 315, + GAUDI2_EVENT_DEC1_VCD_ECC_DERR = 316, + GAUDI2_EVENT_DEC2_VCD_ECC_DERR = 317, + GAUDI2_EVENT_DEC3_VCD_ECC_DERR = 318, + GAUDI2_EVENT_DEC4_VCD_ECC_DERR = 319, + GAUDI2_EVENT_DEC5_VCD_ECC_DERR = 320, + GAUDI2_EVENT_DEC6_VCD_ECC_DERR = 321, + GAUDI2_EVENT_DEC7_VCD_ECC_DERR = 322, + GAUDI2_EVENT_DEC8_VCD_ECC_DERR = 323, + GAUDI2_EVENT_DEC9_VCD_ECC_DERR = 324, + GAUDI2_EVENT_DEC0_L2C_ECC_DERR = 325, + GAUDI2_EVENT_DEC1_L2C_ECC_DERR = 326, + GAUDI2_EVENT_DEC2_L2C_ECC_DERR = 327, + GAUDI2_EVENT_DEC3_L2C_ECC_DERR = 328, + GAUDI2_EVENT_DEC4_L2C_ECC_DERR = 329, + GAUDI2_EVENT_DEC5_L2C_ECC_DERR = 330, + GAUDI2_EVENT_DEC6_L2C_ECC_DERR = 331, + GAUDI2_EVENT_DEC7_L2C_ECC_DERR = 332, + GAUDI2_EVENT_DEC8_L2C_ECC_DERR = 333, + GAUDI2_EVENT_DEC9_L2C_ECC_DERR = 334, + GAUDI2_EVENT_HIF0_ECC_SERR = 337, + GAUDI2_EVENT_HIF1_ECC_SERR = 338, + GAUDI2_EVENT_HIF2_ECC_SERR = 339, + GAUDI2_EVENT_HIF3_ECC_SERR = 340, + GAUDI2_EVENT_HIF8_ECC_SERR = 341, + GAUDI2_EVENT_HIF9_ECC_SERR = 342, + GAUDI2_EVENT_HIF10_ECC_SERR = 343, + GAUDI2_EVENT_HIF11_ECC_SERR = 344, + GAUDI2_EVENT_HIF7_ECC_SERR = 345, + GAUDI2_EVENT_HIF6_ECC_SERR = 346, + GAUDI2_EVENT_HIF5_ECC_SERR = 347, + GAUDI2_EVENT_HIF4_ECC_SERR = 348, + GAUDI2_EVENT_HIF15_ECC_SERR = 349, + GAUDI2_EVENT_HIF14_ECC_SERR = 350, + GAUDI2_EVENT_HIF13_ECC_SERR = 351, + GAUDI2_EVENT_HIF12_ECC_SERR = 352, + GAUDI2_EVENT_HIF0_ECC_DERR = 353, + GAUDI2_EVENT_HIF1_ECC_DERR = 354, + GAUDI2_EVENT_HIF2_ECC_DERR = 355, + GAUDI2_EVENT_HIF3_ECC_DERR = 356, + GAUDI2_EVENT_HIF8_ECC_DERR = 357, + GAUDI2_EVENT_HIF9_ECC_DERR = 358, + GAUDI2_EVENT_HIF10_ECC_DERR = 359, + GAUDI2_EVENT_HIF11_ECC_DERR = 360, + GAUDI2_EVENT_HIF7_ECC_DERR = 361, + GAUDI2_EVENT_HIF6_ECC_DERR = 362, + GAUDI2_EVENT_HIF5_ECC_DERR = 363, + GAUDI2_EVENT_HIF4_ECC_DERR = 364, + GAUDI2_EVENT_HIF15_ECC_DERR = 365, + GAUDI2_EVENT_HIF14_ECC_DERR = 366, + GAUDI2_EVENT_HIF13_ECC_DERR = 367, + GAUDI2_EVENT_HIF12_ECC_DERR = 368, + GAUDI2_EVENT_NIC0_ECC_SERR = 369, + GAUDI2_EVENT_NIC1_ECC_SERR = 370, + GAUDI2_EVENT_NIC2_ECC_SERR = 371, + GAUDI2_EVENT_NIC3_ECC_SERR = 372, + GAUDI2_EVENT_NIC4_ECC_SERR = 373, + GAUDI2_EVENT_NIC5_ECC_SERR = 374, + GAUDI2_EVENT_NIC6_ECC_SERR = 375, + GAUDI2_EVENT_NIC7_ECC_SERR = 376, + GAUDI2_EVENT_NIC8_ECC_SERR = 377, + GAUDI2_EVENT_NIC9_ECC_SERR = 378, + GAUDI2_EVENT_NIC10_ECC_SERR = 379, + GAUDI2_EVENT_NIC11_ECC_SERR = 380, + GAUDI2_EVENT_NIC0_ECC_DERR = 381, + GAUDI2_EVENT_NIC1_ECC_DERR = 382, + GAUDI2_EVENT_NIC2_ECC_DERR = 383, + GAUDI2_EVENT_NIC3_ECC_DERR = 384, + GAUDI2_EVENT_NIC4_ECC_DERR = 385, + GAUDI2_EVENT_NIC5_ECC_DERR = 386, + GAUDI2_EVENT_NIC6_ECC_DERR = 387, + GAUDI2_EVENT_NIC7_ECC_DERR = 388, + GAUDI2_EVENT_NIC8_ECC_DERR = 389, + GAUDI2_EVENT_NIC9_ECC_DERR = 390, + GAUDI2_EVENT_NIC10_ECC_DERR = 391, + GAUDI2_EVENT_NIC11_ECC_DERR = 392, + GAUDI2_EVENT_SM0_ECC_DERR = 393, + GAUDI2_EVENT_SM1_ECC_DERR = 394, + GAUDI2_EVENT_SM2_ECC_DERR = 395, + GAUDI2_EVENT_SM3_ECC_DERR = 396, + GAUDI2_EVENT_SM0_ECC_SERR = 397, + GAUDI2_EVENT_SM1_ECC_SERR = 398, + GAUDI2_EVENT_SM2_ECC_SERR = 399, + GAUDI2_EVENT_SM3_ECC_SERR = 400, + GAUDI2_EVENT_XBAR0_ECC_SERR = 401, + GAUDI2_EVENT_XBAR1_ECC_SERR = 402, + GAUDI2_EVENT_XBAR2_ECC_SERR = 403, + GAUDI2_EVENT_XBAR3_ECC_SERR = 404, + GAUDI2_EVENT_XBAR0_ECC_DERR = 405, + GAUDI2_EVENT_XBAR1_ECC_DERR = 406, + GAUDI2_EVENT_XBAR2_ECC_DERR = 407, + GAUDI2_EVENT_XBAR3_ECC_DERR = 408, + GAUDI2_EVENT_ARC0_ECC_SERR = 409, + GAUDI2_EVENT_ARC0_ECC_DERR = 410, + GAUDI2_EVENT_PCIE_BME_CLEARD = 411, + GAUDI2_EVENT_PCIE_ADDR_DEC_ERR = 412, + GAUDI2_EVENT_TPC0_AXI_ERR_RSP = 413, + GAUDI2_EVENT_TPC1_AXI_ERR_RSP = 414, + GAUDI2_EVENT_TPC2_AXI_ERR_RSP = 415, + GAUDI2_EVENT_TPC3_AXI_ERR_RSP = 416, + GAUDI2_EVENT_TPC4_AXI_ERR_RSP = 417, + GAUDI2_EVENT_TPC5_AXI_ERR_RSP = 418, + GAUDI2_EVENT_TPC6_AXI_ERR_RSP = 419, + GAUDI2_EVENT_TPC7_AXI_ERR_RSP = 420, + GAUDI2_EVENT_TPC8_AXI_ERR_RSP = 421, + GAUDI2_EVENT_TPC9_AXI_ERR_RSP = 422, + GAUDI2_EVENT_TPC10_AXI_ERR_RSP = 423, + GAUDI2_EVENT_TPC11_AXI_ERR_RSP = 424, + GAUDI2_EVENT_TPC12_AXI_ERR_RSP = 425, + GAUDI2_EVENT_TPC13_AXI_ERR_RSP = 426, + GAUDI2_EVENT_TPC14_AXI_ERR_RSP = 427, + GAUDI2_EVENT_TPC15_AXI_ERR_RSP = 428, + GAUDI2_EVENT_TPC16_AXI_ERR_RSP = 429, + GAUDI2_EVENT_TPC17_AXI_ERR_RSP = 430, + GAUDI2_EVENT_TPC18_AXI_ERR_RSP = 431, + GAUDI2_EVENT_TPC19_AXI_ERR_RSP = 432, + GAUDI2_EVENT_TPC20_AXI_ERR_RSP = 433, + GAUDI2_EVENT_TPC21_AXI_ERR_RSP = 434, + GAUDI2_EVENT_TPC22_AXI_ERR_RSP = 435, + GAUDI2_EVENT_TPC23_AXI_ERR_RSP = 436, + GAUDI2_EVENT_TPC24_AXI_ERR_RSP = 437, + GAUDI2_EVENT_CPU_AXI_ECC = 438, + GAUDI2_EVENT_CPU_L2_RAM_ECC = 439, + GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP = 440, + GAUDI2_EVENT_MME0_SBTE1_AXI_ERR_RSP = 441, + GAUDI2_EVENT_MME0_SBTE2_AXI_ERR_RSP = 442, + GAUDI2_EVENT_MME0_SBTE3_AXI_ERR_RSP = 443, + GAUDI2_EVENT_MME0_SBTE4_AXI_ERR_RSP = 444, + GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE = 445, + GAUDI2_EVENT_MME0_QMAN_SW_ERROR = 446, + GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP = 447, + GAUDI2_EVENT_MME1_SBTE1_AXI_ERR_RSP = 448, + GAUDI2_EVENT_MME1_SBTE2_AXI_ERR_RSP = 449, + GAUDI2_EVENT_MME1_SBTE3_AXI_ERR_RSP = 450, + GAUDI2_EVENT_MME1_SBTE4_AXI_ERR_RSP = 451, + GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE = 452, + GAUDI2_EVENT_MME1_QMAN_SW_ERROR = 453, + GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP = 454, + GAUDI2_EVENT_MME2_SBTE1_AXI_ERR_RSP = 455, + GAUDI2_EVENT_MME2_SBTE2_AXI_ERR_RSP = 456, + GAUDI2_EVENT_MME2_SBTE3_AXI_ERR_RSP = 457, + GAUDI2_EVENT_MME2_SBTE4_AXI_ERR_RSP = 458, + GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE = 459, + GAUDI2_EVENT_MME2_QMAN_SW_ERROR = 460, + GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP = 461, + GAUDI2_EVENT_MME3_SBTE1_AXI_ERR_RSP = 462, + GAUDI2_EVENT_MME3_SBTE2_AXI_ERR_RSP = 463, + GAUDI2_EVENT_MME3_SBTE3_AXI_ERR_RSP = 464, + GAUDI2_EVENT_MME3_SBTE4_AXI_ERR_RSP = 465, + GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE = 466, + GAUDI2_EVENT_MME3_QMAN_SW_ERROR = 467, + GAUDI2_EVENT_PSOC_MME_PLL_LOCK_ERR = 468, + GAUDI2_EVENT_PSOC_CPU_PLL_LOCK_ERR = 469, + GAUDI2_EVENT_DCORE3_TPC_PLL_LOCK_ERR = 470, + GAUDI2_EVENT_DCORE3_NIC_PLL_LOCK_ERR = 471, + GAUDI2_EVENT_DCORE3_XBAR_MMU_PLL_LOCK_ERR = 472, + GAUDI2_EVENT_DCORE3_XBAR_DMA_PLL_LOCK_ERR = 473, + GAUDI2_EVENT_DCORE3_XBAR_IF_PLL_LOCK_ERR = 474, + GAUDI2_EVENT_DCORE3_XBAR_BANK_PLL_LOCK_ERR = 475, + GAUDI2_EVENT_DCORE1_XBAR_MMU_PLL_LOCK_ERR = 476, + GAUDI2_EVENT_DCORE1_XBAR_DMA_PLL_LOCK_ERR = 477, + GAUDI2_EVENT_DCORE1_XBAR_IF_PLL_LOCK_ERR = 478, + GAUDI2_EVENT_DCORE1_XBAR_MESH_PLL_LOCK_ERR = 479, + GAUDI2_EVENT_DCORE1_TPC_PLL_LOCK_ERR = 480, + GAUDI2_EVENT_DCORE1_NIC_PLL_LOCK_ERR = 481, + GAUDI2_EVENT_PMMU_MME_PLL_LOCK_ERR = 482, + GAUDI2_EVENT_DCORE0_TPC_PLL_LOCK_ERR = 483, + GAUDI2_EVENT_DCORE0_PCI_PLL_LOCK_ERR = 484, + GAUDI2_EVENT_DCORE0_XBAR_MMU_PLL_LOCK_ERR = 485, + GAUDI2_EVENT_DCORE0_XBAR_DMA_PLL_LOCK_ERR = 486, + GAUDI2_EVENT_DCORE0_XBAR_IF_PLL_LOCK_ERR = 487, + GAUDI2_EVENT_DCORE0_XBAR_MESH_PLL_LOCK_ERR = 488, + GAUDI2_EVENT_DCORE2_XBAR_MMU_PLL_LOCK_ERR = 489, + GAUDI2_EVENT_DCORE2_XBAR_DMA_PLL_LOCK_ERR = 490, + GAUDI2_EVENT_DCORE2_XBAR_IF_PLL_LOCK_ERR = 491, + GAUDI2_EVENT_DCORE2_XBAR_BANK_PLL_LOCK_ERR = 492, + GAUDI2_EVENT_DCORE2_TPC_PLL_LOCK_ERR = 493, + GAUDI2_EVENT_PSOC_VID_PLL_LOCK_ERR = 494, + GAUDI2_EVENT_PMMU_VID_PLL_LOCK_ERR = 495, + GAUDI2_EVENT_DCORE3_HBM_PLL_LOCK_ERR = 496, + GAUDI2_EVENT_DCORE1_XBAR_HBM_PLL_LOCK_ERR = 497, + GAUDI2_EVENT_DCORE1_HBM_PLL_LOCK_ERR = 498, + GAUDI2_EVENT_DCORE0_HBM_PLL_LOCK_ERR = 499, + GAUDI2_EVENT_DCORE2_XBAR_HBM_PLL_LOCK_ERR = 500, + GAUDI2_EVENT_DCORE2_HBM_PLL_LOCK_ERR = 501, + GAUDI2_EVENT_CPU_AXI_ERR_RSP = 502, + GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP = 503, + GAUDI2_EVENT_HMMU_1_AXI_ERR_RSP = 504, + GAUDI2_EVENT_HMMU_2_AXI_ERR_RSP = 505, + GAUDI2_EVENT_HMMU_3_AXI_ERR_RSP = 506, + GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP = 507, + GAUDI2_EVENT_HMMU_9_AXI_ERR_RSP = 508, + GAUDI2_EVENT_HMMU_10_AXI_ERR_RSP = 509, + GAUDI2_EVENT_HMMU_11_AXI_ERR_RSP = 510, + GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP = 511, + GAUDI2_EVENT_HMMU_6_AXI_ERR_RSP = 512, + GAUDI2_EVENT_HMMU_5_AXI_ERR_RSP = 513, + GAUDI2_EVENT_HMMU_4_AXI_ERR_RSP = 514, + GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP = 515, + GAUDI2_EVENT_HMMU_14_AXI_ERR_RSP = 516, + GAUDI2_EVENT_HMMU_13_AXI_ERR_RSP = 517, + GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP = 518, + GAUDI2_EVENT_PMMU_FATAL_0 = 519, + GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0 = 520, + GAUDI2_EVENT_VM0_ALARM_A = 521, + GAUDI2_EVENT_VM0_ALARM_B = 522, + GAUDI2_EVENT_VM1_ALARM_A = 523, + GAUDI2_EVENT_VM1_ALARM_B = 524, + GAUDI2_EVENT_VM2_ALARM_A = 525, + GAUDI2_EVENT_VM2_ALARM_B = 526, + GAUDI2_EVENT_VM3_ALARM_A = 527, + GAUDI2_EVENT_VM3_ALARM_B = 528, + GAUDI2_EVENT_PSOC_AXI_ERR_RSP = 529, + GAUDI2_EVENT_PSOC_PRSTN_FALL = 530, + GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP = 539, + GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP = 540, + GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP = 541, + GAUDI2_EVENT_HBM_CATTRIP_0 = 542, + GAUDI2_EVENT_HBM_CATTRIP_1 = 543, + GAUDI2_EVENT_HBM_CATTRIP_2 = 544, + GAUDI2_EVENT_HBM_CATTRIP_3 = 545, + GAUDI2_EVENT_HBM_CATTRIP_4 = 546, + GAUDI2_EVENT_HBM_CATTRIP_5 = 547, + GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE = 548, + GAUDI2_EVENT_HBM0_MC0_SEI_NON_SEVERE = 549, + GAUDI2_EVENT_HBM0_MC1_SEI_SEVERE = 550, + GAUDI2_EVENT_HBM0_MC1_SEI_NON_SEVERE = 551, + GAUDI2_EVENT_HBM1_MC0_SEI_SEVERE = 552, + GAUDI2_EVENT_HBM1_MC0_SEI_NON_SEVERE = 553, + GAUDI2_EVENT_HBM1_MC1_SEI_SEVERE = 554, + GAUDI2_EVENT_HBM1_MC1_SEI_NON_SEVERE = 555, + GAUDI2_EVENT_HBM2_MC0_SEI_SEVERE = 556, + GAUDI2_EVENT_HBM2_MC0_SEI_NON_SEVERE = 557, + GAUDI2_EVENT_HBM2_MC1_SEI_SEVERE = 558, + GAUDI2_EVENT_HBM2_MC1_SEI_NON_SEVERE = 559, + GAUDI2_EVENT_HBM3_MC0_SEI_SEVERE = 560, + GAUDI2_EVENT_HBM3_MC0_SEI_NON_SEVERE = 561, + GAUDI2_EVENT_HBM3_MC1_SEI_SEVERE = 562, + GAUDI2_EVENT_HBM3_MC1_SEI_NON_SEVERE = 563, + GAUDI2_EVENT_HBM4_MC0_SEI_SEVERE = 564, + GAUDI2_EVENT_HBM4_MC0_SEI_NON_SEVERE = 565, + GAUDI2_EVENT_HBM4_MC1_SEI_SEVERE = 566, + GAUDI2_EVENT_HBM4_MC1_SEI_NON_SEVERE = 567, + GAUDI2_EVENT_HBM5_MC0_SEI_SEVERE = 568, + GAUDI2_EVENT_HBM5_MC0_SEI_NON_SEVERE = 569, + GAUDI2_EVENT_HBM5_MC1_SEI_SEVERE = 570, + GAUDI2_EVENT_HBM5_MC1_SEI_NON_SEVERE = 571, + GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE = 572, + GAUDI2_EVENT_DEC1_AXI_ERR_RSPONSE = 573, + GAUDI2_EVENT_DEC2_AXI_ERR_RSPONSE = 574, + GAUDI2_EVENT_DEC3_AXI_ERR_RSPONSE = 575, + GAUDI2_EVENT_DEC4_AXI_ERR_RSPONSE = 576, + GAUDI2_EVENT_DEC5_AXI_ERR_RSPONSE = 577, + GAUDI2_EVENT_DEC6_AXI_ERR_RSPONSE = 578, + GAUDI2_EVENT_DEC7_AXI_ERR_RSPONSE = 579, + GAUDI2_EVENT_DEC8_AXI_ERR_RSPONSE = 580, + GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE = 581, + GAUDI2_EVENT_HIF0_FATAL = 584, + GAUDI2_EVENT_HIF1_FATAL = 585, + GAUDI2_EVENT_HIF2_FATAL = 586, + GAUDI2_EVENT_HIF3_FATAL = 587, + GAUDI2_EVENT_HIF8_FATAL = 588, + GAUDI2_EVENT_HIF9_FATAL = 589, + GAUDI2_EVENT_HIF10_FATAL = 590, + GAUDI2_EVENT_HIF11_FATAL = 591, + GAUDI2_EVENT_HIF7_FATAL = 592, + GAUDI2_EVENT_HIF6_FATAL = 593, + GAUDI2_EVENT_HIF5_FATAL = 594, + GAUDI2_EVENT_HIF4_FATAL = 595, + GAUDI2_EVENT_HIF15_FATAL = 596, + GAUDI2_EVENT_HIF14_FATAL = 597, + GAUDI2_EVENT_HIF13_FATAL = 598, + GAUDI2_EVENT_HIF12_FATAL = 599, + GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE = 600, + GAUDI2_EVENT_NIC1_AXI_ERROR_RESPONSE = 601, + GAUDI2_EVENT_NIC2_AXI_ERROR_RESPONSE = 602, + GAUDI2_EVENT_NIC3_AXI_ERROR_RESPONSE = 603, + GAUDI2_EVENT_NIC4_AXI_ERROR_RESPONSE = 604, + GAUDI2_EVENT_NIC5_AXI_ERROR_RESPONSE = 605, + GAUDI2_EVENT_NIC6_AXI_ERROR_RESPONSE = 606, + GAUDI2_EVENT_NIC7_AXI_ERROR_RESPONSE = 607, + GAUDI2_EVENT_NIC8_AXI_ERROR_RESPONSE = 608, + GAUDI2_EVENT_NIC9_AXI_ERROR_RESPONSE = 609, + GAUDI2_EVENT_NIC10_AXI_ERROR_RESPONSE = 610, + GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE = 611, + GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE = 612, + GAUDI2_EVENT_SM1_AXI_ERROR_RESPONSE = 613, + GAUDI2_EVENT_SM2_AXI_ERROR_RESPONSE = 614, + GAUDI2_EVENT_SM3_AXI_ERROR_RESPONSE = 615, + GAUDI2_EVENT_ARC_AXI_ERROR_RESPONSE_0 = 616, + GAUDI2_EVENT_PCIE_PME_MSG_RECEIVED = 618, + GAUDI2_EVENT_PCIE_FLR_REQUESTED = 619, + GAUDI2_EVENT_PCIE_HOT_RESET_REQ = 620, + GAUDI2_EVENT_PCIE_PERST = 621, + GAUDI2_EVENT_PCIE_APB_TIMEOUT = 622, + GAUDI2_EVENT_PCIE_BM_D_P_WR = 623, + GAUDI2_EVENT_PCIE_BM_D_RD = 624, + GAUDI2_EVENT_PCIE_BM_U_P_WR = 625, + GAUDI2_EVENT_PCIE_BM_U_RD = 626, + GAUDI2_EVENT_PCIE_FATAL_ERR = 627, + GAUDI2_EVENT_PCIE_PERST_FAL = 628, + GAUDI2_EVENT_PCIE_VDM_READY = 629, + GAUDI2_EVENT_PCIE_VDM_ERROR = 630, + GAUDI2_EVENT_PCIE_P2P_MSIX = 631, + GAUDI2_EVENT_PCIE_DRAIN_COMPLETE = 632, + GAUDI2_EVENT_TPC0_BMON_SPMU = 633, + GAUDI2_EVENT_TPC0_KERNEL_ERR = 634, + GAUDI2_EVENT_TPC1_BMON_SPMU = 635, + GAUDI2_EVENT_TPC1_KERNEL_ERR = 636, + GAUDI2_EVENT_TPC2_BMON_SPMU = 637, + GAUDI2_EVENT_TPC2_KERNEL_ERR = 638, + GAUDI2_EVENT_TPC3_BMON_SPMU = 639, + GAUDI2_EVENT_TPC3_KERNEL_ERR = 640, + GAUDI2_EVENT_TPC4_BMON_SPMU = 641, + GAUDI2_EVENT_TPC4_KERNEL_ERR = 642, + GAUDI2_EVENT_TPC5_BMON_SPMU = 643, + GAUDI2_EVENT_TPC5_KERNEL_ERR = 644, + GAUDI2_EVENT_TPC6_BMON_SPMU = 645, + GAUDI2_EVENT_TPC6_KERNEL_ERR = 646, + GAUDI2_EVENT_TPC7_BMON_SPMU = 647, + GAUDI2_EVENT_TPC7_KERNEL_ERR = 648, + GAUDI2_EVENT_TPC8_BMON_SPMU = 649, + GAUDI2_EVENT_TPC8_KERNEL_ERR = 650, + GAUDI2_EVENT_TPC9_BMON_SPMU = 651, + GAUDI2_EVENT_TPC9_KERNEL_ERR = 652, + GAUDI2_EVENT_TPC10_BMON_SPMU = 653, + GAUDI2_EVENT_TPC10_KERNEL_ERR = 654, + GAUDI2_EVENT_TPC11_BMON_SPMU = 655, + GAUDI2_EVENT_TPC11_KERNEL_ERR = 656, + GAUDI2_EVENT_TPC12_BMON_SPMU = 657, + GAUDI2_EVENT_TPC12_KERNEL_ERR = 658, + GAUDI2_EVENT_TPC13_BMON_SPMU = 659, + GAUDI2_EVENT_TPC13_KERNEL_ERR = 660, + GAUDI2_EVENT_TPC14_BMON_SPMU = 661, + GAUDI2_EVENT_TPC14_KERNEL_ERR = 662, + GAUDI2_EVENT_TPC15_BMON_SPMU = 663, + GAUDI2_EVENT_TPC15_KERNEL_ERR = 664, + GAUDI2_EVENT_TPC16_BMON_SPMU = 665, + GAUDI2_EVENT_TPC16_KERNEL_ERR = 666, + GAUDI2_EVENT_TPC17_BMON_SPMU = 667, + GAUDI2_EVENT_TPC17_KERNEL_ERR = 668, + GAUDI2_EVENT_TPC18_BMON_SPMU = 669, + GAUDI2_EVENT_TPC18_KERNEL_ERR = 670, + GAUDI2_EVENT_TPC19_BMON_SPMU = 671, + GAUDI2_EVENT_TPC19_KERNEL_ERR = 672, + GAUDI2_EVENT_TPC20_BMON_SPMU = 673, + GAUDI2_EVENT_TPC20_KERNEL_ERR = 674, + GAUDI2_EVENT_TPC21_BMON_SPMU = 675, + GAUDI2_EVENT_TPC21_KERNEL_ERR = 676, + GAUDI2_EVENT_TPC22_BMON_SPMU = 677, + GAUDI2_EVENT_TPC22_KERNEL_ERR = 678, + GAUDI2_EVENT_TPC23_BMON_SPMU = 679, + GAUDI2_EVENT_TPC23_KERNEL_ERR = 680, + GAUDI2_EVENT_TPC24_BMON_SPMU = 681, + GAUDI2_EVENT_TPC24_KERNEL_ERR = 682, + GAUDI2_EVENT_MME0_SPI_BASE = 683, + GAUDI2_EVENT_MME0_CTRL_BMON_SPMU = 688, + GAUDI2_EVENT_MME0_SBTE_BMON_SPMU = 689, + GAUDI2_EVENT_MME0_WAP_BMON_SPMU = 690, + GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID = 691, + GAUDI2_EVENT_MME1_SPI_BASE = 692, + GAUDI2_EVENT_MME1_CTRL_BMON_SPMU = 697, + GAUDI2_EVENT_MME1_SBTE_BMON_SPMU = 698, + GAUDI2_EVENT_MME1_WAP_BMON_SPMU = 699, + GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID = 700, + GAUDI2_EVENT_MME2_SPI_BASE = 701, + GAUDI2_EVENT_MME2_CTRL_BMON_SPMU = 706, + GAUDI2_EVENT_MME2_SBTE_BMON_SPMU = 707, + GAUDI2_EVENT_MME2_WAP_BMON_SPMU = 708, + GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID = 709, + GAUDI2_EVENT_MME3_SPI_BASE = 710, + GAUDI2_EVENT_MME3_CTRL_BMON_SPMU = 715, + GAUDI2_EVENT_MME3_SBTE_BMON_SPMU = 716, + GAUDI2_EVENT_MME3_WAP_BMON_SPMU = 717, + GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID = 718, + GAUDI2_EVENT_HMMU0_SPI_BASE = 719, + GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM = 720, + GAUDI2_EVENT_HMMU0_SECURITY_ERROR = 721, + GAUDI2_EVENT_HMMU1_SPI_BASE = 722, + GAUDI2_EVENT_HMMU1_PAGE_FAULT_WR_PERM = 723, + GAUDI2_EVENT_HMMU1_SECURITY_ERROR = 724, + GAUDI2_EVENT_HMMU2_SPI_BASE = 725, + GAUDI2_EVENT_HMMU2_PAGE_FAULT_WR_PERM = 726, + GAUDI2_EVENT_HMMU2_SECURITY_ERROR = 727, + GAUDI2_EVENT_HMMU3_SPI_BASE = 728, + GAUDI2_EVENT_HMMU3_PAGE_FAULT_WR_PERM = 729, + GAUDI2_EVENT_HMMU3_SECURITY_ERROR = 730, + GAUDI2_EVENT_HMMU8_SPI_BASE = 731, + GAUDI2_EVENT_HMMU8_PAGE_FAULT_WR_PERM = 732, + GAUDI2_EVENT_HMMU8_SECURITY_ERROR = 733, + GAUDI2_EVENT_HMMU9_SPI_BASE = 734, + GAUDI2_EVENT_HMMU9_PAGE_FAULT_WR_PERM = 735, + GAUDI2_EVENT_HMMU9_SECURITY_ERROR = 736, + GAUDI2_EVENT_HMMU10_SPI_BASE = 737, + GAUDI2_EVENT_HMMU10_PAGE_FAULT_WR_PERM = 738, + GAUDI2_EVENT_HMMU10_SECURITY_ERROR = 739, + GAUDI2_EVENT_HMMU11_SPI_BASE = 740, + GAUDI2_EVENT_HMMU11_PAGE_FAULT_WR_PERM = 741, + GAUDI2_EVENT_HMMU11_SECURITY_ERROR = 742, + GAUDI2_EVENT_HMMU7_SPI_BASE = 743, + GAUDI2_EVENT_HMMU7_PAGE_FAULT_WR_PERM = 744, + GAUDI2_EVENT_HMMU7_SECURITY_ERROR = 745, + GAUDI2_EVENT_HMMU6_SPI_BASE = 746, + GAUDI2_EVENT_HMMU6_PAGE_FAULT_WR_PERM = 747, + GAUDI2_EVENT_HMMU6_SECURITY_ERROR = 748, + GAUDI2_EVENT_HMMU5_SPI_BASE = 749, + GAUDI2_EVENT_HMMU5_PAGE_FAULT_WR_PERM = 750, + GAUDI2_EVENT_HMMU5_SECURITY_ERROR = 751, + GAUDI2_EVENT_HMMU4_SPI_BASE = 752, + GAUDI2_EVENT_HMMU4_PAGE_FAULT_WR_PERM = 753, + GAUDI2_EVENT_HMMU4_SECURITY_ERROR = 754, + GAUDI2_EVENT_HMMU15_SPI_BASE = 755, + GAUDI2_EVENT_HMMU15_PAGE_FAULT_WR_PERM = 756, + GAUDI2_EVENT_HMMU15_SECURITY_ERROR = 757, + GAUDI2_EVENT_HMMU14_SPI_BASE = 758, + GAUDI2_EVENT_HMMU14_PAGE_FAULT_WR_PERM = 759, + GAUDI2_EVENT_HMMU14_SECURITY_ERROR = 760, + GAUDI2_EVENT_HMMU13_SPI_BASE = 761, + GAUDI2_EVENT_HMMU13_PAGE_FAULT_WR_PERM = 762, + GAUDI2_EVENT_HMMU13_SECURITY_ERROR = 763, + GAUDI2_EVENT_HMMU12_SPI_BASE = 764, + GAUDI2_EVENT_HMMU12_PAGE_FAULT_WR_PERM = 765, + GAUDI2_EVENT_HMMU12_SECURITY_ERROR = 766, + GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM = 768, + GAUDI2_EVENT_PMMU0_SECURITY_ERROR = 769, + GAUDI2_EVENT_HDMA2_BM_SPMU = 770, + GAUDI2_EVENT_HDMA3_BM_SPMU = 772, + GAUDI2_EVENT_HDMA0_BM_SPMU = 774, + GAUDI2_EVENT_HDMA1_BM_SPMU = 776, + GAUDI2_EVENT_HDMA6_BM_SPMU = 778, + GAUDI2_EVENT_HDMA7_BM_SPMU = 780, + GAUDI2_EVENT_HDMA4_BM_SPMU = 782, + GAUDI2_EVENT_HDMA5_BM_SPMU = 784, + GAUDI2_EVENT_KDMA_BM_SPMU = 786, + GAUDI2_EVENT_PDMA0_BM_SPMU = 788, + GAUDI2_EVENT_PDMA1_BM_SPMU = 789, + GAUDI2_EVENT_HBM0_MC0_SPI = 790, + GAUDI2_EVENT_HBM0_MC1_SPI = 791, + GAUDI2_EVENT_HBM1_MC0_SPI = 792, + GAUDI2_EVENT_HBM1_MC1_SPI = 793, + GAUDI2_EVENT_HBM2_MC0_SPI = 794, + GAUDI2_EVENT_HBM2_MC1_SPI = 795, + GAUDI2_EVENT_HBM3_MC0_SPI = 796, + GAUDI2_EVENT_HBM3_MC1_SPI = 797, + GAUDI2_EVENT_HBM4_MC0_SPI = 798, + GAUDI2_EVENT_HBM4_MC1_SPI = 799, + GAUDI2_EVENT_HBM5_MC0_SPI = 800, + GAUDI2_EVENT_HBM5_MC1_SPI = 801, + GAUDI2_EVENT_CPU_BMON = 802, + GAUDI2_EVENT_CPU_BMON_1 = 803, + GAUDI2_EVENT_TS_A_SOUTH_0 = 804, + GAUDI2_EVENT_TS_A_NORTH_1 = 805, + GAUDI2_EVENT_TS_A_EAST_2 = 806, + GAUDI2_EVENT_TS_A_WEST_3 = 807, + GAUDI2_EVENT_PSOC0_GPIO_79_64 = 812, + GAUDI2_EVENT_PSOC1_GPIO_63_48 = 813, + GAUDI2_EVENT_PSOC2_GPIO_47_32 = 814, + GAUDI2_EVENT_PSOC3_GPIO_31_16 = 815, + GAUDI2_EVENT_PSOC4_GPIO_15_0 = 816, + GAUDI2_EVENT_PSOC58_RPM_READY = 870, + GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN = 871, + GAUDI2_EVENT_PSOC60_GPIO_95_80 = 872, + GAUDI2_EVENT_PSOC62_QSPI_INTERRUPT = 874, + GAUDI2_EVENT_PSOC63_RAZWI_OR_PID_MIN_MAX_INTERRUPT = 875, + GAUDI2_EVENT_PSOC64_ADC0_INTERRUPT = 876, + GAUDI2_EVENT_PSOC65_PID = 877, + GAUDI2_EVENT_PSOC66_IC_SLV_SMBALERT_DET_INTR = 878, + GAUDI2_EVENT_PSOC75_SVID0_PARITY_ERROR_INTERRUPT = 887, + GAUDI2_EVENT_PSOC76_SVID1_PARITY_ERROR_INTERRUPT = 888, + GAUDI2_EVENT_PSOC77_SVID_PARITY_ERROR_INTERRUPT = 889, + GAUDI2_EVENT_PSOC78_SVID0_READY_INTERRUPT = 890, + GAUDI2_EVENT_PSOC79_SVID1_READY_INTERRUPT = 891, + GAUDI2_EVENT_PSOC80_SVID2_READY_INTERRUPT = 892, + GAUDI2_EVENT_PSOC81_ADC1_INTERRUPT = 893, + GAUDI2_EVENT_PSOC82_SVID_COMBINED_ALERT_INTERRUPT = 894, + GAUDI2_EVENT_PSOC83_SPI_WARE_OUT_ATTACK_OR_ARP = 895, + GAUDI2_EVENT_DEC0_SPI = 896, + GAUDI2_EVENT_DEC0_BMON_SPMU = 897, + GAUDI2_EVENT_DEC1_SPI = 898, + GAUDI2_EVENT_DEC1_BMON_SPMU = 899, + GAUDI2_EVENT_DEC2_SPI = 900, + GAUDI2_EVENT_DEC2_BMON_SPMU = 901, + GAUDI2_EVENT_DEC3_SPI = 902, + GAUDI2_EVENT_DEC3_BMON_SPMU = 903, + GAUDI2_EVENT_DEC4_SPI = 904, + GAUDI2_EVENT_DEC4_BMON_SPMU = 905, + GAUDI2_EVENT_DEC5_SPI = 906, + GAUDI2_EVENT_DEC5_BMON_SPMU = 907, + GAUDI2_EVENT_DEC6_SPI = 908, + GAUDI2_EVENT_DEC6_BMON_SPMU = 909, + GAUDI2_EVENT_DEC7_SPI = 910, + GAUDI2_EVENT_DEC7_BMON_SPMU = 911, + GAUDI2_EVENT_DEC8_SPI = 912, + GAUDI2_EVENT_DEC8_BMON_SPMU = 913, + GAUDI2_EVENT_DEC9_SPI = 914, + GAUDI2_EVENT_DEC9_BMON_SPMU = 915, + GAUDI2_EVENT_HIF0_SPI_WARN = 918, + GAUDI2_EVENT_HIF1_SPI_WARN = 920, + GAUDI2_EVENT_HIF2_SPI_WARN = 922, + GAUDI2_EVENT_HIF3_SPI_WARN = 924, + GAUDI2_EVENT_HIF8_SPI_WARN = 926, + GAUDI2_EVENT_HIF9_SPI_WARN = 928, + GAUDI2_EVENT_HIF10_SPI_WARN = 930, + GAUDI2_EVENT_HIF11_SPI_WARN = 932, + GAUDI2_EVENT_HIF7_SPI_WARN = 934, + GAUDI2_EVENT_HIF6_SPI_WARN = 936, + GAUDI2_EVENT_HIF5_SPI_WARN = 938, + GAUDI2_EVENT_HIF4_SPI_WARN = 940, + GAUDI2_EVENT_HIF15_SPI_WARN = 942, + GAUDI2_EVENT_HIF14_SPI_WARN = 944, + GAUDI2_EVENT_HIF13_SPI_WARN = 946, + GAUDI2_EVENT_HIF12_SPI_WARN = 948, + GAUDI2_EVENT_NIC0_BMON_SPMU = 951, + GAUDI2_EVENT_NIC0_SW_ERROR = 952, + GAUDI2_EVENT_NIC1_BMON_SPMU = 955, + GAUDI2_EVENT_NIC1_SW_ERROR = 956, + GAUDI2_EVENT_NIC2_BMON_SPMU = 959, + GAUDI2_EVENT_NIC2_SW_ERROR = 960, + GAUDI2_EVENT_NIC3_BMON_SPMU = 963, + GAUDI2_EVENT_NIC3_SW_ERROR = 964, + GAUDI2_EVENT_NIC4_BMON_SPMU = 967, + GAUDI2_EVENT_NIC4_SW_ERROR = 968, + GAUDI2_EVENT_NIC5_BMON_SPMU = 971, + GAUDI2_EVENT_NIC5_SW_ERROR = 972, + GAUDI2_EVENT_NIC6_BMON_SPMU = 975, + GAUDI2_EVENT_NIC6_SW_ERROR = 976, + GAUDI2_EVENT_NIC7_BMON_SPMU = 979, + GAUDI2_EVENT_NIC7_SW_ERROR = 980, + GAUDI2_EVENT_NIC8_BMON_SPMU = 983, + GAUDI2_EVENT_NIC8_SW_ERROR = 984, + GAUDI2_EVENT_NIC9_BMON_SPMU = 987, + GAUDI2_EVENT_NIC9_SW_ERROR = 988, + GAUDI2_EVENT_NIC10_BMON_SPMU = 991, + GAUDI2_EVENT_NIC10_SW_ERROR = 992, + GAUDI2_EVENT_NIC11_BMON_SPMU = 995, + GAUDI2_EVENT_NIC11_SW_ERROR = 996, + GAUDI2_EVENT_ROTATOR0_SERR = 1118, + GAUDI2_EVENT_ROTATOR1_SERR = 1119, + GAUDI2_EVENT_ROTATOR0_DERR = 1120, + GAUDI2_EVENT_ROTATOR1_DERR = 1121, + GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE = 1122, + GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE = 1123, + GAUDI2_EVENT_ROTATOR0_BMON_SPMU = 1126, + GAUDI2_EVENT_ROTATOR1_BMON_SPMU = 1128, + GAUDI2_EVENT_SM0_BMON_SPMU = 1130, + GAUDI2_EVENT_SM1_BMON_SPMU = 1131, + GAUDI2_EVENT_SM2_BMON_SPMU = 1132, + GAUDI2_EVENT_SM3_BMON_SPMU = 1133, + GAUDI2_EVENT_PSOC_DMA_QM = 1174, + GAUDI2_EVENT_TPC0_QM = 1206, + GAUDI2_EVENT_TPC1_QM = 1207, + GAUDI2_EVENT_TPC2_QM = 1208, + GAUDI2_EVENT_TPC3_QM = 1209, + GAUDI2_EVENT_TPC4_QM = 1210, + GAUDI2_EVENT_TPC5_QM = 1211, + GAUDI2_EVENT_TPC6_QM = 1212, + GAUDI2_EVENT_TPC7_QM = 1213, + GAUDI2_EVENT_TPC8_QM = 1214, + GAUDI2_EVENT_TPC9_QM = 1215, + GAUDI2_EVENT_TPC10_QM = 1216, + GAUDI2_EVENT_TPC11_QM = 1217, + GAUDI2_EVENT_TPC12_QM = 1218, + GAUDI2_EVENT_TPC13_QM = 1219, + GAUDI2_EVENT_TPC14_QM = 1220, + GAUDI2_EVENT_TPC15_QM = 1221, + GAUDI2_EVENT_TPC16_QM = 1222, + GAUDI2_EVENT_TPC17_QM = 1223, + GAUDI2_EVENT_TPC18_QM = 1224, + GAUDI2_EVENT_TPC19_QM = 1225, + GAUDI2_EVENT_TPC20_QM = 1226, + GAUDI2_EVENT_TPC21_QM = 1227, + GAUDI2_EVENT_TPC22_QM = 1228, + GAUDI2_EVENT_TPC23_QM = 1229, + GAUDI2_EVENT_TPC24_QM = 1230, + GAUDI2_EVENT_MME0_QM = 1232, + GAUDI2_EVENT_MME1_QM = 1233, + GAUDI2_EVENT_MME2_QM = 1234, + GAUDI2_EVENT_MME3_QM = 1235, + GAUDI2_EVENT_HDMA2_QM = 1236, + GAUDI2_EVENT_HDMA3_QM = 1237, + GAUDI2_EVENT_HDMA0_QM = 1238, + GAUDI2_EVENT_HDMA1_QM = 1239, + GAUDI2_EVENT_HDMA6_QM = 1240, + GAUDI2_EVENT_HDMA7_QM = 1241, + GAUDI2_EVENT_HDMA4_QM = 1242, + GAUDI2_EVENT_HDMA5_QM = 1243, + GAUDI2_EVENT_PDMA0_QM = 1244, + GAUDI2_EVENT_PDMA1_QM = 1245, + GAUDI2_EVENT_CPU_PI_UPDATE = 1246, + GAUDI2_EVENT_CPU_HALT_MACHINE = 1247, + GAUDI2_EVENT_CPU_INTS_REGISTER = 1248, + GAUDI2_EVENT_ROTATOR0_ROT0_QM = 1249, + GAUDI2_EVENT_ROTATOR1_ROT1_QM = 1250, + GAUDI2_EVENT_CPU_SOFT_RESET = 1251, + GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE = 1252, + GAUDI2_EVENT_CPU_FIX_POWER_ENV_S = 1253, + GAUDI2_EVENT_CPU_FIX_POWER_ENV_E = 1254, + GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S = 1255, + GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E = 1256, + GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_EVENT = 1257, + GAUDI2_EVENT_CPU_PKT_QUEUE_OUT_SYNC = 1258, + GAUDI2_EVENT_HDMA2_CORE = 1259, + GAUDI2_EVENT_HDMA3_CORE = 1260, + GAUDI2_EVENT_HDMA0_CORE = 1261, + GAUDI2_EVENT_HDMA1_CORE = 1262, + GAUDI2_EVENT_HDMA6_CORE = 1263, + GAUDI2_EVENT_HDMA7_CORE = 1264, + GAUDI2_EVENT_HDMA4_CORE = 1265, + GAUDI2_EVENT_HDMA5_CORE = 1266, + GAUDI2_EVENT_PDMA0_CORE = 1267, + GAUDI2_EVENT_PDMA1_CORE = 1268, + GAUDI2_EVENT_KDMA0_CORE = 1269, + GAUDI2_EVENT_NIC0_QM0 = 1270, + GAUDI2_EVENT_NIC0_QM1 = 1271, + GAUDI2_EVENT_NIC1_QM0 = 1272, + GAUDI2_EVENT_NIC1_QM1 = 1273, + GAUDI2_EVENT_NIC2_QM0 = 1274, + GAUDI2_EVENT_NIC2_QM1 = 1275, + GAUDI2_EVENT_NIC3_QM0 = 1276, + GAUDI2_EVENT_NIC3_QM1 = 1277, + GAUDI2_EVENT_NIC4_QM0 = 1278, + GAUDI2_EVENT_NIC4_QM1 = 1279, + GAUDI2_EVENT_NIC5_QM0 = 1280, + GAUDI2_EVENT_NIC5_QM1 = 1281, + GAUDI2_EVENT_NIC6_QM0 = 1282, + GAUDI2_EVENT_NIC6_QM1 = 1283, + GAUDI2_EVENT_NIC7_QM0 = 1284, + GAUDI2_EVENT_NIC7_QM1 = 1285, + GAUDI2_EVENT_NIC8_QM0 = 1286, + GAUDI2_EVENT_NIC8_QM1 = 1287, + GAUDI2_EVENT_NIC9_QM0 = 1288, + GAUDI2_EVENT_NIC9_QM1 = 1289, + GAUDI2_EVENT_NIC10_QM0 = 1290, + GAUDI2_EVENT_NIC10_QM1 = 1291, + GAUDI2_EVENT_NIC11_QM0 = 1292, + GAUDI2_EVENT_NIC11_QM1 = 1293, + GAUDI2_EVENT_CPU_PKT_SANITY_FAILED = 1294, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 = 1295, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG1 = 1296, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG0 = 1297, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG1 = 1298, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG0 = 1299, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG1 = 1300, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG0 = 1301, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG1 = 1302, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG0 = 1303, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG1 = 1304, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG0 = 1305, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG1 = 1306, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG0 = 1307, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG1 = 1308, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG0 = 1309, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG1 = 1310, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG0 = 1311, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG1 = 1312, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG0 = 1313, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG1 = 1314, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG0 = 1315, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG1 = 1316, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG0 = 1317, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1 = 1318, + GAUDI2_EVENT_ARC_DCCM_FULL = 1319, + GAUDI2_EVENT_SIZE, +}; + +#endif /* __GAUDI2_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h new file mode 100644 index 000000000..5bd4383c9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h @@ -0,0 +1,2668 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ +#define __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ + +struct gaudi2_async_events_ids_map { + int fc_id; + int cpu_id; + int valid; + int msg; + int reset; + char name[64]; +}; + +static struct gaudi2_async_events_ids_map gaudi2_irq_map_table[] = { + { .fc_id = 0, .cpu_id = 0, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_ECC_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_ECC_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_ECC_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_ECC_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_ECC_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_ECC_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_ECC_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_ECC_SERR" }, + { .fc_id = 46, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_ECC_SERR" }, + { .fc_id = 47, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_ECC_SERR" }, + { .fc_id = 48, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_ECC_SERR" }, + { .fc_id = 49, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_ECC_SERR" }, + { .fc_id = 50, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_ECC_SERR" }, + { .fc_id = 51, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_ECC_SERR" }, + { .fc_id = 52, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_ECC_SERR" }, + { .fc_id = 53, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_ECC_SERR" }, + { .fc_id = 54, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_ECC_SERR" }, + { .fc_id = 55, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_ECC_SERR" }, + { .fc_id = 56, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_ECC_SERR" }, + { .fc_id = 57, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_ECC_SERR" }, + { .fc_id = 58, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_ECC_SERR" }, + { .fc_id = 59, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_ECC_SERR" }, + { .fc_id = 60, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_ECC_SERR" }, + { .fc_id = 61, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_ECC_SERR" }, + { .fc_id = 62, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_ECC_SERR" }, + { .fc_id = 63, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC0_ECC_DERR" }, + { .fc_id = 64, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC1_ECC_DERR" }, + { .fc_id = 65, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC2_ECC_DERR" }, + { .fc_id = 66, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC3_ECC_DERR" }, + { .fc_id = 67, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC4_ECC_DERR" }, + { .fc_id = 68, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC5_ECC_DERR" }, + { .fc_id = 69, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC6_ECC_DERR" }, + { .fc_id = 70, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC7_ECC_DERR" }, + { .fc_id = 71, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC8_ECC_DERR" }, + { .fc_id = 72, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC9_ECC_DERR" }, + { .fc_id = 73, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC10_ECC_DERR" }, + { .fc_id = 74, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC11_ECC_DERR" }, + { .fc_id = 75, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC12_ECC_DERR" }, + { .fc_id = 76, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC13_ECC_DERR" }, + { .fc_id = 77, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC14_ECC_DERR" }, + { .fc_id = 78, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC15_ECC_DERR" }, + { .fc_id = 79, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC16_ECC_DERR" }, + { .fc_id = 80, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC17_ECC_DERR" }, + { .fc_id = 81, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC18_ECC_DERR" }, + { .fc_id = 82, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC19_ECC_DERR" }, + { .fc_id = 83, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC20_ECC_DERR" }, + { .fc_id = 84, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC21_ECC_DERR" }, + { .fc_id = 85, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC22_ECC_DERR" }, + { .fc_id = 86, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC23_ECC_DERR" }, + { .fc_id = 87, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC24_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE0_ECC_SERR" }, + { .fc_id = 89, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE1_ECC_SERR" }, + { .fc_id = 90, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE2_ECC_SERR" }, + { .fc_id = 91, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE3_ECC_SERR" }, + { .fc_id = 92, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE4_ECC_SERR" }, + { .fc_id = 93, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_CTRL_ECC_SERR" }, + { .fc_id = 94, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_ECC_SERR" }, + { .fc_id = 95, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE0_ECC_SERR" }, + { .fc_id = 96, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE1_ECC_SERR" }, + { .fc_id = 97, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE2_ECC_SERR" }, + { .fc_id = 98, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE3_ECC_SERR" }, + { .fc_id = 99, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE4_ECC_SERR" }, + { .fc_id = 100, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_CTRL_ECC_SERR" }, + { .fc_id = 101, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_ECC_SERR" }, + { .fc_id = 102, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE0_ECC_SERR" }, + { .fc_id = 103, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE1_ECC_SERR" }, + { .fc_id = 104, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE2_ECC_SERR" }, + { .fc_id = 105, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE3_ECC_SERR" }, + { .fc_id = 106, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE4_ECC_SERR" }, + { .fc_id = 107, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_CTRL_ECC_SERR" }, + { .fc_id = 108, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_ECC_SERR" }, + { .fc_id = 109, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE0_ECC_SERR" }, + { .fc_id = 110, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE1_ECC_SERR" }, + { .fc_id = 111, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE2_ECC_SERR" }, + { .fc_id = 112, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE3_ECC_SERR" }, + { .fc_id = 113, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE4_ECC_SERR" }, + { .fc_id = 114, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_CTRL_ECC_SERR" }, + { .fc_id = 115, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_ECC_SERR" }, + { .fc_id = 116, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE0_ECC_DERR" }, + { .fc_id = 117, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE1_ECC_DERR" }, + { .fc_id = 118, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE2_ECC_DERR" }, + { .fc_id = 119, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE3_ECC_DERR" }, + { .fc_id = 120, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE4_ECC_DERR" }, + { .fc_id = 121, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_CTRL_ECC_DERR" }, + { .fc_id = 122, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_WAP_ECC_DERR" }, + { .fc_id = 123, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE0_ECC_DERR" }, + { .fc_id = 124, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE1_ECC_DERR" }, + { .fc_id = 125, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE2_ECC_DERR" }, + { .fc_id = 126, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE3_ECC_DERR" }, + { .fc_id = 127, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE4_ECC_DERR" }, + { .fc_id = 128, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_CTRL_ECC_DERR" }, + { .fc_id = 129, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_WAP_ECC_DERR" }, + { .fc_id = 130, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE0_ECC_DERR" }, + { .fc_id = 131, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE1_ECC_DERR" }, + { .fc_id = 132, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE2_ECC_DERR" }, + { .fc_id = 133, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE3_ECC_DERR" }, + { .fc_id = 134, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE4_ECC_DERR" }, + { .fc_id = 135, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_CTRL_ECC_DERR" }, + { .fc_id = 136, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_WAP_ECC_DERR" }, + { .fc_id = 137, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE0_ECC_DERR" }, + { .fc_id = 138, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE1_ECC_DERR" }, + { .fc_id = 139, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE2_ECC_DERR" }, + { .fc_id = 140, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE3_ECC_DERR" }, + { .fc_id = 141, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE4_ECC_DERR" }, + { .fc_id = 142, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_CTRL_ECC_DERR" }, + { .fc_id = 143, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_WAP_ECC_DERR" }, + { .fc_id = 144, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA2_ECC_SERR" }, + { .fc_id = 145, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA3_ECC_SERR" }, + { .fc_id = 146, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA0_ECC_SERR" }, + { .fc_id = 147, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA1_ECC_SERR" }, + { .fc_id = 148, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA6_ECC_SERR" }, + { .fc_id = 149, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA7_ECC_SERR" }, + { .fc_id = 150, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA4_ECC_SERR" }, + { .fc_id = 151, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA5_ECC_SERR" }, + { .fc_id = 152, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA2_ECC_DERR" }, + { .fc_id = 153, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA3_ECC_DERR" }, + { .fc_id = 154, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA0_ECC_DERR" }, + { .fc_id = 155, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA1_ECC_DERR" }, + { .fc_id = 156, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA6_ECC_DERR" }, + { .fc_id = 157, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA7_ECC_DERR" }, + { .fc_id = 158, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA4_ECC_DERR" }, + { .fc_id = 159, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA5_ECC_DERR" }, + { .fc_id = 160, .cpu_id = 50, .valid = 1, + .msg = 0, .reset = 0, .name = "KDMA0_ECC_SERR" }, + { .fc_id = 161, .cpu_id = 51, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA0_ECC_SERR" }, + { .fc_id = 162, .cpu_id = 51, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA1_ECC_SERR" }, + { .fc_id = 163, .cpu_id = 52, .valid = 1, + .msg = 0, .reset = 1, .name = "KDMA0_ECC_DERR" }, + { .fc_id = 164, .cpu_id = 53, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA0_ECC_DERR" }, + { .fc_id = 165, .cpu_id = 53, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA1_ECC_DERR" }, + { .fc_id = 166, .cpu_id = 54, .valid = 1, + .msg = 0, .reset = 0, .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 167, .cpu_id = 55, .valid = 1, + .msg = 0, .reset = 1, .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 168, .cpu_id = 56, .valid = 1, + .msg = 0, .reset = 0, .name = "PSOC_MEM_SERR" }, + { .fc_id = 169, .cpu_id = 57, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_MEM_DERR" }, + { .fc_id = 170, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM0_ECC_SERR" }, + { .fc_id = 171, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM1_ECC_SERR" }, + { .fc_id = 172, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM2_ECC_SERR" }, + { .fc_id = 173, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM3_ECC_SERR" }, + { .fc_id = 174, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM4_ECC_SERR" }, + { .fc_id = 175, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM5_ECC_SERR" }, + { .fc_id = 176, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM6_ECC_SERR" }, + { .fc_id = 177, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM7_ECC_SERR" }, + { .fc_id = 178, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM8_ECC_SERR" }, + { .fc_id = 179, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM9_ECC_SERR" }, + { .fc_id = 180, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM10_ECC_SERR" }, + { .fc_id = 181, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM11_ECC_SERR" }, + { .fc_id = 182, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM12_ECC_SERR" }, + { .fc_id = 183, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM13_ECC_SERR" }, + { .fc_id = 184, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM14_ECC_SERR" }, + { .fc_id = 185, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM15_ECC_SERR" }, + { .fc_id = 186, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM16_ECC_SERR" }, + { .fc_id = 187, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM17_ECC_SERR" }, + { .fc_id = 188, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM18_ECC_SERR" }, + { .fc_id = 189, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM19_ECC_SERR" }, + { .fc_id = 190, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM20_ECC_SERR" }, + { .fc_id = 191, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM21_ECC_SERR" }, + { .fc_id = 192, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM22_ECC_SERR" }, + { .fc_id = 193, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM23_ECC_SERR" }, + { .fc_id = 194, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM24_ECC_SERR" }, + { .fc_id = 195, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM25_ECC_SERR" }, + { .fc_id = 196, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM26_ECC_SERR" }, + { .fc_id = 197, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM27_ECC_SERR" }, + { .fc_id = 198, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM28_ECC_SERR" }, + { .fc_id = 199, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM29_ECC_SERR" }, + { .fc_id = 200, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM30_ECC_SERR" }, + { .fc_id = 201, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM31_ECC_SERR" }, + { .fc_id = 202, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM0_ECC_DERR" }, + { .fc_id = 203, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM1_ECC_DERR" }, + { .fc_id = 204, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM2_ECC_DERR" }, + { .fc_id = 205, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM3_ECC_DERR" }, + { .fc_id = 206, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM4_ECC_DERR" }, + { .fc_id = 207, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM5_ECC_DERR" }, + { .fc_id = 208, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM6_ECC_DERR" }, + { .fc_id = 209, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM7_ECC_DERR" }, + { .fc_id = 210, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM8_ECC_DERR" }, + { .fc_id = 211, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM9_ECC_DERR" }, + { .fc_id = 212, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM10_ECC_DERR" }, + { .fc_id = 213, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM11_ECC_DERR" }, + { .fc_id = 214, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM12_ECC_DERR" }, + { .fc_id = 215, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM13_ECC_DERR" }, + { .fc_id = 216, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM14_ECC_DERR" }, + { .fc_id = 217, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM15_ECC_DERR" }, + { .fc_id = 218, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM16_ECC_DERR" }, + { .fc_id = 219, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM17_ECC_DERR" }, + { .fc_id = 220, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM18_ECC_DERR" }, + { .fc_id = 221, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM19_ECC_DERR" }, + { .fc_id = 222, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM20_ECC_DERR" }, + { .fc_id = 223, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM21_ECC_DERR" }, + { .fc_id = 224, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM22_ECC_DERR" }, + { .fc_id = 225, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM23_ECC_DERR" }, + { .fc_id = 226, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM24_ECC_DERR" }, + { .fc_id = 227, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM25_ECC_DERR" }, + { .fc_id = 228, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM26_ECC_DERR" }, + { .fc_id = 229, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM27_ECC_DERR" }, + { .fc_id = 230, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM28_ECC_DERR" }, + { .fc_id = 231, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM29_ECC_DERR" }, + { .fc_id = 232, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM30_ECC_DERR" }, + { .fc_id = 233, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM31_ECC_DERR" }, + { .fc_id = 234, .cpu_id = 60, .valid = 1, + .msg = 0, .reset = 1, .name = "GIC500" }, + { .fc_id = 235, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_0_MC0_ECC_SERR" }, + { .fc_id = 236, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_1_MC0_ECC_SERR" }, + { .fc_id = 237, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_2_MC0_ECC_SERR" }, + { .fc_id = 238, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_3_MC0_ECC_SERR" }, + { .fc_id = 239, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_4_MC0_ECC_SERR" }, + { .fc_id = 240, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_5_MC0_ECC_SERR" }, + { .fc_id = 241, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_0_MC1_ECC_SERR" }, + { .fc_id = 242, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_1_MC1_ECC_SERR" }, + { .fc_id = 243, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_2_MC1_ECC_SERR" }, + { .fc_id = 244, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_3_MC1_ECC_SERR" }, + { .fc_id = 245, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_4_MC1_ECC_SERR" }, + { .fc_id = 246, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_5_MC1_ECC_SERR" }, + { .fc_id = 247, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_0_MC0_ECC_DERR" }, + { .fc_id = 248, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_1_MC0_ECC_DERR" }, + { .fc_id = 249, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_2_MC0_ECC_DERR" }, + { .fc_id = 250, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_3_MC0_ECC_DERR" }, + { .fc_id = 251, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_4_MC0_ECC_DERR" }, + { .fc_id = 252, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_5_MC0_ECC_DERR" }, + { .fc_id = 253, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_0_MC1_ECC_DERR" }, + { .fc_id = 254, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_1_MC1_ECC_DERR" }, + { .fc_id = 255, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_2_MC1_ECC_DERR" }, + { .fc_id = 256, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_3_MC1_ECC_DERR" }, + { .fc_id = 257, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_4_MC1_ECC_DERR" }, + { .fc_id = 258, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_5_MC1_ECC_DERR" }, + { .fc_id = 259, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_0_ECC_SERR" }, + { .fc_id = 260, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_1_ECC_SERR" }, + { .fc_id = 261, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_2_ECC_SERR" }, + { .fc_id = 262, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_3_ECC_SERR" }, + { .fc_id = 263, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_8_ECC_SERR" }, + { .fc_id = 264, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_9_ECC_SERR" }, + { .fc_id = 265, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_10_ECC_SERR" }, + { .fc_id = 266, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_11_ECC_SERR" }, + { .fc_id = 267, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_7_ECC_SERR" }, + { .fc_id = 268, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_6_ECC_SERR" }, + { .fc_id = 269, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_5_ECC_SERR" }, + { .fc_id = 270, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_4_ECC_SERR" }, + { .fc_id = 271, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_15_ECC_SERR" }, + { .fc_id = 272, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_14_ECC_SERR" }, + { .fc_id = 273, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_13_ECC_SERR" }, + { .fc_id = 274, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_12_ECC_SERR" }, + { .fc_id = 275, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_0_ECC_DERR" }, + { .fc_id = 276, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_1_ECC_DERR" }, + { .fc_id = 277, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_2_ECC_DERR" }, + { .fc_id = 278, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_3_ECC_DERR" }, + { .fc_id = 279, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_8_ECC_DERR" }, + { .fc_id = 280, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_9_ECC_DERR" }, + { .fc_id = 281, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_10_ECC_DERR" }, + { .fc_id = 282, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_11_ECC_DERR" }, + { .fc_id = 283, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_7_ECC_DERR" }, + { .fc_id = 284, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_6_ECC_DERR" }, + { .fc_id = 285, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_5_ECC_DERR" }, + { .fc_id = 286, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_4_ECC_DERR" }, + { .fc_id = 287, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_15_ECC_DERR" }, + { .fc_id = 288, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_14_ECC_DERR" }, + { .fc_id = 289, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_13_ECC_DERR" }, + { .fc_id = 290, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_12_ECC_DERR" }, + { .fc_id = 291, .cpu_id = 65, .valid = 1, + .msg = 0, .reset = 0, .name = "PMMU_ECC_SERR" }, + { .fc_id = 292, .cpu_id = 66, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_ECC_DERR" }, + { .fc_id = 293, .cpu_id = 67, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 294, .cpu_id = 68, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 295, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_VCD_ECC_SERR" }, + { .fc_id = 296, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_VCD_ECC_SERR" }, + { .fc_id = 297, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_VCD_ECC_SERR" }, + { .fc_id = 298, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_VCD_ECC_SERR" }, + { .fc_id = 299, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_VCD_ECC_SERR" }, + { .fc_id = 300, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_VCD_ECC_SERR" }, + { .fc_id = 301, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_VCD_ECC_SERR" }, + { .fc_id = 302, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_VCD_ECC_SERR" }, + { .fc_id = 303, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_VCD_ECC_SERR" }, + { .fc_id = 304, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_VCD_ECC_SERR" }, + { .fc_id = 305, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_L2C_ECC_SERR" }, + { .fc_id = 306, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_L2C_ECC_SERR" }, + { .fc_id = 307, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_L2C_ECC_SERR" }, + { .fc_id = 308, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_L2C_ECC_SERR" }, + { .fc_id = 309, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_L2C_ECC_SERR" }, + { .fc_id = 310, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_L2C_ECC_SERR" }, + { .fc_id = 311, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_L2C_ECC_SERR" }, + { .fc_id = 312, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_L2C_ECC_SERR" }, + { .fc_id = 313, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_L2C_ECC_SERR" }, + { .fc_id = 314, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_L2C_ECC_SERR" }, + { .fc_id = 315, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_VCD_ECC_DERR" }, + { .fc_id = 316, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_VCD_ECC_DERR" }, + { .fc_id = 317, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_VCD_ECC_DERR" }, + { .fc_id = 318, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_VCD_ECC_DERR" }, + { .fc_id = 319, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_VCD_ECC_DERR" }, + { .fc_id = 320, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_VCD_ECC_DERR" }, + { .fc_id = 321, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_VCD_ECC_DERR" }, + { .fc_id = 322, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_VCD_ECC_DERR" }, + { .fc_id = 323, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_VCD_ECC_DERR" }, + { .fc_id = 324, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_VCD_ECC_DERR" }, + { .fc_id = 325, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_L2C_ECC_DERR" }, + { .fc_id = 326, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_L2C_ECC_DERR" }, + { .fc_id = 327, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_L2C_ECC_DERR" }, + { .fc_id = 328, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_L2C_ECC_DERR" }, + { .fc_id = 329, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_L2C_ECC_DERR" }, + { .fc_id = 330, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_L2C_ECC_DERR" }, + { .fc_id = 331, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_L2C_ECC_DERR" }, + { .fc_id = 332, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_L2C_ECC_DERR" }, + { .fc_id = 333, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_L2C_ECC_DERR" }, + { .fc_id = 334, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_L2C_ECC_DERR" }, + { .fc_id = 335, .cpu_id = 71, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 336, .cpu_id = 72, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 337, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF0_ECC_SERR" }, + { .fc_id = 338, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF1_ECC_SERR" }, + { .fc_id = 339, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF2_ECC_SERR" }, + { .fc_id = 340, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF3_ECC_SERR" }, + { .fc_id = 341, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF8_ECC_SERR" }, + { .fc_id = 342, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF9_ECC_SERR" }, + { .fc_id = 343, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF10_ECC_SERR" }, + { .fc_id = 344, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF11_ECC_SERR" }, + { .fc_id = 345, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF7_ECC_SERR" }, + { .fc_id = 346, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF6_ECC_SERR" }, + { .fc_id = 347, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF5_ECC_SERR" }, + { .fc_id = 348, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF4_ECC_SERR" }, + { .fc_id = 349, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF15_ECC_SERR" }, + { .fc_id = 350, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF14_ECC_SERR" }, + { .fc_id = 351, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF13_ECC_SERR" }, + { .fc_id = 352, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF12_ECC_SERR" }, + { .fc_id = 353, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF0_ECC_DERR" }, + { .fc_id = 354, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF1_ECC_DERR" }, + { .fc_id = 355, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF2_ECC_DERR" }, + { .fc_id = 356, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF3_ECC_DERR" }, + { .fc_id = 357, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF8_ECC_DERR" }, + { .fc_id = 358, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF9_ECC_DERR" }, + { .fc_id = 359, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF10_ECC_DERR" }, + { .fc_id = 360, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF11_ECC_DERR" }, + { .fc_id = 361, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF7_ECC_DERR" }, + { .fc_id = 362, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF6_ECC_DERR" }, + { .fc_id = 363, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF5_ECC_DERR" }, + { .fc_id = 364, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF4_ECC_DERR" }, + { .fc_id = 365, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF15_ECC_DERR" }, + { .fc_id = 366, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF14_ECC_DERR" }, + { .fc_id = 367, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF13_ECC_DERR" }, + { .fc_id = 368, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF12_ECC_DERR" }, + { .fc_id = 369, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_ECC_SERR" }, + { .fc_id = 370, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_ECC_SERR" }, + { .fc_id = 371, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_ECC_SERR" }, + { .fc_id = 372, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_ECC_SERR" }, + { .fc_id = 373, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_ECC_SERR" }, + { .fc_id = 374, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_ECC_SERR" }, + { .fc_id = 375, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_ECC_SERR" }, + { .fc_id = 376, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_ECC_SERR" }, + { .fc_id = 377, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_ECC_SERR" }, + { .fc_id = 378, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_ECC_SERR" }, + { .fc_id = 379, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_ECC_SERR" }, + { .fc_id = 380, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_ECC_SERR" }, + { .fc_id = 381, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC0_ECC_DERR" }, + { .fc_id = 382, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC1_ECC_DERR" }, + { .fc_id = 383, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC2_ECC_DERR" }, + { .fc_id = 384, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC3_ECC_DERR" }, + { .fc_id = 385, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC4_ECC_DERR" }, + { .fc_id = 386, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC5_ECC_DERR" }, + { .fc_id = 387, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC6_ECC_DERR" }, + { .fc_id = 388, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC7_ECC_DERR" }, + { .fc_id = 389, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC8_ECC_DERR" }, + { .fc_id = 390, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC9_ECC_DERR" }, + { .fc_id = 391, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC10_ECC_DERR" }, + { .fc_id = 392, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC11_ECC_DERR" }, + { .fc_id = 393, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM0_ECC_DERR" }, + { .fc_id = 394, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM1_ECC_DERR" }, + { .fc_id = 395, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM2_ECC_DERR" }, + { .fc_id = 396, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM3_ECC_DERR" }, + { .fc_id = 397, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM0_ECC_SERR" }, + { .fc_id = 398, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM1_ECC_SERR" }, + { .fc_id = 399, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM2_ECC_SERR" }, + { .fc_id = 400, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM3_ECC_SERR" }, + { .fc_id = 401, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR0_ECC_SERR" }, + { .fc_id = 402, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR1_ECC_SERR" }, + { .fc_id = 403, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR2_ECC_SERR" }, + { .fc_id = 404, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR3_ECC_SERR" }, + { .fc_id = 405, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR0_ECC_DERR" }, + { .fc_id = 406, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR1_ECC_DERR" }, + { .fc_id = 407, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR2_ECC_DERR" }, + { .fc_id = 408, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR3_ECC_DERR" }, + { .fc_id = 409, .cpu_id = 81, .valid = 1, + .msg = 0, .reset = 0, .name = "ARC0_ECC_SERR" }, + { .fc_id = 410, .cpu_id = 82, .valid = 1, + .msg = 0, .reset = 1, .name = "ARC0_ECC_DERR" }, + { .fc_id = 411, .cpu_id = 83, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 412, .cpu_id = 84, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_ADDR_DEC_ERR" }, + { .fc_id = 413, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC0_AXI_ERR_RSP" }, + { .fc_id = 414, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC1_AXI_ERR_RSP" }, + { .fc_id = 415, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC2_AXI_ERR_RSP" }, + { .fc_id = 416, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC3_AXI_ERR_RSP" }, + { .fc_id = 417, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC4_AXI_ERR_RSP" }, + { .fc_id = 418, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC5_AXI_ERR_RSP" }, + { .fc_id = 419, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC6_AXI_ERR_RSP" }, + { .fc_id = 420, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC7_AXI_ERR_RSP" }, + { .fc_id = 421, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC8_AXI_ERR_RSP" }, + { .fc_id = 422, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC9_AXI_ERR_RSP" }, + { .fc_id = 423, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC10_AXI_ERR_RSP" }, + { .fc_id = 424, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC11_AXI_ERR_RSP" }, + { .fc_id = 425, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC12_AXI_ERR_RSP" }, + { .fc_id = 426, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC13_AXI_ERR_RSP" }, + { .fc_id = 427, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC14_AXI_ERR_RSP" }, + { .fc_id = 428, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC15_AXI_ERR_RSP" }, + { .fc_id = 429, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC16_AXI_ERR_RSP" }, + { .fc_id = 430, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC17_AXI_ERR_RSP" }, + { .fc_id = 431, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC18_AXI_ERR_RSP" }, + { .fc_id = 432, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC19_AXI_ERR_RSP" }, + { .fc_id = 433, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC20_AXI_ERR_RSP" }, + { .fc_id = 434, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC21_AXI_ERR_RSP" }, + { .fc_id = 435, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC22_AXI_ERR_RSP" }, + { .fc_id = 436, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC23_AXI_ERR_RSP" }, + { .fc_id = 437, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC24_AXI_ERR_RSP" }, + { .fc_id = 438, .cpu_id = 86, .valid = 1, + .msg = 0, .reset = 1, .name = "AXI_ECC" }, + { .fc_id = 439, .cpu_id = 87, .valid = 1, + .msg = 0, .reset = 1, .name = "L2_RAM_ECC" }, + { .fc_id = 440, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 441, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 442, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 443, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 444, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 445, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 446, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_QMAN_SW_ERROR" }, + { .fc_id = 447, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 448, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 449, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 450, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 451, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 452, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 453, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_QMAN_SW_ERROR" }, + { .fc_id = 454, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 455, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 456, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 457, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 458, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 459, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 460, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_QMAN_SW_ERROR" }, + { .fc_id = 461, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 462, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 463, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 464, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 465, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 466, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 467, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_QMAN_SW_ERROR" }, + { .fc_id = 468, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_MME_PLL_LOCK_ERR" }, + { .fc_id = 469, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_CPU_PLL_LOCK_ERR" }, + { .fc_id = 470, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_TPC_PLL_LOCK_ERR" }, + { .fc_id = 471, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_NIC_PLL_LOCK_ERR" }, + { .fc_id = 472, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 473, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 474, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 475, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 476, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 477, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 478, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 479, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 480, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_TPC_PLL_LOCK_ERR" }, + { .fc_id = 481, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_NIC_PLL_LOCK_ERR" }, + { .fc_id = 482, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_MME_PLL_LOCK_ERR" }, + { .fc_id = 483, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_TPC_PLL_LOCK_ERR" }, + { .fc_id = 484, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_PCI_PLL_LOCK_ERR" }, + { .fc_id = 485, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 486, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 487, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 488, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 489, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 490, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 491, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 492, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 493, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_TPC_PLL_LOCK_ERR" }, + { .fc_id = 494, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_VID_PLL_LOCK_ERR" }, + { .fc_id = 495, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_VID_PLL_LOCK_ERR" }, + { .fc_id = 496, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_HBM_PLL_LOCK_ERR" }, + { .fc_id = 497, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 498, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_HBM_PLL_LOCK_ERR" }, + { .fc_id = 499, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_HBM_PLL_LOCK_ERR" }, + { .fc_id = 500, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 501, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_HBM_PLL_LOCK_ERR" }, + { .fc_id = 502, .cpu_id = 93, .valid = 1, + .msg = 0, .reset = 1, .name = "CPU_AXI_ERR_RSP" }, + { .fc_id = 503, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_0_AXI_ERR_RSP" }, + { .fc_id = 504, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_1_AXI_ERR_RSP" }, + { .fc_id = 505, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_2_AXI_ERR_RSP" }, + { .fc_id = 506, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_3_AXI_ERR_RSP" }, + { .fc_id = 507, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_8_AXI_ERR_RSP" }, + { .fc_id = 508, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_9_AXI_ERR_RSP" }, + { .fc_id = 509, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_10_AXI_ERR_RSP" }, + { .fc_id = 510, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_11_AXI_ERR_RSP" }, + { .fc_id = 511, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_7_AXI_ERR_RSP" }, + { .fc_id = 512, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_6_AXI_ERR_RSP" }, + { .fc_id = 513, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_5_AXI_ERR_RSP" }, + { .fc_id = 514, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_4_AXI_ERR_RSP" }, + { .fc_id = 515, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_15_AXI_ERR_RSP" }, + { .fc_id = 516, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_14_AXI_ERR_RSP" }, + { .fc_id = 517, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_13_AXI_ERR_RSP" }, + { .fc_id = 518, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_12_AXI_ERR_RSP" }, + { .fc_id = 519, .cpu_id = 95, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_FATAL" }, + { .fc_id = 520, .cpu_id = 96, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_AXI_ERR_RSP" }, + { .fc_id = 521, .cpu_id = 97, .valid = 1, + .msg = 0, .reset = 0, .name = "VM0_ALARM_A" }, + { .fc_id = 522, .cpu_id = 98, .valid = 1, + .msg = 0, .reset = 0, .name = "VM0_ALARM_B" }, + { .fc_id = 523, .cpu_id = 99, .valid = 1, + .msg = 0, .reset = 0, .name = "VM1_ALARM_A" }, + { .fc_id = 524, .cpu_id = 100, .valid = 1, + .msg = 0, .reset = 0, .name = "VM1_ALARM_B" }, + { .fc_id = 525, .cpu_id = 101, .valid = 1, + .msg = 0, .reset = 0, .name = "VM2_ALARM_A" }, + { .fc_id = 526, .cpu_id = 102, .valid = 1, + .msg = 0, .reset = 0, .name = "VM2_ALARM_B" }, + { .fc_id = 527, .cpu_id = 103, .valid = 1, + .msg = 0, .reset = 0, .name = "VM3_ALARM_A" }, + { .fc_id = 528, .cpu_id = 104, .valid = 1, + .msg = 0, .reset = 0, .name = "VM3_ALARM_B" }, + { .fc_id = 529, .cpu_id = 105, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_AXI_ERR_RSP" }, + { .fc_id = 530, .cpu_id = 106, .valid = 1, + .msg = 0, .reset = 0, .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 531, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 532, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 533, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 534, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 535, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 536, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 537, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 538, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 539, .cpu_id = 108, .valid = 1, + .msg = 0, .reset = 1, .name = "KDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 540, .cpu_id = 109, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 541, .cpu_id = 109, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA_CH1_AXI_ERR_RSP" }, + { .fc_id = 542, .cpu_id = 110, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_0" }, + { .fc_id = 543, .cpu_id = 111, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_1" }, + { .fc_id = 544, .cpu_id = 112, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_2" }, + { .fc_id = 545, .cpu_id = 113, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_3" }, + { .fc_id = 546, .cpu_id = 114, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_4" }, + { .fc_id = 547, .cpu_id = 115, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_5" }, + { .fc_id = 548, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM0_MC0_SEI_SEVERE" }, + { .fc_id = 549, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC0_SEI_NON_SEVERE" }, + { .fc_id = 550, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM0_MC1_SEI_SEVERE" }, + { .fc_id = 551, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC1_SEI_NON_SEVERE" }, + { .fc_id = 552, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM1_MC0_SEI_SEVERE" }, + { .fc_id = 553, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC0_SEI_NON_SEVERE" }, + { .fc_id = 554, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM1_MC1_SEI_SEVERE" }, + { .fc_id = 555, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC1_SEI_NON_SEVERE" }, + { .fc_id = 556, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM2_MC0_SEI_SEVERE" }, + { .fc_id = 557, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC0_SEI_NON_SEVERE" }, + { .fc_id = 558, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM2_MC1_SEI_SEVERE" }, + { .fc_id = 559, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC1_SEI_NON_SEVERE" }, + { .fc_id = 560, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM3_MC0_SEI_SEVERE" }, + { .fc_id = 561, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC0_SEI_NON_SEVERE" }, + { .fc_id = 562, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM3_MC1_SEI_SEVERE" }, + { .fc_id = 563, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC1_SEI_NON_SEVERE" }, + { .fc_id = 564, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM4_MC0_SEI_SEVERE" }, + { .fc_id = 565, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC0_SEI_NON_SEVERE" }, + { .fc_id = 566, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM4_MC1_SEI_SEVERE" }, + { .fc_id = 567, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC1_SEI_NON_SEVERE" }, + { .fc_id = 568, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM5_MC0_SEI_SEVERE" }, + { .fc_id = 569, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC0_SEI_NON_SEVERE" }, + { .fc_id = 570, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM5_MC1_SEI_SEVERE" }, + { .fc_id = 571, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC1_SEI_NON_SEVERE" }, + { .fc_id = 572, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_AXI_ERR_RSPONSE" }, + { .fc_id = 573, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_AXI_ERR_RSPONSE" }, + { .fc_id = 574, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_AXI_ERR_RSPONSE" }, + { .fc_id = 575, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_AXI_ERR_RSPONSE" }, + { .fc_id = 576, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_AXI_ERR_RSPONSE" }, + { .fc_id = 577, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_AXI_ERR_RSPONSE" }, + { .fc_id = 578, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_AXI_ERR_RSPONSE" }, + { .fc_id = 579, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_AXI_ERR_RSPONSE" }, + { .fc_id = 580, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_AXI_ERR_RSPONSE" }, + { .fc_id = 581, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_AXI_ERR_RSPONSE" }, + { .fc_id = 582, .cpu_id = 118, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 583, .cpu_id = 119, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 584, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF0_FATAL" }, + { .fc_id = 585, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF1_FATAL" }, + { .fc_id = 586, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF2_FATAL" }, + { .fc_id = 587, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF3_FATAL" }, + { .fc_id = 588, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF8_FATAL" }, + { .fc_id = 589, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF9_FATAL" }, + { .fc_id = 590, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF10_FATAL" }, + { .fc_id = 591, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF11_FATAL" }, + { .fc_id = 592, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF7_FATAL" }, + { .fc_id = 593, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF6_FATAL" }, + { .fc_id = 594, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF5_FATAL" }, + { .fc_id = 595, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF4_FATAL" }, + { .fc_id = 596, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF15_FATAL" }, + { .fc_id = 597, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF14_FATAL" }, + { .fc_id = 598, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF13_FATAL" }, + { .fc_id = 599, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF12_FATAL" }, + { .fc_id = 600, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC0_AXI_ERROR_RESPONSE" }, + { .fc_id = 601, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC1_AXI_ERROR_RESPONSE" }, + { .fc_id = 602, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC2_AXI_ERROR_RESPONSE" }, + { .fc_id = 603, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC3_AXI_ERROR_RESPONSE" }, + { .fc_id = 604, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC4_AXI_ERROR_RESPONSE" }, + { .fc_id = 605, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC5_AXI_ERROR_RESPONSE" }, + { .fc_id = 606, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC6_AXI_ERROR_RESPONSE" }, + { .fc_id = 607, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC7_AXI_ERROR_RESPONSE" }, + { .fc_id = 608, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC8_AXI_ERROR_RESPONSE" }, + { .fc_id = 609, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC9_AXI_ERROR_RESPONSE" }, + { .fc_id = 610, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC10_AXI_ERROR_RESPONSE" }, + { .fc_id = 611, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC11_AXI_ERROR_RESPONSE" }, + { .fc_id = 612, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM0_AXI_ERROR_RESPONSE" }, + { .fc_id = 613, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM1_AXI_ERROR_RESPONSE" }, + { .fc_id = 614, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM2_AXI_ERROR_RESPONSE" }, + { .fc_id = 615, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM3_AXI_ERROR_RESPONSE" }, + { .fc_id = 616, .cpu_id = 123, .valid = 1, + .msg = 0, .reset = 1, .name = "ARC_AXI_ERROR_RESPONSE" }, + { .fc_id = 617, .cpu_id = 124, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 618, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 619, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_FLR_REQUESTED" }, + { .fc_id = 620, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 621, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 622, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_APB_TIMEOUT" }, + { .fc_id = 623, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 624, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 625, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 626, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 627, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_FATAL_ERR" }, + { .fc_id = 628, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 629, .cpu_id = 126, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 630, .cpu_id = 127, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 631, .cpu_id = 128, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_P2P_MSIX" }, + { .fc_id = 632, .cpu_id = 129, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_DRAIN_COMPLETE" }, + { .fc_id = 633, .cpu_id = 130, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_BMON_SPMU" }, + { .fc_id = 634, .cpu_id = 131, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_KERNEL_ERR" }, + { .fc_id = 635, .cpu_id = 132, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_BMON_SPMU" }, + { .fc_id = 636, .cpu_id = 133, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_KERNEL_ERR" }, + { .fc_id = 637, .cpu_id = 134, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_BMON_SPMU" }, + { .fc_id = 638, .cpu_id = 135, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_KERNEL_ERR" }, + { .fc_id = 639, .cpu_id = 136, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_BMON_SPMU" }, + { .fc_id = 640, .cpu_id = 137, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_KERNEL_ERR" }, + { .fc_id = 641, .cpu_id = 138, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_BMON_SPMU" }, + { .fc_id = 642, .cpu_id = 139, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_KERNEL_ERR" }, + { .fc_id = 643, .cpu_id = 140, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_BMON_SPMU" }, + { .fc_id = 644, .cpu_id = 141, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_KERNEL_ERR" }, + { .fc_id = 645, .cpu_id = 150, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_BMON_SPMU" }, + { .fc_id = 646, .cpu_id = 151, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_KERNEL_ERR" }, + { .fc_id = 647, .cpu_id = 152, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_BMON_SPMU" }, + { .fc_id = 648, .cpu_id = 153, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_KERNEL_ERR" }, + { .fc_id = 649, .cpu_id = 146, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_BMON_SPMU" }, + { .fc_id = 650, .cpu_id = 147, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_KERNEL_ERR" }, + { .fc_id = 651, .cpu_id = 148, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_BMON_SPMU" }, + { .fc_id = 652, .cpu_id = 149, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_KERNEL_ERR" }, + { .fc_id = 653, .cpu_id = 142, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_BMON_SPMU" }, + { .fc_id = 654, .cpu_id = 143, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_KERNEL_ERR" }, + { .fc_id = 655, .cpu_id = 144, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_BMON_SPMU" }, + { .fc_id = 656, .cpu_id = 145, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_KERNEL_ERR" }, + { .fc_id = 657, .cpu_id = 162, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_BMON_SPMU" }, + { .fc_id = 658, .cpu_id = 163, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_KERNEL_ERR" }, + { .fc_id = 659, .cpu_id = 164, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_BMON_SPMU" }, + { .fc_id = 660, .cpu_id = 165, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_KERNEL_ERR" }, + { .fc_id = 661, .cpu_id = 158, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_BMON_SPMU" }, + { .fc_id = 662, .cpu_id = 159, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_KERNEL_ERR" }, + { .fc_id = 663, .cpu_id = 160, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_BMON_SPMU" }, + { .fc_id = 664, .cpu_id = 161, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_KERNEL_ERR" }, + { .fc_id = 665, .cpu_id = 154, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_BMON_SPMU" }, + { .fc_id = 666, .cpu_id = 155, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_KERNEL_ERR" }, + { .fc_id = 667, .cpu_id = 156, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_BMON_SPMU" }, + { .fc_id = 668, .cpu_id = 157, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_KERNEL_ERR" }, + { .fc_id = 669, .cpu_id = 166, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_BMON_SPMU" }, + { .fc_id = 670, .cpu_id = 167, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_KERNEL_ERR" }, + { .fc_id = 671, .cpu_id = 168, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_BMON_SPMU" }, + { .fc_id = 672, .cpu_id = 169, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_KERNEL_ERR" }, + { .fc_id = 673, .cpu_id = 170, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_BMON_SPMU" }, + { .fc_id = 674, .cpu_id = 171, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_KERNEL_ERR" }, + { .fc_id = 675, .cpu_id = 172, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_BMON_SPMU" }, + { .fc_id = 676, .cpu_id = 173, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_KERNEL_ERR" }, + { .fc_id = 677, .cpu_id = 174, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_BMON_SPMU" }, + { .fc_id = 678, .cpu_id = 175, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_KERNEL_ERR" }, + { .fc_id = 679, .cpu_id = 176, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_BMON_SPMU" }, + { .fc_id = 680, .cpu_id = 177, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_KERNEL_ERR" }, + { .fc_id = 681, .cpu_id = 178, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_BMON_SPMU" }, + { .fc_id = 682, .cpu_id = 179, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_KERNEL_ERR" }, + { .fc_id = 683, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 684, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 685, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 686, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 687, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 688, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_CTRL_BMON_SPMU" }, + { .fc_id = 689, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE_BMON_SPMU" }, + { .fc_id = 690, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_BMON_SPMU" }, + { .fc_id = 691, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 692, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 693, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 694, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 695, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 696, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 697, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_CTRL_BMON_SPMU" }, + { .fc_id = 698, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE_BMON_SPMU" }, + { .fc_id = 699, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_BMON_SPMU" }, + { .fc_id = 700, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 701, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 702, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 703, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 704, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 705, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 706, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_CTRL_BMON_SPMU" }, + { .fc_id = 707, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE_BMON_SPMU" }, + { .fc_id = 708, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_BMON_SPMU" }, + { .fc_id = 709, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 710, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 711, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 712, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 713, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 714, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 715, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_CTRL_BMON_SPMU" }, + { .fc_id = 716, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE_BMON_SPMU" }, + { .fc_id = 717, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_BMON_SPMU" }, + { .fc_id = 718, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 719, .cpu_id = 184, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 720, .cpu_id = 184, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU0_PAGE_FAULT_OR_WR_PERM" }, + { .fc_id = 721, .cpu_id = 184, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU0_SECURITY_ERROR" }, + { .fc_id = 722, .cpu_id = 185, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 723, .cpu_id = 185, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU1_PAGE_FAULT_WR_PERM" }, + { .fc_id = 724, .cpu_id = 185, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU1_SECURITY_ERROR" }, + { .fc_id = 725, .cpu_id = 186, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 726, .cpu_id = 186, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU2_PAGE_FAULT_WR_PERM" }, + { .fc_id = 727, .cpu_id = 186, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU2_SECURITY_ERROR" }, + { .fc_id = 728, .cpu_id = 187, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 729, .cpu_id = 187, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU3_PAGE_FAULT_WR_PERM" }, + { .fc_id = 730, .cpu_id = 187, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU3_SECURITY_ERROR" }, + { .fc_id = 731, .cpu_id = 188, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 732, .cpu_id = 188, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU8_PAGE_FAULT_WR_PERM" }, + { .fc_id = 733, .cpu_id = 188, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU8_SECURITY_ERROR" }, + { .fc_id = 734, .cpu_id = 189, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 735, .cpu_id = 189, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU9_PAGE_FAULT_WR_PERM" }, + { .fc_id = 736, .cpu_id = 189, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU9_SECURITY_ERROR" }, + { .fc_id = 737, .cpu_id = 190, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 738, .cpu_id = 190, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU10_PAGE_FAULT_WR_PERM" }, + { .fc_id = 739, .cpu_id = 190, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU10_SECURITY_ERROR" }, + { .fc_id = 740, .cpu_id = 191, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 741, .cpu_id = 191, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU11_PAGE_FAULT_WR_PERM" }, + { .fc_id = 742, .cpu_id = 191, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU11_SECURITY_ERROR" }, + { .fc_id = 743, .cpu_id = 192, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 744, .cpu_id = 192, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU7_PAGE_FAULT_WR_PERM" }, + { .fc_id = 745, .cpu_id = 192, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU7_SECURITY_ERROR" }, + { .fc_id = 746, .cpu_id = 193, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 747, .cpu_id = 193, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU6_PAGE_FAULT_WR_PERM" }, + { .fc_id = 748, .cpu_id = 193, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU6_SECURITY_ERROR" }, + { .fc_id = 749, .cpu_id = 194, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 750, .cpu_id = 194, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU5_PAGE_FAULT_WR_PERM" }, + { .fc_id = 751, .cpu_id = 194, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU5_SECURITY_ERROR" }, + { .fc_id = 752, .cpu_id = 195, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 753, .cpu_id = 195, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU4_PAGE_FAULT_WR_PERM" }, + { .fc_id = 754, .cpu_id = 195, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU4_SECURITY_ERROR" }, + { .fc_id = 755, .cpu_id = 196, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 756, .cpu_id = 196, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU15_PAGE_FAULT_WR_PERM" }, + { .fc_id = 757, .cpu_id = 196, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU15_SECURITY_ERROR" }, + { .fc_id = 758, .cpu_id = 197, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 759, .cpu_id = 197, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU14_PAGE_FAULT_WR_PERM" }, + { .fc_id = 760, .cpu_id = 197, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU14_SECURITY_ERROR" }, + { .fc_id = 761, .cpu_id = 198, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 762, .cpu_id = 198, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU13_PAGE_FAULT_WR_PERM" }, + { .fc_id = 763, .cpu_id = 198, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU13_SECURITY_ERROR" }, + { .fc_id = 764, .cpu_id = 199, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 765, .cpu_id = 199, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU12_PAGE_FAULT_WR_PERM" }, + { .fc_id = 766, .cpu_id = 199, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU12_SECURITY_ERROR" }, + { .fc_id = 767, .cpu_id = 200, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 768, .cpu_id = 201, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU0_PAGE_FAULT_WR_PERM" }, + { .fc_id = 769, .cpu_id = 202, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU0_SECURITY_ERROR" }, + { .fc_id = 770, .cpu_id = 203, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA2_BM_SPMU" }, + { .fc_id = 771, .cpu_id = 204, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 772, .cpu_id = 205, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA3_BM_SPMU" }, + { .fc_id = 773, .cpu_id = 206, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 774, .cpu_id = 207, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA0_BM_SPMU" }, + { .fc_id = 775, .cpu_id = 208, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 776, .cpu_id = 209, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA1_BM_SPMU" }, + { .fc_id = 777, .cpu_id = 210, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 778, .cpu_id = 211, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA6_BM_SPMU" }, + { .fc_id = 779, .cpu_id = 212, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 780, .cpu_id = 213, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA7_BM_SPMU" }, + { .fc_id = 781, .cpu_id = 214, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 782, .cpu_id = 215, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA4_BM_SPMU" }, + { .fc_id = 783, .cpu_id = 216, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 784, .cpu_id = 217, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA5_BM_SPMU" }, + { .fc_id = 785, .cpu_id = 218, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 786, .cpu_id = 219, .valid = 1, + .msg = 0, .reset = 0, .name = "KDMA_BM_SPMU" }, + { .fc_id = 787, .cpu_id = 220, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 788, .cpu_id = 221, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA0_BM_SPMU" }, + { .fc_id = 789, .cpu_id = 222, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA1_BM_SPMU" }, + { .fc_id = 790, .cpu_id = 223, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC0_SPI" }, + { .fc_id = 791, .cpu_id = 224, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC1_SPI" }, + { .fc_id = 792, .cpu_id = 225, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC0_SPI" }, + { .fc_id = 793, .cpu_id = 226, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC1_SPI" }, + { .fc_id = 794, .cpu_id = 227, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC0_SPI" }, + { .fc_id = 795, .cpu_id = 228, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC1_SPI" }, + { .fc_id = 796, .cpu_id = 229, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC0_SPI" }, + { .fc_id = 797, .cpu_id = 230, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC1_SPI" }, + { .fc_id = 798, .cpu_id = 231, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC0_SPI" }, + { .fc_id = 799, .cpu_id = 232, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC1_SPI" }, + { .fc_id = 800, .cpu_id = 233, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC0_SPI" }, + { .fc_id = 801, .cpu_id = 234, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC1_SPI" }, + { .fc_id = 802, .cpu_id = 235, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 803, .cpu_id = 236, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 804, .cpu_id = 237, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 805, .cpu_id = 238, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 806, .cpu_id = 239, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 807, .cpu_id = 240, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 808, .cpu_id = 241, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 809, .cpu_id = 242, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 810, .cpu_id = 243, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 811, .cpu_id = 244, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 812, .cpu_id = 245, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 813, .cpu_id = 246, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 814, .cpu_id = 247, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 815, .cpu_id = 248, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 816, .cpu_id = 249, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 817, .cpu_id = 250, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 818, .cpu_id = 251, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 819, .cpu_id = 252, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 820, .cpu_id = 253, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 821, .cpu_id = 254, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 822, .cpu_id = 255, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 823, .cpu_id = 256, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 824, .cpu_id = 257, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 825, .cpu_id = 258, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 826, .cpu_id = 259, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 827, .cpu_id = 260, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 828, .cpu_id = 261, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 829, .cpu_id = 262, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 830, .cpu_id = 263, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 831, .cpu_id = 264, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 832, .cpu_id = 265, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 833, .cpu_id = 266, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 834, .cpu_id = 267, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 835, .cpu_id = 268, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 836, .cpu_id = 269, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 837, .cpu_id = 270, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 838, .cpu_id = 271, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 839, .cpu_id = 272, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 840, .cpu_id = 273, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 841, .cpu_id = 274, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 842, .cpu_id = 275, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 843, .cpu_id = 276, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 844, .cpu_id = 277, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 845, .cpu_id = 278, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 846, .cpu_id = 279, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 847, .cpu_id = 280, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 848, .cpu_id = 281, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 849, .cpu_id = 282, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 850, .cpu_id = 283, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 851, .cpu_id = 284, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 852, .cpu_id = 285, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 853, .cpu_id = 286, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 854, .cpu_id = 287, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 855, .cpu_id = 288, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 856, .cpu_id = 289, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 857, .cpu_id = 290, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 858, .cpu_id = 291, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 859, .cpu_id = 292, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 860, .cpu_id = 293, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 861, .cpu_id = 294, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 862, .cpu_id = 295, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 863, .cpu_id = 296, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 864, .cpu_id = 297, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 865, .cpu_id = 298, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 866, .cpu_id = 299, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 867, .cpu_id = 300, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 868, .cpu_id = 301, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 869, .cpu_id = 302, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 870, .cpu_id = 303, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 871, .cpu_id = 304, .valid = 1, + .msg = 0, .reset = 1, .name = "RPM_ERROR_OR_DRAIN" }, + { .fc_id = 872, .cpu_id = 305, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 873, .cpu_id = 306, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 874, .cpu_id = 307, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 875, .cpu_id = 308, .valid = 1, + .msg = 0, .reset = 0, .name = "RAZWI_OR_PID_MIN_MAX_INTERRUPT" }, + { .fc_id = 876, .cpu_id = 309, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 877, .cpu_id = 310, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 878, .cpu_id = 311, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 879, .cpu_id = 312, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 880, .cpu_id = 313, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 881, .cpu_id = 314, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 882, .cpu_id = 315, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 883, .cpu_id = 316, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 884, .cpu_id = 317, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 885, .cpu_id = 318, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 886, .cpu_id = 319, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 887, .cpu_id = 320, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 888, .cpu_id = 321, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 889, .cpu_id = 322, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 890, .cpu_id = 323, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 891, .cpu_id = 324, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 892, .cpu_id = 325, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 893, .cpu_id = 326, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 894, .cpu_id = 327, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 895, .cpu_id = 328, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 896, .cpu_id = 329, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_SPI" }, + { .fc_id = 897, .cpu_id = 329, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_BMON_SPMU" }, + { .fc_id = 898, .cpu_id = 330, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_SPI" }, + { .fc_id = 899, .cpu_id = 330, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_BMON_SPMU" }, + { .fc_id = 900, .cpu_id = 331, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_SPI" }, + { .fc_id = 901, .cpu_id = 331, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_BMON_SPMU" }, + { .fc_id = 902, .cpu_id = 332, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_SPI" }, + { .fc_id = 903, .cpu_id = 332, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_BMON_SPMU" }, + { .fc_id = 904, .cpu_id = 333, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_SPI" }, + { .fc_id = 905, .cpu_id = 333, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_BMON_SPMU" }, + { .fc_id = 906, .cpu_id = 334, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_SPI" }, + { .fc_id = 907, .cpu_id = 334, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_BMON_SPMU" }, + { .fc_id = 908, .cpu_id = 335, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_SPI" }, + { .fc_id = 909, .cpu_id = 335, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_BMON_SPMU" }, + { .fc_id = 910, .cpu_id = 336, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_SPI" }, + { .fc_id = 911, .cpu_id = 336, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_BMON_SPMU" }, + { .fc_id = 912, .cpu_id = 337, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_SPI" }, + { .fc_id = 913, .cpu_id = 337, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_BMON_SPMU" }, + { .fc_id = 914, .cpu_id = 338, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_SPI" }, + { .fc_id = 915, .cpu_id = 338, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_BMON_SPMU" }, + { .fc_id = 916, .cpu_id = 339, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 917, .cpu_id = 340, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 918, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 919, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 920, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 921, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 922, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 923, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 924, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 925, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 926, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 927, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 928, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 929, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 930, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 931, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 932, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 933, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 934, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 935, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 936, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 937, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 938, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 939, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 940, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 941, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 942, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 943, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 944, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 945, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 946, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 947, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 948, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 949, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 950, .cpu_id = 342, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 951, .cpu_id = 343, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_BMON_SPMU" }, + { .fc_id = 952, .cpu_id = 343, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_SW_ERROR" }, + { .fc_id = 953, .cpu_id = 343, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 954, .cpu_id = 343, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 955, .cpu_id = 344, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_BMON_SPMU" }, + { .fc_id = 956, .cpu_id = 344, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_SW_ERROR" }, + { .fc_id = 957, .cpu_id = 344, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 958, .cpu_id = 344, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 959, .cpu_id = 345, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_BMON_SPMU" }, + { .fc_id = 960, .cpu_id = 345, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_SW_ERROR" }, + { .fc_id = 961, .cpu_id = 345, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 962, .cpu_id = 345, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 963, .cpu_id = 346, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_BMON_SPMU" }, + { .fc_id = 964, .cpu_id = 346, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_SW_ERROR" }, + { .fc_id = 965, .cpu_id = 346, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 966, .cpu_id = 346, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 967, .cpu_id = 347, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_BMON_SPMU" }, + { .fc_id = 968, .cpu_id = 347, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_SW_ERROR" }, + { .fc_id = 969, .cpu_id = 347, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 970, .cpu_id = 347, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 971, .cpu_id = 348, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_BMON_SPMU" }, + { .fc_id = 972, .cpu_id = 348, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_SW_ERROR" }, + { .fc_id = 973, .cpu_id = 348, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 974, .cpu_id = 348, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 975, .cpu_id = 349, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_BMON_SPMU" }, + { .fc_id = 976, .cpu_id = 349, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_SW_ERROR" }, + { .fc_id = 977, .cpu_id = 349, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 978, .cpu_id = 349, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 979, .cpu_id = 350, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_BMON_SPMU" }, + { .fc_id = 980, .cpu_id = 350, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_SW_ERROR" }, + { .fc_id = 981, .cpu_id = 350, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 982, .cpu_id = 350, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 983, .cpu_id = 351, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_BMON_SPMU" }, + { .fc_id = 984, .cpu_id = 351, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_SW_ERROR" }, + { .fc_id = 985, .cpu_id = 351, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 986, .cpu_id = 351, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 987, .cpu_id = 352, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_BMON_SPMU" }, + { .fc_id = 988, .cpu_id = 352, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_SW_ERROR" }, + { .fc_id = 989, .cpu_id = 352, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 990, .cpu_id = 352, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 991, .cpu_id = 353, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_BMON_SPMU" }, + { .fc_id = 992, .cpu_id = 353, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_SW_ERROR" }, + { .fc_id = 993, .cpu_id = 353, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 994, .cpu_id = 353, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 995, .cpu_id = 354, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_BMON_SPMU" }, + { .fc_id = 996, .cpu_id = 354, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_SW_ERROR" }, + { .fc_id = 997, .cpu_id = 354, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 998, .cpu_id = 354, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 999, .cpu_id = 355, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1000, .cpu_id = 356, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1001, .cpu_id = 357, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1002, .cpu_id = 358, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1003, .cpu_id = 359, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1004, .cpu_id = 360, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1005, .cpu_id = 361, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1006, .cpu_id = 362, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1007, .cpu_id = 363, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1008, .cpu_id = 368, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1009, .cpu_id = 369, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1010, .cpu_id = 366, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1011, .cpu_id = 367, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1012, .cpu_id = 364, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1013, .cpu_id = 365, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1014, .cpu_id = 374, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1015, .cpu_id = 375, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1016, .cpu_id = 372, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1017, .cpu_id = 373, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1018, .cpu_id = 370, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1019, .cpu_id = 371, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1020, .cpu_id = 376, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1021, .cpu_id = 377, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1022, .cpu_id = 378, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1023, .cpu_id = 379, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1024, .cpu_id = 380, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1025, .cpu_id = 381, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1026, .cpu_id = 382, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1027, .cpu_id = 383, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1028, .cpu_id = 384, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1029, .cpu_id = 385, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1030, .cpu_id = 386, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1031, .cpu_id = 387, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1032, .cpu_id = 388, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1033, .cpu_id = 389, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1034, .cpu_id = 390, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1035, .cpu_id = 391, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1036, .cpu_id = 392, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1037, .cpu_id = 393, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1038, .cpu_id = 394, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1039, .cpu_id = 395, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1040, .cpu_id = 396, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1041, .cpu_id = 397, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1042, .cpu_id = 398, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1043, .cpu_id = 399, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1044, .cpu_id = 400, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1045, .cpu_id = 401, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1046, .cpu_id = 402, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1047, .cpu_id = 403, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1048, .cpu_id = 404, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1049, .cpu_id = 405, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1050, .cpu_id = 406, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1051, .cpu_id = 407, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1052, .cpu_id = 408, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1053, .cpu_id = 409, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1054, .cpu_id = 410, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1055, .cpu_id = 411, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1056, .cpu_id = 412, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1057, .cpu_id = 413, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1058, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1059, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1060, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1061, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1062, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1063, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1064, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1065, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1066, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1067, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1068, .cpu_id = 415, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1069, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1070, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1071, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1072, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1073, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1074, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1075, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1076, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1077, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1078, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1079, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1080, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1081, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1082, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1083, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1084, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1085, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1086, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1087, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1088, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1089, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1090, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1091, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1092, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1093, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1094, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1095, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1096, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1097, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1098, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1099, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1100, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1101, .cpu_id = 418, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1102, .cpu_id = 419, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1103, .cpu_id = 420, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1104, .cpu_id = 421, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1105, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1106, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1107, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1108, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1109, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1110, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1111, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1112, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1113, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1114, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1115, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1116, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1117, .cpu_id = 423, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1118, .cpu_id = 424, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR0_SERR" }, + { .fc_id = 1119, .cpu_id = 425, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR1_SERR" }, + { .fc_id = 1120, .cpu_id = 426, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR0_DERR" }, + { .fc_id = 1121, .cpu_id = 427, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR1_DERR" }, + { .fc_id = 1122, .cpu_id = 428, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR0_AXI_ERROR_RESPONSE" }, + { .fc_id = 1123, .cpu_id = 429, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR1_AXI_ERROR_RESPONSE" }, + { .fc_id = 1124, .cpu_id = 430, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1125, .cpu_id = 431, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1126, .cpu_id = 432, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR0_BMON_SPMU" }, + { .fc_id = 1127, .cpu_id = 433, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1128, .cpu_id = 434, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR1_BMON_SPMU" }, + { .fc_id = 1129, .cpu_id = 435, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1130, .cpu_id = 436, .valid = 1, + .msg = 0, .reset = 0, .name = "SM0_BMON_SPMU" }, + { .fc_id = 1131, .cpu_id = 437, .valid = 1, + .msg = 0, .reset = 0, .name = "SM1_BMON_SPMU" }, + { .fc_id = 1132, .cpu_id = 438, .valid = 1, + .msg = 0, .reset = 0, .name = "SM2_BMON_SPMU" }, + { .fc_id = 1133, .cpu_id = 439, .valid = 1, + .msg = 0, .reset = 0, .name = "SM3_BMON_SPMU" }, + { .fc_id = 1134, .cpu_id = 440, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1135, .cpu_id = 441, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1136, .cpu_id = 442, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1137, .cpu_id = 443, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1138, .cpu_id = 444, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1139, .cpu_id = 445, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1140, .cpu_id = 446, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1141, .cpu_id = 447, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1142, .cpu_id = 448, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1143, .cpu_id = 449, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1144, .cpu_id = 450, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1145, .cpu_id = 451, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1146, .cpu_id = 452, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1147, .cpu_id = 453, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1148, .cpu_id = 454, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1149, .cpu_id = 455, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1150, .cpu_id = 456, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1151, .cpu_id = 457, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1152, .cpu_id = 458, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1153, .cpu_id = 459, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1154, .cpu_id = 460, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1155, .cpu_id = 461, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1156, .cpu_id = 462, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1157, .cpu_id = 463, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1158, .cpu_id = 464, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1159, .cpu_id = 465, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1160, .cpu_id = 466, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1161, .cpu_id = 467, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1162, .cpu_id = 468, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1163, .cpu_id = 469, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1164, .cpu_id = 470, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1165, .cpu_id = 471, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1166, .cpu_id = 472, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1167, .cpu_id = 473, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1168, .cpu_id = 474, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1169, .cpu_id = 475, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1170, .cpu_id = 476, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1171, .cpu_id = 477, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1172, .cpu_id = 478, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1173, .cpu_id = 479, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1174, .cpu_id = 480, .valid = 1, + .msg = 1, .reset = 0, .name = "PSOC_DMA_QM" }, + { .fc_id = 1175, .cpu_id = 481, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1176, .cpu_id = 482, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1177, .cpu_id = 483, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1178, .cpu_id = 484, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1179, .cpu_id = 485, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1180, .cpu_id = 486, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1181, .cpu_id = 487, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1182, .cpu_id = 488, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1183, .cpu_id = 489, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1184, .cpu_id = 490, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1185, .cpu_id = 491, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1186, .cpu_id = 492, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1187, .cpu_id = 493, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1188, .cpu_id = 494, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1189, .cpu_id = 495, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1190, .cpu_id = 496, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1191, .cpu_id = 497, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1192, .cpu_id = 498, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1193, .cpu_id = 499, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1194, .cpu_id = 500, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1195, .cpu_id = 501, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1196, .cpu_id = 502, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1197, .cpu_id = 503, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1198, .cpu_id = 504, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1199, .cpu_id = 505, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1200, .cpu_id = 506, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1201, .cpu_id = 507, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1202, .cpu_id = 508, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1203, .cpu_id = 509, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1204, .cpu_id = 510, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1205, .cpu_id = 511, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1206, .cpu_id = 512, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC0_QM" }, + { .fc_id = 1207, .cpu_id = 513, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC1_QM" }, + { .fc_id = 1208, .cpu_id = 514, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC2_QM" }, + { .fc_id = 1209, .cpu_id = 515, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC3_QM" }, + { .fc_id = 1210, .cpu_id = 516, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC4_QM" }, + { .fc_id = 1211, .cpu_id = 517, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC5_QM" }, + { .fc_id = 1212, .cpu_id = 518, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC6_QM" }, + { .fc_id = 1213, .cpu_id = 519, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC7_QM" }, + { .fc_id = 1214, .cpu_id = 520, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC8_QM" }, + { .fc_id = 1215, .cpu_id = 521, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC9_QM" }, + { .fc_id = 1216, .cpu_id = 522, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC10_QM" }, + { .fc_id = 1217, .cpu_id = 523, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC11_QM" }, + { .fc_id = 1218, .cpu_id = 524, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC12_QM" }, + { .fc_id = 1219, .cpu_id = 525, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC13_QM" }, + { .fc_id = 1220, .cpu_id = 526, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC14_QM" }, + { .fc_id = 1221, .cpu_id = 527, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC15_QM" }, + { .fc_id = 1222, .cpu_id = 528, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC16_QM" }, + { .fc_id = 1223, .cpu_id = 529, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC17_QM" }, + { .fc_id = 1224, .cpu_id = 530, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC18_QM" }, + { .fc_id = 1225, .cpu_id = 531, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC19_QM" }, + { .fc_id = 1226, .cpu_id = 532, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC20_QM" }, + { .fc_id = 1227, .cpu_id = 533, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC21_QM" }, + { .fc_id = 1228, .cpu_id = 534, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC22_QM" }, + { .fc_id = 1229, .cpu_id = 535, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC23_QM" }, + { .fc_id = 1230, .cpu_id = 536, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC24_QM" }, + { .fc_id = 1231, .cpu_id = 537, .valid = 0, + .msg = 1, .reset = 0, .name = "" }, + { .fc_id = 1232, .cpu_id = 538, .valid = 1, + .msg = 1, .reset = 0, .name = "MME0_QM" }, + { .fc_id = 1233, .cpu_id = 539, .valid = 1, + .msg = 1, .reset = 0, .name = "MME1_QM" }, + { .fc_id = 1234, .cpu_id = 540, .valid = 1, + .msg = 1, .reset = 0, .name = "MME2_QM" }, + { .fc_id = 1235, .cpu_id = 541, .valid = 1, + .msg = 1, .reset = 0, .name = "MME3_QM" }, + { .fc_id = 1236, .cpu_id = 542, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA2_QM" }, + { .fc_id = 1237, .cpu_id = 543, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA3_QM" }, + { .fc_id = 1238, .cpu_id = 544, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA0_QM" }, + { .fc_id = 1239, .cpu_id = 545, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA1_QM" }, + { .fc_id = 1240, .cpu_id = 546, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA6_QM" }, + { .fc_id = 1241, .cpu_id = 547, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA7_QM" }, + { .fc_id = 1242, .cpu_id = 548, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA4_QM" }, + { .fc_id = 1243, .cpu_id = 549, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA5_QM" }, + { .fc_id = 1244, .cpu_id = 550, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA0_QM" }, + { .fc_id = 1245, .cpu_id = 551, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA1_QM" }, + { .fc_id = 1246, .cpu_id = 552, .valid = 1, + .msg = 1, .reset = 0, .name = "PI_UPDATE" }, + { .fc_id = 1247, .cpu_id = 553, .valid = 1, + .msg = 1, .reset = 0, .name = "HALT_MACHINE" }, + { .fc_id = 1248, .cpu_id = 554, .valid = 1, + .msg = 1, .reset = 0, .name = "INTS_REGISTER" }, + { .fc_id = 1249, .cpu_id = 555, .valid = 1, + .msg = 1, .reset = 0, .name = "ROT0_QM" }, + { .fc_id = 1250, .cpu_id = 556, .valid = 1, + .msg = 1, .reset = 0, .name = "ROT1_QM" }, + { .fc_id = 1251, .cpu_id = 557, .valid = 1, + .msg = 1, .reset = 0, .name = "SOFT_RESET" }, + { .fc_id = 1252, .cpu_id = 558, .valid = 1, + .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_CAUSE" }, + { .fc_id = 1253, .cpu_id = 559, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_S" }, + { .fc_id = 1254, .cpu_id = 560, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_E" }, + { .fc_id = 1255, .cpu_id = 561, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 1256, .cpu_id = 562, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 1257, .cpu_id = 563, .valid = 1, + .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_EVENT" }, + { .fc_id = 1258, .cpu_id = 564, .valid = 1, + .msg = 1, .reset = 0, .name = "PKT_QUEUE_OUT_SYNC" }, + { .fc_id = 1259, .cpu_id = 565, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA2_CORE" }, + { .fc_id = 1260, .cpu_id = 566, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA3_CORE" }, + { .fc_id = 1261, .cpu_id = 567, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA0_CORE" }, + { .fc_id = 1262, .cpu_id = 568, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA1_CORE" }, + { .fc_id = 1263, .cpu_id = 569, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA6_CORE" }, + { .fc_id = 1264, .cpu_id = 570, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA7_CORE" }, + { .fc_id = 1265, .cpu_id = 571, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA4_CORE" }, + { .fc_id = 1266, .cpu_id = 572, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA5_CORE" }, + { .fc_id = 1267, .cpu_id = 573, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA0_CORE" }, + { .fc_id = 1268, .cpu_id = 574, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA1_CORE" }, + { .fc_id = 1269, .cpu_id = 575, .valid = 1, + .msg = 1, .reset = 0, .name = "KDMA0_CORE" }, + { .fc_id = 1270, .cpu_id = 576, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC0_QM0" }, + { .fc_id = 1271, .cpu_id = 577, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC0_QM1" }, + { .fc_id = 1272, .cpu_id = 578, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC1_QM0" }, + { .fc_id = 1273, .cpu_id = 579, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC1_QM1" }, + { .fc_id = 1274, .cpu_id = 580, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC2_QM0" }, + { .fc_id = 1275, .cpu_id = 581, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC2_QM1" }, + { .fc_id = 1276, .cpu_id = 582, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC3_QM0" }, + { .fc_id = 1277, .cpu_id = 583, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC3_QM1" }, + { .fc_id = 1278, .cpu_id = 584, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC4_QM0" }, + { .fc_id = 1279, .cpu_id = 585, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC4_QM1" }, + { .fc_id = 1280, .cpu_id = 586, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC5_QM0" }, + { .fc_id = 1281, .cpu_id = 587, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC5_QM1" }, + { .fc_id = 1282, .cpu_id = 588, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC6_QM0" }, + { .fc_id = 1283, .cpu_id = 589, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC6_QM1" }, + { .fc_id = 1284, .cpu_id = 590, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC7_QM0" }, + { .fc_id = 1285, .cpu_id = 591, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC7_QM1" }, + { .fc_id = 1286, .cpu_id = 592, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC8_QM0" }, + { .fc_id = 1287, .cpu_id = 593, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC8_QM1" }, + { .fc_id = 1288, .cpu_id = 594, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC9_QM0" }, + { .fc_id = 1289, .cpu_id = 595, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC9_QM1" }, + { .fc_id = 1290, .cpu_id = 596, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC10_QM0" }, + { .fc_id = 1291, .cpu_id = 597, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC10_QM1" }, + { .fc_id = 1292, .cpu_id = 598, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC11_QM0" }, + { .fc_id = 1293, .cpu_id = 599, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC11_QM1" }, + { .fc_id = 1294, .cpu_id = 600, .valid = 1, + .msg = 1, .reset = 0, .name = "CPU_PKT_SANITY_FAILED" }, + { .fc_id = 1295, .cpu_id = 601, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG0" }, + { .fc_id = 1296, .cpu_id = 602, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG1" }, + { .fc_id = 1297, .cpu_id = 603, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG0" }, + { .fc_id = 1298, .cpu_id = 604, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG1" }, + { .fc_id = 1299, .cpu_id = 605, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG0" }, + { .fc_id = 1300, .cpu_id = 606, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG1" }, + { .fc_id = 1301, .cpu_id = 607, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG0" }, + { .fc_id = 1302, .cpu_id = 608, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG1" }, + { .fc_id = 1303, .cpu_id = 609, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG0" }, + { .fc_id = 1304, .cpu_id = 610, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG1" }, + { .fc_id = 1305, .cpu_id = 611, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG0" }, + { .fc_id = 1306, .cpu_id = 612, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG1" }, + { .fc_id = 1307, .cpu_id = 613, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG0" }, + { .fc_id = 1308, .cpu_id = 614, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG1" }, + { .fc_id = 1309, .cpu_id = 615, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG0" }, + { .fc_id = 1310, .cpu_id = 616, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG1" }, + { .fc_id = 1311, .cpu_id = 617, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG0" }, + { .fc_id = 1312, .cpu_id = 618, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG1" }, + { .fc_id = 1313, .cpu_id = 619, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG0" }, + { .fc_id = 1314, .cpu_id = 620, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG1" }, + { .fc_id = 1315, .cpu_id = 621, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG0" }, + { .fc_id = 1316, .cpu_id = 622, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG1" }, + { .fc_id = 1317, .cpu_id = 623, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG0" }, + { .fc_id = 1318, .cpu_id = 624, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG1" }, + { .fc_id = 1319, .cpu_id = 625, .valid = 1, + .msg = 1, .reset = 0, .name = "ARC_DCCM_FULL" }, +}; + +#endif /* __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h new file mode 100644 index 000000000..14f09d775 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h @@ -0,0 +1,984 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_CORESIGHT_H +#define GAUDI2_CORESIGHT_H + +enum gaudi2_debug_stm_regs_index { + GAUDI2_STM_FIRST = 0, + GAUDI2_STM_DCORE0_TPC0_EML = GAUDI2_STM_FIRST, + GAUDI2_STM_DCORE0_TPC1_EML, + GAUDI2_STM_DCORE0_TPC2_EML, + GAUDI2_STM_DCORE0_TPC3_EML, + GAUDI2_STM_DCORE0_TPC4_EML, + GAUDI2_STM_DCORE0_TPC5_EML, + GAUDI2_STM_DCORE0_TPC6_EML, + GAUDI2_STM_DCORE1_TPC0_EML, + GAUDI2_STM_DCORE1_TPC1_EML, + GAUDI2_STM_DCORE1_TPC2_EML, + GAUDI2_STM_DCORE1_TPC3_EML, + GAUDI2_STM_DCORE1_TPC4_EML, + GAUDI2_STM_DCORE1_TPC5_EML, + GAUDI2_STM_DCORE2_TPC0_EML, + GAUDI2_STM_DCORE2_TPC1_EML, + GAUDI2_STM_DCORE2_TPC2_EML, + GAUDI2_STM_DCORE2_TPC3_EML, + GAUDI2_STM_DCORE2_TPC4_EML, + GAUDI2_STM_DCORE2_TPC5_EML, + GAUDI2_STM_DCORE3_TPC0_EML, + GAUDI2_STM_DCORE3_TPC1_EML, + GAUDI2_STM_DCORE3_TPC2_EML, + GAUDI2_STM_DCORE3_TPC3_EML, + GAUDI2_STM_DCORE3_TPC4_EML, + GAUDI2_STM_DCORE3_TPC5_EML, + GAUDI2_STM_DCORE0_HMMU0_CS, + GAUDI2_STM_DCORE0_HMMU1_CS, + GAUDI2_STM_DCORE0_HMMU2_CS, + GAUDI2_STM_DCORE0_HMMU3_CS, + GAUDI2_STM_DCORE0_MME_CTRL, + GAUDI2_STM_DCORE0_MME_SBTE0, + GAUDI2_STM_DCORE0_MME_SBTE1, + GAUDI2_STM_DCORE0_MME_SBTE2, + GAUDI2_STM_DCORE0_MME_SBTE3, + GAUDI2_STM_DCORE0_MME_SBTE4, + GAUDI2_STM_DCORE0_MME_ACC, + GAUDI2_STM_DCORE0_SM, + GAUDI2_STM_DCORE0_EDMA0_CS, + GAUDI2_STM_DCORE0_EDMA1_CS, + GAUDI2_STM_DCORE0_VDEC0_CS, + GAUDI2_STM_DCORE0_VDEC1_CS, + GAUDI2_STM_DCORE1_HMMU0_CS, + GAUDI2_STM_DCORE1_HMMU1_CS, + GAUDI2_STM_DCORE1_HMMU2_CS, + GAUDI2_STM_DCORE1_HMMU3_CS, + GAUDI2_STM_DCORE1_MME_CTRL, + GAUDI2_STM_DCORE1_MME_SBTE0, + GAUDI2_STM_DCORE1_MME_SBTE1, + GAUDI2_STM_DCORE1_MME_SBTE2, + GAUDI2_STM_DCORE1_MME_SBTE3, + GAUDI2_STM_DCORE1_MME_SBTE4, + GAUDI2_STM_DCORE1_MME_ACC, + GAUDI2_STM_DCORE1_SM, + GAUDI2_STM_DCORE1_EDMA0_CS, + GAUDI2_STM_DCORE1_EDMA1_CS, + GAUDI2_STM_DCORE1_VDEC0_CS, + GAUDI2_STM_DCORE1_VDEC1_CS, + GAUDI2_STM_DCORE2_HMMU0_CS, + GAUDI2_STM_DCORE2_HMMU1_CS, + GAUDI2_STM_DCORE2_HMMU2_CS, + GAUDI2_STM_DCORE2_HMMU3_CS, + GAUDI2_STM_DCORE2_MME_CTRL, + GAUDI2_STM_DCORE2_MME_SBTE0, + GAUDI2_STM_DCORE2_MME_SBTE1, + GAUDI2_STM_DCORE2_MME_SBTE2, + GAUDI2_STM_DCORE2_MME_SBTE3, + GAUDI2_STM_DCORE2_MME_SBTE4, + GAUDI2_STM_DCORE2_MME_ACC, + GAUDI2_STM_DCORE2_SM, + GAUDI2_STM_DCORE2_EDMA0_CS, + GAUDI2_STM_DCORE2_EDMA1_CS, + GAUDI2_STM_DCORE2_VDEC0_CS, + GAUDI2_STM_DCORE2_VDEC1_CS, + GAUDI2_STM_DCORE3_HMMU0_CS, + GAUDI2_STM_DCORE3_HMMU1_CS, + GAUDI2_STM_DCORE3_HMMU2_CS, + GAUDI2_STM_DCORE3_HMMU3_CS, + GAUDI2_STM_DCORE3_MME_CTRL, + GAUDI2_STM_DCORE3_MME_SBTE0, + GAUDI2_STM_DCORE3_MME_SBTE1, + GAUDI2_STM_DCORE3_MME_SBTE2, + GAUDI2_STM_DCORE3_MME_SBTE3, + GAUDI2_STM_DCORE3_MME_SBTE4, + GAUDI2_STM_DCORE3_MME_ACC, + GAUDI2_STM_DCORE3_SM, + GAUDI2_STM_DCORE3_EDMA0_CS, + GAUDI2_STM_DCORE3_EDMA1_CS, + GAUDI2_STM_DCORE3_VDEC0_CS, + GAUDI2_STM_DCORE3_VDEC1_CS, + GAUDI2_STM_PCIE, + GAUDI2_STM_PSOC, + GAUDI2_STM_PSOC_ARC0_CS, + GAUDI2_STM_PSOC_ARC1_CS, + GAUDI2_STM_PDMA0_CS, + GAUDI2_STM_PDMA1_CS, + GAUDI2_STM_CPU, + GAUDI2_STM_PMMU_CS, + GAUDI2_STM_ROT0_CS, + GAUDI2_STM_ROT1_CS, + GAUDI2_STM_ARC_FARM_CS, + GAUDI2_STM_KDMA_CS, + GAUDI2_STM_PCIE_VDEC0_CS, + GAUDI2_STM_PCIE_VDEC1_CS, + GAUDI2_STM_HBM0_MC0_CS, + GAUDI2_STM_HBM0_MC1_CS, + GAUDI2_STM_HBM1_MC0_CS, + GAUDI2_STM_HBM1_MC1_CS, + GAUDI2_STM_HBM2_MC0_CS, + GAUDI2_STM_HBM2_MC1_CS, + GAUDI2_STM_HBM3_MC0_CS, + GAUDI2_STM_HBM3_MC1_CS, + GAUDI2_STM_HBM4_MC0_CS, + GAUDI2_STM_HBM4_MC1_CS, + GAUDI2_STM_HBM5_MC0_CS, + GAUDI2_STM_HBM5_MC1_CS, + GAUDI2_STM_NIC0_DBG_0, + GAUDI2_STM_NIC0_DBG_1, + GAUDI2_STM_NIC1_DBG_0, + GAUDI2_STM_NIC1_DBG_1, + GAUDI2_STM_NIC2_DBG_0, + GAUDI2_STM_NIC2_DBG_1, + GAUDI2_STM_NIC3_DBG_0, + GAUDI2_STM_NIC3_DBG_1, + GAUDI2_STM_NIC4_DBG_0, + GAUDI2_STM_NIC4_DBG_1, + GAUDI2_STM_NIC5_DBG_0, + GAUDI2_STM_NIC5_DBG_1, + GAUDI2_STM_NIC6_DBG_0, + GAUDI2_STM_NIC6_DBG_1, + GAUDI2_STM_NIC7_DBG_0, + GAUDI2_STM_NIC7_DBG_1, + GAUDI2_STM_NIC8_DBG_0, + GAUDI2_STM_NIC8_DBG_1, + GAUDI2_STM_NIC9_DBG_0, + GAUDI2_STM_NIC9_DBG_1, + GAUDI2_STM_NIC10_DBG_0, + GAUDI2_STM_NIC10_DBG_1, + GAUDI2_STM_NIC11_DBG_0, + GAUDI2_STM_NIC11_DBG_1, + GAUDI2_STM_LAST = GAUDI2_STM_NIC11_DBG_1 +}; + +enum gaudi2_debug_etf_regs_index { + GAUDI2_ETF_FIRST = 0, + GAUDI2_ETF_DCORE0_TPC0_EML = GAUDI2_ETF_FIRST, + GAUDI2_ETF_DCORE0_TPC1_EML, + GAUDI2_ETF_DCORE0_TPC2_EML, + GAUDI2_ETF_DCORE0_TPC3_EML, + GAUDI2_ETF_DCORE0_TPC4_EML, + GAUDI2_ETF_DCORE0_TPC5_EML, + GAUDI2_ETF_DCORE0_TPC6_EML, + GAUDI2_ETF_DCORE1_TPC0_EML, + GAUDI2_ETF_DCORE1_TPC1_EML, + GAUDI2_ETF_DCORE1_TPC2_EML, + GAUDI2_ETF_DCORE1_TPC3_EML, + GAUDI2_ETF_DCORE1_TPC4_EML, + GAUDI2_ETF_DCORE1_TPC5_EML, + GAUDI2_ETF_DCORE2_TPC0_EML, + GAUDI2_ETF_DCORE2_TPC1_EML, + GAUDI2_ETF_DCORE2_TPC2_EML, + GAUDI2_ETF_DCORE2_TPC3_EML, + GAUDI2_ETF_DCORE2_TPC4_EML, + GAUDI2_ETF_DCORE2_TPC5_EML, + GAUDI2_ETF_DCORE3_TPC0_EML, + GAUDI2_ETF_DCORE3_TPC1_EML, + GAUDI2_ETF_DCORE3_TPC2_EML, + GAUDI2_ETF_DCORE3_TPC3_EML, + GAUDI2_ETF_DCORE3_TPC4_EML, + GAUDI2_ETF_DCORE3_TPC5_EML, + GAUDI2_ETF_DCORE0_HMMU0_CS, + GAUDI2_ETF_DCORE0_HMMU1_CS, + GAUDI2_ETF_DCORE0_HMMU2_CS, + GAUDI2_ETF_DCORE0_HMMU3_CS, + GAUDI2_ETF_DCORE0_MME_CTRL, + GAUDI2_ETF_DCORE0_MME_SBTE0, + GAUDI2_ETF_DCORE0_MME_SBTE1, + GAUDI2_ETF_DCORE0_MME_SBTE2, + GAUDI2_ETF_DCORE0_MME_SBTE3, + GAUDI2_ETF_DCORE0_MME_SBTE4, + GAUDI2_ETF_DCORE0_MME_ACC, + GAUDI2_ETF_DCORE0_SM, + GAUDI2_ETF_DCORE0_EDMA0_CS, + GAUDI2_ETF_DCORE0_EDMA1_CS, + GAUDI2_ETF_DCORE0_VDEC0_CS, + GAUDI2_ETF_DCORE0_VDEC1_CS, + GAUDI2_ETF_DCORE1_HMMU0_CS, + GAUDI2_ETF_DCORE1_HMMU1_CS, + GAUDI2_ETF_DCORE1_HMMU2_CS, + GAUDI2_ETF_DCORE1_HMMU3_CS, + GAUDI2_ETF_DCORE1_MME_CTRL, + GAUDI2_ETF_DCORE1_MME_SBTE0, + GAUDI2_ETF_DCORE1_MME_SBTE1, + GAUDI2_ETF_DCORE1_MME_SBTE2, + GAUDI2_ETF_DCORE1_MME_SBTE3, + GAUDI2_ETF_DCORE1_MME_SBTE4, + GAUDI2_ETF_DCORE1_MME_ACC, + GAUDI2_ETF_DCORE1_SM, + GAUDI2_ETF_DCORE1_EDMA0_CS, + GAUDI2_ETF_DCORE1_EDMA1_CS, + GAUDI2_ETF_DCORE1_VDEC0_CS, + GAUDI2_ETF_DCORE1_VDEC1_CS, + GAUDI2_ETF_DCORE2_HMMU0_CS, + GAUDI2_ETF_DCORE2_HMMU1_CS, + GAUDI2_ETF_DCORE2_HMMU2_CS, + GAUDI2_ETF_DCORE2_HMMU3_CS, + GAUDI2_ETF_DCORE2_MME_CTRL, + GAUDI2_ETF_DCORE2_MME_SBTE0, + GAUDI2_ETF_DCORE2_MME_SBTE1, + GAUDI2_ETF_DCORE2_MME_SBTE2, + GAUDI2_ETF_DCORE2_MME_SBTE3, + GAUDI2_ETF_DCORE2_MME_SBTE4, + GAUDI2_ETF_DCORE2_MME_ACC, + GAUDI2_ETF_DCORE2_SM, + GAUDI2_ETF_DCORE2_EDMA0_CS, + GAUDI2_ETF_DCORE2_EDMA1_CS, + GAUDI2_ETF_DCORE2_VDEC0_CS, + GAUDI2_ETF_DCORE2_VDEC1_CS, + GAUDI2_ETF_DCORE3_HMMU0_CS, + GAUDI2_ETF_DCORE3_HMMU1_CS, + GAUDI2_ETF_DCORE3_HMMU2_CS, + GAUDI2_ETF_DCORE3_HMMU3_CS, + GAUDI2_ETF_DCORE3_MME_CTRL, + GAUDI2_ETF_DCORE3_MME_SBTE0, + GAUDI2_ETF_DCORE3_MME_SBTE1, + GAUDI2_ETF_DCORE3_MME_SBTE2, + GAUDI2_ETF_DCORE3_MME_SBTE3, + GAUDI2_ETF_DCORE3_MME_SBTE4, + GAUDI2_ETF_DCORE3_MME_ACC, + GAUDI2_ETF_DCORE3_SM, + GAUDI2_ETF_DCORE3_EDMA0_CS, + GAUDI2_ETF_DCORE3_EDMA1_CS, + GAUDI2_ETF_DCORE3_VDEC0_CS, + GAUDI2_ETF_DCORE3_VDEC1_CS, + GAUDI2_ETF_PCIE, + GAUDI2_ETF_PSOC, + GAUDI2_ETF_PSOC_ARC0_CS, + GAUDI2_ETF_PSOC_ARC1_CS, + GAUDI2_ETF_PDMA0_CS, + GAUDI2_ETF_PDMA1_CS, + GAUDI2_ETF_CPU_0, + GAUDI2_ETF_CPU_1, + GAUDI2_ETF_CPU_TRACE, + GAUDI2_ETF_PMMU_CS, + GAUDI2_ETF_ROT0_CS, + GAUDI2_ETF_ROT1_CS, + GAUDI2_ETF_ARC_FARM_CS, + GAUDI2_ETF_KDMA_CS, + GAUDI2_ETF_PCIE_VDEC0_CS, + GAUDI2_ETF_PCIE_VDEC1_CS, + GAUDI2_ETF_HBM0_MC0_CS, + GAUDI2_ETF_HBM0_MC1_CS, + GAUDI2_ETF_HBM1_MC0_CS, + GAUDI2_ETF_HBM1_MC1_CS, + GAUDI2_ETF_HBM2_MC0_CS, + GAUDI2_ETF_HBM2_MC1_CS, + GAUDI2_ETF_HBM3_MC0_CS, + GAUDI2_ETF_HBM3_MC1_CS, + GAUDI2_ETF_HBM4_MC0_CS, + GAUDI2_ETF_HBM4_MC1_CS, + GAUDI2_ETF_HBM5_MC0_CS, + GAUDI2_ETF_HBM5_MC1_CS, + GAUDI2_ETF_NIC0_DBG_0, + GAUDI2_ETF_NIC0_DBG_1, + GAUDI2_ETF_NIC1_DBG_0, + GAUDI2_ETF_NIC1_DBG_1, + GAUDI2_ETF_NIC2_DBG_0, + GAUDI2_ETF_NIC2_DBG_1, + GAUDI2_ETF_NIC3_DBG_0, + GAUDI2_ETF_NIC3_DBG_1, + GAUDI2_ETF_NIC4_DBG_0, + GAUDI2_ETF_NIC4_DBG_1, + GAUDI2_ETF_NIC5_DBG_0, + GAUDI2_ETF_NIC5_DBG_1, + GAUDI2_ETF_NIC6_DBG_0, + GAUDI2_ETF_NIC6_DBG_1, + GAUDI2_ETF_NIC7_DBG_0, + GAUDI2_ETF_NIC7_DBG_1, + GAUDI2_ETF_NIC8_DBG_0, + GAUDI2_ETF_NIC8_DBG_1, + GAUDI2_ETF_NIC9_DBG_0, + GAUDI2_ETF_NIC9_DBG_1, + GAUDI2_ETF_NIC10_DBG_0, + GAUDI2_ETF_NIC10_DBG_1, + GAUDI2_ETF_NIC11_DBG_0, + GAUDI2_ETF_NIC11_DBG_1, + GAUDI2_ETF_LAST = GAUDI2_ETF_NIC11_DBG_1 +}; + +enum gaudi2_debug_funnel_regs_index { + GAUDI2_FUNNEL_FIRST = 0, + GAUDI2_FUNNEL_DCORE0_TPC0_EML = GAUDI2_FUNNEL_FIRST, + GAUDI2_FUNNEL_DCORE0_TPC1_EML, + GAUDI2_FUNNEL_DCORE0_TPC2_EML, + GAUDI2_FUNNEL_DCORE0_TPC3_EML, + GAUDI2_FUNNEL_DCORE0_TPC4_EML, + GAUDI2_FUNNEL_DCORE0_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_TPC6_EML, + GAUDI2_FUNNEL_DCORE1_TPC0_EML, + GAUDI2_FUNNEL_DCORE1_TPC1_EML, + GAUDI2_FUNNEL_DCORE1_TPC2_EML, + GAUDI2_FUNNEL_DCORE1_TPC3_EML, + GAUDI2_FUNNEL_DCORE1_TPC4_EML, + GAUDI2_FUNNEL_DCORE1_TPC5_EML, + GAUDI2_FUNNEL_DCORE2_TPC0_EML, + GAUDI2_FUNNEL_DCORE2_TPC1_EML, + GAUDI2_FUNNEL_DCORE2_TPC2_EML, + GAUDI2_FUNNEL_DCORE2_TPC3_EML, + GAUDI2_FUNNEL_DCORE2_TPC4_EML, + GAUDI2_FUNNEL_DCORE2_TPC5_EML, + GAUDI2_FUNNEL_DCORE3_TPC0_EML, + GAUDI2_FUNNEL_DCORE3_TPC1_EML, + GAUDI2_FUNNEL_DCORE3_TPC2_EML, + GAUDI2_FUNNEL_DCORE3_TPC3_EML, + GAUDI2_FUNNEL_DCORE3_TPC4_EML, + GAUDI2_FUNNEL_DCORE3_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_XFT, + GAUDI2_FUNNEL_DCORE0_TFT0, + GAUDI2_FUNNEL_DCORE0_TFT1, + GAUDI2_FUNNEL_DCORE0_TFT2, + GAUDI2_FUNNEL_DCORE0_RTR0, + GAUDI2_FUNNEL_DCORE0_RTR1, + GAUDI2_FUNNEL_DCORE0_RTR2, + GAUDI2_FUNNEL_DCORE0_RTR3, + GAUDI2_FUNNEL_DCORE0_RTR4, + GAUDI2_FUNNEL_DCORE0_MIF0, + GAUDI2_FUNNEL_DCORE0_RTR5, + GAUDI2_FUNNEL_DCORE0_MIF1, + GAUDI2_FUNNEL_DCORE0_RTR6, + GAUDI2_FUNNEL_DCORE0_MIF2, + GAUDI2_FUNNEL_DCORE0_RTR7, + GAUDI2_FUNNEL_DCORE0_MIF3, + GAUDI2_FUNNEL_DCORE1_XFT, + GAUDI2_FUNNEL_DCORE1_TFT0, + GAUDI2_FUNNEL_DCORE1_TFT1, + GAUDI2_FUNNEL_DCORE1_TFT2, + GAUDI2_FUNNEL_DCORE1_RTR0, + GAUDI2_FUNNEL_DCORE1_MIF0, + GAUDI2_FUNNEL_DCORE1_RTR1, + GAUDI2_FUNNEL_DCORE1_MIF1, + GAUDI2_FUNNEL_DCORE1_RTR2, + GAUDI2_FUNNEL_DCORE1_MIF2, + GAUDI2_FUNNEL_DCORE1_RTR3, + GAUDI2_FUNNEL_DCORE1_MIF3, + GAUDI2_FUNNEL_DCORE1_RTR4, + GAUDI2_FUNNEL_DCORE1_RTR5, + GAUDI2_FUNNEL_DCORE1_RTR6, + GAUDI2_FUNNEL_DCORE1_RTR7, + GAUDI2_FUNNEL_DCORE2_XFT, + GAUDI2_FUNNEL_DCORE2_TFT0, + GAUDI2_FUNNEL_DCORE2_TFT1, + GAUDI2_FUNNEL_DCORE2_TFT2, + GAUDI2_FUNNEL_DCORE2_RTR0, + GAUDI2_FUNNEL_DCORE2_RTR1, + GAUDI2_FUNNEL_DCORE2_RTR2, + GAUDI2_FUNNEL_DCORE2_RTR3, + GAUDI2_FUNNEL_DCORE2_RTR4, + GAUDI2_FUNNEL_DCORE2_MIF0, + GAUDI2_FUNNEL_DCORE2_RTR5, + GAUDI2_FUNNEL_DCORE2_MIF1, + GAUDI2_FUNNEL_DCORE2_RTR6, + GAUDI2_FUNNEL_DCORE2_MIF2, + GAUDI2_FUNNEL_DCORE2_RTR7, + GAUDI2_FUNNEL_DCORE2_MIF3, + GAUDI2_FUNNEL_DCORE3_XFT, + GAUDI2_FUNNEL_DCORE3_TFT0, + GAUDI2_FUNNEL_DCORE3_TFT1, + GAUDI2_FUNNEL_DCORE3_TFT2, + GAUDI2_FUNNEL_DCORE3_RTR0, + GAUDI2_FUNNEL_DCORE3_MIF0, + GAUDI2_FUNNEL_DCORE3_RTR1, + GAUDI2_FUNNEL_DCORE3_MIF1, + GAUDI2_FUNNEL_DCORE3_RTR2, + GAUDI2_FUNNEL_DCORE3_MIF2, + GAUDI2_FUNNEL_DCORE3_RTR3, + GAUDI2_FUNNEL_DCORE3_MIF3, + GAUDI2_FUNNEL_DCORE3_RTR4, + GAUDI2_FUNNEL_DCORE3_RTR5, + GAUDI2_FUNNEL_DCORE3_RTR6, + GAUDI2_FUNNEL_DCORE3_RTR7, + GAUDI2_FUNNEL_PSOC, + GAUDI2_FUNNEL_PSOC_ARC0, + GAUDI2_FUNNEL_PSOC_ARC1, + GAUDI2_FUNNEL_XDMA, + GAUDI2_FUNNEL_CPU, + GAUDI2_FUNNEL_PMMU, + GAUDI2_FUNNEL_PMMU_DEC, + GAUDI2_FUNNEL_DCORE0_XBAR_MID, + GAUDI2_FUNNEL_DCORE0_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE1_XBAR_MID, + GAUDI2_FUNNEL_DCORE1_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE2_XBAR_MID, + GAUDI2_FUNNEL_DCORE2_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE3_XBAR_MID, + GAUDI2_FUNNEL_DCORE3_XBAR_EDGE, + GAUDI2_FUNNEL_ARC_FARM, + GAUDI2_FUNNEL_HBM0_MC0, + GAUDI2_FUNNEL_HBM0_MC1, + GAUDI2_FUNNEL_HBM1_MC0, + GAUDI2_FUNNEL_HBM1_MC1, + GAUDI2_FUNNEL_HBM2_MC0, + GAUDI2_FUNNEL_HBM2_MC1, + GAUDI2_FUNNEL_HBM3_MC0, + GAUDI2_FUNNEL_HBM3_MC1, + GAUDI2_FUNNEL_HBM4_MC0, + GAUDI2_FUNNEL_HBM4_MC1, + GAUDI2_FUNNEL_HBM5_MC0, + GAUDI2_FUNNEL_HBM5_MC1, + GAUDI2_FUNNEL_NIC0_DBG_TX, + GAUDI2_FUNNEL_NIC0_DBG_NCH, + GAUDI2_FUNNEL_NIC1_DBG_TX, + GAUDI2_FUNNEL_NIC1_DBG_NCH, + GAUDI2_FUNNEL_NIC2_DBG_TX, + GAUDI2_FUNNEL_NIC2_DBG_NCH, + GAUDI2_FUNNEL_NIC3_DBG_TX, + GAUDI2_FUNNEL_NIC3_DBG_NCH, + GAUDI2_FUNNEL_NIC4_DBG_TX, + GAUDI2_FUNNEL_NIC4_DBG_NCH, + GAUDI2_FUNNEL_NIC5_DBG_TX, + GAUDI2_FUNNEL_NIC5_DBG_NCH, + GAUDI2_FUNNEL_NIC6_DBG_TX, + GAUDI2_FUNNEL_NIC6_DBG_NCH, + GAUDI2_FUNNEL_NIC7_DBG_TX, + GAUDI2_FUNNEL_NIC7_DBG_NCH, + GAUDI2_FUNNEL_NIC8_DBG_TX, + GAUDI2_FUNNEL_NIC8_DBG_NCH, + GAUDI2_FUNNEL_NIC9_DBG_TX, + GAUDI2_FUNNEL_NIC9_DBG_NCH, + GAUDI2_FUNNEL_NIC10_DBG_TX, + GAUDI2_FUNNEL_NIC10_DBG_NCH, + GAUDI2_FUNNEL_NIC11_DBG_TX, + GAUDI2_FUNNEL_NIC11_DBG_NCH, + GAUDI2_FUNNEL_LAST = GAUDI2_FUNNEL_NIC11_DBG_NCH +}; + +enum gaudi2_debug_bmon_regs_index { + GAUDI2_BMON_FIRST = 0, + GAUDI2_BMON_DCORE0_TPC0_EML_0 = GAUDI2_BMON_FIRST, + GAUDI2_BMON_DCORE0_TPC0_EML_1, + GAUDI2_BMON_DCORE0_TPC0_EML_2, + GAUDI2_BMON_DCORE0_TPC0_EML_3, + GAUDI2_BMON_DCORE0_TPC1_EML_0, + GAUDI2_BMON_DCORE0_TPC1_EML_1, + GAUDI2_BMON_DCORE0_TPC1_EML_2, + GAUDI2_BMON_DCORE0_TPC1_EML_3, + GAUDI2_BMON_DCORE0_TPC2_EML_0, + GAUDI2_BMON_DCORE0_TPC2_EML_1, + GAUDI2_BMON_DCORE0_TPC2_EML_2, + GAUDI2_BMON_DCORE0_TPC2_EML_3, + GAUDI2_BMON_DCORE0_TPC3_EML_0, + GAUDI2_BMON_DCORE0_TPC3_EML_1, + GAUDI2_BMON_DCORE0_TPC3_EML_2, + GAUDI2_BMON_DCORE0_TPC3_EML_3, + GAUDI2_BMON_DCORE0_TPC4_EML_0, + GAUDI2_BMON_DCORE0_TPC4_EML_1, + GAUDI2_BMON_DCORE0_TPC4_EML_2, + GAUDI2_BMON_DCORE0_TPC4_EML_3, + GAUDI2_BMON_DCORE0_TPC5_EML_0, + GAUDI2_BMON_DCORE0_TPC5_EML_1, + GAUDI2_BMON_DCORE0_TPC5_EML_2, + GAUDI2_BMON_DCORE0_TPC5_EML_3, + GAUDI2_BMON_DCORE0_TPC6_EML_0, + GAUDI2_BMON_DCORE0_TPC6_EML_1, + GAUDI2_BMON_DCORE0_TPC6_EML_2, + GAUDI2_BMON_DCORE0_TPC6_EML_3, + GAUDI2_BMON_DCORE1_TPC0_EML_0, + GAUDI2_BMON_DCORE1_TPC0_EML_1, + GAUDI2_BMON_DCORE1_TPC0_EML_2, + GAUDI2_BMON_DCORE1_TPC0_EML_3, + GAUDI2_BMON_DCORE1_TPC1_EML_0, + GAUDI2_BMON_DCORE1_TPC1_EML_1, + GAUDI2_BMON_DCORE1_TPC1_EML_2, + GAUDI2_BMON_DCORE1_TPC1_EML_3, + GAUDI2_BMON_DCORE1_TPC2_EML_0, + GAUDI2_BMON_DCORE1_TPC2_EML_1, + GAUDI2_BMON_DCORE1_TPC2_EML_2, + GAUDI2_BMON_DCORE1_TPC2_EML_3, + GAUDI2_BMON_DCORE1_TPC3_EML_0, + GAUDI2_BMON_DCORE1_TPC3_EML_1, + GAUDI2_BMON_DCORE1_TPC3_EML_2, + GAUDI2_BMON_DCORE1_TPC3_EML_3, + GAUDI2_BMON_DCORE1_TPC4_EML_0, + GAUDI2_BMON_DCORE1_TPC4_EML_1, + GAUDI2_BMON_DCORE1_TPC4_EML_2, + GAUDI2_BMON_DCORE1_TPC4_EML_3, + GAUDI2_BMON_DCORE1_TPC5_EML_0, + GAUDI2_BMON_DCORE1_TPC5_EML_1, + GAUDI2_BMON_DCORE1_TPC5_EML_2, + GAUDI2_BMON_DCORE1_TPC5_EML_3, + GAUDI2_BMON_DCORE2_TPC0_EML_0, + GAUDI2_BMON_DCORE2_TPC0_EML_1, + GAUDI2_BMON_DCORE2_TPC0_EML_2, + GAUDI2_BMON_DCORE2_TPC0_EML_3, + GAUDI2_BMON_DCORE2_TPC1_EML_0, + GAUDI2_BMON_DCORE2_TPC1_EML_1, + GAUDI2_BMON_DCORE2_TPC1_EML_2, + GAUDI2_BMON_DCORE2_TPC1_EML_3, + GAUDI2_BMON_DCORE2_TPC2_EML_0, + GAUDI2_BMON_DCORE2_TPC2_EML_1, + GAUDI2_BMON_DCORE2_TPC2_EML_2, + GAUDI2_BMON_DCORE2_TPC2_EML_3, + GAUDI2_BMON_DCORE2_TPC3_EML_0, + GAUDI2_BMON_DCORE2_TPC3_EML_1, + GAUDI2_BMON_DCORE2_TPC3_EML_2, + GAUDI2_BMON_DCORE2_TPC3_EML_3, + GAUDI2_BMON_DCORE2_TPC4_EML_0, + GAUDI2_BMON_DCORE2_TPC4_EML_1, + GAUDI2_BMON_DCORE2_TPC4_EML_2, + GAUDI2_BMON_DCORE2_TPC4_EML_3, + GAUDI2_BMON_DCORE2_TPC5_EML_0, + GAUDI2_BMON_DCORE2_TPC5_EML_1, + GAUDI2_BMON_DCORE2_TPC5_EML_2, + GAUDI2_BMON_DCORE2_TPC5_EML_3, + GAUDI2_BMON_DCORE3_TPC0_EML_0, + GAUDI2_BMON_DCORE3_TPC0_EML_1, + GAUDI2_BMON_DCORE3_TPC0_EML_2, + GAUDI2_BMON_DCORE3_TPC0_EML_3, + GAUDI2_BMON_DCORE3_TPC1_EML_0, + GAUDI2_BMON_DCORE3_TPC1_EML_1, + GAUDI2_BMON_DCORE3_TPC1_EML_2, + GAUDI2_BMON_DCORE3_TPC1_EML_3, + GAUDI2_BMON_DCORE3_TPC2_EML_0, + GAUDI2_BMON_DCORE3_TPC2_EML_1, + GAUDI2_BMON_DCORE3_TPC2_EML_2, + GAUDI2_BMON_DCORE3_TPC2_EML_3, + GAUDI2_BMON_DCORE3_TPC3_EML_0, + GAUDI2_BMON_DCORE3_TPC3_EML_1, + GAUDI2_BMON_DCORE3_TPC3_EML_2, + GAUDI2_BMON_DCORE3_TPC3_EML_3, + GAUDI2_BMON_DCORE3_TPC4_EML_0, + GAUDI2_BMON_DCORE3_TPC4_EML_1, + GAUDI2_BMON_DCORE3_TPC4_EML_2, + GAUDI2_BMON_DCORE3_TPC4_EML_3, + GAUDI2_BMON_DCORE3_TPC5_EML_0, + GAUDI2_BMON_DCORE3_TPC5_EML_1, + GAUDI2_BMON_DCORE3_TPC5_EML_2, + GAUDI2_BMON_DCORE3_TPC5_EML_3, + GAUDI2_BMON_DCORE0_HMMU0_0, + GAUDI2_BMON_DCORE0_HMMU0_1, + GAUDI2_BMON_DCORE0_HMMU0_3, + GAUDI2_BMON_DCORE0_HMMU0_2, + GAUDI2_BMON_DCORE0_HMMU0_4, + GAUDI2_BMON_DCORE0_HMMU1_0, + GAUDI2_BMON_DCORE0_HMMU1_1, + GAUDI2_BMON_DCORE0_HMMU1_3, + GAUDI2_BMON_DCORE0_HMMU1_2, + GAUDI2_BMON_DCORE0_HMMU1_4, + GAUDI2_BMON_DCORE0_HMMU2_0, + GAUDI2_BMON_DCORE0_HMMU2_1, + GAUDI2_BMON_DCORE0_HMMU2_3, + GAUDI2_BMON_DCORE0_HMMU2_2, + GAUDI2_BMON_DCORE0_HMMU2_4, + GAUDI2_BMON_DCORE0_HMMU3_0, + GAUDI2_BMON_DCORE0_HMMU3_1, + GAUDI2_BMON_DCORE0_HMMU3_3, + GAUDI2_BMON_DCORE0_HMMU3_2, + GAUDI2_BMON_DCORE0_HMMU3_4, + GAUDI2_BMON_DCORE0_MME_CTRL_0, + GAUDI2_BMON_DCORE0_MME_CTRL_1, + GAUDI2_BMON_DCORE0_MME_CTRL_2, + GAUDI2_BMON_DCORE0_MME_CTRL_3, + GAUDI2_BMON_DCORE0_MME_SBTE0_0, + GAUDI2_BMON_DCORE0_MME_SBTE1_0, + GAUDI2_BMON_DCORE0_MME_SBTE2_0, + GAUDI2_BMON_DCORE0_MME_SBTE3_0, + GAUDI2_BMON_DCORE0_MME_SBTE4_0, + GAUDI2_BMON_DCORE0_MME_ACC_0, + GAUDI2_BMON_DCORE0_MME_ACC_1, + GAUDI2_BMON_DCORE0_SM, + GAUDI2_BMON_DCORE0_SM_1, + GAUDI2_BMON_DCORE0_EDMA0_0, + GAUDI2_BMON_DCORE0_EDMA0_1, + GAUDI2_BMON_DCORE0_EDMA1_0, + GAUDI2_BMON_DCORE0_EDMA1_1, + GAUDI2_BMON_DCORE0_VDEC0_0, + GAUDI2_BMON_DCORE0_VDEC0_1, + GAUDI2_BMON_DCORE0_VDEC0_2, + GAUDI2_BMON_DCORE0_VDEC1_0, + GAUDI2_BMON_DCORE0_VDEC1_1, + GAUDI2_BMON_DCORE0_VDEC1_2, + GAUDI2_BMON_DCORE1_HMMU0_0, + GAUDI2_BMON_DCORE1_HMMU0_1, + GAUDI2_BMON_DCORE1_HMMU0_3, + GAUDI2_BMON_DCORE1_HMMU0_2, + GAUDI2_BMON_DCORE1_HMMU0_4, + GAUDI2_BMON_DCORE1_HMMU1_0, + GAUDI2_BMON_DCORE1_HMMU1_1, + GAUDI2_BMON_DCORE1_HMMU1_3, + GAUDI2_BMON_DCORE1_HMMU1_2, + GAUDI2_BMON_DCORE1_HMMU1_4, + GAUDI2_BMON_DCORE1_HMMU2_0, + GAUDI2_BMON_DCORE1_HMMU2_1, + GAUDI2_BMON_DCORE1_HMMU2_3, + GAUDI2_BMON_DCORE1_HMMU2_2, + GAUDI2_BMON_DCORE1_HMMU2_4, + GAUDI2_BMON_DCORE1_HMMU3_0, + GAUDI2_BMON_DCORE1_HMMU3_1, + GAUDI2_BMON_DCORE1_HMMU3_3, + GAUDI2_BMON_DCORE1_HMMU3_2, + GAUDI2_BMON_DCORE1_HMMU3_4, + GAUDI2_BMON_DCORE1_MME_CTRL_0, + GAUDI2_BMON_DCORE1_MME_CTRL_1, + GAUDI2_BMON_DCORE1_MME_CTRL_2, + GAUDI2_BMON_DCORE1_MME_CTRL_3, + GAUDI2_BMON_DCORE1_MME_SBTE0_0, + GAUDI2_BMON_DCORE1_MME_SBTE1_0, + GAUDI2_BMON_DCORE1_MME_SBTE2_0, + GAUDI2_BMON_DCORE1_MME_SBTE3_0, + GAUDI2_BMON_DCORE1_MME_SBTE4_0, + GAUDI2_BMON_DCORE1_MME_ACC_0, + GAUDI2_BMON_DCORE1_MME_ACC_1, + GAUDI2_BMON_DCORE1_SM, + GAUDI2_BMON_DCORE1_SM_1, + GAUDI2_BMON_DCORE1_EDMA0_0, + GAUDI2_BMON_DCORE1_EDMA0_1, + GAUDI2_BMON_DCORE1_EDMA1_0, + GAUDI2_BMON_DCORE1_EDMA1_1, + GAUDI2_BMON_DCORE1_VDEC0_0, + GAUDI2_BMON_DCORE1_VDEC0_1, + GAUDI2_BMON_DCORE1_VDEC0_2, + GAUDI2_BMON_DCORE1_VDEC1_0, + GAUDI2_BMON_DCORE1_VDEC1_1, + GAUDI2_BMON_DCORE1_VDEC1_2, + GAUDI2_BMON_DCORE2_HMMU0_0, + GAUDI2_BMON_DCORE2_HMMU0_1, + GAUDI2_BMON_DCORE2_HMMU0_3, + GAUDI2_BMON_DCORE2_HMMU0_2, + GAUDI2_BMON_DCORE2_HMMU0_4, + GAUDI2_BMON_DCORE2_HMMU1_0, + GAUDI2_BMON_DCORE2_HMMU1_1, + GAUDI2_BMON_DCORE2_HMMU1_3, + GAUDI2_BMON_DCORE2_HMMU1_2, + GAUDI2_BMON_DCORE2_HMMU1_4, + GAUDI2_BMON_DCORE2_HMMU2_0, + GAUDI2_BMON_DCORE2_HMMU2_1, + GAUDI2_BMON_DCORE2_HMMU2_3, + GAUDI2_BMON_DCORE2_HMMU2_2, + GAUDI2_BMON_DCORE2_HMMU2_4, + GAUDI2_BMON_DCORE2_HMMU3_0, + GAUDI2_BMON_DCORE2_HMMU3_1, + GAUDI2_BMON_DCORE2_HMMU3_3, + GAUDI2_BMON_DCORE2_HMMU3_2, + GAUDI2_BMON_DCORE2_HMMU3_4, + GAUDI2_BMON_DCORE2_MME_CTRL_0, + GAUDI2_BMON_DCORE2_MME_CTRL_1, + GAUDI2_BMON_DCORE2_MME_CTRL_2, + GAUDI2_BMON_DCORE2_MME_CTRL_3, + GAUDI2_BMON_DCORE2_MME_SBTE0_0, + GAUDI2_BMON_DCORE2_MME_SBTE1_0, + GAUDI2_BMON_DCORE2_MME_SBTE2_0, + GAUDI2_BMON_DCORE2_MME_SBTE3_0, + GAUDI2_BMON_DCORE2_MME_SBTE4_0, + GAUDI2_BMON_DCORE2_MME_ACC_0, + GAUDI2_BMON_DCORE2_MME_ACC_1, + GAUDI2_BMON_DCORE2_SM, + GAUDI2_BMON_DCORE2_SM_1, + GAUDI2_BMON_DCORE2_EDMA0_0, + GAUDI2_BMON_DCORE2_EDMA0_1, + GAUDI2_BMON_DCORE2_EDMA1_0, + GAUDI2_BMON_DCORE2_EDMA1_1, + GAUDI2_BMON_DCORE2_VDEC0_0, + GAUDI2_BMON_DCORE2_VDEC0_1, + GAUDI2_BMON_DCORE2_VDEC0_2, + GAUDI2_BMON_DCORE2_VDEC1_0, + GAUDI2_BMON_DCORE2_VDEC1_1, + GAUDI2_BMON_DCORE2_VDEC1_2, + GAUDI2_BMON_DCORE3_HMMU0_0, + GAUDI2_BMON_DCORE3_HMMU0_1, + GAUDI2_BMON_DCORE3_HMMU0_3, + GAUDI2_BMON_DCORE3_HMMU0_2, + GAUDI2_BMON_DCORE3_HMMU0_4, + GAUDI2_BMON_DCORE3_HMMU1_0, + GAUDI2_BMON_DCORE3_HMMU1_1, + GAUDI2_BMON_DCORE3_HMMU1_3, + GAUDI2_BMON_DCORE3_HMMU1_2, + GAUDI2_BMON_DCORE3_HMMU1_4, + GAUDI2_BMON_DCORE3_HMMU2_0, + GAUDI2_BMON_DCORE3_HMMU2_1, + GAUDI2_BMON_DCORE3_HMMU2_3, + GAUDI2_BMON_DCORE3_HMMU2_2, + GAUDI2_BMON_DCORE3_HMMU2_4, + GAUDI2_BMON_DCORE3_HMMU3_0, + GAUDI2_BMON_DCORE3_HMMU3_1, + GAUDI2_BMON_DCORE3_HMMU3_3, + GAUDI2_BMON_DCORE3_HMMU3_2, + GAUDI2_BMON_DCORE3_HMMU3_4, + GAUDI2_BMON_DCORE3_MME_CTRL_0, + GAUDI2_BMON_DCORE3_MME_CTRL_1, + GAUDI2_BMON_DCORE3_MME_CTRL_2, + GAUDI2_BMON_DCORE3_MME_CTRL_3, + GAUDI2_BMON_DCORE3_MME_SBTE0_0, + GAUDI2_BMON_DCORE3_MME_SBTE1_0, + GAUDI2_BMON_DCORE3_MME_SBTE2_0, + GAUDI2_BMON_DCORE3_MME_SBTE3_0, + GAUDI2_BMON_DCORE3_MME_SBTE4_0, + GAUDI2_BMON_DCORE3_MME_ACC_0, + GAUDI2_BMON_DCORE3_MME_ACC_1, + GAUDI2_BMON_DCORE3_SM, + GAUDI2_BMON_DCORE3_SM_1, + GAUDI2_BMON_DCORE3_EDMA0_0, + GAUDI2_BMON_DCORE3_EDMA0_1, + GAUDI2_BMON_DCORE3_EDMA1_0, + GAUDI2_BMON_DCORE3_EDMA1_1, + GAUDI2_BMON_DCORE3_VDEC0_0, + GAUDI2_BMON_DCORE3_VDEC0_1, + GAUDI2_BMON_DCORE3_VDEC0_2, + GAUDI2_BMON_DCORE3_VDEC1_0, + GAUDI2_BMON_DCORE3_VDEC1_1, + GAUDI2_BMON_DCORE3_VDEC1_2, + GAUDI2_BMON_PCIE_MSTR_WR, + GAUDI2_BMON_PCIE_MSTR_RD, + GAUDI2_BMON_PCIE_SLV_WR, + GAUDI2_BMON_PCIE_SLV_RD, + GAUDI2_BMON_PSOC_ARC0_0, + GAUDI2_BMON_PSOC_ARC0_1, + GAUDI2_BMON_PSOC_ARC1_0, + GAUDI2_BMON_PSOC_ARC1_1, + GAUDI2_BMON_PDMA0_0, + GAUDI2_BMON_PDMA0_1, + GAUDI2_BMON_PDMA1_0, + GAUDI2_BMON_PDMA1_1, + GAUDI2_BMON_CPU_WR, + GAUDI2_BMON_CPU_RD, + GAUDI2_BMON_PMMU_0, + GAUDI2_BMON_PMMU_1, + GAUDI2_BMON_PMMU_2, + GAUDI2_BMON_PMMU_3, + GAUDI2_BMON_PMMU_4, + GAUDI2_BMON_ROT0_0, + GAUDI2_BMON_ROT0_1, + GAUDI2_BMON_ROT0_2, + GAUDI2_BMON_ROT0_3, + GAUDI2_BMON_ROT1_0, + GAUDI2_BMON_ROT1_1, + GAUDI2_BMON_ROT1_2, + GAUDI2_BMON_ROT1_3, + GAUDI2_BMON_ARC_FARM_0, + GAUDI2_BMON_ARC_FARM_1, + GAUDI2_BMON_ARC_FARM_2, + GAUDI2_BMON_ARC_FARM_3, + GAUDI2_BMON_KDMA_0, + GAUDI2_BMON_KDMA_1, + GAUDI2_BMON_KDMA_2, + GAUDI2_BMON_KDMA_3, + GAUDI2_BMON_PCIE_VDEC0_0, + GAUDI2_BMON_PCIE_VDEC0_1, + GAUDI2_BMON_PCIE_VDEC0_2, + GAUDI2_BMON_PCIE_VDEC1_0, + GAUDI2_BMON_PCIE_VDEC1_1, + GAUDI2_BMON_PCIE_VDEC1_2, + GAUDI2_BMON_NIC0_DBG_0_0, + GAUDI2_BMON_NIC0_DBG_1_0, + GAUDI2_BMON_NIC0_DBG_2_0, + GAUDI2_BMON_NIC0_DBG_0_1, + GAUDI2_BMON_NIC0_DBG_1_1, + GAUDI2_BMON_NIC0_DBG_2_1, + GAUDI2_BMON_NIC1_DBG_0_0, + GAUDI2_BMON_NIC1_DBG_1_0, + GAUDI2_BMON_NIC1_DBG_2_0, + GAUDI2_BMON_NIC1_DBG_0_1, + GAUDI2_BMON_NIC1_DBG_1_1, + GAUDI2_BMON_NIC1_DBG_2_1, + GAUDI2_BMON_NIC2_DBG_0_0, + GAUDI2_BMON_NIC2_DBG_1_0, + GAUDI2_BMON_NIC2_DBG_2_0, + GAUDI2_BMON_NIC2_DBG_0_1, + GAUDI2_BMON_NIC2_DBG_1_1, + GAUDI2_BMON_NIC2_DBG_2_1, + GAUDI2_BMON_NIC3_DBG_0_0, + GAUDI2_BMON_NIC3_DBG_1_0, + GAUDI2_BMON_NIC3_DBG_2_0, + GAUDI2_BMON_NIC3_DBG_0_1, + GAUDI2_BMON_NIC3_DBG_1_1, + GAUDI2_BMON_NIC3_DBG_2_1, + GAUDI2_BMON_NIC4_DBG_0_0, + GAUDI2_BMON_NIC4_DBG_1_0, + GAUDI2_BMON_NIC4_DBG_2_0, + GAUDI2_BMON_NIC4_DBG_0_1, + GAUDI2_BMON_NIC4_DBG_1_1, + GAUDI2_BMON_NIC4_DBG_2_1, + GAUDI2_BMON_NIC5_DBG_0_0, + GAUDI2_BMON_NIC5_DBG_1_0, + GAUDI2_BMON_NIC5_DBG_2_0, + GAUDI2_BMON_NIC5_DBG_0_1, + GAUDI2_BMON_NIC5_DBG_1_1, + GAUDI2_BMON_NIC5_DBG_2_1, + GAUDI2_BMON_NIC6_DBG_0_0, + GAUDI2_BMON_NIC6_DBG_1_0, + GAUDI2_BMON_NIC6_DBG_2_0, + GAUDI2_BMON_NIC6_DBG_0_1, + GAUDI2_BMON_NIC6_DBG_1_1, + GAUDI2_BMON_NIC6_DBG_2_1, + GAUDI2_BMON_NIC7_DBG_0_0, + GAUDI2_BMON_NIC7_DBG_1_0, + GAUDI2_BMON_NIC7_DBG_2_0, + GAUDI2_BMON_NIC7_DBG_0_1, + GAUDI2_BMON_NIC7_DBG_1_1, + GAUDI2_BMON_NIC7_DBG_2_1, + GAUDI2_BMON_NIC8_DBG_0_0, + GAUDI2_BMON_NIC8_DBG_1_0, + GAUDI2_BMON_NIC8_DBG_2_0, + GAUDI2_BMON_NIC8_DBG_0_1, + GAUDI2_BMON_NIC8_DBG_1_1, + GAUDI2_BMON_NIC8_DBG_2_1, + GAUDI2_BMON_NIC9_DBG_0_0, + GAUDI2_BMON_NIC9_DBG_1_0, + GAUDI2_BMON_NIC9_DBG_2_0, + GAUDI2_BMON_NIC9_DBG_0_1, + GAUDI2_BMON_NIC9_DBG_1_1, + GAUDI2_BMON_NIC9_DBG_2_1, + GAUDI2_BMON_NIC10_DBG_0_0, + GAUDI2_BMON_NIC10_DBG_1_0, + GAUDI2_BMON_NIC10_DBG_2_0, + GAUDI2_BMON_NIC10_DBG_0_1, + GAUDI2_BMON_NIC10_DBG_1_1, + GAUDI2_BMON_NIC10_DBG_2_1, + GAUDI2_BMON_NIC11_DBG_0_0, + GAUDI2_BMON_NIC11_DBG_1_0, + GAUDI2_BMON_NIC11_DBG_2_0, + GAUDI2_BMON_NIC11_DBG_0_1, + GAUDI2_BMON_NIC11_DBG_1_1, + GAUDI2_BMON_NIC11_DBG_2_1, + GAUDI2_BMON_LAST = GAUDI2_BMON_NIC11_DBG_2_1 +}; + +enum gaudi2_debug_spmu_regs_index { + GAUDI2_SPMU_FIRST = 0, + GAUDI2_SPMU_DCORE0_TPC0_EML = GAUDI2_SPMU_FIRST, + GAUDI2_SPMU_DCORE0_TPC1_EML, + GAUDI2_SPMU_DCORE0_TPC2_EML, + GAUDI2_SPMU_DCORE0_TPC3_EML, + GAUDI2_SPMU_DCORE0_TPC4_EML, + GAUDI2_SPMU_DCORE0_TPC5_EML, + GAUDI2_SPMU_DCORE0_TPC6_EML, + GAUDI2_SPMU_DCORE1_TPC0_EML, + GAUDI2_SPMU_DCORE1_TPC1_EML, + GAUDI2_SPMU_DCORE1_TPC2_EML, + GAUDI2_SPMU_DCORE1_TPC3_EML, + GAUDI2_SPMU_DCORE1_TPC4_EML, + GAUDI2_SPMU_DCORE1_TPC5_EML, + GAUDI2_SPMU_DCORE2_TPC0_EML, + GAUDI2_SPMU_DCORE2_TPC1_EML, + GAUDI2_SPMU_DCORE2_TPC2_EML, + GAUDI2_SPMU_DCORE2_TPC3_EML, + GAUDI2_SPMU_DCORE2_TPC4_EML, + GAUDI2_SPMU_DCORE2_TPC5_EML, + GAUDI2_SPMU_DCORE3_TPC0_EML, + GAUDI2_SPMU_DCORE3_TPC1_EML, + GAUDI2_SPMU_DCORE3_TPC2_EML, + GAUDI2_SPMU_DCORE3_TPC3_EML, + GAUDI2_SPMU_DCORE3_TPC4_EML, + GAUDI2_SPMU_DCORE3_TPC5_EML, + GAUDI2_SPMU_DCORE0_HMMU0_CS, + GAUDI2_SPMU_DCORE0_HMMU1_CS, + GAUDI2_SPMU_DCORE0_HMMU2_CS, + GAUDI2_SPMU_DCORE0_HMMU3_CS, + GAUDI2_SPMU_DCORE0_MME_CTRL, + GAUDI2_SPMU_DCORE0_MME_SBTE0, + GAUDI2_SPMU_DCORE0_MME_SBTE1, + GAUDI2_SPMU_DCORE0_MME_SBTE2, + GAUDI2_SPMU_DCORE0_MME_SBTE3, + GAUDI2_SPMU_DCORE0_MME_SBTE4, + GAUDI2_SPMU_DCORE0_MME_ACC, + GAUDI2_SPMU_DCORE0_SM, + GAUDI2_SPMU_DCORE0_EDMA0_CS, + GAUDI2_SPMU_DCORE0_EDMA1_CS, + GAUDI2_SPMU_DCORE0_VDEC0_CS, + GAUDI2_SPMU_DCORE0_VDEC1_CS, + GAUDI2_SPMU_DCORE1_HMMU0_CS, + GAUDI2_SPMU_DCORE1_HMMU1_CS, + GAUDI2_SPMU_DCORE1_HMMU2_CS, + GAUDI2_SPMU_DCORE1_HMMU3_CS, + GAUDI2_SPMU_DCORE1_MME_CTRL, + GAUDI2_SPMU_DCORE1_MME_SBTE0, + GAUDI2_SPMU_DCORE1_MME_SBTE1, + GAUDI2_SPMU_DCORE1_MME_SBTE2, + GAUDI2_SPMU_DCORE1_MME_SBTE3, + GAUDI2_SPMU_DCORE1_MME_SBTE4, + GAUDI2_SPMU_DCORE1_MME_ACC, + GAUDI2_SPMU_DCORE1_SM, + GAUDI2_SPMU_DCORE1_EDMA0_CS, + GAUDI2_SPMU_DCORE1_EDMA1_CS, + GAUDI2_SPMU_DCORE1_VDEC0_CS, + GAUDI2_SPMU_DCORE1_VDEC1_CS, + GAUDI2_SPMU_DCORE2_HMMU0_CS, + GAUDI2_SPMU_DCORE2_HMMU1_CS, + GAUDI2_SPMU_DCORE2_HMMU2_CS, + GAUDI2_SPMU_DCORE2_HMMU3_CS, + GAUDI2_SPMU_DCORE2_MME_CTRL, + GAUDI2_SPMU_DCORE2_MME_SBTE0, + GAUDI2_SPMU_DCORE2_MME_SBTE1, + GAUDI2_SPMU_DCORE2_MME_SBTE2, + GAUDI2_SPMU_DCORE2_MME_SBTE3, + GAUDI2_SPMU_DCORE2_MME_SBTE4, + GAUDI2_SPMU_DCORE2_MME_ACC, + GAUDI2_SPMU_DCORE2_SM, + GAUDI2_SPMU_DCORE2_EDMA0_CS, + GAUDI2_SPMU_DCORE2_EDMA1_CS, + GAUDI2_SPMU_DCORE2_VDEC0_CS, + GAUDI2_SPMU_DCORE2_VDEC1_CS, + GAUDI2_SPMU_DCORE3_HMMU0_CS, + GAUDI2_SPMU_DCORE3_HMMU1_CS, + GAUDI2_SPMU_DCORE3_HMMU2_CS, + GAUDI2_SPMU_DCORE3_HMMU3_CS, + GAUDI2_SPMU_DCORE3_MME_CTRL, + GAUDI2_SPMU_DCORE3_MME_SBTE0, + GAUDI2_SPMU_DCORE3_MME_SBTE1, + GAUDI2_SPMU_DCORE3_MME_SBTE2, + GAUDI2_SPMU_DCORE3_MME_SBTE3, + GAUDI2_SPMU_DCORE3_MME_SBTE4, + GAUDI2_SPMU_DCORE3_MME_ACC, + GAUDI2_SPMU_DCORE3_SM, + GAUDI2_SPMU_DCORE3_EDMA0_CS, + GAUDI2_SPMU_DCORE3_EDMA1_CS, + GAUDI2_SPMU_DCORE3_VDEC0_CS, + GAUDI2_SPMU_DCORE3_VDEC1_CS, + GAUDI2_SPMU_PCIE, + GAUDI2_SPMU_PSOC_ARC0_CS, + GAUDI2_SPMU_PSOC_ARC1_CS, + GAUDI2_SPMU_PDMA0_CS, + GAUDI2_SPMU_PDMA1_CS, + GAUDI2_SPMU_PMMU_CS, + GAUDI2_SPMU_ROT0_CS, + GAUDI2_SPMU_ROT1_CS, + GAUDI2_SPMU_ARC_FARM_CS, + GAUDI2_SPMU_KDMA_CS, + GAUDI2_SPMU_PCIE_VDEC0_CS, + GAUDI2_SPMU_PCIE_VDEC1_CS, + GAUDI2_SPMU_HBM0_MC0_CS, + GAUDI2_SPMU_HBM0_MC1_CS, + GAUDI2_SPMU_HBM1_MC0_CS, + GAUDI2_SPMU_HBM1_MC1_CS, + GAUDI2_SPMU_HBM2_MC0_CS, + GAUDI2_SPMU_HBM2_MC1_CS, + GAUDI2_SPMU_HBM3_MC0_CS, + GAUDI2_SPMU_HBM3_MC1_CS, + GAUDI2_SPMU_HBM4_MC0_CS, + GAUDI2_SPMU_HBM4_MC1_CS, + GAUDI2_SPMU_HBM5_MC0_CS, + GAUDI2_SPMU_HBM5_MC1_CS, + GAUDI2_SPMU_NIC0_DBG_0, + GAUDI2_SPMU_NIC0_DBG_1, + GAUDI2_SPMU_NIC1_DBG_0, + GAUDI2_SPMU_NIC1_DBG_1, + GAUDI2_SPMU_NIC2_DBG_0, + GAUDI2_SPMU_NIC2_DBG_1, + GAUDI2_SPMU_NIC3_DBG_0, + GAUDI2_SPMU_NIC3_DBG_1, + GAUDI2_SPMU_NIC4_DBG_0, + GAUDI2_SPMU_NIC4_DBG_1, + GAUDI2_SPMU_NIC5_DBG_0, + GAUDI2_SPMU_NIC5_DBG_1, + GAUDI2_SPMU_NIC6_DBG_0, + GAUDI2_SPMU_NIC6_DBG_1, + GAUDI2_SPMU_NIC7_DBG_0, + GAUDI2_SPMU_NIC7_DBG_1, + GAUDI2_SPMU_NIC8_DBG_0, + GAUDI2_SPMU_NIC8_DBG_1, + GAUDI2_SPMU_NIC9_DBG_0, + GAUDI2_SPMU_NIC9_DBG_1, + GAUDI2_SPMU_NIC10_DBG_0, + GAUDI2_SPMU_NIC10_DBG_1, + GAUDI2_SPMU_NIC11_DBG_0, + GAUDI2_SPMU_NIC11_DBG_1, + GAUDI2_SPMU_LAST = GAUDI2_SPMU_NIC11_DBG_1 +}; + +#endif /* GAUDI2_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h new file mode 100644 index 000000000..e4a7d5725 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_FW_IF_H +#define GAUDI2_FW_IF_H + +#define GAUDI2_EVENT_QUEUE_MSIX_IDX 0 + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8BM in DDR */ + +#define GAUDI2_PLL_FREQ_LOW 200000000 /* 200 MHz */ + +#define GAUDI2_SP_SRAM_BASE_ADDR 0x27FE0000 +#define GAUDI2_MAILBOX_BASE_ADDR 0x27FE1800 + +#define GAUDI2_NUM_MME 4 + +#define GAUDI2_ARCPID_TX_MB_SIZE 0x1000 +#define GAUDI2_ARCPID_RX_MB_SIZE 0x400 +#define GAUDI2_ARM_TX_MB_SIZE 0x400 +#define GAUDI2_ARM_RX_MB_SIZE 0x1800 + +#define GAUDI2_DCCM_BASE_ADDR 0x27020000 +#define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR + +#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \ + GAUDI2_ARCPID_TX_MB_SIZE) + +#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR + +#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \ + GAUDI2_ARM_TX_MB_SIZE) + +#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \ + GAUDI2_SP_SRAM_BASE_ADDR) + +#define GAUDI2_ARM_RX_MB_OFFSET (GAUDI2_ARM_RX_MB_ADDR - \ + GAUDI2_SP_SRAM_BASE_ADDR) + +enum gaudi2_fw_status { + GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */ + GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */ + GAUDI2_MGMT_STATUS_UP = 0x3, /* ARC1 Mgmt is up */ + GAUDI2_STATUS_LAST = 0xFF +}; + +struct gaudi2_cold_rst_data { + union { + struct { + u32 recovery_flag: 1; + u32 validation_flag: 1; + u32 efuse_read_flag: 1; + u32 spsram_init_done : 1; + u32 fake_security_enable : 1; + u32 fake_sig_validation_en : 1; + u32 reserved : 26; + }; + __le32 data; + }; +}; + +enum gaudi2_rst_src { + HL_COLD_RST = 1, + HL_MANUAL_RST = 2, + HL_PRSTN_RST = 4, + HL_SOFT_RST = 8, + HL_WD_RST = 16, + HL_FW_ALL_RST = 32, + HL_SW_ALL_RST = 64, + HL_FLR_RST = 128, + HL_ECC_DERR_RST = 256 +}; + +struct gaudi2_redundancy_ctx { + int redundant_hbm; + int redundant_edma; + int redundant_tpc; + int redundant_vdec; + __le64 hbm_mask; + __le64 edma_mask; + __le64 tpc_mask; + __le64 vdec_mask; + __le64 mme_mask; + __le64 nic_mask; + __le64 rtr_mask; + __le64 hmmu_hif_iso; + __le64 xbar_edge_iso; + __le64 hmmu_hif_mask; + __le64 xbar_edge_mask; + __u8 mme_pe_iso[GAUDI2_NUM_MME]; + __le32 full_hbm_mode; /* true on full (non binning hbm)*/ +} __packed; + +#endif /* GAUDI2_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h new file mode 100644 index 000000000..8bf90fc18 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_PACKETS_H +#define GAUDI2_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_CB_LIST = 0xE, + PACKET_LOAD_AND_EXE = 0xF, + PACKET_WRITE_ARC_STREAM = 0x10, + PACKET_LAST_READ_FROM_ARC = 0x11, + PACKET_WREG_64_SHORT = 0x12, + PACKET_WREG_64_LONG = 0x13, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GAUDI2_PKT_CTL_OPCODE_SHIFT 24 +#define GAUDI2_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI2_PKT_CTL_EB_SHIFT 29 +#define GAUDI2_PKT_CTL_EB_MASK 0x20000000 + +#define GAUDI2_PKT_CTL_RB_SHIFT 30 +#define GAUDI2_PKT_CTL_RB_MASK 0x40000000 + +#define GAUDI2_PKT_CTL_MB_SHIFT 31 +#define GAUDI2_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct gaudi2_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[0]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0 +#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x00007FFF + +#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_SHIFT 31 +#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000 + +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0 +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF + +#define GAUDI2_PKT_SHORT_VAL_MON_MASK_SHIFT 8 +#define GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00 + +#define GAUDI2_PKT_SHORT_VAL_MON_MODE_SHIFT 16 +#define GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000 + +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17 +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000 + +#define GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT 0 +#define GAUDI2_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF + +#define GAUDI2_PKT_SHORT_CTL_BASE_SHIFT 22 +#define GAUDI2_PKT_SHORT_CTL_BASE_MASK 0x00C00000 + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_SHIFT 0 +#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F + +#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16 +#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000 + +#define GAUDI2_PKT_FENCE_CFG_ID_SHIFT 30 +#define GAUDI2_PKT_FENCE_CFG_ID_MASK 0xC0000000 + +#define GAUDI2_PKT_FENCE_CTL_PRED_SHIFT 0 +#define GAUDI2_PKT_FENCE_CTL_PRED_MASK 0x0000001F + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_SHIFT 0 +#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_MASK 0x00000001 + +#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_SHIFT 1 +#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_MASK 0x00000006 + +#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4 +#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010 + +#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_SHIFT 8 +#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_MASK 0x00FFFF00 + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_arb_point { + __le32 cfg; + __le32 ctl; +}; + +struct packet_repeat { + __le32 cfg; + __le32 ctl; +}; + +struct packet_wait { + __le32 cfg; + __le32 ctl; +}; + +struct packet_cb_list { + __le32 reserved; + __le32 ctl; + __le64 index_addr; + __le64 table_addr; +}; + +struct packet_load_and_exe { + __le32 cfg; + __le32 ctl; + __le64 src_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GAUDI2_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h new file mode 100644 index 000000000..ae7feb388 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_REG_MAP_H_ +#define GAUDI2_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmHW_STATE mmCPU_IF_KMD_HW_DIRTY_STATUS +#define mmPID_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmARM_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 +#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 +#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 +#define mmEEPROM_COPY_LOCATION_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 +#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 +#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 +#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 +/* + * TODO: mmGIC_RAZWI_STATUS_REG is temporary + * macro and to be removed after GAUDI2 PO + */ +#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 +#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 +#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 +#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 +#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 +#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0 +#define mmPID_CMD_REQ_REG_HI mmPSOC_PID_PID_CMD_1 +#define mmPID_CMD_RSP_REG mmPSOC_PID_PID_CMD_2 +#define mmPID_CMD_RSP_REG_HI mmPSOC_PID_PID_CMD_3 +#define mmPID_CMD_TELEMETRY_REG_0 mmPSOC_PID_PID_CMD_4 +#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5 +#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6 +#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7 + +#endif /* GAUDI2_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h new file mode 100644 index 000000000..4e0dbbbbd --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ +#define ASIC_REG_CPU_CA53_CFG_MASKS_H_ + +/* + ***************************************** + * CPU_CA53_CFG (Prototype: CA53_CFG) + ***************************************** + */ + +/* CPU_CA53_CFG_ARM_CFG */ +#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0 +#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 +#define CPU_CA53_CFG_ARM_CFG_END_SHIFT 4 +#define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30 +#define CPU_CA53_CFG_ARM_CFG_TE_SHIFT 8 +#define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300 +#define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT 12 +#define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000 + +/* CPU_CA53_CFG_RST_ADDR_LSB */ +#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0 +#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF + +/* CPU_CA53_CFG_RST_ADDR_MSB */ +#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0 +#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF + +/* CPU_CA53_CFG_ARM_RST_CONTROL */ +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 + +/* CPU_CA53_CFG_ARM_AFFINITY */ +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT 0 +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK 0xFF +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT 8 +#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK 0xFF00 + +/* CPU_CA53_CFG_ARM_DISABLE */ +#define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT 0 +#define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 +#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT 4 +#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK 0x30 +#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT 8 +#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK 0x100 +#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT 9 +#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK 0x200 + +/* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ +#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT 0 +#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK 0x3FFFFF + +/* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT 0 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT 4 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK 0x30 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT 8 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK 0x300 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT 12 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK 0x3000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT 16 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK 0x30000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK 0x300000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT 24 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK 0x3000000 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT 31 +#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK 0x80000000 + +/* CPU_CA53_CFG_ARM_PWR_MNG */ +#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK 0x1 +#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT 1 +#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK 0x2 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT 2 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK 0x4 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT 3 +#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK 0x8 +#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK 0x3000 + +/* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT 0 +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK 0xFFFFFFF +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31 +#define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000 + +/* CPU_CA53_CFG_ARM_DBG_MODES */ +#define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT 0 +#define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 +#define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT 4 +#define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK 0x30 +#define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT 8 +#define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK 0x300 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT 12 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK 0x3000 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT 16 +#define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK 0x30000 + +/* CPU_CA53_CFG_ARM_PWR_STAT_0 */ +#define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK 0x1 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT 1 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK 0x2 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK 0x1000 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT 13 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK 0x2000 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT 16 +#define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK 0x30000 + +/* CPU_CA53_CFG_ARM_PWR_STAT_1 */ +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT 0 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT 4 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK 0x30 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT 8 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK 0x300 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT 12 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK 0x3000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT 16 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK 0x30000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT 20 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK 0x300000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT 24 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK 0x1000000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT 25 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK 0x2000000 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT 26 +#define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK 0x4000000 + +/* CPU_CA53_CFG_ARM_DBG_STATUS */ +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT 0 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT 4 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK 0x30 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT 8 +#define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK 0x300 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT 12 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK 0x3000 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT 16 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK 0x30000 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK 0x300000 + +/* CPU_CA53_CFG_ARM_MEM_ATTR */ +#define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT 0 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK 0xFF +#define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT 8 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK 0xFF00 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT 16 +#define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK 0x10000 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT 20 +#define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK 0x100000 + +/* CPU_CA53_CFG_ARM_PMU */ +#define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT 0 +#define CPU_CA53_CFG_ARM_PMU_EVENT_MASK 0x3FFFFFFF + +#endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h new file mode 100644 index 000000000..f3faf1aad --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_ +#define ASIC_REG_CPU_CA53_CFG_REGS_H_ + +/* + ***************************************** + * CPU_CA53_CFG (Prototype: CA53_CFG) + ***************************************** + */ + +#define mmCPU_CA53_CFG_ARM_CFG 0x441100 + +#define mmCPU_CA53_CFG_RST_ADDR_LSB_0 0x441104 + +#define mmCPU_CA53_CFG_RST_ADDR_LSB_1 0x441108 + +#define mmCPU_CA53_CFG_RST_ADDR_MSB_0 0x441114 + +#define mmCPU_CA53_CFG_RST_ADDR_MSB_1 0x441118 + +#define mmCPU_CA53_CFG_ARM_RST_CONTROL 0x441124 + +#define mmCPU_CA53_CFG_ARM_AFFINITY 0x441128 + +#define mmCPU_CA53_CFG_ARM_DISABLE 0x44112C + +#define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE 0x441130 + +#define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG 0x441134 + +#define mmCPU_CA53_CFG_ARM_PWR_MNG 0x441138 + +#define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR 0x44113C + +#define mmCPU_CA53_CFG_ARM_DBG_MODES 0x441140 + +#define mmCPU_CA53_CFG_ARM_PWR_STAT_0 0x441200 + +#define mmCPU_CA53_CFG_ARM_PWR_STAT_1 0x441204 + +#define mmCPU_CA53_CFG_ARM_DBG_STATUS 0x441208 + +#define mmCPU_CA53_CFG_ARM_MEM_ATTR 0x44120C + +#define mmCPU_CA53_CFG_ARM_PMU_0 0x441210 + +#define mmCPU_CA53_CFG_ARM_PMU_1 0x441214 + +#endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000..cf6579189 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_PF_PQ_PI 0x442100 + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h new file mode 100644 index 000000000..8c8f9726d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_PLL_REGS_H_ +#define ASIC_REG_CPU_PLL_REGS_H_ + +/* + ***************************************** + * CPU_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmCPU_PLL_NR 0x4A2100 + +#define mmCPU_PLL_NF 0x4A2104 + +#define mmCPU_PLL_OD 0x4A2108 + +#define mmCPU_PLL_NB 0x4A210C + +#define mmCPU_PLL_CFG 0x4A2110 + +#define mmCPU_PLL_LOSE_MASK 0x4A2120 + +#define mmCPU_PLL_LOCK_INTR 0x4A2128 + +#define mmCPU_PLL_LOCK_BYPASS 0x4A212C + +#define mmCPU_PLL_DATA_CHNG 0x4A2130 + +#define mmCPU_PLL_RST 0x4A2134 + +#define mmCPU_PLL_SLIP_WD_CNTR 0x4A2150 + +#define mmCPU_PLL_DIV_FACTOR_0 0x4A2200 + +#define mmCPU_PLL_DIV_FACTOR_1 0x4A2204 + +#define mmCPU_PLL_DIV_FACTOR_2 0x4A2208 + +#define mmCPU_PLL_DIV_FACTOR_3 0x4A220C + +#define mmCPU_PLL_DIV_FACTOR_CMD_0 0x4A2220 + +#define mmCPU_PLL_DIV_FACTOR_CMD_1 0x4A2224 + +#define mmCPU_PLL_DIV_FACTOR_CMD_2 0x4A2228 + +#define mmCPU_PLL_DIV_FACTOR_CMD_3 0x4A222C + +#define mmCPU_PLL_DIV_SEL_0 0x4A2280 + +#define mmCPU_PLL_DIV_SEL_1 0x4A2284 + +#define mmCPU_PLL_DIV_SEL_2 0x4A2288 + +#define mmCPU_PLL_DIV_SEL_3 0x4A228C + +#define mmCPU_PLL_DIV_EN_0 0x4A22A0 + +#define mmCPU_PLL_DIV_EN_1 0x4A22A4 + +#define mmCPU_PLL_DIV_EN_2 0x4A22A8 + +#define mmCPU_PLL_DIV_EN_3 0x4A22AC + +#define mmCPU_PLL_DIV_FACTOR_BUSY_0 0x4A22C0 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_1 0x4A22C4 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_2 0x4A22C8 + +#define mmCPU_PLL_DIV_FACTOR_BUSY_3 0x4A22CC + +#define mmCPU_PLL_CLK_GATER 0x4A2300 + +#define mmCPU_PLL_CLK_RLX_0 0x4A2310 + +#define mmCPU_PLL_CLK_RLX_1 0x4A2314 + +#define mmCPU_PLL_CLK_RLX_2 0x4A2318 + +#define mmCPU_PLL_CLK_RLX_3 0x4A231C + +#define mmCPU_PLL_REF_CNTR_PERIOD 0x4A2400 + +#define mmCPU_PLL_REF_LOW_THRESHOLD 0x4A2410 + +#define mmCPU_PLL_REF_HIGH_THRESHOLD 0x4A2420 + +#define mmCPU_PLL_PLL_NOT_STABLE 0x4A2430 + +#define mmCPU_PLL_FREQ_CALC_EN 0x4A2440 + +#endif /* ASIC_REG_CPU_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h new file mode 100644 index 000000000..028143408 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h @@ -0,0 +1,418 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_0_MASKS_H_ +#define ASIC_REG_DMA_CH_0_MASKS_H_ + +/* + ***************************************** + * DMA_CH_0 (Prototype: DMA_CH) + ***************************************** + */ + +/* DMA_CH_0_CFG0 */ +#define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT 0 +#define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK 0x3FF +#define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_SHIFT 16 +#define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK 0xFFF0000 + +/* DMA_CH_0_CFG1 */ +#define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT 0 +#define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK 0x3FF + +/* DMA_CH_0_ERRMSG_ADDR_LO */ +#define DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_ERRMSG_ADDR_HI */ +#define DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_ERRMSG_WDATA */ +#define DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT 0 +#define DMA_CH_0_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_RD_COMP_ADDR_LO */ +#define DMA_CH_0_RD_COMP_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_RD_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_RD_COMP_ADDR_HI */ +#define DMA_CH_0_RD_COMP_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_RD_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_RD_COMP_WDATA */ +#define DMA_CH_0_RD_COMP_WDATA_VAL_SHIFT 0 +#define DMA_CH_0_RD_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_WR_COMP_ADDR_LO */ +#define DMA_CH_0_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_WR_COMP_ADDR_HI */ +#define DMA_CH_0_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_WR_COMP_WDATA */ +#define DMA_CH_0_WR_COMP_WDATA_VAL_SHIFT 0 +#define DMA_CH_0_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_LDMA_SRC_ADDR_LO */ +#define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_LDMA_SRC_ADDR_HI */ +#define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_LDMA_DST_ADDR_LO */ +#define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_LDMA_DST_ADDR_HI */ +#define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_LDMA_TSIZE */ +#define DMA_CH_0_LDMA_TSIZE_VAL_SHIFT 0 +#define DMA_CH_0_LDMA_TSIZE_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_COMIT_TRANSFER */ +#define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_SHIFT 0 +#define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_MASK 0x1 +#define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_SHIFT 1 +#define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_MASK 0x2 +#define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_SHIFT 2 +#define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_MASK 0x4 +#define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_SHIFT 3 +#define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_MASK 0x8 +#define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_SHIFT 4 +#define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_MASK 0x10 +#define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_SHIFT 5 +#define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_MASK 0x20 +#define DMA_CH_0_COMIT_TRANSFER_MEM_SET_SHIFT 6 +#define DMA_CH_0_COMIT_TRANSFER_MEM_SET_MASK 0x40 +#define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_SHIFT 15 +#define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_MASK 0x8000 +#define DMA_CH_0_COMIT_TRANSFER_CTL_SHIFT 16 +#define DMA_CH_0_COMIT_TRANSFER_CTL_MASK 0xFFFF0000 + +/* DMA_CH_0_STS0 */ +#define DMA_CH_0_STS0_DMA_BUSY_SHIFT 0 +#define DMA_CH_0_STS0_DMA_BUSY_MASK 0x1 +#define DMA_CH_0_STS0_RD_STS_CTX_FULL_SHIFT 1 +#define DMA_CH_0_STS0_RD_STS_CTX_FULL_MASK 0x2 +#define DMA_CH_0_STS0_WR_STS_CTX_FULL_SHIFT 2 +#define DMA_CH_0_STS0_WR_STS_CTX_FULL_MASK 0x4 + +/* DMA_CH_0_STS1 */ +#define DMA_CH_0_STS1_RD_STS_CTX_CNT_SHIFT 0 +#define DMA_CH_0_STS1_RD_STS_CTX_CNT_MASK 0xFFFFFFFF + +/* DMA_CH_0_STS2 */ +#define DMA_CH_0_STS2_WR_STS_CTX_CNT_SHIFT 0 +#define DMA_CH_0_STS2_WR_STS_CTX_CNT_MASK 0xFFFFFFFF + +/* DMA_CH_0_STS3 */ +#define DMA_CH_0_STS3_RD_STS_TRN_CNT_SHIFT 0 +#define DMA_CH_0_STS3_RD_STS_TRN_CNT_MASK 0xFFFFFFFF + +/* DMA_CH_0_STS4 */ +#define DMA_CH_0_STS4_WR_STS_TRN_CNT_SHIFT 0 +#define DMA_CH_0_STS4_WR_STS_TRN_CNT_MASK 0xFFFFFFFF + +/* DMA_CH_0_SRC_ADDR_LO_STS */ +#define DMA_CH_0_SRC_ADDR_LO_STS_VAL_SHIFT 0 +#define DMA_CH_0_SRC_ADDR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_SRC_ADDR_HI_STS */ +#define DMA_CH_0_SRC_ADDR_HI_STS_VAL_SHIFT 0 +#define DMA_CH_0_SRC_ADDR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_SRC_TSIZE_STS */ +#define DMA_CH_0_SRC_TSIZE_STS_VAL_SHIFT 0 +#define DMA_CH_0_SRC_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_DST_ADDR_LO_STS */ +#define DMA_CH_0_DST_ADDR_LO_STS_VAL_SHIFT 0 +#define DMA_CH_0_DST_ADDR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_DST_ADDR_HI_STS */ +#define DMA_CH_0_DST_ADDR_HI_STS_VAL_SHIFT 0 +#define DMA_CH_0_DST_ADDR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_DST_TSIZE_STS */ +#define DMA_CH_0_DST_TSIZE_STS_VAL_SHIFT 0 +#define DMA_CH_0_DST_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_RD_RATE_LIM_EN */ +#define DMA_CH_0_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_CH_0_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_CH_0_RD_RATE_LIM_RST_TOKEN */ +#define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_CH_0_RD_RATE_LIM_SAT */ +#define DMA_CH_0_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_CH_0_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_CH_0_RD_RATE_LIM_TOUT */ +#define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_CH_0_WR_RATE_LIM_EN */ +#define DMA_CH_0_WR_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_CH_0_WR_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_CH_0_WR_RATE_LIM_RST_TOKEN */ +#define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_CH_0_WR_RATE_LIM_SAT */ +#define DMA_CH_0_WR_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_CH_0_WR_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_CH_0_WR_RATE_LIM_TOUT */ +#define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_CH_0_CFG2 */ +#define DMA_CH_0_CFG2_FORCE_WORD_SHIFT 0 +#define DMA_CH_0_CFG2_FORCE_WORD_MASK 0x1 + +/* DMA_CH_0_TDMA_CTL */ +#define DMA_CH_0_TDMA_CTL_DTYPE_SHIFT 0 +#define DMA_CH_0_TDMA_CTL_DTYPE_MASK 0x7 + +/* DMA_CH_0_TDMA_SRC_BASE_ADDR_LO */ +#define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_BASE_ADDR_HI */ +#define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_BASE_0 */ +#define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_SIZE_0 */ +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 */ +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_START_OFFSET_0 */ +#define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_STRIDE_0 */ +#define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_BASE_1 */ +#define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_SIZE_1 */ +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 */ +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_START_OFFSET_1 */ +#define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_STRIDE_1 */ +#define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_BASE_2 */ +#define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_SIZE_2 */ +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 */ +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_START_OFFSET_2 */ +#define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_STRIDE_2 */ +#define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_BASE_3 */ +#define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_SIZE_3 */ +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 */ +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_START_OFFSET_3 */ +#define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_STRIDE_3 */ +#define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_BASE_4 */ +#define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_ROI_SIZE_4 */ +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 */ +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_START_OFFSET_4 */ +#define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_SRC_STRIDE_4 */ +#define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_BASE_ADDR_LO */ +#define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_BASE_ADDR_HI */ +#define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_BASE_0 */ +#define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_SIZE_0 */ +#define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 */ +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_START_OFFSET_0 */ +#define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_STRIDE_0 */ +#define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_BASE_1 */ +#define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_SIZE_1 */ +#define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 */ +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_START_OFFSET_1 */ +#define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_STRIDE_1 */ +#define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_BASE_2 */ +#define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_SIZE_2 */ +#define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 */ +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_START_OFFSET_2 */ +#define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_STRIDE_2 */ +#define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_BASE_3 */ +#define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_SIZE_3 */ +#define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 */ +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_START_OFFSET_3 */ +#define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_STRIDE_3 */ +#define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_BASE_4 */ +#define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_ROI_SIZE_4 */ +#define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 */ +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_START_OFFSET_4 */ +#define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_TDMA_DST_STRIDE_4 */ +#define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_SHIFT 0 +#define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA_CH_0_MEM_INIT_BUSY */ +#define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_SHIFT 0 +#define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_MASK 0xFF +#define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_SHIFT 8 +#define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_MASK 0x100 + +#endif /* ASIC_REG_DMA_CH_0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h new file mode 100644 index 000000000..0b246fe6a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_0_REGS_H_ +#define ASIC_REG_DMA_CH_0_REGS_H_ + +/* + ***************************************** + * DMA_CH_0 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_0_CFG0 0x401000 + +#define mmDMA_CH_0_CFG1 0x401004 + +#define mmDMA_CH_0_ERRMSG_ADDR_LO 0x401008 + +#define mmDMA_CH_0_ERRMSG_ADDR_HI 0x40100C + +#define mmDMA_CH_0_ERRMSG_WDATA 0x401010 + +#define mmDMA_CH_0_RD_COMP_ADDR_LO 0x401014 + +#define mmDMA_CH_0_RD_COMP_ADDR_HI 0x401018 + +#define mmDMA_CH_0_RD_COMP_WDATA 0x40101C + +#define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020 + +#define mmDMA_CH_0_WR_COMP_ADDR_HI 0x401024 + +#define mmDMA_CH_0_WR_COMP_WDATA 0x401028 + +#define mmDMA_CH_0_LDMA_SRC_ADDR_LO 0x40102C + +#define mmDMA_CH_0_LDMA_SRC_ADDR_HI 0x401030 + +#define mmDMA_CH_0_LDMA_DST_ADDR_LO 0x401034 + +#define mmDMA_CH_0_LDMA_DST_ADDR_HI 0x401038 + +#define mmDMA_CH_0_LDMA_TSIZE 0x40103C + +#define mmDMA_CH_0_COMIT_TRANSFER 0x401040 + +#define mmDMA_CH_0_STS0 0x401044 + +#define mmDMA_CH_0_STS1 0x401048 + +#define mmDMA_CH_0_STS2 0x40104C + +#define mmDMA_CH_0_STS3 0x401050 + +#define mmDMA_CH_0_STS4 0x401054 + +#define mmDMA_CH_0_SRC_ADDR_LO_STS 0x401058 + +#define mmDMA_CH_0_SRC_ADDR_HI_STS 0x40105C + +#define mmDMA_CH_0_SRC_TSIZE_STS 0x401060 + +#define mmDMA_CH_0_DST_ADDR_LO_STS 0x401064 + +#define mmDMA_CH_0_DST_ADDR_HI_STS 0x401068 + +#define mmDMA_CH_0_DST_TSIZE_STS 0x40106C + +#define mmDMA_CH_0_RD_RATE_LIM_EN 0x401070 + +#define mmDMA_CH_0_RD_RATE_LIM_RST_TOKEN 0x401074 + +#define mmDMA_CH_0_RD_RATE_LIM_SAT 0x401078 + +#define mmDMA_CH_0_RD_RATE_LIM_TOUT 0x40107C + +#define mmDMA_CH_0_WR_RATE_LIM_EN 0x401080 + +#define mmDMA_CH_0_WR_RATE_LIM_RST_TOKEN 0x401084 + +#define mmDMA_CH_0_WR_RATE_LIM_SAT 0x401088 + +#define mmDMA_CH_0_WR_RATE_LIM_TOUT 0x40108C + +#define mmDMA_CH_0_CFG2 0x401090 + +#define mmDMA_CH_0_TDMA_CTL 0x401100 + +#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_LO 0x401104 + +#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_HI 0x401108 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_0 0x40110C + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_0 0x401110 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 0x401114 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_0 0x401118 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_0 0x40111C + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_1 0x401120 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_1 0x401124 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 0x401128 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_1 0x40112C + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_1 0x401130 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_2 0x401134 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_2 0x401138 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 0x40113C + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_2 0x401140 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_2 0x401144 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_3 0x401148 + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_3 0x40114C + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 0x401150 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_3 0x401154 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_3 0x401158 + +#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_4 0x40115C + +#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_4 0x401160 + +#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 0x401164 + +#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_4 0x401168 + +#define mmDMA_CH_0_TDMA_SRC_STRIDE_4 0x40116C + +#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_LO 0x401170 + +#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_HI 0x401174 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_0 0x401178 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_0 0x40117C + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 0x401180 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_0 0x401184 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_0 0x401188 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_1 0x40118C + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_1 0x401190 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 0x401194 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_1 0x401198 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_1 0x40119C + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_2 0x4011A0 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_2 0x4011A4 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 0x4011A8 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_2 0x4011AC + +#define mmDMA_CH_0_TDMA_DST_STRIDE_2 0x4011B0 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_3 0x4011B4 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_3 0x4011B8 + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 0x4011BC + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_3 0x4011C0 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_3 0x4011C4 + +#define mmDMA_CH_0_TDMA_DST_ROI_BASE_4 0x4011C8 + +#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_4 0x4011CC + +#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 0x4011D0 + +#define mmDMA_CH_0_TDMA_DST_START_OFFSET_4 0x4011D4 + +#define mmDMA_CH_0_TDMA_DST_STRIDE_4 0x4011D8 + +#define mmDMA_CH_0_MEM_INIT_BUSY 0x4011FC + +#endif /* ASIC_REG_DMA_CH_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h new file mode 100644 index 000000000..544903172 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_1_REGS_H_ +#define ASIC_REG_DMA_CH_1_REGS_H_ + +/* + ***************************************** + * DMA_CH_1 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_1_CFG0 0x409000 + +#define mmDMA_CH_1_CFG1 0x409004 + +#define mmDMA_CH_1_ERRMSG_ADDR_LO 0x409008 + +#define mmDMA_CH_1_ERRMSG_ADDR_HI 0x40900C + +#define mmDMA_CH_1_ERRMSG_WDATA 0x409010 + +#define mmDMA_CH_1_RD_COMP_ADDR_LO 0x409014 + +#define mmDMA_CH_1_RD_COMP_ADDR_HI 0x409018 + +#define mmDMA_CH_1_RD_COMP_WDATA 0x40901C + +#define mmDMA_CH_1_WR_COMP_ADDR_LO 0x409020 + +#define mmDMA_CH_1_WR_COMP_ADDR_HI 0x409024 + +#define mmDMA_CH_1_WR_COMP_WDATA 0x409028 + +#define mmDMA_CH_1_LDMA_SRC_ADDR_LO 0x40902C + +#define mmDMA_CH_1_LDMA_SRC_ADDR_HI 0x409030 + +#define mmDMA_CH_1_LDMA_DST_ADDR_LO 0x409034 + +#define mmDMA_CH_1_LDMA_DST_ADDR_HI 0x409038 + +#define mmDMA_CH_1_LDMA_TSIZE 0x40903C + +#define mmDMA_CH_1_COMIT_TRANSFER 0x409040 + +#define mmDMA_CH_1_STS0 0x409044 + +#define mmDMA_CH_1_STS1 0x409048 + +#define mmDMA_CH_1_STS2 0x40904C + +#define mmDMA_CH_1_STS3 0x409050 + +#define mmDMA_CH_1_STS4 0x409054 + +#define mmDMA_CH_1_SRC_ADDR_LO_STS 0x409058 + +#define mmDMA_CH_1_SRC_ADDR_HI_STS 0x40905C + +#define mmDMA_CH_1_SRC_TSIZE_STS 0x409060 + +#define mmDMA_CH_1_DST_ADDR_LO_STS 0x409064 + +#define mmDMA_CH_1_DST_ADDR_HI_STS 0x409068 + +#define mmDMA_CH_1_DST_TSIZE_STS 0x40906C + +#define mmDMA_CH_1_RD_RATE_LIM_EN 0x409070 + +#define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN 0x409074 + +#define mmDMA_CH_1_RD_RATE_LIM_SAT 0x409078 + +#define mmDMA_CH_1_RD_RATE_LIM_TOUT 0x40907C + +#define mmDMA_CH_1_WR_RATE_LIM_EN 0x409080 + +#define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN 0x409084 + +#define mmDMA_CH_1_WR_RATE_LIM_SAT 0x409088 + +#define mmDMA_CH_1_WR_RATE_LIM_TOUT 0x40908C + +#define mmDMA_CH_1_CFG2 0x409090 + +#define mmDMA_CH_1_TDMA_CTL 0x409100 + +#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO 0x409104 + +#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI 0x409108 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0 0x40910C + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_0 0x409110 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_0 0x409114 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_0 0x409118 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_0 0x40911C + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_1 0x409120 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_1 0x409124 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_1 0x409128 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_1 0x40912C + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_1 0x409130 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_2 0x409134 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_2 0x409138 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_2 0x40913C + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_2 0x409140 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_2 0x409144 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_3 0x409148 + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_3 0x40914C + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_3 0x409150 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_3 0x409154 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_3 0x409158 + +#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_4 0x40915C + +#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_4 0x409160 + +#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_4 0x409164 + +#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_4 0x409168 + +#define mmDMA_CH_1_TDMA_SRC_STRIDE_4 0x40916C + +#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_LO 0x409170 + +#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_HI 0x409174 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_0 0x409178 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_0 0x40917C + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_0 0x409180 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_0 0x409184 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_0 0x409188 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_1 0x40918C + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_1 0x409190 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_1 0x409194 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_1 0x409198 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_1 0x40919C + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_2 0x4091A0 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_2 0x4091A4 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_2 0x4091A8 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_2 0x4091AC + +#define mmDMA_CH_1_TDMA_DST_STRIDE_2 0x4091B0 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_3 0x4091B4 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_3 0x4091B8 + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_3 0x4091BC + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_3 0x4091C0 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_3 0x4091C4 + +#define mmDMA_CH_1_TDMA_DST_ROI_BASE_4 0x4091C8 + +#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_4 0x4091CC + +#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_4 0x4091D0 + +#define mmDMA_CH_1_TDMA_DST_START_OFFSET_4 0x4091D4 + +#define mmDMA_CH_1_TDMA_DST_STRIDE_4 0x4091D8 + +#define mmDMA_CH_1_MEM_INIT_BUSY 0x4091FC + +#endif /* ASIC_REG_DMA_CH_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h new file mode 100644 index 000000000..a4768521d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_2_REGS_H_ +#define ASIC_REG_DMA_CH_2_REGS_H_ + +/* + ***************************************** + * DMA_CH_2 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_2_CFG0 0x411000 + +#define mmDMA_CH_2_CFG1 0x411004 + +#define mmDMA_CH_2_ERRMSG_ADDR_LO 0x411008 + +#define mmDMA_CH_2_ERRMSG_ADDR_HI 0x41100C + +#define mmDMA_CH_2_ERRMSG_WDATA 0x411010 + +#define mmDMA_CH_2_RD_COMP_ADDR_LO 0x411014 + +#define mmDMA_CH_2_RD_COMP_ADDR_HI 0x411018 + +#define mmDMA_CH_2_RD_COMP_WDATA 0x41101C + +#define mmDMA_CH_2_WR_COMP_ADDR_LO 0x411020 + +#define mmDMA_CH_2_WR_COMP_ADDR_HI 0x411024 + +#define mmDMA_CH_2_WR_COMP_WDATA 0x411028 + +#define mmDMA_CH_2_LDMA_SRC_ADDR_LO 0x41102C + +#define mmDMA_CH_2_LDMA_SRC_ADDR_HI 0x411030 + +#define mmDMA_CH_2_LDMA_DST_ADDR_LO 0x411034 + +#define mmDMA_CH_2_LDMA_DST_ADDR_HI 0x411038 + +#define mmDMA_CH_2_LDMA_TSIZE 0x41103C + +#define mmDMA_CH_2_COMIT_TRANSFER 0x411040 + +#define mmDMA_CH_2_STS0 0x411044 + +#define mmDMA_CH_2_STS1 0x411048 + +#define mmDMA_CH_2_STS2 0x41104C + +#define mmDMA_CH_2_STS3 0x411050 + +#define mmDMA_CH_2_STS4 0x411054 + +#define mmDMA_CH_2_SRC_ADDR_LO_STS 0x411058 + +#define mmDMA_CH_2_SRC_ADDR_HI_STS 0x41105C + +#define mmDMA_CH_2_SRC_TSIZE_STS 0x411060 + +#define mmDMA_CH_2_DST_ADDR_LO_STS 0x411064 + +#define mmDMA_CH_2_DST_ADDR_HI_STS 0x411068 + +#define mmDMA_CH_2_DST_TSIZE_STS 0x41106C + +#define mmDMA_CH_2_RD_RATE_LIM_EN 0x411070 + +#define mmDMA_CH_2_RD_RATE_LIM_RST_TOKEN 0x411074 + +#define mmDMA_CH_2_RD_RATE_LIM_SAT 0x411078 + +#define mmDMA_CH_2_RD_RATE_LIM_TOUT 0x41107C + +#define mmDMA_CH_2_WR_RATE_LIM_EN 0x411080 + +#define mmDMA_CH_2_WR_RATE_LIM_RST_TOKEN 0x411084 + +#define mmDMA_CH_2_WR_RATE_LIM_SAT 0x411088 + +#define mmDMA_CH_2_WR_RATE_LIM_TOUT 0x41108C + +#define mmDMA_CH_2_CFG2 0x411090 + +#define mmDMA_CH_2_TDMA_CTL 0x411100 + +#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_LO 0x411104 + +#define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_HI 0x411108 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_0 0x41110C + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_0 0x411110 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_0 0x411114 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_0 0x411118 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_0 0x41111C + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_1 0x411120 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_1 0x411124 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_1 0x411128 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_1 0x41112C + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_1 0x411130 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_2 0x411134 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_2 0x411138 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_2 0x41113C + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_2 0x411140 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_2 0x411144 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_3 0x411148 + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_3 0x41114C + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_3 0x411150 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_3 0x411154 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_3 0x411158 + +#define mmDMA_CH_2_TDMA_SRC_ROI_BASE_4 0x41115C + +#define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_4 0x411160 + +#define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_4 0x411164 + +#define mmDMA_CH_2_TDMA_SRC_START_OFFSET_4 0x411168 + +#define mmDMA_CH_2_TDMA_SRC_STRIDE_4 0x41116C + +#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_LO 0x411170 + +#define mmDMA_CH_2_TDMA_DST_BASE_ADDR_HI 0x411174 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_0 0x411178 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_0 0x41117C + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_0 0x411180 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_0 0x411184 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_0 0x411188 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_1 0x41118C + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_1 0x411190 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_1 0x411194 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_1 0x411198 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_1 0x41119C + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_2 0x4111A0 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_2 0x4111A4 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_2 0x4111A8 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_2 0x4111AC + +#define mmDMA_CH_2_TDMA_DST_STRIDE_2 0x4111B0 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_3 0x4111B4 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_3 0x4111B8 + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_3 0x4111BC + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_3 0x4111C0 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_3 0x4111C4 + +#define mmDMA_CH_2_TDMA_DST_ROI_BASE_4 0x4111C8 + +#define mmDMA_CH_2_TDMA_DST_ROI_SIZE_4 0x4111CC + +#define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_4 0x4111D0 + +#define mmDMA_CH_2_TDMA_DST_START_OFFSET_4 0x4111D4 + +#define mmDMA_CH_2_TDMA_DST_STRIDE_4 0x4111D8 + +#define mmDMA_CH_2_MEM_INIT_BUSY 0x4111FC + +#endif /* ASIC_REG_DMA_CH_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h new file mode 100644 index 000000000..619d01897 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_3_REGS_H_ +#define ASIC_REG_DMA_CH_3_REGS_H_ + +/* + ***************************************** + * DMA_CH_3 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_3_CFG0 0x419000 + +#define mmDMA_CH_3_CFG1 0x419004 + +#define mmDMA_CH_3_ERRMSG_ADDR_LO 0x419008 + +#define mmDMA_CH_3_ERRMSG_ADDR_HI 0x41900C + +#define mmDMA_CH_3_ERRMSG_WDATA 0x419010 + +#define mmDMA_CH_3_RD_COMP_ADDR_LO 0x419014 + +#define mmDMA_CH_3_RD_COMP_ADDR_HI 0x419018 + +#define mmDMA_CH_3_RD_COMP_WDATA 0x41901C + +#define mmDMA_CH_3_WR_COMP_ADDR_LO 0x419020 + +#define mmDMA_CH_3_WR_COMP_ADDR_HI 0x419024 + +#define mmDMA_CH_3_WR_COMP_WDATA 0x419028 + +#define mmDMA_CH_3_LDMA_SRC_ADDR_LO 0x41902C + +#define mmDMA_CH_3_LDMA_SRC_ADDR_HI 0x419030 + +#define mmDMA_CH_3_LDMA_DST_ADDR_LO 0x419034 + +#define mmDMA_CH_3_LDMA_DST_ADDR_HI 0x419038 + +#define mmDMA_CH_3_LDMA_TSIZE 0x41903C + +#define mmDMA_CH_3_COMIT_TRANSFER 0x419040 + +#define mmDMA_CH_3_STS0 0x419044 + +#define mmDMA_CH_3_STS1 0x419048 + +#define mmDMA_CH_3_STS2 0x41904C + +#define mmDMA_CH_3_STS3 0x419050 + +#define mmDMA_CH_3_STS4 0x419054 + +#define mmDMA_CH_3_SRC_ADDR_LO_STS 0x419058 + +#define mmDMA_CH_3_SRC_ADDR_HI_STS 0x41905C + +#define mmDMA_CH_3_SRC_TSIZE_STS 0x419060 + +#define mmDMA_CH_3_DST_ADDR_LO_STS 0x419064 + +#define mmDMA_CH_3_DST_ADDR_HI_STS 0x419068 + +#define mmDMA_CH_3_DST_TSIZE_STS 0x41906C + +#define mmDMA_CH_3_RD_RATE_LIM_EN 0x419070 + +#define mmDMA_CH_3_RD_RATE_LIM_RST_TOKEN 0x419074 + +#define mmDMA_CH_3_RD_RATE_LIM_SAT 0x419078 + +#define mmDMA_CH_3_RD_RATE_LIM_TOUT 0x41907C + +#define mmDMA_CH_3_WR_RATE_LIM_EN 0x419080 + +#define mmDMA_CH_3_WR_RATE_LIM_RST_TOKEN 0x419084 + +#define mmDMA_CH_3_WR_RATE_LIM_SAT 0x419088 + +#define mmDMA_CH_3_WR_RATE_LIM_TOUT 0x41908C + +#define mmDMA_CH_3_CFG2 0x419090 + +#define mmDMA_CH_3_TDMA_CTL 0x419100 + +#define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_LO 0x419104 + +#define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_HI 0x419108 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_0 0x41910C + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_0 0x419110 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_0 0x419114 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_0 0x419118 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_0 0x41911C + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_1 0x419120 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_1 0x419124 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_1 0x419128 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_1 0x41912C + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_1 0x419130 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_2 0x419134 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_2 0x419138 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_2 0x41913C + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_2 0x419140 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_2 0x419144 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_3 0x419148 + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_3 0x41914C + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_3 0x419150 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_3 0x419154 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_3 0x419158 + +#define mmDMA_CH_3_TDMA_SRC_ROI_BASE_4 0x41915C + +#define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_4 0x419160 + +#define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_4 0x419164 + +#define mmDMA_CH_3_TDMA_SRC_START_OFFSET_4 0x419168 + +#define mmDMA_CH_3_TDMA_SRC_STRIDE_4 0x41916C + +#define mmDMA_CH_3_TDMA_DST_BASE_ADDR_LO 0x419170 + +#define mmDMA_CH_3_TDMA_DST_BASE_ADDR_HI 0x419174 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_0 0x419178 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_0 0x41917C + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_0 0x419180 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_0 0x419184 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_0 0x419188 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_1 0x41918C + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_1 0x419190 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_1 0x419194 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_1 0x419198 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_1 0x41919C + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_2 0x4191A0 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_2 0x4191A4 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_2 0x4191A8 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_2 0x4191AC + +#define mmDMA_CH_3_TDMA_DST_STRIDE_2 0x4191B0 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_3 0x4191B4 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_3 0x4191B8 + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_3 0x4191BC + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_3 0x4191C0 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_3 0x4191C4 + +#define mmDMA_CH_3_TDMA_DST_ROI_BASE_4 0x4191C8 + +#define mmDMA_CH_3_TDMA_DST_ROI_SIZE_4 0x4191CC + +#define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_4 0x4191D0 + +#define mmDMA_CH_3_TDMA_DST_START_OFFSET_4 0x4191D4 + +#define mmDMA_CH_3_TDMA_DST_STRIDE_4 0x4191D8 + +#define mmDMA_CH_3_MEM_INIT_BUSY 0x4191FC + +#endif /* ASIC_REG_DMA_CH_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h new file mode 100644 index 000000000..038617e16 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_CH_4_REGS_H_ +#define ASIC_REG_DMA_CH_4_REGS_H_ + +/* + ***************************************** + * DMA_CH_4 (Prototype: DMA_CH) + ***************************************** + */ + +#define mmDMA_CH_4_CFG0 0x421000 + +#define mmDMA_CH_4_CFG1 0x421004 + +#define mmDMA_CH_4_ERRMSG_ADDR_LO 0x421008 + +#define mmDMA_CH_4_ERRMSG_ADDR_HI 0x42100C + +#define mmDMA_CH_4_ERRMSG_WDATA 0x421010 + +#define mmDMA_CH_4_RD_COMP_ADDR_LO 0x421014 + +#define mmDMA_CH_4_RD_COMP_ADDR_HI 0x421018 + +#define mmDMA_CH_4_RD_COMP_WDATA 0x42101C + +#define mmDMA_CH_4_WR_COMP_ADDR_LO 0x421020 + +#define mmDMA_CH_4_WR_COMP_ADDR_HI 0x421024 + +#define mmDMA_CH_4_WR_COMP_WDATA 0x421028 + +#define mmDMA_CH_4_LDMA_SRC_ADDR_LO 0x42102C + +#define mmDMA_CH_4_LDMA_SRC_ADDR_HI 0x421030 + +#define mmDMA_CH_4_LDMA_DST_ADDR_LO 0x421034 + +#define mmDMA_CH_4_LDMA_DST_ADDR_HI 0x421038 + +#define mmDMA_CH_4_LDMA_TSIZE 0x42103C + +#define mmDMA_CH_4_COMIT_TRANSFER 0x421040 + +#define mmDMA_CH_4_STS0 0x421044 + +#define mmDMA_CH_4_STS1 0x421048 + +#define mmDMA_CH_4_STS2 0x42104C + +#define mmDMA_CH_4_STS3 0x421050 + +#define mmDMA_CH_4_STS4 0x421054 + +#define mmDMA_CH_4_SRC_ADDR_LO_STS 0x421058 + +#define mmDMA_CH_4_SRC_ADDR_HI_STS 0x42105C + +#define mmDMA_CH_4_SRC_TSIZE_STS 0x421060 + +#define mmDMA_CH_4_DST_ADDR_LO_STS 0x421064 + +#define mmDMA_CH_4_DST_ADDR_HI_STS 0x421068 + +#define mmDMA_CH_4_DST_TSIZE_STS 0x42106C + +#define mmDMA_CH_4_RD_RATE_LIM_EN 0x421070 + +#define mmDMA_CH_4_RD_RATE_LIM_RST_TOKEN 0x421074 + +#define mmDMA_CH_4_RD_RATE_LIM_SAT 0x421078 + +#define mmDMA_CH_4_RD_RATE_LIM_TOUT 0x42107C + +#define mmDMA_CH_4_WR_RATE_LIM_EN 0x421080 + +#define mmDMA_CH_4_WR_RATE_LIM_RST_TOKEN 0x421084 + +#define mmDMA_CH_4_WR_RATE_LIM_SAT 0x421088 + +#define mmDMA_CH_4_WR_RATE_LIM_TOUT 0x42108C + +#define mmDMA_CH_4_CFG2 0x421090 + +#define mmDMA_CH_4_TDMA_CTL 0x421100 + +#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_LO 0x421104 + +#define mmDMA_CH_4_TDMA_SRC_BASE_ADDR_HI 0x421108 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_0 0x42110C + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_0 0x421110 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_0 0x421114 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_0 0x421118 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_0 0x42111C + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_1 0x421120 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_1 0x421124 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_1 0x421128 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_1 0x42112C + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_1 0x421130 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_2 0x421134 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_2 0x421138 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_2 0x42113C + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_2 0x421140 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_2 0x421144 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_3 0x421148 + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_3 0x42114C + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_3 0x421150 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_3 0x421154 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_3 0x421158 + +#define mmDMA_CH_4_TDMA_SRC_ROI_BASE_4 0x42115C + +#define mmDMA_CH_4_TDMA_SRC_ROI_SIZE_4 0x421160 + +#define mmDMA_CH_4_TDMA_SRC_VALID_ELEMENTS_4 0x421164 + +#define mmDMA_CH_4_TDMA_SRC_START_OFFSET_4 0x421168 + +#define mmDMA_CH_4_TDMA_SRC_STRIDE_4 0x42116C + +#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_LO 0x421170 + +#define mmDMA_CH_4_TDMA_DST_BASE_ADDR_HI 0x421174 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_0 0x421178 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_0 0x42117C + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_0 0x421180 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_0 0x421184 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_0 0x421188 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_1 0x42118C + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_1 0x421190 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_1 0x421194 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_1 0x421198 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_1 0x42119C + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_2 0x4211A0 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_2 0x4211A4 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_2 0x4211A8 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_2 0x4211AC + +#define mmDMA_CH_4_TDMA_DST_STRIDE_2 0x4211B0 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_3 0x4211B4 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_3 0x4211B8 + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_3 0x4211BC + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_3 0x4211C0 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_3 0x4211C4 + +#define mmDMA_CH_4_TDMA_DST_ROI_BASE_4 0x4211C8 + +#define mmDMA_CH_4_TDMA_DST_ROI_SIZE_4 0x4211CC + +#define mmDMA_CH_4_TDMA_DST_VALID_ELEMENTS_4 0x4211D0 + +#define mmDMA_CH_4_TDMA_DST_START_OFFSET_4 0x4211D4 + +#define mmDMA_CH_4_TDMA_DST_STRIDE_4 0x4211D8 + +#define mmDMA_CH_4_MEM_INIT_BUSY 0x4211FC + +#endif /* ASIC_REG_DMA_CH_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h new file mode 100644 index 000000000..f43b564af --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_MACRO_MASKS_H_ +#define ASIC_REG_DMA_MACRO_MASKS_H_ + +/* + ***************************************** + * DMA_MACRO (Prototype: DMA_MACRO) + ***************************************** + */ + +/* DMA_MACRO_LBW_RANGE_HIT_BLOCK */ +#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF + +/* DMA_MACRO_LBW_RANGE_MASK */ +#define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF + +/* DMA_MACRO_LBW_RANGE_BASE */ +#define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0 +#define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF + +/* DMA_MACRO_HBW_RANGE_HIT_BLOCK */ +#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF + +/* DMA_MACRO_HBW_RANGE_MASK_49_32 */ +#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF + +/* DMA_MACRO_HBW_RANGE_MASK_31_0 */ +#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF + +/* DMA_MACRO_HBW_RANGE_BASE_49_32 */ +#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF + +/* DMA_MACRO_HBW_RANGE_BASE_31_0 */ +#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 0 +#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF + +/* DMA_MACRO_WRITE_EN */ +#define DMA_MACRO_WRITE_EN_R_SHIFT 0 +#define DMA_MACRO_WRITE_EN_R_MASK 0x1 + +/* DMA_MACRO_WRITE_CREDIT */ +#define DMA_MACRO_WRITE_CREDIT_R_SHIFT 0 +#define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF + +/* DMA_MACRO_READ_EN */ +#define DMA_MACRO_READ_EN_R_SHIFT 0 +#define DMA_MACRO_READ_EN_R_MASK 0x1 + +/* DMA_MACRO_READ_CREDIT */ +#define DMA_MACRO_READ_CREDIT_R_SHIFT 0 +#define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF + +/* DMA_MACRO_SRAM_BUSY */ + +/* DMA_MACRO_RAZWI_LBW_WT_VLD */ +#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_LBW_WT_ID */ +#define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF + +/* DMA_MACRO_RAZWI_LBW_RD_VLD */ +#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_LBW_RD_ID */ +#define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF + +/* DMA_MACRO_RAZWI_HBW_WT_VLD */ +#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_HBW_WT_ID */ +#define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF + +/* DMA_MACRO_RAZWI_HBW_RD_VLD */ +#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x1 + +/* DMA_MACRO_RAZWI_HBW_RD_ID */ +#define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0 +#define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF + +#endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h new file mode 100644 index 000000000..c3bfc1b8e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_MACRO_REGS_H_ +#define ASIC_REG_DMA_MACRO_REGS_H_ + +/* + ***************************************** + * DMA_MACRO (Prototype: DMA_MACRO) + ***************************************** + */ + +#define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK 0x4B0000 + +#define mmDMA_MACRO_LBW_RANGE_MASK_0 0x4B0004 + +#define mmDMA_MACRO_LBW_RANGE_MASK_1 0x4B0008 + +#define mmDMA_MACRO_LBW_RANGE_MASK_2 0x4B000C + +#define mmDMA_MACRO_LBW_RANGE_MASK_3 0x4B0010 + +#define mmDMA_MACRO_LBW_RANGE_MASK_4 0x4B0014 + +#define mmDMA_MACRO_LBW_RANGE_MASK_5 0x4B0018 + +#define mmDMA_MACRO_LBW_RANGE_MASK_6 0x4B001C + +#define mmDMA_MACRO_LBW_RANGE_MASK_7 0x4B0020 + +#define mmDMA_MACRO_LBW_RANGE_MASK_8 0x4B0024 + +#define mmDMA_MACRO_LBW_RANGE_MASK_9 0x4B0028 + +#define mmDMA_MACRO_LBW_RANGE_MASK_10 0x4B002C + +#define mmDMA_MACRO_LBW_RANGE_MASK_11 0x4B0030 + +#define mmDMA_MACRO_LBW_RANGE_MASK_12 0x4B0034 + +#define mmDMA_MACRO_LBW_RANGE_MASK_13 0x4B0038 + +#define mmDMA_MACRO_LBW_RANGE_MASK_14 0x4B003C + +#define mmDMA_MACRO_LBW_RANGE_MASK_15 0x4B0040 + +#define mmDMA_MACRO_LBW_RANGE_BASE_0 0x4B0044 + +#define mmDMA_MACRO_LBW_RANGE_BASE_1 0x4B0048 + +#define mmDMA_MACRO_LBW_RANGE_BASE_2 0x4B004C + +#define mmDMA_MACRO_LBW_RANGE_BASE_3 0x4B0050 + +#define mmDMA_MACRO_LBW_RANGE_BASE_4 0x4B0054 + +#define mmDMA_MACRO_LBW_RANGE_BASE_5 0x4B0058 + +#define mmDMA_MACRO_LBW_RANGE_BASE_6 0x4B005C + +#define mmDMA_MACRO_LBW_RANGE_BASE_7 0x4B0060 + +#define mmDMA_MACRO_LBW_RANGE_BASE_8 0x4B0064 + +#define mmDMA_MACRO_LBW_RANGE_BASE_9 0x4B0068 + +#define mmDMA_MACRO_LBW_RANGE_BASE_10 0x4B006C + +#define mmDMA_MACRO_LBW_RANGE_BASE_11 0x4B0070 + +#define mmDMA_MACRO_LBW_RANGE_BASE_12 0x4B0074 + +#define mmDMA_MACRO_LBW_RANGE_BASE_13 0x4B0078 + +#define mmDMA_MACRO_LBW_RANGE_BASE_14 0x4B007C + +#define mmDMA_MACRO_LBW_RANGE_BASE_15 0x4B0080 + +#define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK 0x4B0084 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0 0x4B00A8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1 0x4B00AC + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2 0x4B00B0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3 0x4B00B4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4 0x4B00B8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5 0x4B00BC + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6 0x4B00C0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_7 0x4B00C4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_0 0x4B00C8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_1 0x4B00CC + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_2 0x4B00D0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_3 0x4B00D4 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_4 0x4B00D8 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_5 0x4B00DC + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_6 0x4B00E0 + +#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_7 0x4B00E4 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_0 0x4B00E8 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_1 0x4B00EC + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_2 0x4B00F0 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_3 0x4B00F4 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_4 0x4B00F8 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_5 0x4B00FC + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_6 0x4B0100 + +#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_7 0x4B0104 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_0 0x4B0108 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_1 0x4B010C + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_2 0x4B0110 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_3 0x4B0114 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_4 0x4B0118 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_5 0x4B011C + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_6 0x4B0120 + +#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_7 0x4B0124 + +#define mmDMA_MACRO_WRITE_EN 0x4B0128 + +#define mmDMA_MACRO_WRITE_CREDIT 0x4B012C + +#define mmDMA_MACRO_READ_EN 0x4B0130 + +#define mmDMA_MACRO_READ_CREDIT 0x4B0134 + +#define mmDMA_MACRO_SRAM_BUSY 0x4B0138 + +#define mmDMA_MACRO_RAZWI_LBW_WT_VLD 0x4B013C + +#define mmDMA_MACRO_RAZWI_LBW_WT_ID 0x4B0140 + +#define mmDMA_MACRO_RAZWI_LBW_RD_VLD 0x4B0144 + +#define mmDMA_MACRO_RAZWI_LBW_RD_ID 0x4B0148 + +#define mmDMA_MACRO_RAZWI_HBW_WT_VLD 0x4B014C + +#define mmDMA_MACRO_RAZWI_HBW_WT_ID 0x4B0150 + +#define mmDMA_MACRO_RAZWI_HBW_RD_VLD 0x4B0154 + +#define mmDMA_MACRO_RAZWI_HBW_RD_ID 0x4B0158 + +#endif /* ASIC_REG_DMA_MACRO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h new file mode 100644 index 000000000..bc977488c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_NRTR_MASKS_H_ +#define ASIC_REG_DMA_NRTR_MASKS_H_ + +/* + ***************************************** + * DMA_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* DMA_NRTR_HBW_MAX_CRED */ +#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define DMA_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define DMA_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* DMA_NRTR_LBW_MAX_CRED */ +#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define DMA_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define DMA_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* DMA_NRTR_DBG_E_ARB */ +#define DMA_NRTR_DBG_E_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_E_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_E_ARB_S_SHIFT 8 +#define DMA_NRTR_DBG_E_ARB_S_MASK 0x700 +#define DMA_NRTR_DBG_E_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_E_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_W_ARB */ +#define DMA_NRTR_DBG_W_ARB_E_SHIFT 0 +#define DMA_NRTR_DBG_W_ARB_E_MASK 0x7 +#define DMA_NRTR_DBG_W_ARB_S_SHIFT 8 +#define DMA_NRTR_DBG_W_ARB_S_MASK 0x700 +#define DMA_NRTR_DBG_W_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_W_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_N_ARB */ +#define DMA_NRTR_DBG_N_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_N_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_N_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_N_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_N_ARB_S_SHIFT 16 +#define DMA_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define DMA_NRTR_DBG_N_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_S_ARB */ +#define DMA_NRTR_DBG_S_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_S_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_S_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_S_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_S_ARB_N_SHIFT 16 +#define DMA_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define DMA_NRTR_DBG_S_ARB_L_SHIFT 24 +#define DMA_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* DMA_NRTR_DBG_L_ARB */ +#define DMA_NRTR_DBG_L_ARB_W_SHIFT 0 +#define DMA_NRTR_DBG_L_ARB_W_MASK 0x7 +#define DMA_NRTR_DBG_L_ARB_E_SHIFT 8 +#define DMA_NRTR_DBG_L_ARB_E_MASK 0x700 +#define DMA_NRTR_DBG_L_ARB_S_SHIFT 16 +#define DMA_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define DMA_NRTR_DBG_L_ARB_N_SHIFT 24 +#define DMA_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* DMA_NRTR_DBG_E_ARB_MAX */ +#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_W_ARB_MAX */ +#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_N_ARB_MAX */ +#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_S_ARB_MAX */ +#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_DBG_L_ARB_MAX */ +#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* DMA_NRTR_SPLIT_COEF */ +#define DMA_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_CFG */ +#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define DMA_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define DMA_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* DMA_NRTR_SPLIT_RD_SAT */ +#define DMA_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_RD_RST_TOKEN */ +#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_RD_TIMEOUT */ +#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_SPLIT_WR_SAT */ +#define DMA_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* DMA_NRTR_WPLIT_WR_TST_TOLEN */ +#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* DMA_NRTR_SPLIT_WR_TIMEOUT */ +#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_HIT */ +#define DMA_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* DMA_NRTR_HBW_RANGE_MASK_L */ +#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_MASK_H */ +#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* DMA_NRTR_HBW_RANGE_BASE_L */ +#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* DMA_NRTR_HBW_RANGE_BASE_H */ +#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define DMA_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* DMA_NRTR_LBW_RANGE_HIT */ +#define DMA_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* DMA_NRTR_LBW_RANGE_MASK */ +#define DMA_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* DMA_NRTR_LBW_RANGE_BASE */ +#define DMA_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define DMA_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* DMA_NRTR_RGLTR */ +#define DMA_NRTR_RGLTR_WR_EN_SHIFT 0 +#define DMA_NRTR_RGLTR_WR_EN_MASK 0x1 +#define DMA_NRTR_RGLTR_RD_EN_SHIFT 4 +#define DMA_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* DMA_NRTR_RGLTR_WR_RESULT */ +#define DMA_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define DMA_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* DMA_NRTR_RGLTR_RD_RESULT */ +#define DMA_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define DMA_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* DMA_NRTR_SCRAMB_EN */ +#define DMA_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define DMA_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* DMA_NRTR_NON_LIN_SCRAMB */ +#define DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define DMA_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_DMA_NRTR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h new file mode 100644 index 000000000..c4abc7ff1 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_NRTR_REGS_H_ +#define ASIC_REG_DMA_NRTR_REGS_H_ + +/* + ***************************************** + * DMA_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmDMA_NRTR_HBW_MAX_CRED 0x1C0100 + +#define mmDMA_NRTR_LBW_MAX_CRED 0x1C0120 + +#define mmDMA_NRTR_DBG_E_ARB 0x1C0300 + +#define mmDMA_NRTR_DBG_W_ARB 0x1C0304 + +#define mmDMA_NRTR_DBG_N_ARB 0x1C0308 + +#define mmDMA_NRTR_DBG_S_ARB 0x1C030C + +#define mmDMA_NRTR_DBG_L_ARB 0x1C0310 + +#define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C0320 + +#define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C0324 + +#define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C0328 + +#define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C + +#define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C0330 + +#define mmDMA_NRTR_SPLIT_COEF_0 0x1C0400 + +#define mmDMA_NRTR_SPLIT_COEF_1 0x1C0404 + +#define mmDMA_NRTR_SPLIT_COEF_2 0x1C0408 + +#define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C + +#define mmDMA_NRTR_SPLIT_COEF_4 0x1C0410 + +#define mmDMA_NRTR_SPLIT_COEF_5 0x1C0414 + +#define mmDMA_NRTR_SPLIT_COEF_6 0x1C0418 + +#define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C + +#define mmDMA_NRTR_SPLIT_COEF_8 0x1C0420 + +#define mmDMA_NRTR_SPLIT_COEF_9 0x1C0424 + +#define mmDMA_NRTR_SPLIT_CFG 0x1C0440 + +#define mmDMA_NRTR_SPLIT_RD_SAT 0x1C0444 + +#define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C0448 + +#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C + +#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C0450 + +#define mmDMA_NRTR_SPLIT_WR_SAT 0x1C0454 + +#define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C0458 + +#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C + +#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C0460 + +#define mmDMA_NRTR_HBW_RANGE_HIT 0x1C0470 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C0480 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C0484 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C0488 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C0490 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C0494 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C0498 + +#define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8 + +#define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8 + +#define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC + +#define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500 + +#define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510 + +#define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514 + +#define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518 + +#define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C + +#define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520 + +#define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524 + +#define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528 + +#define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C + +#define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530 + +#define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534 + +#define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538 + +#define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C + +#define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540 + +#define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544 + +#define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548 + +#define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C + +#define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550 + +#define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554 + +#define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558 + +#define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C + +#define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560 + +#define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564 + +#define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568 + +#define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C + +#define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570 + +#define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574 + +#define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578 + +#define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C + +#define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580 + +#define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584 + +#define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588 + +#define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C + +#define mmDMA_NRTR_RGLTR 0x1C0590 + +#define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594 + +#define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598 + +#define mmDMA_NRTR_SCRAMB_EN 0x1C0600 + +#define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604 + +#endif /* ASIC_REG_DMA_NRTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h new file mode 100644 index 000000000..b17f72c31 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_0_MASKS_H_ +#define ASIC_REG_DMA_QM_0_MASKS_H_ + +/* + ***************************************** + * DMA_QM_0 (Prototype: QMAN) + ***************************************** + */ + +/* DMA_QM_0_GLBL_CFG0 */ +#define DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DMA_QM_0_GLBL_CFG0_PQF_EN_MASK 0x1 +#define DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT 1 +#define DMA_QM_0_GLBL_CFG0_CQF_EN_MASK 0x2 +#define DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT 2 +#define DMA_QM_0_GLBL_CFG0_CP_EN_MASK 0x4 +#define DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT 3 +#define DMA_QM_0_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* DMA_QM_0_GLBL_CFG1 */ +#define DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DMA_QM_0_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define DMA_QM_0_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT 2 +#define DMA_QM_0_GLBL_CFG1_CP_STOP_MASK 0x4 +#define DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define DMA_QM_0_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define DMA_QM_0_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define DMA_QM_0_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* DMA_QM_0_GLBL_PROT */ +#define DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT 0 +#define DMA_QM_0_GLBL_PROT_PQF_PROT_MASK 0x1 +#define DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT 1 +#define DMA_QM_0_GLBL_PROT_CQF_PROT_MASK 0x2 +#define DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT 2 +#define DMA_QM_0_GLBL_PROT_CP_PROT_MASK 0x4 +#define DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT 3 +#define DMA_QM_0_GLBL_PROT_DMA_PROT_MASK 0x8 +#define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* DMA_QM_0_GLBL_ERR_CFG */ +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* DMA_QM_0_GLBL_ERR_ADDR_LO */ +#define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_ERR_ADDR_HI */ +#define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_ERR_WDATA */ +#define DMA_QM_0_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DMA_QM_0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_GLBL_SECURE_PROPS */ +#define DMA_QM_0_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define DMA_QM_0_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA_QM_0_GLBL_NON_SECURE_PROPS */ +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA_QM_0_GLBL_STS0 */ +#define DMA_QM_0_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define DMA_QM_0_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define DMA_QM_0_GLBL_STS0_CP_IDLE_SHIFT 2 +#define DMA_QM_0_GLBL_STS0_CP_IDLE_MASK 0x4 +#define DMA_QM_0_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define DMA_QM_0_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* DMA_QM_0_GLBL_STS1 */ +#define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define DMA_QM_0_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define DMA_QM_0_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA_QM_0_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define DMA_QM_0_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* DMA_QM_0_PQ_BASE_LO */ +#define DMA_QM_0_PQ_BASE_LO_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_BASE_HI */ +#define DMA_QM_0_PQ_BASE_HI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_SIZE */ +#define DMA_QM_0_PQ_SIZE_VAL_SHIFT 0 +#define DMA_QM_0_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PI */ +#define DMA_QM_0_PQ_PI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_CI */ +#define DMA_QM_0_PQ_CI_VAL_SHIFT 0 +#define DMA_QM_0_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_CFG0 */ +#define DMA_QM_0_PQ_CFG0_RESERVED_SHIFT 0 +#define DMA_QM_0_PQ_CFG0_RESERVED_MASK 0x1 + +/* DMA_QM_0_PQ_CFG1 */ +#define DMA_QM_0_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA_QM_0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_ARUSER */ +#define DMA_QM_0_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define DMA_QM_0_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define DMA_QM_0_PQ_ARUSER_WORD_SHIFT 1 +#define DMA_QM_0_PQ_ARUSER_WORD_MASK 0x2 + +/* DMA_QM_0_PQ_PUSH0 */ +#define DMA_QM_0_PQ_PUSH0_PTR_LO_SHIFT 0 +#define DMA_QM_0_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH1 */ +#define DMA_QM_0_PQ_PUSH1_PTR_HI_SHIFT 0 +#define DMA_QM_0_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH2 */ +#define DMA_QM_0_PQ_PUSH2_TSIZE_SHIFT 0 +#define DMA_QM_0_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_PUSH3 */ +#define DMA_QM_0_PQ_PUSH3_RPT_SHIFT 0 +#define DMA_QM_0_PQ_PUSH3_RPT_MASK 0xFFFF +#define DMA_QM_0_PQ_PUSH3_CTL_SHIFT 16 +#define DMA_QM_0_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_STS0 */ +#define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA_QM_0_PQ_STS1 */ +#define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define DMA_QM_0_PQ_STS1_PQ_BUSY_SHIFT 31 +#define DMA_QM_0_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* DMA_QM_0_PQ_RD_RATE_LIM_EN */ +#define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN */ +#define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_QM_0_PQ_RD_RATE_LIM_SAT */ +#define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_QM_0_PQ_RD_RATE_LIM_TOUT */ +#define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_QM_0_CQ_CFG0 */ +#define DMA_QM_0_CQ_CFG0_RESERVED_SHIFT 0 +#define DMA_QM_0_CQ_CFG0_RESERVED_MASK 0x1 + +/* DMA_QM_0_CQ_CFG1 */ +#define DMA_QM_0_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA_QM_0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_ARUSER */ +#define DMA_QM_0_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define DMA_QM_0_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define DMA_QM_0_CQ_ARUSER_WORD_SHIFT 1 +#define DMA_QM_0_CQ_ARUSER_WORD_MASK 0x2 + +/* DMA_QM_0_CQ_PTR_LO */ +#define DMA_QM_0_CQ_PTR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_PTR_HI */ +#define DMA_QM_0_CQ_PTR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_TSIZE */ +#define DMA_QM_0_CQ_TSIZE_VAL_SHIFT 0 +#define DMA_QM_0_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_CTL */ +#define DMA_QM_0_CQ_CTL_RPT_SHIFT 0 +#define DMA_QM_0_CQ_CTL_RPT_MASK 0xFFFF +#define DMA_QM_0_CQ_CTL_CTL_SHIFT 16 +#define DMA_QM_0_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_PTR_LO_STS */ +#define DMA_QM_0_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_PTR_HI_STS */ +#define DMA_QM_0_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_TSIZE_STS */ +#define DMA_QM_0_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DMA_QM_0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_CTL_STS */ +#define DMA_QM_0_CQ_CTL_STS_RPT_SHIFT 0 +#define DMA_QM_0_CQ_CTL_STS_RPT_MASK 0xFFFF +#define DMA_QM_0_CQ_CTL_STS_CTL_SHIFT 16 +#define DMA_QM_0_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_STS0 */ +#define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA_QM_0_CQ_STS1 */ +#define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define DMA_QM_0_CQ_STS1_CQ_BUSY_SHIFT 31 +#define DMA_QM_0_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* DMA_QM_0_CQ_RD_RATE_LIM_EN */ +#define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN */ +#define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* DMA_QM_0_CQ_RD_RATE_LIM_SAT */ +#define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* DMA_QM_0_CQ_RD_RATE_LIM_TOUT */ +#define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* DMA_QM_0_CQ_IFIFO_CNT */ +#define DMA_QM_0_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* DMA_QM_0_CP_MSG_BASE0_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE0_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE1_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE1_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE2_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE2_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE3_ADDR_LO */ +#define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_MSG_BASE3_ADDR_HI */ +#define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_TSIZE_OFFSET */ +#define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET */ +#define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_LDMA_COMMIT_OFFSET */ +#define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_FENCE0_RDATA */ +#define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE1_RDATA */ +#define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE2_RDATA */ +#define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE3_RDATA */ +#define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DMA_QM_0_CP_FENCE0_CNT */ +#define DMA_QM_0_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE1_CNT */ +#define DMA_QM_0_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE2_CNT */ +#define DMA_QM_0_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_FENCE3_CNT */ +#define DMA_QM_0_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DMA_QM_0_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* DMA_QM_0_CP_STS */ +#define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define DMA_QM_0_CP_STS_ERDY_SHIFT 16 +#define DMA_QM_0_CP_STS_ERDY_MASK 0x10000 +#define DMA_QM_0_CP_STS_RRDY_SHIFT 17 +#define DMA_QM_0_CP_STS_RRDY_MASK 0x20000 +#define DMA_QM_0_CP_STS_MRDY_SHIFT 18 +#define DMA_QM_0_CP_STS_MRDY_MASK 0x40000 +#define DMA_QM_0_CP_STS_SW_STOP_SHIFT 19 +#define DMA_QM_0_CP_STS_SW_STOP_MASK 0x80000 +#define DMA_QM_0_CP_STS_FENCE_ID_SHIFT 20 +#define DMA_QM_0_CP_STS_FENCE_ID_MASK 0x300000 +#define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* DMA_QM_0_CP_CURRENT_INST_LO */ +#define DMA_QM_0_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DMA_QM_0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_CURRENT_INST_HI */ +#define DMA_QM_0_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DMA_QM_0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CP_BARRIER_CFG */ +#define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* DMA_QM_0_CP_DBG_0 */ +#define DMA_QM_0_CP_DBG_0_VAL_SHIFT 0 +#define DMA_QM_0_CP_DBG_0_VAL_MASK 0xFF + +/* DMA_QM_0_PQ_BUF_ADDR */ +#define DMA_QM_0_PQ_BUF_ADDR_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_PQ_BUF_RDATA */ +#define DMA_QM_0_PQ_BUF_RDATA_VAL_SHIFT 0 +#define DMA_QM_0_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_BUF_ADDR */ +#define DMA_QM_0_CQ_BUF_ADDR_VAL_SHIFT 0 +#define DMA_QM_0_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* DMA_QM_0_CQ_BUF_RDATA */ +#define DMA_QM_0_CQ_BUF_RDATA_VAL_SHIFT 0 +#define DMA_QM_0_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DMA_QM_0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h new file mode 100644 index 000000000..bf360b301 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_0_REGS_H_ +#define ASIC_REG_DMA_QM_0_REGS_H_ + +/* + ***************************************** + * DMA_QM_0 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_0_GLBL_CFG0 0x400000 + +#define mmDMA_QM_0_GLBL_CFG1 0x400004 + +#define mmDMA_QM_0_GLBL_PROT 0x400008 + +#define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C + +#define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010 + +#define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014 + +#define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018 + +#define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C + +#define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020 + +#define mmDMA_QM_0_GLBL_STS0 0x400024 + +#define mmDMA_QM_0_GLBL_STS1 0x400028 + +#define mmDMA_QM_0_PQ_BASE_LO 0x400060 + +#define mmDMA_QM_0_PQ_BASE_HI 0x400064 + +#define mmDMA_QM_0_PQ_SIZE 0x400068 + +#define mmDMA_QM_0_PQ_PI 0x40006C + +#define mmDMA_QM_0_PQ_CI 0x400070 + +#define mmDMA_QM_0_PQ_CFG0 0x400074 + +#define mmDMA_QM_0_PQ_CFG1 0x400078 + +#define mmDMA_QM_0_PQ_ARUSER 0x40007C + +#define mmDMA_QM_0_PQ_PUSH0 0x400080 + +#define mmDMA_QM_0_PQ_PUSH1 0x400084 + +#define mmDMA_QM_0_PQ_PUSH2 0x400088 + +#define mmDMA_QM_0_PQ_PUSH3 0x40008C + +#define mmDMA_QM_0_PQ_STS0 0x400090 + +#define mmDMA_QM_0_PQ_STS1 0x400094 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8 + +#define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC + +#define mmDMA_QM_0_CQ_CFG0 0x4000B0 + +#define mmDMA_QM_0_CQ_CFG1 0x4000B4 + +#define mmDMA_QM_0_CQ_ARUSER 0x4000B8 + +#define mmDMA_QM_0_CQ_PTR_LO 0x4000C0 + +#define mmDMA_QM_0_CQ_PTR_HI 0x4000C4 + +#define mmDMA_QM_0_CQ_TSIZE 0x4000C8 + +#define mmDMA_QM_0_CQ_CTL 0x4000CC + +#define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4 + +#define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8 + +#define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC + +#define mmDMA_QM_0_CQ_CTL_STS 0x4000E0 + +#define mmDMA_QM_0_CQ_STS0 0x4000E4 + +#define mmDMA_QM_0_CQ_STS1 0x4000E8 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8 + +#define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC + +#define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108 + +#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120 + +#define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124 + +#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128 + +#define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C + +#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130 + +#define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134 + +#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138 + +#define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C + +#define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140 + +#define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144 + +#define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148 + +#define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C + +#define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150 + +#define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154 + +#define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158 + +#define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C + +#define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160 + +#define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164 + +#define mmDMA_QM_0_CP_FENCE0_CNT 0x400168 + +#define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C + +#define mmDMA_QM_0_CP_FENCE2_CNT 0x400170 + +#define mmDMA_QM_0_CP_FENCE3_CNT 0x400174 + +#define mmDMA_QM_0_CP_STS 0x400178 + +#define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C + +#define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180 + +#define mmDMA_QM_0_CP_BARRIER_CFG 0x400184 + +#define mmDMA_QM_0_CP_DBG_0 0x400188 + +#define mmDMA_QM_0_PQ_BUF_ADDR 0x400300 + +#define mmDMA_QM_0_PQ_BUF_RDATA 0x400304 + +#define mmDMA_QM_0_CQ_BUF_ADDR 0x400308 + +#define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C + +#endif /* ASIC_REG_DMA_QM_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h new file mode 100644 index 000000000..51d432d05 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_1_REGS_H_ +#define ASIC_REG_DMA_QM_1_REGS_H_ + +/* + ***************************************** + * DMA_QM_1 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_1_GLBL_CFG0 0x408000 + +#define mmDMA_QM_1_GLBL_CFG1 0x408004 + +#define mmDMA_QM_1_GLBL_PROT 0x408008 + +#define mmDMA_QM_1_GLBL_ERR_CFG 0x40800C + +#define mmDMA_QM_1_GLBL_ERR_ADDR_LO 0x408010 + +#define mmDMA_QM_1_GLBL_ERR_ADDR_HI 0x408014 + +#define mmDMA_QM_1_GLBL_ERR_WDATA 0x408018 + +#define mmDMA_QM_1_GLBL_SECURE_PROPS 0x40801C + +#define mmDMA_QM_1_GLBL_NON_SECURE_PROPS 0x408020 + +#define mmDMA_QM_1_GLBL_STS0 0x408024 + +#define mmDMA_QM_1_GLBL_STS1 0x408028 + +#define mmDMA_QM_1_PQ_BASE_LO 0x408060 + +#define mmDMA_QM_1_PQ_BASE_HI 0x408064 + +#define mmDMA_QM_1_PQ_SIZE 0x408068 + +#define mmDMA_QM_1_PQ_PI 0x40806C + +#define mmDMA_QM_1_PQ_CI 0x408070 + +#define mmDMA_QM_1_PQ_CFG0 0x408074 + +#define mmDMA_QM_1_PQ_CFG1 0x408078 + +#define mmDMA_QM_1_PQ_ARUSER 0x40807C + +#define mmDMA_QM_1_PQ_PUSH0 0x408080 + +#define mmDMA_QM_1_PQ_PUSH1 0x408084 + +#define mmDMA_QM_1_PQ_PUSH2 0x408088 + +#define mmDMA_QM_1_PQ_PUSH3 0x40808C + +#define mmDMA_QM_1_PQ_STS0 0x408090 + +#define mmDMA_QM_1_PQ_STS1 0x408094 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_EN 0x4080A0 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN 0x4080A4 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_SAT 0x4080A8 + +#define mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT 0x4080AC + +#define mmDMA_QM_1_CQ_CFG0 0x4080B0 + +#define mmDMA_QM_1_CQ_CFG1 0x4080B4 + +#define mmDMA_QM_1_CQ_ARUSER 0x4080B8 + +#define mmDMA_QM_1_CQ_PTR_LO 0x4080C0 + +#define mmDMA_QM_1_CQ_PTR_HI 0x4080C4 + +#define mmDMA_QM_1_CQ_TSIZE 0x4080C8 + +#define mmDMA_QM_1_CQ_CTL 0x4080CC + +#define mmDMA_QM_1_CQ_PTR_LO_STS 0x4080D4 + +#define mmDMA_QM_1_CQ_PTR_HI_STS 0x4080D8 + +#define mmDMA_QM_1_CQ_TSIZE_STS 0x4080DC + +#define mmDMA_QM_1_CQ_CTL_STS 0x4080E0 + +#define mmDMA_QM_1_CQ_STS0 0x4080E4 + +#define mmDMA_QM_1_CQ_STS1 0x4080E8 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_EN 0x4080F0 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN 0x4080F4 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_SAT 0x4080F8 + +#define mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT 0x4080FC + +#define mmDMA_QM_1_CQ_IFIFO_CNT 0x408108 + +#define mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO 0x408120 + +#define mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI 0x408124 + +#define mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO 0x408128 + +#define mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI 0x40812C + +#define mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO 0x408130 + +#define mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI 0x408134 + +#define mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO 0x408138 + +#define mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI 0x40813C + +#define mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET 0x408140 + +#define mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET 0x408144 + +#define mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET 0x408148 + +#define mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET 0x40814C + +#define mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET 0x408150 + +#define mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET 0x408154 + +#define mmDMA_QM_1_CP_FENCE0_RDATA 0x408158 + +#define mmDMA_QM_1_CP_FENCE1_RDATA 0x40815C + +#define mmDMA_QM_1_CP_FENCE2_RDATA 0x408160 + +#define mmDMA_QM_1_CP_FENCE3_RDATA 0x408164 + +#define mmDMA_QM_1_CP_FENCE0_CNT 0x408168 + +#define mmDMA_QM_1_CP_FENCE1_CNT 0x40816C + +#define mmDMA_QM_1_CP_FENCE2_CNT 0x408170 + +#define mmDMA_QM_1_CP_FENCE3_CNT 0x408174 + +#define mmDMA_QM_1_CP_STS 0x408178 + +#define mmDMA_QM_1_CP_CURRENT_INST_LO 0x40817C + +#define mmDMA_QM_1_CP_CURRENT_INST_HI 0x408180 + +#define mmDMA_QM_1_CP_BARRIER_CFG 0x408184 + +#define mmDMA_QM_1_CP_DBG_0 0x408188 + +#define mmDMA_QM_1_PQ_BUF_ADDR 0x408300 + +#define mmDMA_QM_1_PQ_BUF_RDATA 0x408304 + +#define mmDMA_QM_1_CQ_BUF_ADDR 0x408308 + +#define mmDMA_QM_1_CQ_BUF_RDATA 0x40830C + +#endif /* ASIC_REG_DMA_QM_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h new file mode 100644 index 000000000..18fc0c2b6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_2_REGS_H_ +#define ASIC_REG_DMA_QM_2_REGS_H_ + +/* + ***************************************** + * DMA_QM_2 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_2_GLBL_CFG0 0x410000 + +#define mmDMA_QM_2_GLBL_CFG1 0x410004 + +#define mmDMA_QM_2_GLBL_PROT 0x410008 + +#define mmDMA_QM_2_GLBL_ERR_CFG 0x41000C + +#define mmDMA_QM_2_GLBL_ERR_ADDR_LO 0x410010 + +#define mmDMA_QM_2_GLBL_ERR_ADDR_HI 0x410014 + +#define mmDMA_QM_2_GLBL_ERR_WDATA 0x410018 + +#define mmDMA_QM_2_GLBL_SECURE_PROPS 0x41001C + +#define mmDMA_QM_2_GLBL_NON_SECURE_PROPS 0x410020 + +#define mmDMA_QM_2_GLBL_STS0 0x410024 + +#define mmDMA_QM_2_GLBL_STS1 0x410028 + +#define mmDMA_QM_2_PQ_BASE_LO 0x410060 + +#define mmDMA_QM_2_PQ_BASE_HI 0x410064 + +#define mmDMA_QM_2_PQ_SIZE 0x410068 + +#define mmDMA_QM_2_PQ_PI 0x41006C + +#define mmDMA_QM_2_PQ_CI 0x410070 + +#define mmDMA_QM_2_PQ_CFG0 0x410074 + +#define mmDMA_QM_2_PQ_CFG1 0x410078 + +#define mmDMA_QM_2_PQ_ARUSER 0x41007C + +#define mmDMA_QM_2_PQ_PUSH0 0x410080 + +#define mmDMA_QM_2_PQ_PUSH1 0x410084 + +#define mmDMA_QM_2_PQ_PUSH2 0x410088 + +#define mmDMA_QM_2_PQ_PUSH3 0x41008C + +#define mmDMA_QM_2_PQ_STS0 0x410090 + +#define mmDMA_QM_2_PQ_STS1 0x410094 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_EN 0x4100A0 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN 0x4100A4 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_SAT 0x4100A8 + +#define mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT 0x4100AC + +#define mmDMA_QM_2_CQ_CFG0 0x4100B0 + +#define mmDMA_QM_2_CQ_CFG1 0x4100B4 + +#define mmDMA_QM_2_CQ_ARUSER 0x4100B8 + +#define mmDMA_QM_2_CQ_PTR_LO 0x4100C0 + +#define mmDMA_QM_2_CQ_PTR_HI 0x4100C4 + +#define mmDMA_QM_2_CQ_TSIZE 0x4100C8 + +#define mmDMA_QM_2_CQ_CTL 0x4100CC + +#define mmDMA_QM_2_CQ_PTR_LO_STS 0x4100D4 + +#define mmDMA_QM_2_CQ_PTR_HI_STS 0x4100D8 + +#define mmDMA_QM_2_CQ_TSIZE_STS 0x4100DC + +#define mmDMA_QM_2_CQ_CTL_STS 0x4100E0 + +#define mmDMA_QM_2_CQ_STS0 0x4100E4 + +#define mmDMA_QM_2_CQ_STS1 0x4100E8 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_EN 0x4100F0 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN 0x4100F4 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_SAT 0x4100F8 + +#define mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT 0x4100FC + +#define mmDMA_QM_2_CQ_IFIFO_CNT 0x410108 + +#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO 0x410120 + +#define mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI 0x410124 + +#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO 0x410128 + +#define mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI 0x41012C + +#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO 0x410130 + +#define mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI 0x410134 + +#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO 0x410138 + +#define mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI 0x41013C + +#define mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET 0x410140 + +#define mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET 0x410144 + +#define mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET 0x410148 + +#define mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET 0x41014C + +#define mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET 0x410150 + +#define mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET 0x410154 + +#define mmDMA_QM_2_CP_FENCE0_RDATA 0x410158 + +#define mmDMA_QM_2_CP_FENCE1_RDATA 0x41015C + +#define mmDMA_QM_2_CP_FENCE2_RDATA 0x410160 + +#define mmDMA_QM_2_CP_FENCE3_RDATA 0x410164 + +#define mmDMA_QM_2_CP_FENCE0_CNT 0x410168 + +#define mmDMA_QM_2_CP_FENCE1_CNT 0x41016C + +#define mmDMA_QM_2_CP_FENCE2_CNT 0x410170 + +#define mmDMA_QM_2_CP_FENCE3_CNT 0x410174 + +#define mmDMA_QM_2_CP_STS 0x410178 + +#define mmDMA_QM_2_CP_CURRENT_INST_LO 0x41017C + +#define mmDMA_QM_2_CP_CURRENT_INST_HI 0x410180 + +#define mmDMA_QM_2_CP_BARRIER_CFG 0x410184 + +#define mmDMA_QM_2_CP_DBG_0 0x410188 + +#define mmDMA_QM_2_PQ_BUF_ADDR 0x410300 + +#define mmDMA_QM_2_PQ_BUF_RDATA 0x410304 + +#define mmDMA_QM_2_CQ_BUF_ADDR 0x410308 + +#define mmDMA_QM_2_CQ_BUF_RDATA 0x41030C + +#endif /* ASIC_REG_DMA_QM_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h new file mode 100644 index 000000000..6cf7204bf --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_3_REGS_H_ +#define ASIC_REG_DMA_QM_3_REGS_H_ + +/* + ***************************************** + * DMA_QM_3 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_3_GLBL_CFG0 0x418000 + +#define mmDMA_QM_3_GLBL_CFG1 0x418004 + +#define mmDMA_QM_3_GLBL_PROT 0x418008 + +#define mmDMA_QM_3_GLBL_ERR_CFG 0x41800C + +#define mmDMA_QM_3_GLBL_ERR_ADDR_LO 0x418010 + +#define mmDMA_QM_3_GLBL_ERR_ADDR_HI 0x418014 + +#define mmDMA_QM_3_GLBL_ERR_WDATA 0x418018 + +#define mmDMA_QM_3_GLBL_SECURE_PROPS 0x41801C + +#define mmDMA_QM_3_GLBL_NON_SECURE_PROPS 0x418020 + +#define mmDMA_QM_3_GLBL_STS0 0x418024 + +#define mmDMA_QM_3_GLBL_STS1 0x418028 + +#define mmDMA_QM_3_PQ_BASE_LO 0x418060 + +#define mmDMA_QM_3_PQ_BASE_HI 0x418064 + +#define mmDMA_QM_3_PQ_SIZE 0x418068 + +#define mmDMA_QM_3_PQ_PI 0x41806C + +#define mmDMA_QM_3_PQ_CI 0x418070 + +#define mmDMA_QM_3_PQ_CFG0 0x418074 + +#define mmDMA_QM_3_PQ_CFG1 0x418078 + +#define mmDMA_QM_3_PQ_ARUSER 0x41807C + +#define mmDMA_QM_3_PQ_PUSH0 0x418080 + +#define mmDMA_QM_3_PQ_PUSH1 0x418084 + +#define mmDMA_QM_3_PQ_PUSH2 0x418088 + +#define mmDMA_QM_3_PQ_PUSH3 0x41808C + +#define mmDMA_QM_3_PQ_STS0 0x418090 + +#define mmDMA_QM_3_PQ_STS1 0x418094 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_EN 0x4180A0 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN 0x4180A4 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_SAT 0x4180A8 + +#define mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT 0x4180AC + +#define mmDMA_QM_3_CQ_CFG0 0x4180B0 + +#define mmDMA_QM_3_CQ_CFG1 0x4180B4 + +#define mmDMA_QM_3_CQ_ARUSER 0x4180B8 + +#define mmDMA_QM_3_CQ_PTR_LO 0x4180C0 + +#define mmDMA_QM_3_CQ_PTR_HI 0x4180C4 + +#define mmDMA_QM_3_CQ_TSIZE 0x4180C8 + +#define mmDMA_QM_3_CQ_CTL 0x4180CC + +#define mmDMA_QM_3_CQ_PTR_LO_STS 0x4180D4 + +#define mmDMA_QM_3_CQ_PTR_HI_STS 0x4180D8 + +#define mmDMA_QM_3_CQ_TSIZE_STS 0x4180DC + +#define mmDMA_QM_3_CQ_CTL_STS 0x4180E0 + +#define mmDMA_QM_3_CQ_STS0 0x4180E4 + +#define mmDMA_QM_3_CQ_STS1 0x4180E8 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_EN 0x4180F0 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN 0x4180F4 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_SAT 0x4180F8 + +#define mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT 0x4180FC + +#define mmDMA_QM_3_CQ_IFIFO_CNT 0x418108 + +#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO 0x418120 + +#define mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI 0x418124 + +#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO 0x418128 + +#define mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI 0x41812C + +#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO 0x418130 + +#define mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI 0x418134 + +#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO 0x418138 + +#define mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI 0x41813C + +#define mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET 0x418140 + +#define mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET 0x418144 + +#define mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET 0x418148 + +#define mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET 0x41814C + +#define mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET 0x418150 + +#define mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET 0x418154 + +#define mmDMA_QM_3_CP_FENCE0_RDATA 0x418158 + +#define mmDMA_QM_3_CP_FENCE1_RDATA 0x41815C + +#define mmDMA_QM_3_CP_FENCE2_RDATA 0x418160 + +#define mmDMA_QM_3_CP_FENCE3_RDATA 0x418164 + +#define mmDMA_QM_3_CP_FENCE0_CNT 0x418168 + +#define mmDMA_QM_3_CP_FENCE1_CNT 0x41816C + +#define mmDMA_QM_3_CP_FENCE2_CNT 0x418170 + +#define mmDMA_QM_3_CP_FENCE3_CNT 0x418174 + +#define mmDMA_QM_3_CP_STS 0x418178 + +#define mmDMA_QM_3_CP_CURRENT_INST_LO 0x41817C + +#define mmDMA_QM_3_CP_CURRENT_INST_HI 0x418180 + +#define mmDMA_QM_3_CP_BARRIER_CFG 0x418184 + +#define mmDMA_QM_3_CP_DBG_0 0x418188 + +#define mmDMA_QM_3_PQ_BUF_ADDR 0x418300 + +#define mmDMA_QM_3_PQ_BUF_RDATA 0x418304 + +#define mmDMA_QM_3_CQ_BUF_ADDR 0x418308 + +#define mmDMA_QM_3_CQ_BUF_RDATA 0x41830C + +#endif /* ASIC_REG_DMA_QM_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h new file mode 100644 index 000000000..36fef2682 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_QM_4_REGS_H_ +#define ASIC_REG_DMA_QM_4_REGS_H_ + +/* + ***************************************** + * DMA_QM_4 (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA_QM_4_GLBL_CFG0 0x420000 + +#define mmDMA_QM_4_GLBL_CFG1 0x420004 + +#define mmDMA_QM_4_GLBL_PROT 0x420008 + +#define mmDMA_QM_4_GLBL_ERR_CFG 0x42000C + +#define mmDMA_QM_4_GLBL_ERR_ADDR_LO 0x420010 + +#define mmDMA_QM_4_GLBL_ERR_ADDR_HI 0x420014 + +#define mmDMA_QM_4_GLBL_ERR_WDATA 0x420018 + +#define mmDMA_QM_4_GLBL_SECURE_PROPS 0x42001C + +#define mmDMA_QM_4_GLBL_NON_SECURE_PROPS 0x420020 + +#define mmDMA_QM_4_GLBL_STS0 0x420024 + +#define mmDMA_QM_4_GLBL_STS1 0x420028 + +#define mmDMA_QM_4_PQ_BASE_LO 0x420060 + +#define mmDMA_QM_4_PQ_BASE_HI 0x420064 + +#define mmDMA_QM_4_PQ_SIZE 0x420068 + +#define mmDMA_QM_4_PQ_PI 0x42006C + +#define mmDMA_QM_4_PQ_CI 0x420070 + +#define mmDMA_QM_4_PQ_CFG0 0x420074 + +#define mmDMA_QM_4_PQ_CFG1 0x420078 + +#define mmDMA_QM_4_PQ_ARUSER 0x42007C + +#define mmDMA_QM_4_PQ_PUSH0 0x420080 + +#define mmDMA_QM_4_PQ_PUSH1 0x420084 + +#define mmDMA_QM_4_PQ_PUSH2 0x420088 + +#define mmDMA_QM_4_PQ_PUSH3 0x42008C + +#define mmDMA_QM_4_PQ_STS0 0x420090 + +#define mmDMA_QM_4_PQ_STS1 0x420094 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_EN 0x4200A0 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN 0x4200A4 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_SAT 0x4200A8 + +#define mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT 0x4200AC + +#define mmDMA_QM_4_CQ_CFG0 0x4200B0 + +#define mmDMA_QM_4_CQ_CFG1 0x4200B4 + +#define mmDMA_QM_4_CQ_ARUSER 0x4200B8 + +#define mmDMA_QM_4_CQ_PTR_LO 0x4200C0 + +#define mmDMA_QM_4_CQ_PTR_HI 0x4200C4 + +#define mmDMA_QM_4_CQ_TSIZE 0x4200C8 + +#define mmDMA_QM_4_CQ_CTL 0x4200CC + +#define mmDMA_QM_4_CQ_PTR_LO_STS 0x4200D4 + +#define mmDMA_QM_4_CQ_PTR_HI_STS 0x4200D8 + +#define mmDMA_QM_4_CQ_TSIZE_STS 0x4200DC + +#define mmDMA_QM_4_CQ_CTL_STS 0x4200E0 + +#define mmDMA_QM_4_CQ_STS0 0x4200E4 + +#define mmDMA_QM_4_CQ_STS1 0x4200E8 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_EN 0x4200F0 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN 0x4200F4 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_SAT 0x4200F8 + +#define mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT 0x4200FC + +#define mmDMA_QM_4_CQ_IFIFO_CNT 0x420108 + +#define mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO 0x420120 + +#define mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI 0x420124 + +#define mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO 0x420128 + +#define mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI 0x42012C + +#define mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO 0x420130 + +#define mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI 0x420134 + +#define mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO 0x420138 + +#define mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI 0x42013C + +#define mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET 0x420140 + +#define mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET 0x420144 + +#define mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET 0x420148 + +#define mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET 0x42014C + +#define mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET 0x420150 + +#define mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET 0x420154 + +#define mmDMA_QM_4_CP_FENCE0_RDATA 0x420158 + +#define mmDMA_QM_4_CP_FENCE1_RDATA 0x42015C + +#define mmDMA_QM_4_CP_FENCE2_RDATA 0x420160 + +#define mmDMA_QM_4_CP_FENCE3_RDATA 0x420164 + +#define mmDMA_QM_4_CP_FENCE0_CNT 0x420168 + +#define mmDMA_QM_4_CP_FENCE1_CNT 0x42016C + +#define mmDMA_QM_4_CP_FENCE2_CNT 0x420170 + +#define mmDMA_QM_4_CP_FENCE3_CNT 0x420174 + +#define mmDMA_QM_4_CP_STS 0x420178 + +#define mmDMA_QM_4_CP_CURRENT_INST_LO 0x42017C + +#define mmDMA_QM_4_CP_CURRENT_INST_HI 0x420180 + +#define mmDMA_QM_4_CP_BARRIER_CFG 0x420184 + +#define mmDMA_QM_4_CP_DBG_0 0x420188 + +#define mmDMA_QM_4_PQ_BUF_ADDR 0x420300 + +#define mmDMA_QM_4_PQ_BUF_RDATA 0x420304 + +#define mmDMA_QM_4_CQ_BUF_ADDR 0x420308 + +#define mmDMA_QM_4_CQ_BUF_RDATA 0x42030C + +#endif /* ASIC_REG_DMA_QM_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h new file mode 100644 index 000000000..85b15010c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h @@ -0,0 +1,1372 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GOYA_BLOCKS_H_ +#define GOYA_BLOCKS_H_ + +#define mmPCI_NRTR_BASE 0x7FFC000000ull +#define PCI_NRTR_MAX_OFFSET 0x608 +#define PCI_NRTR_SECTION 0x4000 +#define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull +#define PCI_RD_REGULATOR_MAX_OFFSET 0x74 +#define PCI_RD_REGULATOR_SECTION 0x1000 +#define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull +#define PCI_WR_REGULATOR_MAX_OFFSET 0x74 +#define PCI_WR_REGULATOR_SECTION 0x3B000 +#define mmMME1_RTR_BASE 0x7FFC040000ull +#define MME1_RTR_MAX_OFFSET 0x608 +#define MME1_RTR_SECTION 0x4000 +#define mmMME1_RD_REGULATOR_BASE 0x7FFC044000ull +#define MME1_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME1_RD_REGULATOR_SECTION 0x1000 +#define mmMME1_WR_REGULATOR_BASE 0x7FFC045000ull +#define MME1_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME1_WR_REGULATOR_SECTION 0x3B000 +#define mmMME2_RTR_BASE 0x7FFC080000ull +#define MME2_RTR_MAX_OFFSET 0x608 +#define MME2_RTR_SECTION 0x4000 +#define mmMME2_RD_REGULATOR_BASE 0x7FFC084000ull +#define MME2_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME2_RD_REGULATOR_SECTION 0x1000 +#define mmMME2_WR_REGULATOR_BASE 0x7FFC085000ull +#define MME2_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME2_WR_REGULATOR_SECTION 0x3B000 +#define mmMME3_RTR_BASE 0x7FFC0C0000ull +#define MME3_RTR_MAX_OFFSET 0x608 +#define MME3_RTR_SECTION 0x4000 +#define mmMME3_RD_REGULATOR_BASE 0x7FFC0C4000ull +#define MME3_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME3_RD_REGULATOR_SECTION 0x1000 +#define mmMME3_WR_REGULATOR_BASE 0x7FFC0C5000ull +#define MME3_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME3_WR_REGULATOR_SECTION 0xB000 +#define mmMME_BASE 0x7FFC0D0000ull +#define MME_MAX_OFFSET 0xBB0 +#define MME_SECTION 0x8000 +#define mmMME_QM_BASE 0x7FFC0D8000ull +#define MME_QM_MAX_OFFSET 0x310 +#define MME_QM_SECTION 0x1000 +#define mmMME_CMDQ_BASE 0x7FFC0D9000ull +#define MME_CMDQ_MAX_OFFSET 0x310 +#define MME_CMDQ_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_0_BASE 0x7FFC0DA000ull +#define ACC_MS_ECC_MEM_0_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_0_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_1_BASE 0x7FFC0DB000ull +#define ACC_MS_ECC_MEM_1_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_1_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_2_BASE 0x7FFC0DC000ull +#define ACC_MS_ECC_MEM_2_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_2_SECTION 0x1000 +#define mmACC_MS_ECC_MEM_3_BASE 0x7FFC0DD000ull +#define ACC_MS_ECC_MEM_3_MAX_OFFSET 0x0 +#define ACC_MS_ECC_MEM_3_SECTION 0x1000 +#define mmSBA_ECC_MEM_BASE 0x7FFC0DE000ull +#define SBA_ECC_MEM_MAX_OFFSET 0x0 +#define SBA_ECC_MEM_SECTION 0x1000 +#define mmSBB_ECC_MEM_BASE 0x7FFC0DF000ull +#define SBB_ECC_MEM_MAX_OFFSET 0x0 +#define SBB_ECC_MEM_SECTION 0x21000 +#define mmMME4_RTR_BASE 0x7FFC100000ull +#define MME4_RTR_MAX_OFFSET 0x608 +#define MME4_RTR_SECTION 0x4000 +#define mmMME4_RD_REGULATOR_BASE 0x7FFC104000ull +#define MME4_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME4_RD_REGULATOR_SECTION 0x1000 +#define mmMME4_WR_REGULATOR_BASE 0x7FFC105000ull +#define MME4_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME4_WR_REGULATOR_SECTION 0xB000 +#define mmSYNC_MNGR_BASE 0x7FFC110000ull +#define SYNC_MNGR_MAX_OFFSET 0x4400 +#define SYNC_MNGR_SECTION 0x30000 +#define mmMME5_RTR_BASE 0x7FFC140000ull +#define MME5_RTR_MAX_OFFSET 0x608 +#define MME5_RTR_SECTION 0x4000 +#define mmMME5_RD_REGULATOR_BASE 0x7FFC144000ull +#define MME5_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME5_RD_REGULATOR_SECTION 0x1000 +#define mmMME5_WR_REGULATOR_BASE 0x7FFC145000ull +#define MME5_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME5_WR_REGULATOR_SECTION 0x3B000 +#define mmMME6_RTR_BASE 0x7FFC180000ull +#define MME6_RTR_MAX_OFFSET 0x608 +#define MME6_RTR_SECTION 0x4000 +#define mmMME6_RD_REGULATOR_BASE 0x7FFC184000ull +#define MME6_RD_REGULATOR_MAX_OFFSET 0x74 +#define MME6_RD_REGULATOR_SECTION 0x1000 +#define mmMME6_WR_REGULATOR_BASE 0x7FFC185000ull +#define MME6_WR_REGULATOR_MAX_OFFSET 0x74 +#define MME6_WR_REGULATOR_SECTION 0x3B000 +#define mmDMA_NRTR_BASE 0x7FFC1C0000ull +#define DMA_NRTR_MAX_OFFSET 0x608 +#define DMA_NRTR_SECTION 0x4000 +#define mmDMA_RD_REGULATOR_BASE 0x7FFC1C4000ull +#define DMA_RD_REGULATOR_MAX_OFFSET 0x74 +#define DMA_RD_REGULATOR_SECTION 0x1000 +#define mmDMA_WR_REGULATOR_BASE 0x7FFC1C5000ull +#define DMA_WR_REGULATOR_MAX_OFFSET 0x74 +#define DMA_WR_REGULATOR_SECTION 0x3B000 +#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull +#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull +#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC204000ull +#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC205000ull +#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC208000ull +#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC209000ull +#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC20C000ull +#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC20D000ull +#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC210000ull +#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y0_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC211000ull +#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y0_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC220000ull +#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC221000ull +#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC224000ull +#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC225000ull +#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC228000ull +#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC229000ull +#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC22C000ull +#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC22D000ull +#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC230000ull +#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y1_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC231000ull +#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y1_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC240000ull +#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC241000ull +#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC244000ull +#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC245000ull +#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC248000ull +#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC249000ull +#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC24C000ull +#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC24D000ull +#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC250000ull +#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y2_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC251000ull +#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y2_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC260000ull +#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC261000ull +#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC264000ull +#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC265000ull +#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC268000ull +#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC269000ull +#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC26C000ull +#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC26D000ull +#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC270000ull +#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y3_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC271000ull +#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y3_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y4_X0_BANK_BASE 0x7FFC280000ull +#define SRAM_Y4_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X0_RTR_BASE 0x7FFC281000ull +#define SRAM_Y4_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X1_BANK_BASE 0x7FFC284000ull +#define SRAM_Y4_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X1_RTR_BASE 0x7FFC285000ull +#define SRAM_Y4_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X2_BANK_BASE 0x7FFC288000ull +#define SRAM_Y4_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X2_RTR_BASE 0x7FFC289000ull +#define SRAM_Y4_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X3_BANK_BASE 0x7FFC28C000ull +#define SRAM_Y4_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X3_RTR_BASE 0x7FFC28D000ull +#define SRAM_Y4_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y4_X4_BANK_BASE 0x7FFC290000ull +#define SRAM_Y4_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y4_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y4_X4_RTR_BASE 0x7FFC291000ull +#define SRAM_Y4_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y4_X4_RTR_SECTION 0xF000 +#define mmSRAM_Y5_X0_BANK_BASE 0x7FFC2A0000ull +#define SRAM_Y5_X0_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X0_RTR_BASE 0x7FFC2A1000ull +#define SRAM_Y5_X0_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X0_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X1_BANK_BASE 0x7FFC2A4000ull +#define SRAM_Y5_X1_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X1_RTR_BASE 0x7FFC2A5000ull +#define SRAM_Y5_X1_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X1_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X2_BANK_BASE 0x7FFC2A8000ull +#define SRAM_Y5_X2_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X2_RTR_BASE 0x7FFC2A9000ull +#define SRAM_Y5_X2_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X2_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X3_BANK_BASE 0x7FFC2AC000ull +#define SRAM_Y5_X3_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X3_RTR_BASE 0x7FFC2AD000ull +#define SRAM_Y5_X3_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X3_RTR_SECTION 0x3000 +#define mmSRAM_Y5_X4_BANK_BASE 0x7FFC2B0000ull +#define SRAM_Y5_X4_BANK_MAX_OFFSET 0x4 +#define SRAM_Y5_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y5_X4_RTR_BASE 0x7FFC2B1000ull +#define SRAM_Y5_X4_RTR_MAX_OFFSET 0x334 +#define SRAM_Y5_X4_RTR_SECTION 0x14F000 +#define mmDMA_QM_0_BASE 0x7FFC400000ull +#define DMA_QM_0_MAX_OFFSET 0x310 +#define DMA_QM_0_SECTION 0x1000 +#define mmDMA_CH_0_BASE 0x7FFC401000ull +#define DMA_CH_0_MAX_OFFSET 0x200 +#define DMA_CH_0_SECTION 0x7000 +#define mmDMA_QM_1_BASE 0x7FFC408000ull +#define DMA_QM_1_MAX_OFFSET 0x310 +#define DMA_QM_1_SECTION 0x1000 +#define mmDMA_CH_1_BASE 0x7FFC409000ull +#define DMA_CH_1_MAX_OFFSET 0x200 +#define DMA_CH_1_SECTION 0x7000 +#define mmDMA_QM_2_BASE 0x7FFC410000ull +#define DMA_QM_2_MAX_OFFSET 0x310 +#define DMA_QM_2_SECTION 0x1000 +#define mmDMA_CH_2_BASE 0x7FFC411000ull +#define DMA_CH_2_MAX_OFFSET 0x200 +#define DMA_CH_2_SECTION 0x7000 +#define mmDMA_QM_3_BASE 0x7FFC418000ull +#define DMA_QM_3_MAX_OFFSET 0x310 +#define DMA_QM_3_SECTION 0x1000 +#define mmDMA_CH_3_BASE 0x7FFC419000ull +#define DMA_CH_3_MAX_OFFSET 0x200 +#define DMA_CH_3_SECTION 0x7000 +#define mmDMA_QM_4_BASE 0x7FFC420000ull +#define DMA_QM_4_MAX_OFFSET 0x310 +#define DMA_QM_4_SECTION 0x1000 +#define mmDMA_CH_4_BASE 0x7FFC421000ull +#define DMA_CH_4_MAX_OFFSET 0x200 +#define DMA_CH_4_SECTION 0x20000 +#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x218 +#define CPU_CA53_CFG_SECTION 0x1000 +#define mmCPU_IF_BASE 0x7FFC442000ull +#define CPU_IF_MAX_OFFSET 0x134 +#define CPU_IF_SECTION 0x2000 +#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x3C000 +#define mmMMU_BASE 0x7FFC480000ull +#define MMU_MAX_OFFSET 0x44 +#define MMU_SECTION 0x10000 +#define mmSTLB_BASE 0x7FFC490000ull +#define STLB_MAX_OFFSET 0x50 +#define STLB_SECTION 0x10000 +#define mmNORTH_THERMAL_SENSOR_BASE 0x7FFC4A0000ull +#define NORTH_THERMAL_SENSOR_MAX_OFFSET 0xE64 +#define NORTH_THERMAL_SENSOR_SECTION 0x1000 +#define mmMC_PLL_BASE 0x7FFC4A1000ull +#define MC_PLL_MAX_OFFSET 0x444 +#define MC_PLL_SECTION 0x1000 +#define mmCPU_PLL_BASE 0x7FFC4A2000ull +#define CPU_PLL_MAX_OFFSET 0x444 +#define CPU_PLL_SECTION 0x1000 +#define mmIC_PLL_BASE 0x7FFC4A3000ull +#define IC_PLL_MAX_OFFSET 0x444 +#define IC_PLL_SECTION 0x1000 +#define mmDMA_PROCESS_MON_BASE 0x7FFC4A4000ull +#define DMA_PROCESS_MON_MAX_OFFSET 0x4 +#define DMA_PROCESS_MON_SECTION 0xC000 +#define mmDMA_MACRO_BASE 0x7FFC4B0000ull +#define DMA_MACRO_MAX_OFFSET 0x15C +#define DMA_MACRO_SECTION 0x150000 +#define mmDDR_PHY_CH0_BASE 0x7FFC600000ull +#define DDR_PHY_CH0_MAX_OFFSET 0x0 +#define DDR_PHY_CH0_SECTION 0x40000 +#define mmDDR_MC_CH0_BASE 0x7FFC640000ull +#define DDR_MC_CH0_MAX_OFFSET 0xF34 +#define DDR_MC_CH0_SECTION 0x8000 +#define mmDDR_MISC_CH0_BASE 0x7FFC648000ull +#define DDR_MISC_CH0_MAX_OFFSET 0x204 +#define DDR_MISC_CH0_SECTION 0xB8000 +#define mmDDR_PHY_CH1_BASE 0x7FFC700000ull +#define DDR_PHY_CH1_MAX_OFFSET 0x0 +#define DDR_PHY_CH1_SECTION 0x40000 +#define mmDDR_MC_CH1_BASE 0x7FFC740000ull +#define DDR_MC_CH1_MAX_OFFSET 0xF34 +#define DDR_MC_CH1_SECTION 0x8000 +#define mmDDR_MISC_CH1_BASE 0x7FFC748000ull +#define DDR_MISC_CH1_MAX_OFFSET 0x204 +#define DDR_MISC_CH1_SECTION 0xB8000 +#define mmGIC_BASE 0x7FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x7FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0xDF4 +#define PCIE_WRAP_SECTION 0x1000 +#define mmPCIE_DBI_BASE 0x7FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC04 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x7FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x9B8 +#define PCIE_CORE_SECTION 0x1000 +#define mmPCIE_DB_CFG_BASE 0x7FFCC05000ull +#define PCIE_DB_CFG_MAX_OFFSET 0xE34 +#define PCIE_DB_CFG_SECTION 0x1000 +#define mmPCIE_DB_CMD_BASE 0x7FFCC06000ull +#define PCIE_DB_CMD_MAX_OFFSET 0x810 +#define PCIE_DB_CMD_SECTION 0x1000 +#define mmPCIE_AUX_BASE 0x7FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x9BC +#define PCIE_AUX_SECTION 0x1000 +#define mmPCIE_DB_RSV_BASE 0x7FFCC08000ull +#define PCIE_DB_RSV_MAX_OFFSET 0x800 +#define PCIE_DB_RSV_SECTION 0x8000 +#define mmPCIE_PHY_BASE 0x7FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x924 +#define PCIE_PHY_SECTION 0x30000 +#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x100 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x100 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x100 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x7FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x100 +#define PSOC_SPI_SECTION 0x1000 +#define mmPSOC_EMMC_BASE 0x7FFCC44000ull +#define PSOC_EMMC_MAX_OFFSET 0xF70 +#define PSOC_EMMC_SECTION 0x1000 +#define mmPSOC_UART_0_BASE 0x7FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x7FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x7FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x7FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x10C +#define PSOC_EFUSE_SECTION 0x1000 +#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xA48 +#define PSOC_GLOBAL_CONF_SECTION 0x1000 +#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x7FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x124 +#define PSOC_BTL_SECTION 0x1000 +#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x0 +#define PSOC_CS_TRACE_SECTION 0x1000 +#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x1000 +#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x10C +#define PSOC_DFT_EFUSE_SECTION 0x1000 +#define mmPSOC_PM_BASE 0x7FFCC54000ull +#define PSOC_PM_MAX_OFFSET 0x4 +#define PSOC_PM_SECTION 0x1000 +#define mmPSOC_TS_BASE 0x7FFCC55000ull +#define PSOC_TS_MAX_OFFSET 0xE64 +#define PSOC_TS_SECTION 0xB000 +#define mmPSOC_MII_BASE 0x7FFCC60000ull +#define PSOC_MII_MAX_OFFSET 0x105C +#define PSOC_MII_SECTION 0x10000 +#define mmPSOC_EMMC_PLL_BASE 0x7FFCC70000ull +#define PSOC_EMMC_PLL_MAX_OFFSET 0x444 +#define PSOC_EMMC_PLL_SECTION 0x1000 +#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull +#define PSOC_MME_PLL_MAX_OFFSET 0x444 +#define PSOC_MME_PLL_SECTION 0x1000 +#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull +#define PSOC_PCI_PLL_MAX_OFFSET 0x444 +#define PSOC_PCI_PLL_SECTION 0x6000 +#define mmPSOC_PWM0_BASE 0x7FFCC78000ull +#define PSOC_PWM0_MAX_OFFSET 0x58 +#define PSOC_PWM0_SECTION 0x1000 +#define mmPSOC_PWM1_BASE 0x7FFCC79000ull +#define PSOC_PWM1_MAX_OFFSET 0x58 +#define PSOC_PWM1_SECTION 0x1000 +#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull +#define PSOC_PWM2_MAX_OFFSET 0x58 +#define PSOC_PWM2_SECTION 0x1000 +#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull +#define PSOC_PWM3_MAX_OFFSET 0x58 +#define PSOC_PWM3_SECTION 0x185000 +#define mmTPC0_NRTR_BASE 0x7FFCE00000ull +#define TPC0_NRTR_MAX_OFFSET 0x608 +#define TPC0_NRTR_SECTION 0x1000 +#define mmTPC_PLL_BASE 0x7FFCE01000ull +#define TPC_PLL_MAX_OFFSET 0x444 +#define TPC_PLL_SECTION 0x1000 +#define mmTPC_THEMAL_SENSOR_BASE 0x7FFCE02000ull +#define TPC_THEMAL_SENSOR_MAX_OFFSET 0xE64 +#define TPC_THEMAL_SENSOR_SECTION 0x1000 +#define mmTPC_PROCESS_MON_BASE 0x7FFCE03000ull +#define TPC_PROCESS_MON_MAX_OFFSET 0x4 +#define TPC_PROCESS_MON_SECTION 0x1000 +#define mmTPC0_RD_REGULATOR_BASE 0x7FFCE04000ull +#define TPC0_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC0_RD_REGULATOR_SECTION 0x1000 +#define mmTPC0_WR_REGULATOR_BASE 0x7FFCE05000ull +#define TPC0_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC0_WR_REGULATOR_SECTION 0x1000 +#define mmTPC0_CFG_BASE 0x7FFCE06000ull +#define TPC0_CFG_MAX_OFFSET 0xE30 +#define TPC0_CFG_SECTION 0x2000 +#define mmTPC0_QM_BASE 0x7FFCE08000ull +#define TPC0_QM_MAX_OFFSET 0x310 +#define TPC0_QM_SECTION 0x1000 +#define mmTPC0_CMDQ_BASE 0x7FFCE09000ull +#define TPC0_CMDQ_MAX_OFFSET 0x310 +#define TPC0_CMDQ_SECTION 0x37000 +#define mmTPC1_RTR_BASE 0x7FFCE40000ull +#define TPC1_RTR_MAX_OFFSET 0x608 +#define TPC1_RTR_SECTION 0x4000 +#define mmTPC1_WR_REGULATOR_BASE 0x7FFCE44000ull +#define TPC1_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC1_WR_REGULATOR_SECTION 0x1000 +#define mmTPC1_RD_REGULATOR_BASE 0x7FFCE45000ull +#define TPC1_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC1_RD_REGULATOR_SECTION 0x1000 +#define mmTPC1_CFG_BASE 0x7FFCE46000ull +#define TPC1_CFG_MAX_OFFSET 0xE30 +#define TPC1_CFG_SECTION 0x2000 +#define mmTPC1_QM_BASE 0x7FFCE48000ull +#define TPC1_QM_MAX_OFFSET 0x310 +#define TPC1_QM_SECTION 0x1000 +#define mmTPC1_CMDQ_BASE 0x7FFCE49000ull +#define TPC1_CMDQ_MAX_OFFSET 0x310 +#define TPC1_CMDQ_SECTION 0x37000 +#define mmTPC2_RTR_BASE 0x7FFCE80000ull +#define TPC2_RTR_MAX_OFFSET 0x608 +#define TPC2_RTR_SECTION 0x4000 +#define mmTPC2_RD_REGULATOR_BASE 0x7FFCE84000ull +#define TPC2_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC2_RD_REGULATOR_SECTION 0x1000 +#define mmTPC2_WR_REGULATOR_BASE 0x7FFCE85000ull +#define TPC2_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC2_WR_REGULATOR_SECTION 0x1000 +#define mmTPC2_CFG_BASE 0x7FFCE86000ull +#define TPC2_CFG_MAX_OFFSET 0xE30 +#define TPC2_CFG_SECTION 0x2000 +#define mmTPC2_QM_BASE 0x7FFCE88000ull +#define TPC2_QM_MAX_OFFSET 0x310 +#define TPC2_QM_SECTION 0x1000 +#define mmTPC2_CMDQ_BASE 0x7FFCE89000ull +#define TPC2_CMDQ_MAX_OFFSET 0x310 +#define TPC2_CMDQ_SECTION 0x37000 +#define mmTPC3_RTR_BASE 0x7FFCEC0000ull +#define TPC3_RTR_MAX_OFFSET 0x608 +#define TPC3_RTR_SECTION 0x4000 +#define mmTPC3_RD_REGULATOR_BASE 0x7FFCEC4000ull +#define TPC3_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC3_RD_REGULATOR_SECTION 0x1000 +#define mmTPC3_WR_REGULATOR_BASE 0x7FFCEC5000ull +#define TPC3_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC3_WR_REGULATOR_SECTION 0x1000 +#define mmTPC3_CFG_BASE 0x7FFCEC6000ull +#define TPC3_CFG_MAX_OFFSET 0xE30 +#define TPC3_CFG_SECTION 0x2000 +#define mmTPC3_QM_BASE 0x7FFCEC8000ull +#define TPC3_QM_MAX_OFFSET 0x310 +#define TPC3_QM_SECTION 0x1000 +#define mmTPC3_CMDQ_BASE 0x7FFCEC9000ull +#define TPC3_CMDQ_MAX_OFFSET 0x310 +#define TPC3_CMDQ_SECTION 0x37000 +#define mmTPC4_RTR_BASE 0x7FFCF00000ull +#define TPC4_RTR_MAX_OFFSET 0x608 +#define TPC4_RTR_SECTION 0x4000 +#define mmTPC4_RD_REGULATOR_BASE 0x7FFCF04000ull +#define TPC4_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC4_RD_REGULATOR_SECTION 0x1000 +#define mmTPC4_WR_REGULATOR_BASE 0x7FFCF05000ull +#define TPC4_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC4_WR_REGULATOR_SECTION 0x1000 +#define mmTPC4_CFG_BASE 0x7FFCF06000ull +#define TPC4_CFG_MAX_OFFSET 0xE30 +#define TPC4_CFG_SECTION 0x2000 +#define mmTPC4_QM_BASE 0x7FFCF08000ull +#define TPC4_QM_MAX_OFFSET 0x310 +#define TPC4_QM_SECTION 0x1000 +#define mmTPC4_CMDQ_BASE 0x7FFCF09000ull +#define TPC4_CMDQ_MAX_OFFSET 0x310 +#define TPC4_CMDQ_SECTION 0x37000 +#define mmTPC5_RTR_BASE 0x7FFCF40000ull +#define TPC5_RTR_MAX_OFFSET 0x608 +#define TPC5_RTR_SECTION 0x4000 +#define mmTPC5_RD_REGULATOR_BASE 0x7FFCF44000ull +#define TPC5_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC5_RD_REGULATOR_SECTION 0x1000 +#define mmTPC5_WR_REGULATOR_BASE 0x7FFCF45000ull +#define TPC5_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC5_WR_REGULATOR_SECTION 0x1000 +#define mmTPC5_CFG_BASE 0x7FFCF46000ull +#define TPC5_CFG_MAX_OFFSET 0xE30 +#define TPC5_CFG_SECTION 0x2000 +#define mmTPC5_QM_BASE 0x7FFCF48000ull +#define TPC5_QM_MAX_OFFSET 0x310 +#define TPC5_QM_SECTION 0x1000 +#define mmTPC5_CMDQ_BASE 0x7FFCF49000ull +#define TPC5_CMDQ_MAX_OFFSET 0x310 +#define TPC5_CMDQ_SECTION 0x37000 +#define mmTPC6_RTR_BASE 0x7FFCF80000ull +#define TPC6_RTR_MAX_OFFSET 0x608 +#define TPC6_RTR_SECTION 0x4000 +#define mmTPC6_RD_REGULATOR_BASE 0x7FFCF84000ull +#define TPC6_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC6_RD_REGULATOR_SECTION 0x1000 +#define mmTPC6_WR_REGULATOR_BASE 0x7FFCF85000ull +#define TPC6_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC6_WR_REGULATOR_SECTION 0x1000 +#define mmTPC6_CFG_BASE 0x7FFCF86000ull +#define TPC6_CFG_MAX_OFFSET 0xE30 +#define TPC6_CFG_SECTION 0x2000 +#define mmTPC6_QM_BASE 0x7FFCF88000ull +#define TPC6_QM_MAX_OFFSET 0x310 +#define TPC6_QM_SECTION 0x1000 +#define mmTPC6_CMDQ_BASE 0x7FFCF89000ull +#define TPC6_CMDQ_MAX_OFFSET 0x310 +#define TPC6_CMDQ_SECTION 0x37000 +#define mmTPC7_NRTR_BASE 0x7FFCFC0000ull +#define TPC7_NRTR_MAX_OFFSET 0x608 +#define TPC7_NRTR_SECTION 0x4000 +#define mmTPC7_RD_REGULATOR_BASE 0x7FFCFC4000ull +#define TPC7_RD_REGULATOR_MAX_OFFSET 0x74 +#define TPC7_RD_REGULATOR_SECTION 0x1000 +#define mmTPC7_WR_REGULATOR_BASE 0x7FFCFC5000ull +#define TPC7_WR_REGULATOR_MAX_OFFSET 0x74 +#define TPC7_WR_REGULATOR_SECTION 0x1000 +#define mmTPC7_CFG_BASE 0x7FFCFC6000ull +#define TPC7_CFG_MAX_OFFSET 0xE30 +#define TPC7_CFG_SECTION 0x2000 +#define mmTPC7_QM_BASE 0x7FFCFC8000ull +#define TPC7_QM_MAX_OFFSET 0x310 +#define TPC7_QM_SECTION 0x1000 +#define mmTPC7_CMDQ_BASE 0x7FFCFC9000ull +#define TPC7_CMDQ_MAX_OFFSET 0x310 +#define TPC7_CMDQ_SECTION 0x1037000 +#define mmMME_TOP_TABLE_BASE 0x7FFE000000ull +#define MME_TOP_TABLE_MAX_OFFSET 0x1000 +#define MME_TOP_TABLE_SECTION 0x1000 +#define mmMME0_RTR_FUNNEL_BASE 0x7FFE001000ull +#define MME0_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME0_RTR_FUNNEL_SECTION 0x40000 +#define mmMME1_RTR_FUNNEL_BASE 0x7FFE041000ull +#define MME1_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME1_RTR_FUNNEL_SECTION 0x1000 +#define mmMME1_SBA_STM_BASE 0x7FFE042000ull +#define MME1_SBA_STM_MAX_OFFSET 0x1000 +#define MME1_SBA_STM_SECTION 0x1000 +#define mmMME1_SBA_CTI_BASE 0x7FFE043000ull +#define MME1_SBA_CTI_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI_SECTION 0x1000 +#define mmMME1_SBA_ETF_BASE 0x7FFE044000ull +#define MME1_SBA_ETF_MAX_OFFSET 0x1000 +#define MME1_SBA_ETF_SECTION 0x1000 +#define mmMME1_SBA_SPMU_BASE 0x7FFE045000ull +#define MME1_SBA_SPMU_MAX_OFFSET 0x1000 +#define MME1_SBA_SPMU_SECTION 0x1000 +#define mmMME1_SBA_CTI0_BASE 0x7FFE046000ull +#define MME1_SBA_CTI0_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI0_SECTION 0x1000 +#define mmMME1_SBA_CTI1_BASE 0x7FFE047000ull +#define MME1_SBA_CTI1_MAX_OFFSET 0x1000 +#define MME1_SBA_CTI1_SECTION 0x1000 +#define mmMME1_SBA_BMON0_BASE 0x7FFE048000ull +#define MME1_SBA_BMON0_MAX_OFFSET 0x1000 +#define MME1_SBA_BMON0_SECTION 0x1000 +#define mmMME1_SBA_BMON1_BASE 0x7FFE049000ull +#define MME1_SBA_BMON1_MAX_OFFSET 0x1000 +#define MME1_SBA_BMON1_SECTION 0x38000 +#define mmMME2_RTR_FUNNEL_BASE 0x7FFE081000ull +#define MME2_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME2_RTR_FUNNEL_SECTION 0x40000 +#define mmMME3_RTR_FUNNEL_BASE 0x7FFE0C1000ull +#define MME3_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME3_RTR_FUNNEL_SECTION 0x1000 +#define mmMME3_SBB_STM_BASE 0x7FFE0C2000ull +#define MME3_SBB_STM_MAX_OFFSET 0x1000 +#define MME3_SBB_STM_SECTION 0x1000 +#define mmMME3_SBB_CTI_BASE 0x7FFE0C3000ull +#define MME3_SBB_CTI_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI_SECTION 0x1000 +#define mmMME3_SBB_ETF_BASE 0x7FFE0C4000ull +#define MME3_SBB_ETF_MAX_OFFSET 0x1000 +#define MME3_SBB_ETF_SECTION 0x1000 +#define mmMME3_SBB_SPMU_BASE 0x7FFE0C5000ull +#define MME3_SBB_SPMU_MAX_OFFSET 0x1000 +#define MME3_SBB_SPMU_SECTION 0x1000 +#define mmMME3_SBB_CTI0_BASE 0x7FFE0C6000ull +#define MME3_SBB_CTI0_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI0_SECTION 0x1000 +#define mmMME3_SBB_CTI1_BASE 0x7FFE0C7000ull +#define MME3_SBB_CTI1_MAX_OFFSET 0x1000 +#define MME3_SBB_CTI1_SECTION 0x1000 +#define mmMME3_SBB_BMON0_BASE 0x7FFE0C8000ull +#define MME3_SBB_BMON0_MAX_OFFSET 0x1000 +#define MME3_SBB_BMON0_SECTION 0x1000 +#define mmMME3_SBB_BMON1_BASE 0x7FFE0C9000ull +#define MME3_SBB_BMON1_MAX_OFFSET 0x1000 +#define MME3_SBB_BMON1_SECTION 0x38000 +#define mmMME4_RTR_FUNNEL_BASE 0x7FFE101000ull +#define MME4_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME4_RTR_FUNNEL_SECTION 0x1000 +#define mmMME4_WACS_STM_BASE 0x7FFE102000ull +#define MME4_WACS_STM_MAX_OFFSET 0x1000 +#define MME4_WACS_STM_SECTION 0x1000 +#define mmMME4_WACS_CTI_BASE 0x7FFE103000ull +#define MME4_WACS_CTI_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI_SECTION 0x1000 +#define mmMME4_WACS_ETF_BASE 0x7FFE104000ull +#define MME4_WACS_ETF_MAX_OFFSET 0x1000 +#define MME4_WACS_ETF_SECTION 0x1000 +#define mmMME4_WACS_SPMU_BASE 0x7FFE105000ull +#define MME4_WACS_SPMU_MAX_OFFSET 0x1000 +#define MME4_WACS_SPMU_SECTION 0x1000 +#define mmMME4_WACS_CTI0_BASE 0x7FFE106000ull +#define MME4_WACS_CTI0_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI0_SECTION 0x1000 +#define mmMME4_WACS_CTI1_BASE 0x7FFE107000ull +#define MME4_WACS_CTI1_MAX_OFFSET 0x1000 +#define MME4_WACS_CTI1_SECTION 0x1000 +#define mmMME4_WACS_BMON0_BASE 0x7FFE108000ull +#define MME4_WACS_BMON0_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON0_SECTION 0x1000 +#define mmMME4_WACS_BMON1_BASE 0x7FFE109000ull +#define MME4_WACS_BMON1_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON1_SECTION 0x1000 +#define mmMME4_WACS_BMON2_BASE 0x7FFE10A000ull +#define MME4_WACS_BMON2_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON2_SECTION 0x1000 +#define mmMME4_WACS_BMON3_BASE 0x7FFE10B000ull +#define MME4_WACS_BMON3_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON3_SECTION 0x1000 +#define mmMME4_WACS_BMON4_BASE 0x7FFE10C000ull +#define MME4_WACS_BMON4_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON4_SECTION 0x1000 +#define mmMME4_WACS_BMON5_BASE 0x7FFE10D000ull +#define MME4_WACS_BMON5_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON5_SECTION 0x1000 +#define mmMME4_WACS_BMON6_BASE 0x7FFE10E000ull +#define MME4_WACS_BMON6_MAX_OFFSET 0x1000 +#define MME4_WACS_BMON6_SECTION 0x4000 +#define mmMME4_WACS2_STM_BASE 0x7FFE112000ull +#define MME4_WACS2_STM_MAX_OFFSET 0x1000 +#define MME4_WACS2_STM_SECTION 0x1000 +#define mmMME4_WACS2_CTI_BASE 0x7FFE113000ull +#define MME4_WACS2_CTI_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI_SECTION 0x1000 +#define mmMME4_WACS2_ETF_BASE 0x7FFE114000ull +#define MME4_WACS2_ETF_MAX_OFFSET 0x1000 +#define MME4_WACS2_ETF_SECTION 0x1000 +#define mmMME4_WACS2_SPMU_BASE 0x7FFE115000ull +#define MME4_WACS2_SPMU_MAX_OFFSET 0x1000 +#define MME4_WACS2_SPMU_SECTION 0x1000 +#define mmMME4_WACS2_CTI0_BASE 0x7FFE116000ull +#define MME4_WACS2_CTI0_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI0_SECTION 0x1000 +#define mmMME4_WACS2_CTI1_BASE 0x7FFE117000ull +#define MME4_WACS2_CTI1_MAX_OFFSET 0x1000 +#define MME4_WACS2_CTI1_SECTION 0x1000 +#define mmMME4_WACS2_BMON0_BASE 0x7FFE118000ull +#define MME4_WACS2_BMON0_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON0_SECTION 0x1000 +#define mmMME4_WACS2_BMON1_BASE 0x7FFE119000ull +#define MME4_WACS2_BMON1_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON1_SECTION 0x1000 +#define mmMME4_WACS2_BMON2_BASE 0x7FFE11A000ull +#define MME4_WACS2_BMON2_MAX_OFFSET 0x1000 +#define MME4_WACS2_BMON2_SECTION 0x27000 +#define mmMME5_RTR_FUNNEL_BASE 0x7FFE141000ull +#define MME5_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define MME5_RTR_FUNNEL_SECTION 0x2BF000 +#define mmDMA_ROM_TABLE_BASE 0x7FFE400000ull +#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_ROM_TABLE_SECTION 0x1000 +#define mmDMA_CH_0_CS_STM_BASE 0x7FFE401000ull +#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_STM_SECTION 0x1000 +#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE402000ull +#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE403000ull +#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE404000ull +#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE405000ull +#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE406000ull +#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_0_BMON_0_BASE 0x7FFE407000ull +#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_0_SECTION 0x1000 +#define mmDMA_CH_0_BMON_1_BASE 0x7FFE408000ull +#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_1_SECTION 0x9000 +#define mmDMA_CH_1_CS_STM_BASE 0x7FFE411000ull +#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_STM_SECTION 0x1000 +#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE412000ull +#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE413000ull +#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE414000ull +#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE415000ull +#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE416000ull +#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_1_BMON_0_BASE 0x7FFE417000ull +#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_0_SECTION 0x1000 +#define mmDMA_CH_1_BMON_1_BASE 0x7FFE418000ull +#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_1_SECTION 0x9000 +#define mmDMA_CH_2_CS_STM_BASE 0x7FFE421000ull +#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_STM_SECTION 0x1000 +#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE422000ull +#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE423000ull +#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE424000ull +#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE425000ull +#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE426000ull +#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_2_BMON_0_BASE 0x7FFE427000ull +#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_0_SECTION 0x1000 +#define mmDMA_CH_2_BMON_1_BASE 0x7FFE428000ull +#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_1_SECTION 0x9000 +#define mmDMA_CH_3_CS_STM_BASE 0x7FFE431000ull +#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_STM_SECTION 0x1000 +#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE432000ull +#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE433000ull +#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE434000ull +#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE435000ull +#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE436000ull +#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_3_BMON_0_BASE 0x7FFE437000ull +#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_0_SECTION 0x1000 +#define mmDMA_CH_3_BMON_1_BASE 0x7FFE438000ull +#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_1_SECTION 0x9000 +#define mmDMA_CH_4_CS_STM_BASE 0x7FFE441000ull +#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_STM_SECTION 0x1000 +#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE442000ull +#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE443000ull +#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE444000ull +#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE445000ull +#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE446000ull +#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_4_BMON_0_BASE 0x7FFE447000ull +#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_0_SECTION 0x1000 +#define mmDMA_CH_4_BMON_1_BASE 0x7FFE448000ull +#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_1_SECTION 0x8000 +#define mmDMA_CH_FUNNEL_6_1_BASE 0x7FFE450000ull +#define DMA_CH_FUNNEL_6_1_MAX_OFFSET 0x1000 +#define DMA_CH_FUNNEL_6_1_SECTION 0x11000 +#define mmDMA_MACRO_CS_STM_BASE 0x7FFE461000ull +#define DMA_MACRO_CS_STM_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_STM_SECTION 0x1000 +#define mmDMA_MACRO_CS_CTI_BASE 0x7FFE462000ull +#define DMA_MACRO_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_CTI_SECTION 0x1000 +#define mmDMA_MACRO_CS_ETF_BASE 0x7FFE463000ull +#define DMA_MACRO_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_ETF_SECTION 0x1000 +#define mmDMA_MACRO_CS_SPMU_BASE 0x7FFE464000ull +#define DMA_MACRO_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_MACRO_CS_SPMU_SECTION 0x1000 +#define mmDMA_MACRO_BMON_CTI_BASE 0x7FFE465000ull +#define DMA_MACRO_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_CTI_SECTION 0x1000 +#define mmDMA_MACRO_USER_CTI_BASE 0x7FFE466000ull +#define DMA_MACRO_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_MACRO_USER_CTI_SECTION 0x1000 +#define mmDMA_MACRO_BMON_0_BASE 0x7FFE467000ull +#define DMA_MACRO_BMON_0_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_0_SECTION 0x1000 +#define mmDMA_MACRO_BMON_1_BASE 0x7FFE468000ull +#define DMA_MACRO_BMON_1_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_1_SECTION 0x1000 +#define mmDMA_MACRO_BMON_2_BASE 0x7FFE469000ull +#define DMA_MACRO_BMON_2_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_2_SECTION 0x1000 +#define mmDMA_MACRO_BMON_3_BASE 0x7FFE46A000ull +#define DMA_MACRO_BMON_3_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_3_SECTION 0x1000 +#define mmDMA_MACRO_BMON_4_BASE 0x7FFE46B000ull +#define DMA_MACRO_BMON_4_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_4_SECTION 0x1000 +#define mmDMA_MACRO_BMON_5_BASE 0x7FFE46C000ull +#define DMA_MACRO_BMON_5_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_5_SECTION 0x1000 +#define mmDMA_MACRO_BMON_6_BASE 0x7FFE46D000ull +#define DMA_MACRO_BMON_6_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_6_SECTION 0x1000 +#define mmDMA_MACRO_BMON_7_BASE 0x7FFE46E000ull +#define DMA_MACRO_BMON_7_MAX_OFFSET 0x1000 +#define DMA_MACRO_BMON_7_SECTION 0x2000 +#define mmDMA_MACRO_FUNNEL_3_1_BASE 0x7FFE470000ull +#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET 0x1000 +#define DMA_MACRO_FUNNEL_3_1_SECTION 0x10000 +#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull +#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 +#define CPU_ROM_TABLE_SECTION 0x1000 +#define mmCPU_ETF_0_BASE 0x7FFE481000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x7FFE482000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x7FFE484000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x7FFE485000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x7FFE486000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x7FFE489000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x37000 +#define mmMMU_CS_STM_BASE 0x7FFE4C1000ull +#define MMU_CS_STM_MAX_OFFSET 0x1000 +#define MMU_CS_STM_SECTION 0x1000 +#define mmMMU_CS_CTI_BASE 0x7FFE4C2000ull +#define MMU_CS_CTI_MAX_OFFSET 0x1000 +#define MMU_CS_CTI_SECTION 0x1000 +#define mmMMU_CS_ETF_BASE 0x7FFE4C3000ull +#define MMU_CS_ETF_MAX_OFFSET 0x1000 +#define MMU_CS_ETF_SECTION 0x1000 +#define mmMMU_CS_SPMU_BASE 0x7FFE4C4000ull +#define MMU_CS_SPMU_MAX_OFFSET 0x1000 +#define MMU_CS_SPMU_SECTION 0x1000 +#define mmMMU_BMON_CTI_BASE 0x7FFE4C5000ull +#define MMU_BMON_CTI_MAX_OFFSET 0x1000 +#define MMU_BMON_CTI_SECTION 0x1000 +#define mmMMU_USER_CTI_BASE 0x7FFE4C6000ull +#define MMU_USER_CTI_MAX_OFFSET 0x1000 +#define MMU_USER_CTI_SECTION 0x1000 +#define mmMMU_BMON_0_BASE 0x7FFE4C7000ull +#define MMU_BMON_0_MAX_OFFSET 0x1000 +#define MMU_BMON_0_SECTION 0x1000 +#define mmMMU_BMON_1_BASE 0x7FFE4C8000ull +#define MMU_BMON_1_MAX_OFFSET 0x1000 +#define MMU_BMON_1_SECTION 0x338000 +#define mmCA53_BASE 0x7FFE800000ull +#define CA53_MAX_OFFSET 0x1000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x7FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x7FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x7FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x1000 +#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull +#define PCIE_FUNNEL_MAX_OFFSET 0x1000 +#define PCIE_FUNNEL_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x36000 +#define mmPSOC_CTI_BASE 0x7FFEC40000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x7FFEC41000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x7FFEC43000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x7FFEC44000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xB000 +#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x1F0000 +#define mmTPC1_RTR_FUNNEL_BASE 0x7FFEE40000ull +#define TPC1_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC2_RTR_FUNNEL_BASE 0x7FFEE80000ull +#define TPC2_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC3_RTR_FUNNEL_BASE 0x7FFEEC0000ull +#define TPC3_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC4_RTR_FUNNEL_BASE 0x7FFEF00000ull +#define TPC4_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC5_RTR_FUNNEL_BASE 0x7FFEF40000ull +#define TPC5_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_RTR_FUNNEL_SECTION 0x40000 +#define mmTPC6_RTR_FUNNEL_BASE 0x7FFEF80000ull +#define TPC6_RTR_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_RTR_FUNNEL_SECTION 0x81000 +#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull +#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC0_EML_SPMU_SECTION 0x1000 +#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull +#define TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define TPC0_EML_ETF_SECTION 0x1000 +#define mmTPC0_EML_STM_BASE 0x7FFF003000ull +#define TPC0_EML_STM_MAX_OFFSET 0x1000 +#define TPC0_EML_STM_SECTION 0x1000 +#define mmTPC0_EML_ETM_R4_BASE 0x7FFF004000ull +#define TPC0_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC0_EML_ETM_R4_SECTION 0x1000 +#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull +#define TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define TPC0_EML_CTI_SECTION 0x1000 +#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull +#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull +#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull +#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull +#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull +#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull +#define TPC0_EML_CFG_MAX_OFFSET 0x338 +#define TPC0_EML_CFG_SECTION 0x1BF000 +#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull +#define TPC0_EML_CS_MAX_OFFSET 0x1000 +#define TPC0_EML_CS_SECTION 0x2000 +#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull +#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC1_EML_SPMU_SECTION 0x1000 +#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull +#define TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define TPC1_EML_ETF_SECTION 0x1000 +#define mmTPC1_EML_STM_BASE 0x7FFF203000ull +#define TPC1_EML_STM_MAX_OFFSET 0x1000 +#define TPC1_EML_STM_SECTION 0x1000 +#define mmTPC1_EML_ETM_R4_BASE 0x7FFF204000ull +#define TPC1_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC1_EML_ETM_R4_SECTION 0x1000 +#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull +#define TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define TPC1_EML_CTI_SECTION 0x1000 +#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull +#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull +#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull +#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull +#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull +#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull +#define TPC1_EML_CFG_MAX_OFFSET 0x338 +#define TPC1_EML_CFG_SECTION 0x1BF000 +#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull +#define TPC1_EML_CS_MAX_OFFSET 0x1000 +#define TPC1_EML_CS_SECTION 0x2000 +#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull +#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC2_EML_SPMU_SECTION 0x1000 +#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull +#define TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define TPC2_EML_ETF_SECTION 0x1000 +#define mmTPC2_EML_STM_BASE 0x7FFF403000ull +#define TPC2_EML_STM_MAX_OFFSET 0x1000 +#define TPC2_EML_STM_SECTION 0x1000 +#define mmTPC2_EML_ETM_R4_BASE 0x7FFF404000ull +#define TPC2_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC2_EML_ETM_R4_SECTION 0x1000 +#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull +#define TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define TPC2_EML_CTI_SECTION 0x1000 +#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull +#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull +#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull +#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull +#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull +#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull +#define TPC2_EML_CFG_MAX_OFFSET 0x338 +#define TPC2_EML_CFG_SECTION 0x1BF000 +#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull +#define TPC2_EML_CS_MAX_OFFSET 0x1000 +#define TPC2_EML_CS_SECTION 0x2000 +#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull +#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC3_EML_SPMU_SECTION 0x1000 +#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull +#define TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define TPC3_EML_ETF_SECTION 0x1000 +#define mmTPC3_EML_STM_BASE 0x7FFF603000ull +#define TPC3_EML_STM_MAX_OFFSET 0x1000 +#define TPC3_EML_STM_SECTION 0x1000 +#define mmTPC3_EML_ETM_R4_BASE 0x7FFF604000ull +#define TPC3_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC3_EML_ETM_R4_SECTION 0x1000 +#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull +#define TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define TPC3_EML_CTI_SECTION 0x1000 +#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull +#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull +#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull +#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull +#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull +#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull +#define TPC3_EML_CFG_MAX_OFFSET 0x338 +#define TPC3_EML_CFG_SECTION 0x1BF000 +#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull +#define TPC3_EML_CS_MAX_OFFSET 0x1000 +#define TPC3_EML_CS_SECTION 0x2000 +#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull +#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC4_EML_SPMU_SECTION 0x1000 +#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull +#define TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define TPC4_EML_ETF_SECTION 0x1000 +#define mmTPC4_EML_STM_BASE 0x7FFF803000ull +#define TPC4_EML_STM_MAX_OFFSET 0x1000 +#define TPC4_EML_STM_SECTION 0x1000 +#define mmTPC4_EML_ETM_R4_BASE 0x7FFF804000ull +#define TPC4_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC4_EML_ETM_R4_SECTION 0x1000 +#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull +#define TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define TPC4_EML_CTI_SECTION 0x1000 +#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull +#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull +#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull +#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull +#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull +#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull +#define TPC4_EML_CFG_MAX_OFFSET 0x338 +#define TPC4_EML_CFG_SECTION 0x1BF000 +#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull +#define TPC4_EML_CS_MAX_OFFSET 0x1000 +#define TPC4_EML_CS_SECTION 0x2000 +#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull +#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC5_EML_SPMU_SECTION 0x1000 +#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull +#define TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define TPC5_EML_ETF_SECTION 0x1000 +#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull +#define TPC5_EML_STM_MAX_OFFSET 0x1000 +#define TPC5_EML_STM_SECTION 0x1000 +#define mmTPC5_EML_ETM_R4_BASE 0x7FFFA04000ull +#define TPC5_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC5_EML_ETM_R4_SECTION 0x1000 +#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull +#define TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define TPC5_EML_CTI_SECTION 0x1000 +#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull +#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull +#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull +#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull +#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull +#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull +#define TPC5_EML_CFG_MAX_OFFSET 0x338 +#define TPC5_EML_CFG_SECTION 0x1BF000 +#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull +#define TPC5_EML_CS_MAX_OFFSET 0x1000 +#define TPC5_EML_CS_SECTION 0x2000 +#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull +#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC6_EML_SPMU_SECTION 0x1000 +#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull +#define TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define TPC6_EML_ETF_SECTION 0x1000 +#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull +#define TPC6_EML_STM_MAX_OFFSET 0x1000 +#define TPC6_EML_STM_SECTION 0x1000 +#define mmTPC6_EML_ETM_R4_BASE 0x7FFFC04000ull +#define TPC6_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC6_EML_ETM_R4_SECTION 0x1000 +#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull +#define TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define TPC6_EML_CTI_SECTION 0x1000 +#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull +#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull +#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull +#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull +#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull +#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull +#define TPC6_EML_CFG_MAX_OFFSET 0x338 +#define TPC6_EML_CFG_SECTION 0x1BF000 +#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull +#define TPC6_EML_CS_MAX_OFFSET 0x1000 +#define TPC6_EML_CS_SECTION 0x2000 +#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull +#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC7_EML_SPMU_SECTION 0x1000 +#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull +#define TPC7_EML_ETF_MAX_OFFSET 0x1000 +#define TPC7_EML_ETF_SECTION 0x1000 +#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull +#define TPC7_EML_STM_MAX_OFFSET 0x1000 +#define TPC7_EML_STM_SECTION 0x1000 +#define mmTPC7_EML_ETM_R4_BASE 0x7FFFE04000ull +#define TPC7_EML_ETM_R4_MAX_OFFSET 0x0 +#define TPC7_EML_ETM_R4_SECTION 0x1000 +#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull +#define TPC7_EML_CTI_MAX_OFFSET 0x1000 +#define TPC7_EML_CTI_SECTION 0x1000 +#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull +#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC7_EML_FUNNEL_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull +#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull +#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull +#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull +#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull +#define TPC7_EML_CFG_MAX_OFFSET 0x338 +#define TPC7_EML_CFG_SECTION 0x1BF000 +#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull +#define TPC7_EML_CS_MAX_OFFSET 0x1000 + +#endif /* GOYA_BLOCKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h new file mode 100644 index 000000000..9ff3cb245 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GOYA_MASKS_H_ +#define ASIC_REG_GOYA_MASKS_H_ + +#include "goya_regs.h" + +/* Useful masks for bits in various registers */ +#define QMAN_DMA_ENABLE (\ + (1 << DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT)) + +#define QMAN_DMA_FULLY_TRUSTED (\ + (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_DMA_PARTLY_TRUSTED (\ + (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_DMA_STOP (\ + (1 << DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT)) + +#define QMAN_DMA_IS_STOPPED (\ + (1 << DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT) | \ + (1 << DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT)) + +#define QMAN_DMA_ERR_MSG_EN (\ + (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define QMAN_MME_ENABLE (\ + (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << MME_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << MME_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define CMDQ_MME_ENABLE (\ + (1 << MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_MME_STOP (\ + (1 << MME_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << MME_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << MME_QM_GLBL_CFG1_CP_STOP_SHIFT)) + +#define CMDQ_MME_STOP (\ + (1 << MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) + +#define QMAN_MME_ERR_MSG_EN (\ + (1 << MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define CMDQ_MME_ERR_MSG_EN (\ + (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define QMAN_MME_ERR_PROT (\ + (1 << MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define CMDQ_MME_ERR_PROT (\ + (1 << MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define QMAN_TPC_ENABLE (\ + (1 << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define CMDQ_TPC_ENABLE (\ + (1 << TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_TPC_STOP (\ + (1 << TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT)) + +#define CMDQ_TPC_STOP (\ + (1 << TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) + +#define QMAN_TPC_ERR_MSG_EN (\ + (1 << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define CMDQ_TPC_ERR_MSG_EN (\ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + +#define QMAN_TPC_ERR_PROT (\ + (1 << TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +#define CMDQ_TPC_ERR_PROT (\ + (1 << TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ + (1 << TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) + +/* RESETS */ +#define DMA_MME_TPC_RESET (\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT) + +#define RESET_ALL (\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT |\ + PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT |\ + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT) + +#define CA53_RESET (\ + (~\ + (1 << PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT)\ + ) & 0x7FFFFF) + +#define CPU_RESET_ASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define CPU_RESET_CORE0_DEASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define GOYA_IRQ_HBW_ID_MASK 0x1FFF +#define GOYA_IRQ_HBW_ID_SHIFT 0 +#define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000 +#define GOYA_IRQ_HBW_INTERNAL_ID_SHIFT 13 +#define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000 +#define GOYA_IRQ_HBW_AGENT_ID_SHIFT 16 +#define GOYA_IRQ_HBW_Y_MASK 0xE00000 +#define GOYA_IRQ_HBW_Y_SHIFT 21 +#define GOYA_IRQ_HBW_X_MASK 0x7000000 +#define GOYA_IRQ_HBW_X_SHIFT 24 +#define GOYA_IRQ_LBW_ID_MASK 0xFF +#define GOYA_IRQ_LBW_ID_SHIFT 0 +#define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700 +#define GOYA_IRQ_LBW_INTERNAL_ID_SHIFT 8 +#define GOYA_IRQ_LBW_AGENT_ID_MASK 0xF800 +#define GOYA_IRQ_LBW_AGENT_ID_SHIFT 11 +#define GOYA_IRQ_LBW_Y_MASK 0x70000 +#define GOYA_IRQ_LBW_Y_SHIFT 16 +#define GOYA_IRQ_LBW_X_MASK 0x380000 +#define GOYA_IRQ_LBW_X_SHIFT 19 + +#define DMA_QM_IDLE_MASK (DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_CP_IDLE_MASK | \ + DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK) + +#define TPC_QM_IDLE_MASK (TPC0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + TPC0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + TPC0_QM_GLBL_STS0_CP_IDLE_MASK) + +#define TPC_CMDQ_IDLE_MASK (TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ + TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK) + +#define TPC_CFG_IDLE_MASK (TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ + TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ + TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK) + +#define MME_QM_IDLE_MASK (MME_QM_GLBL_STS0_PQF_IDLE_MASK | \ + MME_QM_GLBL_STS0_CQF_IDLE_MASK | \ + MME_QM_GLBL_STS0_CP_IDLE_MASK) + +#define MME_CMDQ_IDLE_MASK (MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ + MME_CMDQ_GLBL_STS0_CP_IDLE_MASK) + +#define MME_ARCH_IDLE_MASK (MME_ARCH_STATUS_SB_A_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_B_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_CIN_EMPTY_MASK | \ + MME_ARCH_STATUS_SB_COUT_EMPTY_MASK) + +#define MME_SHADOW_IDLE_MASK (MME_SHADOW_0_STATUS_A_MASK | \ + MME_SHADOW_0_STATUS_B_MASK | \ + MME_SHADOW_0_STATUS_CIN_MASK | \ + MME_SHADOW_0_STATUS_COUT_MASK | \ + MME_SHADOW_0_STATUS_TE_MASK | \ + MME_SHADOW_0_STATUS_LD_MASK | \ + MME_SHADOW_0_STATUS_ST_MASK) + +#define TPC1_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC2_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC3_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC4_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC5_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC6_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT +#define TPC7_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT + +#define DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT +#define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT + +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 +#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 + +#endif /* ASIC_REG_GOYA_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h new file mode 100644 index 000000000..ce65c9da5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GOYA_REGS_H_ +#define ASIC_REG_GOYA_REGS_H_ + +#include "goya_blocks.h" +#include "stlb_regs.h" +#include "mmu_regs.h" +#include "pcie_aux_regs.h" +#include "pcie_wrap_regs.h" +#include "psoc_global_conf_regs.h" +#include "psoc_spi_regs.h" +#include "psoc_mme_pll_regs.h" +#include "psoc_pci_pll_regs.h" +#include "psoc_emmc_pll_regs.h" +#include "psoc_timestamp_regs.h" +#include "cpu_if_regs.h" +#include "cpu_ca53_cfg_regs.h" +#include "cpu_pll_regs.h" +#include "ic_pll_regs.h" +#include "mc_pll_regs.h" +#include "tpc_pll_regs.h" +#include "dma_qm_0_regs.h" +#include "dma_qm_1_regs.h" +#include "dma_qm_2_regs.h" +#include "dma_qm_3_regs.h" +#include "dma_qm_4_regs.h" +#include "dma_ch_0_regs.h" +#include "dma_ch_1_regs.h" +#include "dma_ch_2_regs.h" +#include "dma_ch_3_regs.h" +#include "dma_ch_4_regs.h" +#include "dma_macro_regs.h" +#include "dma_nrtr_regs.h" +#include "pci_nrtr_regs.h" +#include "sram_y0_x0_rtr_regs.h" +#include "sram_y0_x1_rtr_regs.h" +#include "sram_y0_x2_rtr_regs.h" +#include "sram_y0_x3_rtr_regs.h" +#include "sram_y0_x4_rtr_regs.h" +#include "mme_regs.h" +#include "mme_qm_regs.h" +#include "mme_cmdq_regs.h" +#include "mme1_rtr_regs.h" +#include "mme2_rtr_regs.h" +#include "mme3_rtr_regs.h" +#include "mme4_rtr_regs.h" +#include "mme5_rtr_regs.h" +#include "mme6_rtr_regs.h" +#include "tpc0_cfg_regs.h" +#include "tpc1_cfg_regs.h" +#include "tpc2_cfg_regs.h" +#include "tpc3_cfg_regs.h" +#include "tpc4_cfg_regs.h" +#include "tpc5_cfg_regs.h" +#include "tpc6_cfg_regs.h" +#include "tpc7_cfg_regs.h" +#include "tpc0_qm_regs.h" +#include "tpc1_qm_regs.h" +#include "tpc2_qm_regs.h" +#include "tpc3_qm_regs.h" +#include "tpc4_qm_regs.h" +#include "tpc5_qm_regs.h" +#include "tpc6_qm_regs.h" +#include "tpc7_qm_regs.h" +#include "tpc0_cmdq_regs.h" +#include "tpc1_cmdq_regs.h" +#include "tpc2_cmdq_regs.h" +#include "tpc3_cmdq_regs.h" +#include "tpc4_cmdq_regs.h" +#include "tpc5_cmdq_regs.h" +#include "tpc6_cmdq_regs.h" +#include "tpc7_cmdq_regs.h" +#include "tpc0_nrtr_regs.h" +#include "tpc1_rtr_regs.h" +#include "tpc2_rtr_regs.h" +#include "tpc3_rtr_regs.h" +#include "tpc4_rtr_regs.h" +#include "tpc5_rtr_regs.h" +#include "tpc6_rtr_regs.h" +#include "tpc7_nrtr_regs.h" +#include "tpc0_eml_cfg_regs.h" +#include "psoc_etr_regs.h" + +#include "psoc_global_conf_masks.h" +#include "dma_macro_masks.h" +#include "dma_qm_0_masks.h" +#include "dma_ch_0_masks.h" +#include "tpc0_qm_masks.h" +#include "tpc0_cmdq_masks.h" +#include "mme_qm_masks.h" +#include "mme_cmdq_masks.h" +#include "tpc0_cfg_masks.h" +#include "tpc0_eml_cfg_masks.h" +#include "mme1_rtr_masks.h" +#include "tpc0_nrtr_masks.h" +#include "dma_nrtr_masks.h" +#include "pci_nrtr_masks.h" +#include "stlb_masks.h" +#include "cpu_ca53_cfg_masks.h" +#include "mmu_masks.h" +#include "mme_masks.h" + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 +#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0xC02948 + +#define mmSYNC_MNGR_MON_PAY_ADDRL_0 0x113000 +#define mmSYNC_MNGR_SOB_OBJ_0 0x112000 +#define mmSYNC_MNGR_SOB_OBJ_1000 0x112FA0 +#define mmSYNC_MNGR_SOB_OBJ_1007 0x112FBC +#define mmSYNC_MNGR_SOB_OBJ_1023 0x112FFC +#define mmSYNC_MNGR_MON_STATUS_0 0x114000 +#define mmSYNC_MNGR_MON_STATUS_255 0x1143FC + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 + +#endif /* ASIC_REG_GOYA_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h new file mode 100644 index 000000000..4ae7fed8b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_IC_PLL_REGS_H_ +#define ASIC_REG_IC_PLL_REGS_H_ + +/* + ***************************************** + * IC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmIC_PLL_NR 0x4A3100 + +#define mmIC_PLL_NF 0x4A3104 + +#define mmIC_PLL_OD 0x4A3108 + +#define mmIC_PLL_NB 0x4A310C + +#define mmIC_PLL_CFG 0x4A3110 + +#define mmIC_PLL_LOSE_MASK 0x4A3120 + +#define mmIC_PLL_LOCK_INTR 0x4A3128 + +#define mmIC_PLL_LOCK_BYPASS 0x4A312C + +#define mmIC_PLL_DATA_CHNG 0x4A3130 + +#define mmIC_PLL_RST 0x4A3134 + +#define mmIC_PLL_SLIP_WD_CNTR 0x4A3150 + +#define mmIC_PLL_DIV_FACTOR_0 0x4A3200 + +#define mmIC_PLL_DIV_FACTOR_1 0x4A3204 + +#define mmIC_PLL_DIV_FACTOR_2 0x4A3208 + +#define mmIC_PLL_DIV_FACTOR_3 0x4A320C + +#define mmIC_PLL_DIV_FACTOR_CMD_0 0x4A3220 + +#define mmIC_PLL_DIV_FACTOR_CMD_1 0x4A3224 + +#define mmIC_PLL_DIV_FACTOR_CMD_2 0x4A3228 + +#define mmIC_PLL_DIV_FACTOR_CMD_3 0x4A322C + +#define mmIC_PLL_DIV_SEL_0 0x4A3280 + +#define mmIC_PLL_DIV_SEL_1 0x4A3284 + +#define mmIC_PLL_DIV_SEL_2 0x4A3288 + +#define mmIC_PLL_DIV_SEL_3 0x4A328C + +#define mmIC_PLL_DIV_EN_0 0x4A32A0 + +#define mmIC_PLL_DIV_EN_1 0x4A32A4 + +#define mmIC_PLL_DIV_EN_2 0x4A32A8 + +#define mmIC_PLL_DIV_EN_3 0x4A32AC + +#define mmIC_PLL_DIV_FACTOR_BUSY_0 0x4A32C0 + +#define mmIC_PLL_DIV_FACTOR_BUSY_1 0x4A32C4 + +#define mmIC_PLL_DIV_FACTOR_BUSY_2 0x4A32C8 + +#define mmIC_PLL_DIV_FACTOR_BUSY_3 0x4A32CC + +#define mmIC_PLL_CLK_GATER 0x4A3300 + +#define mmIC_PLL_CLK_RLX_0 0x4A3310 + +#define mmIC_PLL_CLK_RLX_1 0x4A3314 + +#define mmIC_PLL_CLK_RLX_2 0x4A3318 + +#define mmIC_PLL_CLK_RLX_3 0x4A331C + +#define mmIC_PLL_REF_CNTR_PERIOD 0x4A3400 + +#define mmIC_PLL_REF_LOW_THRESHOLD 0x4A3410 + +#define mmIC_PLL_REF_HIGH_THRESHOLD 0x4A3420 + +#define mmIC_PLL_PLL_NOT_STABLE 0x4A3430 + +#define mmIC_PLL_FREQ_CALC_EN 0x4A3440 + +#endif /* ASIC_REG_IC_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h new file mode 100644 index 000000000..6d35d8527 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MC_PLL_REGS_H_ +#define ASIC_REG_MC_PLL_REGS_H_ + +/* + ***************************************** + * MC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmMC_PLL_NR 0x4A1100 + +#define mmMC_PLL_NF 0x4A1104 + +#define mmMC_PLL_OD 0x4A1108 + +#define mmMC_PLL_NB 0x4A110C + +#define mmMC_PLL_CFG 0x4A1110 + +#define mmMC_PLL_LOSE_MASK 0x4A1120 + +#define mmMC_PLL_LOCK_INTR 0x4A1128 + +#define mmMC_PLL_LOCK_BYPASS 0x4A112C + +#define mmMC_PLL_DATA_CHNG 0x4A1130 + +#define mmMC_PLL_RST 0x4A1134 + +#define mmMC_PLL_SLIP_WD_CNTR 0x4A1150 + +#define mmMC_PLL_DIV_FACTOR_0 0x4A1200 + +#define mmMC_PLL_DIV_FACTOR_1 0x4A1204 + +#define mmMC_PLL_DIV_FACTOR_2 0x4A1208 + +#define mmMC_PLL_DIV_FACTOR_3 0x4A120C + +#define mmMC_PLL_DIV_FACTOR_CMD_0 0x4A1220 + +#define mmMC_PLL_DIV_FACTOR_CMD_1 0x4A1224 + +#define mmMC_PLL_DIV_FACTOR_CMD_2 0x4A1228 + +#define mmMC_PLL_DIV_FACTOR_CMD_3 0x4A122C + +#define mmMC_PLL_DIV_SEL_0 0x4A1280 + +#define mmMC_PLL_DIV_SEL_1 0x4A1284 + +#define mmMC_PLL_DIV_SEL_2 0x4A1288 + +#define mmMC_PLL_DIV_SEL_3 0x4A128C + +#define mmMC_PLL_DIV_EN_0 0x4A12A0 + +#define mmMC_PLL_DIV_EN_1 0x4A12A4 + +#define mmMC_PLL_DIV_EN_2 0x4A12A8 + +#define mmMC_PLL_DIV_EN_3 0x4A12AC + +#define mmMC_PLL_DIV_FACTOR_BUSY_0 0x4A12C0 + +#define mmMC_PLL_DIV_FACTOR_BUSY_1 0x4A12C4 + +#define mmMC_PLL_DIV_FACTOR_BUSY_2 0x4A12C8 + +#define mmMC_PLL_DIV_FACTOR_BUSY_3 0x4A12CC + +#define mmMC_PLL_CLK_GATER 0x4A1300 + +#define mmMC_PLL_CLK_RLX_0 0x4A1310 + +#define mmMC_PLL_CLK_RLX_1 0x4A1314 + +#define mmMC_PLL_CLK_RLX_2 0x4A1318 + +#define mmMC_PLL_CLK_RLX_3 0x4A131C + +#define mmMC_PLL_REF_CNTR_PERIOD 0x4A1400 + +#define mmMC_PLL_REF_LOW_THRESHOLD 0x4A1410 + +#define mmMC_PLL_REF_HIGH_THRESHOLD 0x4A1420 + +#define mmMC_PLL_PLL_NOT_STABLE 0x4A1430 + +#define mmMC_PLL_FREQ_CALC_EN 0x4A1440 + +#endif /* ASIC_REG_MC_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h new file mode 100644 index 000000000..6c23f8b96 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h @@ -0,0 +1,652 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_RTR_MASKS_H_ +#define ASIC_REG_MME1_RTR_MASKS_H_ + +/* + ***************************************** + * MME1_RTR (Prototype: MME_RTR) + ***************************************** + */ + +/* MME1_RTR_HBW_RD_RQ_E_ARB */ +#define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_W_ARB */ +#define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_N_ARB */ +#define MME1_RTR_HBW_RD_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_S_ARB */ +#define MME1_RTR_HBW_RD_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RQ_L_ARB */ +#define MME1_RTR_HBW_RD_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_RD_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_E_ARB_MAX */ +#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_W_ARB_MAX */ +#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_N_ARB_MAX */ +#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_S_ARB_MAX */ +#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_L_ARB_MAX */ +#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_HBW_RD_RS_MAX_CREDIT */ +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_MASK 0x3F +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_MASK 0x3F00 + +/* MME1_RTR_HBW_WR_RQ_MAX_CREDIT */ +#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_MASK 0x3F + +/* MME1_RTR_HBW_RD_RQ_MAX_CREDIT */ +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_SHIFT 0 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_MASK 0x3F +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_SHIFT 8 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_MASK 0x3F00 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_SHIFT 16 +#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_MASK 0x3F0000 + +/* MME1_RTR_HBW_RD_RS_E_ARB */ +#define MME1_RTR_HBW_RD_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_W_ARB */ +#define MME1_RTR_HBW_RD_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_N_ARB */ +#define MME1_RTR_HBW_RD_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_S_ARB */ +#define MME1_RTR_HBW_RD_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_RD_RS_L_ARB */ +#define MME1_RTR_HBW_RD_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_RD_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_RD_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_RD_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_RD_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_RD_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_RD_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_RD_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_E_ARB */ +#define MME1_RTR_HBW_WR_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_W_ARB */ +#define MME1_RTR_HBW_WR_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_N_ARB */ +#define MME1_RTR_HBW_WR_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_S_ARB */ +#define MME1_RTR_HBW_WR_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RQ_L_ARB */ +#define MME1_RTR_HBW_WR_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_WR_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_E_ARB */ +#define MME1_RTR_HBW_WR_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_W_ARB */ +#define MME1_RTR_HBW_WR_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_N_ARB */ +#define MME1_RTR_HBW_WR_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_S_ARB */ +#define MME1_RTR_HBW_WR_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_HBW_WR_RS_L_ARB */ +#define MME1_RTR_HBW_WR_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_HBW_WR_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_HBW_WR_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_HBW_WR_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_HBW_WR_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_HBW_WR_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_HBW_WR_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_HBW_WR_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_E_ARB */ +#define MME1_RTR_LBW_RD_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_W_ARB */ +#define MME1_RTR_LBW_RD_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_N_ARB */ +#define MME1_RTR_LBW_RD_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_S_ARB */ +#define MME1_RTR_LBW_RD_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RQ_L_ARB */ +#define MME1_RTR_LBW_RD_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_RD_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_E_ARB_MAX */ +#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_W_ARB_MAX */ +#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_N_ARB_MAX */ +#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_S_ARB_MAX */ +#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_L_ARB_MAX */ +#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_LBW_SRAM_MAX_CREDIT */ +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_SHIFT 0 +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_MASK 0x3F +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_SHIFT 8 +#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_MASK 0x3F00 + +/* MME1_RTR_LBW_RD_RS_E_ARB */ +#define MME1_RTR_LBW_RD_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_W_ARB */ +#define MME1_RTR_LBW_RD_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_N_ARB */ +#define MME1_RTR_LBW_RD_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_S_ARB */ +#define MME1_RTR_LBW_RD_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_RD_RS_L_ARB */ +#define MME1_RTR_LBW_RD_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_RD_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_RD_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_RD_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_RD_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_RD_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_RD_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_RD_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_E_ARB */ +#define MME1_RTR_LBW_WR_RQ_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_W_ARB */ +#define MME1_RTR_LBW_WR_RQ_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_N_ARB */ +#define MME1_RTR_LBW_WR_RQ_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_S_ARB */ +#define MME1_RTR_LBW_WR_RQ_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RQ_L_ARB */ +#define MME1_RTR_LBW_WR_RQ_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RQ_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RQ_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RQ_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RQ_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RQ_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RQ_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_WR_RQ_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_E_ARB */ +#define MME1_RTR_LBW_WR_RS_E_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_E_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_E_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_E_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_E_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_E_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_E_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_W_ARB */ +#define MME1_RTR_LBW_WR_RS_W_ARB_E_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_W_ARB_E_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_W_ARB_S_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_W_ARB_S_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_W_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_W_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_W_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_N_ARB */ +#define MME1_RTR_LBW_WR_RS_N_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_N_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_N_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_N_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_N_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_N_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_N_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_S_ARB */ +#define MME1_RTR_LBW_WR_RS_S_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_S_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_S_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_S_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_S_ARB_N_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_S_ARB_N_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_S_ARB_L_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_LBW_WR_RS_L_ARB */ +#define MME1_RTR_LBW_WR_RS_L_ARB_W_SHIFT 0 +#define MME1_RTR_LBW_WR_RS_L_ARB_W_MASK 0x7 +#define MME1_RTR_LBW_WR_RS_L_ARB_E_SHIFT 8 +#define MME1_RTR_LBW_WR_RS_L_ARB_E_MASK 0x700 +#define MME1_RTR_LBW_WR_RS_L_ARB_S_SHIFT 16 +#define MME1_RTR_LBW_WR_RS_L_ARB_S_MASK 0x70000 +#define MME1_RTR_LBW_WR_RS_L_ARB_N_SHIFT 24 +#define MME1_RTR_LBW_WR_RS_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_DBG_E_ARB */ +#define MME1_RTR_DBG_E_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_E_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_E_ARB_S_SHIFT 8 +#define MME1_RTR_DBG_E_ARB_S_MASK 0x700 +#define MME1_RTR_DBG_E_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_E_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_E_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_E_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_W_ARB */ +#define MME1_RTR_DBG_W_ARB_E_SHIFT 0 +#define MME1_RTR_DBG_W_ARB_E_MASK 0x7 +#define MME1_RTR_DBG_W_ARB_S_SHIFT 8 +#define MME1_RTR_DBG_W_ARB_S_MASK 0x700 +#define MME1_RTR_DBG_W_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_W_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_W_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_W_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_N_ARB */ +#define MME1_RTR_DBG_N_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_N_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_N_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_N_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_N_ARB_S_SHIFT 16 +#define MME1_RTR_DBG_N_ARB_S_MASK 0x70000 +#define MME1_RTR_DBG_N_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_N_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_S_ARB */ +#define MME1_RTR_DBG_S_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_S_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_S_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_S_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_S_ARB_N_SHIFT 16 +#define MME1_RTR_DBG_S_ARB_N_MASK 0x70000 +#define MME1_RTR_DBG_S_ARB_L_SHIFT 24 +#define MME1_RTR_DBG_S_ARB_L_MASK 0x7000000 + +/* MME1_RTR_DBG_L_ARB */ +#define MME1_RTR_DBG_L_ARB_W_SHIFT 0 +#define MME1_RTR_DBG_L_ARB_W_MASK 0x7 +#define MME1_RTR_DBG_L_ARB_E_SHIFT 8 +#define MME1_RTR_DBG_L_ARB_E_MASK 0x700 +#define MME1_RTR_DBG_L_ARB_S_SHIFT 16 +#define MME1_RTR_DBG_L_ARB_S_MASK 0x70000 +#define MME1_RTR_DBG_L_ARB_N_SHIFT 24 +#define MME1_RTR_DBG_L_ARB_N_MASK 0x7000000 + +/* MME1_RTR_DBG_E_ARB_MAX */ +#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_W_ARB_MAX */ +#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_N_ARB_MAX */ +#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_S_ARB_MAX */ +#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_DBG_L_ARB_MAX */ +#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* MME1_RTR_SPLIT_COEF */ +#define MME1_RTR_SPLIT_COEF_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_CFG */ +#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 4 +#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x10 +#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 5 +#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x20 +#define MME1_RTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define MME1_RTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* MME1_RTR_SPLIT_RD_SAT */ +#define MME1_RTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_RD_RST_TOKEN */ +#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_RD_TIMEOUT */ +#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_SPLIT_WR_SAT */ +#define MME1_RTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* MME1_RTR_WPLIT_WR_TST_TOLEN */ +#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* MME1_RTR_SPLIT_WR_TIMEOUT */ +#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_HIT */ +#define MME1_RTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define MME1_RTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* MME1_RTR_HBW_RANGE_MASK_L */ +#define MME1_RTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_MASK_H */ +#define MME1_RTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* MME1_RTR_HBW_RANGE_BASE_L */ +#define MME1_RTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* MME1_RTR_HBW_RANGE_BASE_H */ +#define MME1_RTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define MME1_RTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* MME1_RTR_LBW_RANGE_HIT */ +#define MME1_RTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define MME1_RTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* MME1_RTR_LBW_RANGE_MASK */ +#define MME1_RTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define MME1_RTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* MME1_RTR_LBW_RANGE_BASE */ +#define MME1_RTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define MME1_RTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* MME1_RTR_RGLTR */ +#define MME1_RTR_RGLTR_WR_EN_SHIFT 0 +#define MME1_RTR_RGLTR_WR_EN_MASK 0x1 +#define MME1_RTR_RGLTR_RD_EN_SHIFT 4 +#define MME1_RTR_RGLTR_RD_EN_MASK 0x10 + +/* MME1_RTR_RGLTR_WR_RESULT */ +#define MME1_RTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define MME1_RTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* MME1_RTR_RGLTR_RD_RESULT */ +#define MME1_RTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define MME1_RTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* MME1_RTR_SCRAMB_EN */ +#define MME1_RTR_SCRAMB_EN_VAL_SHIFT 0 +#define MME1_RTR_SCRAMB_EN_VAL_MASK 0x1 + +/* MME1_RTR_NON_LIN_SCRAMB */ +#define MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define MME1_RTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_MME1_RTR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h new file mode 100644 index 000000000..122e9d529 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_RTR_REGS_H_ +#define ASIC_REG_MME1_RTR_REGS_H_ + +/* + ***************************************** + * MME1_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME1_RTR_HBW_RD_RQ_E_ARB 0x40100 + +#define mmMME1_RTR_HBW_RD_RQ_W_ARB 0x40104 + +#define mmMME1_RTR_HBW_RD_RQ_N_ARB 0x40108 + +#define mmMME1_RTR_HBW_RD_RQ_S_ARB 0x4010C + +#define mmMME1_RTR_HBW_RD_RQ_L_ARB 0x40110 + +#define mmMME1_RTR_HBW_E_ARB_MAX 0x40120 + +#define mmMME1_RTR_HBW_W_ARB_MAX 0x40124 + +#define mmMME1_RTR_HBW_N_ARB_MAX 0x40128 + +#define mmMME1_RTR_HBW_S_ARB_MAX 0x4012C + +#define mmMME1_RTR_HBW_L_ARB_MAX 0x40130 + +#define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT 0x40140 + +#define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT 0x40144 + +#define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT 0x40148 + +#define mmMME1_RTR_HBW_RD_RS_E_ARB 0x40150 + +#define mmMME1_RTR_HBW_RD_RS_W_ARB 0x40154 + +#define mmMME1_RTR_HBW_RD_RS_N_ARB 0x40158 + +#define mmMME1_RTR_HBW_RD_RS_S_ARB 0x4015C + +#define mmMME1_RTR_HBW_RD_RS_L_ARB 0x40160 + +#define mmMME1_RTR_HBW_WR_RQ_E_ARB 0x40170 + +#define mmMME1_RTR_HBW_WR_RQ_W_ARB 0x40174 + +#define mmMME1_RTR_HBW_WR_RQ_N_ARB 0x40178 + +#define mmMME1_RTR_HBW_WR_RQ_S_ARB 0x4017C + +#define mmMME1_RTR_HBW_WR_RQ_L_ARB 0x40180 + +#define mmMME1_RTR_HBW_WR_RS_E_ARB 0x40190 + +#define mmMME1_RTR_HBW_WR_RS_W_ARB 0x40194 + +#define mmMME1_RTR_HBW_WR_RS_N_ARB 0x40198 + +#define mmMME1_RTR_HBW_WR_RS_S_ARB 0x4019C + +#define mmMME1_RTR_HBW_WR_RS_L_ARB 0x401A0 + +#define mmMME1_RTR_LBW_RD_RQ_E_ARB 0x40200 + +#define mmMME1_RTR_LBW_RD_RQ_W_ARB 0x40204 + +#define mmMME1_RTR_LBW_RD_RQ_N_ARB 0x40208 + +#define mmMME1_RTR_LBW_RD_RQ_S_ARB 0x4020C + +#define mmMME1_RTR_LBW_RD_RQ_L_ARB 0x40210 + +#define mmMME1_RTR_LBW_E_ARB_MAX 0x40220 + +#define mmMME1_RTR_LBW_W_ARB_MAX 0x40224 + +#define mmMME1_RTR_LBW_N_ARB_MAX 0x40228 + +#define mmMME1_RTR_LBW_S_ARB_MAX 0x4022C + +#define mmMME1_RTR_LBW_L_ARB_MAX 0x40230 + +#define mmMME1_RTR_LBW_SRAM_MAX_CREDIT 0x40240 + +#define mmMME1_RTR_LBW_RD_RS_E_ARB 0x40250 + +#define mmMME1_RTR_LBW_RD_RS_W_ARB 0x40254 + +#define mmMME1_RTR_LBW_RD_RS_N_ARB 0x40258 + +#define mmMME1_RTR_LBW_RD_RS_S_ARB 0x4025C + +#define mmMME1_RTR_LBW_RD_RS_L_ARB 0x40260 + +#define mmMME1_RTR_LBW_WR_RQ_E_ARB 0x40270 + +#define mmMME1_RTR_LBW_WR_RQ_W_ARB 0x40274 + +#define mmMME1_RTR_LBW_WR_RQ_N_ARB 0x40278 + +#define mmMME1_RTR_LBW_WR_RQ_S_ARB 0x4027C + +#define mmMME1_RTR_LBW_WR_RQ_L_ARB 0x40280 + +#define mmMME1_RTR_LBW_WR_RS_E_ARB 0x40290 + +#define mmMME1_RTR_LBW_WR_RS_W_ARB 0x40294 + +#define mmMME1_RTR_LBW_WR_RS_N_ARB 0x40298 + +#define mmMME1_RTR_LBW_WR_RS_S_ARB 0x4029C + +#define mmMME1_RTR_LBW_WR_RS_L_ARB 0x402A0 + +#define mmMME1_RTR_DBG_E_ARB 0x40300 + +#define mmMME1_RTR_DBG_W_ARB 0x40304 + +#define mmMME1_RTR_DBG_N_ARB 0x40308 + +#define mmMME1_RTR_DBG_S_ARB 0x4030C + +#define mmMME1_RTR_DBG_L_ARB 0x40310 + +#define mmMME1_RTR_DBG_E_ARB_MAX 0x40320 + +#define mmMME1_RTR_DBG_W_ARB_MAX 0x40324 + +#define mmMME1_RTR_DBG_N_ARB_MAX 0x40328 + +#define mmMME1_RTR_DBG_S_ARB_MAX 0x4032C + +#define mmMME1_RTR_DBG_L_ARB_MAX 0x40330 + +#define mmMME1_RTR_SPLIT_COEF_0 0x40400 + +#define mmMME1_RTR_SPLIT_COEF_1 0x40404 + +#define mmMME1_RTR_SPLIT_COEF_2 0x40408 + +#define mmMME1_RTR_SPLIT_COEF_3 0x4040C + +#define mmMME1_RTR_SPLIT_COEF_4 0x40410 + +#define mmMME1_RTR_SPLIT_COEF_5 0x40414 + +#define mmMME1_RTR_SPLIT_COEF_6 0x40418 + +#define mmMME1_RTR_SPLIT_COEF_7 0x4041C + +#define mmMME1_RTR_SPLIT_COEF_8 0x40420 + +#define mmMME1_RTR_SPLIT_COEF_9 0x40424 + +#define mmMME1_RTR_SPLIT_CFG 0x40440 + +#define mmMME1_RTR_SPLIT_RD_SAT 0x40444 + +#define mmMME1_RTR_SPLIT_RD_RST_TOKEN 0x40448 + +#define mmMME1_RTR_SPLIT_RD_TIMEOUT_0 0x4044C + +#define mmMME1_RTR_SPLIT_RD_TIMEOUT_1 0x40450 + +#define mmMME1_RTR_SPLIT_WR_SAT 0x40454 + +#define mmMME1_RTR_WPLIT_WR_TST_TOLEN 0x40458 + +#define mmMME1_RTR_SPLIT_WR_TIMEOUT_0 0x4045C + +#define mmMME1_RTR_SPLIT_WR_TIMEOUT_1 0x40460 + +#define mmMME1_RTR_HBW_RANGE_HIT 0x40470 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_0 0x40480 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_1 0x40484 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_2 0x40488 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_3 0x4048C + +#define mmMME1_RTR_HBW_RANGE_MASK_L_4 0x40490 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_5 0x40494 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_6 0x40498 + +#define mmMME1_RTR_HBW_RANGE_MASK_L_7 0x4049C + +#define mmMME1_RTR_HBW_RANGE_MASK_H_0 0x404A0 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_1 0x404A4 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_2 0x404A8 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_3 0x404AC + +#define mmMME1_RTR_HBW_RANGE_MASK_H_4 0x404B0 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_5 0x404B4 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_6 0x404B8 + +#define mmMME1_RTR_HBW_RANGE_MASK_H_7 0x404BC + +#define mmMME1_RTR_HBW_RANGE_BASE_L_0 0x404C0 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_1 0x404C4 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_2 0x404C8 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_3 0x404CC + +#define mmMME1_RTR_HBW_RANGE_BASE_L_4 0x404D0 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_5 0x404D4 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_6 0x404D8 + +#define mmMME1_RTR_HBW_RANGE_BASE_L_7 0x404DC + +#define mmMME1_RTR_HBW_RANGE_BASE_H_0 0x404E0 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_1 0x404E4 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_2 0x404E8 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_3 0x404EC + +#define mmMME1_RTR_HBW_RANGE_BASE_H_4 0x404F0 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_5 0x404F4 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_6 0x404F8 + +#define mmMME1_RTR_HBW_RANGE_BASE_H_7 0x404FC + +#define mmMME1_RTR_LBW_RANGE_HIT 0x40500 + +#define mmMME1_RTR_LBW_RANGE_MASK_0 0x40510 + +#define mmMME1_RTR_LBW_RANGE_MASK_1 0x40514 + +#define mmMME1_RTR_LBW_RANGE_MASK_2 0x40518 + +#define mmMME1_RTR_LBW_RANGE_MASK_3 0x4051C + +#define mmMME1_RTR_LBW_RANGE_MASK_4 0x40520 + +#define mmMME1_RTR_LBW_RANGE_MASK_5 0x40524 + +#define mmMME1_RTR_LBW_RANGE_MASK_6 0x40528 + +#define mmMME1_RTR_LBW_RANGE_MASK_7 0x4052C + +#define mmMME1_RTR_LBW_RANGE_MASK_8 0x40530 + +#define mmMME1_RTR_LBW_RANGE_MASK_9 0x40534 + +#define mmMME1_RTR_LBW_RANGE_MASK_10 0x40538 + +#define mmMME1_RTR_LBW_RANGE_MASK_11 0x4053C + +#define mmMME1_RTR_LBW_RANGE_MASK_12 0x40540 + +#define mmMME1_RTR_LBW_RANGE_MASK_13 0x40544 + +#define mmMME1_RTR_LBW_RANGE_MASK_14 0x40548 + +#define mmMME1_RTR_LBW_RANGE_MASK_15 0x4054C + +#define mmMME1_RTR_LBW_RANGE_BASE_0 0x40550 + +#define mmMME1_RTR_LBW_RANGE_BASE_1 0x40554 + +#define mmMME1_RTR_LBW_RANGE_BASE_2 0x40558 + +#define mmMME1_RTR_LBW_RANGE_BASE_3 0x4055C + +#define mmMME1_RTR_LBW_RANGE_BASE_4 0x40560 + +#define mmMME1_RTR_LBW_RANGE_BASE_5 0x40564 + +#define mmMME1_RTR_LBW_RANGE_BASE_6 0x40568 + +#define mmMME1_RTR_LBW_RANGE_BASE_7 0x4056C + +#define mmMME1_RTR_LBW_RANGE_BASE_8 0x40570 + +#define mmMME1_RTR_LBW_RANGE_BASE_9 0x40574 + +#define mmMME1_RTR_LBW_RANGE_BASE_10 0x40578 + +#define mmMME1_RTR_LBW_RANGE_BASE_11 0x4057C + +#define mmMME1_RTR_LBW_RANGE_BASE_12 0x40580 + +#define mmMME1_RTR_LBW_RANGE_BASE_13 0x40584 + +#define mmMME1_RTR_LBW_RANGE_BASE_14 0x40588 + +#define mmMME1_RTR_LBW_RANGE_BASE_15 0x4058C + +#define mmMME1_RTR_RGLTR 0x40590 + +#define mmMME1_RTR_RGLTR_WR_RESULT 0x40594 + +#define mmMME1_RTR_RGLTR_RD_RESULT 0x40598 + +#define mmMME1_RTR_SCRAMB_EN 0x40600 + +#define mmMME1_RTR_NON_LIN_SCRAMB 0x40604 + +#endif /* ASIC_REG_MME1_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h new file mode 100644 index 000000000..00ce2252b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_RTR_REGS_H_ +#define ASIC_REG_MME2_RTR_REGS_H_ + +/* + ***************************************** + * MME2_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME2_RTR_HBW_RD_RQ_E_ARB 0x80100 + +#define mmMME2_RTR_HBW_RD_RQ_W_ARB 0x80104 + +#define mmMME2_RTR_HBW_RD_RQ_N_ARB 0x80108 + +#define mmMME2_RTR_HBW_RD_RQ_S_ARB 0x8010C + +#define mmMME2_RTR_HBW_RD_RQ_L_ARB 0x80110 + +#define mmMME2_RTR_HBW_E_ARB_MAX 0x80120 + +#define mmMME2_RTR_HBW_W_ARB_MAX 0x80124 + +#define mmMME2_RTR_HBW_N_ARB_MAX 0x80128 + +#define mmMME2_RTR_HBW_S_ARB_MAX 0x8012C + +#define mmMME2_RTR_HBW_L_ARB_MAX 0x80130 + +#define mmMME2_RTR_HBW_RD_RS_MAX_CREDIT 0x80140 + +#define mmMME2_RTR_HBW_WR_RQ_MAX_CREDIT 0x80144 + +#define mmMME2_RTR_HBW_RD_RQ_MAX_CREDIT 0x80148 + +#define mmMME2_RTR_HBW_RD_RS_E_ARB 0x80150 + +#define mmMME2_RTR_HBW_RD_RS_W_ARB 0x80154 + +#define mmMME2_RTR_HBW_RD_RS_N_ARB 0x80158 + +#define mmMME2_RTR_HBW_RD_RS_S_ARB 0x8015C + +#define mmMME2_RTR_HBW_RD_RS_L_ARB 0x80160 + +#define mmMME2_RTR_HBW_WR_RQ_E_ARB 0x80170 + +#define mmMME2_RTR_HBW_WR_RQ_W_ARB 0x80174 + +#define mmMME2_RTR_HBW_WR_RQ_N_ARB 0x80178 + +#define mmMME2_RTR_HBW_WR_RQ_S_ARB 0x8017C + +#define mmMME2_RTR_HBW_WR_RQ_L_ARB 0x80180 + +#define mmMME2_RTR_HBW_WR_RS_E_ARB 0x80190 + +#define mmMME2_RTR_HBW_WR_RS_W_ARB 0x80194 + +#define mmMME2_RTR_HBW_WR_RS_N_ARB 0x80198 + +#define mmMME2_RTR_HBW_WR_RS_S_ARB 0x8019C + +#define mmMME2_RTR_HBW_WR_RS_L_ARB 0x801A0 + +#define mmMME2_RTR_LBW_RD_RQ_E_ARB 0x80200 + +#define mmMME2_RTR_LBW_RD_RQ_W_ARB 0x80204 + +#define mmMME2_RTR_LBW_RD_RQ_N_ARB 0x80208 + +#define mmMME2_RTR_LBW_RD_RQ_S_ARB 0x8020C + +#define mmMME2_RTR_LBW_RD_RQ_L_ARB 0x80210 + +#define mmMME2_RTR_LBW_E_ARB_MAX 0x80220 + +#define mmMME2_RTR_LBW_W_ARB_MAX 0x80224 + +#define mmMME2_RTR_LBW_N_ARB_MAX 0x80228 + +#define mmMME2_RTR_LBW_S_ARB_MAX 0x8022C + +#define mmMME2_RTR_LBW_L_ARB_MAX 0x80230 + +#define mmMME2_RTR_LBW_SRAM_MAX_CREDIT 0x80240 + +#define mmMME2_RTR_LBW_RD_RS_E_ARB 0x80250 + +#define mmMME2_RTR_LBW_RD_RS_W_ARB 0x80254 + +#define mmMME2_RTR_LBW_RD_RS_N_ARB 0x80258 + +#define mmMME2_RTR_LBW_RD_RS_S_ARB 0x8025C + +#define mmMME2_RTR_LBW_RD_RS_L_ARB 0x80260 + +#define mmMME2_RTR_LBW_WR_RQ_E_ARB 0x80270 + +#define mmMME2_RTR_LBW_WR_RQ_W_ARB 0x80274 + +#define mmMME2_RTR_LBW_WR_RQ_N_ARB 0x80278 + +#define mmMME2_RTR_LBW_WR_RQ_S_ARB 0x8027C + +#define mmMME2_RTR_LBW_WR_RQ_L_ARB 0x80280 + +#define mmMME2_RTR_LBW_WR_RS_E_ARB 0x80290 + +#define mmMME2_RTR_LBW_WR_RS_W_ARB 0x80294 + +#define mmMME2_RTR_LBW_WR_RS_N_ARB 0x80298 + +#define mmMME2_RTR_LBW_WR_RS_S_ARB 0x8029C + +#define mmMME2_RTR_LBW_WR_RS_L_ARB 0x802A0 + +#define mmMME2_RTR_DBG_E_ARB 0x80300 + +#define mmMME2_RTR_DBG_W_ARB 0x80304 + +#define mmMME2_RTR_DBG_N_ARB 0x80308 + +#define mmMME2_RTR_DBG_S_ARB 0x8030C + +#define mmMME2_RTR_DBG_L_ARB 0x80310 + +#define mmMME2_RTR_DBG_E_ARB_MAX 0x80320 + +#define mmMME2_RTR_DBG_W_ARB_MAX 0x80324 + +#define mmMME2_RTR_DBG_N_ARB_MAX 0x80328 + +#define mmMME2_RTR_DBG_S_ARB_MAX 0x8032C + +#define mmMME2_RTR_DBG_L_ARB_MAX 0x80330 + +#define mmMME2_RTR_SPLIT_COEF_0 0x80400 + +#define mmMME2_RTR_SPLIT_COEF_1 0x80404 + +#define mmMME2_RTR_SPLIT_COEF_2 0x80408 + +#define mmMME2_RTR_SPLIT_COEF_3 0x8040C + +#define mmMME2_RTR_SPLIT_COEF_4 0x80410 + +#define mmMME2_RTR_SPLIT_COEF_5 0x80414 + +#define mmMME2_RTR_SPLIT_COEF_6 0x80418 + +#define mmMME2_RTR_SPLIT_COEF_7 0x8041C + +#define mmMME2_RTR_SPLIT_COEF_8 0x80420 + +#define mmMME2_RTR_SPLIT_COEF_9 0x80424 + +#define mmMME2_RTR_SPLIT_CFG 0x80440 + +#define mmMME2_RTR_SPLIT_RD_SAT 0x80444 + +#define mmMME2_RTR_SPLIT_RD_RST_TOKEN 0x80448 + +#define mmMME2_RTR_SPLIT_RD_TIMEOUT_0 0x8044C + +#define mmMME2_RTR_SPLIT_RD_TIMEOUT_1 0x80450 + +#define mmMME2_RTR_SPLIT_WR_SAT 0x80454 + +#define mmMME2_RTR_WPLIT_WR_TST_TOLEN 0x80458 + +#define mmMME2_RTR_SPLIT_WR_TIMEOUT_0 0x8045C + +#define mmMME2_RTR_SPLIT_WR_TIMEOUT_1 0x80460 + +#define mmMME2_RTR_HBW_RANGE_HIT 0x80470 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_0 0x80480 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_1 0x80484 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_2 0x80488 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_3 0x8048C + +#define mmMME2_RTR_HBW_RANGE_MASK_L_4 0x80490 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_5 0x80494 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_6 0x80498 + +#define mmMME2_RTR_HBW_RANGE_MASK_L_7 0x8049C + +#define mmMME2_RTR_HBW_RANGE_MASK_H_0 0x804A0 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_1 0x804A4 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_2 0x804A8 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_3 0x804AC + +#define mmMME2_RTR_HBW_RANGE_MASK_H_4 0x804B0 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_5 0x804B4 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_6 0x804B8 + +#define mmMME2_RTR_HBW_RANGE_MASK_H_7 0x804BC + +#define mmMME2_RTR_HBW_RANGE_BASE_L_0 0x804C0 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_1 0x804C4 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_2 0x804C8 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_3 0x804CC + +#define mmMME2_RTR_HBW_RANGE_BASE_L_4 0x804D0 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_5 0x804D4 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_6 0x804D8 + +#define mmMME2_RTR_HBW_RANGE_BASE_L_7 0x804DC + +#define mmMME2_RTR_HBW_RANGE_BASE_H_0 0x804E0 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_1 0x804E4 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_2 0x804E8 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_3 0x804EC + +#define mmMME2_RTR_HBW_RANGE_BASE_H_4 0x804F0 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_5 0x804F4 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_6 0x804F8 + +#define mmMME2_RTR_HBW_RANGE_BASE_H_7 0x804FC + +#define mmMME2_RTR_LBW_RANGE_HIT 0x80500 + +#define mmMME2_RTR_LBW_RANGE_MASK_0 0x80510 + +#define mmMME2_RTR_LBW_RANGE_MASK_1 0x80514 + +#define mmMME2_RTR_LBW_RANGE_MASK_2 0x80518 + +#define mmMME2_RTR_LBW_RANGE_MASK_3 0x8051C + +#define mmMME2_RTR_LBW_RANGE_MASK_4 0x80520 + +#define mmMME2_RTR_LBW_RANGE_MASK_5 0x80524 + +#define mmMME2_RTR_LBW_RANGE_MASK_6 0x80528 + +#define mmMME2_RTR_LBW_RANGE_MASK_7 0x8052C + +#define mmMME2_RTR_LBW_RANGE_MASK_8 0x80530 + +#define mmMME2_RTR_LBW_RANGE_MASK_9 0x80534 + +#define mmMME2_RTR_LBW_RANGE_MASK_10 0x80538 + +#define mmMME2_RTR_LBW_RANGE_MASK_11 0x8053C + +#define mmMME2_RTR_LBW_RANGE_MASK_12 0x80540 + +#define mmMME2_RTR_LBW_RANGE_MASK_13 0x80544 + +#define mmMME2_RTR_LBW_RANGE_MASK_14 0x80548 + +#define mmMME2_RTR_LBW_RANGE_MASK_15 0x8054C + +#define mmMME2_RTR_LBW_RANGE_BASE_0 0x80550 + +#define mmMME2_RTR_LBW_RANGE_BASE_1 0x80554 + +#define mmMME2_RTR_LBW_RANGE_BASE_2 0x80558 + +#define mmMME2_RTR_LBW_RANGE_BASE_3 0x8055C + +#define mmMME2_RTR_LBW_RANGE_BASE_4 0x80560 + +#define mmMME2_RTR_LBW_RANGE_BASE_5 0x80564 + +#define mmMME2_RTR_LBW_RANGE_BASE_6 0x80568 + +#define mmMME2_RTR_LBW_RANGE_BASE_7 0x8056C + +#define mmMME2_RTR_LBW_RANGE_BASE_8 0x80570 + +#define mmMME2_RTR_LBW_RANGE_BASE_9 0x80574 + +#define mmMME2_RTR_LBW_RANGE_BASE_10 0x80578 + +#define mmMME2_RTR_LBW_RANGE_BASE_11 0x8057C + +#define mmMME2_RTR_LBW_RANGE_BASE_12 0x80580 + +#define mmMME2_RTR_LBW_RANGE_BASE_13 0x80584 + +#define mmMME2_RTR_LBW_RANGE_BASE_14 0x80588 + +#define mmMME2_RTR_LBW_RANGE_BASE_15 0x8058C + +#define mmMME2_RTR_RGLTR 0x80590 + +#define mmMME2_RTR_RGLTR_WR_RESULT 0x80594 + +#define mmMME2_RTR_RGLTR_RD_RESULT 0x80598 + +#define mmMME2_RTR_SCRAMB_EN 0x80600 + +#define mmMME2_RTR_NON_LIN_SCRAMB 0x80604 + +#endif /* ASIC_REG_MME2_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h new file mode 100644 index 000000000..8e3eb7fd2 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME3_RTR_REGS_H_ +#define ASIC_REG_MME3_RTR_REGS_H_ + +/* + ***************************************** + * MME3_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME3_RTR_HBW_RD_RQ_E_ARB 0xC0100 + +#define mmMME3_RTR_HBW_RD_RQ_W_ARB 0xC0104 + +#define mmMME3_RTR_HBW_RD_RQ_N_ARB 0xC0108 + +#define mmMME3_RTR_HBW_RD_RQ_S_ARB 0xC010C + +#define mmMME3_RTR_HBW_RD_RQ_L_ARB 0xC0110 + +#define mmMME3_RTR_HBW_E_ARB_MAX 0xC0120 + +#define mmMME3_RTR_HBW_W_ARB_MAX 0xC0124 + +#define mmMME3_RTR_HBW_N_ARB_MAX 0xC0128 + +#define mmMME3_RTR_HBW_S_ARB_MAX 0xC012C + +#define mmMME3_RTR_HBW_L_ARB_MAX 0xC0130 + +#define mmMME3_RTR_HBW_RD_RS_MAX_CREDIT 0xC0140 + +#define mmMME3_RTR_HBW_WR_RQ_MAX_CREDIT 0xC0144 + +#define mmMME3_RTR_HBW_RD_RQ_MAX_CREDIT 0xC0148 + +#define mmMME3_RTR_HBW_RD_RS_E_ARB 0xC0150 + +#define mmMME3_RTR_HBW_RD_RS_W_ARB 0xC0154 + +#define mmMME3_RTR_HBW_RD_RS_N_ARB 0xC0158 + +#define mmMME3_RTR_HBW_RD_RS_S_ARB 0xC015C + +#define mmMME3_RTR_HBW_RD_RS_L_ARB 0xC0160 + +#define mmMME3_RTR_HBW_WR_RQ_E_ARB 0xC0170 + +#define mmMME3_RTR_HBW_WR_RQ_W_ARB 0xC0174 + +#define mmMME3_RTR_HBW_WR_RQ_N_ARB 0xC0178 + +#define mmMME3_RTR_HBW_WR_RQ_S_ARB 0xC017C + +#define mmMME3_RTR_HBW_WR_RQ_L_ARB 0xC0180 + +#define mmMME3_RTR_HBW_WR_RS_E_ARB 0xC0190 + +#define mmMME3_RTR_HBW_WR_RS_W_ARB 0xC0194 + +#define mmMME3_RTR_HBW_WR_RS_N_ARB 0xC0198 + +#define mmMME3_RTR_HBW_WR_RS_S_ARB 0xC019C + +#define mmMME3_RTR_HBW_WR_RS_L_ARB 0xC01A0 + +#define mmMME3_RTR_LBW_RD_RQ_E_ARB 0xC0200 + +#define mmMME3_RTR_LBW_RD_RQ_W_ARB 0xC0204 + +#define mmMME3_RTR_LBW_RD_RQ_N_ARB 0xC0208 + +#define mmMME3_RTR_LBW_RD_RQ_S_ARB 0xC020C + +#define mmMME3_RTR_LBW_RD_RQ_L_ARB 0xC0210 + +#define mmMME3_RTR_LBW_E_ARB_MAX 0xC0220 + +#define mmMME3_RTR_LBW_W_ARB_MAX 0xC0224 + +#define mmMME3_RTR_LBW_N_ARB_MAX 0xC0228 + +#define mmMME3_RTR_LBW_S_ARB_MAX 0xC022C + +#define mmMME3_RTR_LBW_L_ARB_MAX 0xC0230 + +#define mmMME3_RTR_LBW_SRAM_MAX_CREDIT 0xC0240 + +#define mmMME3_RTR_LBW_RD_RS_E_ARB 0xC0250 + +#define mmMME3_RTR_LBW_RD_RS_W_ARB 0xC0254 + +#define mmMME3_RTR_LBW_RD_RS_N_ARB 0xC0258 + +#define mmMME3_RTR_LBW_RD_RS_S_ARB 0xC025C + +#define mmMME3_RTR_LBW_RD_RS_L_ARB 0xC0260 + +#define mmMME3_RTR_LBW_WR_RQ_E_ARB 0xC0270 + +#define mmMME3_RTR_LBW_WR_RQ_W_ARB 0xC0274 + +#define mmMME3_RTR_LBW_WR_RQ_N_ARB 0xC0278 + +#define mmMME3_RTR_LBW_WR_RQ_S_ARB 0xC027C + +#define mmMME3_RTR_LBW_WR_RQ_L_ARB 0xC0280 + +#define mmMME3_RTR_LBW_WR_RS_E_ARB 0xC0290 + +#define mmMME3_RTR_LBW_WR_RS_W_ARB 0xC0294 + +#define mmMME3_RTR_LBW_WR_RS_N_ARB 0xC0298 + +#define mmMME3_RTR_LBW_WR_RS_S_ARB 0xC029C + +#define mmMME3_RTR_LBW_WR_RS_L_ARB 0xC02A0 + +#define mmMME3_RTR_DBG_E_ARB 0xC0300 + +#define mmMME3_RTR_DBG_W_ARB 0xC0304 + +#define mmMME3_RTR_DBG_N_ARB 0xC0308 + +#define mmMME3_RTR_DBG_S_ARB 0xC030C + +#define mmMME3_RTR_DBG_L_ARB 0xC0310 + +#define mmMME3_RTR_DBG_E_ARB_MAX 0xC0320 + +#define mmMME3_RTR_DBG_W_ARB_MAX 0xC0324 + +#define mmMME3_RTR_DBG_N_ARB_MAX 0xC0328 + +#define mmMME3_RTR_DBG_S_ARB_MAX 0xC032C + +#define mmMME3_RTR_DBG_L_ARB_MAX 0xC0330 + +#define mmMME3_RTR_SPLIT_COEF_0 0xC0400 + +#define mmMME3_RTR_SPLIT_COEF_1 0xC0404 + +#define mmMME3_RTR_SPLIT_COEF_2 0xC0408 + +#define mmMME3_RTR_SPLIT_COEF_3 0xC040C + +#define mmMME3_RTR_SPLIT_COEF_4 0xC0410 + +#define mmMME3_RTR_SPLIT_COEF_5 0xC0414 + +#define mmMME3_RTR_SPLIT_COEF_6 0xC0418 + +#define mmMME3_RTR_SPLIT_COEF_7 0xC041C + +#define mmMME3_RTR_SPLIT_COEF_8 0xC0420 + +#define mmMME3_RTR_SPLIT_COEF_9 0xC0424 + +#define mmMME3_RTR_SPLIT_CFG 0xC0440 + +#define mmMME3_RTR_SPLIT_RD_SAT 0xC0444 + +#define mmMME3_RTR_SPLIT_RD_RST_TOKEN 0xC0448 + +#define mmMME3_RTR_SPLIT_RD_TIMEOUT_0 0xC044C + +#define mmMME3_RTR_SPLIT_RD_TIMEOUT_1 0xC0450 + +#define mmMME3_RTR_SPLIT_WR_SAT 0xC0454 + +#define mmMME3_RTR_WPLIT_WR_TST_TOLEN 0xC0458 + +#define mmMME3_RTR_SPLIT_WR_TIMEOUT_0 0xC045C + +#define mmMME3_RTR_SPLIT_WR_TIMEOUT_1 0xC0460 + +#define mmMME3_RTR_HBW_RANGE_HIT 0xC0470 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_0 0xC0480 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_1 0xC0484 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_2 0xC0488 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_3 0xC048C + +#define mmMME3_RTR_HBW_RANGE_MASK_L_4 0xC0490 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_5 0xC0494 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_6 0xC0498 + +#define mmMME3_RTR_HBW_RANGE_MASK_L_7 0xC049C + +#define mmMME3_RTR_HBW_RANGE_MASK_H_0 0xC04A0 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_1 0xC04A4 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_2 0xC04A8 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_3 0xC04AC + +#define mmMME3_RTR_HBW_RANGE_MASK_H_4 0xC04B0 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_5 0xC04B4 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_6 0xC04B8 + +#define mmMME3_RTR_HBW_RANGE_MASK_H_7 0xC04BC + +#define mmMME3_RTR_HBW_RANGE_BASE_L_0 0xC04C0 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_1 0xC04C4 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_2 0xC04C8 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_3 0xC04CC + +#define mmMME3_RTR_HBW_RANGE_BASE_L_4 0xC04D0 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_5 0xC04D4 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_6 0xC04D8 + +#define mmMME3_RTR_HBW_RANGE_BASE_L_7 0xC04DC + +#define mmMME3_RTR_HBW_RANGE_BASE_H_0 0xC04E0 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_1 0xC04E4 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_2 0xC04E8 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_3 0xC04EC + +#define mmMME3_RTR_HBW_RANGE_BASE_H_4 0xC04F0 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_5 0xC04F4 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_6 0xC04F8 + +#define mmMME3_RTR_HBW_RANGE_BASE_H_7 0xC04FC + +#define mmMME3_RTR_LBW_RANGE_HIT 0xC0500 + +#define mmMME3_RTR_LBW_RANGE_MASK_0 0xC0510 + +#define mmMME3_RTR_LBW_RANGE_MASK_1 0xC0514 + +#define mmMME3_RTR_LBW_RANGE_MASK_2 0xC0518 + +#define mmMME3_RTR_LBW_RANGE_MASK_3 0xC051C + +#define mmMME3_RTR_LBW_RANGE_MASK_4 0xC0520 + +#define mmMME3_RTR_LBW_RANGE_MASK_5 0xC0524 + +#define mmMME3_RTR_LBW_RANGE_MASK_6 0xC0528 + +#define mmMME3_RTR_LBW_RANGE_MASK_7 0xC052C + +#define mmMME3_RTR_LBW_RANGE_MASK_8 0xC0530 + +#define mmMME3_RTR_LBW_RANGE_MASK_9 0xC0534 + +#define mmMME3_RTR_LBW_RANGE_MASK_10 0xC0538 + +#define mmMME3_RTR_LBW_RANGE_MASK_11 0xC053C + +#define mmMME3_RTR_LBW_RANGE_MASK_12 0xC0540 + +#define mmMME3_RTR_LBW_RANGE_MASK_13 0xC0544 + +#define mmMME3_RTR_LBW_RANGE_MASK_14 0xC0548 + +#define mmMME3_RTR_LBW_RANGE_MASK_15 0xC054C + +#define mmMME3_RTR_LBW_RANGE_BASE_0 0xC0550 + +#define mmMME3_RTR_LBW_RANGE_BASE_1 0xC0554 + +#define mmMME3_RTR_LBW_RANGE_BASE_2 0xC0558 + +#define mmMME3_RTR_LBW_RANGE_BASE_3 0xC055C + +#define mmMME3_RTR_LBW_RANGE_BASE_4 0xC0560 + +#define mmMME3_RTR_LBW_RANGE_BASE_5 0xC0564 + +#define mmMME3_RTR_LBW_RANGE_BASE_6 0xC0568 + +#define mmMME3_RTR_LBW_RANGE_BASE_7 0xC056C + +#define mmMME3_RTR_LBW_RANGE_BASE_8 0xC0570 + +#define mmMME3_RTR_LBW_RANGE_BASE_9 0xC0574 + +#define mmMME3_RTR_LBW_RANGE_BASE_10 0xC0578 + +#define mmMME3_RTR_LBW_RANGE_BASE_11 0xC057C + +#define mmMME3_RTR_LBW_RANGE_BASE_12 0xC0580 + +#define mmMME3_RTR_LBW_RANGE_BASE_13 0xC0584 + +#define mmMME3_RTR_LBW_RANGE_BASE_14 0xC0588 + +#define mmMME3_RTR_LBW_RANGE_BASE_15 0xC058C + +#define mmMME3_RTR_RGLTR 0xC0590 + +#define mmMME3_RTR_RGLTR_WR_RESULT 0xC0594 + +#define mmMME3_RTR_RGLTR_RD_RESULT 0xC0598 + +#define mmMME3_RTR_SCRAMB_EN 0xC0600 + +#define mmMME3_RTR_NON_LIN_SCRAMB 0xC0604 + +#endif /* ASIC_REG_MME3_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h new file mode 100644 index 000000000..79b67bbc8 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME4_RTR_REGS_H_ +#define ASIC_REG_MME4_RTR_REGS_H_ + +/* + ***************************************** + * MME4_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100 + +#define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104 + +#define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108 + +#define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C + +#define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110 + +#define mmMME4_RTR_HBW_E_ARB_MAX 0x100120 + +#define mmMME4_RTR_HBW_W_ARB_MAX 0x100124 + +#define mmMME4_RTR_HBW_N_ARB_MAX 0x100128 + +#define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C + +#define mmMME4_RTR_HBW_L_ARB_MAX 0x100130 + +#define mmMME4_RTR_HBW_RD_RS_MAX_CREDIT 0x100140 + +#define mmMME4_RTR_HBW_WR_RQ_MAX_CREDIT 0x100144 + +#define mmMME4_RTR_HBW_RD_RQ_MAX_CREDIT 0x100148 + +#define mmMME4_RTR_HBW_RD_RS_E_ARB 0x100150 + +#define mmMME4_RTR_HBW_RD_RS_W_ARB 0x100154 + +#define mmMME4_RTR_HBW_RD_RS_N_ARB 0x100158 + +#define mmMME4_RTR_HBW_RD_RS_S_ARB 0x10015C + +#define mmMME4_RTR_HBW_RD_RS_L_ARB 0x100160 + +#define mmMME4_RTR_HBW_WR_RQ_E_ARB 0x100170 + +#define mmMME4_RTR_HBW_WR_RQ_W_ARB 0x100174 + +#define mmMME4_RTR_HBW_WR_RQ_N_ARB 0x100178 + +#define mmMME4_RTR_HBW_WR_RQ_S_ARB 0x10017C + +#define mmMME4_RTR_HBW_WR_RQ_L_ARB 0x100180 + +#define mmMME4_RTR_HBW_WR_RS_E_ARB 0x100190 + +#define mmMME4_RTR_HBW_WR_RS_W_ARB 0x100194 + +#define mmMME4_RTR_HBW_WR_RS_N_ARB 0x100198 + +#define mmMME4_RTR_HBW_WR_RS_S_ARB 0x10019C + +#define mmMME4_RTR_HBW_WR_RS_L_ARB 0x1001A0 + +#define mmMME4_RTR_LBW_RD_RQ_E_ARB 0x100200 + +#define mmMME4_RTR_LBW_RD_RQ_W_ARB 0x100204 + +#define mmMME4_RTR_LBW_RD_RQ_N_ARB 0x100208 + +#define mmMME4_RTR_LBW_RD_RQ_S_ARB 0x10020C + +#define mmMME4_RTR_LBW_RD_RQ_L_ARB 0x100210 + +#define mmMME4_RTR_LBW_E_ARB_MAX 0x100220 + +#define mmMME4_RTR_LBW_W_ARB_MAX 0x100224 + +#define mmMME4_RTR_LBW_N_ARB_MAX 0x100228 + +#define mmMME4_RTR_LBW_S_ARB_MAX 0x10022C + +#define mmMME4_RTR_LBW_L_ARB_MAX 0x100230 + +#define mmMME4_RTR_LBW_SRAM_MAX_CREDIT 0x100240 + +#define mmMME4_RTR_LBW_RD_RS_E_ARB 0x100250 + +#define mmMME4_RTR_LBW_RD_RS_W_ARB 0x100254 + +#define mmMME4_RTR_LBW_RD_RS_N_ARB 0x100258 + +#define mmMME4_RTR_LBW_RD_RS_S_ARB 0x10025C + +#define mmMME4_RTR_LBW_RD_RS_L_ARB 0x100260 + +#define mmMME4_RTR_LBW_WR_RQ_E_ARB 0x100270 + +#define mmMME4_RTR_LBW_WR_RQ_W_ARB 0x100274 + +#define mmMME4_RTR_LBW_WR_RQ_N_ARB 0x100278 + +#define mmMME4_RTR_LBW_WR_RQ_S_ARB 0x10027C + +#define mmMME4_RTR_LBW_WR_RQ_L_ARB 0x100280 + +#define mmMME4_RTR_LBW_WR_RS_E_ARB 0x100290 + +#define mmMME4_RTR_LBW_WR_RS_W_ARB 0x100294 + +#define mmMME4_RTR_LBW_WR_RS_N_ARB 0x100298 + +#define mmMME4_RTR_LBW_WR_RS_S_ARB 0x10029C + +#define mmMME4_RTR_LBW_WR_RS_L_ARB 0x1002A0 + +#define mmMME4_RTR_DBG_E_ARB 0x100300 + +#define mmMME4_RTR_DBG_W_ARB 0x100304 + +#define mmMME4_RTR_DBG_N_ARB 0x100308 + +#define mmMME4_RTR_DBG_S_ARB 0x10030C + +#define mmMME4_RTR_DBG_L_ARB 0x100310 + +#define mmMME4_RTR_DBG_E_ARB_MAX 0x100320 + +#define mmMME4_RTR_DBG_W_ARB_MAX 0x100324 + +#define mmMME4_RTR_DBG_N_ARB_MAX 0x100328 + +#define mmMME4_RTR_DBG_S_ARB_MAX 0x10032C + +#define mmMME4_RTR_DBG_L_ARB_MAX 0x100330 + +#define mmMME4_RTR_SPLIT_COEF_0 0x100400 + +#define mmMME4_RTR_SPLIT_COEF_1 0x100404 + +#define mmMME4_RTR_SPLIT_COEF_2 0x100408 + +#define mmMME4_RTR_SPLIT_COEF_3 0x10040C + +#define mmMME4_RTR_SPLIT_COEF_4 0x100410 + +#define mmMME4_RTR_SPLIT_COEF_5 0x100414 + +#define mmMME4_RTR_SPLIT_COEF_6 0x100418 + +#define mmMME4_RTR_SPLIT_COEF_7 0x10041C + +#define mmMME4_RTR_SPLIT_COEF_8 0x100420 + +#define mmMME4_RTR_SPLIT_COEF_9 0x100424 + +#define mmMME4_RTR_SPLIT_CFG 0x100440 + +#define mmMME4_RTR_SPLIT_RD_SAT 0x100444 + +#define mmMME4_RTR_SPLIT_RD_RST_TOKEN 0x100448 + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_0 0x10044C + +#define mmMME4_RTR_SPLIT_RD_TIMEOUT_1 0x100450 + +#define mmMME4_RTR_SPLIT_WR_SAT 0x100454 + +#define mmMME4_RTR_WPLIT_WR_TST_TOLEN 0x100458 + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_0 0x10045C + +#define mmMME4_RTR_SPLIT_WR_TIMEOUT_1 0x100460 + +#define mmMME4_RTR_HBW_RANGE_HIT 0x100470 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_0 0x100480 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_1 0x100484 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_2 0x100488 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_3 0x10048C + +#define mmMME4_RTR_HBW_RANGE_MASK_L_4 0x100490 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_5 0x100494 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_6 0x100498 + +#define mmMME4_RTR_HBW_RANGE_MASK_L_7 0x10049C + +#define mmMME4_RTR_HBW_RANGE_MASK_H_0 0x1004A0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_1 0x1004A4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_2 0x1004A8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_3 0x1004AC + +#define mmMME4_RTR_HBW_RANGE_MASK_H_4 0x1004B0 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_5 0x1004B4 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_6 0x1004B8 + +#define mmMME4_RTR_HBW_RANGE_MASK_H_7 0x1004BC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_0 0x1004C0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_1 0x1004C4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_2 0x1004C8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_3 0x1004CC + +#define mmMME4_RTR_HBW_RANGE_BASE_L_4 0x1004D0 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_5 0x1004D4 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_6 0x1004D8 + +#define mmMME4_RTR_HBW_RANGE_BASE_L_7 0x1004DC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_0 0x1004E0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_1 0x1004E4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_2 0x1004E8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_3 0x1004EC + +#define mmMME4_RTR_HBW_RANGE_BASE_H_4 0x1004F0 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_5 0x1004F4 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_6 0x1004F8 + +#define mmMME4_RTR_HBW_RANGE_BASE_H_7 0x1004FC + +#define mmMME4_RTR_LBW_RANGE_HIT 0x100500 + +#define mmMME4_RTR_LBW_RANGE_MASK_0 0x100510 + +#define mmMME4_RTR_LBW_RANGE_MASK_1 0x100514 + +#define mmMME4_RTR_LBW_RANGE_MASK_2 0x100518 + +#define mmMME4_RTR_LBW_RANGE_MASK_3 0x10051C + +#define mmMME4_RTR_LBW_RANGE_MASK_4 0x100520 + +#define mmMME4_RTR_LBW_RANGE_MASK_5 0x100524 + +#define mmMME4_RTR_LBW_RANGE_MASK_6 0x100528 + +#define mmMME4_RTR_LBW_RANGE_MASK_7 0x10052C + +#define mmMME4_RTR_LBW_RANGE_MASK_8 0x100530 + +#define mmMME4_RTR_LBW_RANGE_MASK_9 0x100534 + +#define mmMME4_RTR_LBW_RANGE_MASK_10 0x100538 + +#define mmMME4_RTR_LBW_RANGE_MASK_11 0x10053C + +#define mmMME4_RTR_LBW_RANGE_MASK_12 0x100540 + +#define mmMME4_RTR_LBW_RANGE_MASK_13 0x100544 + +#define mmMME4_RTR_LBW_RANGE_MASK_14 0x100548 + +#define mmMME4_RTR_LBW_RANGE_MASK_15 0x10054C + +#define mmMME4_RTR_LBW_RANGE_BASE_0 0x100550 + +#define mmMME4_RTR_LBW_RANGE_BASE_1 0x100554 + +#define mmMME4_RTR_LBW_RANGE_BASE_2 0x100558 + +#define mmMME4_RTR_LBW_RANGE_BASE_3 0x10055C + +#define mmMME4_RTR_LBW_RANGE_BASE_4 0x100560 + +#define mmMME4_RTR_LBW_RANGE_BASE_5 0x100564 + +#define mmMME4_RTR_LBW_RANGE_BASE_6 0x100568 + +#define mmMME4_RTR_LBW_RANGE_BASE_7 0x10056C + +#define mmMME4_RTR_LBW_RANGE_BASE_8 0x100570 + +#define mmMME4_RTR_LBW_RANGE_BASE_9 0x100574 + +#define mmMME4_RTR_LBW_RANGE_BASE_10 0x100578 + +#define mmMME4_RTR_LBW_RANGE_BASE_11 0x10057C + +#define mmMME4_RTR_LBW_RANGE_BASE_12 0x100580 + +#define mmMME4_RTR_LBW_RANGE_BASE_13 0x100584 + +#define mmMME4_RTR_LBW_RANGE_BASE_14 0x100588 + +#define mmMME4_RTR_LBW_RANGE_BASE_15 0x10058C + +#define mmMME4_RTR_RGLTR 0x100590 + +#define mmMME4_RTR_RGLTR_WR_RESULT 0x100594 + +#define mmMME4_RTR_RGLTR_RD_RESULT 0x100598 + +#define mmMME4_RTR_SCRAMB_EN 0x100600 + +#define mmMME4_RTR_NON_LIN_SCRAMB 0x100604 + +#endif /* ASIC_REG_MME4_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h new file mode 100644 index 000000000..0ac3c37ce --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME5_RTR_REGS_H_ +#define ASIC_REG_MME5_RTR_REGS_H_ + +/* + ***************************************** + * MME5_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME5_RTR_HBW_RD_RQ_E_ARB 0x140100 + +#define mmMME5_RTR_HBW_RD_RQ_W_ARB 0x140104 + +#define mmMME5_RTR_HBW_RD_RQ_N_ARB 0x140108 + +#define mmMME5_RTR_HBW_RD_RQ_S_ARB 0x14010C + +#define mmMME5_RTR_HBW_RD_RQ_L_ARB 0x140110 + +#define mmMME5_RTR_HBW_E_ARB_MAX 0x140120 + +#define mmMME5_RTR_HBW_W_ARB_MAX 0x140124 + +#define mmMME5_RTR_HBW_N_ARB_MAX 0x140128 + +#define mmMME5_RTR_HBW_S_ARB_MAX 0x14012C + +#define mmMME5_RTR_HBW_L_ARB_MAX 0x140130 + +#define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT 0x140140 + +#define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT 0x140144 + +#define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT 0x140148 + +#define mmMME5_RTR_HBW_RD_RS_E_ARB 0x140150 + +#define mmMME5_RTR_HBW_RD_RS_W_ARB 0x140154 + +#define mmMME5_RTR_HBW_RD_RS_N_ARB 0x140158 + +#define mmMME5_RTR_HBW_RD_RS_S_ARB 0x14015C + +#define mmMME5_RTR_HBW_RD_RS_L_ARB 0x140160 + +#define mmMME5_RTR_HBW_WR_RQ_E_ARB 0x140170 + +#define mmMME5_RTR_HBW_WR_RQ_W_ARB 0x140174 + +#define mmMME5_RTR_HBW_WR_RQ_N_ARB 0x140178 + +#define mmMME5_RTR_HBW_WR_RQ_S_ARB 0x14017C + +#define mmMME5_RTR_HBW_WR_RQ_L_ARB 0x140180 + +#define mmMME5_RTR_HBW_WR_RS_E_ARB 0x140190 + +#define mmMME5_RTR_HBW_WR_RS_W_ARB 0x140194 + +#define mmMME5_RTR_HBW_WR_RS_N_ARB 0x140198 + +#define mmMME5_RTR_HBW_WR_RS_S_ARB 0x14019C + +#define mmMME5_RTR_HBW_WR_RS_L_ARB 0x1401A0 + +#define mmMME5_RTR_LBW_RD_RQ_E_ARB 0x140200 + +#define mmMME5_RTR_LBW_RD_RQ_W_ARB 0x140204 + +#define mmMME5_RTR_LBW_RD_RQ_N_ARB 0x140208 + +#define mmMME5_RTR_LBW_RD_RQ_S_ARB 0x14020C + +#define mmMME5_RTR_LBW_RD_RQ_L_ARB 0x140210 + +#define mmMME5_RTR_LBW_E_ARB_MAX 0x140220 + +#define mmMME5_RTR_LBW_W_ARB_MAX 0x140224 + +#define mmMME5_RTR_LBW_N_ARB_MAX 0x140228 + +#define mmMME5_RTR_LBW_S_ARB_MAX 0x14022C + +#define mmMME5_RTR_LBW_L_ARB_MAX 0x140230 + +#define mmMME5_RTR_LBW_SRAM_MAX_CREDIT 0x140240 + +#define mmMME5_RTR_LBW_RD_RS_E_ARB 0x140250 + +#define mmMME5_RTR_LBW_RD_RS_W_ARB 0x140254 + +#define mmMME5_RTR_LBW_RD_RS_N_ARB 0x140258 + +#define mmMME5_RTR_LBW_RD_RS_S_ARB 0x14025C + +#define mmMME5_RTR_LBW_RD_RS_L_ARB 0x140260 + +#define mmMME5_RTR_LBW_WR_RQ_E_ARB 0x140270 + +#define mmMME5_RTR_LBW_WR_RQ_W_ARB 0x140274 + +#define mmMME5_RTR_LBW_WR_RQ_N_ARB 0x140278 + +#define mmMME5_RTR_LBW_WR_RQ_S_ARB 0x14027C + +#define mmMME5_RTR_LBW_WR_RQ_L_ARB 0x140280 + +#define mmMME5_RTR_LBW_WR_RS_E_ARB 0x140290 + +#define mmMME5_RTR_LBW_WR_RS_W_ARB 0x140294 + +#define mmMME5_RTR_LBW_WR_RS_N_ARB 0x140298 + +#define mmMME5_RTR_LBW_WR_RS_S_ARB 0x14029C + +#define mmMME5_RTR_LBW_WR_RS_L_ARB 0x1402A0 + +#define mmMME5_RTR_DBG_E_ARB 0x140300 + +#define mmMME5_RTR_DBG_W_ARB 0x140304 + +#define mmMME5_RTR_DBG_N_ARB 0x140308 + +#define mmMME5_RTR_DBG_S_ARB 0x14030C + +#define mmMME5_RTR_DBG_L_ARB 0x140310 + +#define mmMME5_RTR_DBG_E_ARB_MAX 0x140320 + +#define mmMME5_RTR_DBG_W_ARB_MAX 0x140324 + +#define mmMME5_RTR_DBG_N_ARB_MAX 0x140328 + +#define mmMME5_RTR_DBG_S_ARB_MAX 0x14032C + +#define mmMME5_RTR_DBG_L_ARB_MAX 0x140330 + +#define mmMME5_RTR_SPLIT_COEF_0 0x140400 + +#define mmMME5_RTR_SPLIT_COEF_1 0x140404 + +#define mmMME5_RTR_SPLIT_COEF_2 0x140408 + +#define mmMME5_RTR_SPLIT_COEF_3 0x14040C + +#define mmMME5_RTR_SPLIT_COEF_4 0x140410 + +#define mmMME5_RTR_SPLIT_COEF_5 0x140414 + +#define mmMME5_RTR_SPLIT_COEF_6 0x140418 + +#define mmMME5_RTR_SPLIT_COEF_7 0x14041C + +#define mmMME5_RTR_SPLIT_COEF_8 0x140420 + +#define mmMME5_RTR_SPLIT_COEF_9 0x140424 + +#define mmMME5_RTR_SPLIT_CFG 0x140440 + +#define mmMME5_RTR_SPLIT_RD_SAT 0x140444 + +#define mmMME5_RTR_SPLIT_RD_RST_TOKEN 0x140448 + +#define mmMME5_RTR_SPLIT_RD_TIMEOUT_0 0x14044C + +#define mmMME5_RTR_SPLIT_RD_TIMEOUT_1 0x140450 + +#define mmMME5_RTR_SPLIT_WR_SAT 0x140454 + +#define mmMME5_RTR_WPLIT_WR_TST_TOLEN 0x140458 + +#define mmMME5_RTR_SPLIT_WR_TIMEOUT_0 0x14045C + +#define mmMME5_RTR_SPLIT_WR_TIMEOUT_1 0x140460 + +#define mmMME5_RTR_HBW_RANGE_HIT 0x140470 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_0 0x140480 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_1 0x140484 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_2 0x140488 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_3 0x14048C + +#define mmMME5_RTR_HBW_RANGE_MASK_L_4 0x140490 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_5 0x140494 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_6 0x140498 + +#define mmMME5_RTR_HBW_RANGE_MASK_L_7 0x14049C + +#define mmMME5_RTR_HBW_RANGE_MASK_H_0 0x1404A0 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_1 0x1404A4 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_2 0x1404A8 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_3 0x1404AC + +#define mmMME5_RTR_HBW_RANGE_MASK_H_4 0x1404B0 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_5 0x1404B4 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_6 0x1404B8 + +#define mmMME5_RTR_HBW_RANGE_MASK_H_7 0x1404BC + +#define mmMME5_RTR_HBW_RANGE_BASE_L_0 0x1404C0 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_1 0x1404C4 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_2 0x1404C8 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_3 0x1404CC + +#define mmMME5_RTR_HBW_RANGE_BASE_L_4 0x1404D0 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_5 0x1404D4 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_6 0x1404D8 + +#define mmMME5_RTR_HBW_RANGE_BASE_L_7 0x1404DC + +#define mmMME5_RTR_HBW_RANGE_BASE_H_0 0x1404E0 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_1 0x1404E4 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_2 0x1404E8 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_3 0x1404EC + +#define mmMME5_RTR_HBW_RANGE_BASE_H_4 0x1404F0 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_5 0x1404F4 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_6 0x1404F8 + +#define mmMME5_RTR_HBW_RANGE_BASE_H_7 0x1404FC + +#define mmMME5_RTR_LBW_RANGE_HIT 0x140500 + +#define mmMME5_RTR_LBW_RANGE_MASK_0 0x140510 + +#define mmMME5_RTR_LBW_RANGE_MASK_1 0x140514 + +#define mmMME5_RTR_LBW_RANGE_MASK_2 0x140518 + +#define mmMME5_RTR_LBW_RANGE_MASK_3 0x14051C + +#define mmMME5_RTR_LBW_RANGE_MASK_4 0x140520 + +#define mmMME5_RTR_LBW_RANGE_MASK_5 0x140524 + +#define mmMME5_RTR_LBW_RANGE_MASK_6 0x140528 + +#define mmMME5_RTR_LBW_RANGE_MASK_7 0x14052C + +#define mmMME5_RTR_LBW_RANGE_MASK_8 0x140530 + +#define mmMME5_RTR_LBW_RANGE_MASK_9 0x140534 + +#define mmMME5_RTR_LBW_RANGE_MASK_10 0x140538 + +#define mmMME5_RTR_LBW_RANGE_MASK_11 0x14053C + +#define mmMME5_RTR_LBW_RANGE_MASK_12 0x140540 + +#define mmMME5_RTR_LBW_RANGE_MASK_13 0x140544 + +#define mmMME5_RTR_LBW_RANGE_MASK_14 0x140548 + +#define mmMME5_RTR_LBW_RANGE_MASK_15 0x14054C + +#define mmMME5_RTR_LBW_RANGE_BASE_0 0x140550 + +#define mmMME5_RTR_LBW_RANGE_BASE_1 0x140554 + +#define mmMME5_RTR_LBW_RANGE_BASE_2 0x140558 + +#define mmMME5_RTR_LBW_RANGE_BASE_3 0x14055C + +#define mmMME5_RTR_LBW_RANGE_BASE_4 0x140560 + +#define mmMME5_RTR_LBW_RANGE_BASE_5 0x140564 + +#define mmMME5_RTR_LBW_RANGE_BASE_6 0x140568 + +#define mmMME5_RTR_LBW_RANGE_BASE_7 0x14056C + +#define mmMME5_RTR_LBW_RANGE_BASE_8 0x140570 + +#define mmMME5_RTR_LBW_RANGE_BASE_9 0x140574 + +#define mmMME5_RTR_LBW_RANGE_BASE_10 0x140578 + +#define mmMME5_RTR_LBW_RANGE_BASE_11 0x14057C + +#define mmMME5_RTR_LBW_RANGE_BASE_12 0x140580 + +#define mmMME5_RTR_LBW_RANGE_BASE_13 0x140584 + +#define mmMME5_RTR_LBW_RANGE_BASE_14 0x140588 + +#define mmMME5_RTR_LBW_RANGE_BASE_15 0x14058C + +#define mmMME5_RTR_RGLTR 0x140590 + +#define mmMME5_RTR_RGLTR_WR_RESULT 0x140594 + +#define mmMME5_RTR_RGLTR_RD_RESULT 0x140598 + +#define mmMME5_RTR_SCRAMB_EN 0x140600 + +#define mmMME5_RTR_NON_LIN_SCRAMB 0x140604 + +#endif /* ASIC_REG_MME5_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h new file mode 100644 index 000000000..50c49cce7 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME6_RTR_REGS_H_ +#define ASIC_REG_MME6_RTR_REGS_H_ + +/* + ***************************************** + * MME6_RTR (Prototype: MME_RTR) + ***************************************** + */ + +#define mmMME6_RTR_HBW_RD_RQ_E_ARB 0x180100 + +#define mmMME6_RTR_HBW_RD_RQ_W_ARB 0x180104 + +#define mmMME6_RTR_HBW_RD_RQ_N_ARB 0x180108 + +#define mmMME6_RTR_HBW_RD_RQ_S_ARB 0x18010C + +#define mmMME6_RTR_HBW_RD_RQ_L_ARB 0x180110 + +#define mmMME6_RTR_HBW_E_ARB_MAX 0x180120 + +#define mmMME6_RTR_HBW_W_ARB_MAX 0x180124 + +#define mmMME6_RTR_HBW_N_ARB_MAX 0x180128 + +#define mmMME6_RTR_HBW_S_ARB_MAX 0x18012C + +#define mmMME6_RTR_HBW_L_ARB_MAX 0x180130 + +#define mmMME6_RTR_HBW_RD_RS_MAX_CREDIT 0x180140 + +#define mmMME6_RTR_HBW_WR_RQ_MAX_CREDIT 0x180144 + +#define mmMME6_RTR_HBW_RD_RQ_MAX_CREDIT 0x180148 + +#define mmMME6_RTR_HBW_RD_RS_E_ARB 0x180150 + +#define mmMME6_RTR_HBW_RD_RS_W_ARB 0x180154 + +#define mmMME6_RTR_HBW_RD_RS_N_ARB 0x180158 + +#define mmMME6_RTR_HBW_RD_RS_S_ARB 0x18015C + +#define mmMME6_RTR_HBW_RD_RS_L_ARB 0x180160 + +#define mmMME6_RTR_HBW_WR_RQ_E_ARB 0x180170 + +#define mmMME6_RTR_HBW_WR_RQ_W_ARB 0x180174 + +#define mmMME6_RTR_HBW_WR_RQ_N_ARB 0x180178 + +#define mmMME6_RTR_HBW_WR_RQ_S_ARB 0x18017C + +#define mmMME6_RTR_HBW_WR_RQ_L_ARB 0x180180 + +#define mmMME6_RTR_HBW_WR_RS_E_ARB 0x180190 + +#define mmMME6_RTR_HBW_WR_RS_W_ARB 0x180194 + +#define mmMME6_RTR_HBW_WR_RS_N_ARB 0x180198 + +#define mmMME6_RTR_HBW_WR_RS_S_ARB 0x18019C + +#define mmMME6_RTR_HBW_WR_RS_L_ARB 0x1801A0 + +#define mmMME6_RTR_LBW_RD_RQ_E_ARB 0x180200 + +#define mmMME6_RTR_LBW_RD_RQ_W_ARB 0x180204 + +#define mmMME6_RTR_LBW_RD_RQ_N_ARB 0x180208 + +#define mmMME6_RTR_LBW_RD_RQ_S_ARB 0x18020C + +#define mmMME6_RTR_LBW_RD_RQ_L_ARB 0x180210 + +#define mmMME6_RTR_LBW_E_ARB_MAX 0x180220 + +#define mmMME6_RTR_LBW_W_ARB_MAX 0x180224 + +#define mmMME6_RTR_LBW_N_ARB_MAX 0x180228 + +#define mmMME6_RTR_LBW_S_ARB_MAX 0x18022C + +#define mmMME6_RTR_LBW_L_ARB_MAX 0x180230 + +#define mmMME6_RTR_LBW_SRAM_MAX_CREDIT 0x180240 + +#define mmMME6_RTR_LBW_RD_RS_E_ARB 0x180250 + +#define mmMME6_RTR_LBW_RD_RS_W_ARB 0x180254 + +#define mmMME6_RTR_LBW_RD_RS_N_ARB 0x180258 + +#define mmMME6_RTR_LBW_RD_RS_S_ARB 0x18025C + +#define mmMME6_RTR_LBW_RD_RS_L_ARB 0x180260 + +#define mmMME6_RTR_LBW_WR_RQ_E_ARB 0x180270 + +#define mmMME6_RTR_LBW_WR_RQ_W_ARB 0x180274 + +#define mmMME6_RTR_LBW_WR_RQ_N_ARB 0x180278 + +#define mmMME6_RTR_LBW_WR_RQ_S_ARB 0x18027C + +#define mmMME6_RTR_LBW_WR_RQ_L_ARB 0x180280 + +#define mmMME6_RTR_LBW_WR_RS_E_ARB 0x180290 + +#define mmMME6_RTR_LBW_WR_RS_W_ARB 0x180294 + +#define mmMME6_RTR_LBW_WR_RS_N_ARB 0x180298 + +#define mmMME6_RTR_LBW_WR_RS_S_ARB 0x18029C + +#define mmMME6_RTR_LBW_WR_RS_L_ARB 0x1802A0 + +#define mmMME6_RTR_DBG_E_ARB 0x180300 + +#define mmMME6_RTR_DBG_W_ARB 0x180304 + +#define mmMME6_RTR_DBG_N_ARB 0x180308 + +#define mmMME6_RTR_DBG_S_ARB 0x18030C + +#define mmMME6_RTR_DBG_L_ARB 0x180310 + +#define mmMME6_RTR_DBG_E_ARB_MAX 0x180320 + +#define mmMME6_RTR_DBG_W_ARB_MAX 0x180324 + +#define mmMME6_RTR_DBG_N_ARB_MAX 0x180328 + +#define mmMME6_RTR_DBG_S_ARB_MAX 0x18032C + +#define mmMME6_RTR_DBG_L_ARB_MAX 0x180330 + +#define mmMME6_RTR_SPLIT_COEF_0 0x180400 + +#define mmMME6_RTR_SPLIT_COEF_1 0x180404 + +#define mmMME6_RTR_SPLIT_COEF_2 0x180408 + +#define mmMME6_RTR_SPLIT_COEF_3 0x18040C + +#define mmMME6_RTR_SPLIT_COEF_4 0x180410 + +#define mmMME6_RTR_SPLIT_COEF_5 0x180414 + +#define mmMME6_RTR_SPLIT_COEF_6 0x180418 + +#define mmMME6_RTR_SPLIT_COEF_7 0x18041C + +#define mmMME6_RTR_SPLIT_COEF_8 0x180420 + +#define mmMME6_RTR_SPLIT_COEF_9 0x180424 + +#define mmMME6_RTR_SPLIT_CFG 0x180440 + +#define mmMME6_RTR_SPLIT_RD_SAT 0x180444 + +#define mmMME6_RTR_SPLIT_RD_RST_TOKEN 0x180448 + +#define mmMME6_RTR_SPLIT_RD_TIMEOUT_0 0x18044C + +#define mmMME6_RTR_SPLIT_RD_TIMEOUT_1 0x180450 + +#define mmMME6_RTR_SPLIT_WR_SAT 0x180454 + +#define mmMME6_RTR_WPLIT_WR_TST_TOLEN 0x180458 + +#define mmMME6_RTR_SPLIT_WR_TIMEOUT_0 0x18045C + +#define mmMME6_RTR_SPLIT_WR_TIMEOUT_1 0x180460 + +#define mmMME6_RTR_HBW_RANGE_HIT 0x180470 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_0 0x180480 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_1 0x180484 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_2 0x180488 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_3 0x18048C + +#define mmMME6_RTR_HBW_RANGE_MASK_L_4 0x180490 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_5 0x180494 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_6 0x180498 + +#define mmMME6_RTR_HBW_RANGE_MASK_L_7 0x18049C + +#define mmMME6_RTR_HBW_RANGE_MASK_H_0 0x1804A0 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_1 0x1804A4 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_2 0x1804A8 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_3 0x1804AC + +#define mmMME6_RTR_HBW_RANGE_MASK_H_4 0x1804B0 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_5 0x1804B4 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_6 0x1804B8 + +#define mmMME6_RTR_HBW_RANGE_MASK_H_7 0x1804BC + +#define mmMME6_RTR_HBW_RANGE_BASE_L_0 0x1804C0 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_1 0x1804C4 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_2 0x1804C8 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_3 0x1804CC + +#define mmMME6_RTR_HBW_RANGE_BASE_L_4 0x1804D0 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_5 0x1804D4 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_6 0x1804D8 + +#define mmMME6_RTR_HBW_RANGE_BASE_L_7 0x1804DC + +#define mmMME6_RTR_HBW_RANGE_BASE_H_0 0x1804E0 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_1 0x1804E4 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_2 0x1804E8 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_3 0x1804EC + +#define mmMME6_RTR_HBW_RANGE_BASE_H_4 0x1804F0 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_5 0x1804F4 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_6 0x1804F8 + +#define mmMME6_RTR_HBW_RANGE_BASE_H_7 0x1804FC + +#define mmMME6_RTR_LBW_RANGE_HIT 0x180500 + +#define mmMME6_RTR_LBW_RANGE_MASK_0 0x180510 + +#define mmMME6_RTR_LBW_RANGE_MASK_1 0x180514 + +#define mmMME6_RTR_LBW_RANGE_MASK_2 0x180518 + +#define mmMME6_RTR_LBW_RANGE_MASK_3 0x18051C + +#define mmMME6_RTR_LBW_RANGE_MASK_4 0x180520 + +#define mmMME6_RTR_LBW_RANGE_MASK_5 0x180524 + +#define mmMME6_RTR_LBW_RANGE_MASK_6 0x180528 + +#define mmMME6_RTR_LBW_RANGE_MASK_7 0x18052C + +#define mmMME6_RTR_LBW_RANGE_MASK_8 0x180530 + +#define mmMME6_RTR_LBW_RANGE_MASK_9 0x180534 + +#define mmMME6_RTR_LBW_RANGE_MASK_10 0x180538 + +#define mmMME6_RTR_LBW_RANGE_MASK_11 0x18053C + +#define mmMME6_RTR_LBW_RANGE_MASK_12 0x180540 + +#define mmMME6_RTR_LBW_RANGE_MASK_13 0x180544 + +#define mmMME6_RTR_LBW_RANGE_MASK_14 0x180548 + +#define mmMME6_RTR_LBW_RANGE_MASK_15 0x18054C + +#define mmMME6_RTR_LBW_RANGE_BASE_0 0x180550 + +#define mmMME6_RTR_LBW_RANGE_BASE_1 0x180554 + +#define mmMME6_RTR_LBW_RANGE_BASE_2 0x180558 + +#define mmMME6_RTR_LBW_RANGE_BASE_3 0x18055C + +#define mmMME6_RTR_LBW_RANGE_BASE_4 0x180560 + +#define mmMME6_RTR_LBW_RANGE_BASE_5 0x180564 + +#define mmMME6_RTR_LBW_RANGE_BASE_6 0x180568 + +#define mmMME6_RTR_LBW_RANGE_BASE_7 0x18056C + +#define mmMME6_RTR_LBW_RANGE_BASE_8 0x180570 + +#define mmMME6_RTR_LBW_RANGE_BASE_9 0x180574 + +#define mmMME6_RTR_LBW_RANGE_BASE_10 0x180578 + +#define mmMME6_RTR_LBW_RANGE_BASE_11 0x18057C + +#define mmMME6_RTR_LBW_RANGE_BASE_12 0x180580 + +#define mmMME6_RTR_LBW_RANGE_BASE_13 0x180584 + +#define mmMME6_RTR_LBW_RANGE_BASE_14 0x180588 + +#define mmMME6_RTR_LBW_RANGE_BASE_15 0x18058C + +#define mmMME6_RTR_RGLTR 0x180590 + +#define mmMME6_RTR_RGLTR_WR_RESULT 0x180594 + +#define mmMME6_RTR_RGLTR_RD_RESULT 0x180598 + +#define mmMME6_RTR_SCRAMB_EN 0x180600 + +#define mmMME6_RTR_NON_LIN_SCRAMB 0x180604 + +#endif /* ASIC_REG_MME6_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h new file mode 100644 index 000000000..fe7d95bdc --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h @@ -0,0 +1,372 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_CMDQ_MASKS_H_ +#define ASIC_REG_MME_CMDQ_MASKS_H_ + +/* + ***************************************** + * MME_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +/* MME_CMDQ_GLBL_CFG0 */ +#define MME_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x1 +#define MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 1 +#define MME_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x2 +#define MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT 2 +#define MME_CMDQ_GLBL_CFG0_CP_EN_MASK 0x4 +#define MME_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 3 +#define MME_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* MME_CMDQ_GLBL_CFG1 */ +#define MME_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define MME_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 2 +#define MME_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x4 +#define MME_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define MME_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* MME_CMDQ_GLBL_PROT */ +#define MME_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 0 +#define MME_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x1 +#define MME_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 1 +#define MME_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x2 +#define MME_CMDQ_GLBL_PROT_CP_PROT_SHIFT 2 +#define MME_CMDQ_GLBL_PROT_CP_PROT_MASK 0x4 +#define MME_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 3 +#define MME_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x8 +#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* MME_CMDQ_GLBL_ERR_CFG */ +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* MME_CMDQ_GLBL_ERR_ADDR_LO */ +#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_ERR_ADDR_HI */ +#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_ERR_WDATA */ +#define MME_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_GLBL_SECURE_PROPS */ +#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_CMDQ_GLBL_NON_SECURE_PROPS */ +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_CMDQ_GLBL_STS0 */ +#define MME_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define MME_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define MME_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2 +#define MME_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4 +#define MME_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define MME_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* MME_CMDQ_GLBL_STS1 */ +#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* MME_CMDQ_CQ_CFG0 */ +#define MME_CMDQ_CQ_CFG0_RESERVED_SHIFT 0 +#define MME_CMDQ_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME_CMDQ_CQ_CFG1 */ +#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_ARUSER */ +#define MME_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_CMDQ_CQ_ARUSER_WORD_SHIFT 1 +#define MME_CMDQ_CQ_ARUSER_WORD_MASK 0x2 + +/* MME_CMDQ_CQ_PTR_LO */ +#define MME_CMDQ_CQ_PTR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_PTR_HI */ +#define MME_CMDQ_CQ_PTR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_TSIZE */ +#define MME_CMDQ_CQ_TSIZE_VAL_SHIFT 0 +#define MME_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_CTL */ +#define MME_CMDQ_CQ_CTL_RPT_SHIFT 0 +#define MME_CMDQ_CQ_CTL_RPT_MASK 0xFFFF +#define MME_CMDQ_CQ_CTL_CTL_SHIFT 16 +#define MME_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_PTR_LO_STS */ +#define MME_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_PTR_HI_STS */ +#define MME_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_TSIZE_STS */ +#define MME_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_CTL_STS */ +#define MME_CMDQ_CQ_CTL_STS_RPT_SHIFT 0 +#define MME_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME_CMDQ_CQ_CTL_STS_CTL_SHIFT 16 +#define MME_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_STS0 */ +#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_CMDQ_CQ_STS1 */ +#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME_CMDQ_CQ_RD_RATE_LIM_EN */ +#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_CMDQ_CQ_RD_RATE_LIM_SAT */ +#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_CMDQ_CQ_RD_RATE_LIM_TOUT */ +#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_CMDQ_CQ_IFIFO_CNT */ +#define MME_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME_CMDQ_CP_MSG_BASE0_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE0_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE1_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE1_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE2_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE2_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE3_ADDR_LO */ +#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_MSG_BASE3_ADDR_HI */ +#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_TSIZE_OFFSET */ +#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */ +#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_LDMA_COMMIT_OFFSET */ +#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_FENCE0_RDATA */ +#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE1_RDATA */ +#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE2_RDATA */ +#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE3_RDATA */ +#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME_CMDQ_CP_FENCE0_CNT */ +#define MME_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE1_CNT */ +#define MME_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE2_CNT */ +#define MME_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_FENCE3_CNT */ +#define MME_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* MME_CMDQ_CP_STS */ +#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME_CMDQ_CP_STS_ERDY_SHIFT 16 +#define MME_CMDQ_CP_STS_ERDY_MASK 0x10000 +#define MME_CMDQ_CP_STS_RRDY_SHIFT 17 +#define MME_CMDQ_CP_STS_RRDY_MASK 0x20000 +#define MME_CMDQ_CP_STS_MRDY_SHIFT 18 +#define MME_CMDQ_CP_STS_MRDY_MASK 0x40000 +#define MME_CMDQ_CP_STS_SW_STOP_SHIFT 19 +#define MME_CMDQ_CP_STS_SW_STOP_MASK 0x80000 +#define MME_CMDQ_CP_STS_FENCE_ID_SHIFT 20 +#define MME_CMDQ_CP_STS_FENCE_ID_MASK 0x300000 +#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME_CMDQ_CP_CURRENT_INST_LO */ +#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_CURRENT_INST_HI */ +#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CP_BARRIER_CFG */ +#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* MME_CMDQ_CP_DBG_0 */ +#define MME_CMDQ_CP_DBG_0_VAL_SHIFT 0 +#define MME_CMDQ_CP_DBG_0_VAL_MASK 0xFF + +/* MME_CMDQ_CQ_BUF_ADDR */ +#define MME_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_CMDQ_CQ_BUF_RDATA */ +#define MME_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MME_CMDQ_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h new file mode 100644 index 000000000..5f8b85d2b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_CMDQ_REGS_H_ +#define ASIC_REG_MME_CMDQ_REGS_H_ + +/* + ***************************************** + * MME_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmMME_CMDQ_GLBL_CFG0 0xD9000 + +#define mmMME_CMDQ_GLBL_CFG1 0xD9004 + +#define mmMME_CMDQ_GLBL_PROT 0xD9008 + +#define mmMME_CMDQ_GLBL_ERR_CFG 0xD900C + +#define mmMME_CMDQ_GLBL_ERR_ADDR_LO 0xD9010 + +#define mmMME_CMDQ_GLBL_ERR_ADDR_HI 0xD9014 + +#define mmMME_CMDQ_GLBL_ERR_WDATA 0xD9018 + +#define mmMME_CMDQ_GLBL_SECURE_PROPS 0xD901C + +#define mmMME_CMDQ_GLBL_NON_SECURE_PROPS 0xD9020 + +#define mmMME_CMDQ_GLBL_STS0 0xD9024 + +#define mmMME_CMDQ_GLBL_STS1 0xD9028 + +#define mmMME_CMDQ_CQ_CFG0 0xD90B0 + +#define mmMME_CMDQ_CQ_CFG1 0xD90B4 + +#define mmMME_CMDQ_CQ_ARUSER 0xD90B8 + +#define mmMME_CMDQ_CQ_PTR_LO 0xD90C0 + +#define mmMME_CMDQ_CQ_PTR_HI 0xD90C4 + +#define mmMME_CMDQ_CQ_TSIZE 0xD90C8 + +#define mmMME_CMDQ_CQ_CTL 0xD90CC + +#define mmMME_CMDQ_CQ_PTR_LO_STS 0xD90D4 + +#define mmMME_CMDQ_CQ_PTR_HI_STS 0xD90D8 + +#define mmMME_CMDQ_CQ_TSIZE_STS 0xD90DC + +#define mmMME_CMDQ_CQ_CTL_STS 0xD90E0 + +#define mmMME_CMDQ_CQ_STS0 0xD90E4 + +#define mmMME_CMDQ_CQ_STS1 0xD90E8 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_EN 0xD90F0 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xD90F4 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT 0xD90F8 + +#define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT 0xD90FC + +#define mmMME_CMDQ_CQ_IFIFO_CNT 0xD9108 + +#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO 0xD9120 + +#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI 0xD9124 + +#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO 0xD9128 + +#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI 0xD912C + +#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO 0xD9130 + +#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI 0xD9134 + +#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO 0xD9138 + +#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI 0xD913C + +#define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET 0xD9140 + +#define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xD9144 + +#define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xD9148 + +#define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xD914C + +#define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xD9150 + +#define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET 0xD9154 + +#define mmMME_CMDQ_CP_FENCE0_RDATA 0xD9158 + +#define mmMME_CMDQ_CP_FENCE1_RDATA 0xD915C + +#define mmMME_CMDQ_CP_FENCE2_RDATA 0xD9160 + +#define mmMME_CMDQ_CP_FENCE3_RDATA 0xD9164 + +#define mmMME_CMDQ_CP_FENCE0_CNT 0xD9168 + +#define mmMME_CMDQ_CP_FENCE1_CNT 0xD916C + +#define mmMME_CMDQ_CP_FENCE2_CNT 0xD9170 + +#define mmMME_CMDQ_CP_FENCE3_CNT 0xD9174 + +#define mmMME_CMDQ_CP_STS 0xD9178 + +#define mmMME_CMDQ_CP_CURRENT_INST_LO 0xD917C + +#define mmMME_CMDQ_CP_CURRENT_INST_HI 0xD9180 + +#define mmMME_CMDQ_CP_BARRIER_CFG 0xD9184 + +#define mmMME_CMDQ_CP_DBG_0 0xD9188 + +#define mmMME_CMDQ_CQ_BUF_ADDR 0xD9308 + +#define mmMME_CMDQ_CQ_BUF_RDATA 0xD930C + +#endif /* ASIC_REG_MME_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h new file mode 100644 index 000000000..1882c413c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h @@ -0,0 +1,1536 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_MASKS_H_ +#define ASIC_REG_MME_MASKS_H_ + +/* + ***************************************** + * MME (Prototype: MME) + ***************************************** + */ + +/* MME_ARCH_STATUS */ +#define MME_ARCH_STATUS_A_SHIFT 0 +#define MME_ARCH_STATUS_A_MASK 0x1 +#define MME_ARCH_STATUS_B_SHIFT 1 +#define MME_ARCH_STATUS_B_MASK 0x2 +#define MME_ARCH_STATUS_CIN_SHIFT 2 +#define MME_ARCH_STATUS_CIN_MASK 0x4 +#define MME_ARCH_STATUS_COUT_SHIFT 3 +#define MME_ARCH_STATUS_COUT_MASK 0x8 +#define MME_ARCH_STATUS_TE_SHIFT 4 +#define MME_ARCH_STATUS_TE_MASK 0x10 +#define MME_ARCH_STATUS_LD_SHIFT 5 +#define MME_ARCH_STATUS_LD_MASK 0x20 +#define MME_ARCH_STATUS_ST_SHIFT 6 +#define MME_ARCH_STATUS_ST_MASK 0x40 +#define MME_ARCH_STATUS_SB_A_EMPTY_SHIFT 7 +#define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 +#define MME_ARCH_STATUS_SB_B_EMPTY_SHIFT 8 +#define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 +#define MME_ARCH_STATUS_SB_CIN_EMPTY_SHIFT 9 +#define MME_ARCH_STATUS_SB_CIN_EMPTY_MASK 0x200 +#define MME_ARCH_STATUS_SB_COUT_EMPTY_SHIFT 10 +#define MME_ARCH_STATUS_SB_COUT_EMPTY_MASK 0x400 +#define MME_ARCH_STATUS_SM_IDLE_SHIFT 11 +#define MME_ARCH_STATUS_SM_IDLE_MASK 0x800 +#define MME_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 12 +#define MME_ARCH_STATUS_WBC_AXI_IDLE_MASK 0xF000 +#define MME_ARCH_STATUS_SBC_AXI_IDLE_SHIFT 16 +#define MME_ARCH_STATUS_SBC_AXI_IDLE_MASK 0x30000 +#define MME_ARCH_STATUS_SBB_AXI_IDLE_SHIFT 18 +#define MME_ARCH_STATUS_SBB_AXI_IDLE_MASK 0xC0000 +#define MME_ARCH_STATUS_SBA_AXI_IDLE_SHIFT 20 +#define MME_ARCH_STATUS_SBA_AXI_IDLE_MASK 0x300000 +#define MME_ARCH_STATUS_FREE_ACCUMS_SHIFT 22 +#define MME_ARCH_STATUS_FREE_ACCUMS_MASK 0x1C00000 + +/* MME_ARCH_A_BASE_ADDR_HIGH */ +#define MME_ARCH_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_BASE_ADDR_HIGH */ +#define MME_ARCH_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_BASE_ADDR_HIGH */ +#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_COUT_BASE_ADDR_HIGH */ +#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_BIAS_BASE_ADDR_HIGH */ +#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_BASE_ADDR_LOW */ +#define MME_ARCH_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_BASE_ADDR_LOW */ +#define MME_ARCH_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_BASE_ADDR_LOW */ +#define MME_ARCH_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_COUT_BASE_ADDR_LOW */ +#define MME_ARCH_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_BIAS_BASE_ADDR_LOW */ +#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_ARCH_HEADER */ +#define MME_ARCH_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_ARCH_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_ARCH_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_ARCH_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_ARCH_HEADER_TRANS_A_SHIFT 6 +#define MME_ARCH_HEADER_TRANS_A_MASK 0x40 +#define MME_ARCH_HEADER_LOWER_A_SHIFT 7 +#define MME_ARCH_HEADER_LOWER_A_MASK 0x80 +#define MME_ARCH_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_ARCH_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_ARCH_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_ARCH_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_ARCH_HEADER_LOAD_CIN_SHIFT 13 +#define MME_ARCH_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_ARCH_HEADER_STORE_OUT_SHIFT 15 +#define MME_ARCH_HEADER_STORE_OUT_MASK 0x8000 +#define MME_ARCH_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_ARCH_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_ARCH_HEADER_ADVANCE_A_SHIFT 17 +#define MME_ARCH_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_ARCH_HEADER_ADVANCE_B_SHIFT 18 +#define MME_ARCH_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_ARCH_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_ARCH_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_ARCH_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_ARCH_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_ARCH_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_ARCH_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_ARCH_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_ARCH_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_ARCH_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_ARCH_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_ARCH_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_ARCH_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_ARCH_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_ARCH_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_ARCH_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_ARCH_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_ARCH_KERNEL_SIZE_MINUS_1 */ +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_ARCH_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_ARCH_ASSOCIATED_DIMS */ +#define MME_ARCH_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_ARCH_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_ARCH_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_ARCH_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_ARCH_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_ARCH_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_ARCH_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_ARCH_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_ARCH_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_ARCH_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_ARCH_COUT_SCALE */ +#define MME_ARCH_COUT_SCALE_V_SHIFT 0 +#define MME_ARCH_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_CIN_SCALE */ +#define MME_ARCH_CIN_SCALE_V_SHIFT 0 +#define MME_ARCH_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_GEMMLOWP_ZP */ +#define MME_ARCH_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_ARCH_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_ARCH_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_ARCH_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_ARCH_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_ARCH_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_ARCH_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_ARCH_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_ARCH_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_ARCH_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_ARCH_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_ARCH_GEMMLOWP_EXPONENT */ +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_ARCH_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_ARCH_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_ARCH_A_ROI_BASE_OFFSET */ +#define MME_ARCH_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_VALID_ELEMENTS */ +#define MME_ARCH_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_LOOP_STRIDE */ +#define MME_ARCH_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_ROI_SIZE */ +#define MME_ARCH_A_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_START_OFFSET */ +#define MME_ARCH_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_STRIDE */ +#define MME_ARCH_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_ROI_BASE_OFFSET */ +#define MME_ARCH_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_VALID_ELEMENTS */ +#define MME_ARCH_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_LOOP_STRIDE */ +#define MME_ARCH_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_ROI_SIZE */ +#define MME_ARCH_B_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_START_OFFSET */ +#define MME_ARCH_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_STRIDE */ +#define MME_ARCH_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_ROI_BASE_OFFSET */ +#define MME_ARCH_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_ARCH_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_VALID_ELEMENTS */ +#define MME_ARCH_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_ARCH_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_LOOP_STRIDE */ +#define MME_ARCH_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_ARCH_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_ROI_SIZE */ +#define MME_ARCH_C_ROI_SIZE_V_SHIFT 0 +#define MME_ARCH_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_START_OFFSET */ +#define MME_ARCH_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_STRIDE */ +#define MME_ARCH_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_ARCH_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_ARCH_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_ARCH_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_SYNC_OBJECT_MESSAGE */ +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_ARCH_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_ARCH_E_PADDING_VALUE_A */ +#define MME_ARCH_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_ARCH_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_ARCH_E_NUM_ITERATION_MINUS_1 */ +#define MME_ARCH_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_ARCH_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_ARCH_E_BUBBLES_PER_SPLIT */ +#define MME_ARCH_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_ARCH_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_ARCH_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_CMD */ +#define MME_CMD_EXECUTE_SHIFT 0 +#define MME_CMD_EXECUTE_MASK 0x1 + +/* MME_DUMMY */ +#define MME_DUMMY_V_SHIFT 0 +#define MME_DUMMY_V_MASK 0xFFFFFFFF + +/* MME_RESET */ +#define MME_RESET_V_SHIFT 0 +#define MME_RESET_V_MASK 0x1 + +/* MME_STALL */ +#define MME_STALL_V_SHIFT 0 +#define MME_STALL_V_MASK 0xFFFFFFFF + +/* MME_SM_BASE_ADDRESS_LOW */ +#define MME_SM_BASE_ADDRESS_LOW_V_SHIFT 0 +#define MME_SM_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* MME_SM_BASE_ADDRESS_HIGH */ +#define MME_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define MME_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_ADD */ +#define MME_DBGMEM_ADD_V_SHIFT 0 +#define MME_DBGMEM_ADD_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_DATA_WR */ +#define MME_DBGMEM_DATA_WR_V_SHIFT 0 +#define MME_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_DATA_RD */ +#define MME_DBGMEM_DATA_RD_V_SHIFT 0 +#define MME_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF + +/* MME_DBGMEM_CTRL */ +#define MME_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define MME_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* MME_DBGMEM_RC */ +#define MME_DBGMEM_RC_VALID_SHIFT 0 +#define MME_DBGMEM_RC_VALID_MASK 0x1 +#define MME_DBGMEM_RC_FULL_SHIFT 1 +#define MME_DBGMEM_RC_FULL_MASK 0x2 + +/* MME_LOG_SHADOW */ +#define MME_LOG_SHADOW_MASK_0_SHIFT 0 +#define MME_LOG_SHADOW_MASK_0_MASK 0x7F +#define MME_LOG_SHADOW_MASK_1_SHIFT 8 +#define MME_LOG_SHADOW_MASK_1_MASK 0x7F00 +#define MME_LOG_SHADOW_MASK_2_SHIFT 16 +#define MME_LOG_SHADOW_MASK_2_MASK 0x7F0000 +#define MME_LOG_SHADOW_MASK_3_SHIFT 24 +#define MME_LOG_SHADOW_MASK_3_MASK 0x7F000000 + +/* MME_STORE_MAX_CREDIT */ +#define MME_STORE_MAX_CREDIT_V_SHIFT 0 +#define MME_STORE_MAX_CREDIT_V_MASK 0x3F + +/* MME_AGU */ +#define MME_AGU_SBA_MAX_CREDIT_SHIFT 0 +#define MME_AGU_SBA_MAX_CREDIT_MASK 0x1F +#define MME_AGU_SBB_MAX_CREDIT_SHIFT 8 +#define MME_AGU_SBB_MAX_CREDIT_MASK 0x1F00 +#define MME_AGU_SBC_MAX_CREDIT_SHIFT 16 +#define MME_AGU_SBC_MAX_CREDIT_MASK 0x1F0000 +#define MME_AGU_WBC_MAX_CREDIT_SHIFT 24 +#define MME_AGU_WBC_MAX_CREDIT_MASK 0x3F000000 + +/* MME_SBA */ +#define MME_SBA_MAX_SIZE_SHIFT 0 +#define MME_SBA_MAX_SIZE_MASK 0x3FF +#define MME_SBA_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBA_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_SBB */ +#define MME_SBB_MAX_SIZE_SHIFT 0 +#define MME_SBB_MAX_SIZE_MASK 0x3FF +#define MME_SBB_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBB_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_SBC */ +#define MME_SBC_MAX_SIZE_SHIFT 0 +#define MME_SBC_MAX_SIZE_MASK 0x3FF +#define MME_SBC_EU_MAX_CREDIT_SHIFT 16 +#define MME_SBC_EU_MAX_CREDIT_MASK 0x1F0000 + +/* MME_WBC */ +#define MME_WBC_MAX_OUTSTANDING_SHIFT 0 +#define MME_WBC_MAX_OUTSTANDING_MASK 0xFFF +#define MME_WBC_DISABLE_FAST_END_PE_SHIFT 12 +#define MME_WBC_DISABLE_FAST_END_PE_MASK 0x1000 +#define MME_WBC_LD_INSERT_BUBBLE_DIS_SHIFT 13 +#define MME_WBC_LD_INSERT_BUBBLE_DIS_MASK 0x2000 + +/* MME_SBA_CONTROL_DATA */ +#define MME_SBA_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBA_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBA_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBA_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_SBB_CONTROL_DATA */ +#define MME_SBB_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBB_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBB_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBB_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_SBC_CONTROL_DATA */ +#define MME_SBC_CONTROL_DATA_ASID_SHIFT 0 +#define MME_SBC_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_SBC_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_SBC_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_WBC_CONTROL_DATA */ +#define MME_WBC_CONTROL_DATA_ASID_SHIFT 0 +#define MME_WBC_CONTROL_DATA_ASID_MASK 0x3FF +#define MME_WBC_CONTROL_DATA_MMBP_SHIFT 10 +#define MME_WBC_CONTROL_DATA_MMBP_MASK 0x400 + +/* MME_TE */ +#define MME_TE_MAX_CREDIT_SHIFT 0 +#define MME_TE_MAX_CREDIT_MASK 0x1F +#define MME_TE_DESC_MAX_CREDIT_SHIFT 8 +#define MME_TE_DESC_MAX_CREDIT_MASK 0x1F00 + +/* MME_TE2DEC */ +#define MME_TE2DEC_MAX_CREDIT_SHIFT 0 +#define MME_TE2DEC_MAX_CREDIT_MASK 0x1F + +/* MME_REI_STATUS */ +#define MME_REI_STATUS_V_SHIFT 0 +#define MME_REI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_REI_MASK */ +#define MME_REI_MASK_V_SHIFT 0 +#define MME_REI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SEI_STATUS */ +#define MME_SEI_STATUS_V_SHIFT 0 +#define MME_SEI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_SEI_MASK */ +#define MME_SEI_MASK_V_SHIFT 0 +#define MME_SEI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SPI_STATUS */ +#define MME_SPI_STATUS_V_SHIFT 0 +#define MME_SPI_STATUS_V_MASK 0xFFFFFFFF + +/* MME_SPI_MASK */ +#define MME_SPI_MASK_V_SHIFT 0 +#define MME_SPI_MASK_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_STATUS */ +#define MME_SHADOW_0_STATUS_A_SHIFT 0 +#define MME_SHADOW_0_STATUS_A_MASK 0x1 +#define MME_SHADOW_0_STATUS_B_SHIFT 1 +#define MME_SHADOW_0_STATUS_B_MASK 0x2 +#define MME_SHADOW_0_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_0_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_0_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_0_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_0_STATUS_TE_SHIFT 4 +#define MME_SHADOW_0_STATUS_TE_MASK 0x10 +#define MME_SHADOW_0_STATUS_LD_SHIFT 5 +#define MME_SHADOW_0_STATUS_LD_MASK 0x20 +#define MME_SHADOW_0_STATUS_ST_SHIFT 6 +#define MME_SHADOW_0_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_0_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_0_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_0_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_BASE_ADDR_LOW */ +#define MME_SHADOW_0_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_BASE_ADDR_LOW */ +#define MME_SHADOW_0_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_0_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_0_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_0_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_0_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_HEADER */ +#define MME_SHADOW_0_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_0_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_0_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_0_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_0_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_0_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_0_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_0_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_0_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_0_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_0_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_0_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_0_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_0_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_0_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_0_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_0_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_0_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_0_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_0_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_0_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_0_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_0_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_0_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_0_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_0_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_0_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_0_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_0_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_0_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_0_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_0_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_0_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_0_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_0_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_0_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_0_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_0_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_0_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_0_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_0_ASSOCIATED_DIMS */ +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_0_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_0_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_0_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_0_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_0_COUT_SCALE */ +#define MME_SHADOW_0_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_0_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_CIN_SCALE */ +#define MME_SHADOW_0_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_0_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_GEMMLOWP_ZP */ +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_0_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_0_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_0_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_0_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_0_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_0_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_0_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_0_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_0_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_VALID_ELEMENTS */ +#define MME_SHADOW_0_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_LOOP_STRIDE */ +#define MME_SHADOW_0_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_ROI_SIZE */ +#define MME_SHADOW_0_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_STRIDE */ +#define MME_SHADOW_0_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_VALID_ELEMENTS */ +#define MME_SHADOW_0_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_LOOP_STRIDE */ +#define MME_SHADOW_0_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_ROI_SIZE */ +#define MME_SHADOW_0_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_STRIDE */ +#define MME_SHADOW_0_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_0_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_VALID_ELEMENTS */ +#define MME_SHADOW_0_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_0_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_LOOP_STRIDE */ +#define MME_SHADOW_0_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_ROI_SIZE */ +#define MME_SHADOW_0_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_0_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_0_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_STRIDE */ +#define MME_SHADOW_0_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_0_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_0_E_PADDING_VALUE_A */ +#define MME_SHADOW_0_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_0_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_0_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_0_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_0_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_0_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_0_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_1_STATUS */ +#define MME_SHADOW_1_STATUS_A_SHIFT 0 +#define MME_SHADOW_1_STATUS_A_MASK 0x1 +#define MME_SHADOW_1_STATUS_B_SHIFT 1 +#define MME_SHADOW_1_STATUS_B_MASK 0x2 +#define MME_SHADOW_1_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_1_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_1_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_1_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_1_STATUS_TE_SHIFT 4 +#define MME_SHADOW_1_STATUS_TE_MASK 0x10 +#define MME_SHADOW_1_STATUS_LD_SHIFT 5 +#define MME_SHADOW_1_STATUS_LD_MASK 0x20 +#define MME_SHADOW_1_STATUS_ST_SHIFT 6 +#define MME_SHADOW_1_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_1_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_1_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_1_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_BASE_ADDR_LOW */ +#define MME_SHADOW_1_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_BASE_ADDR_LOW */ +#define MME_SHADOW_1_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_1_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_1_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_1_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_1_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_HEADER */ +#define MME_SHADOW_1_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_1_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_1_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_1_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_1_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_1_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_1_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_1_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_1_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_1_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_1_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_1_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_1_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_1_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_1_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_1_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_1_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_1_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_1_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_1_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_1_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_1_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_1_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_1_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_1_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_1_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_1_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_1_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_1_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_1_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_1_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_1_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_1_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_1_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_1_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_1_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_1_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_1_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_1_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_1_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_1_ASSOCIATED_DIMS */ +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_1_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_1_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_1_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_1_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_1_COUT_SCALE */ +#define MME_SHADOW_1_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_1_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_CIN_SCALE */ +#define MME_SHADOW_1_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_1_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_GEMMLOWP_ZP */ +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_1_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_1_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_1_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_1_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_1_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_1_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_1_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_1_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_1_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_VALID_ELEMENTS */ +#define MME_SHADOW_1_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_LOOP_STRIDE */ +#define MME_SHADOW_1_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_ROI_SIZE */ +#define MME_SHADOW_1_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_STRIDE */ +#define MME_SHADOW_1_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_VALID_ELEMENTS */ +#define MME_SHADOW_1_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_LOOP_STRIDE */ +#define MME_SHADOW_1_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_ROI_SIZE */ +#define MME_SHADOW_1_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_STRIDE */ +#define MME_SHADOW_1_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_1_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_VALID_ELEMENTS */ +#define MME_SHADOW_1_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_1_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_LOOP_STRIDE */ +#define MME_SHADOW_1_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_ROI_SIZE */ +#define MME_SHADOW_1_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_1_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_1_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_STRIDE */ +#define MME_SHADOW_1_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_1_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_1_E_PADDING_VALUE_A */ +#define MME_SHADOW_1_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_1_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_1_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_1_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_1_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_1_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_1_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_2_STATUS */ +#define MME_SHADOW_2_STATUS_A_SHIFT 0 +#define MME_SHADOW_2_STATUS_A_MASK 0x1 +#define MME_SHADOW_2_STATUS_B_SHIFT 1 +#define MME_SHADOW_2_STATUS_B_MASK 0x2 +#define MME_SHADOW_2_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_2_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_2_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_2_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_2_STATUS_TE_SHIFT 4 +#define MME_SHADOW_2_STATUS_TE_MASK 0x10 +#define MME_SHADOW_2_STATUS_LD_SHIFT 5 +#define MME_SHADOW_2_STATUS_LD_MASK 0x20 +#define MME_SHADOW_2_STATUS_ST_SHIFT 6 +#define MME_SHADOW_2_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_2_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_2_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_2_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_BASE_ADDR_LOW */ +#define MME_SHADOW_2_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_BASE_ADDR_LOW */ +#define MME_SHADOW_2_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_2_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_2_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_2_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_2_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_HEADER */ +#define MME_SHADOW_2_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_2_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_2_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_2_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_2_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_2_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_2_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_2_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_2_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_2_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_2_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_2_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_2_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_2_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_2_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_2_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_2_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_2_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_2_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_2_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_2_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_2_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_2_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_2_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_2_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_2_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_2_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_2_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_2_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_2_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_2_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_2_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_2_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_2_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_2_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_2_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_2_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_2_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_2_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_2_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_2_ASSOCIATED_DIMS */ +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_2_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_2_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_2_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_2_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_2_COUT_SCALE */ +#define MME_SHADOW_2_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_2_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_CIN_SCALE */ +#define MME_SHADOW_2_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_2_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_GEMMLOWP_ZP */ +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_2_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_2_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_2_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_2_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_2_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_2_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_2_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_2_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_2_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_VALID_ELEMENTS */ +#define MME_SHADOW_2_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_LOOP_STRIDE */ +#define MME_SHADOW_2_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_ROI_SIZE */ +#define MME_SHADOW_2_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_STRIDE */ +#define MME_SHADOW_2_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_VALID_ELEMENTS */ +#define MME_SHADOW_2_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_LOOP_STRIDE */ +#define MME_SHADOW_2_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_ROI_SIZE */ +#define MME_SHADOW_2_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_STRIDE */ +#define MME_SHADOW_2_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_2_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_VALID_ELEMENTS */ +#define MME_SHADOW_2_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_2_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_LOOP_STRIDE */ +#define MME_SHADOW_2_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_ROI_SIZE */ +#define MME_SHADOW_2_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_2_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_2_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_STRIDE */ +#define MME_SHADOW_2_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_2_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_2_E_PADDING_VALUE_A */ +#define MME_SHADOW_2_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_2_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_2_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_2_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_2_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_2_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_2_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +/* MME_SHADOW_3_STATUS */ +#define MME_SHADOW_3_STATUS_A_SHIFT 0 +#define MME_SHADOW_3_STATUS_A_MASK 0x1 +#define MME_SHADOW_3_STATUS_B_SHIFT 1 +#define MME_SHADOW_3_STATUS_B_MASK 0x2 +#define MME_SHADOW_3_STATUS_CIN_SHIFT 2 +#define MME_SHADOW_3_STATUS_CIN_MASK 0x4 +#define MME_SHADOW_3_STATUS_COUT_SHIFT 3 +#define MME_SHADOW_3_STATUS_COUT_MASK 0x8 +#define MME_SHADOW_3_STATUS_TE_SHIFT 4 +#define MME_SHADOW_3_STATUS_TE_MASK 0x10 +#define MME_SHADOW_3_STATUS_LD_SHIFT 5 +#define MME_SHADOW_3_STATUS_LD_MASK 0x20 +#define MME_SHADOW_3_STATUS_ST_SHIFT 6 +#define MME_SHADOW_3_STATUS_ST_MASK 0x40 + +/* MME_SHADOW_3_A_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_A_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_B_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_CIN_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_COUT_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_COUT_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_BIAS_BASE_ADDR_HIGH */ +#define MME_SHADOW_3_BIAS_BASE_ADDR_HIGH_V_SHIFT 0 +#define MME_SHADOW_3_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_BASE_ADDR_LOW */ +#define MME_SHADOW_3_A_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_BASE_ADDR_LOW */ +#define MME_SHADOW_3_B_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_BASE_ADDR_LOW */ +#define MME_SHADOW_3_CIN_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_COUT_BASE_ADDR_LOW */ +#define MME_SHADOW_3_COUT_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_BIAS_BASE_ADDR_LOW */ +#define MME_SHADOW_3_BIAS_BASE_ADDR_LOW_V_SHIFT 0 +#define MME_SHADOW_3_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_HEADER */ +#define MME_SHADOW_3_HEADER_SIGNAL_MASK_SHIFT 0 +#define MME_SHADOW_3_HEADER_SIGNAL_MASK_MASK 0x1F +#define MME_SHADOW_3_HEADER_SIGNAL_EN_SHIFT 5 +#define MME_SHADOW_3_HEADER_SIGNAL_EN_MASK 0x20 +#define MME_SHADOW_3_HEADER_TRANS_A_SHIFT 6 +#define MME_SHADOW_3_HEADER_TRANS_A_MASK 0x40 +#define MME_SHADOW_3_HEADER_LOWER_A_SHIFT 7 +#define MME_SHADOW_3_HEADER_LOWER_A_MASK 0x80 +#define MME_SHADOW_3_HEADER_ACCUM_MASK_SHIFT 8 +#define MME_SHADOW_3_HEADER_ACCUM_MASK_MASK 0xF00 +#define MME_SHADOW_3_HEADER_LOAD_BIAS_SHIFT 12 +#define MME_SHADOW_3_HEADER_LOAD_BIAS_MASK 0x1000 +#define MME_SHADOW_3_HEADER_LOAD_CIN_SHIFT 13 +#define MME_SHADOW_3_HEADER_LOAD_CIN_MASK 0x2000 +#define MME_SHADOW_3_HEADER_STORE_OUT_SHIFT 15 +#define MME_SHADOW_3_HEADER_STORE_OUT_MASK 0x8000 +#define MME_SHADOW_3_HEADER_ACC_LD_INC_DISABLE_SHIFT 16 +#define MME_SHADOW_3_HEADER_ACC_LD_INC_DISABLE_MASK 0x10000 +#define MME_SHADOW_3_HEADER_ADVANCE_A_SHIFT 17 +#define MME_SHADOW_3_HEADER_ADVANCE_A_MASK 0x20000 +#define MME_SHADOW_3_HEADER_ADVANCE_B_SHIFT 18 +#define MME_SHADOW_3_HEADER_ADVANCE_B_MASK 0x40000 +#define MME_SHADOW_3_HEADER_ADVANCE_CIN_SHIFT 19 +#define MME_SHADOW_3_HEADER_ADVANCE_CIN_MASK 0x80000 +#define MME_SHADOW_3_HEADER_ADVANCE_COUT_SHIFT 20 +#define MME_SHADOW_3_HEADER_ADVANCE_COUT_MASK 0x100000 +#define MME_SHADOW_3_HEADER_COMPRESSED_B_SHIFT 21 +#define MME_SHADOW_3_HEADER_COMPRESSED_B_MASK 0x200000 +#define MME_SHADOW_3_HEADER_MASK_CONV_END_SHIFT 22 +#define MME_SHADOW_3_HEADER_MASK_CONV_END_MASK 0x400000 +#define MME_SHADOW_3_HEADER_ACC_ST_INC_DISABLE_SHIFT 23 +#define MME_SHADOW_3_HEADER_ACC_ST_INC_DISABLE_MASK 0x800000 +#define MME_SHADOW_3_HEADER_AB_DATA_TYPE_SHIFT 24 +#define MME_SHADOW_3_HEADER_AB_DATA_TYPE_MASK 0x3000000 +#define MME_SHADOW_3_HEADER_CIN_DATA_TYPE_SHIFT 26 +#define MME_SHADOW_3_HEADER_CIN_DATA_TYPE_MASK 0x1C000000 +#define MME_SHADOW_3_HEADER_COUT_DATA_TYPE_SHIFT 29 +#define MME_SHADOW_3_HEADER_COUT_DATA_TYPE_MASK 0xE0000000 + +/* MME_SHADOW_3_KERNEL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_0_SHIFT 0 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_0_MASK 0xFF +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_1_SHIFT 8 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_1_MASK 0xFF00 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_2_SHIFT 16 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_2_MASK 0xFF0000 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_3_SHIFT 24 +#define MME_SHADOW_3_KERNEL_SIZE_MINUS_1_DIM_3_MASK 0xFF000000 + +/* MME_SHADOW_3_ASSOCIATED_DIMS */ +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_0_SHIFT 0 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_0_MASK 0x7 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_0_SHIFT 3 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_0_MASK 0x38 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_0_SHIFT 6 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_0_MASK 0x1C0 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_0_SHIFT 9 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_0_MASK 0xE00 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_1_SHIFT 16 +#define MME_SHADOW_3_ASSOCIATED_DIMS_A_1_MASK 0x70000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_1_SHIFT 19 +#define MME_SHADOW_3_ASSOCIATED_DIMS_B_1_MASK 0x380000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_1_SHIFT 22 +#define MME_SHADOW_3_ASSOCIATED_DIMS_CIN_1_MASK 0x1C00000 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_1_SHIFT 25 +#define MME_SHADOW_3_ASSOCIATED_DIMS_COUT_1_MASK 0xE000000 + +/* MME_SHADOW_3_COUT_SCALE */ +#define MME_SHADOW_3_COUT_SCALE_V_SHIFT 0 +#define MME_SHADOW_3_COUT_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_CIN_SCALE */ +#define MME_SHADOW_3_CIN_SCALE_V_SHIFT 0 +#define MME_SHADOW_3_CIN_SCALE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_GEMMLOWP_ZP */ +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_CIN_SHIFT 0 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_CIN_MASK 0x1FF +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_COUT_SHIFT 9 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_COUT_MASK 0x3FE00 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_B_SHIFT 18 +#define MME_SHADOW_3_GEMMLOWP_ZP_ZP_B_MASK 0x7FC0000 +#define MME_SHADOW_3_GEMMLOWP_ZP_GEMMLOWP_EU_EN_SHIFT 27 +#define MME_SHADOW_3_GEMMLOWP_ZP_GEMMLOWP_EU_EN_MASK 0x8000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_SHIFT 28 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_MASK 0x10000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_BIAS_SHIFT 29 +#define MME_SHADOW_3_GEMMLOWP_ZP_ACCUM_BIAS_MASK 0x20000000 +#define MME_SHADOW_3_GEMMLOWP_ZP_RELU_EN_SHIFT 30 +#define MME_SHADOW_3_GEMMLOWP_ZP_RELU_EN_MASK 0x40000000 + +/* MME_SHADOW_3_GEMMLOWP_EXPONENT */ +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_CIN_SHIFT 0 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_CIN_MASK 0x3F +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_COUT_SHIFT 8 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_EXPONENT_COUT_MASK 0x3F00 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_CIN_EN_SHIFT 16 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_CIN_EN_MASK 0x10000 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_COUT_EN_SHIFT 17 +#define MME_SHADOW_3_GEMMLOWP_EXPONENT_MUL_COUT_EN_MASK 0x20000 + +/* MME_SHADOW_3_A_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_A_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_A_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_VALID_ELEMENTS */ +#define MME_SHADOW_3_A_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_A_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_LOOP_STRIDE */ +#define MME_SHADOW_3_A_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_A_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_ROI_SIZE */ +#define MME_SHADOW_3_A_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_A_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_A_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_STRIDE */ +#define MME_SHADOW_3_A_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_B_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_B_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_VALID_ELEMENTS */ +#define MME_SHADOW_3_B_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_B_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_LOOP_STRIDE */ +#define MME_SHADOW_3_B_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_B_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_ROI_SIZE */ +#define MME_SHADOW_3_B_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_B_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_B_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_STRIDE */ +#define MME_SHADOW_3_B_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_ROI_BASE_OFFSET */ +#define MME_SHADOW_3_C_ROI_BASE_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_C_ROI_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_VALID_ELEMENTS */ +#define MME_SHADOW_3_C_VALID_ELEMENTS_V_SHIFT 0 +#define MME_SHADOW_3_C_VALID_ELEMENTS_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_LOOP_STRIDE */ +#define MME_SHADOW_3_C_LOOP_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_C_LOOP_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_ROI_SIZE */ +#define MME_SHADOW_3_C_ROI_SIZE_V_SHIFT 0 +#define MME_SHADOW_3_C_ROI_SIZE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_START_OFFSET */ +#define MME_SHADOW_3_C_SPATIAL_START_OFFSET_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_START_OFFSET_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_STRIDE */ +#define MME_SHADOW_3_C_SPATIAL_STRIDE_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_STRIDE_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1 */ +#define MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_SYNC_OBJECT_MESSAGE */ +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define MME_SHADOW_3_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* MME_SHADOW_3_E_PADDING_VALUE_A */ +#define MME_SHADOW_3_E_PADDING_VALUE_A_V_SHIFT 0 +#define MME_SHADOW_3_E_PADDING_VALUE_A_V_MASK 0xFFFF + +/* MME_SHADOW_3_E_NUM_ITERATION_MINUS_1 */ +#define MME_SHADOW_3_E_NUM_ITERATION_MINUS_1_V_SHIFT 0 +#define MME_SHADOW_3_E_NUM_ITERATION_MINUS_1_V_MASK 0xFFFFFFFF + +/* MME_SHADOW_3_E_BUBBLES_PER_SPLIT */ +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_A_SHIFT 0 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_A_MASK 0xFF +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_B_SHIFT 8 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_B_MASK 0xFF00 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_CIN_SHIFT 16 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_CIN_MASK 0xFF0000 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_ID_SHIFT 24 +#define MME_SHADOW_3_E_BUBBLES_PER_SPLIT_ID_MASK 0xFF000000 + +#endif /* ASIC_REG_MME_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h new file mode 100644 index 000000000..e464e3815 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_QM_MASKS_H_ +#define ASIC_REG_MME_QM_MASKS_H_ + +/* + ***************************************** + * MME_QM (Prototype: QMAN) + ***************************************** + */ + +/* MME_QM_GLBL_CFG0 */ +#define MME_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME_QM_GLBL_CFG0_PQF_EN_MASK 0x1 +#define MME_QM_GLBL_CFG0_CQF_EN_SHIFT 1 +#define MME_QM_GLBL_CFG0_CQF_EN_MASK 0x2 +#define MME_QM_GLBL_CFG0_CP_EN_SHIFT 2 +#define MME_QM_GLBL_CFG0_CP_EN_MASK 0x4 +#define MME_QM_GLBL_CFG0_DMA_EN_SHIFT 3 +#define MME_QM_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* MME_QM_GLBL_CFG1 */ +#define MME_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define MME_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define MME_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define MME_QM_GLBL_CFG1_CP_STOP_SHIFT 2 +#define MME_QM_GLBL_CFG1_CP_STOP_MASK 0x4 +#define MME_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define MME_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define MME_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define MME_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define MME_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define MME_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define MME_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define MME_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define MME_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define MME_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* MME_QM_GLBL_PROT */ +#define MME_QM_GLBL_PROT_PQF_PROT_SHIFT 0 +#define MME_QM_GLBL_PROT_PQF_PROT_MASK 0x1 +#define MME_QM_GLBL_PROT_CQF_PROT_SHIFT 1 +#define MME_QM_GLBL_PROT_CQF_PROT_MASK 0x2 +#define MME_QM_GLBL_PROT_CP_PROT_SHIFT 2 +#define MME_QM_GLBL_PROT_CP_PROT_MASK 0x4 +#define MME_QM_GLBL_PROT_DMA_PROT_SHIFT 3 +#define MME_QM_GLBL_PROT_DMA_PROT_MASK 0x8 +#define MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define MME_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define MME_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define MME_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define MME_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* MME_QM_GLBL_ERR_CFG */ +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* MME_QM_GLBL_ERR_ADDR_LO */ +#define MME_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_ERR_ADDR_HI */ +#define MME_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_ERR_WDATA */ +#define MME_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME_QM_GLBL_SECURE_PROPS */ +#define MME_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define MME_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_QM_GLBL_NON_SECURE_PROPS */ +#define MME_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define MME_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define MME_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define MME_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* MME_QM_GLBL_STS0 */ +#define MME_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define MME_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define MME_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define MME_QM_GLBL_STS0_CP_IDLE_SHIFT 2 +#define MME_QM_GLBL_STS0_CP_IDLE_MASK 0x4 +#define MME_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define MME_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define MME_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define MME_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define MME_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define MME_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define MME_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define MME_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define MME_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define MME_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* MME_QM_GLBL_STS1 */ +#define MME_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define MME_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define MME_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define MME_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define MME_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define MME_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* MME_QM_PQ_BASE_LO */ +#define MME_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define MME_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_BASE_HI */ +#define MME_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define MME_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_SIZE */ +#define MME_QM_PQ_SIZE_VAL_SHIFT 0 +#define MME_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PI */ +#define MME_QM_PQ_PI_VAL_SHIFT 0 +#define MME_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_CI */ +#define MME_QM_PQ_CI_VAL_SHIFT 0 +#define MME_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_CFG0 */ +#define MME_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define MME_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* MME_QM_PQ_CFG1 */ +#define MME_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_QM_PQ_ARUSER */ +#define MME_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_QM_PQ_ARUSER_WORD_SHIFT 1 +#define MME_QM_PQ_ARUSER_WORD_MASK 0x2 + +/* MME_QM_PQ_PUSH0 */ +#define MME_QM_PQ_PUSH0_PTR_LO_SHIFT 0 +#define MME_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH1 */ +#define MME_QM_PQ_PUSH1_PTR_HI_SHIFT 0 +#define MME_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH2 */ +#define MME_QM_PQ_PUSH2_TSIZE_SHIFT 0 +#define MME_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* MME_QM_PQ_PUSH3 */ +#define MME_QM_PQ_PUSH3_RPT_SHIFT 0 +#define MME_QM_PQ_PUSH3_RPT_MASK 0xFFFF +#define MME_QM_PQ_PUSH3_CTL_SHIFT 16 +#define MME_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* MME_QM_PQ_STS0 */ +#define MME_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define MME_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define MME_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define MME_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_QM_PQ_STS1 */ +#define MME_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define MME_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define MME_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define MME_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* MME_QM_PQ_RD_RATE_LIM_EN */ +#define MME_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_QM_PQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_QM_PQ_RD_RATE_LIM_SAT */ +#define MME_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_QM_PQ_RD_RATE_LIM_TOUT */ +#define MME_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_QM_CQ_CFG0 */ +#define MME_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define MME_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME_QM_CQ_CFG1 */ +#define MME_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME_QM_CQ_ARUSER */ +#define MME_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define MME_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define MME_QM_CQ_ARUSER_WORD_SHIFT 1 +#define MME_QM_CQ_ARUSER_WORD_MASK 0x2 + +/* MME_QM_CQ_PTR_LO */ +#define MME_QM_CQ_PTR_LO_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_PTR_HI */ +#define MME_QM_CQ_PTR_HI_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_TSIZE */ +#define MME_QM_CQ_TSIZE_VAL_SHIFT 0 +#define MME_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_CTL */ +#define MME_QM_CQ_CTL_RPT_SHIFT 0 +#define MME_QM_CQ_CTL_RPT_MASK 0xFFFF +#define MME_QM_CQ_CTL_CTL_SHIFT 16 +#define MME_QM_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* MME_QM_CQ_PTR_LO_STS */ +#define MME_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_PTR_HI_STS */ +#define MME_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_TSIZE_STS */ +#define MME_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_CTL_STS */ +#define MME_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define MME_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define MME_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME_QM_CQ_STS0 */ +#define MME_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME_QM_CQ_STS1 */ +#define MME_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME_QM_CQ_RD_RATE_LIM_EN */ +#define MME_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* MME_QM_CQ_RD_RATE_LIM_RST_TOKEN */ +#define MME_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* MME_QM_CQ_RD_RATE_LIM_SAT */ +#define MME_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* MME_QM_CQ_RD_RATE_LIM_TOUT */ +#define MME_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define MME_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* MME_QM_CQ_IFIFO_CNT */ +#define MME_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME_QM_CP_MSG_BASE0_ADDR_LO */ +#define MME_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE0_ADDR_HI */ +#define MME_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE1_ADDR_LO */ +#define MME_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE1_ADDR_HI */ +#define MME_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE2_ADDR_LO */ +#define MME_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE2_ADDR_HI */ +#define MME_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE3_ADDR_LO */ +#define MME_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_MSG_BASE3_ADDR_HI */ +#define MME_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_TSIZE_OFFSET */ +#define MME_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_DST_BASE_HI_OFFSET */ +#define MME_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_LDMA_COMMIT_OFFSET */ +#define MME_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define MME_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_FENCE0_RDATA */ +#define MME_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE1_RDATA */ +#define MME_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE2_RDATA */ +#define MME_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE3_RDATA */ +#define MME_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME_QM_CP_FENCE0_CNT */ +#define MME_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE1_CNT */ +#define MME_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE2_CNT */ +#define MME_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_FENCE3_CNT */ +#define MME_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME_QM_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* MME_QM_CP_STS */ +#define MME_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME_QM_CP_STS_ERDY_SHIFT 16 +#define MME_QM_CP_STS_ERDY_MASK 0x10000 +#define MME_QM_CP_STS_RRDY_SHIFT 17 +#define MME_QM_CP_STS_RRDY_MASK 0x20000 +#define MME_QM_CP_STS_MRDY_SHIFT 18 +#define MME_QM_CP_STS_MRDY_MASK 0x40000 +#define MME_QM_CP_STS_SW_STOP_SHIFT 19 +#define MME_QM_CP_STS_SW_STOP_MASK 0x80000 +#define MME_QM_CP_STS_FENCE_ID_SHIFT 20 +#define MME_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define MME_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME_QM_CP_CURRENT_INST_LO */ +#define MME_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_CURRENT_INST_HI */ +#define MME_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CP_BARRIER_CFG */ +#define MME_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* MME_QM_CP_DBG_0 */ +#define MME_QM_CP_DBG_0_VAL_SHIFT 0 +#define MME_QM_CP_DBG_0_VAL_MASK 0xFF + +/* MME_QM_PQ_BUF_ADDR */ +#define MME_QM_PQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_QM_PQ_BUF_RDATA */ +#define MME_QM_PQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_BUF_ADDR */ +#define MME_QM_CQ_BUF_ADDR_VAL_SHIFT 0 +#define MME_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* MME_QM_CQ_BUF_RDATA */ +#define MME_QM_CQ_BUF_RDATA_VAL_SHIFT 0 +#define MME_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MME_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h new file mode 100644 index 000000000..538708bef --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_QM_REGS_H_ +#define ASIC_REG_MME_QM_REGS_H_ + +/* + ***************************************** + * MME_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME_QM_GLBL_CFG0 0xD8000 + +#define mmMME_QM_GLBL_CFG1 0xD8004 + +#define mmMME_QM_GLBL_PROT 0xD8008 + +#define mmMME_QM_GLBL_ERR_CFG 0xD800C + +#define mmMME_QM_GLBL_ERR_ADDR_LO 0xD8010 + +#define mmMME_QM_GLBL_ERR_ADDR_HI 0xD8014 + +#define mmMME_QM_GLBL_ERR_WDATA 0xD8018 + +#define mmMME_QM_GLBL_SECURE_PROPS 0xD801C + +#define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD8020 + +#define mmMME_QM_GLBL_STS0 0xD8024 + +#define mmMME_QM_GLBL_STS1 0xD8028 + +#define mmMME_QM_PQ_BASE_LO 0xD8060 + +#define mmMME_QM_PQ_BASE_HI 0xD8064 + +#define mmMME_QM_PQ_SIZE 0xD8068 + +#define mmMME_QM_PQ_PI 0xD806C + +#define mmMME_QM_PQ_CI 0xD8070 + +#define mmMME_QM_PQ_CFG0 0xD8074 + +#define mmMME_QM_PQ_CFG1 0xD8078 + +#define mmMME_QM_PQ_ARUSER 0xD807C + +#define mmMME_QM_PQ_PUSH0 0xD8080 + +#define mmMME_QM_PQ_PUSH1 0xD8084 + +#define mmMME_QM_PQ_PUSH2 0xD8088 + +#define mmMME_QM_PQ_PUSH3 0xD808C + +#define mmMME_QM_PQ_STS0 0xD8090 + +#define mmMME_QM_PQ_STS1 0xD8094 + +#define mmMME_QM_PQ_RD_RATE_LIM_EN 0xD80A0 + +#define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xD80A4 + +#define mmMME_QM_PQ_RD_RATE_LIM_SAT 0xD80A8 + +#define mmMME_QM_PQ_RD_RATE_LIM_TOUT 0xD80AC + +#define mmMME_QM_CQ_CFG0 0xD80B0 + +#define mmMME_QM_CQ_CFG1 0xD80B4 + +#define mmMME_QM_CQ_ARUSER 0xD80B8 + +#define mmMME_QM_CQ_PTR_LO 0xD80C0 + +#define mmMME_QM_CQ_PTR_HI 0xD80C4 + +#define mmMME_QM_CQ_TSIZE 0xD80C8 + +#define mmMME_QM_CQ_CTL 0xD80CC + +#define mmMME_QM_CQ_PTR_LO_STS 0xD80D4 + +#define mmMME_QM_CQ_PTR_HI_STS 0xD80D8 + +#define mmMME_QM_CQ_TSIZE_STS 0xD80DC + +#define mmMME_QM_CQ_CTL_STS 0xD80E0 + +#define mmMME_QM_CQ_STS0 0xD80E4 + +#define mmMME_QM_CQ_STS1 0xD80E8 + +#define mmMME_QM_CQ_RD_RATE_LIM_EN 0xD80F0 + +#define mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xD80F4 + +#define mmMME_QM_CQ_RD_RATE_LIM_SAT 0xD80F8 + +#define mmMME_QM_CQ_RD_RATE_LIM_TOUT 0xD80FC + +#define mmMME_QM_CQ_IFIFO_CNT 0xD8108 + +#define mmMME_QM_CP_MSG_BASE0_ADDR_LO 0xD8120 + +#define mmMME_QM_CP_MSG_BASE0_ADDR_HI 0xD8124 + +#define mmMME_QM_CP_MSG_BASE1_ADDR_LO 0xD8128 + +#define mmMME_QM_CP_MSG_BASE1_ADDR_HI 0xD812C + +#define mmMME_QM_CP_MSG_BASE2_ADDR_LO 0xD8130 + +#define mmMME_QM_CP_MSG_BASE2_ADDR_HI 0xD8134 + +#define mmMME_QM_CP_MSG_BASE3_ADDR_LO 0xD8138 + +#define mmMME_QM_CP_MSG_BASE3_ADDR_HI 0xD813C + +#define mmMME_QM_CP_LDMA_TSIZE_OFFSET 0xD8140 + +#define mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xD8144 + +#define mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xD8148 + +#define mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xD814C + +#define mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xD8150 + +#define mmMME_QM_CP_LDMA_COMMIT_OFFSET 0xD8154 + +#define mmMME_QM_CP_FENCE0_RDATA 0xD8158 + +#define mmMME_QM_CP_FENCE1_RDATA 0xD815C + +#define mmMME_QM_CP_FENCE2_RDATA 0xD8160 + +#define mmMME_QM_CP_FENCE3_RDATA 0xD8164 + +#define mmMME_QM_CP_FENCE0_CNT 0xD8168 + +#define mmMME_QM_CP_FENCE1_CNT 0xD816C + +#define mmMME_QM_CP_FENCE2_CNT 0xD8170 + +#define mmMME_QM_CP_FENCE3_CNT 0xD8174 + +#define mmMME_QM_CP_STS 0xD8178 + +#define mmMME_QM_CP_CURRENT_INST_LO 0xD817C + +#define mmMME_QM_CP_CURRENT_INST_HI 0xD8180 + +#define mmMME_QM_CP_BARRIER_CFG 0xD8184 + +#define mmMME_QM_CP_DBG_0 0xD8188 + +#define mmMME_QM_PQ_BUF_ADDR 0xD8300 + +#define mmMME_QM_PQ_BUF_RDATA 0xD8304 + +#define mmMME_QM_CQ_BUF_ADDR 0xD8308 + +#define mmMME_QM_CQ_BUF_RDATA 0xD830C + +#endif /* ASIC_REG_MME_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h new file mode 100644 index 000000000..0396cbfd5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h @@ -0,0 +1,1152 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME_REGS_H_ +#define ASIC_REG_MME_REGS_H_ + +/* + ***************************************** + * MME (Prototype: MME) + ***************************************** + */ + +#define mmMME_ARCH_STATUS 0xD0000 + +#define mmMME_ARCH_A_BASE_ADDR_HIGH 0xD0008 + +#define mmMME_ARCH_B_BASE_ADDR_HIGH 0xD000C + +#define mmMME_ARCH_CIN_BASE_ADDR_HIGH 0xD0010 + +#define mmMME_ARCH_COUT_BASE_ADDR_HIGH 0xD0014 + +#define mmMME_ARCH_BIAS_BASE_ADDR_HIGH 0xD0018 + +#define mmMME_ARCH_A_BASE_ADDR_LOW 0xD001C + +#define mmMME_ARCH_B_BASE_ADDR_LOW 0xD0020 + +#define mmMME_ARCH_CIN_BASE_ADDR_LOW 0xD0024 + +#define mmMME_ARCH_COUT_BASE_ADDR_LOW 0xD0028 + +#define mmMME_ARCH_BIAS_BASE_ADDR_LOW 0xD002C + +#define mmMME_ARCH_HEADER 0xD0030 + +#define mmMME_ARCH_KERNEL_SIZE_MINUS_1 0xD0034 + +#define mmMME_ARCH_ASSOCIATED_DIMS_0 0xD0038 + +#define mmMME_ARCH_ASSOCIATED_DIMS_1 0xD003C + +#define mmMME_ARCH_COUT_SCALE 0xD0040 + +#define mmMME_ARCH_CIN_SCALE 0xD0044 + +#define mmMME_ARCH_GEMMLOWP_ZP 0xD0048 + +#define mmMME_ARCH_GEMMLOWP_EXPONENT 0xD004C + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_0 0xD0050 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_1 0xD0054 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_2 0xD0058 + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_3 0xD005C + +#define mmMME_ARCH_A_ROI_BASE_OFFSET_4 0xD0060 + +#define mmMME_ARCH_A_VALID_ELEMENTS_0 0xD0064 + +#define mmMME_ARCH_A_VALID_ELEMENTS_1 0xD0068 + +#define mmMME_ARCH_A_VALID_ELEMENTS_2 0xD006C + +#define mmMME_ARCH_A_VALID_ELEMENTS_3 0xD0070 + +#define mmMME_ARCH_A_VALID_ELEMENTS_4 0xD0074 + +#define mmMME_ARCH_A_LOOP_STRIDE_0 0xD0078 + +#define mmMME_ARCH_A_LOOP_STRIDE_1 0xD007C + +#define mmMME_ARCH_A_LOOP_STRIDE_2 0xD0080 + +#define mmMME_ARCH_A_LOOP_STRIDE_3 0xD0084 + +#define mmMME_ARCH_A_LOOP_STRIDE_4 0xD0088 + +#define mmMME_ARCH_A_ROI_SIZE_0 0xD008C + +#define mmMME_ARCH_A_ROI_SIZE_1 0xD0090 + +#define mmMME_ARCH_A_ROI_SIZE_2 0xD0094 + +#define mmMME_ARCH_A_ROI_SIZE_3 0xD0098 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_0 0xD009C + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_1 0xD00A0 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_2 0xD00A4 + +#define mmMME_ARCH_A_SPATIAL_START_OFFSET_3 0xD00A8 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_0 0xD00AC + +#define mmMME_ARCH_A_SPATIAL_STRIDE_1 0xD00B0 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_2 0xD00B4 + +#define mmMME_ARCH_A_SPATIAL_STRIDE_3 0xD00B8 + +#define mmMME_ARCH_A_SPATIAL_SIZE_MINUS_1 0xD00BC + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_0 0xD00C0 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_1 0xD00C4 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_2 0xD00C8 + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_3 0xD00CC + +#define mmMME_ARCH_B_ROI_BASE_OFFSET_4 0xD00D0 + +#define mmMME_ARCH_B_VALID_ELEMENTS_0 0xD00D4 + +#define mmMME_ARCH_B_VALID_ELEMENTS_1 0xD00D8 + +#define mmMME_ARCH_B_VALID_ELEMENTS_2 0xD00DC + +#define mmMME_ARCH_B_VALID_ELEMENTS_3 0xD00E0 + +#define mmMME_ARCH_B_VALID_ELEMENTS_4 0xD00E4 + +#define mmMME_ARCH_B_LOOP_STRIDE_0 0xD00E8 + +#define mmMME_ARCH_B_LOOP_STRIDE_1 0xD00EC + +#define mmMME_ARCH_B_LOOP_STRIDE_2 0xD00F0 + +#define mmMME_ARCH_B_LOOP_STRIDE_3 0xD00F4 + +#define mmMME_ARCH_B_LOOP_STRIDE_4 0xD00F8 + +#define mmMME_ARCH_B_ROI_SIZE_0 0xD00FC + +#define mmMME_ARCH_B_ROI_SIZE_1 0xD0100 + +#define mmMME_ARCH_B_ROI_SIZE_2 0xD0104 + +#define mmMME_ARCH_B_ROI_SIZE_3 0xD0108 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_0 0xD010C + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_1 0xD0110 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_2 0xD0114 + +#define mmMME_ARCH_B_SPATIAL_START_OFFSET_3 0xD0118 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_0 0xD011C + +#define mmMME_ARCH_B_SPATIAL_STRIDE_1 0xD0120 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_2 0xD0124 + +#define mmMME_ARCH_B_SPATIAL_STRIDE_3 0xD0128 + +#define mmMME_ARCH_B_SPATIAL_SIZE_MINUS_1 0xD012C + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_0 0xD0130 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_1 0xD0134 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_2 0xD0138 + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_3 0xD013C + +#define mmMME_ARCH_C_ROI_BASE_OFFSET_4 0xD0140 + +#define mmMME_ARCH_C_VALID_ELEMENTS_0 0xD0144 + +#define mmMME_ARCH_C_VALID_ELEMENTS_1 0xD0148 + +#define mmMME_ARCH_C_VALID_ELEMENTS_2 0xD014C + +#define mmMME_ARCH_C_VALID_ELEMENTS_3 0xD0150 + +#define mmMME_ARCH_C_VALID_ELEMENTS_4 0xD0154 + +#define mmMME_ARCH_C_LOOP_STRIDE_0 0xD0158 + +#define mmMME_ARCH_C_LOOP_STRIDE_1 0xD015C + +#define mmMME_ARCH_C_LOOP_STRIDE_2 0xD0160 + +#define mmMME_ARCH_C_LOOP_STRIDE_3 0xD0164 + +#define mmMME_ARCH_C_LOOP_STRIDE_4 0xD0168 + +#define mmMME_ARCH_C_ROI_SIZE_0 0xD016C + +#define mmMME_ARCH_C_ROI_SIZE_1 0xD0170 + +#define mmMME_ARCH_C_ROI_SIZE_2 0xD0174 + +#define mmMME_ARCH_C_ROI_SIZE_3 0xD0178 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_0 0xD017C + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_1 0xD0180 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_2 0xD0184 + +#define mmMME_ARCH_C_SPATIAL_START_OFFSET_3 0xD0188 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_0 0xD018C + +#define mmMME_ARCH_C_SPATIAL_STRIDE_1 0xD0190 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_2 0xD0194 + +#define mmMME_ARCH_C_SPATIAL_STRIDE_3 0xD0198 + +#define mmMME_ARCH_C_SPATIAL_SIZE_MINUS_1 0xD019C + +#define mmMME_ARCH_SYNC_OBJECT_MESSAGE 0xD01A0 + +#define mmMME_ARCH_E_PADDING_VALUE_A 0xD01A4 + +#define mmMME_ARCH_E_NUM_ITERATION_MINUS_1 0xD01A8 + +#define mmMME_ARCH_E_BUBBLES_PER_SPLIT 0xD01AC + +#define mmMME_CMD 0xD0200 + +#define mmMME_DUMMY 0xD0204 + +#define mmMME_RESET 0xD0208 + +#define mmMME_STALL 0xD020C + +#define mmMME_SM_BASE_ADDRESS_LOW 0xD0210 + +#define mmMME_SM_BASE_ADDRESS_HIGH 0xD0214 + +#define mmMME_DBGMEM_ADD 0xD0218 + +#define mmMME_DBGMEM_DATA_WR 0xD021C + +#define mmMME_DBGMEM_DATA_RD 0xD0220 + +#define mmMME_DBGMEM_CTRL 0xD0224 + +#define mmMME_DBGMEM_RC 0xD0228 + +#define mmMME_LOG_SHADOW 0xD022C + +#define mmMME_STORE_MAX_CREDIT 0xD0300 + +#define mmMME_AGU 0xD0304 + +#define mmMME_SBA 0xD0308 + +#define mmMME_SBB 0xD030C + +#define mmMME_SBC 0xD0310 + +#define mmMME_WBC 0xD0314 + +#define mmMME_SBA_CONTROL_DATA 0xD0318 + +#define mmMME_SBB_CONTROL_DATA 0xD031C + +#define mmMME_SBC_CONTROL_DATA 0xD0320 + +#define mmMME_WBC_CONTROL_DATA 0xD0324 + +#define mmMME_TE 0xD0328 + +#define mmMME_TE2DEC 0xD032C + +#define mmMME_REI_STATUS 0xD0330 + +#define mmMME_REI_MASK 0xD0334 + +#define mmMME_SEI_STATUS 0xD0338 + +#define mmMME_SEI_MASK 0xD033C + +#define mmMME_SPI_STATUS 0xD0340 + +#define mmMME_SPI_MASK 0xD0344 + +#define mmMME_SHADOW_0_STATUS 0xD0400 + +#define mmMME_SHADOW_0_A_BASE_ADDR_HIGH 0xD0408 + +#define mmMME_SHADOW_0_B_BASE_ADDR_HIGH 0xD040C + +#define mmMME_SHADOW_0_CIN_BASE_ADDR_HIGH 0xD0410 + +#define mmMME_SHADOW_0_COUT_BASE_ADDR_HIGH 0xD0414 + +#define mmMME_SHADOW_0_BIAS_BASE_ADDR_HIGH 0xD0418 + +#define mmMME_SHADOW_0_A_BASE_ADDR_LOW 0xD041C + +#define mmMME_SHADOW_0_B_BASE_ADDR_LOW 0xD0420 + +#define mmMME_SHADOW_0_CIN_BASE_ADDR_LOW 0xD0424 + +#define mmMME_SHADOW_0_COUT_BASE_ADDR_LOW 0xD0428 + +#define mmMME_SHADOW_0_BIAS_BASE_ADDR_LOW 0xD042C + +#define mmMME_SHADOW_0_HEADER 0xD0430 + +#define mmMME_SHADOW_0_KERNEL_SIZE_MINUS_1 0xD0434 + +#define mmMME_SHADOW_0_ASSOCIATED_DIMS_0 0xD0438 + +#define mmMME_SHADOW_0_ASSOCIATED_DIMS_1 0xD043C + +#define mmMME_SHADOW_0_COUT_SCALE 0xD0440 + +#define mmMME_SHADOW_0_CIN_SCALE 0xD0444 + +#define mmMME_SHADOW_0_GEMMLOWP_ZP 0xD0448 + +#define mmMME_SHADOW_0_GEMMLOWP_EXPONENT 0xD044C + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_0 0xD0450 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_1 0xD0454 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_2 0xD0458 + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_3 0xD045C + +#define mmMME_SHADOW_0_A_ROI_BASE_OFFSET_4 0xD0460 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_0 0xD0464 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_1 0xD0468 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_2 0xD046C + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_3 0xD0470 + +#define mmMME_SHADOW_0_A_VALID_ELEMENTS_4 0xD0474 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_0 0xD0478 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_1 0xD047C + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_2 0xD0480 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_3 0xD0484 + +#define mmMME_SHADOW_0_A_LOOP_STRIDE_4 0xD0488 + +#define mmMME_SHADOW_0_A_ROI_SIZE_0 0xD048C + +#define mmMME_SHADOW_0_A_ROI_SIZE_1 0xD0490 + +#define mmMME_SHADOW_0_A_ROI_SIZE_2 0xD0494 + +#define mmMME_SHADOW_0_A_ROI_SIZE_3 0xD0498 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_0 0xD049C + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_1 0xD04A0 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_2 0xD04A4 + +#define mmMME_SHADOW_0_A_SPATIAL_START_OFFSET_3 0xD04A8 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_0 0xD04AC + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_1 0xD04B0 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_2 0xD04B4 + +#define mmMME_SHADOW_0_A_SPATIAL_STRIDE_3 0xD04B8 + +#define mmMME_SHADOW_0_A_SPATIAL_SIZE_MINUS_1 0xD04BC + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_0 0xD04C0 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_1 0xD04C4 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_2 0xD04C8 + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_3 0xD04CC + +#define mmMME_SHADOW_0_B_ROI_BASE_OFFSET_4 0xD04D0 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_0 0xD04D4 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_1 0xD04D8 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_2 0xD04DC + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_3 0xD04E0 + +#define mmMME_SHADOW_0_B_VALID_ELEMENTS_4 0xD04E4 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_0 0xD04E8 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_1 0xD04EC + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_2 0xD04F0 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_3 0xD04F4 + +#define mmMME_SHADOW_0_B_LOOP_STRIDE_4 0xD04F8 + +#define mmMME_SHADOW_0_B_ROI_SIZE_0 0xD04FC + +#define mmMME_SHADOW_0_B_ROI_SIZE_1 0xD0500 + +#define mmMME_SHADOW_0_B_ROI_SIZE_2 0xD0504 + +#define mmMME_SHADOW_0_B_ROI_SIZE_3 0xD0508 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_0 0xD050C + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_1 0xD0510 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_2 0xD0514 + +#define mmMME_SHADOW_0_B_SPATIAL_START_OFFSET_3 0xD0518 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_0 0xD051C + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_1 0xD0520 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_2 0xD0524 + +#define mmMME_SHADOW_0_B_SPATIAL_STRIDE_3 0xD0528 + +#define mmMME_SHADOW_0_B_SPATIAL_SIZE_MINUS_1 0xD052C + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_0 0xD0530 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_1 0xD0534 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_2 0xD0538 + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_3 0xD053C + +#define mmMME_SHADOW_0_C_ROI_BASE_OFFSET_4 0xD0540 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_0 0xD0544 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_1 0xD0548 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_2 0xD054C + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_3 0xD0550 + +#define mmMME_SHADOW_0_C_VALID_ELEMENTS_4 0xD0554 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_0 0xD0558 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_1 0xD055C + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_2 0xD0560 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_3 0xD0564 + +#define mmMME_SHADOW_0_C_LOOP_STRIDE_4 0xD0568 + +#define mmMME_SHADOW_0_C_ROI_SIZE_0 0xD056C + +#define mmMME_SHADOW_0_C_ROI_SIZE_1 0xD0570 + +#define mmMME_SHADOW_0_C_ROI_SIZE_2 0xD0574 + +#define mmMME_SHADOW_0_C_ROI_SIZE_3 0xD0578 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_0 0xD057C + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_1 0xD0580 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_2 0xD0584 + +#define mmMME_SHADOW_0_C_SPATIAL_START_OFFSET_3 0xD0588 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_0 0xD058C + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_1 0xD0590 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_2 0xD0594 + +#define mmMME_SHADOW_0_C_SPATIAL_STRIDE_3 0xD0598 + +#define mmMME_SHADOW_0_C_SPATIAL_SIZE_MINUS_1 0xD059C + +#define mmMME_SHADOW_0_SYNC_OBJECT_MESSAGE 0xD05A0 + +#define mmMME_SHADOW_0_E_PADDING_VALUE_A 0xD05A4 + +#define mmMME_SHADOW_0_E_NUM_ITERATION_MINUS_1 0xD05A8 + +#define mmMME_SHADOW_0_E_BUBBLES_PER_SPLIT 0xD05AC + +#define mmMME_SHADOW_1_STATUS 0xD0600 + +#define mmMME_SHADOW_1_A_BASE_ADDR_HIGH 0xD0608 + +#define mmMME_SHADOW_1_B_BASE_ADDR_HIGH 0xD060C + +#define mmMME_SHADOW_1_CIN_BASE_ADDR_HIGH 0xD0610 + +#define mmMME_SHADOW_1_COUT_BASE_ADDR_HIGH 0xD0614 + +#define mmMME_SHADOW_1_BIAS_BASE_ADDR_HIGH 0xD0618 + +#define mmMME_SHADOW_1_A_BASE_ADDR_LOW 0xD061C + +#define mmMME_SHADOW_1_B_BASE_ADDR_LOW 0xD0620 + +#define mmMME_SHADOW_1_CIN_BASE_ADDR_LOW 0xD0624 + +#define mmMME_SHADOW_1_COUT_BASE_ADDR_LOW 0xD0628 + +#define mmMME_SHADOW_1_BIAS_BASE_ADDR_LOW 0xD062C + +#define mmMME_SHADOW_1_HEADER 0xD0630 + +#define mmMME_SHADOW_1_KERNEL_SIZE_MINUS_1 0xD0634 + +#define mmMME_SHADOW_1_ASSOCIATED_DIMS_0 0xD0638 + +#define mmMME_SHADOW_1_ASSOCIATED_DIMS_1 0xD063C + +#define mmMME_SHADOW_1_COUT_SCALE 0xD0640 + +#define mmMME_SHADOW_1_CIN_SCALE 0xD0644 + +#define mmMME_SHADOW_1_GEMMLOWP_ZP 0xD0648 + +#define mmMME_SHADOW_1_GEMMLOWP_EXPONENT 0xD064C + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_0 0xD0650 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_1 0xD0654 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_2 0xD0658 + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_3 0xD065C + +#define mmMME_SHADOW_1_A_ROI_BASE_OFFSET_4 0xD0660 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_0 0xD0664 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_1 0xD0668 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_2 0xD066C + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_3 0xD0670 + +#define mmMME_SHADOW_1_A_VALID_ELEMENTS_4 0xD0674 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_0 0xD0678 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_1 0xD067C + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_2 0xD0680 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_3 0xD0684 + +#define mmMME_SHADOW_1_A_LOOP_STRIDE_4 0xD0688 + +#define mmMME_SHADOW_1_A_ROI_SIZE_0 0xD068C + +#define mmMME_SHADOW_1_A_ROI_SIZE_1 0xD0690 + +#define mmMME_SHADOW_1_A_ROI_SIZE_2 0xD0694 + +#define mmMME_SHADOW_1_A_ROI_SIZE_3 0xD0698 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_0 0xD069C + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_1 0xD06A0 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_2 0xD06A4 + +#define mmMME_SHADOW_1_A_SPATIAL_START_OFFSET_3 0xD06A8 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_0 0xD06AC + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_1 0xD06B0 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_2 0xD06B4 + +#define mmMME_SHADOW_1_A_SPATIAL_STRIDE_3 0xD06B8 + +#define mmMME_SHADOW_1_A_SPATIAL_SIZE_MINUS_1 0xD06BC + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_0 0xD06C0 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_1 0xD06C4 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_2 0xD06C8 + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_3 0xD06CC + +#define mmMME_SHADOW_1_B_ROI_BASE_OFFSET_4 0xD06D0 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_0 0xD06D4 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_1 0xD06D8 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_2 0xD06DC + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_3 0xD06E0 + +#define mmMME_SHADOW_1_B_VALID_ELEMENTS_4 0xD06E4 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_0 0xD06E8 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_1 0xD06EC + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_2 0xD06F0 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_3 0xD06F4 + +#define mmMME_SHADOW_1_B_LOOP_STRIDE_4 0xD06F8 + +#define mmMME_SHADOW_1_B_ROI_SIZE_0 0xD06FC + +#define mmMME_SHADOW_1_B_ROI_SIZE_1 0xD0700 + +#define mmMME_SHADOW_1_B_ROI_SIZE_2 0xD0704 + +#define mmMME_SHADOW_1_B_ROI_SIZE_3 0xD0708 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_0 0xD070C + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_1 0xD0710 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_2 0xD0714 + +#define mmMME_SHADOW_1_B_SPATIAL_START_OFFSET_3 0xD0718 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_0 0xD071C + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_1 0xD0720 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_2 0xD0724 + +#define mmMME_SHADOW_1_B_SPATIAL_STRIDE_3 0xD0728 + +#define mmMME_SHADOW_1_B_SPATIAL_SIZE_MINUS_1 0xD072C + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_0 0xD0730 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_1 0xD0734 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_2 0xD0738 + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_3 0xD073C + +#define mmMME_SHADOW_1_C_ROI_BASE_OFFSET_4 0xD0740 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_0 0xD0744 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_1 0xD0748 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_2 0xD074C + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_3 0xD0750 + +#define mmMME_SHADOW_1_C_VALID_ELEMENTS_4 0xD0754 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_0 0xD0758 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_1 0xD075C + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_2 0xD0760 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_3 0xD0764 + +#define mmMME_SHADOW_1_C_LOOP_STRIDE_4 0xD0768 + +#define mmMME_SHADOW_1_C_ROI_SIZE_0 0xD076C + +#define mmMME_SHADOW_1_C_ROI_SIZE_1 0xD0770 + +#define mmMME_SHADOW_1_C_ROI_SIZE_2 0xD0774 + +#define mmMME_SHADOW_1_C_ROI_SIZE_3 0xD0778 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_0 0xD077C + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_1 0xD0780 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_2 0xD0784 + +#define mmMME_SHADOW_1_C_SPATIAL_START_OFFSET_3 0xD0788 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_0 0xD078C + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_1 0xD0790 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_2 0xD0794 + +#define mmMME_SHADOW_1_C_SPATIAL_STRIDE_3 0xD0798 + +#define mmMME_SHADOW_1_C_SPATIAL_SIZE_MINUS_1 0xD079C + +#define mmMME_SHADOW_1_SYNC_OBJECT_MESSAGE 0xD07A0 + +#define mmMME_SHADOW_1_E_PADDING_VALUE_A 0xD07A4 + +#define mmMME_SHADOW_1_E_NUM_ITERATION_MINUS_1 0xD07A8 + +#define mmMME_SHADOW_1_E_BUBBLES_PER_SPLIT 0xD07AC + +#define mmMME_SHADOW_2_STATUS 0xD0800 + +#define mmMME_SHADOW_2_A_BASE_ADDR_HIGH 0xD0808 + +#define mmMME_SHADOW_2_B_BASE_ADDR_HIGH 0xD080C + +#define mmMME_SHADOW_2_CIN_BASE_ADDR_HIGH 0xD0810 + +#define mmMME_SHADOW_2_COUT_BASE_ADDR_HIGH 0xD0814 + +#define mmMME_SHADOW_2_BIAS_BASE_ADDR_HIGH 0xD0818 + +#define mmMME_SHADOW_2_A_BASE_ADDR_LOW 0xD081C + +#define mmMME_SHADOW_2_B_BASE_ADDR_LOW 0xD0820 + +#define mmMME_SHADOW_2_CIN_BASE_ADDR_LOW 0xD0824 + +#define mmMME_SHADOW_2_COUT_BASE_ADDR_LOW 0xD0828 + +#define mmMME_SHADOW_2_BIAS_BASE_ADDR_LOW 0xD082C + +#define mmMME_SHADOW_2_HEADER 0xD0830 + +#define mmMME_SHADOW_2_KERNEL_SIZE_MINUS_1 0xD0834 + +#define mmMME_SHADOW_2_ASSOCIATED_DIMS_0 0xD0838 + +#define mmMME_SHADOW_2_ASSOCIATED_DIMS_1 0xD083C + +#define mmMME_SHADOW_2_COUT_SCALE 0xD0840 + +#define mmMME_SHADOW_2_CIN_SCALE 0xD0844 + +#define mmMME_SHADOW_2_GEMMLOWP_ZP 0xD0848 + +#define mmMME_SHADOW_2_GEMMLOWP_EXPONENT 0xD084C + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_0 0xD0850 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_1 0xD0854 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_2 0xD0858 + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_3 0xD085C + +#define mmMME_SHADOW_2_A_ROI_BASE_OFFSET_4 0xD0860 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_0 0xD0864 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_1 0xD0868 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_2 0xD086C + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_3 0xD0870 + +#define mmMME_SHADOW_2_A_VALID_ELEMENTS_4 0xD0874 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_0 0xD0878 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_1 0xD087C + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_2 0xD0880 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_3 0xD0884 + +#define mmMME_SHADOW_2_A_LOOP_STRIDE_4 0xD0888 + +#define mmMME_SHADOW_2_A_ROI_SIZE_0 0xD088C + +#define mmMME_SHADOW_2_A_ROI_SIZE_1 0xD0890 + +#define mmMME_SHADOW_2_A_ROI_SIZE_2 0xD0894 + +#define mmMME_SHADOW_2_A_ROI_SIZE_3 0xD0898 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_0 0xD089C + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_1 0xD08A0 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_2 0xD08A4 + +#define mmMME_SHADOW_2_A_SPATIAL_START_OFFSET_3 0xD08A8 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_0 0xD08AC + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_1 0xD08B0 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_2 0xD08B4 + +#define mmMME_SHADOW_2_A_SPATIAL_STRIDE_3 0xD08B8 + +#define mmMME_SHADOW_2_A_SPATIAL_SIZE_MINUS_1 0xD08BC + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_0 0xD08C0 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_1 0xD08C4 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_2 0xD08C8 + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_3 0xD08CC + +#define mmMME_SHADOW_2_B_ROI_BASE_OFFSET_4 0xD08D0 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_0 0xD08D4 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_1 0xD08D8 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_2 0xD08DC + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_3 0xD08E0 + +#define mmMME_SHADOW_2_B_VALID_ELEMENTS_4 0xD08E4 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_0 0xD08E8 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_1 0xD08EC + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_2 0xD08F0 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_3 0xD08F4 + +#define mmMME_SHADOW_2_B_LOOP_STRIDE_4 0xD08F8 + +#define mmMME_SHADOW_2_B_ROI_SIZE_0 0xD08FC + +#define mmMME_SHADOW_2_B_ROI_SIZE_1 0xD0900 + +#define mmMME_SHADOW_2_B_ROI_SIZE_2 0xD0904 + +#define mmMME_SHADOW_2_B_ROI_SIZE_3 0xD0908 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_0 0xD090C + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_1 0xD0910 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_2 0xD0914 + +#define mmMME_SHADOW_2_B_SPATIAL_START_OFFSET_3 0xD0918 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_0 0xD091C + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_1 0xD0920 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_2 0xD0924 + +#define mmMME_SHADOW_2_B_SPATIAL_STRIDE_3 0xD0928 + +#define mmMME_SHADOW_2_B_SPATIAL_SIZE_MINUS_1 0xD092C + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_0 0xD0930 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_1 0xD0934 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_2 0xD0938 + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_3 0xD093C + +#define mmMME_SHADOW_2_C_ROI_BASE_OFFSET_4 0xD0940 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_0 0xD0944 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_1 0xD0948 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_2 0xD094C + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_3 0xD0950 + +#define mmMME_SHADOW_2_C_VALID_ELEMENTS_4 0xD0954 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_0 0xD0958 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_1 0xD095C + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_2 0xD0960 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_3 0xD0964 + +#define mmMME_SHADOW_2_C_LOOP_STRIDE_4 0xD0968 + +#define mmMME_SHADOW_2_C_ROI_SIZE_0 0xD096C + +#define mmMME_SHADOW_2_C_ROI_SIZE_1 0xD0970 + +#define mmMME_SHADOW_2_C_ROI_SIZE_2 0xD0974 + +#define mmMME_SHADOW_2_C_ROI_SIZE_3 0xD0978 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_0 0xD097C + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_1 0xD0980 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_2 0xD0984 + +#define mmMME_SHADOW_2_C_SPATIAL_START_OFFSET_3 0xD0988 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_0 0xD098C + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_1 0xD0990 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_2 0xD0994 + +#define mmMME_SHADOW_2_C_SPATIAL_STRIDE_3 0xD0998 + +#define mmMME_SHADOW_2_C_SPATIAL_SIZE_MINUS_1 0xD099C + +#define mmMME_SHADOW_2_SYNC_OBJECT_MESSAGE 0xD09A0 + +#define mmMME_SHADOW_2_E_PADDING_VALUE_A 0xD09A4 + +#define mmMME_SHADOW_2_E_NUM_ITERATION_MINUS_1 0xD09A8 + +#define mmMME_SHADOW_2_E_BUBBLES_PER_SPLIT 0xD09AC + +#define mmMME_SHADOW_3_STATUS 0xD0A00 + +#define mmMME_SHADOW_3_A_BASE_ADDR_HIGH 0xD0A08 + +#define mmMME_SHADOW_3_B_BASE_ADDR_HIGH 0xD0A0C + +#define mmMME_SHADOW_3_CIN_BASE_ADDR_HIGH 0xD0A10 + +#define mmMME_SHADOW_3_COUT_BASE_ADDR_HIGH 0xD0A14 + +#define mmMME_SHADOW_3_BIAS_BASE_ADDR_HIGH 0xD0A18 + +#define mmMME_SHADOW_3_A_BASE_ADDR_LOW 0xD0A1C + +#define mmMME_SHADOW_3_B_BASE_ADDR_LOW 0xD0A20 + +#define mmMME_SHADOW_3_CIN_BASE_ADDR_LOW 0xD0A24 + +#define mmMME_SHADOW_3_COUT_BASE_ADDR_LOW 0xD0A28 + +#define mmMME_SHADOW_3_BIAS_BASE_ADDR_LOW 0xD0A2C + +#define mmMME_SHADOW_3_HEADER 0xD0A30 + +#define mmMME_SHADOW_3_KERNEL_SIZE_MINUS_1 0xD0A34 + +#define mmMME_SHADOW_3_ASSOCIATED_DIMS_0 0xD0A38 + +#define mmMME_SHADOW_3_ASSOCIATED_DIMS_1 0xD0A3C + +#define mmMME_SHADOW_3_COUT_SCALE 0xD0A40 + +#define mmMME_SHADOW_3_CIN_SCALE 0xD0A44 + +#define mmMME_SHADOW_3_GEMMLOWP_ZP 0xD0A48 + +#define mmMME_SHADOW_3_GEMMLOWP_EXPONENT 0xD0A4C + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_0 0xD0A50 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_1 0xD0A54 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_2 0xD0A58 + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_3 0xD0A5C + +#define mmMME_SHADOW_3_A_ROI_BASE_OFFSET_4 0xD0A60 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_0 0xD0A64 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_1 0xD0A68 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_2 0xD0A6C + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_3 0xD0A70 + +#define mmMME_SHADOW_3_A_VALID_ELEMENTS_4 0xD0A74 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_0 0xD0A78 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_1 0xD0A7C + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_2 0xD0A80 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_3 0xD0A84 + +#define mmMME_SHADOW_3_A_LOOP_STRIDE_4 0xD0A88 + +#define mmMME_SHADOW_3_A_ROI_SIZE_0 0xD0A8C + +#define mmMME_SHADOW_3_A_ROI_SIZE_1 0xD0A90 + +#define mmMME_SHADOW_3_A_ROI_SIZE_2 0xD0A94 + +#define mmMME_SHADOW_3_A_ROI_SIZE_3 0xD0A98 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_0 0xD0A9C + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_1 0xD0AA0 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_2 0xD0AA4 + +#define mmMME_SHADOW_3_A_SPATIAL_START_OFFSET_3 0xD0AA8 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_0 0xD0AAC + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_1 0xD0AB0 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_2 0xD0AB4 + +#define mmMME_SHADOW_3_A_SPATIAL_STRIDE_3 0xD0AB8 + +#define mmMME_SHADOW_3_A_SPATIAL_SIZE_MINUS_1 0xD0ABC + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_0 0xD0AC0 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_1 0xD0AC4 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_2 0xD0AC8 + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_3 0xD0ACC + +#define mmMME_SHADOW_3_B_ROI_BASE_OFFSET_4 0xD0AD0 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_0 0xD0AD4 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_1 0xD0AD8 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_2 0xD0ADC + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_3 0xD0AE0 + +#define mmMME_SHADOW_3_B_VALID_ELEMENTS_4 0xD0AE4 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_0 0xD0AE8 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_1 0xD0AEC + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_2 0xD0AF0 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_3 0xD0AF4 + +#define mmMME_SHADOW_3_B_LOOP_STRIDE_4 0xD0AF8 + +#define mmMME_SHADOW_3_B_ROI_SIZE_0 0xD0AFC + +#define mmMME_SHADOW_3_B_ROI_SIZE_1 0xD0B00 + +#define mmMME_SHADOW_3_B_ROI_SIZE_2 0xD0B04 + +#define mmMME_SHADOW_3_B_ROI_SIZE_3 0xD0B08 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_0 0xD0B0C + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_1 0xD0B10 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_2 0xD0B14 + +#define mmMME_SHADOW_3_B_SPATIAL_START_OFFSET_3 0xD0B18 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_0 0xD0B1C + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_1 0xD0B20 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_2 0xD0B24 + +#define mmMME_SHADOW_3_B_SPATIAL_STRIDE_3 0xD0B28 + +#define mmMME_SHADOW_3_B_SPATIAL_SIZE_MINUS_1 0xD0B2C + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_0 0xD0B30 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_1 0xD0B34 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_2 0xD0B38 + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_3 0xD0B3C + +#define mmMME_SHADOW_3_C_ROI_BASE_OFFSET_4 0xD0B40 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_0 0xD0B44 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_1 0xD0B48 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_2 0xD0B4C + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_3 0xD0B50 + +#define mmMME_SHADOW_3_C_VALID_ELEMENTS_4 0xD0B54 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_0 0xD0B58 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_1 0xD0B5C + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_2 0xD0B60 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_3 0xD0B64 + +#define mmMME_SHADOW_3_C_LOOP_STRIDE_4 0xD0B68 + +#define mmMME_SHADOW_3_C_ROI_SIZE_0 0xD0B6C + +#define mmMME_SHADOW_3_C_ROI_SIZE_1 0xD0B70 + +#define mmMME_SHADOW_3_C_ROI_SIZE_2 0xD0B74 + +#define mmMME_SHADOW_3_C_ROI_SIZE_3 0xD0B78 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_0 0xD0B7C + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_1 0xD0B80 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_2 0xD0B84 + +#define mmMME_SHADOW_3_C_SPATIAL_START_OFFSET_3 0xD0B88 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_0 0xD0B8C + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_1 0xD0B90 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_2 0xD0B94 + +#define mmMME_SHADOW_3_C_SPATIAL_STRIDE_3 0xD0B98 + +#define mmMME_SHADOW_3_C_SPATIAL_SIZE_MINUS_1 0xD0B9C + +#define mmMME_SHADOW_3_SYNC_OBJECT_MESSAGE 0xD0BA0 + +#define mmMME_SHADOW_3_E_PADDING_VALUE_A 0xD0BA4 + +#define mmMME_SHADOW_3_E_NUM_ITERATION_MINUS_1 0xD0BA8 + +#define mmMME_SHADOW_3_E_BUBBLES_PER_SPLIT 0xD0BAC + +#endif /* ASIC_REG_MME_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h new file mode 100644 index 000000000..c3e69062b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_MASKS_H_ +#define ASIC_REG_MMU_MASKS_H_ + +/* + ***************************************** + * MMU (Prototype: MMU) + ***************************************** + */ + +/* MMU_INPUT_FIFO_THRESHOLD */ +#define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0 +#define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7 +#define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 4 +#define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70 +#define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 8 +#define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700 +#define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 12 +#define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000 +#define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 16 +#define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000 +#define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 20 +#define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000 +#define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 24 +#define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000 + +/* MMU_MMU_ENABLE */ +#define MMU_MMU_ENABLE_R_SHIFT 0 +#define MMU_MMU_ENABLE_R_MASK 0x1 + +/* MMU_FORCE_ORDERING */ +#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0 +#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1 +#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 1 +#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2 +#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 2 +#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4 +#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 3 +#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8 +#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 4 +#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10 +#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 5 +#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20 +#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 6 +#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40 +#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 8 +#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100 +#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 9 +#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200 +#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 10 +#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400 +#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 11 +#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800 +#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 12 +#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000 +#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 13 +#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000 +#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 14 +#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000 + +/* MMU_FEATURE_ENABLE */ +#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 +#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 +#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 +#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 +#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 +#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 +#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 +#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 +#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 +#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 +#define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 +#define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 + +/* MMU_VA_ORDERING_MASK_31_7 */ +#define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0 +#define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF + +/* MMU_VA_ORDERING_MASK_49_32 */ +#define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0 +#define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF + +/* MMU_LOG2_DDR_SIZE */ +#define MMU_LOG2_DDR_SIZE_R_SHIFT 0 +#define MMU_LOG2_DDR_SIZE_R_MASK 0xFF + +/* MMU_SCRAMBLER */ +#define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 +#define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F +#define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 +#define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 +#define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 +#define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 + +/* MMU_MEM_INIT_BUSY */ +#define MMU_MEM_INIT_BUSY_DATA_SHIFT 0 +#define MMU_MEM_INIT_BUSY_DATA_MASK 0x3 +#define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 +#define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 +#define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 +#define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 + +/* MMU_SPI_MASK */ +#define MMU_SPI_MASK_R_SHIFT 0 +#define MMU_SPI_MASK_R_MASK 0xFF + +/* MMU_SPI_CAUSE */ +#define MMU_SPI_CAUSE_R_SHIFT 0 +#define MMU_SPI_CAUSE_R_MASK 0xFF + +/* MMU_PAGE_ERROR_CAPTURE */ +#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0 +#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 +#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_PAGE_ERROR_CAPTURE_VA */ +#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* MMU_ACCESS_ERROR_CAPTURE */ +#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0 +#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 +#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_ACCESS_ERROR_CAPTURE_VA */ +#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_MMU_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h new file mode 100644 index 000000000..7ec81f120 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_REGS_H_ +#define ASIC_REG_MMU_REGS_H_ + +/* + ***************************************** + * MMU (Prototype: MMU) + ***************************************** + */ + +#define mmMMU_INPUT_FIFO_THRESHOLD 0x480000 + +#define mmMMU_MMU_ENABLE 0x48000C + +#define mmMMU_FORCE_ORDERING 0x480010 + +#define mmMMU_FEATURE_ENABLE 0x480014 + +#define mmMMU_VA_ORDERING_MASK_31_7 0x480018 + +#define mmMMU_VA_ORDERING_MASK_49_32 0x48001C + +#define mmMMU_LOG2_DDR_SIZE 0x480020 + +#define mmMMU_SCRAMBLER 0x480024 + +#define mmMMU_MEM_INIT_BUSY 0x480028 + +#define mmMMU_SPI_MASK 0x48002C + +#define mmMMU_SPI_CAUSE 0x480030 + +#define mmMMU_PAGE_ERROR_CAPTURE 0x480034 + +#define mmMMU_PAGE_ERROR_CAPTURE_VA 0x480038 + +#define mmMMU_ACCESS_ERROR_CAPTURE 0x48003C + +#define mmMMU_ACCESS_ERROR_CAPTURE_VA 0x480040 + +#endif /* ASIC_REG_MMU_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h new file mode 100644 index 000000000..ceb59f2e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCI_NRTR_MASKS_H_ +#define ASIC_REG_PCI_NRTR_MASKS_H_ + +/* + ***************************************** + * PCI_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* PCI_NRTR_HBW_MAX_CRED */ +#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define PCI_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define PCI_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* PCI_NRTR_LBW_MAX_CRED */ +#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define PCI_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define PCI_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* PCI_NRTR_DBG_E_ARB */ +#define PCI_NRTR_DBG_E_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_E_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_E_ARB_S_SHIFT 8 +#define PCI_NRTR_DBG_E_ARB_S_MASK 0x700 +#define PCI_NRTR_DBG_E_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_E_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_W_ARB */ +#define PCI_NRTR_DBG_W_ARB_E_SHIFT 0 +#define PCI_NRTR_DBG_W_ARB_E_MASK 0x7 +#define PCI_NRTR_DBG_W_ARB_S_SHIFT 8 +#define PCI_NRTR_DBG_W_ARB_S_MASK 0x700 +#define PCI_NRTR_DBG_W_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_W_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_N_ARB */ +#define PCI_NRTR_DBG_N_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_N_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_N_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_N_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_N_ARB_S_SHIFT 16 +#define PCI_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define PCI_NRTR_DBG_N_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_S_ARB */ +#define PCI_NRTR_DBG_S_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_S_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_S_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_S_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_S_ARB_N_SHIFT 16 +#define PCI_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define PCI_NRTR_DBG_S_ARB_L_SHIFT 24 +#define PCI_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* PCI_NRTR_DBG_L_ARB */ +#define PCI_NRTR_DBG_L_ARB_W_SHIFT 0 +#define PCI_NRTR_DBG_L_ARB_W_MASK 0x7 +#define PCI_NRTR_DBG_L_ARB_E_SHIFT 8 +#define PCI_NRTR_DBG_L_ARB_E_MASK 0x700 +#define PCI_NRTR_DBG_L_ARB_S_SHIFT 16 +#define PCI_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define PCI_NRTR_DBG_L_ARB_N_SHIFT 24 +#define PCI_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* PCI_NRTR_DBG_E_ARB_MAX */ +#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_W_ARB_MAX */ +#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_N_ARB_MAX */ +#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_S_ARB_MAX */ +#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_DBG_L_ARB_MAX */ +#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* PCI_NRTR_SPLIT_COEF */ +#define PCI_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_CFG */ +#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define PCI_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define PCI_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* PCI_NRTR_SPLIT_RD_SAT */ +#define PCI_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_RD_RST_TOKEN */ +#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_RD_TIMEOUT */ +#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_SPLIT_WR_SAT */ +#define PCI_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* PCI_NRTR_WPLIT_WR_TST_TOLEN */ +#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* PCI_NRTR_SPLIT_WR_TIMEOUT */ +#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_HIT */ +#define PCI_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* PCI_NRTR_HBW_RANGE_MASK_L */ +#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_MASK_H */ +#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* PCI_NRTR_HBW_RANGE_BASE_L */ +#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* PCI_NRTR_HBW_RANGE_BASE_H */ +#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* PCI_NRTR_LBW_RANGE_HIT */ +#define PCI_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* PCI_NRTR_LBW_RANGE_MASK */ +#define PCI_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* PCI_NRTR_LBW_RANGE_BASE */ +#define PCI_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define PCI_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* PCI_NRTR_RGLTR */ +#define PCI_NRTR_RGLTR_WR_EN_SHIFT 0 +#define PCI_NRTR_RGLTR_WR_EN_MASK 0x1 +#define PCI_NRTR_RGLTR_RD_EN_SHIFT 4 +#define PCI_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* PCI_NRTR_RGLTR_WR_RESULT */ +#define PCI_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define PCI_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* PCI_NRTR_RGLTR_RD_RESULT */ +#define PCI_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define PCI_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* PCI_NRTR_SCRAMB_EN */ +#define PCI_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define PCI_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* PCI_NRTR_NON_LIN_SCRAMB */ +#define PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define PCI_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_PCI_NRTR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h new file mode 100644 index 000000000..dd067f301 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCI_NRTR_REGS_H_ +#define ASIC_REG_PCI_NRTR_REGS_H_ + +/* + ***************************************** + * PCI_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmPCI_NRTR_HBW_MAX_CRED 0x100 + +#define mmPCI_NRTR_LBW_MAX_CRED 0x120 + +#define mmPCI_NRTR_DBG_E_ARB 0x300 + +#define mmPCI_NRTR_DBG_W_ARB 0x304 + +#define mmPCI_NRTR_DBG_N_ARB 0x308 + +#define mmPCI_NRTR_DBG_S_ARB 0x30C + +#define mmPCI_NRTR_DBG_L_ARB 0x310 + +#define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 + +#define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 + +#define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 + +#define mmPCI_NRTR_DBG_S_ARB_MAX 0x32C + +#define mmPCI_NRTR_DBG_L_ARB_MAX 0x330 + +#define mmPCI_NRTR_SPLIT_COEF_0 0x400 + +#define mmPCI_NRTR_SPLIT_COEF_1 0x404 + +#define mmPCI_NRTR_SPLIT_COEF_2 0x408 + +#define mmPCI_NRTR_SPLIT_COEF_3 0x40C + +#define mmPCI_NRTR_SPLIT_COEF_4 0x410 + +#define mmPCI_NRTR_SPLIT_COEF_5 0x414 + +#define mmPCI_NRTR_SPLIT_COEF_6 0x418 + +#define mmPCI_NRTR_SPLIT_COEF_7 0x41C + +#define mmPCI_NRTR_SPLIT_COEF_8 0x420 + +#define mmPCI_NRTR_SPLIT_COEF_9 0x424 + +#define mmPCI_NRTR_SPLIT_CFG 0x440 + +#define mmPCI_NRTR_SPLIT_RD_SAT 0x444 + +#define mmPCI_NRTR_SPLIT_RD_RST_TOKEN 0x448 + +#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0 0x44C + +#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1 0x450 + +#define mmPCI_NRTR_SPLIT_WR_SAT 0x454 + +#define mmPCI_NRTR_WPLIT_WR_TST_TOLEN 0x458 + +#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0 0x45C + +#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1 0x460 + +#define mmPCI_NRTR_HBW_RANGE_HIT 0x470 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_0 0x480 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_1 0x484 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_2 0x488 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_3 0x48C + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_4 0x490 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_5 0x494 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_6 0x498 + +#define mmPCI_NRTR_HBW_RANGE_MASK_L_7 0x49C + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_0 0x4A0 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_1 0x4A4 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_2 0x4A8 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_3 0x4AC + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_4 0x4B0 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_5 0x4B4 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_6 0x4B8 + +#define mmPCI_NRTR_HBW_RANGE_MASK_H_7 0x4BC + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_0 0x4C0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_1 0x4C4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_2 0x4C8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_3 0x4CC + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_4 0x4D0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_5 0x4D4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_6 0x4D8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_L_7 0x4DC + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_0 0x4E0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_1 0x4E4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_2 0x4E8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_3 0x4EC + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_4 0x4F0 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_5 0x4F4 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_6 0x4F8 + +#define mmPCI_NRTR_HBW_RANGE_BASE_H_7 0x4FC + +#define mmPCI_NRTR_LBW_RANGE_HIT 0x500 + +#define mmPCI_NRTR_LBW_RANGE_MASK_0 0x510 + +#define mmPCI_NRTR_LBW_RANGE_MASK_1 0x514 + +#define mmPCI_NRTR_LBW_RANGE_MASK_2 0x518 + +#define mmPCI_NRTR_LBW_RANGE_MASK_3 0x51C + +#define mmPCI_NRTR_LBW_RANGE_MASK_4 0x520 + +#define mmPCI_NRTR_LBW_RANGE_MASK_5 0x524 + +#define mmPCI_NRTR_LBW_RANGE_MASK_6 0x528 + +#define mmPCI_NRTR_LBW_RANGE_MASK_7 0x52C + +#define mmPCI_NRTR_LBW_RANGE_MASK_8 0x530 + +#define mmPCI_NRTR_LBW_RANGE_MASK_9 0x534 + +#define mmPCI_NRTR_LBW_RANGE_MASK_10 0x538 + +#define mmPCI_NRTR_LBW_RANGE_MASK_11 0x53C + +#define mmPCI_NRTR_LBW_RANGE_MASK_12 0x540 + +#define mmPCI_NRTR_LBW_RANGE_MASK_13 0x544 + +#define mmPCI_NRTR_LBW_RANGE_MASK_14 0x548 + +#define mmPCI_NRTR_LBW_RANGE_MASK_15 0x54C + +#define mmPCI_NRTR_LBW_RANGE_BASE_0 0x550 + +#define mmPCI_NRTR_LBW_RANGE_BASE_1 0x554 + +#define mmPCI_NRTR_LBW_RANGE_BASE_2 0x558 + +#define mmPCI_NRTR_LBW_RANGE_BASE_3 0x55C + +#define mmPCI_NRTR_LBW_RANGE_BASE_4 0x560 + +#define mmPCI_NRTR_LBW_RANGE_BASE_5 0x564 + +#define mmPCI_NRTR_LBW_RANGE_BASE_6 0x568 + +#define mmPCI_NRTR_LBW_RANGE_BASE_7 0x56C + +#define mmPCI_NRTR_LBW_RANGE_BASE_8 0x570 + +#define mmPCI_NRTR_LBW_RANGE_BASE_9 0x574 + +#define mmPCI_NRTR_LBW_RANGE_BASE_10 0x578 + +#define mmPCI_NRTR_LBW_RANGE_BASE_11 0x57C + +#define mmPCI_NRTR_LBW_RANGE_BASE_12 0x580 + +#define mmPCI_NRTR_LBW_RANGE_BASE_13 0x584 + +#define mmPCI_NRTR_LBW_RANGE_BASE_14 0x588 + +#define mmPCI_NRTR_LBW_RANGE_BASE_15 0x58C + +#define mmPCI_NRTR_RGLTR 0x590 + +#define mmPCI_NRTR_RGLTR_WR_RESULT 0x594 + +#define mmPCI_NRTR_RGLTR_RD_RESULT 0x598 + +#define mmPCI_NRTR_SCRAMB_EN 0x600 + +#define mmPCI_NRTR_NON_LIN_SCRAMB 0x604 + +#endif /* ASIC_REG_PCI_NRTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h new file mode 100644 index 000000000..35b1d8ac6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_AUX_REGS_H_ +#define ASIC_REG_PCIE_AUX_REGS_H_ + +/* + ***************************************** + * PCIE_AUX (Prototype: PCIE_AUX) + ***************************************** + */ + +#define mmPCIE_AUX_APB_TIMEOUT 0xC07004 + +#define mmPCIE_AUX_PHY_INIT 0xC07100 + +#define mmPCIE_AUX_LTR_MAX_LATENCY 0xC07138 + +#define mmPCIE_AUX_BAR0_START_L 0xC07160 + +#define mmPCIE_AUX_BAR0_START_H 0xC07164 + +#define mmPCIE_AUX_BAR1_START 0xC07168 + +#define mmPCIE_AUX_BAR2_START_L 0xC0716C + +#define mmPCIE_AUX_BAR2_START_H 0xC07170 + +#define mmPCIE_AUX_BAR3_START 0xC07174 + +#define mmPCIE_AUX_BAR4_START_L 0xC07178 + +#define mmPCIE_AUX_BAR4_START_H 0xC0717C + +#define mmPCIE_AUX_BAR5_START 0xC07180 + +#define mmPCIE_AUX_BAR0_LIMIT_L 0xC07184 + +#define mmPCIE_AUX_BAR0_LIMIT_H 0xC07188 + +#define mmPCIE_AUX_BAR1_LIMIT 0xC0718C + +#define mmPCIE_AUX_BAR2_LIMIT_L 0xC07190 + +#define mmPCIE_AUX_BAR2_LIMIT_H 0xC07194 + +#define mmPCIE_AUX_BAR3_LIMIT 0xC07198 + +#define mmPCIE_AUX_BAR4_LIMIT_L 0xC0719C + +#define mmPCIE_AUX_BAR4_LIMIT_H 0xC07200 + +#define mmPCIE_AUX_BAR5_LIMIT 0xC07204 + +#define mmPCIE_AUX_BUS_MASTER_EN 0xC07208 + +#define mmPCIE_AUX_MEM_SPACE_EN 0xC0720C + +#define mmPCIE_AUX_MAX_RD_REQ_SIZE 0xC07210 + +#define mmPCIE_AUX_MAX_PAYLOAD_SIZE 0xC07214 + +#define mmPCIE_AUX_EXT_TAG_EN 0xC07218 + +#define mmPCIE_AUX_RCB 0xC0721C + +#define mmPCIE_AUX_PM_NO_SOFT_RST 0xC07220 + +#define mmPCIE_AUX_PBUS_NUM 0xC07224 + +#define mmPCIE_AUX_PBUS_DEV_NUM 0xC07228 + +#define mmPCIE_AUX_NO_SNOOP_EN 0xC0722C + +#define mmPCIE_AUX_RELAX_ORDER_EN 0xC07230 + +#define mmPCIE_AUX_HP_SLOT_CTRL_ACCESS 0xC07234 + +#define mmPCIE_AUX_DLL_STATE_CHGED_EN 0xC07238 + +#define mmPCIE_AUX_CMP_CPLED_INT_EN 0xC0723C + +#define mmPCIE_AUX_HP_INT_EN 0xC07340 + +#define mmPCIE_AUX_PRE_DET_CHGEN_EN 0xC07344 + +#define mmPCIE_AUX_MRL_SENSOR_CHGED_EN 0xC07348 + +#define mmPCIE_AUX_PWR_FAULT_DET_EN 0xC0734C + +#define mmPCIE_AUX_ATTEN_BUTTON_PRESSED_EN 0xC07350 + +#define mmPCIE_AUX_PF_FLR_ACTIVE 0xC07360 + +#define mmPCIE_AUX_PF_FLR_DONE 0xC07364 + +#define mmPCIE_AUX_FLR_INT 0xC07390 + +#define mmPCIE_AUX_LTR_M_EN 0xC073B0 + +#define mmPCIE_AUX_LTSSM_EN 0xC07428 + +#define mmPCIE_AUX_SYS_INTR 0xC07440 + +#define mmPCIE_AUX_INT_DISABLE 0xC07444 + +#define mmPCIE_AUX_SMLH_LINK_UP 0xC07448 + +#define mmPCIE_AUX_PM_CURR_STATE 0xC07450 + +#define mmPCIE_AUX_RDLH_LINK_UP 0xC07458 + +#define mmPCIE_AUX_BRDG_SLV_XFER_PENDING 0xC0745C + +#define mmPCIE_AUX_BRDG_DBI_XFER_PENDING 0xC07460 + +#define mmPCIE_AUX_AUTO_SP_DIS 0xC07478 + +#define mmPCIE_AUX_DBI 0xC07490 + +#define mmPCIE_AUX_DBI_32 0xC07494 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_0 0xC074A4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_1 0xC074A8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_2 0xC074AC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_3 0xC074B0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_4 0xC074B4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_5 0xC074B8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_6 0xC074BC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_7 0xC074C0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_8 0xC074C4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_9 0xC074C8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_10 0xC074CC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_11 0xC074D0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_12 0xC074D4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_13 0xC074D8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_14 0xC074DC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_15 0xC074E0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_16 0xC074E4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_17 0xC074E8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_18 0xC074EC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_19 0xC074F0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_20 0xC074F4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_21 0xC074F8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_22 0xC074FC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_23 0xC07500 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_24 0xC07504 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_25 0xC07508 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_26 0xC0750C + +#define mmPCIE_AUX_DIAG_STATUS_BUS_27 0xC07510 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_28 0xC07514 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_0 0xC07640 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_1 0xC07644 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_2 0xC07648 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_3 0xC0764C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_4 0xC07650 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_5 0xC07654 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_6 0xC07658 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_7 0xC0765C + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_0 0xC07744 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_1 0xC07748 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_2 0xC0774C + +#define mmPCIE_AUX_APP_RAS_DES_TBA_CTRL 0xC07774 + +#define mmPCIE_AUX_PM_DSTATE 0xC07840 + +#define mmPCIE_AUX_PM_PME_EN 0xC07844 + +#define mmPCIE_AUX_PM_LINKST_IN_L0S 0xC07848 + +#define mmPCIE_AUX_PM_LINKST_IN_L1 0xC0784C + +#define mmPCIE_AUX_PM_LINKST_IN_L2 0xC07850 + +#define mmPCIE_AUX_PM_LINKST_L2_EXIT 0xC07854 + +#define mmPCIE_AUX_PM_STATUS 0xC07858 + +#define mmPCIE_AUX_APP_READY_ENTER_L23 0xC0785C + +#define mmPCIE_AUX_APP_XFER_PENDING 0xC07860 + +#define mmPCIE_AUX_APP_REQ_L1 0xC07930 + +#define mmPCIE_AUX_AUX_PM_EN 0xC07934 + +#define mmPCIE_AUX_APPS_PM_XMT_PME 0xC07938 + +#define mmPCIE_AUX_OUTBAND_PWRUP_CMD 0xC07940 + +#define mmPCIE_AUX_PERST 0xC079B8 + +#endif /* ASIC_REG_PCIE_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h new file mode 100644 index 000000000..d1e55aace --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h @@ -0,0 +1,306 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_WRAP_REGS_H_ +#define ASIC_REG_PCIE_WRAP_REGS_H_ + +/* + ***************************************** + * PCIE_WRAP (Prototype: PCIE_WRAP) + ***************************************** + */ + +#define mmPCIE_WRAP_PHY_RST_N 0xC01300 + +#define mmPCIE_WRAP_OUTSTAND_TRANS 0xC01400 + +#define mmPCIE_WRAP_MASK_REQ 0xC01404 + +#define mmPCIE_WRAP_IND_AWADDR_L 0xC01500 + +#define mmPCIE_WRAP_IND_AWADDR_H 0xC01504 + +#define mmPCIE_WRAP_IND_AWLEN 0xC01508 + +#define mmPCIE_WRAP_IND_AWSIZE 0xC0150C + +#define mmPCIE_WRAP_IND_AWBURST 0xC01510 + +#define mmPCIE_WRAP_IND_AWLOCK 0xC01514 + +#define mmPCIE_WRAP_IND_AWCACHE 0xC01518 + +#define mmPCIE_WRAP_IND_AWPROT 0xC0151C + +#define mmPCIE_WRAP_IND_AWVALID 0xC01520 + +#define mmPCIE_WRAP_IND_WDATA_0 0xC01524 + +#define mmPCIE_WRAP_IND_WDATA_1 0xC01528 + +#define mmPCIE_WRAP_IND_WDATA_2 0xC0152C + +#define mmPCIE_WRAP_IND_WDATA_3 0xC01530 + +#define mmPCIE_WRAP_IND_WSTRB 0xC01544 + +#define mmPCIE_WRAP_IND_WLAST 0xC01548 + +#define mmPCIE_WRAP_IND_WVALID 0xC0154C + +#define mmPCIE_WRAP_IND_BRESP 0xC01550 + +#define mmPCIE_WRAP_IND_BVALID 0xC01554 + +#define mmPCIE_WRAP_IND_ARADDR_0 0xC01558 + +#define mmPCIE_WRAP_IND_ARADDR_1 0xC0155C + +#define mmPCIE_WRAP_IND_ARLEN 0xC01560 + +#define mmPCIE_WRAP_IND_ARSIZE 0xC01564 + +#define mmPCIE_WRAP_IND_ARBURST 0xC01568 + +#define mmPCIE_WRAP_IND_ARLOCK 0xC0156C + +#define mmPCIE_WRAP_IND_ARCACHE 0xC01570 + +#define mmPCIE_WRAP_IND_ARPROT 0xC01574 + +#define mmPCIE_WRAP_IND_ARVALID 0xC01578 + +#define mmPCIE_WRAP_IND_RDATA_0 0xC0157C + +#define mmPCIE_WRAP_IND_RDATA_1 0xC01580 + +#define mmPCIE_WRAP_IND_RDATA_2 0xC01584 + +#define mmPCIE_WRAP_IND_RDATA_3 0xC01588 + +#define mmPCIE_WRAP_IND_RLAST 0xC0159C + +#define mmPCIE_WRAP_IND_RRESP 0xC015A0 + +#define mmPCIE_WRAP_IND_RVALID 0xC015A4 + +#define mmPCIE_WRAP_IND_AWMISC_INFO 0xC015A8 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_0 0xC015AC + +#define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_1 0xC015B0 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_P_TAG 0xC015B4 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_ATU_BYPAS 0xC015B8 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_FUNC_NUM 0xC015BC + +#define mmPCIE_WRAP_IND_AWMISC_INFO_VFUNC_ACT 0xC015C0 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_VFUNC_NUM 0xC015C4 + +#define mmPCIE_WRAP_IND_AWMISC_INFO_TLPPRFX 0xC015C8 + +#define mmPCIE_WRAP_IND_ARMISC_INFO 0xC015CC + +#define mmPCIE_WRAP_IND_ARMISC_INFO_TLPPRFX 0xC015D0 + +#define mmPCIE_WRAP_IND_ARMISC_INFO_ATU_BYP 0xC015D4 + +#define mmPCIE_WRAP_IND_ARMISC_INFO_FUNC_NUM 0xC015D8 + +#define mmPCIE_WRAP_IND_ARMISC_INFO_VFUNC_ACT 0xC015DC + +#define mmPCIE_WRAP_IND_ARMISC_INFO_VFUNC_NUM 0xC015E0 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO 0xC01800 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_0 0xC01804 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_1 0xC01808 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_P_TAG 0xC0180C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_ATU_BYPAS 0xC01810 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_FUNC_NUM 0xC01814 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_ACT 0xC01818 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_NUM 0xC0181C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_TLPPRFX 0xC01820 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO 0xC01824 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_TLPPRFX 0xC01828 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_ATU_BYP 0xC0182C + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_FUNC_NUM 0xC01830 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_ACT 0xC01834 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_NUM 0xC01838 + +#define mmPCIE_WRAP_MAX_QID 0xC01900 + +#define mmPCIE_WRAP_DB_BASE_ADDR_L_0 0xC01910 + +#define mmPCIE_WRAP_DB_BASE_ADDR_L_1 0xC01914 + +#define mmPCIE_WRAP_DB_BASE_ADDR_L_2 0xC01918 + +#define mmPCIE_WRAP_DB_BASE_ADDR_L_3 0xC0191C + +#define mmPCIE_WRAP_DB_BASE_ADDR_H_0 0xC01920 + +#define mmPCIE_WRAP_DB_BASE_ADDR_H_1 0xC01924 + +#define mmPCIE_WRAP_DB_BASE_ADDR_H_2 0xC01928 + +#define mmPCIE_WRAP_DB_BASE_ADDR_H_3 0xC0192C + +#define mmPCIE_WRAP_DB_MASK 0xC01940 + +#define mmPCIE_WRAP_SQ_BASE_ADDR_H 0xC01A00 + +#define mmPCIE_WRAP_SQ_BASE_ADDR_L 0xC01A04 + +#define mmPCIE_WRAP_SQ_STRIDE_ACCRESS 0xC01A08 + +#define mmPCIE_WRAP_SQ_POP_CMD 0xC01A10 + +#define mmPCIE_WRAP_SQ_POP_DATA 0xC01A14 + +#define mmPCIE_WRAP_DB_INTR_0 0xC01A20 + +#define mmPCIE_WRAP_DB_INTR_1 0xC01A24 + +#define mmPCIE_WRAP_DB_INTR_2 0xC01A28 + +#define mmPCIE_WRAP_DB_INTR_3 0xC01A2C + +#define mmPCIE_WRAP_DB_INTR_4 0xC01A30 + +#define mmPCIE_WRAP_DB_INTR_5 0xC01A34 + +#define mmPCIE_WRAP_DB_INTR_6 0xC01A38 + +#define mmPCIE_WRAP_DB_INTR_7 0xC01A3C + +#define mmPCIE_WRAP_MMU_BYPASS_DMA 0xC01A80 + +#define mmPCIE_WRAP_MMU_BYPASS_NON_DMA 0xC01A84 + +#define mmPCIE_WRAP_ASID_NON_DMA 0xC01A90 + +#define mmPCIE_WRAP_ASID_DMA_0 0xC01AA0 + +#define mmPCIE_WRAP_ASID_DMA_1 0xC01AA4 + +#define mmPCIE_WRAP_ASID_DMA_2 0xC01AA8 + +#define mmPCIE_WRAP_ASID_DMA_3 0xC01AAC + +#define mmPCIE_WRAP_ASID_DMA_4 0xC01AB0 + +#define mmPCIE_WRAP_ASID_DMA_5 0xC01AB4 + +#define mmPCIE_WRAP_ASID_DMA_6 0xC01AB8 + +#define mmPCIE_WRAP_ASID_DMA_7 0xC01ABC + +#define mmPCIE_WRAP_CPU_HOT_RST 0xC01AE0 + +#define mmPCIE_WRAP_AXI_PROT_OVR 0xC01AE4 + +#define mmPCIE_WRAP_CACHE_OVR 0xC01B00 + +#define mmPCIE_WRAP_LOCK_OVR 0xC01B04 + +#define mmPCIE_WRAP_PROT_OVR 0xC01B08 + +#define mmPCIE_WRAP_ARUSER_OVR 0xC01B0C + +#define mmPCIE_WRAP_AWUSER_OVR 0xC01B10 + +#define mmPCIE_WRAP_ARUSER_OVR_EN 0xC01B14 + +#define mmPCIE_WRAP_AWUSER_OVR_EN 0xC01B18 + +#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 + +#define mmPCIE_WRAP_MST_IN 0xC01B24 + +#define mmPCIE_WRAP_RSP_OK 0xC01B28 + +#define mmPCIE_WRAP_LBW_CACHE_OVR 0xC01B40 + +#define mmPCIE_WRAP_LBW_LOCK_OVR 0xC01B44 + +#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 + +#define mmPCIE_WRAP_LBW_ARUSER_OVR 0xC01B4C + +#define mmPCIE_WRAP_LBW_AWUSER_OVR 0xC01B50 + +#define mmPCIE_WRAP_LBW_ARUSER_OVR_EN 0xC01B58 + +#define mmPCIE_WRAP_LBW_AWUSER_OVR_EN 0xC01B5C + +#define mmPCIE_WRAP_LBW_MAX_OUTSTAND 0xC01B60 + +#define mmPCIE_WRAP_LBW_MST_IN 0xC01B64 + +#define mmPCIE_WRAP_LBW_RSP_OK 0xC01B68 + +#define mmPCIE_WRAP_QUEUE_INIT 0xC01C00 + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_0 0xC01C10 + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_1 0xC01C14 + +#define mmPCIE_WRAP_DB_AWUSER 0xC01D00 + +#define mmPCIE_WRAP_DB_ARUSER 0xC01D04 + +#define mmPCIE_WRAP_PCIE_AWUSER 0xC01D08 + +#define mmPCIE_WRAP_PCIE_ARUSER 0xC01D0C + +#define mmPCIE_WRAP_PSOC_AWUSER 0xC01D10 + +#define mmPCIE_WRAP_PSOC_ARUSER 0xC01D14 + +#define mmPCIE_WRAP_SCH_Q_AWUSER 0xC01D18 + +#define mmPCIE_WRAP_SCH_Q_ARUSER 0xC01D1C + +#define mmPCIE_WRAP_PSOC2PCI_AWUSER 0xC01D40 + +#define mmPCIE_WRAP_PSOC2PCI_ARUSER 0xC01D44 + +#define mmPCIE_WRAP_DRAIN_TIMEOUT 0xC01D50 + +#define mmPCIE_WRAP_DRAIN_CFG 0xC01D54 + +#define mmPCIE_WRAP_DB_AXI_ERR 0xC01DE0 + +#define mmPCIE_WRAP_SPMU_INTR 0xC01DE4 + +#define mmPCIE_WRAP_AXI_INTR 0xC01DE8 + +#define mmPCIE_WRAP_E2E_CTRL 0xC01DF0 + +#endif /* ASIC_REG_PCIE_WRAP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h new file mode 100644 index 000000000..9271ea95e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_EMMC_PLL_REGS_H_ +#define ASIC_REG_PSOC_EMMC_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_EMMC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_EMMC_PLL_NR 0xC70100 + +#define mmPSOC_EMMC_PLL_NF 0xC70104 + +#define mmPSOC_EMMC_PLL_OD 0xC70108 + +#define mmPSOC_EMMC_PLL_NB 0xC7010C + +#define mmPSOC_EMMC_PLL_CFG 0xC70110 + +#define mmPSOC_EMMC_PLL_LOSE_MASK 0xC70120 + +#define mmPSOC_EMMC_PLL_LOCK_INTR 0xC70128 + +#define mmPSOC_EMMC_PLL_LOCK_BYPASS 0xC7012C + +#define mmPSOC_EMMC_PLL_DATA_CHNG 0xC70130 + +#define mmPSOC_EMMC_PLL_RST 0xC70134 + +#define mmPSOC_EMMC_PLL_SLIP_WD_CNTR 0xC70150 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_0 0xC70200 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_1 0xC70204 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_2 0xC70208 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_3 0xC7020C + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_0 0xC70220 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_1 0xC70224 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_2 0xC70228 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_CMD_3 0xC7022C + +#define mmPSOC_EMMC_PLL_DIV_SEL_0 0xC70280 + +#define mmPSOC_EMMC_PLL_DIV_SEL_1 0xC70284 + +#define mmPSOC_EMMC_PLL_DIV_SEL_2 0xC70288 + +#define mmPSOC_EMMC_PLL_DIV_SEL_3 0xC7028C + +#define mmPSOC_EMMC_PLL_DIV_EN_0 0xC702A0 + +#define mmPSOC_EMMC_PLL_DIV_EN_1 0xC702A4 + +#define mmPSOC_EMMC_PLL_DIV_EN_2 0xC702A8 + +#define mmPSOC_EMMC_PLL_DIV_EN_3 0xC702AC + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_0 0xC702C0 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_1 0xC702C4 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_2 0xC702C8 + +#define mmPSOC_EMMC_PLL_DIV_FACTOR_BUSY_3 0xC702CC + +#define mmPSOC_EMMC_PLL_CLK_GATER 0xC70300 + +#define mmPSOC_EMMC_PLL_CLK_RLX_0 0xC70310 + +#define mmPSOC_EMMC_PLL_CLK_RLX_1 0xC70314 + +#define mmPSOC_EMMC_PLL_CLK_RLX_2 0xC70318 + +#define mmPSOC_EMMC_PLL_CLK_RLX_3 0xC7031C + +#define mmPSOC_EMMC_PLL_REF_CNTR_PERIOD 0xC70400 + +#define mmPSOC_EMMC_PLL_REF_LOW_THRESHOLD 0xC70410 + +#define mmPSOC_EMMC_PLL_REF_HIGH_THRESHOLD 0xC70420 + +#define mmPSOC_EMMC_PLL_PLL_NOT_STABLE 0xC70430 + +#define mmPSOC_EMMC_PLL_FREQ_CALC_EN 0xC70440 + +#endif /* ASIC_REG_PSOC_EMMC_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000..b7c33e025 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x2C43004 + +#define mmPSOC_ETR_STS 0x2C4300C + +#define mmPSOC_ETR_RRD 0x2C43010 + +#define mmPSOC_ETR_RRP 0x2C43014 + +#define mmPSOC_ETR_RWP 0x2C43018 + +#define mmPSOC_ETR_TRG 0x2C4301C + +#define mmPSOC_ETR_CTL 0x2C43020 + +#define mmPSOC_ETR_RWD 0x2C43024 + +#define mmPSOC_ETR_MODE 0x2C43028 + +#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C + +#define mmPSOC_ETR_CBUFLEVEL 0x2C43030 + +#define mmPSOC_ETR_BUFWM 0x2C43034 + +#define mmPSOC_ETR_RRPHI 0x2C43038 + +#define mmPSOC_ETR_RWPHI 0x2C4303C + +#define mmPSOC_ETR_AXICTL 0x2C43110 + +#define mmPSOC_ETR_DBALO 0x2C43118 + +#define mmPSOC_ETR_DBAHI 0x2C4311C + +#define mmPSOC_ETR_FFSR 0x2C43300 + +#define mmPSOC_ETR_FFCR 0x2C43304 + +#define mmPSOC_ETR_PSCR 0x2C43308 + +#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC + +#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8 + +#define mmPSOC_ETR_ITCTRL 0x2C43F00 + +#define mmPSOC_ETR_CLAIMSET 0x2C43FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4 + +#define mmPSOC_ETR_LAR 0x2C43FB0 + +#define mmPSOC_ETR_LSR 0x2C43FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8 + +#define mmPSOC_ETR_DEVID 0x2C43FC8 + +#define mmPSOC_ETR_DEVTYPE 0x2C43FCC + +#define mmPSOC_ETR_PERIPHID4 0x2C43FD0 + +#define mmPSOC_ETR_PERIPHID5 0x2C43FD4 + +#define mmPSOC_ETR_PERIPHID6 0x2C43FD8 + +#define mmPSOC_ETR_PERIPHID7 0x2C43FDC + +#define mmPSOC_ETR_PERIPHID0 0x2C43FE0 + +#define mmPSOC_ETR_PERIPHID1 0x2C43FE4 + +#define mmPSOC_ETR_PERIPHID2 0x2C43FE8 + +#define mmPSOC_ETR_PERIPHID3 0x2C43FEC + +#define mmPSOC_ETR_COMPID0 0x2C43FF0 + +#define mmPSOC_ETR_COMPID1 0x2C43FF4 + +#define mmPSOC_ETR_COMPID2 0x2C43FF8 + +#define mmPSOC_ETR_COMPID3 0x2C43FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000..324266653 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_WARM_REBOOT */ +#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_UBOOT_MAGIC */ +#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 + +/* PSOC_GLOBAL_CONF_APP_STATUS */ +#define PSOC_GLOBAL_CONF_APP_STATUS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_APP_STATUS_IND_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 12 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFFF000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MII_ADDR */ +#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MII_ADDR_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_MII_SPEED */ +#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MII_SPEED_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0xFE0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_SHIFT 12 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_MASK 0x3000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_SHIFT 14 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_MASK 0x1FC000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_SHIFT 21 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK 0x200000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_MASK 0x1C00000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_SHIFT 25 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_MASK 0x2000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_SHIFT 26 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_MASK 0x1C000000 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_WD_RST_CFG */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_UNIT_RST_N */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_MASK 0x1 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_SHIFT 1 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_MASK 0x2 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_SHIFT 2 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_MASK 0x1FC +#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_SHIFT 9 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK 0x200 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_SHIFT 10 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_MASK 0x400 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_SHIFT 11 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_MASK 0x800 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT 12 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_MASK 0x1000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_SHIFT 13 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_MASK 0x2000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_SHIFT 14 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_MASK 0x4000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_SHIFT 15 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_MASK 0x1F8000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_SHIFT 21 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_MASK 0x200000 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_SHIFT 22 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_MASK 0x400000 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000..8141f422e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C + +#define mmPSOC_GLOBAL_CONF_WARM_REBOOT 0xC4B300 + +#define mmPSOC_GLOBAL_CONF_UBOOT_MAGIC 0xC4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 + +#define mmPSOC_GLOBAL_CONF_APP_STATUS 0xC4B320 + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 + +#define mmPSOC_GLOBAL_CONF_MII_ADDR 0xC4B424 + +#define mmPSOC_GLOBAL_CONF_MII_SPEED 0xC4B428 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG 0xC4B470 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG 0xC4B474 + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG 0xC4B478 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG 0xC4B47C + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B480 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B484 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B488 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B490 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B668 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B66C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B680 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B684 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B688 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B68C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B694 + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B6E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B700 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B704 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B708 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B70C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B710 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B714 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B718 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B71C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B720 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B724 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B728 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B72C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B730 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B734 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B738 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B73C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B740 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B744 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B748 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B74C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B750 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B754 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B758 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B75C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B760 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B764 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B768 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B76C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B770 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B774 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B778 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B77C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B780 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B784 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B788 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B78C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B790 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B794 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B798 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B79C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B7A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B7A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B7A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B7AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B7B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B7B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B7B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B7BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B7C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B7C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B7C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B7CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B7D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B7D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B7D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B7DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B7E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B7E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B7E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B7EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B7F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B7F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B7F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B7FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4B99C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4B9A0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4B9A4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4B9A8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4B9AC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4B9B0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4B9B4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4B9B8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4B9BC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4B9C0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4B9C4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4B9C8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4B9CC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4B9D0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4B9D4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4B9D8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4B9DC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4B9E0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4B9E4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4B9E8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4B9EC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4B9F0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4B9F4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4B9F8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4B9FC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BA44 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h new file mode 100644 index 000000000..4789ebb9c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_ +#define ASIC_REG_PSOC_MME_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_MME_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_MME_PLL_NR 0xC71100 + +#define mmPSOC_MME_PLL_NF 0xC71104 + +#define mmPSOC_MME_PLL_OD 0xC71108 + +#define mmPSOC_MME_PLL_NB 0xC7110C + +#define mmPSOC_MME_PLL_CFG 0xC71110 + +#define mmPSOC_MME_PLL_LOSE_MASK 0xC71120 + +#define mmPSOC_MME_PLL_LOCK_INTR 0xC71128 + +#define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C + +#define mmPSOC_MME_PLL_DATA_CHNG 0xC71130 + +#define mmPSOC_MME_PLL_RST 0xC71134 + +#define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150 + +#define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200 + +#define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204 + +#define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208 + +#define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228 + +#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C + +#define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280 + +#define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284 + +#define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288 + +#define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C + +#define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0 + +#define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4 + +#define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8 + +#define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8 + +#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC + +#define mmPSOC_MME_PLL_CLK_GATER 0xC71300 + +#define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310 + +#define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314 + +#define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318 + +#define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C + +#define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400 + +#define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410 + +#define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420 + +#define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430 + +#define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440 + +#endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h new file mode 100644 index 000000000..27a296ea6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_ +#define ASIC_REG_PSOC_PCI_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_PCI_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_PCI_PLL_NR 0xC72100 + +#define mmPSOC_PCI_PLL_NF 0xC72104 + +#define mmPSOC_PCI_PLL_OD 0xC72108 + +#define mmPSOC_PCI_PLL_NB 0xC7210C + +#define mmPSOC_PCI_PLL_CFG 0xC72110 + +#define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120 + +#define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128 + +#define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C + +#define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130 + +#define mmPSOC_PCI_PLL_RST 0xC72134 + +#define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C + +#define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280 + +#define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284 + +#define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288 + +#define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C + +#define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0 + +#define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4 + +#define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8 + +#define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC + +#define mmPSOC_PCI_PLL_CLK_GATER 0xC72300 + +#define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310 + +#define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314 + +#define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318 + +#define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C + +#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400 + +#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410 + +#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420 + +#define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430 + +#define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440 + +#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h new file mode 100644 index 000000000..66aee7fa6 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_SPI_REGS_H_ +#define ASIC_REG_PSOC_SPI_REGS_H_ + +/* + ***************************************** + * PSOC_SPI (Prototype: SPI) + ***************************************** + */ + +#define mmPSOC_SPI_CTRLR0 0xC43000 + +#define mmPSOC_SPI_CTRLR1 0xC43004 + +#define mmPSOC_SPI_SSIENR 0xC43008 + +#define mmPSOC_SPI_MWCR 0xC4300C + +#define mmPSOC_SPI_SER 0xC43010 + +#define mmPSOC_SPI_BAUDR 0xC43014 + +#define mmPSOC_SPI_TXFTLR 0xC43018 + +#define mmPSOC_SPI_RXFTLR 0xC4301C + +#define mmPSOC_SPI_TXFLR 0xC43020 + +#define mmPSOC_SPI_RXFLR 0xC43024 + +#define mmPSOC_SPI_SR 0xC43028 + +#define mmPSOC_SPI_IMR 0xC4302C + +#define mmPSOC_SPI_ISR 0xC43030 + +#define mmPSOC_SPI_RISR 0xC43034 + +#define mmPSOC_SPI_TXOICR 0xC43038 + +#define mmPSOC_SPI_RXOICR 0xC4303C + +#define mmPSOC_SPI_RXUICR 0xC43040 + +#define mmPSOC_SPI_MSTICR 0xC43044 + +#define mmPSOC_SPI_ICR 0xC43048 + +#define mmPSOC_SPI_IDR 0xC43058 + +#define mmPSOC_SPI_SSI_VERSION_ID 0xC4305C + +#define mmPSOC_SPI_DR0 0xC43060 + +#define mmPSOC_SPI_DR1 0xC43064 + +#define mmPSOC_SPI_DR2 0xC43068 + +#define mmPSOC_SPI_DR3 0xC4306C + +#define mmPSOC_SPI_DR4 0xC43070 + +#define mmPSOC_SPI_DR5 0xC43074 + +#define mmPSOC_SPI_DR6 0xC43078 + +#define mmPSOC_SPI_DR7 0xC4307C + +#define mmPSOC_SPI_DR8 0xC43080 + +#define mmPSOC_SPI_DR9 0xC43084 + +#define mmPSOC_SPI_DR10 0xC43088 + +#define mmPSOC_SPI_DR11 0xC4308C + +#define mmPSOC_SPI_DR12 0xC43090 + +#define mmPSOC_SPI_DR13 0xC43094 + +#define mmPSOC_SPI_DR14 0xC43098 + +#define mmPSOC_SPI_DR15 0xC4309C + +#define mmPSOC_SPI_DR16 0xC430A0 + +#define mmPSOC_SPI_DR17 0xC430A4 + +#define mmPSOC_SPI_DR18 0xC430A8 + +#define mmPSOC_SPI_DR19 0xC430AC + +#define mmPSOC_SPI_DR20 0xC430B0 + +#define mmPSOC_SPI_DR21 0xC430B4 + +#define mmPSOC_SPI_DR22 0xC430B8 + +#define mmPSOC_SPI_DR23 0xC430BC + +#define mmPSOC_SPI_DR24 0xC430C0 + +#define mmPSOC_SPI_DR25 0xC430C4 + +#define mmPSOC_SPI_DR26 0xC430C8 + +#define mmPSOC_SPI_DR27 0xC430CC + +#define mmPSOC_SPI_DR28 0xC430D0 + +#define mmPSOC_SPI_DR29 0xC430D4 + +#define mmPSOC_SPI_DR30 0xC430D8 + +#define mmPSOC_SPI_DR31 0xC430DC + +#define mmPSOC_SPI_DR32 0xC430E0 + +#define mmPSOC_SPI_DR33 0xC430E4 + +#define mmPSOC_SPI_DR34 0xC430E8 + +#define mmPSOC_SPI_DR35 0xC430EC + +#define mmPSOC_SPI_RX_SAMPLE_DLY 0xC430F0 + +#define mmPSOC_SPI_RSVD_1 0xC430F8 + +#define mmPSOC_SPI_RSVD_2 0xC430FC + +#endif /* ASIC_REG_PSOC_SPI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000..9ce24597d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h new file mode 100644 index 000000000..2ea1770b0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X0_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_E_ARB 0x201100 + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_W_ARB 0x201104 + +#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB 0x201110 + +#define mmSRAM_Y0_X0_RTR_HBW_E_ARB_MAX 0x201120 + +#define mmSRAM_Y0_X0_RTR_HBW_W_ARB_MAX 0x201124 + +#define mmSRAM_Y0_X0_RTR_HBW_L_ARB_MAX 0x201130 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB 0x201140 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB 0x201144 + +#define mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB 0x201148 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB 0x201160 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB 0x201164 + +#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_L_ARB 0x201168 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_E_ARB 0x201200 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_W_ARB 0x201204 + +#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_L_ARB 0x201210 + +#define mmSRAM_Y0_X0_RTR_LBW_E_ARB_MAX 0x201220 + +#define mmSRAM_Y0_X0_RTR_LBW_W_ARB_MAX 0x201224 + +#define mmSRAM_Y0_X0_RTR_LBW_L_ARB_MAX 0x201230 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_E_ARB 0x201240 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_W_ARB 0x201244 + +#define mmSRAM_Y0_X0_RTR_LBW_DATA_L_ARB 0x201248 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_E_ARB 0x201260 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_W_ARB 0x201264 + +#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_L_ARB 0x201268 + +#define mmSRAM_Y0_X0_RTR_DBG_E_ARB 0x201300 + +#define mmSRAM_Y0_X0_RTR_DBG_W_ARB 0x201304 + +#define mmSRAM_Y0_X0_RTR_DBG_L_ARB 0x201310 + +#define mmSRAM_Y0_X0_RTR_DBG_E_ARB_MAX 0x201320 + +#define mmSRAM_Y0_X0_RTR_DBG_W_ARB_MAX 0x201324 + +#define mmSRAM_Y0_X0_RTR_DBG_L_ARB_MAX 0x201330 + +#endif /* ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h new file mode 100644 index 000000000..37e0713ef --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X1_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_E_ARB 0x205100 + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_W_ARB 0x205104 + +#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB 0x205110 + +#define mmSRAM_Y0_X1_RTR_HBW_E_ARB_MAX 0x205120 + +#define mmSRAM_Y0_X1_RTR_HBW_W_ARB_MAX 0x205124 + +#define mmSRAM_Y0_X1_RTR_HBW_L_ARB_MAX 0x205130 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB 0x205140 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB 0x205144 + +#define mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB 0x205148 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB 0x205160 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB 0x205164 + +#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_L_ARB 0x205168 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_E_ARB 0x205200 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_W_ARB 0x205204 + +#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_L_ARB 0x205210 + +#define mmSRAM_Y0_X1_RTR_LBW_E_ARB_MAX 0x205220 + +#define mmSRAM_Y0_X1_RTR_LBW_W_ARB_MAX 0x205224 + +#define mmSRAM_Y0_X1_RTR_LBW_L_ARB_MAX 0x205230 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_E_ARB 0x205240 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_W_ARB 0x205244 + +#define mmSRAM_Y0_X1_RTR_LBW_DATA_L_ARB 0x205248 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_E_ARB 0x205260 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_W_ARB 0x205264 + +#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_L_ARB 0x205268 + +#define mmSRAM_Y0_X1_RTR_DBG_E_ARB 0x205300 + +#define mmSRAM_Y0_X1_RTR_DBG_W_ARB 0x205304 + +#define mmSRAM_Y0_X1_RTR_DBG_L_ARB 0x205310 + +#define mmSRAM_Y0_X1_RTR_DBG_E_ARB_MAX 0x205320 + +#define mmSRAM_Y0_X1_RTR_DBG_W_ARB_MAX 0x205324 + +#define mmSRAM_Y0_X1_RTR_DBG_L_ARB_MAX 0x205330 + +#endif /* ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h new file mode 100644 index 000000000..d2572279a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X2_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_E_ARB 0x209100 + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_W_ARB 0x209104 + +#define mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB 0x209110 + +#define mmSRAM_Y0_X2_RTR_HBW_E_ARB_MAX 0x209120 + +#define mmSRAM_Y0_X2_RTR_HBW_W_ARB_MAX 0x209124 + +#define mmSRAM_Y0_X2_RTR_HBW_L_ARB_MAX 0x209130 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB 0x209140 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB 0x209144 + +#define mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB 0x209148 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB 0x209160 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB 0x209164 + +#define mmSRAM_Y0_X2_RTR_HBW_WR_RS_L_ARB 0x209168 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_E_ARB 0x209200 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_W_ARB 0x209204 + +#define mmSRAM_Y0_X2_RTR_LBW_RD_RQ_L_ARB 0x209210 + +#define mmSRAM_Y0_X2_RTR_LBW_E_ARB_MAX 0x209220 + +#define mmSRAM_Y0_X2_RTR_LBW_W_ARB_MAX 0x209224 + +#define mmSRAM_Y0_X2_RTR_LBW_L_ARB_MAX 0x209230 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_E_ARB 0x209240 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_W_ARB 0x209244 + +#define mmSRAM_Y0_X2_RTR_LBW_DATA_L_ARB 0x209248 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_E_ARB 0x209260 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_W_ARB 0x209264 + +#define mmSRAM_Y0_X2_RTR_LBW_WR_RS_L_ARB 0x209268 + +#define mmSRAM_Y0_X2_RTR_DBG_E_ARB 0x209300 + +#define mmSRAM_Y0_X2_RTR_DBG_W_ARB 0x209304 + +#define mmSRAM_Y0_X2_RTR_DBG_L_ARB 0x209310 + +#define mmSRAM_Y0_X2_RTR_DBG_E_ARB_MAX 0x209320 + +#define mmSRAM_Y0_X2_RTR_DBG_W_ARB_MAX 0x209324 + +#define mmSRAM_Y0_X2_RTR_DBG_L_ARB_MAX 0x209330 + +#endif /* ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h new file mode 100644 index 000000000..68c5b402c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X3_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_E_ARB 0x20D100 + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_W_ARB 0x20D104 + +#define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB 0x20D110 + +#define mmSRAM_Y0_X3_RTR_HBW_E_ARB_MAX 0x20D120 + +#define mmSRAM_Y0_X3_RTR_HBW_W_ARB_MAX 0x20D124 + +#define mmSRAM_Y0_X3_RTR_HBW_L_ARB_MAX 0x20D130 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB 0x20D140 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB 0x20D144 + +#define mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB 0x20D148 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB 0x20D160 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB 0x20D164 + +#define mmSRAM_Y0_X3_RTR_HBW_WR_RS_L_ARB 0x20D168 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_E_ARB 0x20D200 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_W_ARB 0x20D204 + +#define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_L_ARB 0x20D210 + +#define mmSRAM_Y0_X3_RTR_LBW_E_ARB_MAX 0x20D220 + +#define mmSRAM_Y0_X3_RTR_LBW_W_ARB_MAX 0x20D224 + +#define mmSRAM_Y0_X3_RTR_LBW_L_ARB_MAX 0x20D230 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_E_ARB 0x20D240 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_W_ARB 0x20D244 + +#define mmSRAM_Y0_X3_RTR_LBW_DATA_L_ARB 0x20D248 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_E_ARB 0x20D260 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_W_ARB 0x20D264 + +#define mmSRAM_Y0_X3_RTR_LBW_WR_RS_L_ARB 0x20D268 + +#define mmSRAM_Y0_X3_RTR_DBG_E_ARB 0x20D300 + +#define mmSRAM_Y0_X3_RTR_DBG_W_ARB 0x20D304 + +#define mmSRAM_Y0_X3_RTR_DBG_L_ARB 0x20D310 + +#define mmSRAM_Y0_X3_RTR_DBG_E_ARB_MAX 0x20D320 + +#define mmSRAM_Y0_X3_RTR_DBG_W_ARB_MAX 0x20D324 + +#define mmSRAM_Y0_X3_RTR_DBG_L_ARB_MAX 0x20D330 + +#endif /* ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h new file mode 100644 index 000000000..a42f1ba06 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ +#define ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ + +/* + ***************************************** + * SRAM_Y0_X4_RTR (Prototype: IC_RTR) + ***************************************** + */ + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_E_ARB 0x211100 + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_W_ARB 0x211104 + +#define mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB 0x211110 + +#define mmSRAM_Y0_X4_RTR_HBW_E_ARB_MAX 0x211120 + +#define mmSRAM_Y0_X4_RTR_HBW_W_ARB_MAX 0x211124 + +#define mmSRAM_Y0_X4_RTR_HBW_L_ARB_MAX 0x211130 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB 0x211140 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB 0x211144 + +#define mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB 0x211148 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB 0x211160 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB 0x211164 + +#define mmSRAM_Y0_X4_RTR_HBW_WR_RS_L_ARB 0x211168 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_E_ARB 0x211200 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_W_ARB 0x211204 + +#define mmSRAM_Y0_X4_RTR_LBW_RD_RQ_L_ARB 0x211210 + +#define mmSRAM_Y0_X4_RTR_LBW_E_ARB_MAX 0x211220 + +#define mmSRAM_Y0_X4_RTR_LBW_W_ARB_MAX 0x211224 + +#define mmSRAM_Y0_X4_RTR_LBW_L_ARB_MAX 0x211230 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_E_ARB 0x211240 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_W_ARB 0x211244 + +#define mmSRAM_Y0_X4_RTR_LBW_DATA_L_ARB 0x211248 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_E_ARB 0x211260 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_W_ARB 0x211264 + +#define mmSRAM_Y0_X4_RTR_LBW_WR_RS_L_ARB 0x211268 + +#define mmSRAM_Y0_X4_RTR_DBG_E_ARB 0x211300 + +#define mmSRAM_Y0_X4_RTR_DBG_W_ARB 0x211304 + +#define mmSRAM_Y0_X4_RTR_DBG_L_ARB 0x211310 + +#define mmSRAM_Y0_X4_RTR_DBG_E_ARB_MAX 0x211320 + +#define mmSRAM_Y0_X4_RTR_DBG_W_ARB_MAX 0x211324 + +#define mmSRAM_Y0_X4_RTR_DBG_L_ARB_MAX 0x211330 + +#endif /* ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h new file mode 100644 index 000000000..94f2ed4a3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_MASKS_H_ +#define ASIC_REG_STLB_MASKS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +/* STLB_CACHE_INV */ +#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* STLB_CACHE_INV_BASE_39_8 */ +#define STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* STLB_CACHE_INV_BASE_49_40 */ +#define STLB_CACHE_INV_BASE_49_40_PA_SHIFT 0 +#define STLB_CACHE_INV_BASE_49_40_PA_MASK 0x3FF + +/* STLB_STLB_FEATURE_EN */ +#define STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0xF80 + +/* STLB_STLB_AXI_CACHE */ +#define STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* STLB_HOP_CONFIGURATION */ +#define STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SHIFT 4 +#define STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_MASK 0x70 +#define STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 8 +#define STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x700 + +/* STLB_LINK_LIST_LOOKUP_MASK_49_32 */ +#define STLB_LINK_LIST_LOOKUP_MASK_49_32_R_SHIFT 0 +#define STLB_LINK_LIST_LOOKUP_MASK_49_32_R_MASK 0x3FFFF + +/* STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* STLB_LINK_LIST */ +#define STLB_LINK_LIST_CLEAR_SHIFT 0 +#define STLB_LINK_LIST_CLEAR_MASK 0x1 +#define STLB_LINK_LIST_EN_SHIFT 1 +#define STLB_LINK_LIST_EN_MASK 0x2 + +/* STLB_INV_ALL_START */ +#define STLB_INV_ALL_START_R_SHIFT 0 +#define STLB_INV_ALL_START_R_MASK 0x1 + +/* STLB_INV_ALL_SET */ +#define STLB_INV_ALL_SET_R_SHIFT 0 +#define STLB_INV_ALL_SET_R_MASK 0xFF + +/* STLB_INV_PS */ +#define STLB_INV_PS_R_SHIFT 0 +#define STLB_INV_PS_R_MASK 0x3 + +/* STLB_INV_CONSUMER_INDEX */ +#define STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* STLB_INV_HIT_COUNT */ +#define STLB_INV_HIT_COUNT_R_SHIFT 0 +#define STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* STLB_INV_SET */ +#define STLB_INV_SET_R_SHIFT 0 +#define STLB_INV_SET_R_MASK 0xFF + +/* STLB_SRAM_INIT */ +#define STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +#endif /* ASIC_REG_STLB_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h new file mode 100644 index 000000000..35013f65a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0x490010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0x490014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0x490018 + +#define mmSTLB_STLB_FEATURE_EN 0x49001C + +#define mmSTLB_STLB_AXI_CACHE 0x490020 + +#define mmSTLB_HOP_CONFIGURATION 0x490024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0x490028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0x49002C + +#define mmSTLB_LINK_LIST 0x490030 + +#define mmSTLB_INV_ALL_START 0x490034 + +#define mmSTLB_INV_ALL_SET 0x490038 + +#define mmSTLB_INV_PS 0x49003C + +#define mmSTLB_INV_CONSUMER_INDEX 0x490040 + +#define mmSTLB_INV_HIT_COUNT 0x490044 + +#define mmSTLB_INV_SET 0x490048 + +#define mmSTLB_SRAM_INIT 0x49004C + +#endif /* ASIC_REG_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h new file mode 100644 index 000000000..89c9507a5 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h @@ -0,0 +1,1606 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_MASKS_H_ +#define ASIC_REG_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_SRF */ +#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_CONFIG */ +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 8 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F00 + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* TPC0_CFG_RESERVED_DESC_END */ +#define TPC0_CFG_RESERVED_DESC_END_V_SHIFT 0 +#define TPC0_CFG_RESERVED_DESC_END_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ROUND_CSR */ +#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* TPC0_CFG_TBUF_BASE_ADDR_LOW */ +#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TBUF_BASE_ADDR_HIGH */ +#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SEMAPHORE */ +#define TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_VFLAGS */ +#define TPC0_CFG_VFLAGS_V_SHIFT 0 +#define TPC0_CFG_VFLAGS_V_MASK 0xF + +/* TPC0_CFG_SFLAGS */ +#define TPC0_CFG_SFLAGS_V_SHIFT 0 +#define TPC0_CFG_SFLAGS_V_MASK 0xF + +/* TPC0_CFG_LFSR_POLYNOM */ +#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_STATUS */ +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT 4 +#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK 0x10 + +/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_LOW */ +#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_CMD */ +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* TPC0_CFG_TPC_EXECUTE */ +#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* TPC0_CFG_TPC_STALL */ +#define TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_MSS_CONFIG */ +#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 + +/* TPC0_CFG_TPC_INTR_CAUSE */ +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_INTR_MASK */ +#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +/* TPC0_CFG_TSB_CONFIG */ +#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT 0 +#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK 0x1F +#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT 5 +#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK 0x3E0 +#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT 10 +#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK 0xFFC00 +#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT 20 +#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK 0x3FF00000 + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_0 */ +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_0 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_1 */ +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_1 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_2 */ +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_2 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_3 */ +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_3 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_4 */ +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_4 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_SRF */ +#define TPC0_CFG_QM_SRF_V_SHIFT 0 +#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_CONFIG */ +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 8 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F00 + +/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000 + +/* TPC0_CFG_ARUSER */ +#define TPC0_CFG_ARUSER_ASID_SHIFT 0 +#define TPC0_CFG_ARUSER_ASID_MASK 0x3FF +#define TPC0_CFG_ARUSER_MMBP_SHIFT 10 +#define TPC0_CFG_ARUSER_MMBP_MASK 0x400 +#define TPC0_CFG_ARUSER_V_SHIFT 11 +#define TPC0_CFG_ARUSER_V_MASK 0xFFFFF800 + +/* TPC0_CFG_AWUSER */ +#define TPC0_CFG_AWUSER_ASID_SHIFT 0 +#define TPC0_CFG_AWUSER_ASID_MASK 0x3FF +#define TPC0_CFG_AWUSER_MMBP_SHIFT 10 +#define TPC0_CFG_AWUSER_MMBP_MASK 0x400 +#define TPC0_CFG_AWUSER_V_SHIFT 11 +#define TPC0_CFG_AWUSER_V_MASK 0xFFFFF800 + +/* TPC0_CFG_FUNC_MBIST_CNTRL */ +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 + +/* TPC0_CFG_FUNC_MBIST_PAT */ +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 + +/* TPC0_CFG_FUNC_MBIST_MEM */ +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 + +#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h new file mode 100644 index 000000000..7d71c4b73 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_REGS_H_ +#define ASIC_REG_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE06418 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE0641C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE06420 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE06424 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06428 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE0642C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE06430 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06434 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE06438 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE0643C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06440 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06444 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE06448 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE0644C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE06450 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06454 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06458 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE0645C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE06460 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE06464 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06468 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE0646C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE06470 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06474 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE06478 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE0647C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06480 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06484 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE06488 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE0648C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE06490 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE06494 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06498 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE0649C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE064A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE064A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE064A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE064AC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE064B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE064B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE064B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE064BC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE064C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE064C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE064C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE064CC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE064D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE064D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064DC + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE064E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064EC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE064FC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE06500 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE06504 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE06508 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE0650C + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE06510 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE06514 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE06518 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE0651C + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE06520 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE06524 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE06528 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE0652C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE06530 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE06534 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE06538 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE0653C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE06540 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE06544 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE06548 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE0654C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE06550 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE06554 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06558 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE0655C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE06560 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06564 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE06568 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE0656C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06570 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06574 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE06578 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE0657C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE06580 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06584 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06588 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE0658C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE06590 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE06594 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06598 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE0659C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE065A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE065A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE065A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE065AC + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE065B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE065B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE065B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE065BC + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE065C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE065C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE065C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE065CC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE065D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE065D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE065D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE065DC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE065E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE065E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE065E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE065EC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE065F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE065F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE065F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE065FC + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE06600 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE06604 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06608 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE0660C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE06610 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06614 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE06618 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE0661C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06620 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06624 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE06628 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE0662C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE06630 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE06634 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE06638 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE0663C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE06640 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE06644 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE06648 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE0664C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE06650 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE06654 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE06658 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE0665C + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06660 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE06664 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06668 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE0666C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06670 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE06674 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE06678 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE0667C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE06680 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE06684 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE06688 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE0668C + +#define mmTPC0_CFG_KERNEL_SRF_0 0xE06690 + +#define mmTPC0_CFG_KERNEL_SRF_1 0xE06694 + +#define mmTPC0_CFG_KERNEL_SRF_2 0xE06698 + +#define mmTPC0_CFG_KERNEL_SRF_3 0xE0669C + +#define mmTPC0_CFG_KERNEL_SRF_4 0xE066A0 + +#define mmTPC0_CFG_KERNEL_SRF_5 0xE066A4 + +#define mmTPC0_CFG_KERNEL_SRF_6 0xE066A8 + +#define mmTPC0_CFG_KERNEL_SRF_7 0xE066AC + +#define mmTPC0_CFG_KERNEL_SRF_8 0xE066B0 + +#define mmTPC0_CFG_KERNEL_SRF_9 0xE066B4 + +#define mmTPC0_CFG_KERNEL_SRF_10 0xE066B8 + +#define mmTPC0_CFG_KERNEL_SRF_11 0xE066BC + +#define mmTPC0_CFG_KERNEL_SRF_12 0xE066C0 + +#define mmTPC0_CFG_KERNEL_SRF_13 0xE066C4 + +#define mmTPC0_CFG_KERNEL_SRF_14 0xE066C8 + +#define mmTPC0_CFG_KERNEL_SRF_15 0xE066CC + +#define mmTPC0_CFG_KERNEL_SRF_16 0xE066D0 + +#define mmTPC0_CFG_KERNEL_SRF_17 0xE066D4 + +#define mmTPC0_CFG_KERNEL_SRF_18 0xE066D8 + +#define mmTPC0_CFG_KERNEL_SRF_19 0xE066DC + +#define mmTPC0_CFG_KERNEL_SRF_20 0xE066E0 + +#define mmTPC0_CFG_KERNEL_SRF_21 0xE066E4 + +#define mmTPC0_CFG_KERNEL_SRF_22 0xE066E8 + +#define mmTPC0_CFG_KERNEL_SRF_23 0xE066EC + +#define mmTPC0_CFG_KERNEL_SRF_24 0xE066F0 + +#define mmTPC0_CFG_KERNEL_SRF_25 0xE066F4 + +#define mmTPC0_CFG_KERNEL_SRF_26 0xE066F8 + +#define mmTPC0_CFG_KERNEL_SRF_27 0xE066FC + +#define mmTPC0_CFG_KERNEL_SRF_28 0xE06700 + +#define mmTPC0_CFG_KERNEL_SRF_29 0xE06704 + +#define mmTPC0_CFG_KERNEL_SRF_30 0xE06708 + +#define mmTPC0_CFG_KERNEL_SRF_31 0xE0670C + +#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE06710 + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06714 + +#define mmTPC0_CFG_RESERVED_DESC_END 0xE06738 + +#define mmTPC0_CFG_ROUND_CSR 0xE067FC + +#define mmTPC0_CFG_TBUF_BASE_ADDR_LOW 0xE06800 + +#define mmTPC0_CFG_TBUF_BASE_ADDR_HIGH 0xE06804 + +#define mmTPC0_CFG_SEMAPHORE 0xE06808 + +#define mmTPC0_CFG_VFLAGS 0xE0680C + +#define mmTPC0_CFG_SFLAGS 0xE06810 + +#define mmTPC0_CFG_LFSR_POLYNOM 0xE06818 + +#define mmTPC0_CFG_STATUS 0xE0681C + +#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06820 + +#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06824 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_LOW 0xE06828 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0682C + +#define mmTPC0_CFG_TPC_CMD 0xE06830 + +#define mmTPC0_CFG_TPC_EXECUTE 0xE06838 + +#define mmTPC0_CFG_TPC_STALL 0xE0683C + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06840 + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06844 + +#define mmTPC0_CFG_MSS_CONFIG 0xE06854 + +#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06858 + +#define mmTPC0_CFG_TPC_INTR_MASK 0xE0685C + +#define mmTPC0_CFG_TSB_CONFIG 0xE06860 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 + +#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 + +#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE06A18 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A1C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A20 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE06A24 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A28 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A2C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE06A30 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A34 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A38 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE06A3C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A40 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A44 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE06A48 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A4C + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A50 + +#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A54 + +#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A58 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A5C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A60 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE06A64 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A68 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A6C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE06A70 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A74 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A78 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE06A7C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A80 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A84 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE06A88 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A8C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A90 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE06A94 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A98 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A9C + +#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06AA0 + +#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06AA4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06AA8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06AAC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE06AB0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06AB4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06AB8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE06ABC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06AC0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06AC4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE06AC8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06ACC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06AD0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE06AD4 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AD8 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06ADC + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE06AE0 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AE4 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AE8 + +#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AEC + +#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AF0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AF4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06AF8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE06AFC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06B00 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06B04 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE06B08 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06B0C + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06B10 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE06B14 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06B18 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06B1C + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE06B20 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06B24 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06B28 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE06B2C + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06B30 + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06B34 + +#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06B38 + +#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06B3C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06B40 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06B44 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE06B48 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06B4C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06B50 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE06B54 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B58 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B5C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE06B60 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B64 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B68 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE06B6C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B70 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B74 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE06B78 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B7C + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B80 + +#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B84 + +#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B88 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B8C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B90 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE06B94 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B98 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B9C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE06BA0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06BA4 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06BA8 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE06BAC + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06BB0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06BB4 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE06BB8 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06BBC + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06BC0 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE06BC4 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06BC8 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06BCC + +#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06BD0 + +#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06BD4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06BD8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06BDC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE06BE0 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06BE4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06BE8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE06BEC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06BF0 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06BF4 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE06BF8 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06BFC + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06C00 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE06C04 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06C08 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06C0C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE06C10 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06C14 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06C18 + +#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06C1C + +#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06C20 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06C24 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06C28 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE06C2C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06C30 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06C34 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE06C38 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06C3C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06C40 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE06C44 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06C48 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06C4C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE06C50 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06C54 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06C58 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE06C5C + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06C60 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06C64 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06C68 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06C6C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06C70 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06C74 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06C78 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06C7C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06C80 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06C84 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06C88 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06C8C + +#define mmTPC0_CFG_QM_SRF_0 0xE06C90 + +#define mmTPC0_CFG_QM_SRF_1 0xE06C94 + +#define mmTPC0_CFG_QM_SRF_2 0xE06C98 + +#define mmTPC0_CFG_QM_SRF_3 0xE06C9C + +#define mmTPC0_CFG_QM_SRF_4 0xE06CA0 + +#define mmTPC0_CFG_QM_SRF_5 0xE06CA4 + +#define mmTPC0_CFG_QM_SRF_6 0xE06CA8 + +#define mmTPC0_CFG_QM_SRF_7 0xE06CAC + +#define mmTPC0_CFG_QM_SRF_8 0xE06CB0 + +#define mmTPC0_CFG_QM_SRF_9 0xE06CB4 + +#define mmTPC0_CFG_QM_SRF_10 0xE06CB8 + +#define mmTPC0_CFG_QM_SRF_11 0xE06CBC + +#define mmTPC0_CFG_QM_SRF_12 0xE06CC0 + +#define mmTPC0_CFG_QM_SRF_13 0xE06CC4 + +#define mmTPC0_CFG_QM_SRF_14 0xE06CC8 + +#define mmTPC0_CFG_QM_SRF_15 0xE06CCC + +#define mmTPC0_CFG_QM_SRF_16 0xE06CD0 + +#define mmTPC0_CFG_QM_SRF_17 0xE06CD4 + +#define mmTPC0_CFG_QM_SRF_18 0xE06CD8 + +#define mmTPC0_CFG_QM_SRF_19 0xE06CDC + +#define mmTPC0_CFG_QM_SRF_20 0xE06CE0 + +#define mmTPC0_CFG_QM_SRF_21 0xE06CE4 + +#define mmTPC0_CFG_QM_SRF_22 0xE06CE8 + +#define mmTPC0_CFG_QM_SRF_23 0xE06CEC + +#define mmTPC0_CFG_QM_SRF_24 0xE06CF0 + +#define mmTPC0_CFG_QM_SRF_25 0xE06CF4 + +#define mmTPC0_CFG_QM_SRF_26 0xE06CF8 + +#define mmTPC0_CFG_QM_SRF_27 0xE06CFC + +#define mmTPC0_CFG_QM_SRF_28 0xE06D00 + +#define mmTPC0_CFG_QM_SRF_29 0xE06D04 + +#define mmTPC0_CFG_QM_SRF_30 0xE06D08 + +#define mmTPC0_CFG_QM_SRF_31 0xE06D0C + +#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06D10 + +#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D14 + +#define mmTPC0_CFG_ARUSER 0xE06D18 + +#define mmTPC0_CFG_AWUSER 0xE06D1C + +#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE06E00 + +#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE06E04 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE06E08 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE06E0C + +#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE06E10 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE06E14 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE06E18 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE06E1C + +#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE06E20 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE06E24 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE06E28 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE06E2C + +#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h new file mode 100644 index 000000000..9395f2458 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h @@ -0,0 +1,372 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CMDQ_MASKS_H_ +#define ASIC_REG_TPC0_CMDQ_MASKS_H_ + +/* + ***************************************** + * TPC0_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +/* TPC0_CMDQ_GLBL_CFG0 */ +#define TPC0_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x1 +#define TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 1 +#define TPC0_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x2 +#define TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT 2 +#define TPC0_CMDQ_GLBL_CFG0_CP_EN_MASK 0x4 +#define TPC0_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 3 +#define TPC0_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* TPC0_CMDQ_GLBL_CFG1 */ +#define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define TPC0_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 2 +#define TPC0_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x4 +#define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define TPC0_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* TPC0_CMDQ_GLBL_PROT */ +#define TPC0_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 0 +#define TPC0_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x1 +#define TPC0_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 1 +#define TPC0_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x2 +#define TPC0_CMDQ_GLBL_PROT_CP_PROT_SHIFT 2 +#define TPC0_CMDQ_GLBL_PROT_CP_PROT_MASK 0x4 +#define TPC0_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 3 +#define TPC0_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x8 +#define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* TPC0_CMDQ_GLBL_ERR_CFG */ +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* TPC0_CMDQ_GLBL_ERR_ADDR_LO */ +#define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_ERR_ADDR_HI */ +#define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_ERR_WDATA */ +#define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_GLBL_SECURE_PROPS */ +#define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_CMDQ_GLBL_NON_SECURE_PROPS */ +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_CMDQ_GLBL_STS0 */ +#define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define TPC0_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2 +#define TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4 +#define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define TPC0_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* TPC0_CMDQ_GLBL_STS1 */ +#define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* TPC0_CMDQ_CQ_CFG0 */ +#define TPC0_CMDQ_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_CMDQ_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_CMDQ_CQ_CFG1 */ +#define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_ARUSER */ +#define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_CMDQ_CQ_ARUSER_WORD_SHIFT 1 +#define TPC0_CMDQ_CQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_CMDQ_CQ_PTR_LO */ +#define TPC0_CMDQ_CQ_PTR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_PTR_HI */ +#define TPC0_CMDQ_CQ_PTR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_TSIZE */ +#define TPC0_CMDQ_CQ_TSIZE_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_CTL */ +#define TPC0_CMDQ_CQ_CTL_RPT_SHIFT 0 +#define TPC0_CMDQ_CQ_CTL_RPT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CTL_CTL_SHIFT 16 +#define TPC0_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_PTR_LO_STS */ +#define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_PTR_HI_STS */ +#define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_TSIZE_STS */ +#define TPC0_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_CTL_STS */ +#define TPC0_CMDQ_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_STS0 */ +#define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_CMDQ_CQ_STS1 */ +#define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_EN */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_SAT */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT */ +#define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_CMDQ_CQ_IFIFO_CNT */ +#define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET */ +#define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_FENCE0_RDATA */ +#define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE1_RDATA */ +#define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE2_RDATA */ +#define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE3_RDATA */ +#define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_CMDQ_CP_FENCE0_CNT */ +#define TPC0_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE1_CNT */ +#define TPC0_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE2_CNT */ +#define TPC0_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_FENCE3_CNT */ +#define TPC0_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* TPC0_CMDQ_CP_STS */ +#define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_CMDQ_CP_STS_ERDY_SHIFT 16 +#define TPC0_CMDQ_CP_STS_ERDY_MASK 0x10000 +#define TPC0_CMDQ_CP_STS_RRDY_SHIFT 17 +#define TPC0_CMDQ_CP_STS_RRDY_MASK 0x20000 +#define TPC0_CMDQ_CP_STS_MRDY_SHIFT 18 +#define TPC0_CMDQ_CP_STS_MRDY_MASK 0x40000 +#define TPC0_CMDQ_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_CMDQ_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_CMDQ_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_CMDQ_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_CMDQ_CP_CURRENT_INST_LO */ +#define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_CURRENT_INST_HI */ +#define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CP_BARRIER_CFG */ +#define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* TPC0_CMDQ_CP_DBG_0 */ +#define TPC0_CMDQ_CP_DBG_0_VAL_SHIFT 0 +#define TPC0_CMDQ_CP_DBG_0_VAL_MASK 0xFF + +/* TPC0_CMDQ_CQ_BUF_ADDR */ +#define TPC0_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_CMDQ_CQ_BUF_RDATA */ +#define TPC0_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_CMDQ_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h new file mode 100644 index 000000000..bc51df573 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CMDQ_REGS_H_ +#define ASIC_REG_TPC0_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC0_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC0_CMDQ_GLBL_CFG0 0xE09000 + +#define mmTPC0_CMDQ_GLBL_CFG1 0xE09004 + +#define mmTPC0_CMDQ_GLBL_PROT 0xE09008 + +#define mmTPC0_CMDQ_GLBL_ERR_CFG 0xE0900C + +#define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO 0xE09010 + +#define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI 0xE09014 + +#define mmTPC0_CMDQ_GLBL_ERR_WDATA 0xE09018 + +#define mmTPC0_CMDQ_GLBL_SECURE_PROPS 0xE0901C + +#define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS 0xE09020 + +#define mmTPC0_CMDQ_GLBL_STS0 0xE09024 + +#define mmTPC0_CMDQ_GLBL_STS1 0xE09028 + +#define mmTPC0_CMDQ_CQ_CFG0 0xE090B0 + +#define mmTPC0_CMDQ_CQ_CFG1 0xE090B4 + +#define mmTPC0_CMDQ_CQ_ARUSER 0xE090B8 + +#define mmTPC0_CMDQ_CQ_PTR_LO 0xE090C0 + +#define mmTPC0_CMDQ_CQ_PTR_HI 0xE090C4 + +#define mmTPC0_CMDQ_CQ_TSIZE 0xE090C8 + +#define mmTPC0_CMDQ_CQ_CTL 0xE090CC + +#define mmTPC0_CMDQ_CQ_PTR_LO_STS 0xE090D4 + +#define mmTPC0_CMDQ_CQ_PTR_HI_STS 0xE090D8 + +#define mmTPC0_CMDQ_CQ_TSIZE_STS 0xE090DC + +#define mmTPC0_CMDQ_CQ_CTL_STS 0xE090E0 + +#define mmTPC0_CMDQ_CQ_STS0 0xE090E4 + +#define mmTPC0_CMDQ_CQ_STS1 0xE090E8 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN 0xE090F0 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE090F4 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT 0xE090F8 + +#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE090FC + +#define mmTPC0_CMDQ_CQ_IFIFO_CNT 0xE09108 + +#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE09120 + +#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE09124 + +#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE09128 + +#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE0912C + +#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE09130 + +#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE09134 + +#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE09138 + +#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE0913C + +#define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE09140 + +#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE09144 + +#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE09148 + +#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE0914C + +#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE09150 + +#define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE09154 + +#define mmTPC0_CMDQ_CP_FENCE0_RDATA 0xE09158 + +#define mmTPC0_CMDQ_CP_FENCE1_RDATA 0xE0915C + +#define mmTPC0_CMDQ_CP_FENCE2_RDATA 0xE09160 + +#define mmTPC0_CMDQ_CP_FENCE3_RDATA 0xE09164 + +#define mmTPC0_CMDQ_CP_FENCE0_CNT 0xE09168 + +#define mmTPC0_CMDQ_CP_FENCE1_CNT 0xE0916C + +#define mmTPC0_CMDQ_CP_FENCE2_CNT 0xE09170 + +#define mmTPC0_CMDQ_CP_FENCE3_CNT 0xE09174 + +#define mmTPC0_CMDQ_CP_STS 0xE09178 + +#define mmTPC0_CMDQ_CP_CURRENT_INST_LO 0xE0917C + +#define mmTPC0_CMDQ_CP_CURRENT_INST_HI 0xE09180 + +#define mmTPC0_CMDQ_CP_BARRIER_CFG 0xE09184 + +#define mmTPC0_CMDQ_CP_DBG_0 0xE09188 + +#define mmTPC0_CMDQ_CQ_BUF_ADDR 0xE09308 + +#define mmTPC0_CMDQ_CQ_BUF_RDATA 0xE0930C + +#endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h new file mode 100644 index 000000000..553c6b6bd --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h @@ -0,0 +1,346 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_EML_CFG_MASKS_H_ +#define ASIC_REG_TPC0_EML_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_EML_CFG (Prototype: TPC_EML_CFG) + ***************************************** + */ + +/* TPC0_EML_CFG_DBG_CNT */ +#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_SHIFT 0 +#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_MASK 0x1 +#define TPC0_EML_CFG_DBG_CNT_DBG_EN_SHIFT 1 +#define TPC0_EML_CFG_DBG_CNT_DBG_EN_MASK 0x2 +#define TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT 2 +#define TPC0_EML_CFG_DBG_CNT_CORE_RST_MASK 0x4 +#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_SHIFT 4 +#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_MASK 0x10 +#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_SHIFT 5 +#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_MASK 0x20 +#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_SHIFT 6 +#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40 +#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_SHIFT 7 +#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_MASK 0x80 +#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_SHIFT 16 +#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_MASK 0x10000 + +/* TPC0_EML_CFG_DBG_STS */ +#define TPC0_EML_CFG_DBG_STS_DBG_MODE_SHIFT 0 +#define TPC0_EML_CFG_DBG_STS_DBG_MODE_MASK 0x1 +#define TPC0_EML_CFG_DBG_STS_CORE_READY_SHIFT 1 +#define TPC0_EML_CFG_DBG_STS_CORE_READY_MASK 0x2 +#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_SHIFT 2 +#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_MASK 0x4 +#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_SHIFT 3 +#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_MASK 0x8 +#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_SHIFT 4 +#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_MASK 0x10 +#define TPC0_EML_CFG_DBG_STS_QM_IDLE_SHIFT 5 +#define TPC0_EML_CFG_DBG_STS_QM_IDLE_MASK 0x20 +#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_SHIFT 6 +#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_MASK 0x40 +#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_SHIFT 7 +#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_MASK 0x80 +#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_SHIFT 8 +#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_MASK 0xFFFFFF00 + +/* TPC0_EML_CFG_DBG_PADD */ +#define TPC0_EML_CFG_DBG_PADD_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_PADD_COUNT */ +#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_PADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_PADD_EN */ +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_SHIFT 2 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_MASK 0x4 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_SHIFT 3 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_MASK 0x8 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_SHIFT 4 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_MASK 0x10 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_SHIFT 5 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_MASK 0x20 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_SHIFT 6 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_MASK 0x40 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_SHIFT 7 +#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_MASK 0x80 + +/* TPC0_EML_CFG_DBG_VPADD_HIGH */ +#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_MASK 0x1FF + +/* TPC0_EML_CFG_DBG_VPADD_LOW */ +#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_MASK 0x1FF + +/* TPC0_EML_CFG_DBG_VPADD_COUNT */ +#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_VPADD_EN */ +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_SPADD_HIGH */ +#define TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_LOW */ +#define TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_COUNT */ +#define TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPADD_EN */ +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AGUADD_COUNT */ +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AGUADD_EN */ +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_COUNT */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWADD_EN */ +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW */ +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW */ +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_COUNT */ +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWADD_EN */ +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_SPDATA */ +#define TPC0_EML_CFG_DBG_SPDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_SPDATA_COUNT */ +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_SPDATA_EN */ +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_SHIFT 0 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_MASK 0x1 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_SHIFT 1 +#define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_MASK 0x2 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_SHIFT 2 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_MASK 0x4 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_SHIFT 3 +#define TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_MASK 0x8 + +/* TPC0_EML_CFG_DBG_AXIHBWDATA */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXIHBWDATA_EN */ +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_MASK 0x2 + +/* TPC0_EML_CFG_DBG_AXILBWDATA */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_DATA_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_DATA_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_AXILBWDATA_COUNT */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH */ +#define TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_MASK 0xFF + +/* TPC0_EML_CFG_DBG_AXILBWDATA_EN */ +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_SHIFT 0 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_MASK 0x1 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_SHIFT 1 +#define TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_MASK 0x2 + +/* TPC0_EML_CFG_DBG_D0_PC */ +#define TPC0_EML_CFG_DBG_D0_PC_PC_SHIFT 0 +#define TPC0_EML_CFG_DBG_D0_PC_PC_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_RTTCONFIG */ +#define TPC0_EML_CFG_RTTCONFIG_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTCONFIG_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTCONFIG_PRIO_SHIFT 1 +#define TPC0_EML_CFG_RTTCONFIG_PRIO_MASK 0x2 + +/* TPC0_EML_CFG_RTTPREDICATE */ +#define TPC0_EML_CFG_RTTPREDICATE_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTPREDICATE_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTPREDICATE_GEN_SHIFT 1 +#define TPC0_EML_CFG_RTTPREDICATE_GEN_MASK 0x2 +#define TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_SHIFT 2 +#define TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_MASK 0x4 +#define TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_SHIFT 16 +#define TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_MASK 0xFFFF0000 + +/* TPC0_EML_CFG_RTTPREDICATE_INTV */ +#define TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_SHIFT 0 +#define TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_RTTTS */ +#define TPC0_EML_CFG_RTTTS_TR_EN_SHIFT 0 +#define TPC0_EML_CFG_RTTTS_TR_EN_MASK 0x1 +#define TPC0_EML_CFG_RTTTS_GEN_SHIFT 1 +#define TPC0_EML_CFG_RTTTS_GEN_MASK 0x2 +#define TPC0_EML_CFG_RTTTS_COMPRESS_EN_SHIFT 2 +#define TPC0_EML_CFG_RTTTS_COMPRESS_EN_MASK 0x4 + +/* TPC0_EML_CFG_RTTTS_INTV */ +#define TPC0_EML_CFG_RTTTS_INTV_INTERVAL_SHIFT 0 +#define TPC0_EML_CFG_RTTTS_INTV_INTERVAL_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_INST_INSERT */ +#define TPC0_EML_CFG_DBG_INST_INSERT_INST_SHIFT 0 +#define TPC0_EML_CFG_DBG_INST_INSERT_INST_MASK 0xFFFFFFFF + +/* TPC0_EML_CFG_DBG_INST_INSERT_CTL */ +#define TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_SHIFT 0 +#define TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_MASK 0x1 + +#endif /* ASIC_REG_TPC0_EML_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h new file mode 100644 index 000000000..8495479c3 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h @@ -0,0 +1,312 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_EML_CFG_REGS_H_ +#define ASIC_REG_TPC0_EML_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_EML_CFG (Prototype: TPC_EML_CFG) + ***************************************** + */ + +#define mmTPC0_EML_CFG_DBG_CNT 0x3040000 + +#define mmTPC0_EML_CFG_DBG_STS 0x3040004 + +#define mmTPC0_EML_CFG_DBG_PADD_0 0x3040008 + +#define mmTPC0_EML_CFG_DBG_PADD_1 0x304000C + +#define mmTPC0_EML_CFG_DBG_PADD_2 0x3040010 + +#define mmTPC0_EML_CFG_DBG_PADD_3 0x3040014 + +#define mmTPC0_EML_CFG_DBG_PADD_4 0x3040018 + +#define mmTPC0_EML_CFG_DBG_PADD_5 0x304001C + +#define mmTPC0_EML_CFG_DBG_PADD_6 0x3040020 + +#define mmTPC0_EML_CFG_DBG_PADD_7 0x3040024 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_0 0x3040028 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_1 0x304002C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_2 0x3040030 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_3 0x3040034 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_4 0x3040038 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_5 0x304003C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_6 0x3040040 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_7 0x3040044 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_0 0x3040048 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_1 0x304004C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_2 0x3040050 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_3 0x3040054 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_4 0x3040058 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_5 0x304005C + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_6 0x3040060 + +#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_7 0x3040064 + +#define mmTPC0_EML_CFG_DBG_PADD_EN 0x3040068 + +#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_0 0x304006C + +#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_1 0x3040070 + +#define mmTPC0_EML_CFG_DBG_VPADD_LOW_0 0x3040074 + +#define mmTPC0_EML_CFG_DBG_VPADD_LOW_1 0x3040078 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_0 0x304007C + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_1 0x3040080 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_0 0x3040084 + +#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_1 0x3040088 + +#define mmTPC0_EML_CFG_DBG_VPADD_EN 0x304008C + +#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_0 0x3040090 + +#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_1 0x3040094 + +#define mmTPC0_EML_CFG_DBG_SPADD_LOW_0 0x3040098 + +#define mmTPC0_EML_CFG_DBG_SPADD_LOW_1 0x304009C + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_0 0x30400A0 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_1 0x30400A4 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_0 0x30400A8 + +#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_1 0x30400AC + +#define mmTPC0_EML_CFG_DBG_SPADD_EN 0x30400B0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_0 0x30400B4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_1 0x30400B8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_0 0x30400BC + +#define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_1 0x30400C0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_0 0x30400C4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_1 0x30400C8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_0 0x30400CC + +#define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_1 0x30400D0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_0 0x30400D4 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_1 0x30400D8 + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_0 0x30400DC + +#define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_1 0x30400E0 + +#define mmTPC0_EML_CFG_DBG_AGUADD_EN 0x30400E4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_0 0x30400E8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_1 0x30400EC + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_0 0x30400F0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_1 0x30400F4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_0 0x30400F8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_1 0x30400FC + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_0 0x3040100 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_1 0x3040104 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_0 0x3040108 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_1 0x304010C + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_0 0x3040110 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_1 0x3040114 + +#define mmTPC0_EML_CFG_DBG_AXIHBWADD_EN 0x3040118 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_0 0x304011C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_1 0x3040120 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_0 0x3040124 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_1 0x3040128 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_0 0x304012C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_1 0x3040130 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_0 0x3040134 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_1 0x3040138 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_0 0x304013C + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_1 0x3040140 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_0 0x3040144 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_1 0x3040148 + +#define mmTPC0_EML_CFG_DBG_AXILBWADD_EN 0x304014C + +#define mmTPC0_EML_CFG_DBG_SPDATA_0 0x3040150 + +#define mmTPC0_EML_CFG_DBG_SPDATA_1 0x3040154 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_0 0x3040158 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_1 0x304015C + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_0 0x3040160 + +#define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_1 0x3040164 + +#define mmTPC0_EML_CFG_DBG_SPDATA_EN 0x3040168 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_0 0x304016C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_1 0x3040170 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_2 0x3040174 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_3 0x3040178 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_4 0x304017C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_5 0x3040180 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_6 0x3040184 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_7 0x3040188 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_8 0x304018C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_9 0x3040190 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_10 0x3040194 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_11 0x3040198 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_12 0x304019C + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_13 0x30401A0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_14 0x30401A4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_15 0x30401A8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_16 0x30401AC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_17 0x30401B0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_18 0x30401B4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_19 0x30401B8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_20 0x30401BC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_21 0x30401C0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_22 0x30401C4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_23 0x30401C8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_24 0x30401CC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_25 0x30401D0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_26 0x30401D4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_27 0x30401D8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_28 0x30401DC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_29 0x30401E0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_30 0x30401E4 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_31 0x30401E8 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_COUNT 0x30401EC + +#define mmTPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH 0x30401F0 + +#define mmTPC0_EML_CFG_DBG_AXIHBWDATA_EN 0x30401F4 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA 0x30401F8 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA_COUNT 0x30401FC + +#define mmTPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH 0x3040200 + +#define mmTPC0_EML_CFG_DBG_AXILBWDATA_EN 0x3040204 + +#define mmTPC0_EML_CFG_DBG_D0_PC 0x3040208 + +#define mmTPC0_EML_CFG_RTTCONFIG 0x3040300 + +#define mmTPC0_EML_CFG_RTTPREDICATE 0x3040304 + +#define mmTPC0_EML_CFG_RTTPREDICATE_INTV 0x3040308 + +#define mmTPC0_EML_CFG_RTTTS 0x304030C + +#define mmTPC0_EML_CFG_RTTTS_INTV 0x3040310 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_0 0x3040314 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_1 0x3040318 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_2 0x304031C + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_3 0x3040320 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_4 0x3040324 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_5 0x3040328 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_6 0x304032C + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_7 0x3040330 + +#define mmTPC0_EML_CFG_DBG_INST_INSERT_CTL 0x3040334 + +#endif /* ASIC_REG_TPC0_EML_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h new file mode 100644 index 000000000..43fafcf01 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_NRTR_MASKS_H_ +#define ASIC_REG_TPC0_NRTR_MASKS_H_ + +/* + ***************************************** + * TPC0_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +/* TPC0_NRTR_HBW_MAX_CRED */ +#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 +#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F +#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 +#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 +#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* TPC0_NRTR_LBW_MAX_CRED */ +#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 +#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F +#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 +#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 +#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 + +/* TPC0_NRTR_DBG_E_ARB */ +#define TPC0_NRTR_DBG_E_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_E_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_E_ARB_S_SHIFT 8 +#define TPC0_NRTR_DBG_E_ARB_S_MASK 0x700 +#define TPC0_NRTR_DBG_E_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_E_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_E_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_E_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_W_ARB */ +#define TPC0_NRTR_DBG_W_ARB_E_SHIFT 0 +#define TPC0_NRTR_DBG_W_ARB_E_MASK 0x7 +#define TPC0_NRTR_DBG_W_ARB_S_SHIFT 8 +#define TPC0_NRTR_DBG_W_ARB_S_MASK 0x700 +#define TPC0_NRTR_DBG_W_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_W_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_W_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_W_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_N_ARB */ +#define TPC0_NRTR_DBG_N_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_N_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_N_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_N_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_N_ARB_S_SHIFT 16 +#define TPC0_NRTR_DBG_N_ARB_S_MASK 0x70000 +#define TPC0_NRTR_DBG_N_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_N_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_S_ARB */ +#define TPC0_NRTR_DBG_S_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_S_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_S_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_S_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_S_ARB_N_SHIFT 16 +#define TPC0_NRTR_DBG_S_ARB_N_MASK 0x70000 +#define TPC0_NRTR_DBG_S_ARB_L_SHIFT 24 +#define TPC0_NRTR_DBG_S_ARB_L_MASK 0x7000000 + +/* TPC0_NRTR_DBG_L_ARB */ +#define TPC0_NRTR_DBG_L_ARB_W_SHIFT 0 +#define TPC0_NRTR_DBG_L_ARB_W_MASK 0x7 +#define TPC0_NRTR_DBG_L_ARB_E_SHIFT 8 +#define TPC0_NRTR_DBG_L_ARB_E_MASK 0x700 +#define TPC0_NRTR_DBG_L_ARB_S_SHIFT 16 +#define TPC0_NRTR_DBG_L_ARB_S_MASK 0x70000 +#define TPC0_NRTR_DBG_L_ARB_N_SHIFT 24 +#define TPC0_NRTR_DBG_L_ARB_N_MASK 0x7000000 + +/* TPC0_NRTR_DBG_E_ARB_MAX */ +#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_W_ARB_MAX */ +#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_N_ARB_MAX */ +#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_S_ARB_MAX */ +#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_DBG_L_ARB_MAX */ +#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 +#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F + +/* TPC0_NRTR_SPLIT_COEF */ +#define TPC0_NRTR_SPLIT_COEF_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_CFG */ +#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 +#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 +#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 +#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 +#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 +#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC +#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 +#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 +#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 +#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 +#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 +#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 + +/* TPC0_NRTR_SPLIT_RD_SAT */ +#define TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_RD_RST_TOKEN */ +#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_RD_TIMEOUT */ +#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_SPLIT_WR_SAT */ +#define TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF + +/* TPC0_NRTR_WPLIT_WR_TST_TOLEN */ +#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 +#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF + +/* TPC0_NRTR_SPLIT_WR_TIMEOUT */ +#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 +#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_HIT */ +#define TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF + +/* TPC0_NRTR_HBW_RANGE_MASK_L */ +#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_MASK_H */ +#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF + +/* TPC0_NRTR_HBW_RANGE_BASE_L */ +#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF + +/* TPC0_NRTR_HBW_RANGE_BASE_H */ +#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 +#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF + +/* TPC0_NRTR_LBW_RANGE_HIT */ +#define TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF + +/* TPC0_NRTR_LBW_RANGE_MASK */ +#define TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF + +/* TPC0_NRTR_LBW_RANGE_BASE */ +#define TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 +#define TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF + +/* TPC0_NRTR_RGLTR */ +#define TPC0_NRTR_RGLTR_WR_EN_SHIFT 0 +#define TPC0_NRTR_RGLTR_WR_EN_MASK 0x1 +#define TPC0_NRTR_RGLTR_RD_EN_SHIFT 4 +#define TPC0_NRTR_RGLTR_RD_EN_MASK 0x10 + +/* TPC0_NRTR_RGLTR_WR_RESULT */ +#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 +#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF + +/* TPC0_NRTR_RGLTR_RD_RESULT */ +#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 +#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF + +/* TPC0_NRTR_SCRAMB_EN */ +#define TPC0_NRTR_SCRAMB_EN_VAL_SHIFT 0 +#define TPC0_NRTR_SCRAMB_EN_VAL_MASK 0x1 + +/* TPC0_NRTR_NON_LIN_SCRAMB */ +#define TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 +#define TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 + +#endif /* ASIC_REG_TPC0_NRTR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h new file mode 100644 index 000000000..ce3346dd2 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_NRTR_REGS_H_ +#define ASIC_REG_TPC0_NRTR_REGS_H_ + +/* + ***************************************** + * TPC0_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmTPC0_NRTR_HBW_MAX_CRED 0xE00100 + +#define mmTPC0_NRTR_LBW_MAX_CRED 0xE00120 + +#define mmTPC0_NRTR_DBG_E_ARB 0xE00300 + +#define mmTPC0_NRTR_DBG_W_ARB 0xE00304 + +#define mmTPC0_NRTR_DBG_N_ARB 0xE00308 + +#define mmTPC0_NRTR_DBG_S_ARB 0xE0030C + +#define mmTPC0_NRTR_DBG_L_ARB 0xE00310 + +#define mmTPC0_NRTR_DBG_E_ARB_MAX 0xE00320 + +#define mmTPC0_NRTR_DBG_W_ARB_MAX 0xE00324 + +#define mmTPC0_NRTR_DBG_N_ARB_MAX 0xE00328 + +#define mmTPC0_NRTR_DBG_S_ARB_MAX 0xE0032C + +#define mmTPC0_NRTR_DBG_L_ARB_MAX 0xE00330 + +#define mmTPC0_NRTR_SPLIT_COEF_0 0xE00400 + +#define mmTPC0_NRTR_SPLIT_COEF_1 0xE00404 + +#define mmTPC0_NRTR_SPLIT_COEF_2 0xE00408 + +#define mmTPC0_NRTR_SPLIT_COEF_3 0xE0040C + +#define mmTPC0_NRTR_SPLIT_COEF_4 0xE00410 + +#define mmTPC0_NRTR_SPLIT_COEF_5 0xE00414 + +#define mmTPC0_NRTR_SPLIT_COEF_6 0xE00418 + +#define mmTPC0_NRTR_SPLIT_COEF_7 0xE0041C + +#define mmTPC0_NRTR_SPLIT_COEF_8 0xE00420 + +#define mmTPC0_NRTR_SPLIT_COEF_9 0xE00424 + +#define mmTPC0_NRTR_SPLIT_CFG 0xE00440 + +#define mmTPC0_NRTR_SPLIT_RD_SAT 0xE00444 + +#define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN 0xE00448 + +#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0 0xE0044C + +#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1 0xE00450 + +#define mmTPC0_NRTR_SPLIT_WR_SAT 0xE00454 + +#define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN 0xE00458 + +#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0 0xE0045C + +#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1 0xE00460 + +#define mmTPC0_NRTR_HBW_RANGE_HIT 0xE00470 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_0 0xE00480 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_1 0xE00484 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_2 0xE00488 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_3 0xE0048C + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_4 0xE00490 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_5 0xE00494 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_6 0xE00498 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_L_7 0xE0049C + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_0 0xE004A0 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_1 0xE004A4 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_2 0xE004A8 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_3 0xE004AC + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_4 0xE004B0 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_5 0xE004B4 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_6 0xE004B8 + +#define mmTPC0_NRTR_HBW_RANGE_MASK_H_7 0xE004BC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_0 0xE004C0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_1 0xE004C4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_2 0xE004C8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_3 0xE004CC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_4 0xE004D0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_5 0xE004D4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_6 0xE004D8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_L_7 0xE004DC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_0 0xE004E0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_1 0xE004E4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_2 0xE004E8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_3 0xE004EC + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_4 0xE004F0 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_5 0xE004F4 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_6 0xE004F8 + +#define mmTPC0_NRTR_HBW_RANGE_BASE_H_7 0xE004FC + +#define mmTPC0_NRTR_LBW_RANGE_HIT 0xE00500 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_0 0xE00510 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_1 0xE00514 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_2 0xE00518 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_3 0xE0051C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_4 0xE00520 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_5 0xE00524 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_6 0xE00528 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_7 0xE0052C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_8 0xE00530 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_9 0xE00534 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_10 0xE00538 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_11 0xE0053C + +#define mmTPC0_NRTR_LBW_RANGE_MASK_12 0xE00540 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_13 0xE00544 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_14 0xE00548 + +#define mmTPC0_NRTR_LBW_RANGE_MASK_15 0xE0054C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_0 0xE00550 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_1 0xE00554 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_2 0xE00558 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_3 0xE0055C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_4 0xE00560 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_5 0xE00564 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_6 0xE00568 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_7 0xE0056C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_8 0xE00570 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_9 0xE00574 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_10 0xE00578 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_11 0xE0057C + +#define mmTPC0_NRTR_LBW_RANGE_BASE_12 0xE00580 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_13 0xE00584 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_14 0xE00588 + +#define mmTPC0_NRTR_LBW_RANGE_BASE_15 0xE0058C + +#define mmTPC0_NRTR_RGLTR 0xE00590 + +#define mmTPC0_NRTR_RGLTR_WR_RESULT 0xE00594 + +#define mmTPC0_NRTR_RGLTR_RD_RESULT 0xE00598 + +#define mmTPC0_NRTR_SCRAMB_EN 0xE00600 + +#define mmTPC0_NRTR_NON_LIN_SCRAMB 0xE00604 + +#endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h new file mode 100644 index 000000000..2e4b45947 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_MASKS_H_ +#define ASIC_REG_TPC0_QM_MASKS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +/* TPC0_QM_GLBL_CFG0 */ +#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1 +#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1 +#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2 +#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2 +#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4 +#define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3 +#define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8 + +/* TPC0_QM_GLBL_CFG1 */ +#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 +#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2 +#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4 +#define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 +#define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 +#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 +#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 + +/* TPC0_QM_GLBL_PROT */ +#define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0 +#define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1 +#define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1 +#define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2 +#define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2 +#define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4 +#define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3 +#define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8 +#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 +#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 +#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 +#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 +#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 +#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 +#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 +#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 + +/* TPC0_QM_GLBL_ERR_CFG */ +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 +#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 +#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 +#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 + +/* TPC0_QM_GLBL_ERR_ADDR_LO */ +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_ADDR_HI */ +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_WDATA */ +#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_SECURE_PROPS */ +#define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_NON_SECURE_PROPS */ +#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_STS0 */ +#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 +#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2 +#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4 +#define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 +#define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 +#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 +#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 + +/* TPC0_QM_GLBL_STS1 */ +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 + +/* TPC0_QM_PQ_BASE_LO */ +#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BASE_HI */ +#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_SIZE */ +#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 +#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PI */ +#define TPC0_QM_PQ_PI_VAL_SHIFT 0 +#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CI */ +#define TPC0_QM_PQ_CI_VAL_SHIFT 0 +#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CFG0 */ +#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_PQ_CFG1 */ +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_ARUSER */ +#define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1 +#define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_QM_PQ_PUSH0 */ +#define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0 +#define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH1 */ +#define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0 +#define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH2 */ +#define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0 +#define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PUSH3 */ +#define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0 +#define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF +#define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16 +#define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS0 */ +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS1 */ +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_PQ_RD_RATE_LIM_EN */ +#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_QM_PQ_RD_RATE_LIM_SAT */ +#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_QM_PQ_RD_RATE_LIM_TOUT */ +#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_QM_CQ_CFG0 */ +#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_CQ_CFG1 */ +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_ARUSER */ +#define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 +#define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 +#define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1 +#define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2 + +/* TPC0_QM_CQ_PTR_LO */ +#define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI */ +#define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE */ +#define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL */ +#define TPC0_QM_CQ_CTL_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_STS */ +#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_STS */ +#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_STS */ +#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_STS */ +#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS0 */ +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS1 */ +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_RD_RATE_LIM_EN */ +#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 + +/* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */ +#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF + +/* TPC0_QM_CQ_RD_RATE_LIM_SAT */ +#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF + +/* TPC0_QM_CQ_RD_RATE_LIM_TOUT */ +#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 +#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF + +/* TPC0_QM_CQ_IFIFO_CNT */ +#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_COMMIT_OFFSET */ +#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_FENCE0_RDATA */ +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE1_RDATA */ +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE2_RDATA */ +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE3_RDATA */ +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE0_CNT */ +#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE1_CNT */ +#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE2_CNT */ +#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_FENCE3_CNT */ +#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF + +/* TPC0_QM_CP_STS */ +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CP_STS_ERDY_SHIFT 16 +#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 +#define TPC0_QM_CP_STS_RRDY_SHIFT 17 +#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 +#define TPC0_QM_CP_STS_MRDY_SHIFT 18 +#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 +#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_QM_CP_CURRENT_INST_LO */ +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_CURRENT_INST_HI */ +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_BARRIER_CFG */ +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF + +/* TPC0_QM_CP_DBG_0 */ +#define TPC0_QM_CP_DBG_0_VAL_SHIFT 0 +#define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF + +/* TPC0_QM_PQ_BUF_ADDR */ +#define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BUF_RDATA */ +#define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_BUF_ADDR */ +#define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0 +#define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_BUF_RDATA */ +#define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0 +#define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000..4fa09eb88 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08010 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08014 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS 0xE0801C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS 0xE08020 + +#define mmTPC0_QM_GLBL_STS0 0xE08024 + +#define mmTPC0_QM_GLBL_STS1 0xE08028 + +#define mmTPC0_QM_PQ_BASE_LO 0xE08060 + +#define mmTPC0_QM_PQ_BASE_HI 0xE08064 + +#define mmTPC0_QM_PQ_SIZE 0xE08068 + +#define mmTPC0_QM_PQ_PI 0xE0806C + +#define mmTPC0_QM_PQ_CI 0xE08070 + +#define mmTPC0_QM_PQ_CFG0 0xE08074 + +#define mmTPC0_QM_PQ_CFG1 0xE08078 + +#define mmTPC0_QM_PQ_ARUSER 0xE0807C + +#define mmTPC0_QM_PQ_PUSH0 0xE08080 + +#define mmTPC0_QM_PQ_PUSH1 0xE08084 + +#define mmTPC0_QM_PQ_PUSH2 0xE08088 + +#define mmTPC0_QM_PQ_PUSH3 0xE0808C + +#define mmTPC0_QM_PQ_STS0 0xE08090 + +#define mmTPC0_QM_PQ_STS1 0xE08094 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_EN 0xE080A0 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE080A4 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_SAT 0xE080A8 + +#define mmTPC0_QM_PQ_RD_RATE_LIM_TOUT 0xE080AC + +#define mmTPC0_QM_CQ_CFG0 0xE080B0 + +#define mmTPC0_QM_CQ_CFG1 0xE080B4 + +#define mmTPC0_QM_CQ_ARUSER 0xE080B8 + +#define mmTPC0_QM_CQ_PTR_LO 0xE080C0 + +#define mmTPC0_QM_CQ_PTR_HI 0xE080C4 + +#define mmTPC0_QM_CQ_TSIZE 0xE080C8 + +#define mmTPC0_QM_CQ_CTL 0xE080CC + +#define mmTPC0_QM_CQ_PTR_LO_STS 0xE080D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS 0xE080D8 + +#define mmTPC0_QM_CQ_TSIZE_STS 0xE080DC + +#define mmTPC0_QM_CQ_CTL_STS 0xE080E0 + +#define mmTPC0_QM_CQ_STS0 0xE080E4 + +#define mmTPC0_QM_CQ_STS1 0xE080E8 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_EN 0xE080F0 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE080F4 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_SAT 0xE080F8 + +#define mmTPC0_QM_CQ_RD_RATE_LIM_TOUT 0xE080FC + +#define mmTPC0_QM_CQ_IFIFO_CNT 0xE08108 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO 0xE08120 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI 0xE08124 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO 0xE08128 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI 0xE0812C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO 0xE08130 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI 0xE08134 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO 0xE08138 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI 0xE0813C + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET 0xE08140 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE08144 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE08148 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE0814C + +#define mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE08150 + +#define mmTPC0_QM_CP_LDMA_COMMIT_OFFSET 0xE08154 + +#define mmTPC0_QM_CP_FENCE0_RDATA 0xE08158 + +#define mmTPC0_QM_CP_FENCE1_RDATA 0xE0815C + +#define mmTPC0_QM_CP_FENCE2_RDATA 0xE08160 + +#define mmTPC0_QM_CP_FENCE3_RDATA 0xE08164 + +#define mmTPC0_QM_CP_FENCE0_CNT 0xE08168 + +#define mmTPC0_QM_CP_FENCE1_CNT 0xE0816C + +#define mmTPC0_QM_CP_FENCE2_CNT 0xE08170 + +#define mmTPC0_QM_CP_FENCE3_CNT 0xE08174 + +#define mmTPC0_QM_CP_STS 0xE08178 + +#define mmTPC0_QM_CP_CURRENT_INST_LO 0xE0817C + +#define mmTPC0_QM_CP_CURRENT_INST_HI 0xE08180 + +#define mmTPC0_QM_CP_BARRIER_CFG 0xE08184 + +#define mmTPC0_QM_CP_DBG_0 0xE08188 + +#define mmTPC0_QM_PQ_BUF_ADDR 0xE08300 + +#define mmTPC0_QM_PQ_BUF_RDATA 0xE08304 + +#define mmTPC0_QM_CQ_BUF_ADDR 0xE08308 + +#define mmTPC0_QM_CQ_BUF_RDATA 0xE0830C + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h new file mode 100644 index 000000000..928eef180 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CFG_REGS_H_ +#define ASIC_REG_TPC1_CFG_REGS_H_ + +/* + ***************************************** + * TPC1_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE46418 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE4641C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE46420 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE46424 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46428 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE4642C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE46430 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46434 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE46438 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE4643C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46440 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46444 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE46448 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE4644C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE46450 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46454 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46458 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE4645C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE46460 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE46464 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46468 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE4646C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE46470 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46474 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE46478 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE4647C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46480 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46484 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE46488 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE4648C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE46490 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE46494 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46498 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE4649C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE464A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE464A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE464A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE464AC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE464B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE464B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE464B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE464BC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE464C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE464C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE464C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE464CC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE464D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE464D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464DC + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE464E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464EC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE464FC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE46500 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE46504 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE46508 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE4650C + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE46510 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE46514 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE46518 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE4651C + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE46520 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE46524 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE46528 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE4652C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE46530 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE46534 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE46538 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE4653C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE46540 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE46544 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE46548 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE4654C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE46550 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE46554 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46558 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE4655C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE46560 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46564 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE46568 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE4656C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46570 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46574 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE46578 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE4657C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE46580 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46584 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46588 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE4658C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE46590 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE46594 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46598 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE4659C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE465A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE465A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE465A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE465AC + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE465B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE465B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE465B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE465BC + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE465C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE465C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE465C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE465CC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE465D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE465D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE465D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE465DC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE465E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE465E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE465E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE465EC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE465F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE465F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE465F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE465FC + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE46600 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE46604 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46608 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE4660C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE46610 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46614 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE46618 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE4661C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46620 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46624 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE46628 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE4662C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE46630 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE46634 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE46638 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE4663C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE46640 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE46644 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE46648 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE4664C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE46650 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE46654 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE46658 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE4665C + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46660 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE46664 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46668 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE4666C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46670 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE46674 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE46678 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE4667C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE46680 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE46684 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE46688 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE4668C + +#define mmTPC1_CFG_KERNEL_SRF_0 0xE46690 + +#define mmTPC1_CFG_KERNEL_SRF_1 0xE46694 + +#define mmTPC1_CFG_KERNEL_SRF_2 0xE46698 + +#define mmTPC1_CFG_KERNEL_SRF_3 0xE4669C + +#define mmTPC1_CFG_KERNEL_SRF_4 0xE466A0 + +#define mmTPC1_CFG_KERNEL_SRF_5 0xE466A4 + +#define mmTPC1_CFG_KERNEL_SRF_6 0xE466A8 + +#define mmTPC1_CFG_KERNEL_SRF_7 0xE466AC + +#define mmTPC1_CFG_KERNEL_SRF_8 0xE466B0 + +#define mmTPC1_CFG_KERNEL_SRF_9 0xE466B4 + +#define mmTPC1_CFG_KERNEL_SRF_10 0xE466B8 + +#define mmTPC1_CFG_KERNEL_SRF_11 0xE466BC + +#define mmTPC1_CFG_KERNEL_SRF_12 0xE466C0 + +#define mmTPC1_CFG_KERNEL_SRF_13 0xE466C4 + +#define mmTPC1_CFG_KERNEL_SRF_14 0xE466C8 + +#define mmTPC1_CFG_KERNEL_SRF_15 0xE466CC + +#define mmTPC1_CFG_KERNEL_SRF_16 0xE466D0 + +#define mmTPC1_CFG_KERNEL_SRF_17 0xE466D4 + +#define mmTPC1_CFG_KERNEL_SRF_18 0xE466D8 + +#define mmTPC1_CFG_KERNEL_SRF_19 0xE466DC + +#define mmTPC1_CFG_KERNEL_SRF_20 0xE466E0 + +#define mmTPC1_CFG_KERNEL_SRF_21 0xE466E4 + +#define mmTPC1_CFG_KERNEL_SRF_22 0xE466E8 + +#define mmTPC1_CFG_KERNEL_SRF_23 0xE466EC + +#define mmTPC1_CFG_KERNEL_SRF_24 0xE466F0 + +#define mmTPC1_CFG_KERNEL_SRF_25 0xE466F4 + +#define mmTPC1_CFG_KERNEL_SRF_26 0xE466F8 + +#define mmTPC1_CFG_KERNEL_SRF_27 0xE466FC + +#define mmTPC1_CFG_KERNEL_SRF_28 0xE46700 + +#define mmTPC1_CFG_KERNEL_SRF_29 0xE46704 + +#define mmTPC1_CFG_KERNEL_SRF_30 0xE46708 + +#define mmTPC1_CFG_KERNEL_SRF_31 0xE4670C + +#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE46710 + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46714 + +#define mmTPC1_CFG_RESERVED_DESC_END 0xE46738 + +#define mmTPC1_CFG_ROUND_CSR 0xE467FC + +#define mmTPC1_CFG_TBUF_BASE_ADDR_LOW 0xE46800 + +#define mmTPC1_CFG_TBUF_BASE_ADDR_HIGH 0xE46804 + +#define mmTPC1_CFG_SEMAPHORE 0xE46808 + +#define mmTPC1_CFG_VFLAGS 0xE4680C + +#define mmTPC1_CFG_SFLAGS 0xE46810 + +#define mmTPC1_CFG_LFSR_POLYNOM 0xE46818 + +#define mmTPC1_CFG_STATUS 0xE4681C + +#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46820 + +#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46824 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_LOW 0xE46828 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4682C + +#define mmTPC1_CFG_TPC_CMD 0xE46830 + +#define mmTPC1_CFG_TPC_EXECUTE 0xE46838 + +#define mmTPC1_CFG_TPC_STALL 0xE4683C + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46840 + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46844 + +#define mmTPC1_CFG_MSS_CONFIG 0xE46854 + +#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46858 + +#define mmTPC1_CFG_TPC_INTR_MASK 0xE4685C + +#define mmTPC1_CFG_TSB_CONFIG 0xE46860 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 + +#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 + +#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE46A18 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A1C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A20 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE46A24 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A28 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A2C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE46A30 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A34 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A38 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE46A3C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A40 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A44 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE46A48 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A4C + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A50 + +#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A54 + +#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A58 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A5C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A60 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE46A64 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A68 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A6C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE46A70 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A74 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A78 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE46A7C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A80 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A84 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE46A88 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A8C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A90 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE46A94 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A98 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A9C + +#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46AA0 + +#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46AA4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46AA8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46AAC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE46AB0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46AB4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46AB8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE46ABC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46AC0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46AC4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE46AC8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46ACC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46AD0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE46AD4 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AD8 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46ADC + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE46AE0 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AE4 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AE8 + +#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AEC + +#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AF0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AF4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46AF8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE46AFC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46B00 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46B04 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE46B08 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46B0C + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46B10 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE46B14 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46B18 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46B1C + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE46B20 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46B24 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46B28 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE46B2C + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46B30 + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46B34 + +#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46B38 + +#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46B3C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46B40 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46B44 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE46B48 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46B4C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46B50 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE46B54 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B58 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B5C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE46B60 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B64 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B68 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE46B6C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B70 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B74 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE46B78 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B7C + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B80 + +#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B84 + +#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B88 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B8C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B90 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE46B94 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B98 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B9C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE46BA0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46BA4 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46BA8 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE46BAC + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46BB0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46BB4 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE46BB8 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46BBC + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46BC0 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE46BC4 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46BC8 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46BCC + +#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46BD0 + +#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46BD4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46BD8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46BDC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE46BE0 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46BE4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46BE8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE46BEC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46BF0 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46BF4 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE46BF8 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46BFC + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46C00 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE46C04 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46C08 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46C0C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE46C10 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46C14 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46C18 + +#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46C1C + +#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46C20 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46C24 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46C28 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE46C2C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46C30 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46C34 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE46C38 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46C3C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46C40 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE46C44 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46C48 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46C4C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE46C50 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46C54 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46C58 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE46C5C + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46C60 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46C64 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46C68 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46C6C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46C70 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46C74 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46C78 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46C7C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46C80 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46C84 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46C88 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46C8C + +#define mmTPC1_CFG_QM_SRF_0 0xE46C90 + +#define mmTPC1_CFG_QM_SRF_1 0xE46C94 + +#define mmTPC1_CFG_QM_SRF_2 0xE46C98 + +#define mmTPC1_CFG_QM_SRF_3 0xE46C9C + +#define mmTPC1_CFG_QM_SRF_4 0xE46CA0 + +#define mmTPC1_CFG_QM_SRF_5 0xE46CA4 + +#define mmTPC1_CFG_QM_SRF_6 0xE46CA8 + +#define mmTPC1_CFG_QM_SRF_7 0xE46CAC + +#define mmTPC1_CFG_QM_SRF_8 0xE46CB0 + +#define mmTPC1_CFG_QM_SRF_9 0xE46CB4 + +#define mmTPC1_CFG_QM_SRF_10 0xE46CB8 + +#define mmTPC1_CFG_QM_SRF_11 0xE46CBC + +#define mmTPC1_CFG_QM_SRF_12 0xE46CC0 + +#define mmTPC1_CFG_QM_SRF_13 0xE46CC4 + +#define mmTPC1_CFG_QM_SRF_14 0xE46CC8 + +#define mmTPC1_CFG_QM_SRF_15 0xE46CCC + +#define mmTPC1_CFG_QM_SRF_16 0xE46CD0 + +#define mmTPC1_CFG_QM_SRF_17 0xE46CD4 + +#define mmTPC1_CFG_QM_SRF_18 0xE46CD8 + +#define mmTPC1_CFG_QM_SRF_19 0xE46CDC + +#define mmTPC1_CFG_QM_SRF_20 0xE46CE0 + +#define mmTPC1_CFG_QM_SRF_21 0xE46CE4 + +#define mmTPC1_CFG_QM_SRF_22 0xE46CE8 + +#define mmTPC1_CFG_QM_SRF_23 0xE46CEC + +#define mmTPC1_CFG_QM_SRF_24 0xE46CF0 + +#define mmTPC1_CFG_QM_SRF_25 0xE46CF4 + +#define mmTPC1_CFG_QM_SRF_26 0xE46CF8 + +#define mmTPC1_CFG_QM_SRF_27 0xE46CFC + +#define mmTPC1_CFG_QM_SRF_28 0xE46D00 + +#define mmTPC1_CFG_QM_SRF_29 0xE46D04 + +#define mmTPC1_CFG_QM_SRF_30 0xE46D08 + +#define mmTPC1_CFG_QM_SRF_31 0xE46D0C + +#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46D10 + +#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D14 + +#define mmTPC1_CFG_ARUSER 0xE46D18 + +#define mmTPC1_CFG_AWUSER 0xE46D1C + +#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE46E00 + +#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE46E04 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE46E08 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE46E0C + +#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE46E10 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE46E14 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE46E18 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE46E1C + +#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE46E20 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE46E24 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE46E28 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE46E2C + +#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h new file mode 100644 index 000000000..30ae0f307 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CMDQ_REGS_H_ +#define ASIC_REG_TPC1_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC1_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC1_CMDQ_GLBL_CFG0 0xE49000 + +#define mmTPC1_CMDQ_GLBL_CFG1 0xE49004 + +#define mmTPC1_CMDQ_GLBL_PROT 0xE49008 + +#define mmTPC1_CMDQ_GLBL_ERR_CFG 0xE4900C + +#define mmTPC1_CMDQ_GLBL_ERR_ADDR_LO 0xE49010 + +#define mmTPC1_CMDQ_GLBL_ERR_ADDR_HI 0xE49014 + +#define mmTPC1_CMDQ_GLBL_ERR_WDATA 0xE49018 + +#define mmTPC1_CMDQ_GLBL_SECURE_PROPS 0xE4901C + +#define mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS 0xE49020 + +#define mmTPC1_CMDQ_GLBL_STS0 0xE49024 + +#define mmTPC1_CMDQ_GLBL_STS1 0xE49028 + +#define mmTPC1_CMDQ_CQ_CFG0 0xE490B0 + +#define mmTPC1_CMDQ_CQ_CFG1 0xE490B4 + +#define mmTPC1_CMDQ_CQ_ARUSER 0xE490B8 + +#define mmTPC1_CMDQ_CQ_PTR_LO 0xE490C0 + +#define mmTPC1_CMDQ_CQ_PTR_HI 0xE490C4 + +#define mmTPC1_CMDQ_CQ_TSIZE 0xE490C8 + +#define mmTPC1_CMDQ_CQ_CTL 0xE490CC + +#define mmTPC1_CMDQ_CQ_PTR_LO_STS 0xE490D4 + +#define mmTPC1_CMDQ_CQ_PTR_HI_STS 0xE490D8 + +#define mmTPC1_CMDQ_CQ_TSIZE_STS 0xE490DC + +#define mmTPC1_CMDQ_CQ_CTL_STS 0xE490E0 + +#define mmTPC1_CMDQ_CQ_STS0 0xE490E4 + +#define mmTPC1_CMDQ_CQ_STS1 0xE490E8 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN 0xE490F0 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE490F4 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT 0xE490F8 + +#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE490FC + +#define mmTPC1_CMDQ_CQ_IFIFO_CNT 0xE49108 + +#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE49120 + +#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE49124 + +#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE49128 + +#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE4912C + +#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE49130 + +#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE49134 + +#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE49138 + +#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE4913C + +#define mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE49140 + +#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE49144 + +#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE49148 + +#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE4914C + +#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE49150 + +#define mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE49154 + +#define mmTPC1_CMDQ_CP_FENCE0_RDATA 0xE49158 + +#define mmTPC1_CMDQ_CP_FENCE1_RDATA 0xE4915C + +#define mmTPC1_CMDQ_CP_FENCE2_RDATA 0xE49160 + +#define mmTPC1_CMDQ_CP_FENCE3_RDATA 0xE49164 + +#define mmTPC1_CMDQ_CP_FENCE0_CNT 0xE49168 + +#define mmTPC1_CMDQ_CP_FENCE1_CNT 0xE4916C + +#define mmTPC1_CMDQ_CP_FENCE2_CNT 0xE49170 + +#define mmTPC1_CMDQ_CP_FENCE3_CNT 0xE49174 + +#define mmTPC1_CMDQ_CP_STS 0xE49178 + +#define mmTPC1_CMDQ_CP_CURRENT_INST_LO 0xE4917C + +#define mmTPC1_CMDQ_CP_CURRENT_INST_HI 0xE49180 + +#define mmTPC1_CMDQ_CP_BARRIER_CFG 0xE49184 + +#define mmTPC1_CMDQ_CP_DBG_0 0xE49188 + +#define mmTPC1_CMDQ_CQ_BUF_ADDR 0xE49308 + +#define mmTPC1_CMDQ_CQ_BUF_RDATA 0xE4930C + +#endif /* ASIC_REG_TPC1_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000..b95de4f95 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48010 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48014 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS 0xE4801C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS 0xE48020 + +#define mmTPC1_QM_GLBL_STS0 0xE48024 + +#define mmTPC1_QM_GLBL_STS1 0xE48028 + +#define mmTPC1_QM_PQ_BASE_LO 0xE48060 + +#define mmTPC1_QM_PQ_BASE_HI 0xE48064 + +#define mmTPC1_QM_PQ_SIZE 0xE48068 + +#define mmTPC1_QM_PQ_PI 0xE4806C + +#define mmTPC1_QM_PQ_CI 0xE48070 + +#define mmTPC1_QM_PQ_CFG0 0xE48074 + +#define mmTPC1_QM_PQ_CFG1 0xE48078 + +#define mmTPC1_QM_PQ_ARUSER 0xE4807C + +#define mmTPC1_QM_PQ_PUSH0 0xE48080 + +#define mmTPC1_QM_PQ_PUSH1 0xE48084 + +#define mmTPC1_QM_PQ_PUSH2 0xE48088 + +#define mmTPC1_QM_PQ_PUSH3 0xE4808C + +#define mmTPC1_QM_PQ_STS0 0xE48090 + +#define mmTPC1_QM_PQ_STS1 0xE48094 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_EN 0xE480A0 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE480A4 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_SAT 0xE480A8 + +#define mmTPC1_QM_PQ_RD_RATE_LIM_TOUT 0xE480AC + +#define mmTPC1_QM_CQ_CFG0 0xE480B0 + +#define mmTPC1_QM_CQ_CFG1 0xE480B4 + +#define mmTPC1_QM_CQ_ARUSER 0xE480B8 + +#define mmTPC1_QM_CQ_PTR_LO 0xE480C0 + +#define mmTPC1_QM_CQ_PTR_HI 0xE480C4 + +#define mmTPC1_QM_CQ_TSIZE 0xE480C8 + +#define mmTPC1_QM_CQ_CTL 0xE480CC + +#define mmTPC1_QM_CQ_PTR_LO_STS 0xE480D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS 0xE480D8 + +#define mmTPC1_QM_CQ_TSIZE_STS 0xE480DC + +#define mmTPC1_QM_CQ_CTL_STS 0xE480E0 + +#define mmTPC1_QM_CQ_STS0 0xE480E4 + +#define mmTPC1_QM_CQ_STS1 0xE480E8 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_EN 0xE480F0 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE480F4 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_SAT 0xE480F8 + +#define mmTPC1_QM_CQ_RD_RATE_LIM_TOUT 0xE480FC + +#define mmTPC1_QM_CQ_IFIFO_CNT 0xE48108 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO 0xE48120 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI 0xE48124 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO 0xE48128 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI 0xE4812C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO 0xE48130 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI 0xE48134 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO 0xE48138 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI 0xE4813C + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET 0xE48140 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE48144 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE48148 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE4814C + +#define mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE48150 + +#define mmTPC1_QM_CP_LDMA_COMMIT_OFFSET 0xE48154 + +#define mmTPC1_QM_CP_FENCE0_RDATA 0xE48158 + +#define mmTPC1_QM_CP_FENCE1_RDATA 0xE4815C + +#define mmTPC1_QM_CP_FENCE2_RDATA 0xE48160 + +#define mmTPC1_QM_CP_FENCE3_RDATA 0xE48164 + +#define mmTPC1_QM_CP_FENCE0_CNT 0xE48168 + +#define mmTPC1_QM_CP_FENCE1_CNT 0xE4816C + +#define mmTPC1_QM_CP_FENCE2_CNT 0xE48170 + +#define mmTPC1_QM_CP_FENCE3_CNT 0xE48174 + +#define mmTPC1_QM_CP_STS 0xE48178 + +#define mmTPC1_QM_CP_CURRENT_INST_LO 0xE4817C + +#define mmTPC1_QM_CP_CURRENT_INST_HI 0xE48180 + +#define mmTPC1_QM_CP_BARRIER_CFG 0xE48184 + +#define mmTPC1_QM_CP_DBG_0 0xE48188 + +#define mmTPC1_QM_PQ_BUF_ADDR 0xE48300 + +#define mmTPC1_QM_PQ_BUF_RDATA 0xE48304 + +#define mmTPC1_QM_CQ_BUF_ADDR 0xE48308 + +#define mmTPC1_QM_CQ_BUF_RDATA 0xE4830C + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h new file mode 100644 index 000000000..0f91e3078 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_RTR_REGS_H_ +#define ASIC_REG_TPC1_RTR_REGS_H_ + +/* + ***************************************** + * TPC1_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC1_RTR_HBW_RD_RQ_E_ARB 0xE40100 + +#define mmTPC1_RTR_HBW_RD_RQ_W_ARB 0xE40104 + +#define mmTPC1_RTR_HBW_RD_RQ_N_ARB 0xE40108 + +#define mmTPC1_RTR_HBW_RD_RQ_S_ARB 0xE4010C + +#define mmTPC1_RTR_HBW_RD_RQ_L_ARB 0xE40110 + +#define mmTPC1_RTR_HBW_E_ARB_MAX 0xE40120 + +#define mmTPC1_RTR_HBW_W_ARB_MAX 0xE40124 + +#define mmTPC1_RTR_HBW_N_ARB_MAX 0xE40128 + +#define mmTPC1_RTR_HBW_S_ARB_MAX 0xE4012C + +#define mmTPC1_RTR_HBW_L_ARB_MAX 0xE40130 + +#define mmTPC1_RTR_HBW_RD_RS_E_ARB 0xE40140 + +#define mmTPC1_RTR_HBW_RD_RS_W_ARB 0xE40144 + +#define mmTPC1_RTR_HBW_RD_RS_N_ARB 0xE40148 + +#define mmTPC1_RTR_HBW_RD_RS_S_ARB 0xE4014C + +#define mmTPC1_RTR_HBW_RD_RS_L_ARB 0xE40150 + +#define mmTPC1_RTR_HBW_WR_RQ_E_ARB 0xE40170 + +#define mmTPC1_RTR_HBW_WR_RQ_W_ARB 0xE40174 + +#define mmTPC1_RTR_HBW_WR_RQ_N_ARB 0xE40178 + +#define mmTPC1_RTR_HBW_WR_RQ_S_ARB 0xE4017C + +#define mmTPC1_RTR_HBW_WR_RQ_L_ARB 0xE40180 + +#define mmTPC1_RTR_HBW_WR_RS_E_ARB 0xE40190 + +#define mmTPC1_RTR_HBW_WR_RS_W_ARB 0xE40194 + +#define mmTPC1_RTR_HBW_WR_RS_N_ARB 0xE40198 + +#define mmTPC1_RTR_HBW_WR_RS_S_ARB 0xE4019C + +#define mmTPC1_RTR_HBW_WR_RS_L_ARB 0xE401A0 + +#define mmTPC1_RTR_LBW_RD_RQ_E_ARB 0xE40200 + +#define mmTPC1_RTR_LBW_RD_RQ_W_ARB 0xE40204 + +#define mmTPC1_RTR_LBW_RD_RQ_N_ARB 0xE40208 + +#define mmTPC1_RTR_LBW_RD_RQ_S_ARB 0xE4020C + +#define mmTPC1_RTR_LBW_RD_RQ_L_ARB 0xE40210 + +#define mmTPC1_RTR_LBW_E_ARB_MAX 0xE40220 + +#define mmTPC1_RTR_LBW_W_ARB_MAX 0xE40224 + +#define mmTPC1_RTR_LBW_N_ARB_MAX 0xE40228 + +#define mmTPC1_RTR_LBW_S_ARB_MAX 0xE4022C + +#define mmTPC1_RTR_LBW_L_ARB_MAX 0xE40230 + +#define mmTPC1_RTR_LBW_RD_RS_E_ARB 0xE40250 + +#define mmTPC1_RTR_LBW_RD_RS_W_ARB 0xE40254 + +#define mmTPC1_RTR_LBW_RD_RS_N_ARB 0xE40258 + +#define mmTPC1_RTR_LBW_RD_RS_S_ARB 0xE4025C + +#define mmTPC1_RTR_LBW_RD_RS_L_ARB 0xE40260 + +#define mmTPC1_RTR_LBW_WR_RQ_E_ARB 0xE40270 + +#define mmTPC1_RTR_LBW_WR_RQ_W_ARB 0xE40274 + +#define mmTPC1_RTR_LBW_WR_RQ_N_ARB 0xE40278 + +#define mmTPC1_RTR_LBW_WR_RQ_S_ARB 0xE4027C + +#define mmTPC1_RTR_LBW_WR_RQ_L_ARB 0xE40280 + +#define mmTPC1_RTR_LBW_WR_RS_E_ARB 0xE40290 + +#define mmTPC1_RTR_LBW_WR_RS_W_ARB 0xE40294 + +#define mmTPC1_RTR_LBW_WR_RS_N_ARB 0xE40298 + +#define mmTPC1_RTR_LBW_WR_RS_S_ARB 0xE4029C + +#define mmTPC1_RTR_LBW_WR_RS_L_ARB 0xE402A0 + +#define mmTPC1_RTR_DBG_E_ARB 0xE40300 + +#define mmTPC1_RTR_DBG_W_ARB 0xE40304 + +#define mmTPC1_RTR_DBG_N_ARB 0xE40308 + +#define mmTPC1_RTR_DBG_S_ARB 0xE4030C + +#define mmTPC1_RTR_DBG_L_ARB 0xE40310 + +#define mmTPC1_RTR_DBG_E_ARB_MAX 0xE40320 + +#define mmTPC1_RTR_DBG_W_ARB_MAX 0xE40324 + +#define mmTPC1_RTR_DBG_N_ARB_MAX 0xE40328 + +#define mmTPC1_RTR_DBG_S_ARB_MAX 0xE4032C + +#define mmTPC1_RTR_DBG_L_ARB_MAX 0xE40330 + +#define mmTPC1_RTR_SPLIT_COEF_0 0xE40400 + +#define mmTPC1_RTR_SPLIT_COEF_1 0xE40404 + +#define mmTPC1_RTR_SPLIT_COEF_2 0xE40408 + +#define mmTPC1_RTR_SPLIT_COEF_3 0xE4040C + +#define mmTPC1_RTR_SPLIT_COEF_4 0xE40410 + +#define mmTPC1_RTR_SPLIT_COEF_5 0xE40414 + +#define mmTPC1_RTR_SPLIT_COEF_6 0xE40418 + +#define mmTPC1_RTR_SPLIT_COEF_7 0xE4041C + +#define mmTPC1_RTR_SPLIT_COEF_8 0xE40420 + +#define mmTPC1_RTR_SPLIT_COEF_9 0xE40424 + +#define mmTPC1_RTR_SPLIT_CFG 0xE40440 + +#define mmTPC1_RTR_SPLIT_RD_SAT 0xE40444 + +#define mmTPC1_RTR_SPLIT_RD_RST_TOKEN 0xE40448 + +#define mmTPC1_RTR_SPLIT_RD_TIMEOUT_0 0xE4044C + +#define mmTPC1_RTR_SPLIT_RD_TIMEOUT_1 0xE40450 + +#define mmTPC1_RTR_SPLIT_WR_SAT 0xE40454 + +#define mmTPC1_RTR_WPLIT_WR_TST_TOLEN 0xE40458 + +#define mmTPC1_RTR_SPLIT_WR_TIMEOUT_0 0xE4045C + +#define mmTPC1_RTR_SPLIT_WR_TIMEOUT_1 0xE40460 + +#define mmTPC1_RTR_HBW_RANGE_HIT 0xE40470 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_0 0xE40480 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_1 0xE40484 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_2 0xE40488 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_3 0xE4048C + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_4 0xE40490 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_5 0xE40494 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_6 0xE40498 + +#define mmTPC1_RTR_HBW_RANGE_MASK_L_7 0xE4049C + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_0 0xE404A0 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_1 0xE404A4 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_2 0xE404A8 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_3 0xE404AC + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_4 0xE404B0 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_5 0xE404B4 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_6 0xE404B8 + +#define mmTPC1_RTR_HBW_RANGE_MASK_H_7 0xE404BC + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_0 0xE404C0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_1 0xE404C4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_2 0xE404C8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_3 0xE404CC + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_4 0xE404D0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_5 0xE404D4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_6 0xE404D8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_L_7 0xE404DC + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_0 0xE404E0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_1 0xE404E4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_2 0xE404E8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_3 0xE404EC + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_4 0xE404F0 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_5 0xE404F4 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_6 0xE404F8 + +#define mmTPC1_RTR_HBW_RANGE_BASE_H_7 0xE404FC + +#define mmTPC1_RTR_LBW_RANGE_HIT 0xE40500 + +#define mmTPC1_RTR_LBW_RANGE_MASK_0 0xE40510 + +#define mmTPC1_RTR_LBW_RANGE_MASK_1 0xE40514 + +#define mmTPC1_RTR_LBW_RANGE_MASK_2 0xE40518 + +#define mmTPC1_RTR_LBW_RANGE_MASK_3 0xE4051C + +#define mmTPC1_RTR_LBW_RANGE_MASK_4 0xE40520 + +#define mmTPC1_RTR_LBW_RANGE_MASK_5 0xE40524 + +#define mmTPC1_RTR_LBW_RANGE_MASK_6 0xE40528 + +#define mmTPC1_RTR_LBW_RANGE_MASK_7 0xE4052C + +#define mmTPC1_RTR_LBW_RANGE_MASK_8 0xE40530 + +#define mmTPC1_RTR_LBW_RANGE_MASK_9 0xE40534 + +#define mmTPC1_RTR_LBW_RANGE_MASK_10 0xE40538 + +#define mmTPC1_RTR_LBW_RANGE_MASK_11 0xE4053C + +#define mmTPC1_RTR_LBW_RANGE_MASK_12 0xE40540 + +#define mmTPC1_RTR_LBW_RANGE_MASK_13 0xE40544 + +#define mmTPC1_RTR_LBW_RANGE_MASK_14 0xE40548 + +#define mmTPC1_RTR_LBW_RANGE_MASK_15 0xE4054C + +#define mmTPC1_RTR_LBW_RANGE_BASE_0 0xE40550 + +#define mmTPC1_RTR_LBW_RANGE_BASE_1 0xE40554 + +#define mmTPC1_RTR_LBW_RANGE_BASE_2 0xE40558 + +#define mmTPC1_RTR_LBW_RANGE_BASE_3 0xE4055C + +#define mmTPC1_RTR_LBW_RANGE_BASE_4 0xE40560 + +#define mmTPC1_RTR_LBW_RANGE_BASE_5 0xE40564 + +#define mmTPC1_RTR_LBW_RANGE_BASE_6 0xE40568 + +#define mmTPC1_RTR_LBW_RANGE_BASE_7 0xE4056C + +#define mmTPC1_RTR_LBW_RANGE_BASE_8 0xE40570 + +#define mmTPC1_RTR_LBW_RANGE_BASE_9 0xE40574 + +#define mmTPC1_RTR_LBW_RANGE_BASE_10 0xE40578 + +#define mmTPC1_RTR_LBW_RANGE_BASE_11 0xE4057C + +#define mmTPC1_RTR_LBW_RANGE_BASE_12 0xE40580 + +#define mmTPC1_RTR_LBW_RANGE_BASE_13 0xE40584 + +#define mmTPC1_RTR_LBW_RANGE_BASE_14 0xE40588 + +#define mmTPC1_RTR_LBW_RANGE_BASE_15 0xE4058C + +#define mmTPC1_RTR_RGLTR 0xE40590 + +#define mmTPC1_RTR_RGLTR_WR_RESULT 0xE40594 + +#define mmTPC1_RTR_RGLTR_RD_RESULT 0xE40598 + +#define mmTPC1_RTR_SCRAMB_EN 0xE40600 + +#define mmTPC1_RTR_NON_LIN_SCRAMB 0xE40604 + +#endif /* ASIC_REG_TPC1_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000..73421227f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE8665C + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86660 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE86664 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86668 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE8666C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86670 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE86674 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE86678 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE8667C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE86680 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE86684 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE86688 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE8668C + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE86690 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE86694 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE86698 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE8669C + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE866A0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE866A4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE866A8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE866AC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE866B0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE866B4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE866B8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE866BC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE866C0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE866C4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE866C8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE866CC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE866D0 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE866D4 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE866D8 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE866DC + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE866E0 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE866E4 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE866E8 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE866EC + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE866F0 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE866F4 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE866F8 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE866FC + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86700 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86704 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86708 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8670C + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE86710 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86714 + +#define mmTPC2_CFG_RESERVED_DESC_END 0xE86738 + +#define mmTPC2_CFG_ROUND_CSR 0xE867FC + +#define mmTPC2_CFG_TBUF_BASE_ADDR_LOW 0xE86800 + +#define mmTPC2_CFG_TBUF_BASE_ADDR_HIGH 0xE86804 + +#define mmTPC2_CFG_SEMAPHORE 0xE86808 + +#define mmTPC2_CFG_VFLAGS 0xE8680C + +#define mmTPC2_CFG_SFLAGS 0xE86810 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86818 + +#define mmTPC2_CFG_STATUS 0xE8681C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86820 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86824 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_LOW 0xE86828 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8682C + +#define mmTPC2_CFG_TPC_CMD 0xE86830 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86838 + +#define mmTPC2_CFG_TPC_STALL 0xE8683C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86840 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86844 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86854 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86858 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8685C + +#define mmTPC2_CFG_TSB_CONFIG 0xE86860 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE86C5C + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86C60 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86C64 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86C68 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86C6C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86C70 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86C74 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86C78 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86C7C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86C80 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86C84 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86C88 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86C8C + +#define mmTPC2_CFG_QM_SRF_0 0xE86C90 + +#define mmTPC2_CFG_QM_SRF_1 0xE86C94 + +#define mmTPC2_CFG_QM_SRF_2 0xE86C98 + +#define mmTPC2_CFG_QM_SRF_3 0xE86C9C + +#define mmTPC2_CFG_QM_SRF_4 0xE86CA0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86CA4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86CA8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86CAC + +#define mmTPC2_CFG_QM_SRF_8 0xE86CB0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86CB4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86CB8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86CBC + +#define mmTPC2_CFG_QM_SRF_12 0xE86CC0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86CC4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86CC8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86CCC + +#define mmTPC2_CFG_QM_SRF_16 0xE86CD0 + +#define mmTPC2_CFG_QM_SRF_17 0xE86CD4 + +#define mmTPC2_CFG_QM_SRF_18 0xE86CD8 + +#define mmTPC2_CFG_QM_SRF_19 0xE86CDC + +#define mmTPC2_CFG_QM_SRF_20 0xE86CE0 + +#define mmTPC2_CFG_QM_SRF_21 0xE86CE4 + +#define mmTPC2_CFG_QM_SRF_22 0xE86CE8 + +#define mmTPC2_CFG_QM_SRF_23 0xE86CEC + +#define mmTPC2_CFG_QM_SRF_24 0xE86CF0 + +#define mmTPC2_CFG_QM_SRF_25 0xE86CF4 + +#define mmTPC2_CFG_QM_SRF_26 0xE86CF8 + +#define mmTPC2_CFG_QM_SRF_27 0xE86CFC + +#define mmTPC2_CFG_QM_SRF_28 0xE86D00 + +#define mmTPC2_CFG_QM_SRF_29 0xE86D04 + +#define mmTPC2_CFG_QM_SRF_30 0xE86D08 + +#define mmTPC2_CFG_QM_SRF_31 0xE86D0C + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86D10 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D14 + +#define mmTPC2_CFG_ARUSER 0xE86D18 + +#define mmTPC2_CFG_AWUSER 0xE86D1C + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE86E00 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE86E04 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE86E08 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE86E0C + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE86E10 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE86E14 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE86E18 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE86E1C + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE86E20 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE86E24 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE86E28 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE86E2C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h new file mode 100644 index 000000000..27b66bf2d --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CMDQ_REGS_H_ +#define ASIC_REG_TPC2_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC2_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC2_CMDQ_GLBL_CFG0 0xE89000 + +#define mmTPC2_CMDQ_GLBL_CFG1 0xE89004 + +#define mmTPC2_CMDQ_GLBL_PROT 0xE89008 + +#define mmTPC2_CMDQ_GLBL_ERR_CFG 0xE8900C + +#define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO 0xE89010 + +#define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI 0xE89014 + +#define mmTPC2_CMDQ_GLBL_ERR_WDATA 0xE89018 + +#define mmTPC2_CMDQ_GLBL_SECURE_PROPS 0xE8901C + +#define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS 0xE89020 + +#define mmTPC2_CMDQ_GLBL_STS0 0xE89024 + +#define mmTPC2_CMDQ_GLBL_STS1 0xE89028 + +#define mmTPC2_CMDQ_CQ_CFG0 0xE890B0 + +#define mmTPC2_CMDQ_CQ_CFG1 0xE890B4 + +#define mmTPC2_CMDQ_CQ_ARUSER 0xE890B8 + +#define mmTPC2_CMDQ_CQ_PTR_LO 0xE890C0 + +#define mmTPC2_CMDQ_CQ_PTR_HI 0xE890C4 + +#define mmTPC2_CMDQ_CQ_TSIZE 0xE890C8 + +#define mmTPC2_CMDQ_CQ_CTL 0xE890CC + +#define mmTPC2_CMDQ_CQ_PTR_LO_STS 0xE890D4 + +#define mmTPC2_CMDQ_CQ_PTR_HI_STS 0xE890D8 + +#define mmTPC2_CMDQ_CQ_TSIZE_STS 0xE890DC + +#define mmTPC2_CMDQ_CQ_CTL_STS 0xE890E0 + +#define mmTPC2_CMDQ_CQ_STS0 0xE890E4 + +#define mmTPC2_CMDQ_CQ_STS1 0xE890E8 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN 0xE890F0 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE890F4 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT 0xE890F8 + +#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE890FC + +#define mmTPC2_CMDQ_CQ_IFIFO_CNT 0xE89108 + +#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE89120 + +#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE89124 + +#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE89128 + +#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE8912C + +#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE89130 + +#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE89134 + +#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE89138 + +#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE8913C + +#define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE89140 + +#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE89144 + +#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE89148 + +#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE8914C + +#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE89150 + +#define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE89154 + +#define mmTPC2_CMDQ_CP_FENCE0_RDATA 0xE89158 + +#define mmTPC2_CMDQ_CP_FENCE1_RDATA 0xE8915C + +#define mmTPC2_CMDQ_CP_FENCE2_RDATA 0xE89160 + +#define mmTPC2_CMDQ_CP_FENCE3_RDATA 0xE89164 + +#define mmTPC2_CMDQ_CP_FENCE0_CNT 0xE89168 + +#define mmTPC2_CMDQ_CP_FENCE1_CNT 0xE8916C + +#define mmTPC2_CMDQ_CP_FENCE2_CNT 0xE89170 + +#define mmTPC2_CMDQ_CP_FENCE3_CNT 0xE89174 + +#define mmTPC2_CMDQ_CP_STS 0xE89178 + +#define mmTPC2_CMDQ_CP_CURRENT_INST_LO 0xE8917C + +#define mmTPC2_CMDQ_CP_CURRENT_INST_HI 0xE89180 + +#define mmTPC2_CMDQ_CP_BARRIER_CFG 0xE89184 + +#define mmTPC2_CMDQ_CP_DBG_0 0xE89188 + +#define mmTPC2_CMDQ_CQ_BUF_ADDR 0xE89308 + +#define mmTPC2_CMDQ_CQ_BUF_RDATA 0xE8930C + +#endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h new file mode 100644 index 000000000..31e5b2f53 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_QM_REGS_H_ +#define ASIC_REG_TPC2_QM_REGS_H_ + +/* + ***************************************** + * TPC2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC2_QM_GLBL_CFG0 0xE88000 + +#define mmTPC2_QM_GLBL_CFG1 0xE88004 + +#define mmTPC2_QM_GLBL_PROT 0xE88008 + +#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C + +#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88010 + +#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88014 + +#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88018 + +#define mmTPC2_QM_GLBL_SECURE_PROPS 0xE8801C + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS 0xE88020 + +#define mmTPC2_QM_GLBL_STS0 0xE88024 + +#define mmTPC2_QM_GLBL_STS1 0xE88028 + +#define mmTPC2_QM_PQ_BASE_LO 0xE88060 + +#define mmTPC2_QM_PQ_BASE_HI 0xE88064 + +#define mmTPC2_QM_PQ_SIZE 0xE88068 + +#define mmTPC2_QM_PQ_PI 0xE8806C + +#define mmTPC2_QM_PQ_CI 0xE88070 + +#define mmTPC2_QM_PQ_CFG0 0xE88074 + +#define mmTPC2_QM_PQ_CFG1 0xE88078 + +#define mmTPC2_QM_PQ_ARUSER 0xE8807C + +#define mmTPC2_QM_PQ_PUSH0 0xE88080 + +#define mmTPC2_QM_PQ_PUSH1 0xE88084 + +#define mmTPC2_QM_PQ_PUSH2 0xE88088 + +#define mmTPC2_QM_PQ_PUSH3 0xE8808C + +#define mmTPC2_QM_PQ_STS0 0xE88090 + +#define mmTPC2_QM_PQ_STS1 0xE88094 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_EN 0xE880A0 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE880A4 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_SAT 0xE880A8 + +#define mmTPC2_QM_PQ_RD_RATE_LIM_TOUT 0xE880AC + +#define mmTPC2_QM_CQ_CFG0 0xE880B0 + +#define mmTPC2_QM_CQ_CFG1 0xE880B4 + +#define mmTPC2_QM_CQ_ARUSER 0xE880B8 + +#define mmTPC2_QM_CQ_PTR_LO 0xE880C0 + +#define mmTPC2_QM_CQ_PTR_HI 0xE880C4 + +#define mmTPC2_QM_CQ_TSIZE 0xE880C8 + +#define mmTPC2_QM_CQ_CTL 0xE880CC + +#define mmTPC2_QM_CQ_PTR_LO_STS 0xE880D4 + +#define mmTPC2_QM_CQ_PTR_HI_STS 0xE880D8 + +#define mmTPC2_QM_CQ_TSIZE_STS 0xE880DC + +#define mmTPC2_QM_CQ_CTL_STS 0xE880E0 + +#define mmTPC2_QM_CQ_STS0 0xE880E4 + +#define mmTPC2_QM_CQ_STS1 0xE880E8 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_EN 0xE880F0 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE880F4 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_SAT 0xE880F8 + +#define mmTPC2_QM_CQ_RD_RATE_LIM_TOUT 0xE880FC + +#define mmTPC2_QM_CQ_IFIFO_CNT 0xE88108 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO 0xE88120 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI 0xE88124 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO 0xE88128 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI 0xE8812C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO 0xE88130 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI 0xE88134 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO 0xE88138 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI 0xE8813C + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET 0xE88140 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE88144 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE88148 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE8814C + +#define mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE88150 + +#define mmTPC2_QM_CP_LDMA_COMMIT_OFFSET 0xE88154 + +#define mmTPC2_QM_CP_FENCE0_RDATA 0xE88158 + +#define mmTPC2_QM_CP_FENCE1_RDATA 0xE8815C + +#define mmTPC2_QM_CP_FENCE2_RDATA 0xE88160 + +#define mmTPC2_QM_CP_FENCE3_RDATA 0xE88164 + +#define mmTPC2_QM_CP_FENCE0_CNT 0xE88168 + +#define mmTPC2_QM_CP_FENCE1_CNT 0xE8816C + +#define mmTPC2_QM_CP_FENCE2_CNT 0xE88170 + +#define mmTPC2_QM_CP_FENCE3_CNT 0xE88174 + +#define mmTPC2_QM_CP_STS 0xE88178 + +#define mmTPC2_QM_CP_CURRENT_INST_LO 0xE8817C + +#define mmTPC2_QM_CP_CURRENT_INST_HI 0xE88180 + +#define mmTPC2_QM_CP_BARRIER_CFG 0xE88184 + +#define mmTPC2_QM_CP_DBG_0 0xE88188 + +#define mmTPC2_QM_PQ_BUF_ADDR 0xE88300 + +#define mmTPC2_QM_PQ_BUF_RDATA 0xE88304 + +#define mmTPC2_QM_CQ_BUF_ADDR 0xE88308 + +#define mmTPC2_QM_CQ_BUF_RDATA 0xE8830C + +#endif /* ASIC_REG_TPC2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h new file mode 100644 index 000000000..4eddeaa15 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_RTR_REGS_H_ +#define ASIC_REG_TPC2_RTR_REGS_H_ + +/* + ***************************************** + * TPC2_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC2_RTR_HBW_RD_RQ_E_ARB 0xE80100 + +#define mmTPC2_RTR_HBW_RD_RQ_W_ARB 0xE80104 + +#define mmTPC2_RTR_HBW_RD_RQ_N_ARB 0xE80108 + +#define mmTPC2_RTR_HBW_RD_RQ_S_ARB 0xE8010C + +#define mmTPC2_RTR_HBW_RD_RQ_L_ARB 0xE80110 + +#define mmTPC2_RTR_HBW_E_ARB_MAX 0xE80120 + +#define mmTPC2_RTR_HBW_W_ARB_MAX 0xE80124 + +#define mmTPC2_RTR_HBW_N_ARB_MAX 0xE80128 + +#define mmTPC2_RTR_HBW_S_ARB_MAX 0xE8012C + +#define mmTPC2_RTR_HBW_L_ARB_MAX 0xE80130 + +#define mmTPC2_RTR_HBW_RD_RS_E_ARB 0xE80140 + +#define mmTPC2_RTR_HBW_RD_RS_W_ARB 0xE80144 + +#define mmTPC2_RTR_HBW_RD_RS_N_ARB 0xE80148 + +#define mmTPC2_RTR_HBW_RD_RS_S_ARB 0xE8014C + +#define mmTPC2_RTR_HBW_RD_RS_L_ARB 0xE80150 + +#define mmTPC2_RTR_HBW_WR_RQ_E_ARB 0xE80170 + +#define mmTPC2_RTR_HBW_WR_RQ_W_ARB 0xE80174 + +#define mmTPC2_RTR_HBW_WR_RQ_N_ARB 0xE80178 + +#define mmTPC2_RTR_HBW_WR_RQ_S_ARB 0xE8017C + +#define mmTPC2_RTR_HBW_WR_RQ_L_ARB 0xE80180 + +#define mmTPC2_RTR_HBW_WR_RS_E_ARB 0xE80190 + +#define mmTPC2_RTR_HBW_WR_RS_W_ARB 0xE80194 + +#define mmTPC2_RTR_HBW_WR_RS_N_ARB 0xE80198 + +#define mmTPC2_RTR_HBW_WR_RS_S_ARB 0xE8019C + +#define mmTPC2_RTR_HBW_WR_RS_L_ARB 0xE801A0 + +#define mmTPC2_RTR_LBW_RD_RQ_E_ARB 0xE80200 + +#define mmTPC2_RTR_LBW_RD_RQ_W_ARB 0xE80204 + +#define mmTPC2_RTR_LBW_RD_RQ_N_ARB 0xE80208 + +#define mmTPC2_RTR_LBW_RD_RQ_S_ARB 0xE8020C + +#define mmTPC2_RTR_LBW_RD_RQ_L_ARB 0xE80210 + +#define mmTPC2_RTR_LBW_E_ARB_MAX 0xE80220 + +#define mmTPC2_RTR_LBW_W_ARB_MAX 0xE80224 + +#define mmTPC2_RTR_LBW_N_ARB_MAX 0xE80228 + +#define mmTPC2_RTR_LBW_S_ARB_MAX 0xE8022C + +#define mmTPC2_RTR_LBW_L_ARB_MAX 0xE80230 + +#define mmTPC2_RTR_LBW_RD_RS_E_ARB 0xE80250 + +#define mmTPC2_RTR_LBW_RD_RS_W_ARB 0xE80254 + +#define mmTPC2_RTR_LBW_RD_RS_N_ARB 0xE80258 + +#define mmTPC2_RTR_LBW_RD_RS_S_ARB 0xE8025C + +#define mmTPC2_RTR_LBW_RD_RS_L_ARB 0xE80260 + +#define mmTPC2_RTR_LBW_WR_RQ_E_ARB 0xE80270 + +#define mmTPC2_RTR_LBW_WR_RQ_W_ARB 0xE80274 + +#define mmTPC2_RTR_LBW_WR_RQ_N_ARB 0xE80278 + +#define mmTPC2_RTR_LBW_WR_RQ_S_ARB 0xE8027C + +#define mmTPC2_RTR_LBW_WR_RQ_L_ARB 0xE80280 + +#define mmTPC2_RTR_LBW_WR_RS_E_ARB 0xE80290 + +#define mmTPC2_RTR_LBW_WR_RS_W_ARB 0xE80294 + +#define mmTPC2_RTR_LBW_WR_RS_N_ARB 0xE80298 + +#define mmTPC2_RTR_LBW_WR_RS_S_ARB 0xE8029C + +#define mmTPC2_RTR_LBW_WR_RS_L_ARB 0xE802A0 + +#define mmTPC2_RTR_DBG_E_ARB 0xE80300 + +#define mmTPC2_RTR_DBG_W_ARB 0xE80304 + +#define mmTPC2_RTR_DBG_N_ARB 0xE80308 + +#define mmTPC2_RTR_DBG_S_ARB 0xE8030C + +#define mmTPC2_RTR_DBG_L_ARB 0xE80310 + +#define mmTPC2_RTR_DBG_E_ARB_MAX 0xE80320 + +#define mmTPC2_RTR_DBG_W_ARB_MAX 0xE80324 + +#define mmTPC2_RTR_DBG_N_ARB_MAX 0xE80328 + +#define mmTPC2_RTR_DBG_S_ARB_MAX 0xE8032C + +#define mmTPC2_RTR_DBG_L_ARB_MAX 0xE80330 + +#define mmTPC2_RTR_SPLIT_COEF_0 0xE80400 + +#define mmTPC2_RTR_SPLIT_COEF_1 0xE80404 + +#define mmTPC2_RTR_SPLIT_COEF_2 0xE80408 + +#define mmTPC2_RTR_SPLIT_COEF_3 0xE8040C + +#define mmTPC2_RTR_SPLIT_COEF_4 0xE80410 + +#define mmTPC2_RTR_SPLIT_COEF_5 0xE80414 + +#define mmTPC2_RTR_SPLIT_COEF_6 0xE80418 + +#define mmTPC2_RTR_SPLIT_COEF_7 0xE8041C + +#define mmTPC2_RTR_SPLIT_COEF_8 0xE80420 + +#define mmTPC2_RTR_SPLIT_COEF_9 0xE80424 + +#define mmTPC2_RTR_SPLIT_CFG 0xE80440 + +#define mmTPC2_RTR_SPLIT_RD_SAT 0xE80444 + +#define mmTPC2_RTR_SPLIT_RD_RST_TOKEN 0xE80448 + +#define mmTPC2_RTR_SPLIT_RD_TIMEOUT_0 0xE8044C + +#define mmTPC2_RTR_SPLIT_RD_TIMEOUT_1 0xE80450 + +#define mmTPC2_RTR_SPLIT_WR_SAT 0xE80454 + +#define mmTPC2_RTR_WPLIT_WR_TST_TOLEN 0xE80458 + +#define mmTPC2_RTR_SPLIT_WR_TIMEOUT_0 0xE8045C + +#define mmTPC2_RTR_SPLIT_WR_TIMEOUT_1 0xE80460 + +#define mmTPC2_RTR_HBW_RANGE_HIT 0xE80470 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_0 0xE80480 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_1 0xE80484 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_2 0xE80488 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_3 0xE8048C + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_4 0xE80490 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_5 0xE80494 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_6 0xE80498 + +#define mmTPC2_RTR_HBW_RANGE_MASK_L_7 0xE8049C + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_0 0xE804A0 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_1 0xE804A4 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_2 0xE804A8 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_3 0xE804AC + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_4 0xE804B0 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_5 0xE804B4 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_6 0xE804B8 + +#define mmTPC2_RTR_HBW_RANGE_MASK_H_7 0xE804BC + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_0 0xE804C0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_1 0xE804C4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_2 0xE804C8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_3 0xE804CC + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_4 0xE804D0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_5 0xE804D4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_6 0xE804D8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_L_7 0xE804DC + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_0 0xE804E0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_1 0xE804E4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_2 0xE804E8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_3 0xE804EC + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_4 0xE804F0 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_5 0xE804F4 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_6 0xE804F8 + +#define mmTPC2_RTR_HBW_RANGE_BASE_H_7 0xE804FC + +#define mmTPC2_RTR_LBW_RANGE_HIT 0xE80500 + +#define mmTPC2_RTR_LBW_RANGE_MASK_0 0xE80510 + +#define mmTPC2_RTR_LBW_RANGE_MASK_1 0xE80514 + +#define mmTPC2_RTR_LBW_RANGE_MASK_2 0xE80518 + +#define mmTPC2_RTR_LBW_RANGE_MASK_3 0xE8051C + +#define mmTPC2_RTR_LBW_RANGE_MASK_4 0xE80520 + +#define mmTPC2_RTR_LBW_RANGE_MASK_5 0xE80524 + +#define mmTPC2_RTR_LBW_RANGE_MASK_6 0xE80528 + +#define mmTPC2_RTR_LBW_RANGE_MASK_7 0xE8052C + +#define mmTPC2_RTR_LBW_RANGE_MASK_8 0xE80530 + +#define mmTPC2_RTR_LBW_RANGE_MASK_9 0xE80534 + +#define mmTPC2_RTR_LBW_RANGE_MASK_10 0xE80538 + +#define mmTPC2_RTR_LBW_RANGE_MASK_11 0xE8053C + +#define mmTPC2_RTR_LBW_RANGE_MASK_12 0xE80540 + +#define mmTPC2_RTR_LBW_RANGE_MASK_13 0xE80544 + +#define mmTPC2_RTR_LBW_RANGE_MASK_14 0xE80548 + +#define mmTPC2_RTR_LBW_RANGE_MASK_15 0xE8054C + +#define mmTPC2_RTR_LBW_RANGE_BASE_0 0xE80550 + +#define mmTPC2_RTR_LBW_RANGE_BASE_1 0xE80554 + +#define mmTPC2_RTR_LBW_RANGE_BASE_2 0xE80558 + +#define mmTPC2_RTR_LBW_RANGE_BASE_3 0xE8055C + +#define mmTPC2_RTR_LBW_RANGE_BASE_4 0xE80560 + +#define mmTPC2_RTR_LBW_RANGE_BASE_5 0xE80564 + +#define mmTPC2_RTR_LBW_RANGE_BASE_6 0xE80568 + +#define mmTPC2_RTR_LBW_RANGE_BASE_7 0xE8056C + +#define mmTPC2_RTR_LBW_RANGE_BASE_8 0xE80570 + +#define mmTPC2_RTR_LBW_RANGE_BASE_9 0xE80574 + +#define mmTPC2_RTR_LBW_RANGE_BASE_10 0xE80578 + +#define mmTPC2_RTR_LBW_RANGE_BASE_11 0xE8057C + +#define mmTPC2_RTR_LBW_RANGE_BASE_12 0xE80580 + +#define mmTPC2_RTR_LBW_RANGE_BASE_13 0xE80584 + +#define mmTPC2_RTR_LBW_RANGE_BASE_14 0xE80588 + +#define mmTPC2_RTR_LBW_RANGE_BASE_15 0xE8058C + +#define mmTPC2_RTR_RGLTR 0xE80590 + +#define mmTPC2_RTR_RGLTR_WR_RESULT 0xE80594 + +#define mmTPC2_RTR_RGLTR_RD_RESULT 0xE80598 + +#define mmTPC2_RTR_SCRAMB_EN 0xE80600 + +#define mmTPC2_RTR_NON_LIN_SCRAMB 0xE80604 + +#endif /* ASIC_REG_TPC2_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h new file mode 100644 index 000000000..ce573a1a8 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CFG_REGS_H_ +#define ASIC_REG_TPC3_CFG_REGS_H_ + +/* + ***************************************** + * TPC3_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xEC6418 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC641C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC6420 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xEC6424 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6428 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC642C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xEC6430 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6434 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC6438 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xEC643C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6440 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6444 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xEC6448 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC644C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC6450 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6454 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6458 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC645C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC6460 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xEC6464 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6468 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC646C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xEC6470 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6474 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC6478 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xEC647C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6480 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6484 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xEC6488 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC648C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC6490 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xEC6494 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6498 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC649C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC64A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC64A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC64A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC64AC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xEC64B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC64B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC64B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xEC64BC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC64C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC64C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xEC64C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC64CC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC64D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xEC64D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64DC + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xEC64E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64EC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xEC64FC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC6500 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC6504 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6508 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC650C + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC6510 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6514 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC6518 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC651C + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6520 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC6524 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC6528 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xEC652C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC6530 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC6534 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC6538 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC653C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC6540 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC6544 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6548 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC654C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC6550 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6554 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6558 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC655C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6560 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6564 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC6568 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xEC656C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6570 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6574 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6578 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC657C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC6580 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6584 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6588 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC658C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC6590 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6594 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6598 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC659C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xEC65A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC65A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC65A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xEC65AC + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC65B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC65B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xEC65B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC65BC + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC65C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xEC65C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC65C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC65CC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC65D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC65D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC65D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC65DC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xEC65E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC65E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC65E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xEC65EC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC65F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC65F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xEC65F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC65FC + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC6600 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6604 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6608 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC660C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6610 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6614 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC6618 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC661C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6620 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6624 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC6628 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xEC662C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC6630 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC6634 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6638 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC663C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC6640 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6644 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC6648 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC664C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6650 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC6654 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC6658 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xEC665C + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6660 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC6664 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6668 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC666C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6670 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC6674 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC6678 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC667C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC6680 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC6684 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC6688 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC668C + +#define mmTPC3_CFG_KERNEL_SRF_0 0xEC6690 + +#define mmTPC3_CFG_KERNEL_SRF_1 0xEC6694 + +#define mmTPC3_CFG_KERNEL_SRF_2 0xEC6698 + +#define mmTPC3_CFG_KERNEL_SRF_3 0xEC669C + +#define mmTPC3_CFG_KERNEL_SRF_4 0xEC66A0 + +#define mmTPC3_CFG_KERNEL_SRF_5 0xEC66A4 + +#define mmTPC3_CFG_KERNEL_SRF_6 0xEC66A8 + +#define mmTPC3_CFG_KERNEL_SRF_7 0xEC66AC + +#define mmTPC3_CFG_KERNEL_SRF_8 0xEC66B0 + +#define mmTPC3_CFG_KERNEL_SRF_9 0xEC66B4 + +#define mmTPC3_CFG_KERNEL_SRF_10 0xEC66B8 + +#define mmTPC3_CFG_KERNEL_SRF_11 0xEC66BC + +#define mmTPC3_CFG_KERNEL_SRF_12 0xEC66C0 + +#define mmTPC3_CFG_KERNEL_SRF_13 0xEC66C4 + +#define mmTPC3_CFG_KERNEL_SRF_14 0xEC66C8 + +#define mmTPC3_CFG_KERNEL_SRF_15 0xEC66CC + +#define mmTPC3_CFG_KERNEL_SRF_16 0xEC66D0 + +#define mmTPC3_CFG_KERNEL_SRF_17 0xEC66D4 + +#define mmTPC3_CFG_KERNEL_SRF_18 0xEC66D8 + +#define mmTPC3_CFG_KERNEL_SRF_19 0xEC66DC + +#define mmTPC3_CFG_KERNEL_SRF_20 0xEC66E0 + +#define mmTPC3_CFG_KERNEL_SRF_21 0xEC66E4 + +#define mmTPC3_CFG_KERNEL_SRF_22 0xEC66E8 + +#define mmTPC3_CFG_KERNEL_SRF_23 0xEC66EC + +#define mmTPC3_CFG_KERNEL_SRF_24 0xEC66F0 + +#define mmTPC3_CFG_KERNEL_SRF_25 0xEC66F4 + +#define mmTPC3_CFG_KERNEL_SRF_26 0xEC66F8 + +#define mmTPC3_CFG_KERNEL_SRF_27 0xEC66FC + +#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6700 + +#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6704 + +#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6708 + +#define mmTPC3_CFG_KERNEL_SRF_31 0xEC670C + +#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC6710 + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6714 + +#define mmTPC3_CFG_RESERVED_DESC_END 0xEC6738 + +#define mmTPC3_CFG_ROUND_CSR 0xEC67FC + +#define mmTPC3_CFG_TBUF_BASE_ADDR_LOW 0xEC6800 + +#define mmTPC3_CFG_TBUF_BASE_ADDR_HIGH 0xEC6804 + +#define mmTPC3_CFG_SEMAPHORE 0xEC6808 + +#define mmTPC3_CFG_VFLAGS 0xEC680C + +#define mmTPC3_CFG_SFLAGS 0xEC6810 + +#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6818 + +#define mmTPC3_CFG_STATUS 0xEC681C + +#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6820 + +#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6824 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_LOW 0xEC6828 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC682C + +#define mmTPC3_CFG_TPC_CMD 0xEC6830 + +#define mmTPC3_CFG_TPC_EXECUTE 0xEC6838 + +#define mmTPC3_CFG_TPC_STALL 0xEC683C + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6840 + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6844 + +#define mmTPC3_CFG_MSS_CONFIG 0xEC6854 + +#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6858 + +#define mmTPC3_CFG_TPC_INTR_MASK 0xEC685C + +#define mmTPC3_CFG_TSB_CONFIG 0xEC6860 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 + +#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 + +#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xEC6A18 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A1C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A20 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xEC6A24 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A28 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A2C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xEC6A30 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A34 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A38 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xEC6A3C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A40 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A44 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xEC6A48 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A4C + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A50 + +#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A54 + +#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A58 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A5C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A60 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xEC6A64 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A68 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A6C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xEC6A70 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A74 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A78 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xEC6A7C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A80 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A84 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xEC6A88 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A8C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A90 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xEC6A94 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A98 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A9C + +#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6AA0 + +#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6AA4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6AA8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6AAC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xEC6AB0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6AB4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6AB8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xEC6ABC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6AC0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6AC4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xEC6AC8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6ACC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6AD0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xEC6AD4 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AD8 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6ADC + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xEC6AE0 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AE4 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AE8 + +#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AEC + +#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AF0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AF4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6AF8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xEC6AFC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6B00 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6B04 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6B08 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6B0C + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6B10 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6B14 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6B18 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6B1C + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6B20 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6B24 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6B28 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xEC6B2C + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6B30 + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6B34 + +#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6B38 + +#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6B3C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6B40 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6B44 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6B48 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6B4C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6B50 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6B54 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B58 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B5C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6B60 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B64 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B68 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xEC6B6C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B70 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B74 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6B78 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B7C + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B80 + +#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B84 + +#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B88 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B8C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B90 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6B94 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B98 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B9C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xEC6BA0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6BA4 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6BA8 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xEC6BAC + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6BB0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6BB4 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xEC6BB8 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6BBC + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6BC0 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xEC6BC4 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6BC8 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6BCC + +#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6BD0 + +#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6BD4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6BD8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6BDC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xEC6BE0 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6BE4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6BE8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xEC6BEC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6BF0 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6BF4 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xEC6BF8 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6BFC + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6C00 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6C04 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6C08 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6C0C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6C10 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6C14 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6C18 + +#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6C1C + +#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6C20 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6C24 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6C28 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xEC6C2C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6C30 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6C34 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6C38 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6C3C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6C40 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6C44 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6C48 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6C4C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6C50 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6C54 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6C58 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xEC6C5C + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6C60 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6C64 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6C68 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6C6C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6C70 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6C74 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6C78 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6C7C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6C80 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6C84 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6C88 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6C8C + +#define mmTPC3_CFG_QM_SRF_0 0xEC6C90 + +#define mmTPC3_CFG_QM_SRF_1 0xEC6C94 + +#define mmTPC3_CFG_QM_SRF_2 0xEC6C98 + +#define mmTPC3_CFG_QM_SRF_3 0xEC6C9C + +#define mmTPC3_CFG_QM_SRF_4 0xEC6CA0 + +#define mmTPC3_CFG_QM_SRF_5 0xEC6CA4 + +#define mmTPC3_CFG_QM_SRF_6 0xEC6CA8 + +#define mmTPC3_CFG_QM_SRF_7 0xEC6CAC + +#define mmTPC3_CFG_QM_SRF_8 0xEC6CB0 + +#define mmTPC3_CFG_QM_SRF_9 0xEC6CB4 + +#define mmTPC3_CFG_QM_SRF_10 0xEC6CB8 + +#define mmTPC3_CFG_QM_SRF_11 0xEC6CBC + +#define mmTPC3_CFG_QM_SRF_12 0xEC6CC0 + +#define mmTPC3_CFG_QM_SRF_13 0xEC6CC4 + +#define mmTPC3_CFG_QM_SRF_14 0xEC6CC8 + +#define mmTPC3_CFG_QM_SRF_15 0xEC6CCC + +#define mmTPC3_CFG_QM_SRF_16 0xEC6CD0 + +#define mmTPC3_CFG_QM_SRF_17 0xEC6CD4 + +#define mmTPC3_CFG_QM_SRF_18 0xEC6CD8 + +#define mmTPC3_CFG_QM_SRF_19 0xEC6CDC + +#define mmTPC3_CFG_QM_SRF_20 0xEC6CE0 + +#define mmTPC3_CFG_QM_SRF_21 0xEC6CE4 + +#define mmTPC3_CFG_QM_SRF_22 0xEC6CE8 + +#define mmTPC3_CFG_QM_SRF_23 0xEC6CEC + +#define mmTPC3_CFG_QM_SRF_24 0xEC6CF0 + +#define mmTPC3_CFG_QM_SRF_25 0xEC6CF4 + +#define mmTPC3_CFG_QM_SRF_26 0xEC6CF8 + +#define mmTPC3_CFG_QM_SRF_27 0xEC6CFC + +#define mmTPC3_CFG_QM_SRF_28 0xEC6D00 + +#define mmTPC3_CFG_QM_SRF_29 0xEC6D04 + +#define mmTPC3_CFG_QM_SRF_30 0xEC6D08 + +#define mmTPC3_CFG_QM_SRF_31 0xEC6D0C + +#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6D10 + +#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D14 + +#define mmTPC3_CFG_ARUSER 0xEC6D18 + +#define mmTPC3_CFG_AWUSER 0xEC6D1C + +#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC6E00 + +#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC6E04 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC6E08 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC6E0C + +#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC6E10 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC6E14 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC6E18 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC6E1C + +#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC6E20 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC6E24 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC6E28 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC6E2C + +#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h new file mode 100644 index 000000000..11d81fca0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CMDQ_REGS_H_ +#define ASIC_REG_TPC3_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC3_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC3_CMDQ_GLBL_CFG0 0xEC9000 + +#define mmTPC3_CMDQ_GLBL_CFG1 0xEC9004 + +#define mmTPC3_CMDQ_GLBL_PROT 0xEC9008 + +#define mmTPC3_CMDQ_GLBL_ERR_CFG 0xEC900C + +#define mmTPC3_CMDQ_GLBL_ERR_ADDR_LO 0xEC9010 + +#define mmTPC3_CMDQ_GLBL_ERR_ADDR_HI 0xEC9014 + +#define mmTPC3_CMDQ_GLBL_ERR_WDATA 0xEC9018 + +#define mmTPC3_CMDQ_GLBL_SECURE_PROPS 0xEC901C + +#define mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS 0xEC9020 + +#define mmTPC3_CMDQ_GLBL_STS0 0xEC9024 + +#define mmTPC3_CMDQ_GLBL_STS1 0xEC9028 + +#define mmTPC3_CMDQ_CQ_CFG0 0xEC90B0 + +#define mmTPC3_CMDQ_CQ_CFG1 0xEC90B4 + +#define mmTPC3_CMDQ_CQ_ARUSER 0xEC90B8 + +#define mmTPC3_CMDQ_CQ_PTR_LO 0xEC90C0 + +#define mmTPC3_CMDQ_CQ_PTR_HI 0xEC90C4 + +#define mmTPC3_CMDQ_CQ_TSIZE 0xEC90C8 + +#define mmTPC3_CMDQ_CQ_CTL 0xEC90CC + +#define mmTPC3_CMDQ_CQ_PTR_LO_STS 0xEC90D4 + +#define mmTPC3_CMDQ_CQ_PTR_HI_STS 0xEC90D8 + +#define mmTPC3_CMDQ_CQ_TSIZE_STS 0xEC90DC + +#define mmTPC3_CMDQ_CQ_CTL_STS 0xEC90E0 + +#define mmTPC3_CMDQ_CQ_STS0 0xEC90E4 + +#define mmTPC3_CMDQ_CQ_STS1 0xEC90E8 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN 0xEC90F0 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xEC90F4 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT 0xEC90F8 + +#define mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT 0xEC90FC + +#define mmTPC3_CMDQ_CQ_IFIFO_CNT 0xEC9108 + +#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO 0xEC9120 + +#define mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI 0xEC9124 + +#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO 0xEC9128 + +#define mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI 0xEC912C + +#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO 0xEC9130 + +#define mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI 0xEC9134 + +#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO 0xEC9138 + +#define mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI 0xEC913C + +#define mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET 0xEC9140 + +#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xEC9144 + +#define mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xEC9148 + +#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xEC914C + +#define mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xEC9150 + +#define mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET 0xEC9154 + +#define mmTPC3_CMDQ_CP_FENCE0_RDATA 0xEC9158 + +#define mmTPC3_CMDQ_CP_FENCE1_RDATA 0xEC915C + +#define mmTPC3_CMDQ_CP_FENCE2_RDATA 0xEC9160 + +#define mmTPC3_CMDQ_CP_FENCE3_RDATA 0xEC9164 + +#define mmTPC3_CMDQ_CP_FENCE0_CNT 0xEC9168 + +#define mmTPC3_CMDQ_CP_FENCE1_CNT 0xEC916C + +#define mmTPC3_CMDQ_CP_FENCE2_CNT 0xEC9170 + +#define mmTPC3_CMDQ_CP_FENCE3_CNT 0xEC9174 + +#define mmTPC3_CMDQ_CP_STS 0xEC9178 + +#define mmTPC3_CMDQ_CP_CURRENT_INST_LO 0xEC917C + +#define mmTPC3_CMDQ_CP_CURRENT_INST_HI 0xEC9180 + +#define mmTPC3_CMDQ_CP_BARRIER_CFG 0xEC9184 + +#define mmTPC3_CMDQ_CP_DBG_0 0xEC9188 + +#define mmTPC3_CMDQ_CQ_BUF_ADDR 0xEC9308 + +#define mmTPC3_CMDQ_CQ_BUF_RDATA 0xEC930C + +#endif /* ASIC_REG_TPC3_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h new file mode 100644 index 000000000..e41595a19 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_QM_REGS_H_ +#define ASIC_REG_TPC3_QM_REGS_H_ + +/* + ***************************************** + * TPC3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC3_QM_GLBL_CFG0 0xEC8000 + +#define mmTPC3_QM_GLBL_CFG1 0xEC8004 + +#define mmTPC3_QM_GLBL_PROT 0xEC8008 + +#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C + +#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8010 + +#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8014 + +#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8018 + +#define mmTPC3_QM_GLBL_SECURE_PROPS 0xEC801C + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS 0xEC8020 + +#define mmTPC3_QM_GLBL_STS0 0xEC8024 + +#define mmTPC3_QM_GLBL_STS1 0xEC8028 + +#define mmTPC3_QM_PQ_BASE_LO 0xEC8060 + +#define mmTPC3_QM_PQ_BASE_HI 0xEC8064 + +#define mmTPC3_QM_PQ_SIZE 0xEC8068 + +#define mmTPC3_QM_PQ_PI 0xEC806C + +#define mmTPC3_QM_PQ_CI 0xEC8070 + +#define mmTPC3_QM_PQ_CFG0 0xEC8074 + +#define mmTPC3_QM_PQ_CFG1 0xEC8078 + +#define mmTPC3_QM_PQ_ARUSER 0xEC807C + +#define mmTPC3_QM_PQ_PUSH0 0xEC8080 + +#define mmTPC3_QM_PQ_PUSH1 0xEC8084 + +#define mmTPC3_QM_PQ_PUSH2 0xEC8088 + +#define mmTPC3_QM_PQ_PUSH3 0xEC808C + +#define mmTPC3_QM_PQ_STS0 0xEC8090 + +#define mmTPC3_QM_PQ_STS1 0xEC8094 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_EN 0xEC80A0 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xEC80A4 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_SAT 0xEC80A8 + +#define mmTPC3_QM_PQ_RD_RATE_LIM_TOUT 0xEC80AC + +#define mmTPC3_QM_CQ_CFG0 0xEC80B0 + +#define mmTPC3_QM_CQ_CFG1 0xEC80B4 + +#define mmTPC3_QM_CQ_ARUSER 0xEC80B8 + +#define mmTPC3_QM_CQ_PTR_LO 0xEC80C0 + +#define mmTPC3_QM_CQ_PTR_HI 0xEC80C4 + +#define mmTPC3_QM_CQ_TSIZE 0xEC80C8 + +#define mmTPC3_QM_CQ_CTL 0xEC80CC + +#define mmTPC3_QM_CQ_PTR_LO_STS 0xEC80D4 + +#define mmTPC3_QM_CQ_PTR_HI_STS 0xEC80D8 + +#define mmTPC3_QM_CQ_TSIZE_STS 0xEC80DC + +#define mmTPC3_QM_CQ_CTL_STS 0xEC80E0 + +#define mmTPC3_QM_CQ_STS0 0xEC80E4 + +#define mmTPC3_QM_CQ_STS1 0xEC80E8 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_EN 0xEC80F0 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xEC80F4 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_SAT 0xEC80F8 + +#define mmTPC3_QM_CQ_RD_RATE_LIM_TOUT 0xEC80FC + +#define mmTPC3_QM_CQ_IFIFO_CNT 0xEC8108 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO 0xEC8120 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI 0xEC8124 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO 0xEC8128 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI 0xEC812C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO 0xEC8130 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI 0xEC8134 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO 0xEC8138 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI 0xEC813C + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET 0xEC8140 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xEC8144 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xEC8148 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xEC814C + +#define mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xEC8150 + +#define mmTPC3_QM_CP_LDMA_COMMIT_OFFSET 0xEC8154 + +#define mmTPC3_QM_CP_FENCE0_RDATA 0xEC8158 + +#define mmTPC3_QM_CP_FENCE1_RDATA 0xEC815C + +#define mmTPC3_QM_CP_FENCE2_RDATA 0xEC8160 + +#define mmTPC3_QM_CP_FENCE3_RDATA 0xEC8164 + +#define mmTPC3_QM_CP_FENCE0_CNT 0xEC8168 + +#define mmTPC3_QM_CP_FENCE1_CNT 0xEC816C + +#define mmTPC3_QM_CP_FENCE2_CNT 0xEC8170 + +#define mmTPC3_QM_CP_FENCE3_CNT 0xEC8174 + +#define mmTPC3_QM_CP_STS 0xEC8178 + +#define mmTPC3_QM_CP_CURRENT_INST_LO 0xEC817C + +#define mmTPC3_QM_CP_CURRENT_INST_HI 0xEC8180 + +#define mmTPC3_QM_CP_BARRIER_CFG 0xEC8184 + +#define mmTPC3_QM_CP_DBG_0 0xEC8188 + +#define mmTPC3_QM_PQ_BUF_ADDR 0xEC8300 + +#define mmTPC3_QM_PQ_BUF_RDATA 0xEC8304 + +#define mmTPC3_QM_CQ_BUF_ADDR 0xEC8308 + +#define mmTPC3_QM_CQ_BUF_RDATA 0xEC830C + +#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h new file mode 100644 index 000000000..34a438b1e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_RTR_REGS_H_ +#define ASIC_REG_TPC3_RTR_REGS_H_ + +/* + ***************************************** + * TPC3_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC3_RTR_HBW_RD_RQ_E_ARB 0xEC0100 + +#define mmTPC3_RTR_HBW_RD_RQ_W_ARB 0xEC0104 + +#define mmTPC3_RTR_HBW_RD_RQ_N_ARB 0xEC0108 + +#define mmTPC3_RTR_HBW_RD_RQ_S_ARB 0xEC010C + +#define mmTPC3_RTR_HBW_RD_RQ_L_ARB 0xEC0110 + +#define mmTPC3_RTR_HBW_E_ARB_MAX 0xEC0120 + +#define mmTPC3_RTR_HBW_W_ARB_MAX 0xEC0124 + +#define mmTPC3_RTR_HBW_N_ARB_MAX 0xEC0128 + +#define mmTPC3_RTR_HBW_S_ARB_MAX 0xEC012C + +#define mmTPC3_RTR_HBW_L_ARB_MAX 0xEC0130 + +#define mmTPC3_RTR_HBW_RD_RS_E_ARB 0xEC0140 + +#define mmTPC3_RTR_HBW_RD_RS_W_ARB 0xEC0144 + +#define mmTPC3_RTR_HBW_RD_RS_N_ARB 0xEC0148 + +#define mmTPC3_RTR_HBW_RD_RS_S_ARB 0xEC014C + +#define mmTPC3_RTR_HBW_RD_RS_L_ARB 0xEC0150 + +#define mmTPC3_RTR_HBW_WR_RQ_E_ARB 0xEC0170 + +#define mmTPC3_RTR_HBW_WR_RQ_W_ARB 0xEC0174 + +#define mmTPC3_RTR_HBW_WR_RQ_N_ARB 0xEC0178 + +#define mmTPC3_RTR_HBW_WR_RQ_S_ARB 0xEC017C + +#define mmTPC3_RTR_HBW_WR_RQ_L_ARB 0xEC0180 + +#define mmTPC3_RTR_HBW_WR_RS_E_ARB 0xEC0190 + +#define mmTPC3_RTR_HBW_WR_RS_W_ARB 0xEC0194 + +#define mmTPC3_RTR_HBW_WR_RS_N_ARB 0xEC0198 + +#define mmTPC3_RTR_HBW_WR_RS_S_ARB 0xEC019C + +#define mmTPC3_RTR_HBW_WR_RS_L_ARB 0xEC01A0 + +#define mmTPC3_RTR_LBW_RD_RQ_E_ARB 0xEC0200 + +#define mmTPC3_RTR_LBW_RD_RQ_W_ARB 0xEC0204 + +#define mmTPC3_RTR_LBW_RD_RQ_N_ARB 0xEC0208 + +#define mmTPC3_RTR_LBW_RD_RQ_S_ARB 0xEC020C + +#define mmTPC3_RTR_LBW_RD_RQ_L_ARB 0xEC0210 + +#define mmTPC3_RTR_LBW_E_ARB_MAX 0xEC0220 + +#define mmTPC3_RTR_LBW_W_ARB_MAX 0xEC0224 + +#define mmTPC3_RTR_LBW_N_ARB_MAX 0xEC0228 + +#define mmTPC3_RTR_LBW_S_ARB_MAX 0xEC022C + +#define mmTPC3_RTR_LBW_L_ARB_MAX 0xEC0230 + +#define mmTPC3_RTR_LBW_RD_RS_E_ARB 0xEC0250 + +#define mmTPC3_RTR_LBW_RD_RS_W_ARB 0xEC0254 + +#define mmTPC3_RTR_LBW_RD_RS_N_ARB 0xEC0258 + +#define mmTPC3_RTR_LBW_RD_RS_S_ARB 0xEC025C + +#define mmTPC3_RTR_LBW_RD_RS_L_ARB 0xEC0260 + +#define mmTPC3_RTR_LBW_WR_RQ_E_ARB 0xEC0270 + +#define mmTPC3_RTR_LBW_WR_RQ_W_ARB 0xEC0274 + +#define mmTPC3_RTR_LBW_WR_RQ_N_ARB 0xEC0278 + +#define mmTPC3_RTR_LBW_WR_RQ_S_ARB 0xEC027C + +#define mmTPC3_RTR_LBW_WR_RQ_L_ARB 0xEC0280 + +#define mmTPC3_RTR_LBW_WR_RS_E_ARB 0xEC0290 + +#define mmTPC3_RTR_LBW_WR_RS_W_ARB 0xEC0294 + +#define mmTPC3_RTR_LBW_WR_RS_N_ARB 0xEC0298 + +#define mmTPC3_RTR_LBW_WR_RS_S_ARB 0xEC029C + +#define mmTPC3_RTR_LBW_WR_RS_L_ARB 0xEC02A0 + +#define mmTPC3_RTR_DBG_E_ARB 0xEC0300 + +#define mmTPC3_RTR_DBG_W_ARB 0xEC0304 + +#define mmTPC3_RTR_DBG_N_ARB 0xEC0308 + +#define mmTPC3_RTR_DBG_S_ARB 0xEC030C + +#define mmTPC3_RTR_DBG_L_ARB 0xEC0310 + +#define mmTPC3_RTR_DBG_E_ARB_MAX 0xEC0320 + +#define mmTPC3_RTR_DBG_W_ARB_MAX 0xEC0324 + +#define mmTPC3_RTR_DBG_N_ARB_MAX 0xEC0328 + +#define mmTPC3_RTR_DBG_S_ARB_MAX 0xEC032C + +#define mmTPC3_RTR_DBG_L_ARB_MAX 0xEC0330 + +#define mmTPC3_RTR_SPLIT_COEF_0 0xEC0400 + +#define mmTPC3_RTR_SPLIT_COEF_1 0xEC0404 + +#define mmTPC3_RTR_SPLIT_COEF_2 0xEC0408 + +#define mmTPC3_RTR_SPLIT_COEF_3 0xEC040C + +#define mmTPC3_RTR_SPLIT_COEF_4 0xEC0410 + +#define mmTPC3_RTR_SPLIT_COEF_5 0xEC0414 + +#define mmTPC3_RTR_SPLIT_COEF_6 0xEC0418 + +#define mmTPC3_RTR_SPLIT_COEF_7 0xEC041C + +#define mmTPC3_RTR_SPLIT_COEF_8 0xEC0420 + +#define mmTPC3_RTR_SPLIT_COEF_9 0xEC0424 + +#define mmTPC3_RTR_SPLIT_CFG 0xEC0440 + +#define mmTPC3_RTR_SPLIT_RD_SAT 0xEC0444 + +#define mmTPC3_RTR_SPLIT_RD_RST_TOKEN 0xEC0448 + +#define mmTPC3_RTR_SPLIT_RD_TIMEOUT_0 0xEC044C + +#define mmTPC3_RTR_SPLIT_RD_TIMEOUT_1 0xEC0450 + +#define mmTPC3_RTR_SPLIT_WR_SAT 0xEC0454 + +#define mmTPC3_RTR_WPLIT_WR_TST_TOLEN 0xEC0458 + +#define mmTPC3_RTR_SPLIT_WR_TIMEOUT_0 0xEC045C + +#define mmTPC3_RTR_SPLIT_WR_TIMEOUT_1 0xEC0460 + +#define mmTPC3_RTR_HBW_RANGE_HIT 0xEC0470 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_0 0xEC0480 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_1 0xEC0484 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_2 0xEC0488 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_3 0xEC048C + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_4 0xEC0490 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_5 0xEC0494 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_6 0xEC0498 + +#define mmTPC3_RTR_HBW_RANGE_MASK_L_7 0xEC049C + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_0 0xEC04A0 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_1 0xEC04A4 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_2 0xEC04A8 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_3 0xEC04AC + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_4 0xEC04B0 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_5 0xEC04B4 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_6 0xEC04B8 + +#define mmTPC3_RTR_HBW_RANGE_MASK_H_7 0xEC04BC + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_0 0xEC04C0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_1 0xEC04C4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_2 0xEC04C8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_3 0xEC04CC + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_4 0xEC04D0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_5 0xEC04D4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_6 0xEC04D8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_L_7 0xEC04DC + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_0 0xEC04E0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_1 0xEC04E4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_2 0xEC04E8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_3 0xEC04EC + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_4 0xEC04F0 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_5 0xEC04F4 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_6 0xEC04F8 + +#define mmTPC3_RTR_HBW_RANGE_BASE_H_7 0xEC04FC + +#define mmTPC3_RTR_LBW_RANGE_HIT 0xEC0500 + +#define mmTPC3_RTR_LBW_RANGE_MASK_0 0xEC0510 + +#define mmTPC3_RTR_LBW_RANGE_MASK_1 0xEC0514 + +#define mmTPC3_RTR_LBW_RANGE_MASK_2 0xEC0518 + +#define mmTPC3_RTR_LBW_RANGE_MASK_3 0xEC051C + +#define mmTPC3_RTR_LBW_RANGE_MASK_4 0xEC0520 + +#define mmTPC3_RTR_LBW_RANGE_MASK_5 0xEC0524 + +#define mmTPC3_RTR_LBW_RANGE_MASK_6 0xEC0528 + +#define mmTPC3_RTR_LBW_RANGE_MASK_7 0xEC052C + +#define mmTPC3_RTR_LBW_RANGE_MASK_8 0xEC0530 + +#define mmTPC3_RTR_LBW_RANGE_MASK_9 0xEC0534 + +#define mmTPC3_RTR_LBW_RANGE_MASK_10 0xEC0538 + +#define mmTPC3_RTR_LBW_RANGE_MASK_11 0xEC053C + +#define mmTPC3_RTR_LBW_RANGE_MASK_12 0xEC0540 + +#define mmTPC3_RTR_LBW_RANGE_MASK_13 0xEC0544 + +#define mmTPC3_RTR_LBW_RANGE_MASK_14 0xEC0548 + +#define mmTPC3_RTR_LBW_RANGE_MASK_15 0xEC054C + +#define mmTPC3_RTR_LBW_RANGE_BASE_0 0xEC0550 + +#define mmTPC3_RTR_LBW_RANGE_BASE_1 0xEC0554 + +#define mmTPC3_RTR_LBW_RANGE_BASE_2 0xEC0558 + +#define mmTPC3_RTR_LBW_RANGE_BASE_3 0xEC055C + +#define mmTPC3_RTR_LBW_RANGE_BASE_4 0xEC0560 + +#define mmTPC3_RTR_LBW_RANGE_BASE_5 0xEC0564 + +#define mmTPC3_RTR_LBW_RANGE_BASE_6 0xEC0568 + +#define mmTPC3_RTR_LBW_RANGE_BASE_7 0xEC056C + +#define mmTPC3_RTR_LBW_RANGE_BASE_8 0xEC0570 + +#define mmTPC3_RTR_LBW_RANGE_BASE_9 0xEC0574 + +#define mmTPC3_RTR_LBW_RANGE_BASE_10 0xEC0578 + +#define mmTPC3_RTR_LBW_RANGE_BASE_11 0xEC057C + +#define mmTPC3_RTR_LBW_RANGE_BASE_12 0xEC0580 + +#define mmTPC3_RTR_LBW_RANGE_BASE_13 0xEC0584 + +#define mmTPC3_RTR_LBW_RANGE_BASE_14 0xEC0588 + +#define mmTPC3_RTR_LBW_RANGE_BASE_15 0xEC058C + +#define mmTPC3_RTR_RGLTR 0xEC0590 + +#define mmTPC3_RTR_RGLTR_WR_RESULT 0xEC0594 + +#define mmTPC3_RTR_RGLTR_RD_RESULT 0xEC0598 + +#define mmTPC3_RTR_SCRAMB_EN 0xEC0600 + +#define mmTPC3_RTR_NON_LIN_SCRAMB 0xEC0604 + +#endif /* ASIC_REG_TPC3_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h new file mode 100644 index 000000000..d44caf0fc --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CFG_REGS_H_ +#define ASIC_REG_TPC4_CFG_REGS_H_ + +/* + ***************************************** + * TPC4_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF06418 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF06420 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF06424 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06428 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF06430 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06434 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF06438 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06440 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06444 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF06448 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF06450 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06454 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06458 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF06460 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF06464 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06468 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF06470 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06474 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF06478 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06480 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06484 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF06488 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF06490 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF06494 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06498 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C + +#define mmTPC4_CFG_KERNEL_SRF_0 0xF06690 + +#define mmTPC4_CFG_KERNEL_SRF_1 0xF06694 + +#define mmTPC4_CFG_KERNEL_SRF_2 0xF06698 + +#define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C + +#define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0 + +#define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4 + +#define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8 + +#define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC + +#define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0 + +#define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4 + +#define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8 + +#define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC + +#define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0 + +#define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4 + +#define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8 + +#define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC + +#define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0 + +#define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4 + +#define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8 + +#define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC + +#define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0 + +#define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4 + +#define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8 + +#define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC + +#define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0 + +#define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4 + +#define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8 + +#define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC + +#define mmTPC4_CFG_KERNEL_SRF_28 0xF06700 + +#define mmTPC4_CFG_KERNEL_SRF_29 0xF06704 + +#define mmTPC4_CFG_KERNEL_SRF_30 0xF06708 + +#define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C + +#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710 + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714 + +#define mmTPC4_CFG_RESERVED_DESC_END 0xF06738 + +#define mmTPC4_CFG_ROUND_CSR 0xF067FC + +#define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800 + +#define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804 + +#define mmTPC4_CFG_SEMAPHORE 0xF06808 + +#define mmTPC4_CFG_VFLAGS 0xF0680C + +#define mmTPC4_CFG_SFLAGS 0xF06810 + +#define mmTPC4_CFG_LFSR_POLYNOM 0xF06818 + +#define mmTPC4_CFG_STATUS 0xF0681C + +#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820 + +#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C + +#define mmTPC4_CFG_TPC_CMD 0xF06830 + +#define mmTPC4_CFG_TPC_EXECUTE 0xF06838 + +#define mmTPC4_CFG_TPC_STALL 0xF0683C + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840 + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844 + +#define mmTPC4_CFG_MSS_CONFIG 0xF06854 + +#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858 + +#define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C + +#define mmTPC4_CFG_TSB_CONFIG 0xF06860 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 + +#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 + +#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50 + +#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54 + +#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C + +#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0 + +#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8 + +#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC + +#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30 + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34 + +#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38 + +#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80 + +#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84 + +#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC + +#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0 + +#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18 + +#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C + +#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C + +#define mmTPC4_CFG_QM_SRF_0 0xF06C90 + +#define mmTPC4_CFG_QM_SRF_1 0xF06C94 + +#define mmTPC4_CFG_QM_SRF_2 0xF06C98 + +#define mmTPC4_CFG_QM_SRF_3 0xF06C9C + +#define mmTPC4_CFG_QM_SRF_4 0xF06CA0 + +#define mmTPC4_CFG_QM_SRF_5 0xF06CA4 + +#define mmTPC4_CFG_QM_SRF_6 0xF06CA8 + +#define mmTPC4_CFG_QM_SRF_7 0xF06CAC + +#define mmTPC4_CFG_QM_SRF_8 0xF06CB0 + +#define mmTPC4_CFG_QM_SRF_9 0xF06CB4 + +#define mmTPC4_CFG_QM_SRF_10 0xF06CB8 + +#define mmTPC4_CFG_QM_SRF_11 0xF06CBC + +#define mmTPC4_CFG_QM_SRF_12 0xF06CC0 + +#define mmTPC4_CFG_QM_SRF_13 0xF06CC4 + +#define mmTPC4_CFG_QM_SRF_14 0xF06CC8 + +#define mmTPC4_CFG_QM_SRF_15 0xF06CCC + +#define mmTPC4_CFG_QM_SRF_16 0xF06CD0 + +#define mmTPC4_CFG_QM_SRF_17 0xF06CD4 + +#define mmTPC4_CFG_QM_SRF_18 0xF06CD8 + +#define mmTPC4_CFG_QM_SRF_19 0xF06CDC + +#define mmTPC4_CFG_QM_SRF_20 0xF06CE0 + +#define mmTPC4_CFG_QM_SRF_21 0xF06CE4 + +#define mmTPC4_CFG_QM_SRF_22 0xF06CE8 + +#define mmTPC4_CFG_QM_SRF_23 0xF06CEC + +#define mmTPC4_CFG_QM_SRF_24 0xF06CF0 + +#define mmTPC4_CFG_QM_SRF_25 0xF06CF4 + +#define mmTPC4_CFG_QM_SRF_26 0xF06CF8 + +#define mmTPC4_CFG_QM_SRF_27 0xF06CFC + +#define mmTPC4_CFG_QM_SRF_28 0xF06D00 + +#define mmTPC4_CFG_QM_SRF_29 0xF06D04 + +#define mmTPC4_CFG_QM_SRF_30 0xF06D08 + +#define mmTPC4_CFG_QM_SRF_31 0xF06D0C + +#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10 + +#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14 + +#define mmTPC4_CFG_ARUSER 0xF06D18 + +#define mmTPC4_CFG_AWUSER 0xF06D1C + +#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00 + +#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C + +#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C + +#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C + +#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h new file mode 100644 index 000000000..f13a65329 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_ +#define ASIC_REG_TPC4_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC4_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC4_CMDQ_GLBL_CFG0 0xF09000 + +#define mmTPC4_CMDQ_GLBL_CFG1 0xF09004 + +#define mmTPC4_CMDQ_GLBL_PROT 0xF09008 + +#define mmTPC4_CMDQ_GLBL_ERR_CFG 0xF0900C + +#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO 0xF09010 + +#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI 0xF09014 + +#define mmTPC4_CMDQ_GLBL_ERR_WDATA 0xF09018 + +#define mmTPC4_CMDQ_GLBL_SECURE_PROPS 0xF0901C + +#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS 0xF09020 + +#define mmTPC4_CMDQ_GLBL_STS0 0xF09024 + +#define mmTPC4_CMDQ_GLBL_STS1 0xF09028 + +#define mmTPC4_CMDQ_CQ_CFG0 0xF090B0 + +#define mmTPC4_CMDQ_CQ_CFG1 0xF090B4 + +#define mmTPC4_CMDQ_CQ_ARUSER 0xF090B8 + +#define mmTPC4_CMDQ_CQ_PTR_LO 0xF090C0 + +#define mmTPC4_CMDQ_CQ_PTR_HI 0xF090C4 + +#define mmTPC4_CMDQ_CQ_TSIZE 0xF090C8 + +#define mmTPC4_CMDQ_CQ_CTL 0xF090CC + +#define mmTPC4_CMDQ_CQ_PTR_LO_STS 0xF090D4 + +#define mmTPC4_CMDQ_CQ_PTR_HI_STS 0xF090D8 + +#define mmTPC4_CMDQ_CQ_TSIZE_STS 0xF090DC + +#define mmTPC4_CMDQ_CQ_CTL_STS 0xF090E0 + +#define mmTPC4_CMDQ_CQ_STS0 0xF090E4 + +#define mmTPC4_CMDQ_CQ_STS1 0xF090E8 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN 0xF090F0 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF090F4 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT 0xF090F8 + +#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF090FC + +#define mmTPC4_CMDQ_CQ_IFIFO_CNT 0xF09108 + +#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF09120 + +#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF09124 + +#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF09128 + +#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF0912C + +#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF09130 + +#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF09134 + +#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF09138 + +#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF0913C + +#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF09140 + +#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF09144 + +#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF09148 + +#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF0914C + +#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF09150 + +#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF09154 + +#define mmTPC4_CMDQ_CP_FENCE0_RDATA 0xF09158 + +#define mmTPC4_CMDQ_CP_FENCE1_RDATA 0xF0915C + +#define mmTPC4_CMDQ_CP_FENCE2_RDATA 0xF09160 + +#define mmTPC4_CMDQ_CP_FENCE3_RDATA 0xF09164 + +#define mmTPC4_CMDQ_CP_FENCE0_CNT 0xF09168 + +#define mmTPC4_CMDQ_CP_FENCE1_CNT 0xF0916C + +#define mmTPC4_CMDQ_CP_FENCE2_CNT 0xF09170 + +#define mmTPC4_CMDQ_CP_FENCE3_CNT 0xF09174 + +#define mmTPC4_CMDQ_CP_STS 0xF09178 + +#define mmTPC4_CMDQ_CP_CURRENT_INST_LO 0xF0917C + +#define mmTPC4_CMDQ_CP_CURRENT_INST_HI 0xF09180 + +#define mmTPC4_CMDQ_CP_BARRIER_CFG 0xF09184 + +#define mmTPC4_CMDQ_CP_DBG_0 0xF09188 + +#define mmTPC4_CMDQ_CQ_BUF_ADDR 0xF09308 + +#define mmTPC4_CMDQ_CQ_BUF_RDATA 0xF0930C + +#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h new file mode 100644 index 000000000..db081fc17 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_QM_REGS_H_ +#define ASIC_REG_TPC4_QM_REGS_H_ + +/* + ***************************************** + * TPC4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC4_QM_GLBL_CFG0 0xF08000 + +#define mmTPC4_QM_GLBL_CFG1 0xF08004 + +#define mmTPC4_QM_GLBL_PROT 0xF08008 + +#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C + +#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08010 + +#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08014 + +#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08018 + +#define mmTPC4_QM_GLBL_SECURE_PROPS 0xF0801C + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS 0xF08020 + +#define mmTPC4_QM_GLBL_STS0 0xF08024 + +#define mmTPC4_QM_GLBL_STS1 0xF08028 + +#define mmTPC4_QM_PQ_BASE_LO 0xF08060 + +#define mmTPC4_QM_PQ_BASE_HI 0xF08064 + +#define mmTPC4_QM_PQ_SIZE 0xF08068 + +#define mmTPC4_QM_PQ_PI 0xF0806C + +#define mmTPC4_QM_PQ_CI 0xF08070 + +#define mmTPC4_QM_PQ_CFG0 0xF08074 + +#define mmTPC4_QM_PQ_CFG1 0xF08078 + +#define mmTPC4_QM_PQ_ARUSER 0xF0807C + +#define mmTPC4_QM_PQ_PUSH0 0xF08080 + +#define mmTPC4_QM_PQ_PUSH1 0xF08084 + +#define mmTPC4_QM_PQ_PUSH2 0xF08088 + +#define mmTPC4_QM_PQ_PUSH3 0xF0808C + +#define mmTPC4_QM_PQ_STS0 0xF08090 + +#define mmTPC4_QM_PQ_STS1 0xF08094 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_EN 0xF080A0 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF080A4 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_SAT 0xF080A8 + +#define mmTPC4_QM_PQ_RD_RATE_LIM_TOUT 0xF080AC + +#define mmTPC4_QM_CQ_CFG0 0xF080B0 + +#define mmTPC4_QM_CQ_CFG1 0xF080B4 + +#define mmTPC4_QM_CQ_ARUSER 0xF080B8 + +#define mmTPC4_QM_CQ_PTR_LO 0xF080C0 + +#define mmTPC4_QM_CQ_PTR_HI 0xF080C4 + +#define mmTPC4_QM_CQ_TSIZE 0xF080C8 + +#define mmTPC4_QM_CQ_CTL 0xF080CC + +#define mmTPC4_QM_CQ_PTR_LO_STS 0xF080D4 + +#define mmTPC4_QM_CQ_PTR_HI_STS 0xF080D8 + +#define mmTPC4_QM_CQ_TSIZE_STS 0xF080DC + +#define mmTPC4_QM_CQ_CTL_STS 0xF080E0 + +#define mmTPC4_QM_CQ_STS0 0xF080E4 + +#define mmTPC4_QM_CQ_STS1 0xF080E8 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_EN 0xF080F0 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF080F4 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_SAT 0xF080F8 + +#define mmTPC4_QM_CQ_RD_RATE_LIM_TOUT 0xF080FC + +#define mmTPC4_QM_CQ_IFIFO_CNT 0xF08108 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO 0xF08120 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI 0xF08124 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO 0xF08128 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI 0xF0812C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO 0xF08130 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI 0xF08134 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO 0xF08138 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI 0xF0813C + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET 0xF08140 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF08144 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF08148 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF0814C + +#define mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF08150 + +#define mmTPC4_QM_CP_LDMA_COMMIT_OFFSET 0xF08154 + +#define mmTPC4_QM_CP_FENCE0_RDATA 0xF08158 + +#define mmTPC4_QM_CP_FENCE1_RDATA 0xF0815C + +#define mmTPC4_QM_CP_FENCE2_RDATA 0xF08160 + +#define mmTPC4_QM_CP_FENCE3_RDATA 0xF08164 + +#define mmTPC4_QM_CP_FENCE0_CNT 0xF08168 + +#define mmTPC4_QM_CP_FENCE1_CNT 0xF0816C + +#define mmTPC4_QM_CP_FENCE2_CNT 0xF08170 + +#define mmTPC4_QM_CP_FENCE3_CNT 0xF08174 + +#define mmTPC4_QM_CP_STS 0xF08178 + +#define mmTPC4_QM_CP_CURRENT_INST_LO 0xF0817C + +#define mmTPC4_QM_CP_CURRENT_INST_HI 0xF08180 + +#define mmTPC4_QM_CP_BARRIER_CFG 0xF08184 + +#define mmTPC4_QM_CP_DBG_0 0xF08188 + +#define mmTPC4_QM_PQ_BUF_ADDR 0xF08300 + +#define mmTPC4_QM_PQ_BUF_RDATA 0xF08304 + +#define mmTPC4_QM_CQ_BUF_ADDR 0xF08308 + +#define mmTPC4_QM_CQ_BUF_RDATA 0xF0830C + +#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h new file mode 100644 index 000000000..8c5372303 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_RTR_REGS_H_ +#define ASIC_REG_TPC4_RTR_REGS_H_ + +/* + ***************************************** + * TPC4_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC4_RTR_HBW_RD_RQ_E_ARB 0xF00100 + +#define mmTPC4_RTR_HBW_RD_RQ_W_ARB 0xF00104 + +#define mmTPC4_RTR_HBW_RD_RQ_N_ARB 0xF00108 + +#define mmTPC4_RTR_HBW_RD_RQ_S_ARB 0xF0010C + +#define mmTPC4_RTR_HBW_RD_RQ_L_ARB 0xF00110 + +#define mmTPC4_RTR_HBW_E_ARB_MAX 0xF00120 + +#define mmTPC4_RTR_HBW_W_ARB_MAX 0xF00124 + +#define mmTPC4_RTR_HBW_N_ARB_MAX 0xF00128 + +#define mmTPC4_RTR_HBW_S_ARB_MAX 0xF0012C + +#define mmTPC4_RTR_HBW_L_ARB_MAX 0xF00130 + +#define mmTPC4_RTR_HBW_RD_RS_E_ARB 0xF00140 + +#define mmTPC4_RTR_HBW_RD_RS_W_ARB 0xF00144 + +#define mmTPC4_RTR_HBW_RD_RS_N_ARB 0xF00148 + +#define mmTPC4_RTR_HBW_RD_RS_S_ARB 0xF0014C + +#define mmTPC4_RTR_HBW_RD_RS_L_ARB 0xF00150 + +#define mmTPC4_RTR_HBW_WR_RQ_E_ARB 0xF00170 + +#define mmTPC4_RTR_HBW_WR_RQ_W_ARB 0xF00174 + +#define mmTPC4_RTR_HBW_WR_RQ_N_ARB 0xF00178 + +#define mmTPC4_RTR_HBW_WR_RQ_S_ARB 0xF0017C + +#define mmTPC4_RTR_HBW_WR_RQ_L_ARB 0xF00180 + +#define mmTPC4_RTR_HBW_WR_RS_E_ARB 0xF00190 + +#define mmTPC4_RTR_HBW_WR_RS_W_ARB 0xF00194 + +#define mmTPC4_RTR_HBW_WR_RS_N_ARB 0xF00198 + +#define mmTPC4_RTR_HBW_WR_RS_S_ARB 0xF0019C + +#define mmTPC4_RTR_HBW_WR_RS_L_ARB 0xF001A0 + +#define mmTPC4_RTR_LBW_RD_RQ_E_ARB 0xF00200 + +#define mmTPC4_RTR_LBW_RD_RQ_W_ARB 0xF00204 + +#define mmTPC4_RTR_LBW_RD_RQ_N_ARB 0xF00208 + +#define mmTPC4_RTR_LBW_RD_RQ_S_ARB 0xF0020C + +#define mmTPC4_RTR_LBW_RD_RQ_L_ARB 0xF00210 + +#define mmTPC4_RTR_LBW_E_ARB_MAX 0xF00220 + +#define mmTPC4_RTR_LBW_W_ARB_MAX 0xF00224 + +#define mmTPC4_RTR_LBW_N_ARB_MAX 0xF00228 + +#define mmTPC4_RTR_LBW_S_ARB_MAX 0xF0022C + +#define mmTPC4_RTR_LBW_L_ARB_MAX 0xF00230 + +#define mmTPC4_RTR_LBW_RD_RS_E_ARB 0xF00250 + +#define mmTPC4_RTR_LBW_RD_RS_W_ARB 0xF00254 + +#define mmTPC4_RTR_LBW_RD_RS_N_ARB 0xF00258 + +#define mmTPC4_RTR_LBW_RD_RS_S_ARB 0xF0025C + +#define mmTPC4_RTR_LBW_RD_RS_L_ARB 0xF00260 + +#define mmTPC4_RTR_LBW_WR_RQ_E_ARB 0xF00270 + +#define mmTPC4_RTR_LBW_WR_RQ_W_ARB 0xF00274 + +#define mmTPC4_RTR_LBW_WR_RQ_N_ARB 0xF00278 + +#define mmTPC4_RTR_LBW_WR_RQ_S_ARB 0xF0027C + +#define mmTPC4_RTR_LBW_WR_RQ_L_ARB 0xF00280 + +#define mmTPC4_RTR_LBW_WR_RS_E_ARB 0xF00290 + +#define mmTPC4_RTR_LBW_WR_RS_W_ARB 0xF00294 + +#define mmTPC4_RTR_LBW_WR_RS_N_ARB 0xF00298 + +#define mmTPC4_RTR_LBW_WR_RS_S_ARB 0xF0029C + +#define mmTPC4_RTR_LBW_WR_RS_L_ARB 0xF002A0 + +#define mmTPC4_RTR_DBG_E_ARB 0xF00300 + +#define mmTPC4_RTR_DBG_W_ARB 0xF00304 + +#define mmTPC4_RTR_DBG_N_ARB 0xF00308 + +#define mmTPC4_RTR_DBG_S_ARB 0xF0030C + +#define mmTPC4_RTR_DBG_L_ARB 0xF00310 + +#define mmTPC4_RTR_DBG_E_ARB_MAX 0xF00320 + +#define mmTPC4_RTR_DBG_W_ARB_MAX 0xF00324 + +#define mmTPC4_RTR_DBG_N_ARB_MAX 0xF00328 + +#define mmTPC4_RTR_DBG_S_ARB_MAX 0xF0032C + +#define mmTPC4_RTR_DBG_L_ARB_MAX 0xF00330 + +#define mmTPC4_RTR_SPLIT_COEF_0 0xF00400 + +#define mmTPC4_RTR_SPLIT_COEF_1 0xF00404 + +#define mmTPC4_RTR_SPLIT_COEF_2 0xF00408 + +#define mmTPC4_RTR_SPLIT_COEF_3 0xF0040C + +#define mmTPC4_RTR_SPLIT_COEF_4 0xF00410 + +#define mmTPC4_RTR_SPLIT_COEF_5 0xF00414 + +#define mmTPC4_RTR_SPLIT_COEF_6 0xF00418 + +#define mmTPC4_RTR_SPLIT_COEF_7 0xF0041C + +#define mmTPC4_RTR_SPLIT_COEF_8 0xF00420 + +#define mmTPC4_RTR_SPLIT_COEF_9 0xF00424 + +#define mmTPC4_RTR_SPLIT_CFG 0xF00440 + +#define mmTPC4_RTR_SPLIT_RD_SAT 0xF00444 + +#define mmTPC4_RTR_SPLIT_RD_RST_TOKEN 0xF00448 + +#define mmTPC4_RTR_SPLIT_RD_TIMEOUT_0 0xF0044C + +#define mmTPC4_RTR_SPLIT_RD_TIMEOUT_1 0xF00450 + +#define mmTPC4_RTR_SPLIT_WR_SAT 0xF00454 + +#define mmTPC4_RTR_WPLIT_WR_TST_TOLEN 0xF00458 + +#define mmTPC4_RTR_SPLIT_WR_TIMEOUT_0 0xF0045C + +#define mmTPC4_RTR_SPLIT_WR_TIMEOUT_1 0xF00460 + +#define mmTPC4_RTR_HBW_RANGE_HIT 0xF00470 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_0 0xF00480 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_1 0xF00484 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_2 0xF00488 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_3 0xF0048C + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_4 0xF00490 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_5 0xF00494 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_6 0xF00498 + +#define mmTPC4_RTR_HBW_RANGE_MASK_L_7 0xF0049C + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_0 0xF004A0 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_1 0xF004A4 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_2 0xF004A8 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_3 0xF004AC + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_4 0xF004B0 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_5 0xF004B4 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_6 0xF004B8 + +#define mmTPC4_RTR_HBW_RANGE_MASK_H_7 0xF004BC + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_0 0xF004C0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_1 0xF004C4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_2 0xF004C8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_3 0xF004CC + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_4 0xF004D0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_5 0xF004D4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_6 0xF004D8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_L_7 0xF004DC + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_0 0xF004E0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_1 0xF004E4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_2 0xF004E8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_3 0xF004EC + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_4 0xF004F0 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_5 0xF004F4 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_6 0xF004F8 + +#define mmTPC4_RTR_HBW_RANGE_BASE_H_7 0xF004FC + +#define mmTPC4_RTR_LBW_RANGE_HIT 0xF00500 + +#define mmTPC4_RTR_LBW_RANGE_MASK_0 0xF00510 + +#define mmTPC4_RTR_LBW_RANGE_MASK_1 0xF00514 + +#define mmTPC4_RTR_LBW_RANGE_MASK_2 0xF00518 + +#define mmTPC4_RTR_LBW_RANGE_MASK_3 0xF0051C + +#define mmTPC4_RTR_LBW_RANGE_MASK_4 0xF00520 + +#define mmTPC4_RTR_LBW_RANGE_MASK_5 0xF00524 + +#define mmTPC4_RTR_LBW_RANGE_MASK_6 0xF00528 + +#define mmTPC4_RTR_LBW_RANGE_MASK_7 0xF0052C + +#define mmTPC4_RTR_LBW_RANGE_MASK_8 0xF00530 + +#define mmTPC4_RTR_LBW_RANGE_MASK_9 0xF00534 + +#define mmTPC4_RTR_LBW_RANGE_MASK_10 0xF00538 + +#define mmTPC4_RTR_LBW_RANGE_MASK_11 0xF0053C + +#define mmTPC4_RTR_LBW_RANGE_MASK_12 0xF00540 + +#define mmTPC4_RTR_LBW_RANGE_MASK_13 0xF00544 + +#define mmTPC4_RTR_LBW_RANGE_MASK_14 0xF00548 + +#define mmTPC4_RTR_LBW_RANGE_MASK_15 0xF0054C + +#define mmTPC4_RTR_LBW_RANGE_BASE_0 0xF00550 + +#define mmTPC4_RTR_LBW_RANGE_BASE_1 0xF00554 + +#define mmTPC4_RTR_LBW_RANGE_BASE_2 0xF00558 + +#define mmTPC4_RTR_LBW_RANGE_BASE_3 0xF0055C + +#define mmTPC4_RTR_LBW_RANGE_BASE_4 0xF00560 + +#define mmTPC4_RTR_LBW_RANGE_BASE_5 0xF00564 + +#define mmTPC4_RTR_LBW_RANGE_BASE_6 0xF00568 + +#define mmTPC4_RTR_LBW_RANGE_BASE_7 0xF0056C + +#define mmTPC4_RTR_LBW_RANGE_BASE_8 0xF00570 + +#define mmTPC4_RTR_LBW_RANGE_BASE_9 0xF00574 + +#define mmTPC4_RTR_LBW_RANGE_BASE_10 0xF00578 + +#define mmTPC4_RTR_LBW_RANGE_BASE_11 0xF0057C + +#define mmTPC4_RTR_LBW_RANGE_BASE_12 0xF00580 + +#define mmTPC4_RTR_LBW_RANGE_BASE_13 0xF00584 + +#define mmTPC4_RTR_LBW_RANGE_BASE_14 0xF00588 + +#define mmTPC4_RTR_LBW_RANGE_BASE_15 0xF0058C + +#define mmTPC4_RTR_RGLTR 0xF00590 + +#define mmTPC4_RTR_RGLTR_WR_RESULT 0xF00594 + +#define mmTPC4_RTR_RGLTR_RD_RESULT 0xF00598 + +#define mmTPC4_RTR_SCRAMB_EN 0xF00600 + +#define mmTPC4_RTR_NON_LIN_SCRAMB 0xF00604 + +#endif /* ASIC_REG_TPC4_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h new file mode 100644 index 000000000..5139fde71 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CFG_REGS_H_ +#define ASIC_REG_TPC5_CFG_REGS_H_ + +/* + ***************************************** + * TPC5_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF46418 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF4641C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF46420 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF46424 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46428 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF4642C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF46430 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46434 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF46438 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF4643C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46440 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46444 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF46448 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF4644C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF46450 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46454 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46458 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF4645C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF46460 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF46464 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46468 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF4646C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF46470 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46474 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF46478 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF4647C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46480 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46484 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF46488 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF4648C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF46490 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF46494 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46498 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF4649C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF464A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF464A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF464A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF464AC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF464B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF464B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF464B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF464BC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF464C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF464C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF464C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF464CC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF464D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF464D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464DC + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF464E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464EC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF464FC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF46500 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF46504 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF46508 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF4650C + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF46510 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF46514 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF46518 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF4651C + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF46520 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF46524 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF46528 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF4652C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF46530 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF46534 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF46538 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF4653C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF46540 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF46544 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF46548 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF4654C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF46550 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF46554 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46558 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF4655C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF46560 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46564 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF46568 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF4656C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46570 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46574 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF46578 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF4657C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF46580 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46584 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46588 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF4658C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF46590 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF46594 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46598 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF4659C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF465A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF465A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF465A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF465AC + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF465B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF465B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF465B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF465BC + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF465C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF465C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF465C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF465CC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF465D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF465D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF465D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF465DC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF465E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF465E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF465E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF465EC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF465F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF465F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF465F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF465FC + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF46600 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF46604 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46608 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF4660C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF46610 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46614 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF46618 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF4661C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46620 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46624 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF46628 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF4662C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF46630 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF46634 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF46638 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF4663C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF46640 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF46644 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF46648 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF4664C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF46650 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF46654 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF46658 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF4665C + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46660 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF46664 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46668 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF4666C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46670 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF46674 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF46678 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF4667C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF46680 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF46684 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF46688 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF4668C + +#define mmTPC5_CFG_KERNEL_SRF_0 0xF46690 + +#define mmTPC5_CFG_KERNEL_SRF_1 0xF46694 + +#define mmTPC5_CFG_KERNEL_SRF_2 0xF46698 + +#define mmTPC5_CFG_KERNEL_SRF_3 0xF4669C + +#define mmTPC5_CFG_KERNEL_SRF_4 0xF466A0 + +#define mmTPC5_CFG_KERNEL_SRF_5 0xF466A4 + +#define mmTPC5_CFG_KERNEL_SRF_6 0xF466A8 + +#define mmTPC5_CFG_KERNEL_SRF_7 0xF466AC + +#define mmTPC5_CFG_KERNEL_SRF_8 0xF466B0 + +#define mmTPC5_CFG_KERNEL_SRF_9 0xF466B4 + +#define mmTPC5_CFG_KERNEL_SRF_10 0xF466B8 + +#define mmTPC5_CFG_KERNEL_SRF_11 0xF466BC + +#define mmTPC5_CFG_KERNEL_SRF_12 0xF466C0 + +#define mmTPC5_CFG_KERNEL_SRF_13 0xF466C4 + +#define mmTPC5_CFG_KERNEL_SRF_14 0xF466C8 + +#define mmTPC5_CFG_KERNEL_SRF_15 0xF466CC + +#define mmTPC5_CFG_KERNEL_SRF_16 0xF466D0 + +#define mmTPC5_CFG_KERNEL_SRF_17 0xF466D4 + +#define mmTPC5_CFG_KERNEL_SRF_18 0xF466D8 + +#define mmTPC5_CFG_KERNEL_SRF_19 0xF466DC + +#define mmTPC5_CFG_KERNEL_SRF_20 0xF466E0 + +#define mmTPC5_CFG_KERNEL_SRF_21 0xF466E4 + +#define mmTPC5_CFG_KERNEL_SRF_22 0xF466E8 + +#define mmTPC5_CFG_KERNEL_SRF_23 0xF466EC + +#define mmTPC5_CFG_KERNEL_SRF_24 0xF466F0 + +#define mmTPC5_CFG_KERNEL_SRF_25 0xF466F4 + +#define mmTPC5_CFG_KERNEL_SRF_26 0xF466F8 + +#define mmTPC5_CFG_KERNEL_SRF_27 0xF466FC + +#define mmTPC5_CFG_KERNEL_SRF_28 0xF46700 + +#define mmTPC5_CFG_KERNEL_SRF_29 0xF46704 + +#define mmTPC5_CFG_KERNEL_SRF_30 0xF46708 + +#define mmTPC5_CFG_KERNEL_SRF_31 0xF4670C + +#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF46710 + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46714 + +#define mmTPC5_CFG_RESERVED_DESC_END 0xF46738 + +#define mmTPC5_CFG_ROUND_CSR 0xF467FC + +#define mmTPC5_CFG_TBUF_BASE_ADDR_LOW 0xF46800 + +#define mmTPC5_CFG_TBUF_BASE_ADDR_HIGH 0xF46804 + +#define mmTPC5_CFG_SEMAPHORE 0xF46808 + +#define mmTPC5_CFG_VFLAGS 0xF4680C + +#define mmTPC5_CFG_SFLAGS 0xF46810 + +#define mmTPC5_CFG_LFSR_POLYNOM 0xF46818 + +#define mmTPC5_CFG_STATUS 0xF4681C + +#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46820 + +#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46824 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_LOW 0xF46828 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4682C + +#define mmTPC5_CFG_TPC_CMD 0xF46830 + +#define mmTPC5_CFG_TPC_EXECUTE 0xF46838 + +#define mmTPC5_CFG_TPC_STALL 0xF4683C + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46840 + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46844 + +#define mmTPC5_CFG_MSS_CONFIG 0xF46854 + +#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46858 + +#define mmTPC5_CFG_TPC_INTR_MASK 0xF4685C + +#define mmTPC5_CFG_TSB_CONFIG 0xF46860 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 + +#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 + +#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF46A18 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A1C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A20 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF46A24 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A28 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A2C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF46A30 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A34 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A38 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF46A3C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A40 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A44 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF46A48 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A4C + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A50 + +#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A54 + +#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A58 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A5C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A60 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF46A64 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A68 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A6C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF46A70 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A74 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A78 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF46A7C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A80 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A84 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF46A88 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A8C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A90 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF46A94 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A98 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A9C + +#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46AA0 + +#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46AA4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46AA8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46AAC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF46AB0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46AB4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46AB8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF46ABC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46AC0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46AC4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF46AC8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46ACC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46AD0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF46AD4 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AD8 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46ADC + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF46AE0 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AE4 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AE8 + +#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AEC + +#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AF0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AF4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46AF8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF46AFC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46B00 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46B04 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF46B08 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46B0C + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46B10 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF46B14 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46B18 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46B1C + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF46B20 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46B24 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46B28 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF46B2C + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46B30 + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46B34 + +#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46B38 + +#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46B3C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46B40 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46B44 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF46B48 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46B4C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46B50 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF46B54 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B58 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B5C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF46B60 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B64 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B68 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF46B6C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B70 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B74 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF46B78 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B7C + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B80 + +#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B84 + +#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B88 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B8C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B90 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF46B94 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B98 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B9C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF46BA0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46BA4 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46BA8 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF46BAC + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46BB0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46BB4 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF46BB8 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46BBC + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46BC0 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF46BC4 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46BC8 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46BCC + +#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46BD0 + +#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46BD4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46BD8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46BDC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF46BE0 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46BE4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46BE8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF46BEC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46BF0 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46BF4 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF46BF8 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46BFC + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46C00 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF46C04 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46C08 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46C0C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF46C10 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46C14 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46C18 + +#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46C1C + +#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46C20 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46C24 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46C28 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF46C2C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46C30 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46C34 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF46C38 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46C3C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46C40 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF46C44 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46C48 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46C4C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF46C50 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46C54 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46C58 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF46C5C + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46C60 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46C64 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46C68 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46C6C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46C70 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46C74 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46C78 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46C7C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46C80 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46C84 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46C88 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46C8C + +#define mmTPC5_CFG_QM_SRF_0 0xF46C90 + +#define mmTPC5_CFG_QM_SRF_1 0xF46C94 + +#define mmTPC5_CFG_QM_SRF_2 0xF46C98 + +#define mmTPC5_CFG_QM_SRF_3 0xF46C9C + +#define mmTPC5_CFG_QM_SRF_4 0xF46CA0 + +#define mmTPC5_CFG_QM_SRF_5 0xF46CA4 + +#define mmTPC5_CFG_QM_SRF_6 0xF46CA8 + +#define mmTPC5_CFG_QM_SRF_7 0xF46CAC + +#define mmTPC5_CFG_QM_SRF_8 0xF46CB0 + +#define mmTPC5_CFG_QM_SRF_9 0xF46CB4 + +#define mmTPC5_CFG_QM_SRF_10 0xF46CB8 + +#define mmTPC5_CFG_QM_SRF_11 0xF46CBC + +#define mmTPC5_CFG_QM_SRF_12 0xF46CC0 + +#define mmTPC5_CFG_QM_SRF_13 0xF46CC4 + +#define mmTPC5_CFG_QM_SRF_14 0xF46CC8 + +#define mmTPC5_CFG_QM_SRF_15 0xF46CCC + +#define mmTPC5_CFG_QM_SRF_16 0xF46CD0 + +#define mmTPC5_CFG_QM_SRF_17 0xF46CD4 + +#define mmTPC5_CFG_QM_SRF_18 0xF46CD8 + +#define mmTPC5_CFG_QM_SRF_19 0xF46CDC + +#define mmTPC5_CFG_QM_SRF_20 0xF46CE0 + +#define mmTPC5_CFG_QM_SRF_21 0xF46CE4 + +#define mmTPC5_CFG_QM_SRF_22 0xF46CE8 + +#define mmTPC5_CFG_QM_SRF_23 0xF46CEC + +#define mmTPC5_CFG_QM_SRF_24 0xF46CF0 + +#define mmTPC5_CFG_QM_SRF_25 0xF46CF4 + +#define mmTPC5_CFG_QM_SRF_26 0xF46CF8 + +#define mmTPC5_CFG_QM_SRF_27 0xF46CFC + +#define mmTPC5_CFG_QM_SRF_28 0xF46D00 + +#define mmTPC5_CFG_QM_SRF_29 0xF46D04 + +#define mmTPC5_CFG_QM_SRF_30 0xF46D08 + +#define mmTPC5_CFG_QM_SRF_31 0xF46D0C + +#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46D10 + +#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D14 + +#define mmTPC5_CFG_ARUSER 0xF46D18 + +#define mmTPC5_CFG_AWUSER 0xF46D1C + +#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF46E00 + +#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF46E04 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF46E08 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF46E0C + +#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF46E10 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF46E14 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF46E18 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF46E1C + +#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF46E20 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF46E24 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF46E28 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF46E2C + +#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h new file mode 100644 index 000000000..1e7cd6e1e --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_ +#define ASIC_REG_TPC5_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC5_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC5_CMDQ_GLBL_CFG0 0xF49000 + +#define mmTPC5_CMDQ_GLBL_CFG1 0xF49004 + +#define mmTPC5_CMDQ_GLBL_PROT 0xF49008 + +#define mmTPC5_CMDQ_GLBL_ERR_CFG 0xF4900C + +#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO 0xF49010 + +#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI 0xF49014 + +#define mmTPC5_CMDQ_GLBL_ERR_WDATA 0xF49018 + +#define mmTPC5_CMDQ_GLBL_SECURE_PROPS 0xF4901C + +#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS 0xF49020 + +#define mmTPC5_CMDQ_GLBL_STS0 0xF49024 + +#define mmTPC5_CMDQ_GLBL_STS1 0xF49028 + +#define mmTPC5_CMDQ_CQ_CFG0 0xF490B0 + +#define mmTPC5_CMDQ_CQ_CFG1 0xF490B4 + +#define mmTPC5_CMDQ_CQ_ARUSER 0xF490B8 + +#define mmTPC5_CMDQ_CQ_PTR_LO 0xF490C0 + +#define mmTPC5_CMDQ_CQ_PTR_HI 0xF490C4 + +#define mmTPC5_CMDQ_CQ_TSIZE 0xF490C8 + +#define mmTPC5_CMDQ_CQ_CTL 0xF490CC + +#define mmTPC5_CMDQ_CQ_PTR_LO_STS 0xF490D4 + +#define mmTPC5_CMDQ_CQ_PTR_HI_STS 0xF490D8 + +#define mmTPC5_CMDQ_CQ_TSIZE_STS 0xF490DC + +#define mmTPC5_CMDQ_CQ_CTL_STS 0xF490E0 + +#define mmTPC5_CMDQ_CQ_STS0 0xF490E4 + +#define mmTPC5_CMDQ_CQ_STS1 0xF490E8 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN 0xF490F0 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF490F4 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT 0xF490F8 + +#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF490FC + +#define mmTPC5_CMDQ_CQ_IFIFO_CNT 0xF49108 + +#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF49120 + +#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF49124 + +#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF49128 + +#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF4912C + +#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF49130 + +#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF49134 + +#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF49138 + +#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF4913C + +#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF49140 + +#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF49144 + +#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF49148 + +#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF4914C + +#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF49150 + +#define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF49154 + +#define mmTPC5_CMDQ_CP_FENCE0_RDATA 0xF49158 + +#define mmTPC5_CMDQ_CP_FENCE1_RDATA 0xF4915C + +#define mmTPC5_CMDQ_CP_FENCE2_RDATA 0xF49160 + +#define mmTPC5_CMDQ_CP_FENCE3_RDATA 0xF49164 + +#define mmTPC5_CMDQ_CP_FENCE0_CNT 0xF49168 + +#define mmTPC5_CMDQ_CP_FENCE1_CNT 0xF4916C + +#define mmTPC5_CMDQ_CP_FENCE2_CNT 0xF49170 + +#define mmTPC5_CMDQ_CP_FENCE3_CNT 0xF49174 + +#define mmTPC5_CMDQ_CP_STS 0xF49178 + +#define mmTPC5_CMDQ_CP_CURRENT_INST_LO 0xF4917C + +#define mmTPC5_CMDQ_CP_CURRENT_INST_HI 0xF49180 + +#define mmTPC5_CMDQ_CP_BARRIER_CFG 0xF49184 + +#define mmTPC5_CMDQ_CP_DBG_0 0xF49188 + +#define mmTPC5_CMDQ_CQ_BUF_ADDR 0xF49308 + +#define mmTPC5_CMDQ_CQ_BUF_RDATA 0xF4930C + +#endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h new file mode 100644 index 000000000..ac0d3820c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_QM_REGS_H_ +#define ASIC_REG_TPC5_QM_REGS_H_ + +/* + ***************************************** + * TPC5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC5_QM_GLBL_CFG0 0xF48000 + +#define mmTPC5_QM_GLBL_CFG1 0xF48004 + +#define mmTPC5_QM_GLBL_PROT 0xF48008 + +#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C + +#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48010 + +#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48014 + +#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48018 + +#define mmTPC5_QM_GLBL_SECURE_PROPS 0xF4801C + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS 0xF48020 + +#define mmTPC5_QM_GLBL_STS0 0xF48024 + +#define mmTPC5_QM_GLBL_STS1 0xF48028 + +#define mmTPC5_QM_PQ_BASE_LO 0xF48060 + +#define mmTPC5_QM_PQ_BASE_HI 0xF48064 + +#define mmTPC5_QM_PQ_SIZE 0xF48068 + +#define mmTPC5_QM_PQ_PI 0xF4806C + +#define mmTPC5_QM_PQ_CI 0xF48070 + +#define mmTPC5_QM_PQ_CFG0 0xF48074 + +#define mmTPC5_QM_PQ_CFG1 0xF48078 + +#define mmTPC5_QM_PQ_ARUSER 0xF4807C + +#define mmTPC5_QM_PQ_PUSH0 0xF48080 + +#define mmTPC5_QM_PQ_PUSH1 0xF48084 + +#define mmTPC5_QM_PQ_PUSH2 0xF48088 + +#define mmTPC5_QM_PQ_PUSH3 0xF4808C + +#define mmTPC5_QM_PQ_STS0 0xF48090 + +#define mmTPC5_QM_PQ_STS1 0xF48094 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_EN 0xF480A0 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF480A4 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_SAT 0xF480A8 + +#define mmTPC5_QM_PQ_RD_RATE_LIM_TOUT 0xF480AC + +#define mmTPC5_QM_CQ_CFG0 0xF480B0 + +#define mmTPC5_QM_CQ_CFG1 0xF480B4 + +#define mmTPC5_QM_CQ_ARUSER 0xF480B8 + +#define mmTPC5_QM_CQ_PTR_LO 0xF480C0 + +#define mmTPC5_QM_CQ_PTR_HI 0xF480C4 + +#define mmTPC5_QM_CQ_TSIZE 0xF480C8 + +#define mmTPC5_QM_CQ_CTL 0xF480CC + +#define mmTPC5_QM_CQ_PTR_LO_STS 0xF480D4 + +#define mmTPC5_QM_CQ_PTR_HI_STS 0xF480D8 + +#define mmTPC5_QM_CQ_TSIZE_STS 0xF480DC + +#define mmTPC5_QM_CQ_CTL_STS 0xF480E0 + +#define mmTPC5_QM_CQ_STS0 0xF480E4 + +#define mmTPC5_QM_CQ_STS1 0xF480E8 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_EN 0xF480F0 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF480F4 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_SAT 0xF480F8 + +#define mmTPC5_QM_CQ_RD_RATE_LIM_TOUT 0xF480FC + +#define mmTPC5_QM_CQ_IFIFO_CNT 0xF48108 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO 0xF48120 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI 0xF48124 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO 0xF48128 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI 0xF4812C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO 0xF48130 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI 0xF48134 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO 0xF48138 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI 0xF4813C + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET 0xF48140 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF48144 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF48148 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF4814C + +#define mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF48150 + +#define mmTPC5_QM_CP_LDMA_COMMIT_OFFSET 0xF48154 + +#define mmTPC5_QM_CP_FENCE0_RDATA 0xF48158 + +#define mmTPC5_QM_CP_FENCE1_RDATA 0xF4815C + +#define mmTPC5_QM_CP_FENCE2_RDATA 0xF48160 + +#define mmTPC5_QM_CP_FENCE3_RDATA 0xF48164 + +#define mmTPC5_QM_CP_FENCE0_CNT 0xF48168 + +#define mmTPC5_QM_CP_FENCE1_CNT 0xF4816C + +#define mmTPC5_QM_CP_FENCE2_CNT 0xF48170 + +#define mmTPC5_QM_CP_FENCE3_CNT 0xF48174 + +#define mmTPC5_QM_CP_STS 0xF48178 + +#define mmTPC5_QM_CP_CURRENT_INST_LO 0xF4817C + +#define mmTPC5_QM_CP_CURRENT_INST_HI 0xF48180 + +#define mmTPC5_QM_CP_BARRIER_CFG 0xF48184 + +#define mmTPC5_QM_CP_DBG_0 0xF48188 + +#define mmTPC5_QM_PQ_BUF_ADDR 0xF48300 + +#define mmTPC5_QM_PQ_BUF_RDATA 0xF48304 + +#define mmTPC5_QM_CQ_BUF_ADDR 0xF48308 + +#define mmTPC5_QM_CQ_BUF_RDATA 0xF4830C + +#endif /* ASIC_REG_TPC5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h new file mode 100644 index 000000000..57f83bc3b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_RTR_REGS_H_ +#define ASIC_REG_TPC5_RTR_REGS_H_ + +/* + ***************************************** + * TPC5_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC5_RTR_HBW_RD_RQ_E_ARB 0xF40100 + +#define mmTPC5_RTR_HBW_RD_RQ_W_ARB 0xF40104 + +#define mmTPC5_RTR_HBW_RD_RQ_N_ARB 0xF40108 + +#define mmTPC5_RTR_HBW_RD_RQ_S_ARB 0xF4010C + +#define mmTPC5_RTR_HBW_RD_RQ_L_ARB 0xF40110 + +#define mmTPC5_RTR_HBW_E_ARB_MAX 0xF40120 + +#define mmTPC5_RTR_HBW_W_ARB_MAX 0xF40124 + +#define mmTPC5_RTR_HBW_N_ARB_MAX 0xF40128 + +#define mmTPC5_RTR_HBW_S_ARB_MAX 0xF4012C + +#define mmTPC5_RTR_HBW_L_ARB_MAX 0xF40130 + +#define mmTPC5_RTR_HBW_RD_RS_E_ARB 0xF40140 + +#define mmTPC5_RTR_HBW_RD_RS_W_ARB 0xF40144 + +#define mmTPC5_RTR_HBW_RD_RS_N_ARB 0xF40148 + +#define mmTPC5_RTR_HBW_RD_RS_S_ARB 0xF4014C + +#define mmTPC5_RTR_HBW_RD_RS_L_ARB 0xF40150 + +#define mmTPC5_RTR_HBW_WR_RQ_E_ARB 0xF40170 + +#define mmTPC5_RTR_HBW_WR_RQ_W_ARB 0xF40174 + +#define mmTPC5_RTR_HBW_WR_RQ_N_ARB 0xF40178 + +#define mmTPC5_RTR_HBW_WR_RQ_S_ARB 0xF4017C + +#define mmTPC5_RTR_HBW_WR_RQ_L_ARB 0xF40180 + +#define mmTPC5_RTR_HBW_WR_RS_E_ARB 0xF40190 + +#define mmTPC5_RTR_HBW_WR_RS_W_ARB 0xF40194 + +#define mmTPC5_RTR_HBW_WR_RS_N_ARB 0xF40198 + +#define mmTPC5_RTR_HBW_WR_RS_S_ARB 0xF4019C + +#define mmTPC5_RTR_HBW_WR_RS_L_ARB 0xF401A0 + +#define mmTPC5_RTR_LBW_RD_RQ_E_ARB 0xF40200 + +#define mmTPC5_RTR_LBW_RD_RQ_W_ARB 0xF40204 + +#define mmTPC5_RTR_LBW_RD_RQ_N_ARB 0xF40208 + +#define mmTPC5_RTR_LBW_RD_RQ_S_ARB 0xF4020C + +#define mmTPC5_RTR_LBW_RD_RQ_L_ARB 0xF40210 + +#define mmTPC5_RTR_LBW_E_ARB_MAX 0xF40220 + +#define mmTPC5_RTR_LBW_W_ARB_MAX 0xF40224 + +#define mmTPC5_RTR_LBW_N_ARB_MAX 0xF40228 + +#define mmTPC5_RTR_LBW_S_ARB_MAX 0xF4022C + +#define mmTPC5_RTR_LBW_L_ARB_MAX 0xF40230 + +#define mmTPC5_RTR_LBW_RD_RS_E_ARB 0xF40250 + +#define mmTPC5_RTR_LBW_RD_RS_W_ARB 0xF40254 + +#define mmTPC5_RTR_LBW_RD_RS_N_ARB 0xF40258 + +#define mmTPC5_RTR_LBW_RD_RS_S_ARB 0xF4025C + +#define mmTPC5_RTR_LBW_RD_RS_L_ARB 0xF40260 + +#define mmTPC5_RTR_LBW_WR_RQ_E_ARB 0xF40270 + +#define mmTPC5_RTR_LBW_WR_RQ_W_ARB 0xF40274 + +#define mmTPC5_RTR_LBW_WR_RQ_N_ARB 0xF40278 + +#define mmTPC5_RTR_LBW_WR_RQ_S_ARB 0xF4027C + +#define mmTPC5_RTR_LBW_WR_RQ_L_ARB 0xF40280 + +#define mmTPC5_RTR_LBW_WR_RS_E_ARB 0xF40290 + +#define mmTPC5_RTR_LBW_WR_RS_W_ARB 0xF40294 + +#define mmTPC5_RTR_LBW_WR_RS_N_ARB 0xF40298 + +#define mmTPC5_RTR_LBW_WR_RS_S_ARB 0xF4029C + +#define mmTPC5_RTR_LBW_WR_RS_L_ARB 0xF402A0 + +#define mmTPC5_RTR_DBG_E_ARB 0xF40300 + +#define mmTPC5_RTR_DBG_W_ARB 0xF40304 + +#define mmTPC5_RTR_DBG_N_ARB 0xF40308 + +#define mmTPC5_RTR_DBG_S_ARB 0xF4030C + +#define mmTPC5_RTR_DBG_L_ARB 0xF40310 + +#define mmTPC5_RTR_DBG_E_ARB_MAX 0xF40320 + +#define mmTPC5_RTR_DBG_W_ARB_MAX 0xF40324 + +#define mmTPC5_RTR_DBG_N_ARB_MAX 0xF40328 + +#define mmTPC5_RTR_DBG_S_ARB_MAX 0xF4032C + +#define mmTPC5_RTR_DBG_L_ARB_MAX 0xF40330 + +#define mmTPC5_RTR_SPLIT_COEF_0 0xF40400 + +#define mmTPC5_RTR_SPLIT_COEF_1 0xF40404 + +#define mmTPC5_RTR_SPLIT_COEF_2 0xF40408 + +#define mmTPC5_RTR_SPLIT_COEF_3 0xF4040C + +#define mmTPC5_RTR_SPLIT_COEF_4 0xF40410 + +#define mmTPC5_RTR_SPLIT_COEF_5 0xF40414 + +#define mmTPC5_RTR_SPLIT_COEF_6 0xF40418 + +#define mmTPC5_RTR_SPLIT_COEF_7 0xF4041C + +#define mmTPC5_RTR_SPLIT_COEF_8 0xF40420 + +#define mmTPC5_RTR_SPLIT_COEF_9 0xF40424 + +#define mmTPC5_RTR_SPLIT_CFG 0xF40440 + +#define mmTPC5_RTR_SPLIT_RD_SAT 0xF40444 + +#define mmTPC5_RTR_SPLIT_RD_RST_TOKEN 0xF40448 + +#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_0 0xF4044C + +#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_1 0xF40450 + +#define mmTPC5_RTR_SPLIT_WR_SAT 0xF40454 + +#define mmTPC5_RTR_WPLIT_WR_TST_TOLEN 0xF40458 + +#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_0 0xF4045C + +#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_1 0xF40460 + +#define mmTPC5_RTR_HBW_RANGE_HIT 0xF40470 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_0 0xF40480 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_1 0xF40484 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_2 0xF40488 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_3 0xF4048C + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_4 0xF40490 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_5 0xF40494 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_6 0xF40498 + +#define mmTPC5_RTR_HBW_RANGE_MASK_L_7 0xF4049C + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_0 0xF404A0 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_1 0xF404A4 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_2 0xF404A8 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_3 0xF404AC + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_4 0xF404B0 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_5 0xF404B4 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_6 0xF404B8 + +#define mmTPC5_RTR_HBW_RANGE_MASK_H_7 0xF404BC + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_0 0xF404C0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_1 0xF404C4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_2 0xF404C8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_3 0xF404CC + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_4 0xF404D0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_5 0xF404D4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_6 0xF404D8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_L_7 0xF404DC + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_0 0xF404E0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_1 0xF404E4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_2 0xF404E8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_3 0xF404EC + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_4 0xF404F0 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_5 0xF404F4 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_6 0xF404F8 + +#define mmTPC5_RTR_HBW_RANGE_BASE_H_7 0xF404FC + +#define mmTPC5_RTR_LBW_RANGE_HIT 0xF40500 + +#define mmTPC5_RTR_LBW_RANGE_MASK_0 0xF40510 + +#define mmTPC5_RTR_LBW_RANGE_MASK_1 0xF40514 + +#define mmTPC5_RTR_LBW_RANGE_MASK_2 0xF40518 + +#define mmTPC5_RTR_LBW_RANGE_MASK_3 0xF4051C + +#define mmTPC5_RTR_LBW_RANGE_MASK_4 0xF40520 + +#define mmTPC5_RTR_LBW_RANGE_MASK_5 0xF40524 + +#define mmTPC5_RTR_LBW_RANGE_MASK_6 0xF40528 + +#define mmTPC5_RTR_LBW_RANGE_MASK_7 0xF4052C + +#define mmTPC5_RTR_LBW_RANGE_MASK_8 0xF40530 + +#define mmTPC5_RTR_LBW_RANGE_MASK_9 0xF40534 + +#define mmTPC5_RTR_LBW_RANGE_MASK_10 0xF40538 + +#define mmTPC5_RTR_LBW_RANGE_MASK_11 0xF4053C + +#define mmTPC5_RTR_LBW_RANGE_MASK_12 0xF40540 + +#define mmTPC5_RTR_LBW_RANGE_MASK_13 0xF40544 + +#define mmTPC5_RTR_LBW_RANGE_MASK_14 0xF40548 + +#define mmTPC5_RTR_LBW_RANGE_MASK_15 0xF4054C + +#define mmTPC5_RTR_LBW_RANGE_BASE_0 0xF40550 + +#define mmTPC5_RTR_LBW_RANGE_BASE_1 0xF40554 + +#define mmTPC5_RTR_LBW_RANGE_BASE_2 0xF40558 + +#define mmTPC5_RTR_LBW_RANGE_BASE_3 0xF4055C + +#define mmTPC5_RTR_LBW_RANGE_BASE_4 0xF40560 + +#define mmTPC5_RTR_LBW_RANGE_BASE_5 0xF40564 + +#define mmTPC5_RTR_LBW_RANGE_BASE_6 0xF40568 + +#define mmTPC5_RTR_LBW_RANGE_BASE_7 0xF4056C + +#define mmTPC5_RTR_LBW_RANGE_BASE_8 0xF40570 + +#define mmTPC5_RTR_LBW_RANGE_BASE_9 0xF40574 + +#define mmTPC5_RTR_LBW_RANGE_BASE_10 0xF40578 + +#define mmTPC5_RTR_LBW_RANGE_BASE_11 0xF4057C + +#define mmTPC5_RTR_LBW_RANGE_BASE_12 0xF40580 + +#define mmTPC5_RTR_LBW_RANGE_BASE_13 0xF40584 + +#define mmTPC5_RTR_LBW_RANGE_BASE_14 0xF40588 + +#define mmTPC5_RTR_LBW_RANGE_BASE_15 0xF4058C + +#define mmTPC5_RTR_RGLTR 0xF40590 + +#define mmTPC5_RTR_RGLTR_WR_RESULT 0xF40594 + +#define mmTPC5_RTR_RGLTR_RD_RESULT 0xF40598 + +#define mmTPC5_RTR_SCRAMB_EN 0xF40600 + +#define mmTPC5_RTR_NON_LIN_SCRAMB 0xF40604 + +#endif /* ASIC_REG_TPC5_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h new file mode 100644 index 000000000..94e0191c0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CFG_REGS_H_ +#define ASIC_REG_TPC6_CFG_REGS_H_ + +/* + ***************************************** + * TPC6_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF86418 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF86420 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF86424 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86428 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF86430 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86434 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF86438 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86440 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86444 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF86448 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF86450 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86454 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86458 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF86460 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF86464 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86468 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF86470 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86474 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF86478 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86480 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86484 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF86488 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF86490 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF86494 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86498 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C + +#define mmTPC6_CFG_KERNEL_SRF_0 0xF86690 + +#define mmTPC6_CFG_KERNEL_SRF_1 0xF86694 + +#define mmTPC6_CFG_KERNEL_SRF_2 0xF86698 + +#define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C + +#define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0 + +#define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4 + +#define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8 + +#define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC + +#define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0 + +#define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4 + +#define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8 + +#define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC + +#define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0 + +#define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4 + +#define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8 + +#define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC + +#define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0 + +#define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4 + +#define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8 + +#define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC + +#define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0 + +#define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4 + +#define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8 + +#define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC + +#define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0 + +#define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4 + +#define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8 + +#define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC + +#define mmTPC6_CFG_KERNEL_SRF_28 0xF86700 + +#define mmTPC6_CFG_KERNEL_SRF_29 0xF86704 + +#define mmTPC6_CFG_KERNEL_SRF_30 0xF86708 + +#define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C + +#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710 + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714 + +#define mmTPC6_CFG_RESERVED_DESC_END 0xF86738 + +#define mmTPC6_CFG_ROUND_CSR 0xF867FC + +#define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800 + +#define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804 + +#define mmTPC6_CFG_SEMAPHORE 0xF86808 + +#define mmTPC6_CFG_VFLAGS 0xF8680C + +#define mmTPC6_CFG_SFLAGS 0xF86810 + +#define mmTPC6_CFG_LFSR_POLYNOM 0xF86818 + +#define mmTPC6_CFG_STATUS 0xF8681C + +#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820 + +#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C + +#define mmTPC6_CFG_TPC_CMD 0xF86830 + +#define mmTPC6_CFG_TPC_EXECUTE 0xF86838 + +#define mmTPC6_CFG_TPC_STALL 0xF8683C + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840 + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844 + +#define mmTPC6_CFG_MSS_CONFIG 0xF86854 + +#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858 + +#define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C + +#define mmTPC6_CFG_TSB_CONFIG 0xF86860 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 + +#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 + +#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50 + +#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54 + +#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C + +#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0 + +#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8 + +#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC + +#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30 + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34 + +#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38 + +#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80 + +#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84 + +#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC + +#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0 + +#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18 + +#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C + +#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C + +#define mmTPC6_CFG_QM_SRF_0 0xF86C90 + +#define mmTPC6_CFG_QM_SRF_1 0xF86C94 + +#define mmTPC6_CFG_QM_SRF_2 0xF86C98 + +#define mmTPC6_CFG_QM_SRF_3 0xF86C9C + +#define mmTPC6_CFG_QM_SRF_4 0xF86CA0 + +#define mmTPC6_CFG_QM_SRF_5 0xF86CA4 + +#define mmTPC6_CFG_QM_SRF_6 0xF86CA8 + +#define mmTPC6_CFG_QM_SRF_7 0xF86CAC + +#define mmTPC6_CFG_QM_SRF_8 0xF86CB0 + +#define mmTPC6_CFG_QM_SRF_9 0xF86CB4 + +#define mmTPC6_CFG_QM_SRF_10 0xF86CB8 + +#define mmTPC6_CFG_QM_SRF_11 0xF86CBC + +#define mmTPC6_CFG_QM_SRF_12 0xF86CC0 + +#define mmTPC6_CFG_QM_SRF_13 0xF86CC4 + +#define mmTPC6_CFG_QM_SRF_14 0xF86CC8 + +#define mmTPC6_CFG_QM_SRF_15 0xF86CCC + +#define mmTPC6_CFG_QM_SRF_16 0xF86CD0 + +#define mmTPC6_CFG_QM_SRF_17 0xF86CD4 + +#define mmTPC6_CFG_QM_SRF_18 0xF86CD8 + +#define mmTPC6_CFG_QM_SRF_19 0xF86CDC + +#define mmTPC6_CFG_QM_SRF_20 0xF86CE0 + +#define mmTPC6_CFG_QM_SRF_21 0xF86CE4 + +#define mmTPC6_CFG_QM_SRF_22 0xF86CE8 + +#define mmTPC6_CFG_QM_SRF_23 0xF86CEC + +#define mmTPC6_CFG_QM_SRF_24 0xF86CF0 + +#define mmTPC6_CFG_QM_SRF_25 0xF86CF4 + +#define mmTPC6_CFG_QM_SRF_26 0xF86CF8 + +#define mmTPC6_CFG_QM_SRF_27 0xF86CFC + +#define mmTPC6_CFG_QM_SRF_28 0xF86D00 + +#define mmTPC6_CFG_QM_SRF_29 0xF86D04 + +#define mmTPC6_CFG_QM_SRF_30 0xF86D08 + +#define mmTPC6_CFG_QM_SRF_31 0xF86D0C + +#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10 + +#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14 + +#define mmTPC6_CFG_ARUSER 0xF86D18 + +#define mmTPC6_CFG_AWUSER 0xF86D1C + +#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00 + +#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C + +#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C + +#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C + +#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h new file mode 100644 index 000000000..7a1a0e87b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CMDQ_REGS_H_ +#define ASIC_REG_TPC6_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC6_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC6_CMDQ_GLBL_CFG0 0xF89000 + +#define mmTPC6_CMDQ_GLBL_CFG1 0xF89004 + +#define mmTPC6_CMDQ_GLBL_PROT 0xF89008 + +#define mmTPC6_CMDQ_GLBL_ERR_CFG 0xF8900C + +#define mmTPC6_CMDQ_GLBL_ERR_ADDR_LO 0xF89010 + +#define mmTPC6_CMDQ_GLBL_ERR_ADDR_HI 0xF89014 + +#define mmTPC6_CMDQ_GLBL_ERR_WDATA 0xF89018 + +#define mmTPC6_CMDQ_GLBL_SECURE_PROPS 0xF8901C + +#define mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS 0xF89020 + +#define mmTPC6_CMDQ_GLBL_STS0 0xF89024 + +#define mmTPC6_CMDQ_GLBL_STS1 0xF89028 + +#define mmTPC6_CMDQ_CQ_CFG0 0xF890B0 + +#define mmTPC6_CMDQ_CQ_CFG1 0xF890B4 + +#define mmTPC6_CMDQ_CQ_ARUSER 0xF890B8 + +#define mmTPC6_CMDQ_CQ_PTR_LO 0xF890C0 + +#define mmTPC6_CMDQ_CQ_PTR_HI 0xF890C4 + +#define mmTPC6_CMDQ_CQ_TSIZE 0xF890C8 + +#define mmTPC6_CMDQ_CQ_CTL 0xF890CC + +#define mmTPC6_CMDQ_CQ_PTR_LO_STS 0xF890D4 + +#define mmTPC6_CMDQ_CQ_PTR_HI_STS 0xF890D8 + +#define mmTPC6_CMDQ_CQ_TSIZE_STS 0xF890DC + +#define mmTPC6_CMDQ_CQ_CTL_STS 0xF890E0 + +#define mmTPC6_CMDQ_CQ_STS0 0xF890E4 + +#define mmTPC6_CMDQ_CQ_STS1 0xF890E8 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN 0xF890F0 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF890F4 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT 0xF890F8 + +#define mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF890FC + +#define mmTPC6_CMDQ_CQ_IFIFO_CNT 0xF89108 + +#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF89120 + +#define mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF89124 + +#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF89128 + +#define mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF8912C + +#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF89130 + +#define mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF89134 + +#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF89138 + +#define mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF8913C + +#define mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF89140 + +#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF89144 + +#define mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF89148 + +#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF8914C + +#define mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF89150 + +#define mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF89154 + +#define mmTPC6_CMDQ_CP_FENCE0_RDATA 0xF89158 + +#define mmTPC6_CMDQ_CP_FENCE1_RDATA 0xF8915C + +#define mmTPC6_CMDQ_CP_FENCE2_RDATA 0xF89160 + +#define mmTPC6_CMDQ_CP_FENCE3_RDATA 0xF89164 + +#define mmTPC6_CMDQ_CP_FENCE0_CNT 0xF89168 + +#define mmTPC6_CMDQ_CP_FENCE1_CNT 0xF8916C + +#define mmTPC6_CMDQ_CP_FENCE2_CNT 0xF89170 + +#define mmTPC6_CMDQ_CP_FENCE3_CNT 0xF89174 + +#define mmTPC6_CMDQ_CP_STS 0xF89178 + +#define mmTPC6_CMDQ_CP_CURRENT_INST_LO 0xF8917C + +#define mmTPC6_CMDQ_CP_CURRENT_INST_HI 0xF89180 + +#define mmTPC6_CMDQ_CP_BARRIER_CFG 0xF89184 + +#define mmTPC6_CMDQ_CP_DBG_0 0xF89188 + +#define mmTPC6_CMDQ_CQ_BUF_ADDR 0xF89308 + +#define mmTPC6_CMDQ_CQ_BUF_RDATA 0xF8930C + +#endif /* ASIC_REG_TPC6_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h new file mode 100644 index 000000000..80fa0fe0f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_QM_REGS_H_ +#define ASIC_REG_TPC6_QM_REGS_H_ + +/* + ***************************************** + * TPC6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC6_QM_GLBL_CFG0 0xF88000 + +#define mmTPC6_QM_GLBL_CFG1 0xF88004 + +#define mmTPC6_QM_GLBL_PROT 0xF88008 + +#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C + +#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88010 + +#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88014 + +#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88018 + +#define mmTPC6_QM_GLBL_SECURE_PROPS 0xF8801C + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS 0xF88020 + +#define mmTPC6_QM_GLBL_STS0 0xF88024 + +#define mmTPC6_QM_GLBL_STS1 0xF88028 + +#define mmTPC6_QM_PQ_BASE_LO 0xF88060 + +#define mmTPC6_QM_PQ_BASE_HI 0xF88064 + +#define mmTPC6_QM_PQ_SIZE 0xF88068 + +#define mmTPC6_QM_PQ_PI 0xF8806C + +#define mmTPC6_QM_PQ_CI 0xF88070 + +#define mmTPC6_QM_PQ_CFG0 0xF88074 + +#define mmTPC6_QM_PQ_CFG1 0xF88078 + +#define mmTPC6_QM_PQ_ARUSER 0xF8807C + +#define mmTPC6_QM_PQ_PUSH0 0xF88080 + +#define mmTPC6_QM_PQ_PUSH1 0xF88084 + +#define mmTPC6_QM_PQ_PUSH2 0xF88088 + +#define mmTPC6_QM_PQ_PUSH3 0xF8808C + +#define mmTPC6_QM_PQ_STS0 0xF88090 + +#define mmTPC6_QM_PQ_STS1 0xF88094 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_EN 0xF880A0 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF880A4 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_SAT 0xF880A8 + +#define mmTPC6_QM_PQ_RD_RATE_LIM_TOUT 0xF880AC + +#define mmTPC6_QM_CQ_CFG0 0xF880B0 + +#define mmTPC6_QM_CQ_CFG1 0xF880B4 + +#define mmTPC6_QM_CQ_ARUSER 0xF880B8 + +#define mmTPC6_QM_CQ_PTR_LO 0xF880C0 + +#define mmTPC6_QM_CQ_PTR_HI 0xF880C4 + +#define mmTPC6_QM_CQ_TSIZE 0xF880C8 + +#define mmTPC6_QM_CQ_CTL 0xF880CC + +#define mmTPC6_QM_CQ_PTR_LO_STS 0xF880D4 + +#define mmTPC6_QM_CQ_PTR_HI_STS 0xF880D8 + +#define mmTPC6_QM_CQ_TSIZE_STS 0xF880DC + +#define mmTPC6_QM_CQ_CTL_STS 0xF880E0 + +#define mmTPC6_QM_CQ_STS0 0xF880E4 + +#define mmTPC6_QM_CQ_STS1 0xF880E8 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_EN 0xF880F0 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF880F4 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_SAT 0xF880F8 + +#define mmTPC6_QM_CQ_RD_RATE_LIM_TOUT 0xF880FC + +#define mmTPC6_QM_CQ_IFIFO_CNT 0xF88108 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO 0xF88120 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI 0xF88124 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO 0xF88128 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI 0xF8812C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO 0xF88130 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI 0xF88134 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO 0xF88138 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI 0xF8813C + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET 0xF88140 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF88144 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF88148 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF8814C + +#define mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF88150 + +#define mmTPC6_QM_CP_LDMA_COMMIT_OFFSET 0xF88154 + +#define mmTPC6_QM_CP_FENCE0_RDATA 0xF88158 + +#define mmTPC6_QM_CP_FENCE1_RDATA 0xF8815C + +#define mmTPC6_QM_CP_FENCE2_RDATA 0xF88160 + +#define mmTPC6_QM_CP_FENCE3_RDATA 0xF88164 + +#define mmTPC6_QM_CP_FENCE0_CNT 0xF88168 + +#define mmTPC6_QM_CP_FENCE1_CNT 0xF8816C + +#define mmTPC6_QM_CP_FENCE2_CNT 0xF88170 + +#define mmTPC6_QM_CP_FENCE3_CNT 0xF88174 + +#define mmTPC6_QM_CP_STS 0xF88178 + +#define mmTPC6_QM_CP_CURRENT_INST_LO 0xF8817C + +#define mmTPC6_QM_CP_CURRENT_INST_HI 0xF88180 + +#define mmTPC6_QM_CP_BARRIER_CFG 0xF88184 + +#define mmTPC6_QM_CP_DBG_0 0xF88188 + +#define mmTPC6_QM_PQ_BUF_ADDR 0xF88300 + +#define mmTPC6_QM_PQ_BUF_RDATA 0xF88304 + +#define mmTPC6_QM_CQ_BUF_ADDR 0xF88308 + +#define mmTPC6_QM_CQ_BUF_RDATA 0xF8830C + +#endif /* ASIC_REG_TPC6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h new file mode 100644 index 000000000..d6cae8b8a --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_RTR_REGS_H_ +#define ASIC_REG_TPC6_RTR_REGS_H_ + +/* + ***************************************** + * TPC6_RTR (Prototype: TPC_RTR) + ***************************************** + */ + +#define mmTPC6_RTR_HBW_RD_RQ_E_ARB 0xF80100 + +#define mmTPC6_RTR_HBW_RD_RQ_W_ARB 0xF80104 + +#define mmTPC6_RTR_HBW_RD_RQ_N_ARB 0xF80108 + +#define mmTPC6_RTR_HBW_RD_RQ_S_ARB 0xF8010C + +#define mmTPC6_RTR_HBW_RD_RQ_L_ARB 0xF80110 + +#define mmTPC6_RTR_HBW_E_ARB_MAX 0xF80120 + +#define mmTPC6_RTR_HBW_W_ARB_MAX 0xF80124 + +#define mmTPC6_RTR_HBW_N_ARB_MAX 0xF80128 + +#define mmTPC6_RTR_HBW_S_ARB_MAX 0xF8012C + +#define mmTPC6_RTR_HBW_L_ARB_MAX 0xF80130 + +#define mmTPC6_RTR_HBW_RD_RS_E_ARB 0xF80140 + +#define mmTPC6_RTR_HBW_RD_RS_W_ARB 0xF80144 + +#define mmTPC6_RTR_HBW_RD_RS_N_ARB 0xF80148 + +#define mmTPC6_RTR_HBW_RD_RS_S_ARB 0xF8014C + +#define mmTPC6_RTR_HBW_RD_RS_L_ARB 0xF80150 + +#define mmTPC6_RTR_HBW_WR_RQ_E_ARB 0xF80170 + +#define mmTPC6_RTR_HBW_WR_RQ_W_ARB 0xF80174 + +#define mmTPC6_RTR_HBW_WR_RQ_N_ARB 0xF80178 + +#define mmTPC6_RTR_HBW_WR_RQ_S_ARB 0xF8017C + +#define mmTPC6_RTR_HBW_WR_RQ_L_ARB 0xF80180 + +#define mmTPC6_RTR_HBW_WR_RS_E_ARB 0xF80190 + +#define mmTPC6_RTR_HBW_WR_RS_W_ARB 0xF80194 + +#define mmTPC6_RTR_HBW_WR_RS_N_ARB 0xF80198 + +#define mmTPC6_RTR_HBW_WR_RS_S_ARB 0xF8019C + +#define mmTPC6_RTR_HBW_WR_RS_L_ARB 0xF801A0 + +#define mmTPC6_RTR_LBW_RD_RQ_E_ARB 0xF80200 + +#define mmTPC6_RTR_LBW_RD_RQ_W_ARB 0xF80204 + +#define mmTPC6_RTR_LBW_RD_RQ_N_ARB 0xF80208 + +#define mmTPC6_RTR_LBW_RD_RQ_S_ARB 0xF8020C + +#define mmTPC6_RTR_LBW_RD_RQ_L_ARB 0xF80210 + +#define mmTPC6_RTR_LBW_E_ARB_MAX 0xF80220 + +#define mmTPC6_RTR_LBW_W_ARB_MAX 0xF80224 + +#define mmTPC6_RTR_LBW_N_ARB_MAX 0xF80228 + +#define mmTPC6_RTR_LBW_S_ARB_MAX 0xF8022C + +#define mmTPC6_RTR_LBW_L_ARB_MAX 0xF80230 + +#define mmTPC6_RTR_LBW_RD_RS_E_ARB 0xF80250 + +#define mmTPC6_RTR_LBW_RD_RS_W_ARB 0xF80254 + +#define mmTPC6_RTR_LBW_RD_RS_N_ARB 0xF80258 + +#define mmTPC6_RTR_LBW_RD_RS_S_ARB 0xF8025C + +#define mmTPC6_RTR_LBW_RD_RS_L_ARB 0xF80260 + +#define mmTPC6_RTR_LBW_WR_RQ_E_ARB 0xF80270 + +#define mmTPC6_RTR_LBW_WR_RQ_W_ARB 0xF80274 + +#define mmTPC6_RTR_LBW_WR_RQ_N_ARB 0xF80278 + +#define mmTPC6_RTR_LBW_WR_RQ_S_ARB 0xF8027C + +#define mmTPC6_RTR_LBW_WR_RQ_L_ARB 0xF80280 + +#define mmTPC6_RTR_LBW_WR_RS_E_ARB 0xF80290 + +#define mmTPC6_RTR_LBW_WR_RS_W_ARB 0xF80294 + +#define mmTPC6_RTR_LBW_WR_RS_N_ARB 0xF80298 + +#define mmTPC6_RTR_LBW_WR_RS_S_ARB 0xF8029C + +#define mmTPC6_RTR_LBW_WR_RS_L_ARB 0xF802A0 + +#define mmTPC6_RTR_DBG_E_ARB 0xF80300 + +#define mmTPC6_RTR_DBG_W_ARB 0xF80304 + +#define mmTPC6_RTR_DBG_N_ARB 0xF80308 + +#define mmTPC6_RTR_DBG_S_ARB 0xF8030C + +#define mmTPC6_RTR_DBG_L_ARB 0xF80310 + +#define mmTPC6_RTR_DBG_E_ARB_MAX 0xF80320 + +#define mmTPC6_RTR_DBG_W_ARB_MAX 0xF80324 + +#define mmTPC6_RTR_DBG_N_ARB_MAX 0xF80328 + +#define mmTPC6_RTR_DBG_S_ARB_MAX 0xF8032C + +#define mmTPC6_RTR_DBG_L_ARB_MAX 0xF80330 + +#define mmTPC6_RTR_SPLIT_COEF_0 0xF80400 + +#define mmTPC6_RTR_SPLIT_COEF_1 0xF80404 + +#define mmTPC6_RTR_SPLIT_COEF_2 0xF80408 + +#define mmTPC6_RTR_SPLIT_COEF_3 0xF8040C + +#define mmTPC6_RTR_SPLIT_COEF_4 0xF80410 + +#define mmTPC6_RTR_SPLIT_COEF_5 0xF80414 + +#define mmTPC6_RTR_SPLIT_COEF_6 0xF80418 + +#define mmTPC6_RTR_SPLIT_COEF_7 0xF8041C + +#define mmTPC6_RTR_SPLIT_COEF_8 0xF80420 + +#define mmTPC6_RTR_SPLIT_COEF_9 0xF80424 + +#define mmTPC6_RTR_SPLIT_CFG 0xF80440 + +#define mmTPC6_RTR_SPLIT_RD_SAT 0xF80444 + +#define mmTPC6_RTR_SPLIT_RD_RST_TOKEN 0xF80448 + +#define mmTPC6_RTR_SPLIT_RD_TIMEOUT_0 0xF8044C + +#define mmTPC6_RTR_SPLIT_RD_TIMEOUT_1 0xF80450 + +#define mmTPC6_RTR_SPLIT_WR_SAT 0xF80454 + +#define mmTPC6_RTR_WPLIT_WR_TST_TOLEN 0xF80458 + +#define mmTPC6_RTR_SPLIT_WR_TIMEOUT_0 0xF8045C + +#define mmTPC6_RTR_SPLIT_WR_TIMEOUT_1 0xF80460 + +#define mmTPC6_RTR_HBW_RANGE_HIT 0xF80470 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_0 0xF80480 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_1 0xF80484 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_2 0xF80488 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_3 0xF8048C + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_4 0xF80490 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_5 0xF80494 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_6 0xF80498 + +#define mmTPC6_RTR_HBW_RANGE_MASK_L_7 0xF8049C + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_0 0xF804A0 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_1 0xF804A4 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_2 0xF804A8 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_3 0xF804AC + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_4 0xF804B0 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_5 0xF804B4 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_6 0xF804B8 + +#define mmTPC6_RTR_HBW_RANGE_MASK_H_7 0xF804BC + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_0 0xF804C0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_1 0xF804C4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_2 0xF804C8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_3 0xF804CC + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_4 0xF804D0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_5 0xF804D4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_6 0xF804D8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_L_7 0xF804DC + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_0 0xF804E0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_1 0xF804E4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_2 0xF804E8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_3 0xF804EC + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_4 0xF804F0 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_5 0xF804F4 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_6 0xF804F8 + +#define mmTPC6_RTR_HBW_RANGE_BASE_H_7 0xF804FC + +#define mmTPC6_RTR_LBW_RANGE_HIT 0xF80500 + +#define mmTPC6_RTR_LBW_RANGE_MASK_0 0xF80510 + +#define mmTPC6_RTR_LBW_RANGE_MASK_1 0xF80514 + +#define mmTPC6_RTR_LBW_RANGE_MASK_2 0xF80518 + +#define mmTPC6_RTR_LBW_RANGE_MASK_3 0xF8051C + +#define mmTPC6_RTR_LBW_RANGE_MASK_4 0xF80520 + +#define mmTPC6_RTR_LBW_RANGE_MASK_5 0xF80524 + +#define mmTPC6_RTR_LBW_RANGE_MASK_6 0xF80528 + +#define mmTPC6_RTR_LBW_RANGE_MASK_7 0xF8052C + +#define mmTPC6_RTR_LBW_RANGE_MASK_8 0xF80530 + +#define mmTPC6_RTR_LBW_RANGE_MASK_9 0xF80534 + +#define mmTPC6_RTR_LBW_RANGE_MASK_10 0xF80538 + +#define mmTPC6_RTR_LBW_RANGE_MASK_11 0xF8053C + +#define mmTPC6_RTR_LBW_RANGE_MASK_12 0xF80540 + +#define mmTPC6_RTR_LBW_RANGE_MASK_13 0xF80544 + +#define mmTPC6_RTR_LBW_RANGE_MASK_14 0xF80548 + +#define mmTPC6_RTR_LBW_RANGE_MASK_15 0xF8054C + +#define mmTPC6_RTR_LBW_RANGE_BASE_0 0xF80550 + +#define mmTPC6_RTR_LBW_RANGE_BASE_1 0xF80554 + +#define mmTPC6_RTR_LBW_RANGE_BASE_2 0xF80558 + +#define mmTPC6_RTR_LBW_RANGE_BASE_3 0xF8055C + +#define mmTPC6_RTR_LBW_RANGE_BASE_4 0xF80560 + +#define mmTPC6_RTR_LBW_RANGE_BASE_5 0xF80564 + +#define mmTPC6_RTR_LBW_RANGE_BASE_6 0xF80568 + +#define mmTPC6_RTR_LBW_RANGE_BASE_7 0xF8056C + +#define mmTPC6_RTR_LBW_RANGE_BASE_8 0xF80570 + +#define mmTPC6_RTR_LBW_RANGE_BASE_9 0xF80574 + +#define mmTPC6_RTR_LBW_RANGE_BASE_10 0xF80578 + +#define mmTPC6_RTR_LBW_RANGE_BASE_11 0xF8057C + +#define mmTPC6_RTR_LBW_RANGE_BASE_12 0xF80580 + +#define mmTPC6_RTR_LBW_RANGE_BASE_13 0xF80584 + +#define mmTPC6_RTR_LBW_RANGE_BASE_14 0xF80588 + +#define mmTPC6_RTR_LBW_RANGE_BASE_15 0xF8058C + +#define mmTPC6_RTR_RGLTR 0xF80590 + +#define mmTPC6_RTR_RGLTR_WR_RESULT 0xF80594 + +#define mmTPC6_RTR_RGLTR_RD_RESULT 0xF80598 + +#define mmTPC6_RTR_SCRAMB_EN 0xF80600 + +#define mmTPC6_RTR_NON_LIN_SCRAMB 0xF80604 + +#endif /* ASIC_REG_TPC6_RTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h new file mode 100644 index 000000000..234147adb --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h @@ -0,0 +1,886 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CFG_REGS_H_ +#define ASIC_REG_TPC7_CFG_REGS_H_ + +/* + ***************************************** + * TPC7_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6418 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC641C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC6420 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6424 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6428 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC642C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6430 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6434 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC6438 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xFC643C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6440 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6444 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6448 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC644C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC6450 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6454 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6458 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC645C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC6460 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6464 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6468 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC646C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6470 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6474 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC6478 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xFC647C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6480 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6484 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6488 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC648C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC6490 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6494 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6498 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC649C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC64A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC64A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC64A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC64AC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xFC64B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC64B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC64B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xFC64BC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC64C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC64C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xFC64C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC64CC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC64D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xFC64D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64DC + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xFC64E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64EC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xFC64FC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC6500 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC6504 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6508 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC650C + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC6510 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6514 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC6518 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC651C + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6520 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC6524 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC6528 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xFC652C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC6530 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC6534 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC6538 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC653C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC6540 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC6544 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6548 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC654C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC6550 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6554 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6558 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC655C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6560 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6564 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC6568 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xFC656C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6570 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6574 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6578 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC657C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC6580 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6584 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6588 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC658C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC6590 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6594 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6598 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC659C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xFC65A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC65A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC65A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xFC65AC + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC65B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC65B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xFC65B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC65BC + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC65C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xFC65C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC65C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC65CC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC65D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC65D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC65D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC65DC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xFC65E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC65E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC65E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xFC65EC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC65F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC65F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xFC65F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC65FC + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC6600 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6604 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6608 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC660C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6610 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6614 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC6618 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC661C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6620 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6624 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC6628 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xFC662C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC6630 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC6634 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6638 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC663C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC6640 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6644 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC6648 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC664C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6650 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC6654 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC6658 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xFC665C + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6660 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC6664 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6668 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC666C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6670 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC6674 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC6678 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC667C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC6680 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC6684 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC6688 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC668C + +#define mmTPC7_CFG_KERNEL_SRF_0 0xFC6690 + +#define mmTPC7_CFG_KERNEL_SRF_1 0xFC6694 + +#define mmTPC7_CFG_KERNEL_SRF_2 0xFC6698 + +#define mmTPC7_CFG_KERNEL_SRF_3 0xFC669C + +#define mmTPC7_CFG_KERNEL_SRF_4 0xFC66A0 + +#define mmTPC7_CFG_KERNEL_SRF_5 0xFC66A4 + +#define mmTPC7_CFG_KERNEL_SRF_6 0xFC66A8 + +#define mmTPC7_CFG_KERNEL_SRF_7 0xFC66AC + +#define mmTPC7_CFG_KERNEL_SRF_8 0xFC66B0 + +#define mmTPC7_CFG_KERNEL_SRF_9 0xFC66B4 + +#define mmTPC7_CFG_KERNEL_SRF_10 0xFC66B8 + +#define mmTPC7_CFG_KERNEL_SRF_11 0xFC66BC + +#define mmTPC7_CFG_KERNEL_SRF_12 0xFC66C0 + +#define mmTPC7_CFG_KERNEL_SRF_13 0xFC66C4 + +#define mmTPC7_CFG_KERNEL_SRF_14 0xFC66C8 + +#define mmTPC7_CFG_KERNEL_SRF_15 0xFC66CC + +#define mmTPC7_CFG_KERNEL_SRF_16 0xFC66D0 + +#define mmTPC7_CFG_KERNEL_SRF_17 0xFC66D4 + +#define mmTPC7_CFG_KERNEL_SRF_18 0xFC66D8 + +#define mmTPC7_CFG_KERNEL_SRF_19 0xFC66DC + +#define mmTPC7_CFG_KERNEL_SRF_20 0xFC66E0 + +#define mmTPC7_CFG_KERNEL_SRF_21 0xFC66E4 + +#define mmTPC7_CFG_KERNEL_SRF_22 0xFC66E8 + +#define mmTPC7_CFG_KERNEL_SRF_23 0xFC66EC + +#define mmTPC7_CFG_KERNEL_SRF_24 0xFC66F0 + +#define mmTPC7_CFG_KERNEL_SRF_25 0xFC66F4 + +#define mmTPC7_CFG_KERNEL_SRF_26 0xFC66F8 + +#define mmTPC7_CFG_KERNEL_SRF_27 0xFC66FC + +#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6700 + +#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6704 + +#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6708 + +#define mmTPC7_CFG_KERNEL_SRF_31 0xFC670C + +#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC6710 + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6714 + +#define mmTPC7_CFG_RESERVED_DESC_END 0xFC6738 + +#define mmTPC7_CFG_ROUND_CSR 0xFC67FC + +#define mmTPC7_CFG_TBUF_BASE_ADDR_LOW 0xFC6800 + +#define mmTPC7_CFG_TBUF_BASE_ADDR_HIGH 0xFC6804 + +#define mmTPC7_CFG_SEMAPHORE 0xFC6808 + +#define mmTPC7_CFG_VFLAGS 0xFC680C + +#define mmTPC7_CFG_SFLAGS 0xFC6810 + +#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6818 + +#define mmTPC7_CFG_STATUS 0xFC681C + +#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6820 + +#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6824 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_LOW 0xFC6828 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC682C + +#define mmTPC7_CFG_TPC_CMD 0xFC6830 + +#define mmTPC7_CFG_TPC_EXECUTE 0xFC6838 + +#define mmTPC7_CFG_TPC_STALL 0xFC683C + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6840 + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6844 + +#define mmTPC7_CFG_MSS_CONFIG 0xFC6854 + +#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6858 + +#define mmTPC7_CFG_TPC_INTR_MASK 0xFC685C + +#define mmTPC7_CFG_TSB_CONFIG 0xFC6860 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04 + +#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08 + +#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6A18 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A1C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A20 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6A24 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A28 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A2C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6A30 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A34 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A38 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xFC6A3C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A40 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A44 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6A48 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A4C + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A50 + +#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A54 + +#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A58 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A5C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A60 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6A64 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A68 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A6C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6A70 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A74 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A78 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xFC6A7C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A80 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A84 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6A88 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A8C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A90 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6A94 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A98 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A9C + +#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6AA0 + +#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6AA4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6AA8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6AAC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xFC6AB0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6AB4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6AB8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xFC6ABC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6AC0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6AC4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xFC6AC8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6ACC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6AD0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xFC6AD4 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AD8 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6ADC + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xFC6AE0 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AE4 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AE8 + +#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AEC + +#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AF0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AF4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6AF8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xFC6AFC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6B00 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6B04 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6B08 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6B0C + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6B10 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6B14 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6B18 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6B1C + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6B20 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6B24 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6B28 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xFC6B2C + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6B30 + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6B34 + +#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6B38 + +#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6B3C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6B40 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6B44 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6B48 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6B4C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6B50 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6B54 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B58 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B5C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6B60 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B64 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B68 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xFC6B6C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B70 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B74 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6B78 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B7C + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B80 + +#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B84 + +#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B88 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B8C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B90 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6B94 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B98 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B9C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xFC6BA0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6BA4 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6BA8 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xFC6BAC + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6BB0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6BB4 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xFC6BB8 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6BBC + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6BC0 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xFC6BC4 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6BC8 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6BCC + +#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6BD0 + +#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6BD4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6BD8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6BDC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xFC6BE0 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6BE4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6BE8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xFC6BEC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6BF0 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6BF4 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xFC6BF8 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6BFC + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6C00 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6C04 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6C08 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6C0C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6C10 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6C14 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6C18 + +#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6C1C + +#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6C20 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6C24 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6C28 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xFC6C2C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6C30 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6C34 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6C38 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6C3C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6C40 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6C44 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6C48 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6C4C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6C50 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6C54 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6C58 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xFC6C5C + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6C60 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6C64 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6C68 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6C6C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6C70 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6C74 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6C78 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6C7C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6C80 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6C84 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6C88 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6C8C + +#define mmTPC7_CFG_QM_SRF_0 0xFC6C90 + +#define mmTPC7_CFG_QM_SRF_1 0xFC6C94 + +#define mmTPC7_CFG_QM_SRF_2 0xFC6C98 + +#define mmTPC7_CFG_QM_SRF_3 0xFC6C9C + +#define mmTPC7_CFG_QM_SRF_4 0xFC6CA0 + +#define mmTPC7_CFG_QM_SRF_5 0xFC6CA4 + +#define mmTPC7_CFG_QM_SRF_6 0xFC6CA8 + +#define mmTPC7_CFG_QM_SRF_7 0xFC6CAC + +#define mmTPC7_CFG_QM_SRF_8 0xFC6CB0 + +#define mmTPC7_CFG_QM_SRF_9 0xFC6CB4 + +#define mmTPC7_CFG_QM_SRF_10 0xFC6CB8 + +#define mmTPC7_CFG_QM_SRF_11 0xFC6CBC + +#define mmTPC7_CFG_QM_SRF_12 0xFC6CC0 + +#define mmTPC7_CFG_QM_SRF_13 0xFC6CC4 + +#define mmTPC7_CFG_QM_SRF_14 0xFC6CC8 + +#define mmTPC7_CFG_QM_SRF_15 0xFC6CCC + +#define mmTPC7_CFG_QM_SRF_16 0xFC6CD0 + +#define mmTPC7_CFG_QM_SRF_17 0xFC6CD4 + +#define mmTPC7_CFG_QM_SRF_18 0xFC6CD8 + +#define mmTPC7_CFG_QM_SRF_19 0xFC6CDC + +#define mmTPC7_CFG_QM_SRF_20 0xFC6CE0 + +#define mmTPC7_CFG_QM_SRF_21 0xFC6CE4 + +#define mmTPC7_CFG_QM_SRF_22 0xFC6CE8 + +#define mmTPC7_CFG_QM_SRF_23 0xFC6CEC + +#define mmTPC7_CFG_QM_SRF_24 0xFC6CF0 + +#define mmTPC7_CFG_QM_SRF_25 0xFC6CF4 + +#define mmTPC7_CFG_QM_SRF_26 0xFC6CF8 + +#define mmTPC7_CFG_QM_SRF_27 0xFC6CFC + +#define mmTPC7_CFG_QM_SRF_28 0xFC6D00 + +#define mmTPC7_CFG_QM_SRF_29 0xFC6D04 + +#define mmTPC7_CFG_QM_SRF_30 0xFC6D08 + +#define mmTPC7_CFG_QM_SRF_31 0xFC6D0C + +#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6D10 + +#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D14 + +#define mmTPC7_CFG_ARUSER 0xFC6D18 + +#define mmTPC7_CFG_AWUSER 0xFC6D1C + +#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC6E00 + +#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC6E04 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC6E08 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC6E0C + +#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC6E10 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC6E14 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC6E18 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC6E1C + +#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC6E20 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC6E24 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC6E28 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC6E2C + +#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h new file mode 100644 index 000000000..4c160632f --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CMDQ_REGS_H_ +#define ASIC_REG_TPC7_CMDQ_REGS_H_ + +/* + ***************************************** + * TPC7_CMDQ (Prototype: CMDQ) + ***************************************** + */ + +#define mmTPC7_CMDQ_GLBL_CFG0 0xFC9000 + +#define mmTPC7_CMDQ_GLBL_CFG1 0xFC9004 + +#define mmTPC7_CMDQ_GLBL_PROT 0xFC9008 + +#define mmTPC7_CMDQ_GLBL_ERR_CFG 0xFC900C + +#define mmTPC7_CMDQ_GLBL_ERR_ADDR_LO 0xFC9010 + +#define mmTPC7_CMDQ_GLBL_ERR_ADDR_HI 0xFC9014 + +#define mmTPC7_CMDQ_GLBL_ERR_WDATA 0xFC9018 + +#define mmTPC7_CMDQ_GLBL_SECURE_PROPS 0xFC901C + +#define mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS 0xFC9020 + +#define mmTPC7_CMDQ_GLBL_STS0 0xFC9024 + +#define mmTPC7_CMDQ_GLBL_STS1 0xFC9028 + +#define mmTPC7_CMDQ_CQ_CFG0 0xFC90B0 + +#define mmTPC7_CMDQ_CQ_CFG1 0xFC90B4 + +#define mmTPC7_CMDQ_CQ_ARUSER 0xFC90B8 + +#define mmTPC7_CMDQ_CQ_PTR_LO 0xFC90C0 + +#define mmTPC7_CMDQ_CQ_PTR_HI 0xFC90C4 + +#define mmTPC7_CMDQ_CQ_TSIZE 0xFC90C8 + +#define mmTPC7_CMDQ_CQ_CTL 0xFC90CC + +#define mmTPC7_CMDQ_CQ_PTR_LO_STS 0xFC90D4 + +#define mmTPC7_CMDQ_CQ_PTR_HI_STS 0xFC90D8 + +#define mmTPC7_CMDQ_CQ_TSIZE_STS 0xFC90DC + +#define mmTPC7_CMDQ_CQ_CTL_STS 0xFC90E0 + +#define mmTPC7_CMDQ_CQ_STS0 0xFC90E4 + +#define mmTPC7_CMDQ_CQ_STS1 0xFC90E8 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN 0xFC90F0 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xFC90F4 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT 0xFC90F8 + +#define mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT 0xFC90FC + +#define mmTPC7_CMDQ_CQ_IFIFO_CNT 0xFC9108 + +#define mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO 0xFC9120 + +#define mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI 0xFC9124 + +#define mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO 0xFC9128 + +#define mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI 0xFC912C + +#define mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO 0xFC9130 + +#define mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI 0xFC9134 + +#define mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO 0xFC9138 + +#define mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI 0xFC913C + +#define mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET 0xFC9140 + +#define mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xFC9144 + +#define mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xFC9148 + +#define mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xFC914C + +#define mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xFC9150 + +#define mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET 0xFC9154 + +#define mmTPC7_CMDQ_CP_FENCE0_RDATA 0xFC9158 + +#define mmTPC7_CMDQ_CP_FENCE1_RDATA 0xFC915C + +#define mmTPC7_CMDQ_CP_FENCE2_RDATA 0xFC9160 + +#define mmTPC7_CMDQ_CP_FENCE3_RDATA 0xFC9164 + +#define mmTPC7_CMDQ_CP_FENCE0_CNT 0xFC9168 + +#define mmTPC7_CMDQ_CP_FENCE1_CNT 0xFC916C + +#define mmTPC7_CMDQ_CP_FENCE2_CNT 0xFC9170 + +#define mmTPC7_CMDQ_CP_FENCE3_CNT 0xFC9174 + +#define mmTPC7_CMDQ_CP_STS 0xFC9178 + +#define mmTPC7_CMDQ_CP_CURRENT_INST_LO 0xFC917C + +#define mmTPC7_CMDQ_CP_CURRENT_INST_HI 0xFC9180 + +#define mmTPC7_CMDQ_CP_BARRIER_CFG 0xFC9184 + +#define mmTPC7_CMDQ_CP_DBG_0 0xFC9188 + +#define mmTPC7_CMDQ_CQ_BUF_ADDR 0xFC9308 + +#define mmTPC7_CMDQ_CQ_BUF_RDATA 0xFC930C + +#endif /* ASIC_REG_TPC7_CMDQ_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h new file mode 100644 index 000000000..0c13d4d16 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_NRTR_REGS_H_ +#define ASIC_REG_TPC7_NRTR_REGS_H_ + +/* + ***************************************** + * TPC7_NRTR (Prototype: IF_NRTR) + ***************************************** + */ + +#define mmTPC7_NRTR_HBW_MAX_CRED 0xFC0100 + +#define mmTPC7_NRTR_LBW_MAX_CRED 0xFC0120 + +#define mmTPC7_NRTR_DBG_E_ARB 0xFC0300 + +#define mmTPC7_NRTR_DBG_W_ARB 0xFC0304 + +#define mmTPC7_NRTR_DBG_N_ARB 0xFC0308 + +#define mmTPC7_NRTR_DBG_S_ARB 0xFC030C + +#define mmTPC7_NRTR_DBG_L_ARB 0xFC0310 + +#define mmTPC7_NRTR_DBG_E_ARB_MAX 0xFC0320 + +#define mmTPC7_NRTR_DBG_W_ARB_MAX 0xFC0324 + +#define mmTPC7_NRTR_DBG_N_ARB_MAX 0xFC0328 + +#define mmTPC7_NRTR_DBG_S_ARB_MAX 0xFC032C + +#define mmTPC7_NRTR_DBG_L_ARB_MAX 0xFC0330 + +#define mmTPC7_NRTR_SPLIT_COEF_0 0xFC0400 + +#define mmTPC7_NRTR_SPLIT_COEF_1 0xFC0404 + +#define mmTPC7_NRTR_SPLIT_COEF_2 0xFC0408 + +#define mmTPC7_NRTR_SPLIT_COEF_3 0xFC040C + +#define mmTPC7_NRTR_SPLIT_COEF_4 0xFC0410 + +#define mmTPC7_NRTR_SPLIT_COEF_5 0xFC0414 + +#define mmTPC7_NRTR_SPLIT_COEF_6 0xFC0418 + +#define mmTPC7_NRTR_SPLIT_COEF_7 0xFC041C + +#define mmTPC7_NRTR_SPLIT_COEF_8 0xFC0420 + +#define mmTPC7_NRTR_SPLIT_COEF_9 0xFC0424 + +#define mmTPC7_NRTR_SPLIT_CFG 0xFC0440 + +#define mmTPC7_NRTR_SPLIT_RD_SAT 0xFC0444 + +#define mmTPC7_NRTR_SPLIT_RD_RST_TOKEN 0xFC0448 + +#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_0 0xFC044C + +#define mmTPC7_NRTR_SPLIT_RD_TIMEOUT_1 0xFC0450 + +#define mmTPC7_NRTR_SPLIT_WR_SAT 0xFC0454 + +#define mmTPC7_NRTR_WPLIT_WR_TST_TOLEN 0xFC0458 + +#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_0 0xFC045C + +#define mmTPC7_NRTR_SPLIT_WR_TIMEOUT_1 0xFC0460 + +#define mmTPC7_NRTR_HBW_RANGE_HIT 0xFC0470 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_0 0xFC0480 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_1 0xFC0484 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_2 0xFC0488 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_3 0xFC048C + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_4 0xFC0490 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_5 0xFC0494 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_6 0xFC0498 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_L_7 0xFC049C + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_0 0xFC04A0 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_1 0xFC04A4 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_2 0xFC04A8 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_3 0xFC04AC + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_4 0xFC04B0 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_5 0xFC04B4 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_6 0xFC04B8 + +#define mmTPC7_NRTR_HBW_RANGE_MASK_H_7 0xFC04BC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_0 0xFC04C0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_1 0xFC04C4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_2 0xFC04C8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_3 0xFC04CC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_4 0xFC04D0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_5 0xFC04D4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_6 0xFC04D8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_L_7 0xFC04DC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_0 0xFC04E0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_1 0xFC04E4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_2 0xFC04E8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_3 0xFC04EC + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_4 0xFC04F0 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_5 0xFC04F4 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_6 0xFC04F8 + +#define mmTPC7_NRTR_HBW_RANGE_BASE_H_7 0xFC04FC + +#define mmTPC7_NRTR_LBW_RANGE_HIT 0xFC0500 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_0 0xFC0510 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_1 0xFC0514 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_2 0xFC0518 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_3 0xFC051C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_4 0xFC0520 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_5 0xFC0524 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_6 0xFC0528 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_7 0xFC052C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_8 0xFC0530 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_9 0xFC0534 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_10 0xFC0538 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_11 0xFC053C + +#define mmTPC7_NRTR_LBW_RANGE_MASK_12 0xFC0540 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_13 0xFC0544 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_14 0xFC0548 + +#define mmTPC7_NRTR_LBW_RANGE_MASK_15 0xFC054C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_0 0xFC0550 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_1 0xFC0554 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_2 0xFC0558 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_3 0xFC055C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_4 0xFC0560 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_5 0xFC0564 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_6 0xFC0568 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_7 0xFC056C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_8 0xFC0570 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_9 0xFC0574 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_10 0xFC0578 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_11 0xFC057C + +#define mmTPC7_NRTR_LBW_RANGE_BASE_12 0xFC0580 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_13 0xFC0584 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_14 0xFC0588 + +#define mmTPC7_NRTR_LBW_RANGE_BASE_15 0xFC058C + +#define mmTPC7_NRTR_RGLTR 0xFC0590 + +#define mmTPC7_NRTR_RGLTR_WR_RESULT 0xFC0594 + +#define mmTPC7_NRTR_RGLTR_RD_RESULT 0xFC0598 + +#define mmTPC7_NRTR_SCRAMB_EN 0xFC0600 + +#define mmTPC7_NRTR_NON_LIN_SCRAMB 0xFC0604 + +#endif /* ASIC_REG_TPC7_NRTR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h new file mode 100644 index 000000000..cbe11425b --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_QM_REGS_H_ +#define ASIC_REG_TPC7_QM_REGS_H_ + +/* + ***************************************** + * TPC7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC7_QM_GLBL_CFG0 0xFC8000 + +#define mmTPC7_QM_GLBL_CFG1 0xFC8004 + +#define mmTPC7_QM_GLBL_PROT 0xFC8008 + +#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C + +#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8010 + +#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8014 + +#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8018 + +#define mmTPC7_QM_GLBL_SECURE_PROPS 0xFC801C + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS 0xFC8020 + +#define mmTPC7_QM_GLBL_STS0 0xFC8024 + +#define mmTPC7_QM_GLBL_STS1 0xFC8028 + +#define mmTPC7_QM_PQ_BASE_LO 0xFC8060 + +#define mmTPC7_QM_PQ_BASE_HI 0xFC8064 + +#define mmTPC7_QM_PQ_SIZE 0xFC8068 + +#define mmTPC7_QM_PQ_PI 0xFC806C + +#define mmTPC7_QM_PQ_CI 0xFC8070 + +#define mmTPC7_QM_PQ_CFG0 0xFC8074 + +#define mmTPC7_QM_PQ_CFG1 0xFC8078 + +#define mmTPC7_QM_PQ_ARUSER 0xFC807C + +#define mmTPC7_QM_PQ_PUSH0 0xFC8080 + +#define mmTPC7_QM_PQ_PUSH1 0xFC8084 + +#define mmTPC7_QM_PQ_PUSH2 0xFC8088 + +#define mmTPC7_QM_PQ_PUSH3 0xFC808C + +#define mmTPC7_QM_PQ_STS0 0xFC8090 + +#define mmTPC7_QM_PQ_STS1 0xFC8094 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_EN 0xFC80A0 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xFC80A4 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_SAT 0xFC80A8 + +#define mmTPC7_QM_PQ_RD_RATE_LIM_TOUT 0xFC80AC + +#define mmTPC7_QM_CQ_CFG0 0xFC80B0 + +#define mmTPC7_QM_CQ_CFG1 0xFC80B4 + +#define mmTPC7_QM_CQ_ARUSER 0xFC80B8 + +#define mmTPC7_QM_CQ_PTR_LO 0xFC80C0 + +#define mmTPC7_QM_CQ_PTR_HI 0xFC80C4 + +#define mmTPC7_QM_CQ_TSIZE 0xFC80C8 + +#define mmTPC7_QM_CQ_CTL 0xFC80CC + +#define mmTPC7_QM_CQ_PTR_LO_STS 0xFC80D4 + +#define mmTPC7_QM_CQ_PTR_HI_STS 0xFC80D8 + +#define mmTPC7_QM_CQ_TSIZE_STS 0xFC80DC + +#define mmTPC7_QM_CQ_CTL_STS 0xFC80E0 + +#define mmTPC7_QM_CQ_STS0 0xFC80E4 + +#define mmTPC7_QM_CQ_STS1 0xFC80E8 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_EN 0xFC80F0 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xFC80F4 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_SAT 0xFC80F8 + +#define mmTPC7_QM_CQ_RD_RATE_LIM_TOUT 0xFC80FC + +#define mmTPC7_QM_CQ_IFIFO_CNT 0xFC8108 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO 0xFC8120 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI 0xFC8124 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO 0xFC8128 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI 0xFC812C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO 0xFC8130 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI 0xFC8134 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO 0xFC8138 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI 0xFC813C + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET 0xFC8140 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xFC8144 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xFC8148 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xFC814C + +#define mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xFC8150 + +#define mmTPC7_QM_CP_LDMA_COMMIT_OFFSET 0xFC8154 + +#define mmTPC7_QM_CP_FENCE0_RDATA 0xFC8158 + +#define mmTPC7_QM_CP_FENCE1_RDATA 0xFC815C + +#define mmTPC7_QM_CP_FENCE2_RDATA 0xFC8160 + +#define mmTPC7_QM_CP_FENCE3_RDATA 0xFC8164 + +#define mmTPC7_QM_CP_FENCE0_CNT 0xFC8168 + +#define mmTPC7_QM_CP_FENCE1_CNT 0xFC816C + +#define mmTPC7_QM_CP_FENCE2_CNT 0xFC8170 + +#define mmTPC7_QM_CP_FENCE3_CNT 0xFC8174 + +#define mmTPC7_QM_CP_STS 0xFC8178 + +#define mmTPC7_QM_CP_CURRENT_INST_LO 0xFC817C + +#define mmTPC7_QM_CP_CURRENT_INST_HI 0xFC8180 + +#define mmTPC7_QM_CP_BARRIER_CFG 0xFC8184 + +#define mmTPC7_QM_CP_DBG_0 0xFC8188 + +#define mmTPC7_QM_PQ_BUF_ADDR 0xFC8300 + +#define mmTPC7_QM_PQ_BUF_RDATA 0xFC8304 + +#define mmTPC7_QM_CQ_BUF_ADDR 0xFC8308 + +#define mmTPC7_QM_CQ_BUF_RDATA 0xFC830C + +#endif /* ASIC_REG_TPC7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h new file mode 100644 index 000000000..e25e19660 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC_PLL_REGS_H_ +#define ASIC_REG_TPC_PLL_REGS_H_ + +/* + ***************************************** + * TPC_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmTPC_PLL_NR 0xE01100 + +#define mmTPC_PLL_NF 0xE01104 + +#define mmTPC_PLL_OD 0xE01108 + +#define mmTPC_PLL_NB 0xE0110C + +#define mmTPC_PLL_CFG 0xE01110 + +#define mmTPC_PLL_LOSE_MASK 0xE01120 + +#define mmTPC_PLL_LOCK_INTR 0xE01128 + +#define mmTPC_PLL_LOCK_BYPASS 0xE0112C + +#define mmTPC_PLL_DATA_CHNG 0xE01130 + +#define mmTPC_PLL_RST 0xE01134 + +#define mmTPC_PLL_SLIP_WD_CNTR 0xE01150 + +#define mmTPC_PLL_DIV_FACTOR_0 0xE01200 + +#define mmTPC_PLL_DIV_FACTOR_1 0xE01204 + +#define mmTPC_PLL_DIV_FACTOR_2 0xE01208 + +#define mmTPC_PLL_DIV_FACTOR_3 0xE0120C + +#define mmTPC_PLL_DIV_FACTOR_CMD_0 0xE01220 + +#define mmTPC_PLL_DIV_FACTOR_CMD_1 0xE01224 + +#define mmTPC_PLL_DIV_FACTOR_CMD_2 0xE01228 + +#define mmTPC_PLL_DIV_FACTOR_CMD_3 0xE0122C + +#define mmTPC_PLL_DIV_SEL_0 0xE01280 + +#define mmTPC_PLL_DIV_SEL_1 0xE01284 + +#define mmTPC_PLL_DIV_SEL_2 0xE01288 + +#define mmTPC_PLL_DIV_SEL_3 0xE0128C + +#define mmTPC_PLL_DIV_EN_0 0xE012A0 + +#define mmTPC_PLL_DIV_EN_1 0xE012A4 + +#define mmTPC_PLL_DIV_EN_2 0xE012A8 + +#define mmTPC_PLL_DIV_EN_3 0xE012AC + +#define mmTPC_PLL_DIV_FACTOR_BUSY_0 0xE012C0 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_1 0xE012C4 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_2 0xE012C8 + +#define mmTPC_PLL_DIV_FACTOR_BUSY_3 0xE012CC + +#define mmTPC_PLL_CLK_GATER 0xE01300 + +#define mmTPC_PLL_CLK_RLX_0 0xE01310 + +#define mmTPC_PLL_CLK_RLX_1 0xE01314 + +#define mmTPC_PLL_CLK_RLX_2 0xE01318 + +#define mmTPC_PLL_CLK_RLX_3 0xE0131C + +#define mmTPC_PLL_REF_CNTR_PERIOD 0xE01400 + +#define mmTPC_PLL_REF_LOW_THRESHOLD 0xE01410 + +#define mmTPC_PLL_REF_HIGH_THRESHOLD 0xE01420 + +#define mmTPC_PLL_PLL_NOT_STABLE 0xE01430 + +#define mmTPC_PLL_FREQ_CALC_EN 0xE01440 + +#endif /* ASIC_REG_TPC_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya.h b/drivers/misc/habanalabs/include/goya/goya.h new file mode 100644 index 000000000..1b4ca4350 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_H +#define GOYA_H + +#define SRAM_CFG_BAR_ID 0 +#define MSIX_BAR_ID 2 +#define DDR_BAR_ID 4 + +#define CFG_BAR_SIZE 0x10000000ull /* 256MB */ +#define MSIX_BAR_SIZE 0x1000ull /* 4KB */ + +#define CFG_BASE 0x7FFC000000ull +#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ + +#define SRAM_BASE_ADDR 0x7FF0000000ull +#define SRAM_SIZE 0x32A0000 /* 50.625MB */ + +#define DRAM_PHYS_BASE 0x0ull + +#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ +#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ + +#define GOYA_MSIX_ENTRIES 8 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 2 + +#define PROT_BITS_OFFS 0xF80 + +#define DMA_MAX_NUM 5 + +#define TPC_MAX_NUM 8 + +#define MME_MAX_NUM 1 + +#endif /* GOYA_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_async_events.h b/drivers/misc/habanalabs/include/goya/goya_async_events.h new file mode 100644 index 000000000..09081401c --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_async_events.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef __GOYA_ASYNC_EVENTS_H_ +#define __GOYA_ASYNC_EVENTS_H_ + +enum goya_async_event_id { + GOYA_ASYNC_EVENT_ID_PCIE_CORE = 32, + GOYA_ASYNC_EVENT_ID_PCIE_IF = 33, + GOYA_ASYNC_EVENT_ID_PCIE_PHY = 34, + GOYA_ASYNC_EVENT_ID_TPC0_ECC = 36, + GOYA_ASYNC_EVENT_ID_TPC1_ECC = 39, + GOYA_ASYNC_EVENT_ID_TPC2_ECC = 42, + GOYA_ASYNC_EVENT_ID_TPC3_ECC = 45, + GOYA_ASYNC_EVENT_ID_TPC4_ECC = 48, + GOYA_ASYNC_EVENT_ID_TPC5_ECC = 51, + GOYA_ASYNC_EVENT_ID_TPC6_ECC = 54, + GOYA_ASYNC_EVENT_ID_TPC7_ECC = 57, + GOYA_ASYNC_EVENT_ID_MME_ECC = 60, + GOYA_ASYNC_EVENT_ID_MME_ECC_EXT = 61, + GOYA_ASYNC_EVENT_ID_MMU_ECC = 63, + GOYA_ASYNC_EVENT_ID_DMA_MACRO = 64, + GOYA_ASYNC_EVENT_ID_DMA_ECC = 66, + GOYA_ASYNC_EVENT_ID_DDR0_PARITY = 69, + GOYA_ASYNC_EVENT_ID_DDR1_PARITY = 72, + GOYA_ASYNC_EVENT_ID_CPU_IF_ECC = 75, + GOYA_ASYNC_EVENT_ID_PSOC_MEM = 78, + GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT = 79, + GOYA_ASYNC_EVENT_ID_SRAM0 = 81, + GOYA_ASYNC_EVENT_ID_SRAM1 = 82, + GOYA_ASYNC_EVENT_ID_SRAM2 = 83, + GOYA_ASYNC_EVENT_ID_SRAM3 = 84, + GOYA_ASYNC_EVENT_ID_SRAM4 = 85, + GOYA_ASYNC_EVENT_ID_SRAM5 = 86, + GOYA_ASYNC_EVENT_ID_SRAM6 = 87, + GOYA_ASYNC_EVENT_ID_SRAM7 = 88, + GOYA_ASYNC_EVENT_ID_SRAM8 = 89, + GOYA_ASYNC_EVENT_ID_SRAM9 = 90, + GOYA_ASYNC_EVENT_ID_SRAM10 = 91, + GOYA_ASYNC_EVENT_ID_SRAM11 = 92, + GOYA_ASYNC_EVENT_ID_SRAM12 = 93, + GOYA_ASYNC_EVENT_ID_SRAM13 = 94, + GOYA_ASYNC_EVENT_ID_SRAM14 = 95, + GOYA_ASYNC_EVENT_ID_SRAM15 = 96, + GOYA_ASYNC_EVENT_ID_SRAM16 = 97, + GOYA_ASYNC_EVENT_ID_SRAM17 = 98, + GOYA_ASYNC_EVENT_ID_SRAM18 = 99, + GOYA_ASYNC_EVENT_ID_SRAM19 = 100, + GOYA_ASYNC_EVENT_ID_SRAM20 = 101, + GOYA_ASYNC_EVENT_ID_SRAM21 = 102, + GOYA_ASYNC_EVENT_ID_SRAM22 = 103, + GOYA_ASYNC_EVENT_ID_SRAM23 = 104, + GOYA_ASYNC_EVENT_ID_SRAM24 = 105, + GOYA_ASYNC_EVENT_ID_SRAM25 = 106, + GOYA_ASYNC_EVENT_ID_SRAM26 = 107, + GOYA_ASYNC_EVENT_ID_SRAM27 = 108, + GOYA_ASYNC_EVENT_ID_SRAM28 = 109, + GOYA_ASYNC_EVENT_ID_SRAM29 = 110, + GOYA_ASYNC_EVENT_ID_GIC500 = 112, + GOYA_ASYNC_EVENT_ID_PCIE_DEC = 115, + GOYA_ASYNC_EVENT_ID_TPC0_DEC = 117, + GOYA_ASYNC_EVENT_ID_TPC1_DEC = 120, + GOYA_ASYNC_EVENT_ID_TPC2_DEC = 123, + GOYA_ASYNC_EVENT_ID_TPC3_DEC = 126, + GOYA_ASYNC_EVENT_ID_TPC4_DEC = 129, + GOYA_ASYNC_EVENT_ID_TPC5_DEC = 132, + GOYA_ASYNC_EVENT_ID_TPC6_DEC = 135, + GOYA_ASYNC_EVENT_ID_TPC7_DEC = 138, + GOYA_ASYNC_EVENT_ID_AXI_ECC = 139, + GOYA_ASYNC_EVENT_ID_L2_RAM_ECC = 140, + GOYA_ASYNC_EVENT_ID_MME_WACS = 141, + GOYA_ASYNC_EVENT_ID_MME_WACSD = 142, + GOYA_ASYNC_EVENT_ID_PLL0 = 143, + GOYA_ASYNC_EVENT_ID_PLL1 = 144, + GOYA_ASYNC_EVENT_ID_PLL2 = 145, + GOYA_ASYNC_EVENT_ID_PLL3 = 146, + GOYA_ASYNC_EVENT_ID_PLL4 = 147, + GOYA_ASYNC_EVENT_ID_PLL5 = 148, + GOYA_ASYNC_EVENT_ID_PLL6 = 149, + GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER = 155, + GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC = 159, + GOYA_ASYNC_EVENT_ID_PSOC = 160, + GOYA_ASYNC_EVENT_ID_PCIE_FLR = 171, + GOYA_ASYNC_EVENT_ID_PCIE_HOT_RESET = 172, + GOYA_ASYNC_EVENT_ID_PCIE_PERST = 173, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG0 = 174, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG1 = 175, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG2 = 176, + GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG3 = 177, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG0 = 178, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG1 = 179, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG2 = 180, + GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG3 = 181, + GOYA_ASYNC_EVENT_ID_PCIE_APB = 182, + GOYA_ASYNC_EVENT_ID_PCIE_QDB = 183, + GOYA_ASYNC_EVENT_ID_PCIE_BM_D_P_WR = 184, + GOYA_ASYNC_EVENT_ID_PCIE_BM_D_RD = 185, + GOYA_ASYNC_EVENT_ID_PCIE_BM_U_P_WR = 186, + GOYA_ASYNC_EVENT_ID_PCIE_BM_U_RD = 187, + GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU = 190, + GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR = 191, + GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU = 200, + GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR = 201, + GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU = 210, + GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR = 211, + GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU = 220, + GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR = 221, + GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU = 230, + GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR = 231, + GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU = 240, + GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR = 241, + GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU = 250, + GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR = 251, + GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU = 260, + GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR = 261, + GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU0 = 270, + GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU1 = 271, + GOYA_ASYNC_EVENT_ID_MME_WACS_UP = 272, + GOYA_ASYNC_EVENT_ID_MME_WACS_DOWN = 273, + GOYA_ASYNC_EVENT_ID_MMU_PAGE_FAULT = 280, + GOYA_ASYNC_EVENT_ID_MMU_WR_PERM = 281, + GOYA_ASYNC_EVENT_ID_MMU_DBG_BM = 282, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 = 290, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH1 = 291, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH2 = 292, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH3 = 293, + GOYA_ASYNC_EVENT_ID_DMA_BM_CH4 = 294, + GOYA_ASYNC_EVENT_ID_DDR0_PHY_DFI = 300, + GOYA_ASYNC_EVENT_ID_DDR0_ECC_SCRUB = 301, + GOYA_ASYNC_EVENT_ID_DDR0_DB_ECC = 302, + GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC = 303, + GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC_MC = 304, + GOYA_ASYNC_EVENT_ID_DDR0_AXI_RD = 305, + GOYA_ASYNC_EVENT_ID_DDR0_AXI_WR = 306, + GOYA_ASYNC_EVENT_ID_DDR1_PHY_DFI = 310, + GOYA_ASYNC_EVENT_ID_DDR1_ECC_SCRUB = 311, + GOYA_ASYNC_EVENT_ID_DDR1_DB_ECC = 312, + GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC = 313, + GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC_MC = 314, + GOYA_ASYNC_EVENT_ID_DDR1_AXI_RD = 315, + GOYA_ASYNC_EVENT_ID_DDR1_AXI_WR = 316, + GOYA_ASYNC_EVENT_ID_CPU_BMON = 320, + GOYA_ASYNC_EVENT_ID_TS_EAST = 322, + GOYA_ASYNC_EVENT_ID_TS_WEST = 323, + GOYA_ASYNC_EVENT_ID_TS_NORTH = 324, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_0 = 330, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_1 = 331, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_2 = 332, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_3 = 333, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_4 = 334, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET = 356, + GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT = 361, + GOYA_ASYNC_EVENT_ID_FAN = 425, + GOYA_ASYNC_EVENT_ID_TPC0_CMDQ = 430, + GOYA_ASYNC_EVENT_ID_TPC1_CMDQ = 431, + GOYA_ASYNC_EVENT_ID_TPC2_CMDQ = 432, + GOYA_ASYNC_EVENT_ID_TPC3_CMDQ = 433, + GOYA_ASYNC_EVENT_ID_TPC4_CMDQ = 434, + GOYA_ASYNC_EVENT_ID_TPC5_CMDQ = 435, + GOYA_ASYNC_EVENT_ID_TPC6_CMDQ = 436, + GOYA_ASYNC_EVENT_ID_TPC7_CMDQ = 437, + GOYA_ASYNC_EVENT_ID_TPC0_QM = 438, + GOYA_ASYNC_EVENT_ID_TPC1_QM = 439, + GOYA_ASYNC_EVENT_ID_TPC2_QM = 440, + GOYA_ASYNC_EVENT_ID_TPC3_QM = 441, + GOYA_ASYNC_EVENT_ID_TPC4_QM = 442, + GOYA_ASYNC_EVENT_ID_TPC5_QM = 443, + GOYA_ASYNC_EVENT_ID_TPC6_QM = 444, + GOYA_ASYNC_EVENT_ID_TPC7_QM = 445, + GOYA_ASYNC_EVENT_ID_MME_QM = 447, + GOYA_ASYNC_EVENT_ID_MME_CMDQ = 448, + GOYA_ASYNC_EVENT_ID_DMA0_QM = 449, + GOYA_ASYNC_EVENT_ID_DMA1_QM = 450, + GOYA_ASYNC_EVENT_ID_DMA2_QM = 451, + GOYA_ASYNC_EVENT_ID_DMA3_QM = 452, + GOYA_ASYNC_EVENT_ID_DMA4_QM = 453, + GOYA_ASYNC_EVENT_ID_DMA_ON_HBW = 454, + GOYA_ASYNC_EVENT_ID_DMA0_CH = 455, + GOYA_ASYNC_EVENT_ID_DMA1_CH = 456, + GOYA_ASYNC_EVENT_ID_DMA2_CH = 457, + GOYA_ASYNC_EVENT_ID_DMA3_CH = 458, + GOYA_ASYNC_EVENT_ID_DMA4_CH = 459, + GOYA_ASYNC_EVENT_ID_PI_UPDATE = 484, + GOYA_ASYNC_EVENT_ID_HALT_MACHINE = 485, + GOYA_ASYNC_EVENT_ID_INTS_REGISTER = 486, + GOYA_ASYNC_EVENT_ID_SOFT_RESET = 487, + GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC = 506, + GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S = 507, + GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E = 508, + GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S = 509, + GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E = 510, + GOYA_ASYNC_EVENT_ID_LAST_VALID_ID = 1023, + GOYA_ASYNC_EVENT_ID_SIZE +}; + +#endif /* __GOYA_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya_coresight.h b/drivers/misc/habanalabs/include/goya/goya_coresight.h new file mode 100644 index 000000000..6e933c0ca --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_coresight.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_CORESIGHT_H +#define GOYA_CORESIGHT_H + +enum goya_debug_stm_regs_index { + GOYA_STM_FIRST = 0, + GOYA_STM_CPU = GOYA_STM_FIRST, + GOYA_STM_DMA_CH_0_CS, + GOYA_STM_DMA_CH_1_CS, + GOYA_STM_DMA_CH_2_CS, + GOYA_STM_DMA_CH_3_CS, + GOYA_STM_DMA_CH_4_CS, + GOYA_STM_DMA_MACRO_CS, + GOYA_STM_MME1_SBA, + GOYA_STM_MME3_SBB, + GOYA_STM_MME4_WACS2, + GOYA_STM_MME4_WACS, + GOYA_STM_MMU_CS, + GOYA_STM_PCIE, + GOYA_STM_PSOC, + GOYA_STM_TPC0_EML, + GOYA_STM_TPC1_EML, + GOYA_STM_TPC2_EML, + GOYA_STM_TPC3_EML, + GOYA_STM_TPC4_EML, + GOYA_STM_TPC5_EML, + GOYA_STM_TPC6_EML, + GOYA_STM_TPC7_EML, + GOYA_STM_LAST = GOYA_STM_TPC7_EML +}; + +enum goya_debug_etf_regs_index { + GOYA_ETF_FIRST = 0, + GOYA_ETF_CPU_0 = GOYA_ETF_FIRST, + GOYA_ETF_CPU_1, + GOYA_ETF_CPU_TRACE, + GOYA_ETF_DMA_CH_0_CS, + GOYA_ETF_DMA_CH_1_CS, + GOYA_ETF_DMA_CH_2_CS, + GOYA_ETF_DMA_CH_3_CS, + GOYA_ETF_DMA_CH_4_CS, + GOYA_ETF_DMA_MACRO_CS, + GOYA_ETF_MME1_SBA, + GOYA_ETF_MME3_SBB, + GOYA_ETF_MME4_WACS2, + GOYA_ETF_MME4_WACS, + GOYA_ETF_MMU_CS, + GOYA_ETF_PCIE, + GOYA_ETF_PSOC, + GOYA_ETF_TPC0_EML, + GOYA_ETF_TPC1_EML, + GOYA_ETF_TPC2_EML, + GOYA_ETF_TPC3_EML, + GOYA_ETF_TPC4_EML, + GOYA_ETF_TPC5_EML, + GOYA_ETF_TPC6_EML, + GOYA_ETF_TPC7_EML, + GOYA_ETF_LAST = GOYA_ETF_TPC7_EML +}; + +enum goya_debug_funnel_regs_index { + GOYA_FUNNEL_FIRST = 0, + GOYA_FUNNEL_CPU = GOYA_FUNNEL_FIRST, + GOYA_FUNNEL_DMA_CH_6_1, + GOYA_FUNNEL_DMA_MACRO_3_1, + GOYA_FUNNEL_MME0_RTR, + GOYA_FUNNEL_MME1_RTR, + GOYA_FUNNEL_MME2_RTR, + GOYA_FUNNEL_MME3_RTR, + GOYA_FUNNEL_MME4_RTR, + GOYA_FUNNEL_MME5_RTR, + GOYA_FUNNEL_PCIE, + GOYA_FUNNEL_PSOC, + GOYA_FUNNEL_TPC0_EML, + GOYA_FUNNEL_TPC1_EML, + GOYA_FUNNEL_TPC1_RTR, + GOYA_FUNNEL_TPC2_EML, + GOYA_FUNNEL_TPC2_RTR, + GOYA_FUNNEL_TPC3_EML, + GOYA_FUNNEL_TPC3_RTR, + GOYA_FUNNEL_TPC4_EML, + GOYA_FUNNEL_TPC4_RTR, + GOYA_FUNNEL_TPC5_EML, + GOYA_FUNNEL_TPC5_RTR, + GOYA_FUNNEL_TPC6_EML, + GOYA_FUNNEL_TPC6_RTR, + GOYA_FUNNEL_TPC7_EML, + GOYA_FUNNEL_LAST = GOYA_FUNNEL_TPC7_EML +}; + +enum goya_debug_bmon_regs_index { + GOYA_BMON_FIRST = 0, + GOYA_BMON_CPU_RD = GOYA_BMON_FIRST, + GOYA_BMON_CPU_WR, + GOYA_BMON_DMA_CH_0_0, + GOYA_BMON_DMA_CH_0_1, + GOYA_BMON_DMA_CH_1_0, + GOYA_BMON_DMA_CH_1_1, + GOYA_BMON_DMA_CH_2_0, + GOYA_BMON_DMA_CH_2_1, + GOYA_BMON_DMA_CH_3_0, + GOYA_BMON_DMA_CH_3_1, + GOYA_BMON_DMA_CH_4_0, + GOYA_BMON_DMA_CH_4_1, + GOYA_BMON_DMA_MACRO_0, + GOYA_BMON_DMA_MACRO_1, + GOYA_BMON_DMA_MACRO_2, + GOYA_BMON_DMA_MACRO_3, + GOYA_BMON_DMA_MACRO_4, + GOYA_BMON_DMA_MACRO_5, + GOYA_BMON_DMA_MACRO_6, + GOYA_BMON_DMA_MACRO_7, + GOYA_BMON_MME1_SBA_0, + GOYA_BMON_MME1_SBA_1, + GOYA_BMON_MME3_SBB_0, + GOYA_BMON_MME3_SBB_1, + GOYA_BMON_MME4_WACS2_0, + GOYA_BMON_MME4_WACS2_1, + GOYA_BMON_MME4_WACS2_2, + GOYA_BMON_MME4_WACS_0, + GOYA_BMON_MME4_WACS_1, + GOYA_BMON_MME4_WACS_2, + GOYA_BMON_MME4_WACS_3, + GOYA_BMON_MME4_WACS_4, + GOYA_BMON_MME4_WACS_5, + GOYA_BMON_MME4_WACS_6, + GOYA_BMON_MMU_0, + GOYA_BMON_MMU_1, + GOYA_BMON_PCIE_MSTR_RD, + GOYA_BMON_PCIE_MSTR_WR, + GOYA_BMON_PCIE_SLV_RD, + GOYA_BMON_PCIE_SLV_WR, + GOYA_BMON_TPC0_EML_0, + GOYA_BMON_TPC0_EML_1, + GOYA_BMON_TPC0_EML_2, + GOYA_BMON_TPC0_EML_3, + GOYA_BMON_TPC1_EML_0, + GOYA_BMON_TPC1_EML_1, + GOYA_BMON_TPC1_EML_2, + GOYA_BMON_TPC1_EML_3, + GOYA_BMON_TPC2_EML_0, + GOYA_BMON_TPC2_EML_1, + GOYA_BMON_TPC2_EML_2, + GOYA_BMON_TPC2_EML_3, + GOYA_BMON_TPC3_EML_0, + GOYA_BMON_TPC3_EML_1, + GOYA_BMON_TPC3_EML_2, + GOYA_BMON_TPC3_EML_3, + GOYA_BMON_TPC4_EML_0, + GOYA_BMON_TPC4_EML_1, + GOYA_BMON_TPC4_EML_2, + GOYA_BMON_TPC4_EML_3, + GOYA_BMON_TPC5_EML_0, + GOYA_BMON_TPC5_EML_1, + GOYA_BMON_TPC5_EML_2, + GOYA_BMON_TPC5_EML_3, + GOYA_BMON_TPC6_EML_0, + GOYA_BMON_TPC6_EML_1, + GOYA_BMON_TPC6_EML_2, + GOYA_BMON_TPC6_EML_3, + GOYA_BMON_TPC7_EML_0, + GOYA_BMON_TPC7_EML_1, + GOYA_BMON_TPC7_EML_2, + GOYA_BMON_TPC7_EML_3, + GOYA_BMON_LAST = GOYA_BMON_TPC7_EML_3 +}; + +enum goya_debug_spmu_regs_index { + GOYA_SPMU_FIRST = 0, + GOYA_SPMU_DMA_CH_0_CS = GOYA_SPMU_FIRST, + GOYA_SPMU_DMA_CH_1_CS, + GOYA_SPMU_DMA_CH_2_CS, + GOYA_SPMU_DMA_CH_3_CS, + GOYA_SPMU_DMA_CH_4_CS, + GOYA_SPMU_DMA_MACRO_CS, + GOYA_SPMU_MME1_SBA, + GOYA_SPMU_MME3_SBB, + GOYA_SPMU_MME4_WACS2, + GOYA_SPMU_MME4_WACS, + GOYA_SPMU_MMU_CS, + GOYA_SPMU_PCIE, + GOYA_SPMU_TPC0_EML, + GOYA_SPMU_TPC1_EML, + GOYA_SPMU_TPC2_EML, + GOYA_SPMU_TPC3_EML, + GOYA_SPMU_TPC4_EML, + GOYA_SPMU_TPC5_EML, + GOYA_SPMU_TPC6_EML, + GOYA_SPMU_TPC7_EML, + GOYA_SPMU_LAST = GOYA_SPMU_TPC7_EML +}; + +#endif /* GOYA_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_fw_if.h b/drivers/misc/habanalabs/include/goya/goya_fw_if.h new file mode 100644 index 000000000..bc05f86c7 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_fw_if.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_FW_IF_H +#define GOYA_FW_IF_H + +#define GOYA_EVENT_QUEUE_MSIX_IDX 5 + +#define CPU_BOOT_ADDR 0x7FF8040000ull + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8MB in DDR */ + +#define GOYA_PLL_FREQ_LOW 50000000 /* 50 MHz */ + +#endif /* GOYA_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_packets.h b/drivers/misc/habanalabs/include/goya/goya_packets.h new file mode 100644 index 000000000..896799204 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_packets.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2017-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_PACKETS_H +#define GOYA_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GOYA_PKT_CTL_OPCODE_SHIFT 24 +#define GOYA_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GOYA_PKT_CTL_EB_SHIFT 29 +#define GOYA_PKT_CTL_EB_MASK 0x20000000 + +#define GOYA_PKT_CTL_RB_SHIFT 30 +#define GOYA_PKT_CTL_RB_MASK 0x40000000 + +#define GOYA_PKT_CTL_MB_SHIFT 31 +#define GOYA_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct goya_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +#define GOYA_PKT_WREG32_CTL_REG_OFFSET_SHIFT 0 +#define GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK 0x0000FFFF + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GOYA_PKT_LIN_DMA_CTL_WO_SHIFT 0 +#define GOYA_PKT_LIN_DMA_CTL_WO_MASK 0x00000001 + +#define GOYA_PKT_LIN_DMA_CTL_RDCOMP_SHIFT 1 +#define GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK 0x00000002 + +#define GOYA_PKT_LIN_DMA_CTL_WRCOMP_SHIFT 2 +#define GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK 0x00000004 + +#define GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT 6 +#define GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000040 + +#define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT 20 +#define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK 0x00700000 + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GOYA_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/goya/goya_reg_map.h b/drivers/misc/habanalabs/include/goya/goya_reg_map.h new file mode 100644 index 000000000..f3ab282ca --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/goya_reg_map.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GOYA_REG_MAP_H_ +#define GOYA_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 +#define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 +#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 +#define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 + +#define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS mmPSOC_GLOBAL_CONF_WARM_REBOOT +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU mmPSOC_GLOBAL_CONF_UBOOT_MAGIC +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 + +#endif /* GOYA_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h new file mode 100644 index 000000000..d408feecd --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_GENERAL_H_ +#define INCLUDE_MMU_GENERAL_H_ + +#define PAGE_SHIFT_4KB 12 +#define PAGE_SHIFT_64KB 16 +#define PAGE_SHIFT_2MB 21 +#define PAGE_SHIFT_16MB 24 +#define PAGE_SHIFT_64MB 26 +#define PAGE_SHIFT_1GB 30 +#define PAGE_SIZE_4KB _BITUL(PAGE_SHIFT_4KB) +#define PAGE_SIZE_64KB _BITUL(PAGE_SHIFT_64KB) +#define PAGE_SIZE_2MB _BITUL(PAGE_SHIFT_2MB) +#define PAGE_SIZE_16MB _BITUL(PAGE_SHIFT_16MB) +#define PAGE_SIZE_64MB _BITUL(PAGE_SHIFT_64MB) +#define PAGE_SIZE_1GB _BITUL(PAGE_SHIFT_1GB) + +#define PAGE_PRESENT_MASK 0x0000000000001ull +#define SWAP_OUT_MASK 0x0000000000004ull +#define LAST_MASK 0x0000000000800ull +#define FLAGS_MASK 0x0000000000FFFull + +#define MMU_ARCH_5_HOPS 5 +#define MMU_ARCH_6_HOPS 6 + +#define HOP_PHYS_ADDR_MASK (~FLAGS_MASK) + +#define HL_PTE_SIZE sizeof(u64) + +/* definitions for HOP with 512 PTE entries */ +#define HOP_PTE_ENTRIES_512 512 +#define HOP_TABLE_SIZE_512_PTE (HOP_PTE_ENTRIES_512 * HL_PTE_SIZE) +#define HOP0_512_PTE_TABLES_TOTAL_SIZE (HOP_TABLE_SIZE_512_PTE * MAX_ASID) + +#define MMU_HOP0_PA43_12_SHIFT 12 +#define MMU_HOP0_PA49_44_SHIFT (12 + 32) +#define MMU_HOP0_PA63_44_SHIFT (12 + 32) + +#define MMU_CONFIG_TIMEOUT_USEC 2000 /* 2 ms */ + +enum mmu_hop_num { + MMU_HOP0, + MMU_HOP1, + MMU_HOP2, + MMU_HOP3, + MMU_HOP4, + MMU_HOP5, + MMU_HOP_MAX, +}; + +#endif /* INCLUDE_MMU_GENERAL_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h new file mode 100644 index 000000000..86511002e --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V1_0_H_ +#define INCLUDE_MMU_V1_0_H_ + +#define MMU_V1_0_HOP0_MASK 0x3000000000000ull +#define MMU_V1_0_HOP1_MASK 0x0FF8000000000ull +#define MMU_V1_0_HOP2_MASK 0x0007FC0000000ull +#define MMU_V1_0_HOP3_MASK 0x000003FE00000ull +#define MMU_V1_0_HOP4_MASK 0x00000001FF000ull + +#define MMU_V1_0_HOP0_SHIFT 48 +#define MMU_V1_0_HOP1_SHIFT 39 +#define MMU_V1_0_HOP2_SHIFT 30 +#define MMU_V1_0_HOP3_SHIFT 21 +#define MMU_V1_0_HOP4_SHIFT 12 + +#define MMU_HOP0_PA43_12 0x490004 +#define MMU_HOP0_PA49_44 0x490008 +#define MMU_ASID_BUSY 0x490000 + +#endif /* INCLUDE_MMU_V1_0_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h new file mode 100644 index 000000000..9c727a5d4 --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V1_1_H_ +#define INCLUDE_MMU_V1_1_H_ + +#define MMU_V1_1_HOP0_MASK 0x3000000000000ull +#define MMU_V1_1_HOP1_MASK 0x0FF8000000000ull +#define MMU_V1_1_HOP2_MASK 0x0007FC0000000ull +#define MMU_V1_1_HOP3_MASK 0x000003FE00000ull +#define MMU_V1_1_HOP4_MASK 0x00000001FF000ull + +#define MMU_V1_1_HOP0_SHIFT 48 +#define MMU_V1_1_HOP1_SHIFT 39 +#define MMU_V1_1_HOP2_SHIFT 30 +#define MMU_V1_1_HOP3_SHIFT 21 +#define MMU_V1_1_HOP4_SHIFT 12 + +#define MMU_ASID 0xC12004 +#define MMU_HOP0_PA43_12 0xC12008 +#define MMU_HOP0_PA49_44 0xC1200C +#define MMU_BUSY 0xC12000 + +#endif /* INCLUDE_MMU_V1_1_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h new file mode 100644 index 000000000..cd7bf25d2 --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V2_0_H_ +#define INCLUDE_MMU_V2_0_H_ + +#define HOP0_MASK_4K 0xFE00000000000000ull +#define HOP1_MASK_4K 0x01FF000000000000ull +#define HOP2_MASK_4K 0x0000FF8000000000ull +#define HOP3_MASK_4K 0x0000007FC0000000ull +#define HOP4_MASK_4K 0x000000003FE00000ull +#define HOP5_MASK_4K 0x00000000001FF000ull + +#define HOP0_MASK_64K 0xFF00000000000000ull +#define HOP1_MASK_64K 0x00FF000000000000ull +#define HOP2_MASK_64K 0x0000FF0000000000ull +#define HOP3_MASK_64K 0x000000FF00000000ull +#define HOP4_MASK_64K 0x00000000FF000000ull +#define HOP5_MASK_64K 0x0000000000FF0000ull + +#define HOP0_SHIFT_4K 57 +#define HOP1_SHIFT_4K 48 +#define HOP2_SHIFT_4K 39 +#define HOP3_SHIFT_4K 30 +#define HOP4_SHIFT_4K 21 +#define HOP5_SHIFT_4K 12 + +#define HOP0_SHIFT_64K 56 +#define HOP1_SHIFT_64K 48 +#define HOP2_SHIFT_64K 40 +#define HOP3_SHIFT_64K 32 +#define HOP4_SHIFT_64K 24 +#define HOP5_SHIFT_64K 16 + +#define DHOP0_MASK HOP0_MASK_4K +#define DHOP1_MASK HOP1_MASK_4K +#define DHOP2_MASK HOP2_MASK_4K +#define DHOP3_MASK HOP3_MASK_4K +#define DHOP4_MASK 0x000003C000000ull + +#define DHOP0_SHIFT HOP0_SHIFT_4K +#define DHOP1_SHIFT HOP1_SHIFT_4K +#define DHOP2_SHIFT HOP2_SHIFT_4K +#define DHOP3_SHIFT HOP3_SHIFT_4K +#define DHOP4_SHIFT 26 + +#endif /* INCLUDE_MMU_V2_0_H_ */ diff --git a/drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h b/drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h new file mode 100644 index 000000000..d232081d4 --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_PCI_GENERAL_H_ +#define INCLUDE_PCI_GENERAL_H_ + +/* PCI CONFIGURATION SPACE */ +#define mmPCI_CONFIG_ELBI_ADDR 0xFF0 +#define mmPCI_CONFIG_ELBI_DATA 0xFF4 +#define mmPCI_CONFIG_ELBI_CTRL 0xFF8 +#define PCI_CONFIG_ELBI_CTRL_WRITE (1 << 31) + +#define mmPCI_CONFIG_ELBI_STS 0xFFC +#define PCI_CONFIG_ELBI_STS_ERR (1 << 30) +#define PCI_CONFIG_ELBI_STS_DONE (1 << 31) +#define PCI_CONFIG_ELBI_STS_MASK (PCI_CONFIG_ELBI_STS_ERR | \ + PCI_CONFIG_ELBI_STS_DONE) + +#endif /* INCLUDE_PCI_GENERAL_H_ */ -- cgit v1.2.3