1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*/
#ifndef __QLA_DEF_H
#define __QLA_DEF_H
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/dmapool.h>
#include <linux/mempool.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/firmware.h>
#include <linux/aer.h>
#include <linux/mutex.h>
#include <linux/btree.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_transport_fc.h>
#include <scsi/scsi_bsg_fc.h>
#include <uapi/scsi/fc/fc_els.h>
#define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \
struct dentry *dfs_##_debugfs_file_name
#define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \
struct dentry *qla_dfs_##_debugfs_file_name
/* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
typedef struct {
uint8_t domain;
uint8_t area;
uint8_t al_pa;
} be_id_t;
/* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
typedef struct {
uint8_t al_pa;
uint8_t area;
uint8_t domain;
} le_id_t;
/*
* 24 bit port ID type definition.
*/
typedef union {
uint32_t b24 : 24;
struct {
#ifdef __BIG_ENDIAN
uint8_t domain;
uint8_t area;
uint8_t al_pa;
#elif defined(__LITTLE_ENDIAN)
uint8_t al_pa;
uint8_t area;
uint8_t domain;
#else
#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
#endif
uint8_t rsvd_1;
} b;
} port_id_t;
#define INVALID_PORT_ID 0xFFFFFF
#include "qla_bsg.h"
#include "qla_dsd.h"
#include "qla_nx.h"
#include "qla_nx2.h"
#include "qla_nvme.h"
#define QLA2XXX_DRIVER_NAME "qla2xxx"
#define QLA2XXX_APIDEV "ql2xapidev"
#define QLA2XXX_MANUFACTURER "Marvell"
/*
* We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
* but that's fine as we don't look at the last 24 ones for
* ISP2100 HBAs.
*/
#define MAILBOX_REGISTER_COUNT_2100 8
#define MAILBOX_REGISTER_COUNT_2200 24
#define MAILBOX_REGISTER_COUNT 32
#define QLA2200A_RISC_ROM_VER 4
#define FPM_2300 6
#define FPM_2310 7
#include "qla_settings.h"
#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
/*
* Data bit definitions
*/
#define BIT_0 0x1
#define BIT_1 0x2
#define BIT_2 0x4
#define BIT_3 0x8
#define BIT_4 0x10
#define BIT_5 0x20
#define BIT_6 0x40
#define BIT_7 0x80
#define BIT_8 0x100
#define BIT_9 0x200
#define BIT_10 0x400
#define BIT_11 0x800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_16 0x10000
#define BIT_17 0x20000
#define BIT_18 0x40000
#define BIT_19 0x80000
#define BIT_20 0x100000
#define BIT_21 0x200000
#define BIT_22 0x400000
#define BIT_23 0x800000
#define BIT_24 0x1000000
#define BIT_25 0x2000000
#define BIT_26 0x4000000
#define BIT_27 0x8000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
#define LSB(x) ((uint8_t)(x))
#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
#define LSW(x) ((uint16_t)(x))
#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
#define LSD(x) ((uint32_t)((uint64_t)(x)))
#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
static inline uint32_t make_handle(uint16_t x, uint16_t y)
{
return ((uint32_t)x << 16) | y;
}
/*
* I/O register
*/
static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
{
return readb(addr);
}
static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
{
return readw(addr);
}
static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
{
return readl(addr);
}
static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
{
return readb_relaxed(addr);
}
static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
{
return readw_relaxed(addr);
}
static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
{
return readl_relaxed(addr);
}
static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
{
return writeb(data, addr);
}
static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
{
return writew(data, addr);
}
static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
{
return writel(data, addr);
}
/*
* ISP83XX specific remote register addresses
*/
#define QLA83XX_LED_PORT0 0x00201320
#define QLA83XX_LED_PORT1 0x00201328
#define QLA83XX_IDC_DEV_STATE 0x22102384
#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
#define QLA83XX_IDC_MINOR_VERSION 0x22102398
#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
#define QLA83XX_IDC_CONTROL 0x22102390
#define QLA83XX_IDC_AUDIT 0x22102394
#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
#define QLA83XX_DRIVER_LOCKID 0x22102104
#define QLA83XX_DRIVER_LOCK 0x8111c028
#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
#define QLA83XX_FLASH_LOCKID 0x22102100
#define QLA83XX_FLASH_LOCK 0x8111c010
#define QLA83XX_FLASH_UNLOCK 0x8111c014
#define QLA83XX_DEV_PARTINFO1 0x221023e0
#define QLA83XX_DEV_PARTINFO2 0x221023e4
#define QLA83XX_FW_HEARTBEAT 0x221020b0
#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
/* 83XX: Macros defining 8200 AEN Reason codes */
#define IDC_DEVICE_STATE_CHANGE BIT_0
#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
#define IDC_HEARTBEAT_FAILURE BIT_3
/* 83XX: Macros defining 8200 AEN Error-levels */
#define ERR_LEVEL_NON_FATAL 0x1
#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
/* 83XX: Macros for IDC Version */
#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
/* 83XX: Macros for scheduling dpc tasks */
#define QLA83XX_NIC_CORE_RESET 0x1
#define QLA83XX_IDC_STATE_HANDLER 0x2
#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
/* 83XX: Macros for defining IDC-Control bits */
#define QLA83XX_IDC_RESET_DISABLED BIT_0
#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
/* 83XX: Macros for different timeouts */
#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
/* 83XX: Macros for defining class in DEV-Partition Info register */
#define QLA83XX_CLASS_TYPE_NONE 0x0
#define QLA83XX_CLASS_TYPE_NIC 0x1
#define QLA83XX_CLASS_TYPE_FCOE 0x2
#define QLA83XX_CLASS_TYPE_ISCSI 0x3
/* 83XX: Macros for IDC Lock-Recovery stages */
#define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
* lock-recovery
*/
#define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
/* 83XX: Macros for IDC Audit type */
#define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
* dev-state change to NEED-RESET
* or NEED-QUIESCENT
*/
#define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
* reset-recovery completion is
* second
*/
/* ISP2031: Values for laser on/off */
#define PORT_0_2031 0x00201340
#define PORT_1_2031 0x00201350
#define LASER_ON_2031 0x01800100
#define LASER_OFF_2031 0x01800180
/*
* The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
* 133Mhz slot.
*/
#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
/*
* Fibre Channel device definitions.
*/
#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
#define MAX_FIBRE_DEVICES_2100 512
#define MAX_FIBRE_DEVICES_2400 2048
#define MAX_FIBRE_DEVICES_LOOP 128
#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
#define MAX_FIBRE_LUNS 0xFFFF
#define MAX_HOST_COUNT 16
/*
* Host adapter default definitions.
*/
#define MAX_BUSES 1 /* We only have one bus today */
#define MIN_LUNS 8
#define MAX_LUNS MAX_FIBRE_LUNS
#define MAX_CMDS_PER_LUN 255
/*
* Fibre Channel device definitions.
*/
#define SNS_LAST_LOOP_ID_2100 0xfe
#define SNS_LAST_LOOP_ID_2300 0x7ff
#define LAST_LOCAL_LOOP_ID 0x7d
#define SNS_FL_PORT 0x7e
#define FABRIC_CONTROLLER 0x7f
#define SIMPLE_NAME_SERVER 0x80
#define SNS_FIRST_LOOP_ID 0x81
#define MANAGEMENT_SERVER 0xfe
#define BROADCAST 0xff
/*
* There is no correspondence between an N-PORT id and an AL_PA. Therefore the
* valid range of an N-PORT id is 0 through 0x7ef.
*/
#define NPH_LAST_HANDLE 0x7ee
#define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
#define NPH_SNS 0x7fc /* FFFFFC */
#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
#define NPH_F_PORT 0x7fe /* FFFFFE */
#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
#include "qla_fw.h"
struct name_list_extended {
struct get_name_list_extended *l;
dma_addr_t ldma;
struct list_head fcports;
u32 size;
u8 sent;
};
struct els_reject {
struct fc_els_ls_rjt *c;
dma_addr_t cdma;
u16 size;
};
/*
* Timeout timer counts in seconds
*/
#define PORT_RETRY_TIME 1
#define LOOP_DOWN_TIMEOUT 60
#define LOOP_DOWN_TIME 255 /* 240 */
#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
#define DEFAULT_OUTSTANDING_COMMANDS 4096
#define MIN_OUTSTANDING_COMMANDS 128
/* ISP request and response entry counts (37-65535) */
#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
#define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
#define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
#define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
#define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
#define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
#define FW_DEF_EXCHANGES_CNT 2048
#define FW_MAX_EXCHANGES_CNT (32 * 1024)
#define REDUCE_EXCHANGES_CNT (8 * 1024)
#define SET_DID_STATUS(stat_var, status) (stat_var = status << 16)
struct req_que;
struct qla_tgt_sess;
/*
* SCSI Request Block
*/
struct srb_cmd {
struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
uint32_t request_sense_length;
uint32_t fw_sense_length;
uint8_t *request_sense_ptr;
struct ct6_dsd *ct6_ctx;
struct crc_context *crc_ctx;
};
/*
* SRB flag definitions
*/
#define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
#define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
#define SRB_WAKEUP_ON_COMP BIT_6
#define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
#define SRB_EDIF_CLEANUP_DELETE BIT_9
/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
#define ISP_REG16_DISCONNECT 0xFFFF
static inline le_id_t be_id_to_le(be_id_t id)
{
le_id_t res;
res.domain = id.domain;
res.area = id.area;
res.al_pa = id.al_pa;
return res;
}
static inline be_id_t le_id_to_be(le_id_t id)
{
be_id_t res;
res.domain = id.domain;
res.area = id.area;
res.al_pa = id.al_pa;
return res;
}
static inline port_id_t be_to_port_id(be_id_t id)
{
port_id_t res;
res.b.domain = id.domain;
res.b.area = id.area;
res.b.al_pa = id.al_pa;
res.b.rsvd_1 = 0;
return res;
}
static inline be_id_t port_id_to_be_id(port_id_t port_id)
{
be_id_t res;
res.domain = port_id.b.domain;
res.area = port_id.b.area;
res.al_pa = port_id.b.al_pa;
return res;
}
struct tmf_arg {
struct list_head tmf_elem;
struct qla_qpair *qpair;
struct fc_port *fcport;
struct scsi_qla_host *vha;
u64 lun;
u32 flags;
uint8_t modifier;
};
struct els_logo_payload {
uint8_t opcode;
uint8_t rsvd[3];
uint8_t s_id[3];
uint8_t rsvd1[1];
uint8_t wwpn[WWN_SIZE];
};
struct els_plogi_payload {
uint8_t opcode;
uint8_t rsvd[3];
__be32 data[112 / 4];
};
struct ct_arg {
void *iocb;
u16 nport_handle;
dma_addr_t req_dma;
dma_addr_t rsp_dma;
u32 req_size;
u32 rsp_size;
u32 req_allocated_size;
u32 rsp_allocated_size;
void *req;
void *rsp;
port_id_t id;
};
/*
* SRB extensions.
*/
struct srb_iocb {
union {
struct {
uint16_t flags;
#define SRB_LOGIN_RETRIED BIT_0
#define SRB_LOGIN_COND_PLOGI BIT_1
#define SRB_LOGIN_SKIP_PRLI BIT_2
#define SRB_LOGIN_NVME_PRLI BIT_3
#define SRB_LOGIN_PRLI_ONLY BIT_4
#define SRB_LOGIN_FCSP BIT_5
uint16_t data[2];
u32 iop[2];
} logio;
struct {
#define ELS_DCMD_TIMEOUT 20
#define ELS_DCMD_LOGO 0x5
uint32_t flags;
uint32_t els_cmd;
struct completion comp;
struct els_logo_payload *els_logo_pyld;
dma_addr_t els_logo_pyld_dma;
} els_logo;
struct els_plogi {
#define ELS_DCMD_PLOGI 0x3
uint32_t flags;
uint32_t els_cmd;
struct completion comp;
struct els_plogi_payload *els_plogi_pyld;
struct els_plogi_payload *els_resp_pyld;
u32 tx_size;
u32 rx_size;
dma_addr_t els_plogi_pyld_dma;
dma_addr_t els_resp_pyld_dma;
__le32 fw_status[3];
__le16 comp_status;
__le16 len;
} els_plogi;
struct {
/*
* Values for flags field below are as
* defined in tsk_mgmt_entry struct
* for control_flags field in qla_fw.h.
*/
uint64_t lun;
uint32_t flags;
uint32_t data;
struct completion comp;
__le16 comp_status;
uint8_t modifier;
uint8_t vp_index;
uint16_t loop_id;
} tmf;
struct {
#define SRB_FXDISC_REQ_DMA_VALID BIT_0
#define SRB_FXDISC_RESP_DMA_VALID BIT_1
#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
#define FXDISC_TIMEOUT 20
uint8_t flags;
uint32_t req_len;
uint32_t rsp_len;
void *req_addr;
void *rsp_addr;
dma_addr_t req_dma_handle;
dma_addr_t rsp_dma_handle;
__le32 adapter_id;
__le32 adapter_id_hi;
__le16 req_func_type;
__le32 req_data;
__le32 req_data_extra;
__le32 result;
__le32 seq_number;
__le16 fw_flags;
struct completion fxiocb_comp;
__le32 reserved_0;
uint8_t reserved_1;
} fxiocb;
struct {
uint32_t cmd_hndl;
__le16 comp_status;
__le16 req_que_no;
struct completion comp;
} abt;
struct ct_arg ctarg;
#define MAX_IOCB_MB_REG 28
#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
struct {
u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
void *out, *in;
dma_addr_t out_dma, in_dma;
struct completion comp;
int rc;
} mbx;
struct {
struct imm_ntfy_from_isp *ntfy;
} nack;
struct {
__le16 comp_status;
__le16 rsp_pyld_len;
uint8_t aen_op;
void *desc;
/* These are only used with ls4 requests */
int cmd_len;
int rsp_len;
dma_addr_t cmd_dma;
dma_addr_t rsp_dma;
enum nvmefc_fcp_datadir dir;
uint32_t dl;
uint32_t timeout_sec;
struct list_head entry;
} nvme;
struct {
u16 cmd;
u16 vp_index;
} ctrlvp;
struct {
struct edif_sa_ctl *sa_ctl;
struct qla_sa_update_frame sa_frame;
} sa_update;
} u;
struct timer_list timer;
void (*timeout)(void *);
};
/* Values for srb_ctx type */
#define SRB_LOGIN_CMD 1
#define SRB_LOGOUT_CMD 2
#define SRB_ELS_CMD_RPT 3
#define SRB_ELS_CMD_HST 4
#define SRB_CT_CMD 5
#define SRB_ADISC_CMD 6
#define SRB_TM_CMD 7
#define SRB_SCSI_CMD 8
#define SRB_BIDI_CMD 9
#define SRB_FXIOCB_DCMD 10
#define SRB_FXIOCB_BCMD 11
#define SRB_ABT_CMD 12
#define SRB_ELS_DCMD 13
#define SRB_MB_IOCB 14
#define SRB_CT_PTHRU_CMD 15
#define SRB_NACK_PLOGI 16
#define SRB_NACK_PRLI 17
#define SRB_NACK_LOGO 18
#define SRB_NVME_CMD 19
#define SRB_NVME_LS 20
#define SRB_PRLI_CMD 21
#define SRB_CTRL_VP 22
#define SRB_PRLO_CMD 23
#define SRB_SA_UPDATE 25
#define SRB_ELS_CMD_HST_NOLOGIN 26
#define SRB_SA_REPLACE 27
#define SRB_MARKER 28
struct qla_els_pt_arg {
u8 els_opcode;
u8 vp_idx;
__le16 nport_handle;
u16 control_flags, ox_id;
__le32 rx_xchg_address;
port_id_t did, sid;
u32 tx_len, tx_byte_count, rx_len, rx_byte_count;
dma_addr_t tx_addr, rx_addr;
};
enum {
TYPE_SRB,
TYPE_TGT_CMD,
TYPE_TGT_TMCMD, /* task management */
};
struct iocb_resource {
u8 res_type;
u8 exch_cnt;
u16 iocb_cnt;
};
struct bsg_cmd {
struct bsg_job *bsg_job;
union {
struct qla_els_pt_arg els_arg;
} u;
};
typedef struct srb {
/*
* Do not move cmd_type field, it needs to
* line up with qla_tgt_cmd->cmd_type
*/
uint8_t cmd_type;
uint8_t pad[3];
struct iocb_resource iores;
struct kref cmd_kref; /* need to migrate ref_count over to this */
void *priv;
struct fc_port *fcport;
struct scsi_qla_host *vha;
unsigned int start_timer:1;
uint32_t handle;
uint16_t flags;
uint16_t type;
const char *name;
int iocbs;
struct qla_qpair *qpair;
struct srb *cmd_sp;
struct list_head elem;
u32 gen1; /* scratch */
u32 gen2; /* scratch */
int rc;
int retry_count;
struct completion *comp;
union {
struct srb_iocb iocb_cmd;
struct bsg_job *bsg_job;
struct srb_cmd scmd;
struct bsg_cmd bsg_cmd;
} u;
struct {
bool remapped;
struct {
dma_addr_t dma;
void *buf;
uint len;
} req;
struct {
dma_addr_t dma;
void *buf;
uint len;
} rsp;
} remap;
/*
* Report completion status @res and call sp_put(@sp). @res is
* an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
* QLA_* status value.
*/
void (*done)(struct srb *sp, int res);
/* Stop the timer and free @sp. Only used by the FCP code. */
void (*free)(struct srb *sp);
/*
* Call nvme_private->fd->done() and free @sp. Only used by the NVMe
* code.
*/
void (*put_fn)(struct kref *kref);
/*
* Report completion for asynchronous commands.
*/
void (*async_done)(struct srb *sp, int res);
} srb_t;
#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
#define GET_CMD_SENSE_LEN(sp) \
(sp->u.scmd.request_sense_length)
#define SET_CMD_SENSE_LEN(sp, len) \
(sp->u.scmd.request_sense_length = len)
#define GET_CMD_SENSE_PTR(sp) \
(sp->u.scmd.request_sense_ptr)
#define SET_CMD_SENSE_PTR(sp, ptr) \
(sp->u.scmd.request_sense_ptr = ptr)
#define GET_FW_SENSE_LEN(sp) \
(sp->u.scmd.fw_sense_length)
#define SET_FW_SENSE_LEN(sp, len) \
(sp->u.scmd.fw_sense_length = len)
struct msg_echo_lb {
dma_addr_t send_dma;
dma_addr_t rcv_dma;
uint16_t req_sg_cnt;
uint16_t rsp_sg_cnt;
uint16_t options;
uint32_t transfer_size;
uint32_t iteration_count;
};
/*
* ISP I/O Register Set structure definitions.
*/
struct device_reg_2xxx {
__le16 flash_address; /* Flash BIOS address */
__le16 flash_data; /* Flash BIOS data */
__le16 unused_1[1]; /* Gap */
__le16 ctrl_status; /* Control/Status */
#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
__le16 ictrl; /* Interrupt control */
#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
__le16 istatus; /* Interrupt status */
#define ISR_RISC_INT BIT_3 /* RISC interrupt */
__le16 semaphore; /* Semaphore */
__le16 nvram; /* NVRAM register. */
#define NVR_DESELECT 0
#define NVR_BUSY BIT_15
#define NVR_WRT_ENABLE BIT_14 /* Write enable */
#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
#define NVR_DATA_IN BIT_3
#define NVR_DATA_OUT BIT_2
#define NVR_SELECT BIT_1
#define NVR_CLOCK BIT_0
#define NVR_WAIT_CNT 20000
union {
struct {
__le16 mailbox0;
__le16 mailbox1;
__le16 mailbox2;
__le16 mailbox3;
__le16 mailbox4;
__le16 mailbox5;
__le16 mailbox6;
__le16 mailbox7;
__le16 unused_2[59]; /* Gap */
} __attribute__((packed)) isp2100;
struct {
/* Request Queue */
__le16 req_q_in; /* In-Pointer */
__le16 req_q_out; /* Out-Pointer */
/* Response Queue */
__le16 rsp_q_in; /* In-Pointer */
__le16 rsp_q_out; /* Out-Pointer */
/* RISC to Host Status */
__le32 host_status;
#define HSR_RISC_INT BIT_15 /* RISC interrupt */
#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
/* Host to Host Semaphore */
__le16 host_semaphore;
__le16 unused_3[17]; /* Gap */
__le16 mailbox0;
__le16 mailbox1;
__le16 mailbox2;
__le16 mailbox3;
__le16 mailbox4;
__le16 mailbox5;
__le16 mailbox6;
__le16 mailbox7;
__le16 mailbox8;
__le16 mailbox9;
__le16 mailbox10;
__le16 mailbox11;
__le16 mailbox12;
__le16 mailbox13;
__le16 mailbox14;
__le16 mailbox15;
__le16 mailbox16;
__le16 mailbox17;
__le16 mailbox18;
__le16 mailbox19;
__le16 mailbox20;
__le16 mailbox21;
__le16 mailbox22;
__le16 mailbox23;
__le16 mailbox24;
__le16 mailbox25;
__le16 mailbox26;
__le16 mailbox27;
__le16 mailbox28;
__le16 mailbox29;
__le16 mailbox30;
__le16 mailbox31;
__le16 fb_cmd;
__le16 unused_4[10]; /* Gap */
} __attribute__((packed)) isp2300;
} u;
__le16 fpm_diag_config;
__le16 unused_5[0x4]; /* Gap */
__le16 risc_hw;
__le16 unused_5_1; /* Gap */
__le16 pcr; /* Processor Control Register. */
__le16 unused_6[0x5]; /* Gap */
__le16 mctr; /* Memory Configuration and Timing. */
__le16 unused_7[0x3]; /* Gap */
__le16 fb_cmd_2100; /* Unused on 23XX */
__le16 unused_8[0x3]; /* Gap */
__le16 hccr; /* Host command & control register. */
#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
/* HCCR commands */
#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
__le16 unused_9[5]; /* Gap */
__le16 gpiod; /* GPIO Data register. */
__le16 gpioe; /* GPIO Enable register. */
#define GPIO_LED_MASK 0x00C0
#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
#define GPIO_LED_ALL_OFF 0x0000
#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
union {
struct {
__le16 unused_10[8]; /* Gap */
__le16 mailbox8;
__le16 mailbox9;
__le16 mailbox10;
__le16 mailbox11;
__le16 mailbox12;
__le16 mailbox13;
__le16 mailbox14;
__le16 mailbox15;
__le16 mailbox16;
__le16 mailbox17;
__le16 mailbox18;
__le16 mailbox19;
__le16 mailbox20;
__le16 mailbox21;
__le16 mailbox22;
__le16 mailbox23; /* Also probe reg. */
} __attribute__((packed)) isp2200;
} u_end;
};
struct device_reg_25xxmq {
__le32 req_q_in;
__le32 req_q_out;
__le32 rsp_q_in;
__le32 rsp_q_out;
__le32 atio_q_in;
__le32 atio_q_out;
};
struct device_reg_fx00 {
__le32 mailbox0; /* 00 */
__le32 mailbox1; /* 04 */
__le32 mailbox2; /* 08 */
__le32 mailbox3; /* 0C */
__le32 mailbox4; /* 10 */
__le32 mailbox5; /* 14 */
__le32 mailbox6; /* 18 */
__le32 mailbox7; /* 1C */
__le32 mailbox8; /* 20 */
__le32 mailbox9; /* 24 */
__le32 mailbox10; /* 28 */
__le32 mailbox11;
__le32 mailbox12;
__le32 mailbox13;
__le32 mailbox14;
__le32 mailbox15;
__le32 mailbox16;
__le32 mailbox17;
__le32 mailbox18;
__le32 mailbox19;
__le32 mailbox20;
__le32 mailbox21;
__le32 mailbox22;
__le32 mailbox23;
__le32 mailbox24;
__le32 mailbox25;
__le32 mailbox26;
__le32 mailbox27;
__le32 mailbox28;
__le32 mailbox29;
__le32 mailbox30;
__le32 mailbox31;
__le32 aenmailbox0;
__le32 aenmailbox1;
__le32 aenmailbox2;
__le32 aenmailbox3;
__le32 aenmailbox4;
__le32 aenmailbox5;
__le32 aenmailbox6;
__le32 aenmailbox7;
/* Request Queue. */
__le32 req_q_in; /* A0 - Request Queue In-Pointer */
__le32 req_q_out; /* A4 - Request Queue Out-Pointer */
/* Response Queue. */
__le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
__le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
/* Init values shadowed on FW Up Event */
__le32 initval0; /* B0 */
__le32 initval1; /* B4 */
__le32 initval2; /* B8 */
__le32 initval3; /* BC */
__le32 initval4; /* C0 */
__le32 initval5; /* C4 */
__le32 initval6; /* C8 */
__le32 initval7; /* CC */
__le32 fwheartbeat; /* D0 */
__le32 pseudoaen; /* D4 */
};
typedef union {
struct device_reg_2xxx isp;
struct device_reg_24xx isp24;
struct device_reg_25xxmq isp25mq;
struct device_reg_82xx isp82;
struct device_reg_fx00 ispfx00;
} __iomem device_reg_t;
#define ISP_REQ_Q_IN(ha, reg) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
&(reg)->u.isp2100.mailbox4 : \
&(reg)->u.isp2300.req_q_in)
#define ISP_REQ_Q_OUT(ha, reg) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
&(reg)->u.isp2100.mailbox4 : \
&(reg)->u.isp2300.req_q_out)
#define ISP_RSP_Q_IN(ha, reg) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
&(reg)->u.isp2100.mailbox5 : \
&(reg)->u.isp2300.rsp_q_in)
#define ISP_RSP_Q_OUT(ha, reg) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
&(reg)->u.isp2100.mailbox5 : \
&(reg)->u.isp2300.rsp_q_out)
#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
#define MAILBOX_REG(ha, reg, num) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
(num < 8 ? \
&(reg)->u.isp2100.mailbox0 + (num) : \
&(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
&(reg)->u.isp2300.mailbox0 + (num))
#define RD_MAILBOX_REG(ha, reg, num) \
rd_reg_word(MAILBOX_REG(ha, reg, num))
#define WRT_MAILBOX_REG(ha, reg, num, data) \
wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
#define FB_CMD_REG(ha, reg) \
(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
&(reg)->fb_cmd_2100 : \
&(reg)->u.isp2300.fb_cmd)
#define RD_FB_CMD_REG(ha, reg) \
rd_reg_word(FB_CMD_REG(ha, reg))
#define WRT_FB_CMD_REG(ha, reg, data) \
wrt_reg_word(FB_CMD_REG(ha, reg), data)
typedef struct {
uint32_t out_mb; /* outbound from driver */
uint32_t in_mb; /* Incoming from RISC */
uint16_t mb[MAILBOX_REGISTER_COUNT];
long buf_size;
void *bufp;
uint32_t tov;
uint8_t flags;
#define MBX_DMA_IN BIT_0
#define MBX_DMA_OUT BIT_1
#define IOCTL_CMD BIT_2
} mbx_cmd_t;
struct mbx_cmd_32 {
uint32_t out_mb; /* outbound from driver */
uint32_t in_mb; /* Incoming from RISC */
uint32_t mb[MAILBOX_REGISTER_COUNT];
long buf_size;
void *bufp;
uint32_t tov;
uint8_t flags;
#define MBX_DMA_IN BIT_0
#define MBX_DMA_OUT BIT_1
#define IOCTL_CMD BIT_2
};
#define MBX_TOV_SECONDS 30
/*
* ISP product identification definitions in mailboxes after reset.
*/
#define PROD_ID_1 0x4953
#define PROD_ID_2 0x0000
#define PROD_ID_2a 0x5020
#define PROD_ID_3 0x2020
/*
* ISP mailbox Self-Test status codes
*/
#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
#define MBS_BUSY 4 /* Busy. */
/*
* ISP mailbox command complete status codes
*/
#define MBS_COMMAND_COMPLETE 0x4000
#define MBS_INVALID_COMMAND 0x4001
#define MBS_HOST_INTERFACE_ERROR 0x4002
#define MBS_TEST_FAILED 0x4003
#define MBS_COMMAND_ERROR 0x4005
#define MBS_COMMAND_PARAMETER_ERROR 0x4006
#define MBS_PORT_ID_USED 0x4007
#define MBS_LOOP_ID_USED 0x4008
#define MBS_ALL_IDS_IN_USE 0x4009
#define MBS_NOT_LOGGED_IN 0x400A
#define MBS_LINK_DOWN_ERROR 0x400B
#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
{
return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
}
/*
* ISP mailbox asynchronous event status codes
*/
#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
#define MBA_RESET 0x8001 /* Reset Detected. */
#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
/* occurred. */
#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
#define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
/* used. */
#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
#define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
#define MBA_FW_STARTING 0x8051 /* Firmware starting */
#define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
#define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
#define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
#define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
#define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
#define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
#define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
#define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
#define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
Notification */
#define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
#define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
#define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
/* 83XX FCoE specific */
#define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
/* Interrupt type codes */
#define INTR_ROM_MB_SUCCESS 0x1
#define INTR_ROM_MB_FAILED 0x2
#define INTR_MB_SUCCESS 0x10
#define INTR_MB_FAILED 0x11
#define INTR_ASYNC_EVENT 0x12
#define INTR_RSP_QUE_UPDATE 0x13
#define INTR_RSP_QUE_UPDATE_83XX 0x14
#define INTR_ATIO_QUE_UPDATE 0x1C
#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
/* ISP mailbox loopback echo diagnostic error code */
#define MBS_LB_RESET 0x17
/* AEN mailbox Port Diagnostics test */
#define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */
#define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */
#define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/
/*
* Firmware options 1, 2, 3.
*/
#define FO1_AE_ON_LIPF8 BIT_0
#define FO1_AE_ALL_LIP_RESET BIT_1
#define FO1_CTIO_RETRY BIT_3
#define FO1_DISABLE_LIP_F7_SW BIT_4
#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
#define FO1_SET_EMPHASIS_SWING BIT_8
#define FO1_AE_AUTO_BYPASS BIT_9
#define FO1_ENABLE_PURE_IOCB BIT_10
#define FO1_AE_PLOGI_RJT BIT_11
#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
#define FO1_AE_QUEUE_FULL BIT_13
#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
#define FO2_REV_LOOPBACK BIT_1
#define FO3_ENABLE_EMERG_IOCB BIT_0
#define FO3_AE_RND_ERROR BIT_1
/* 24XX additional firmware options */
#define ADD_FO_COUNT 3
#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
/*
* ISP mailbox commands
*/
#define MBC_LOAD_RAM 1 /* Load RAM. */
#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
#define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
#define MBC_RESET 0x18 /* Reset. */
#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
#define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
#define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
#define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
#define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
#define MBC_DATA_RATE 0x5d /* Data Rate */
#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
/* Initialization Procedure */
#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
#define MBC_TARGET_RESET 0x66 /* Target Reset. */
#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
#define MBC_LIP_RESET 0x6c /* LIP reset. */
#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
/* commandd. */
#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
#define MBC_LUN_RESET 0x7E /* Send LUN reset */
/*
* all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
* should be defined with MBC_MR_*
*/
#define MBC_MR_DRV_SHUTDOWN 0x6A
/*
* ISP24xx mailbox commands
*/
#define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
#define MBC_READ_SERDES 0x4 /* Read serdes word. */
#define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
#define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
#define MBC_READ_SFP 0x31 /* Read SFP Data. */
#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
#define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
#define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
#define MBC_PORT_RESET 0x120 /* Port Reset */
#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
/*
* ISP81xx mailbox commands
*/
#define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
/*
* ISP8044 mailbox commands
*/
#define MBC_SET_GET_ETH_SERDES_REG 0x150
#define HCS_WRITE_SERDES 0x3
#define HCS_READ_SERDES 0x4
/* Firmware return data sizes */
#define FCAL_MAP_SIZE 128
/* Mailbox bit definitions for out_mb and in_mb */
#define MBX_31 BIT_31
#define MBX_30 BIT_30
#define MBX_29 BIT_29
#define MBX_28 BIT_28
#define MBX_27 BIT_27
#define MBX_26 BIT_26
#define MBX_25 BIT_25
#define MBX_24 BIT_24
#define MBX_23 BIT_23
#define MBX_22 BIT_22
#define MBX_21 BIT_21
#define MBX_20 BIT_20
#define MBX_19 BIT_19
#define MBX_18 BIT_18
#define MBX_17 BIT_17
#define MBX_16 BIT_16
#define MBX_15 BIT_15
#define MBX_14 BIT_14
#define MBX_13 BIT_13
#define MBX_12 BIT_12
#define MBX_11 BIT_11
#define MBX_10 BIT_10
#define MBX_9 BIT_9
#define MBX_8 BIT_8
#define MBX_7 BIT_7
#define MBX_6 BIT_6
#define MBX_5 BIT_5
#define MBX_4 BIT_4
#define MBX_3 BIT_3
#define MBX_2 BIT_2
#define MBX_1 BIT_1
#define MBX_0 BIT_0
#define RNID_TYPE_ELS_CMD 0x5
#define RNID_TYPE_PORT_LOGIN 0x7
#define RNID_BUFFER_CREDITS 0x8
#define RNID_TYPE_SET_VERSION 0x9
#define RNID_TYPE_ASIC_TEMP 0xC
#define ELS_CMD_MAP_SIZE 32
/*
* Firmware state codes from get firmware state mailbox command
*/
#define FSTATE_CONFIG_WAIT 0
#define FSTATE_WAIT_AL_PA 1
#define FSTATE_WAIT_LOGIN 2
#define FSTATE_READY 3
#define FSTATE_LOSS_OF_SYNC 4
#define FSTATE_ERROR 5
#define FSTATE_REINIT 6
#define FSTATE_NON_PART 7
#define FSTATE_CONFIG_CORRECT 0
#define FSTATE_P2P_RCV_LIP 1
#define FSTATE_P2P_CHOOSE_LOOP 2
#define FSTATE_P2P_RCV_UNIDEN_LIP 3
#define FSTATE_FATAL_ERROR 4
#define FSTATE_LOOP_BACK_CONN 5
#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
#define QLA27XX_DEFAULT_IMAGE 0
#define QLA27XX_PRIMARY_IMAGE 1
#define QLA27XX_SECONDARY_IMAGE 2
/*
* Port Database structure definition
* Little endian except where noted.
*/
#define PORT_DATABASE_SIZE 128 /* bytes */
typedef struct {
uint8_t options;
uint8_t control;
uint8_t master_state;
uint8_t slave_state;
uint8_t reserved[2];
uint8_t hard_address;
uint8_t reserved_1;
uint8_t port_id[4];
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
__le16 execution_throttle;
uint16_t execution_count;
uint8_t reset_count;
uint8_t reserved_2;
uint16_t resource_allocation;
uint16_t current_allocation;
uint16_t queue_head;
uint16_t queue_tail;
uint16_t transmit_execution_list_next;
uint16_t transmit_execution_list_previous;
uint16_t common_features;
uint16_t total_concurrent_sequences;
uint16_t RO_by_information_category;
uint8_t recipient;
uint8_t initiator;
uint16_t receive_data_size;
uint16_t concurrent_sequences;
uint16_t open_sequences_per_exchange;
uint16_t lun_abort_flags;
uint16_t lun_stop_flags;
uint16_t stop_queue_head;
uint16_t stop_queue_tail;
uint16_t port_retry_timer;
uint16_t next_sequence_id;
uint16_t frame_count;
uint16_t PRLI_payload_length;
uint8_t prli_svc_param_word_0[2]; /* Big endian */
/* Bits 15-0 of word 0 */
uint8_t prli_svc_param_word_3[2]; /* Big endian */
/* Bits 15-0 of word 3 */
uint16_t loop_id;
uint16_t extended_lun_info_list_pointer;
uint16_t extended_lun_stop_list_pointer;
} port_database_t;
/*
* Port database slave/master states
*/
#define PD_STATE_DISCOVERY 0
#define PD_STATE_WAIT_DISCOVERY_ACK 1
#define PD_STATE_PORT_LOGIN 2
#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
#define PD_STATE_PROCESS_LOGIN 4
#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
#define PD_STATE_PORT_LOGGED_IN 6
#define PD_STATE_PORT_UNAVAILABLE 7
#define PD_STATE_PROCESS_LOGOUT 8
#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
#define PD_STATE_PORT_LOGOUT 10
#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
#define QLA_ZIO_DISABLED 0
#define QLA_ZIO_DEFAULT_TIMER 2
/*
* ISP Initialization Control Block.
* Little endian except where noted.
*/
#define ICB_VERSION 1
typedef struct {
uint8_t version;
uint8_t reserved_1;
/*
* LSB BIT 0 = Enable Hard Loop Id
* LSB BIT 1 = Enable Fairness
* LSB BIT 2 = Enable Full-Duplex
* LSB BIT 3 = Enable Fast Posting
* LSB BIT 4 = Enable Target Mode
* LSB BIT 5 = Disable Initiator Mode
* LSB BIT 6 = Enable ADISC
* LSB BIT 7 = Enable Target Inquiry Data
*
* MSB BIT 0 = Enable PDBC Notify
* MSB BIT 1 = Non Participating LIP
* MSB BIT 2 = Descending Loop ID Search
* MSB BIT 3 = Acquire Loop ID in LIPA
* MSB BIT 4 = Stop PortQ on Full Status
* MSB BIT 5 = Full Login after LIP
* MSB BIT 6 = Node Name Option
* MSB BIT 7 = Ext IFWCB enable bit
*/
uint8_t firmware_options[2];
__le16 frame_payload_size;
__le16 max_iocb_allocation;
__le16 execution_throttle;
uint8_t retry_count;
uint8_t retry_delay; /* unused */
uint8_t port_name[WWN_SIZE]; /* Big endian. */
uint16_t hard_address;
uint8_t inquiry_data;
uint8_t login_timeout;
uint8_t node_name[WWN_SIZE]; /* Big endian. */
__le16 request_q_outpointer;
__le16 response_q_inpointer;
__le16 request_q_length;
__le16 response_q_length;
__le64 request_q_address __packed;
__le64 response_q_address __packed;
__le16 lun_enables;
uint8_t command_resource_count;
uint8_t immediate_notify_resource_count;
__le16 timeout;
uint8_t reserved_2[2];
/*
* LSB BIT 0 = Timer Operation mode bit 0
* LSB BIT 1 = Timer Operation mode bit 1
* LSB BIT 2 = Timer Operation mode bit 2
* LSB BIT 3 = Timer Operation mode bit 3
* LSB BIT 4 = Init Config Mode bit 0
* LSB BIT 5 = Init Config Mode bit 1
* LSB BIT 6 = Init Config Mode bit 2
* LSB BIT 7 = Enable Non part on LIHA failure
*
* MSB BIT 0 = Enable class 2
* MSB BIT 1 = Enable ACK0
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 = FC Tape Enable
* MSB BIT 5 = Enable FC Confirm
* MSB BIT 6 = Enable command queuing in target mode
* MSB BIT 7 = No Logo On Link Down
*/
uint8_t add_firmware_options[2];
uint8_t response_accumulation_timer;
uint8_t interrupt_delay_timer;
/*
* LSB BIT 0 = Enable Read xfr_rdy
* LSB BIT 1 = Soft ID only
* LSB BIT 2 =
* LSB BIT 3 =
* LSB BIT 4 = FCP RSP Payload [0]
* LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
* LSB BIT 6 = Enable Out-of-Order frame handling
* LSB BIT 7 = Disable Automatic PLOGI on Local Loop
*
* MSB BIT 0 = Sbus enable - 2300
* MSB BIT 1 =
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 = LED mode
* MSB BIT 5 = enable 50 ohm termination
* MSB BIT 6 = Data Rate (2300 only)
* MSB BIT 7 = Data Rate (2300 only)
*/
uint8_t special_options[2];
uint8_t reserved_3[26];
} init_cb_t;
/* Special Features Control Block */
struct init_sf_cb {
uint8_t format;
uint8_t reserved0;
/*
* BIT 15-14 = Reserved
* BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
* BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
* BIT 11-0 = Reserved
*/
__le16 flags;
uint8_t reserved1[32];
uint16_t discard_OHRB_timeout_value;
uint16_t remote_write_opt_queue_num;
uint8_t reserved2[40];
uint8_t scm_related_parameter[16];
uint8_t reserved3[32];
};
/*
* Get Link Status mailbox command return buffer.
*/
#define GLSO_SEND_RPS BIT_0
#define GLSO_USE_DID BIT_3
struct link_statistics {
__le32 link_fail_cnt;
__le32 loss_sync_cnt;
__le32 loss_sig_cnt;
__le32 prim_seq_err_cnt;
__le32 inval_xmit_word_cnt;
__le32 inval_crc_cnt;
__le32 lip_cnt;
__le32 link_up_cnt;
__le32 link_down_loop_init_tmo;
__le32 link_down_los;
__le32 link_down_loss_rcv_clk;
uint32_t reserved0[5];
__le32 port_cfg_chg;
uint32_t reserved1[11];
__le32 rsp_q_full;
__le32 atio_q_full;
__le32 drop_ae;
__le32 els_proto_err;
__le32 reserved2;
__le32 tx_frames;
__le32 rx_frames;
__le32 discarded_frames;
__le32 dropped_frames;
uint32_t reserved3;
__le32 nos_rcvd;
uint32_t reserved4[4];
__le32 tx_prjt;
__le32 rcv_exfail;
__le32 rcv_abts;
__le32 seq_frm_miss;
__le32 corr_err;
__le32 mb_rqst;
__le32 nport_full;
__le32 eofa;
uint32_t reserved5;
__le64 fpm_recv_word_cnt;
__le64 fpm_disc_word_cnt;
__le64 fpm_xmit_word_cnt;
uint32_t reserved6[70];
};
/*
* NVRAM Command values.
*/
#define NV_START_BIT BIT_2
#define NV_WRITE_OP (BIT_26+BIT_24)
#define NV_READ_OP (BIT_26+BIT_25)
#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
#define NV_DELAY_COUNT 10
/*
* QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
*/
typedef struct {
/*
* NVRAM header
*/
uint8_t id[4];
uint8_t nvram_version;
uint8_t reserved_0;
/*
* NVRAM RISC parameter block
*/
uint8_t parameter_block_version;
uint8_t reserved_1;
/*
* LSB BIT 0 = Enable Hard Loop Id
* LSB BIT 1 = Enable Fairness
* LSB BIT 2 = Enable Full-Duplex
* LSB BIT 3 = Enable Fast Posting
* LSB BIT 4 = Enable Target Mode
* LSB BIT 5 = Disable Initiator Mode
* LSB BIT 6 = Enable ADISC
* LSB BIT 7 = Enable Target Inquiry Data
*
* MSB BIT 0 = Enable PDBC Notify
* MSB BIT 1 = Non Participating LIP
* MSB BIT 2 = Descending Loop ID Search
* MSB BIT 3 = Acquire Loop ID in LIPA
* MSB BIT 4 = Stop PortQ on Full Status
* MSB BIT 5 = Full Login after LIP
* MSB BIT 6 = Node Name Option
* MSB BIT 7 = Ext IFWCB enable bit
*/
uint8_t firmware_options[2];
__le16 frame_payload_size;
__le16 max_iocb_allocation;
__le16 execution_throttle;
uint8_t retry_count;
uint8_t retry_delay; /* unused */
uint8_t port_name[WWN_SIZE]; /* Big endian. */
uint16_t hard_address;
uint8_t inquiry_data;
uint8_t login_timeout;
uint8_t node_name[WWN_SIZE]; /* Big endian. */
/*
* LSB BIT 0 = Timer Operation mode bit 0
* LSB BIT 1 = Timer Operation mode bit 1
* LSB BIT 2 = Timer Operation mode bit 2
* LSB BIT 3 = Timer Operation mode bit 3
* LSB BIT 4 = Init Config Mode bit 0
* LSB BIT 5 = Init Config Mode bit 1
* LSB BIT 6 = Init Config Mode bit 2
* LSB BIT 7 = Enable Non part on LIHA failure
*
* MSB BIT 0 = Enable class 2
* MSB BIT 1 = Enable ACK0
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 = FC Tape Enable
* MSB BIT 5 = Enable FC Confirm
* MSB BIT 6 = Enable command queuing in target mode
* MSB BIT 7 = No Logo On Link Down
*/
uint8_t add_firmware_options[2];
uint8_t response_accumulation_timer;
uint8_t interrupt_delay_timer;
/*
* LSB BIT 0 = Enable Read xfr_rdy
* LSB BIT 1 = Soft ID only
* LSB BIT 2 =
* LSB BIT 3 =
* LSB BIT 4 = FCP RSP Payload [0]
* LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
* LSB BIT 6 = Enable Out-of-Order frame handling
* LSB BIT 7 = Disable Automatic PLOGI on Local Loop
*
* MSB BIT 0 = Sbus enable - 2300
* MSB BIT 1 =
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 = LED mode
* MSB BIT 5 = enable 50 ohm termination
* MSB BIT 6 = Data Rate (2300 only)
* MSB BIT 7 = Data Rate (2300 only)
*/
uint8_t special_options[2];
/* Reserved for expanded RISC parameter block */
uint8_t reserved_2[22];
/*
* LSB BIT 0 = Tx Sensitivity 1G bit 0
* LSB BIT 1 = Tx Sensitivity 1G bit 1
* LSB BIT 2 = Tx Sensitivity 1G bit 2
* LSB BIT 3 = Tx Sensitivity 1G bit 3
* LSB BIT 4 = Rx Sensitivity 1G bit 0
* LSB BIT 5 = Rx Sensitivity 1G bit 1
* LSB BIT 6 = Rx Sensitivity 1G bit 2
* LSB BIT 7 = Rx Sensitivity 1G bit 3
*
* MSB BIT 0 = Tx Sensitivity 2G bit 0
* MSB BIT 1 = Tx Sensitivity 2G bit 1
* MSB BIT 2 = Tx Sensitivity 2G bit 2
* MSB BIT 3 = Tx Sensitivity 2G bit 3
* MSB BIT 4 = Rx Sensitivity 2G bit 0
* MSB BIT 5 = Rx Sensitivity 2G bit 1
* MSB BIT 6 = Rx Sensitivity 2G bit 2
* MSB BIT 7 = Rx Sensitivity 2G bit 3
*
* LSB BIT 0 = Output Swing 1G bit 0
* LSB BIT 1 = Output Swing 1G bit 1
* LSB BIT 2 = Output Swing 1G bit 2
* LSB BIT 3 = Output Emphasis 1G bit 0
* LSB BIT 4 = Output Emphasis 1G bit 1
* LSB BIT 5 = Output Swing 2G bit 0
* LSB BIT 6 = Output Swing 2G bit 1
* LSB BIT 7 = Output Swing 2G bit 2
*
* MSB BIT 0 = Output Emphasis 2G bit 0
* MSB BIT 1 = Output Emphasis 2G bit 1
* MSB BIT 2 = Output Enable
* MSB BIT 3 =
* MSB BIT 4 =
* MSB BIT 5 =
* MSB BIT 6 =
* MSB BIT 7 =
*/
uint8_t seriallink_options[4];
/*
* NVRAM host parameter block
*
* LSB BIT 0 = Enable spinup delay
* LSB BIT 1 = Disable BIOS
* LSB BIT 2 = Enable Memory Map BIOS
* LSB BIT 3 = Enable Selectable Boot
* LSB BIT 4 = Disable RISC code load
* LSB BIT 5 = Set cache line size 1
* LSB BIT 6 = PCI Parity Disable
* LSB BIT 7 = Enable extended logging
*
* MSB BIT 0 = Enable 64bit addressing
* MSB BIT 1 = Enable lip reset
* MSB BIT 2 = Enable lip full login
* MSB BIT 3 = Enable target reset
* MSB BIT 4 = Enable database storage
* MSB BIT 5 = Enable cache flush read
* MSB BIT 6 = Enable database load
* MSB BIT 7 = Enable alternate WWN
*/
uint8_t host_p[2];
uint8_t boot_node_name[WWN_SIZE];
uint8_t boot_lun_number;
uint8_t reset_delay;
uint8_t port_down_retry_count;
uint8_t boot_id_number;
__le16 max_luns_per_target;
uint8_t fcode_boot_port_name[WWN_SIZE];
uint8_t alternate_port_name[WWN_SIZE];
uint8_t alternate_node_name[WWN_SIZE];
/*
* BIT 0 = Selective Login
* BIT 1 = Alt-Boot Enable
* BIT 2 =
* BIT 3 = Boot Order List
* BIT 4 =
* BIT 5 = Selective LUN
* BIT 6 =
* BIT 7 = unused
*/
uint8_t efi_parameters;
uint8_t link_down_timeout;
uint8_t adapter_id[16];
uint8_t alt1_boot_node_name[WWN_SIZE];
uint16_t alt1_boot_lun_number;
uint8_t alt2_boot_node_name[WWN_SIZE];
uint16_t alt2_boot_lun_number;
uint8_t alt3_boot_node_name[WWN_SIZE];
uint16_t alt3_boot_lun_number;
uint8_t alt4_boot_node_name[WWN_SIZE];
uint16_t alt4_boot_lun_number;
uint8_t alt5_boot_node_name[WWN_SIZE];
uint16_t alt5_boot_lun_number;
uint8_t alt6_boot_node_name[WWN_SIZE];
uint16_t alt6_boot_lun_number;
uint8_t alt7_boot_node_name[WWN_SIZE];
uint16_t alt7_boot_lun_number;
uint8_t reserved_3[2];
/* Offset 200-215 : Model Number */
uint8_t model_number[16];
/* OEM related items */
uint8_t oem_specific[16];
/*
* NVRAM Adapter Features offset 232-239
*
* LSB BIT 0 = External GBIC
* LSB BIT 1 = Risc RAM parity
* LSB BIT 2 = Buffer Plus Module
* LSB BIT 3 = Multi Chip Adapter
* LSB BIT 4 = Internal connector
* LSB BIT 5 =
* LSB BIT 6 =
* LSB BIT 7 =
*
* MSB BIT 0 =
* MSB BIT 1 =
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 =
* MSB BIT 5 =
* MSB BIT 6 =
* MSB BIT 7 =
*/
uint8_t adapter_features[2];
uint8_t reserved_4[16];
/* Subsystem vendor ID for ISP2200 */
uint16_t subsystem_vendor_id_2200;
/* Subsystem device ID for ISP2200 */
uint16_t subsystem_device_id_2200;
uint8_t reserved_5;
uint8_t checksum;
} nvram_t;
/*
* ISP queue - response queue entry definition.
*/
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System defined handle */
uint8_t data[52];
uint32_t signature;
#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
} response_t;
/*
* ISP queue - ATIO queue entry definition.
*/
struct atio {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
__le16 attr_n_length;
uint8_t data[56];
uint32_t signature;
#define ATIO_PROCESSED 0xDEADDEAD /* Signature */
};
typedef union {
__le16 extended;
struct {
uint8_t reserved;
uint8_t standard;
} id;
} target_id_t;
#define SET_TARGET_ID(ha, to, from) \
do { \
if (HAS_EXTENDED_IDS(ha)) \
to.extended = cpu_to_le16(from); \
else \
to.id.standard = (uint8_t)from; \
} while (0)
/*
* ISP queue - command entry structure definition.
*/
#define COMMAND_TYPE 0x11 /* Command entry */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
target_id_t target; /* SCSI ID */
__le16 lun; /* SCSI LUN */
__le16 control_flags; /* Control flags. */
#define CF_WRITE BIT_6
#define CF_READ BIT_5
#define CF_SIMPLE_TAG BIT_3
#define CF_ORDERED_TAG BIT_2
#define CF_HEAD_TAG BIT_1
uint16_t reserved_1;
__le16 timeout; /* Command timeout. */
__le16 dseg_count; /* Data segment count. */
uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
__le32 byte_count; /* Total byte count. */
union {
struct dsd32 dsd32[3];
struct dsd64 dsd64[2];
};
} cmd_entry_t;
/*
* ISP queue - 64-Bit addressing, command entry structure definition.
*/
#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
target_id_t target; /* SCSI ID */
__le16 lun; /* SCSI LUN */
__le16 control_flags; /* Control flags. */
uint16_t reserved_1;
__le16 timeout; /* Command timeout. */
__le16 dseg_count; /* Data segment count. */
uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
uint32_t byte_count; /* Total byte count. */
struct dsd64 dsd[2];
} cmd_a64_entry_t, request_t;
/*
* ISP queue - continuation entry structure definition.
*/
#define CONTINUE_TYPE 0x02 /* Continuation entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t reserved;
struct dsd32 dsd[7];
} cont_entry_t;
/*
* ISP queue - 64-Bit addressing, continuation entry structure definition.
*/
#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
struct dsd64 dsd[5];
} cont_a64_entry_t;
#define PO_MODE_DIF_INSERT 0
#define PO_MODE_DIF_REMOVE 1
#define PO_MODE_DIF_PASS 2
#define PO_MODE_DIF_REPLACE 3
#define PO_MODE_DIF_TCP_CKSUM 6
#define PO_ENABLE_INCR_GUARD_SEED BIT_3
#define PO_DISABLE_GUARD_CHECK BIT_4
#define PO_DISABLE_INCR_REF_TAG BIT_5
#define PO_DIS_HEADER_MODE BIT_7
#define PO_ENABLE_DIF_BUNDLING BIT_8
#define PO_DIS_FRAME_MODE BIT_9
#define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
#define PO_DIS_VALD_APP_REF_ESC BIT_11
#define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
#define PO_DIS_REF_TAG_REPL BIT_13
#define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
#define PO_DIS_REF_TAG_VALD BIT_15
/*
* ISP queue - 64-Bit addressing, continuation crc entry structure definition.
*/
struct crc_context {
uint32_t handle; /* System handle. */
__le32 ref_tag;
__le16 app_tag;
uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
__le16 guard_seed; /* Initial Guard Seed */
__le16 prot_opts; /* Requested Data Protection Mode */
__le16 blk_size; /* Data size in bytes */
__le16 runt_blk_guard; /* Guard value for runt block (tape
* only) */
__le32 byte_count; /* Total byte count/ total data
* transfer count */
union {
struct {
uint32_t reserved_1;
uint16_t reserved_2;
uint16_t reserved_3;
uint32_t reserved_4;
struct dsd64 data_dsd[1];
uint32_t reserved_5[2];
uint32_t reserved_6;
} nobundling;
struct {
__le32 dif_byte_count; /* Total DIF byte
* count */
uint16_t reserved_1;
__le16 dseg_count; /* Data segment count */
uint32_t reserved_2;
struct dsd64 data_dsd[1];
struct dsd64 dif_dsd;
} bundling;
} u;
struct fcp_cmnd fcp_cmnd;
dma_addr_t crc_ctx_dma;
/* List of DMA context transfers */
struct list_head dsd_list;
/* List of DIF Bundling context DMA address */
struct list_head ldif_dsd_list;
u8 no_ldif_dsd;
struct list_head ldif_dma_hndl_list;
u32 dif_bundl_len;
u8 no_dif_bundl;
/* This structure should not exceed 512 bytes */
};
#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
/*
* ISP queue - status entry structure definition.
*/
#define STATUS_TYPE 0x03 /* Status entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
__le16 scsi_status; /* SCSI status. */
__le16 comp_status; /* Completion status. */
__le16 state_flags; /* State flags. */
__le16 status_flags; /* Status flags. */
__le16 rsp_info_len; /* Response Info Length. */
__le16 req_sense_length; /* Request sense data length. */
__le32 residual_length; /* Residual transfer length. */
uint8_t rsp_info[8]; /* FCP response information. */
uint8_t req_sense_data[32]; /* Request sense data. */
} sts_entry_t;
/*
* Status entry entry status
*/
#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
#define RF_BUSY BIT_1 /* Busy */
#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
RF_INV_E_TYPE)
/*
* Status entry SCSI status bit definitions.
*/
#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
#define SS_RESIDUAL_UNDER BIT_11
#define SS_RESIDUAL_OVER BIT_10
#define SS_SENSE_LEN_VALID BIT_9
#define SS_RESPONSE_INFO_LEN_VALID BIT_8
#define SS_SCSI_STATUS_BYTE 0xff
#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
#define SS_BUSY_CONDITION BIT_3
#define SS_CONDITION_MET BIT_2
#define SS_CHECK_CONDITION BIT_1
/*
* Status entry completion status
*/
#define CS_COMPLETE 0x0 /* No errors */
#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
#define CS_DMA 0x2 /* A DMA direction error. */
#define CS_TRANSPORT 0x3 /* Transport error. */
#define CS_RESET 0x4 /* SCSI bus reset occurred */
#define CS_ABORTED 0x5 /* System aborted command. */
#define CS_TIMEOUT 0x6 /* Timeout error. */
#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
#define CS_DIF_ERROR 0xC /* DIF error detected */
#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
#define CS_QUEUE_FULL 0x1C /* Queue Full. */
#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
/* (selection timeout) */
#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
#define CS_PORT_BUSY 0x2B /* Port Busy */
#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
#define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
failure */
#define CS_REJECT_RECEIVED 0x4E /* Reject received */
#define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */
#define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */
#define CS_EDIF_INV_REQ 0x66 /* invalid request */
#define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */
#define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */
#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
#define CS_UNKNOWN 0x81 /* Driver defined */
#define CS_RETRY 0x82 /* Driver defined */
#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
#define CS_BIDIR_RD_OVERRUN 0x700
#define CS_BIDIR_RD_WR_OVERRUN 0x707
#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
#define CS_BIDIR_RD_UNDERRUN 0x1500
#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
#define CS_BIDIR_DMA 0x200
/*
* Status entry status flags
*/
#define SF_ABTS_TERMINATED BIT_10
#define SF_LOGOUT_SENT BIT_13
/*
* ISP queue - status continuation entry structure definition.
*/
#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint8_t data[60]; /* data */
} sts_cont_entry_t;
/*
* ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
* structure definition.
*/
#define STATUS_TYPE_21 0x21 /* Status entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t handle_count; /* Handle count. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle[15]; /* System handles. */
} sts21_entry_t;
/*
* ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
* structure definition.
*/
#define STATUS_TYPE_22 0x22 /* Status entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t handle_count; /* Handle count. */
uint8_t entry_status; /* Entry Status. */
uint16_t handle[30]; /* System handles. */
} sts22_entry_t;
/*
* ISP queue - marker entry structure definition.
*/
#define MARKER_TYPE 0x04 /* Marker entry. */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t handle_count; /* Handle count. */
uint8_t entry_status; /* Entry Status. */
uint32_t sys_define_2; /* System defined. */
target_id_t target; /* SCSI ID */
uint8_t modifier; /* Modifier (7-0). */
#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
#define MK_SYNC_ID 1 /* Synchronize ID */
#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
/* clear port changed, */
/* use sequence number. */
uint8_t reserved_1;
__le16 sequence_number; /* Sequence number of event */
__le16 lun; /* SCSI LUN */
uint8_t reserved_2[48];
} mrk_entry_t;
/*
* ISP queue - Management Server entry structure definition.
*/
#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
typedef struct {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t handle_count; /* Handle count. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle1; /* System handle. */
target_id_t loop_id;
__le16 status;
__le16 control_flags; /* Control flags. */
uint16_t reserved2;
__le16 timeout;
__le16 cmd_dsd_count;
__le16 total_dsd_count;
uint8_t type;
uint8_t r_ctl;
__le16 rx_id;
uint16_t reserved3;
uint32_t handle2;
__le32 rsp_bytecount;
__le32 req_bytecount;
struct dsd64 req_dsd;
struct dsd64 rsp_dsd;
} ms_iocb_entry_t;
#define SCM_EDC_ACC_RECEIVED BIT_6
#define SCM_RDF_ACC_RECEIVED BIT_7
/*
* ISP queue - Mailbox Command entry structure definition.
*/
#define MBX_IOCB_TYPE 0x39
struct mbx_entry {
uint8_t entry_type;
uint8_t entry_count;
uint8_t sys_define1;
/* Use sys_define1 for source type */
#define SOURCE_SCSI 0x00
#define SOURCE_IP 0x01
#define SOURCE_VI 0x02
#define SOURCE_SCTP 0x03
#define SOURCE_MP 0x04
#define SOURCE_MPIOCTL 0x05
#define SOURCE_ASYNC_IOCB 0x07
uint8_t entry_status;
uint32_t handle;
target_id_t loop_id;
__le16 status;
__le16 state_flags;
__le16 status_flags;
uint32_t sys_define2[2];
__le16 mb0;
__le16 mb1;
__le16 mb2;
__le16 mb3;
__le16 mb6;
__le16 mb7;
__le16 mb9;
__le16 mb10;
uint32_t reserved_2[2];
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
};
#ifndef IMMED_NOTIFY_TYPE
#define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
/*
* ISP queue - immediate notify entry structure definition.
* This is sent by the ISP to the Target driver.
* This IOCB would have report of events sent by the
* initiator, that needs to be handled by the target
* driver immediately.
*/
struct imm_ntfy_from_isp {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
union {
struct {
__le32 sys_define_2; /* System defined. */
target_id_t target;
__le16 lun;
uint8_t target_id;
uint8_t reserved_1;
__le16 status_modifier;
__le16 status;
__le16 task_flags;
__le16 seq_id;
__le16 srr_rx_id;
__le32 srr_rel_offs;
__le16 srr_ui;
#define SRR_IU_DATA_IN 0x1
#define SRR_IU_DATA_OUT 0x5
#define SRR_IU_STATUS 0x7
__le16 srr_ox_id;
uint8_t reserved_2[28];
} isp2x;
struct {
uint32_t reserved;
__le16 nport_handle;
uint16_t reserved_2;
__le16 flags;
#define NOTIFY24XX_FLAGS_FCSP BIT_5
#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
__le16 srr_rx_id;
__le16 status;
uint8_t status_subcode;
uint8_t fw_handle;
__le32 exchange_address;
__le32 srr_rel_offs;
__le16 srr_ui;
__le16 srr_ox_id;
union {
struct {
uint8_t node_name[8];
} plogi; /* PLOGI/ADISC/PDISC */
struct {
/* PRLI word 3 bit 0-15 */
__le16 wd3_lo;
uint8_t resv0[6];
} prli;
struct {
uint8_t port_id[3];
uint8_t resv1;
__le16 nport_handle;
uint16_t resv2;
} req_els;
} u;
uint8_t port_name[8];
uint8_t resv3[3];
uint8_t vp_index;
uint32_t reserved_5;
uint8_t port_id[3];
uint8_t reserved_6;
} isp24;
} u;
uint16_t reserved_7;
__le16 ox_id;
} __packed;
#endif
/*
* ISP request and response queue entry sizes
*/
#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
#define REQUEST_ENTRY_SIZE (sizeof(request_t))
/*
* Switch info gathering structure.
*/
typedef struct {
port_id_t d_id;
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
uint8_t fabric_port_name[WWN_SIZE];
uint16_t fp_speed;
uint8_t fc4_type;
uint8_t fc4_features;
} sw_info_t;
/* FCP-4 types */
#define FC4_TYPE_FCP_SCSI 0x08
#define FC4_TYPE_NVME 0x28
#define FC4_TYPE_OTHER 0x0
#define FC4_TYPE_UNKNOWN 0xff
/* mailbox command 4G & above */
struct mbx_24xx_entry {
uint8_t entry_type;
uint8_t entry_count;
uint8_t sys_define1;
uint8_t entry_status;
uint32_t handle;
uint16_t mb[28];
};
#define IOCB_SIZE 64
/*
* Fibre channel port type.
*/
typedef enum {
FCT_UNKNOWN,
FCT_BROADCAST = 0x01,
FCT_INITIATOR = 0x02,
FCT_TARGET = 0x04,
FCT_NVME_INITIATOR = 0x10,
FCT_NVME_TARGET = 0x20,
FCT_NVME_DISCOVERY = 0x40,
FCT_NVME = 0xf0,
} fc_port_type_t;
enum qla_sess_deletion {
QLA_SESS_DELETION_NONE = 0,
QLA_SESS_DELETION_IN_PROGRESS,
QLA_SESS_DELETED,
};
enum qlt_plogi_link_t {
QLT_PLOGI_LINK_SAME_WWN,
QLT_PLOGI_LINK_CONFLICT,
QLT_PLOGI_LINK_MAX
};
struct qlt_plogi_ack_t {
struct list_head list;
struct imm_ntfy_from_isp iocb;
port_id_t id;
int ref_count;
void *fcport;
};
struct ct_sns_desc {
struct ct_sns_pkt *ct_sns;
dma_addr_t ct_sns_dma;
};
enum discovery_state {
DSC_DELETED,
DSC_GNN_ID,
DSC_GNL,
DSC_LOGIN_PEND,
DSC_LOGIN_FAILED,
DSC_GPDB,
DSC_UPD_FCPORT,
DSC_LOGIN_COMPLETE,
DSC_ADISC,
DSC_DELETE_PEND,
DSC_LOGIN_AUTH_PEND,
};
enum login_state { /* FW control Target side */
DSC_LS_LLIOCB_SENT = 2,
DSC_LS_PLOGI_PEND,
DSC_LS_PLOGI_COMP,
DSC_LS_PRLI_PEND,
DSC_LS_PRLI_COMP,
DSC_LS_PORT_UNAVAIL,
DSC_LS_PRLO_PEND = 9,
DSC_LS_LOGO_PEND,
};
enum rscn_addr_format {
RSCN_PORT_ADDR,
RSCN_AREA_ADDR,
RSCN_DOM_ADDR,
RSCN_FAB_ADDR,
};
/*
* Fibre channel port structure.
*/
typedef struct fc_port {
struct list_head list;
struct scsi_qla_host *vha;
unsigned int conf_compl_supported:1;
unsigned int deleted:2;
unsigned int free_pending:1;
unsigned int local:1;
unsigned int logout_on_delete:1;
unsigned int logo_ack_needed:1;
unsigned int keep_nport_handle:1;
unsigned int send_els_logo:1;
unsigned int login_pause:1;
unsigned int login_succ:1;
unsigned int query:1;
unsigned int id_changed:1;
unsigned int scan_needed:1;
unsigned int n2n_flag:1;
unsigned int explicit_logout:1;
unsigned int prli_pend_timer:1;
unsigned int do_prli_nvme:1;
uint8_t nvme_flag;
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
port_id_t d_id;
uint16_t loop_id;
uint16_t old_loop_id;
struct completion nvme_del_done;
uint32_t nvme_prli_service_param;
#define NVME_PRLI_SP_PI_CTRL BIT_9
#define NVME_PRLI_SP_SLER BIT_8
#define NVME_PRLI_SP_CONF BIT_7
#define NVME_PRLI_SP_INITIATOR BIT_5
#define NVME_PRLI_SP_TARGET BIT_4
#define NVME_PRLI_SP_DISCOVERY BIT_3
#define NVME_PRLI_SP_FIRST_BURST BIT_0
uint32_t nvme_first_burst_size;
#define NVME_FLAG_REGISTERED 4
#define NVME_FLAG_DELETING 2
#define NVME_FLAG_RESETTING 1
struct fc_port *conflict;
unsigned char logout_completed;
int generation;
struct se_session *se_sess;
struct list_head sess_cmd_list;
spinlock_t sess_cmd_lock;
struct kref sess_kref;
struct qla_tgt *tgt;
unsigned long expires;
struct list_head del_list_entry;
struct work_struct free_work;
struct work_struct reg_work;
uint64_t jiffies_at_registration;
unsigned long prli_expired;
struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
uint16_t tgt_id;
uint16_t old_tgt_id;
uint16_t sec_since_registration;
uint8_t fcp_prio;
uint8_t fabric_port_name[WWN_SIZE];
uint16_t fp_speed;
fc_port_type_t port_type;
atomic_t state;
uint32_t flags;
int login_retry;
struct fc_rport *rport, *drport;
u32 supported_classes;
uint8_t fc4_type;
uint8_t fc4_features;
uint8_t scan_state;
unsigned long last_queue_full;
unsigned long last_ramp_up;
uint16_t port_id;
struct nvme_fc_remote_port *nvme_remote_port;
unsigned long retry_delay_timestamp;
struct qla_tgt_sess *tgt_session;
struct ct_sns_desc ct_desc;
enum discovery_state disc_state;
atomic_t shadow_disc_state;
enum discovery_state next_disc_state;
enum login_state fw_login_state;
unsigned long dm_login_expire;
unsigned long plogi_nack_done_deadline;
u32 login_gen, last_login_gen;
u32 rscn_gen, last_rscn_gen;
u32 chip_reset;
struct list_head gnl_entry;
struct work_struct del_work;
u8 iocb[IOCB_SIZE];
u8 current_login_state;
u8 last_login_state;
u16 n2n_link_reset_cnt;
u16 n2n_chip_reset;
struct dentry *dfs_rport_dir;
u64 tgt_short_link_down_cnt;
u64 tgt_link_down_time;
u64 dev_loss_tmo;
/*
* EDIF parameters for encryption.
*/
struct {
uint32_t enable:1; /* device is edif enabled/req'd */
uint32_t app_stop:2;
uint32_t aes_gmac:1;
uint32_t app_sess_online:1;
uint32_t tx_sa_set:1;
uint32_t rx_sa_set:1;
uint32_t tx_sa_pending:1;
uint32_t rx_sa_pending:1;
uint32_t tx_rekey_cnt;
uint32_t rx_rekey_cnt;
uint64_t tx_bytes;
uint64_t rx_bytes;
uint8_t sess_down_acked;
uint8_t auth_state;
uint16_t authok:1;
uint16_t rekey_cnt;
struct list_head edif_indx_list;
spinlock_t indx_list_lock;
struct list_head tx_sa_list;
struct list_head rx_sa_list;
spinlock_t sa_list_lock;
} edif;
} fc_port_t;
enum {
FC4_PRIORITY_NVME = 1,
FC4_PRIORITY_FCP = 2,
};
#define QLA_FCPORT_SCAN 1
#define QLA_FCPORT_FOUND 2
struct event_arg {
fc_port_t *fcport;
srb_t *sp;
port_id_t id;
u16 data[2], rc;
u8 port_name[WWN_SIZE];
u32 iop[2];
};
#include "qla_mr.h"
/*
* Fibre channel port/lun states.
*/
enum {
FCS_UNKNOWN,
FCS_UNCONFIGURED,
FCS_DEVICE_DEAD,
FCS_DEVICE_LOST,
FCS_ONLINE,
};
extern const char *const port_state_str[5];
static const char *const port_dstate_str[] = {
[DSC_DELETED] = "DELETED",
[DSC_GNN_ID] = "GNN_ID",
[DSC_GNL] = "GNL",
[DSC_LOGIN_PEND] = "LOGIN_PEND",
[DSC_LOGIN_FAILED] = "LOGIN_FAILED",
[DSC_GPDB] = "GPDB",
[DSC_UPD_FCPORT] = "UPD_FCPORT",
[DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE",
[DSC_ADISC] = "ADISC",
[DSC_DELETE_PEND] = "DELETE_PEND",
[DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND",
};
/*
* FC port flags.
*/
#define FCF_FABRIC_DEVICE BIT_0
#define FCF_LOGIN_NEEDED BIT_1
#define FCF_FCP2_DEVICE BIT_2
#define FCF_ASYNC_SENT BIT_3
#define FCF_CONF_COMP_SUPPORTED BIT_4
#define FCF_ASYNC_ACTIVE BIT_5
#define FCF_FCSP_DEVICE BIT_6
#define FCF_EDIF_DELETE BIT_7
/* No loop ID flag. */
#define FC_NO_LOOP_ID 0x1000
/*
* FC-CT interface
*
* NOTE: All structures are big-endian in form.
*/
#define CT_REJECT_RESPONSE 0x8001
#define CT_ACCEPT_RESPONSE 0x8002
#define CT_REASON_INVALID_COMMAND_CODE 0x01
#define CT_REASON_CANNOT_PERFORM 0x09
#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
#define CT_EXPL_ALREADY_REGISTERED 0x10
#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
#define CT_EXPL_HBA_NOT_REGISTERED 0x17
#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
#define CT_EXPL_PORT_NOT_REGISTERED 0x21
#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
#define NS_N_PORT_TYPE 0x01
#define NS_NL_PORT_TYPE 0x02
#define NS_NX_PORT_TYPE 0x7F
#define GA_NXT_CMD 0x100
#define GA_NXT_REQ_SIZE (16 + 4)
#define GA_NXT_RSP_SIZE (16 + 620)
#define GPN_FT_CMD 0x172
#define GPN_FT_REQ_SIZE (16 + 4)
#define GNN_FT_CMD 0x173
#define GNN_FT_REQ_SIZE (16 + 4)
#define GID_PT_CMD 0x1A1
#define GID_PT_REQ_SIZE (16 + 4)
#define GPN_ID_CMD 0x112
#define GPN_ID_REQ_SIZE (16 + 4)
#define GPN_ID_RSP_SIZE (16 + 8)
#define GNN_ID_CMD 0x113
#define GNN_ID_REQ_SIZE (16 + 4)
#define GNN_ID_RSP_SIZE (16 + 8)
#define GFT_ID_CMD 0x117
#define GFT_ID_REQ_SIZE (16 + 4)
#define GFT_ID_RSP_SIZE (16 + 32)
#define GID_PN_CMD 0x121
#define GID_PN_REQ_SIZE (16 + 8)
#define GID_PN_RSP_SIZE (16 + 4)
#define RFT_ID_CMD 0x217
#define RFT_ID_REQ_SIZE (16 + 4 + 32)
#define RFT_ID_RSP_SIZE 16
#define RFF_ID_CMD 0x21F
#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
#define RFF_ID_RSP_SIZE 16
#define RNN_ID_CMD 0x213
#define RNN_ID_REQ_SIZE (16 + 4 + 8)
#define RNN_ID_RSP_SIZE 16
#define RSNN_NN_CMD 0x239
#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
#define RSNN_NN_RSP_SIZE 16
#define GFPN_ID_CMD 0x11C
#define GFPN_ID_REQ_SIZE (16 + 4)
#define GFPN_ID_RSP_SIZE (16 + 8)
#define GPSC_CMD 0x127
#define GPSC_REQ_SIZE (16 + 8)
#define GPSC_RSP_SIZE (16 + 2 + 2)
#define GFF_ID_CMD 0x011F
#define GFF_ID_REQ_SIZE (16 + 4)
#define GFF_ID_RSP_SIZE (16 + 128)
/*
* FDMI HBA attribute types.
*/
#define FDMI1_HBA_ATTR_COUNT 10
#define FDMI2_HBA_ATTR_COUNT 17
#define FDMI_HBA_NODE_NAME 0x1
#define FDMI_HBA_MANUFACTURER 0x2
#define FDMI_HBA_SERIAL_NUMBER 0x3
#define FDMI_HBA_MODEL 0x4
#define FDMI_HBA_MODEL_DESCRIPTION 0x5
#define FDMI_HBA_HARDWARE_VERSION 0x6
#define FDMI_HBA_DRIVER_VERSION 0x7
#define FDMI_HBA_OPTION_ROM_VERSION 0x8
#define FDMI_HBA_FIRMWARE_VERSION 0x9
#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
#define FDMI_HBA_NUM_PORTS 0xe
#define FDMI_HBA_FABRIC_NAME 0xf
#define FDMI_HBA_BOOT_BIOS_NAME 0x10
#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
struct ct_fdmi_hba_attr {
__be16 type;
__be16 len;
union {
uint8_t node_name[WWN_SIZE];
uint8_t manufacturer[64];
uint8_t serial_num[32];
uint8_t model[16+1];
uint8_t model_desc[80];
uint8_t hw_version[32];
uint8_t driver_version[32];
uint8_t orom_version[16];
uint8_t fw_version[32];
uint8_t os_version[128];
__be32 max_ct_len;
uint8_t sym_name[256];
__be32 vendor_specific_info;
__be32 num_ports;
uint8_t fabric_name[WWN_SIZE];
uint8_t bios_name[32];
uint8_t vendor_identifier[8];
} a;
};
struct ct_fdmi1_hba_attributes {
__be32 count;
struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
};
struct ct_fdmi2_hba_attributes {
__be32 count;
struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
};
/*
* FDMI Port attribute types.
*/
#define FDMI1_PORT_ATTR_COUNT 6
#define FDMI2_PORT_ATTR_COUNT 16
#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
#define FDMI_PORT_FC4_TYPES 0x1
#define FDMI_PORT_SUPPORT_SPEED 0x2
#define FDMI_PORT_CURRENT_SPEED 0x3
#define FDMI_PORT_MAX_FRAME_SIZE 0x4
#define FDMI_PORT_OS_DEVICE_NAME 0x5
#define FDMI_PORT_HOST_NAME 0x6
#define FDMI_PORT_NODE_NAME 0x7
#define FDMI_PORT_NAME 0x8
#define FDMI_PORT_SYM_NAME 0x9
#define FDMI_PORT_TYPE 0xa
#define FDMI_PORT_SUPP_COS 0xb
#define FDMI_PORT_FABRIC_NAME 0xc
#define FDMI_PORT_FC4_TYPE 0xd
#define FDMI_PORT_STATE 0x101
#define FDMI_PORT_COUNT 0x102
#define FDMI_PORT_IDENTIFIER 0x103
#define FDMI_SMARTSAN_SERVICE 0xF100
#define FDMI_SMARTSAN_GUID 0xF101
#define FDMI_SMARTSAN_VERSION 0xF102
#define FDMI_SMARTSAN_PROD_NAME 0xF103
#define FDMI_SMARTSAN_PORT_INFO 0xF104
#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
#define FDMI_PORT_SPEED_1GB 0x1
#define FDMI_PORT_SPEED_2GB 0x2
#define FDMI_PORT_SPEED_10GB 0x4
#define FDMI_PORT_SPEED_4GB 0x8
#define FDMI_PORT_SPEED_8GB 0x10
#define FDMI_PORT_SPEED_16GB 0x20
#define FDMI_PORT_SPEED_32GB 0x40
#define FDMI_PORT_SPEED_20GB 0x80
#define FDMI_PORT_SPEED_40GB 0x100
#define FDMI_PORT_SPEED_128GB 0x200
#define FDMI_PORT_SPEED_64GB 0x400
#define FDMI_PORT_SPEED_256GB 0x800
#define FDMI_PORT_SPEED_UNKNOWN 0x8000
#define FC_CLASS_2 0x04
#define FC_CLASS_3 0x08
#define FC_CLASS_2_3 0x0C
struct ct_fdmi_port_attr {
__be16 type;
__be16 len;
union {
uint8_t fc4_types[32];
__be32 sup_speed;
__be32 cur_speed;
__be32 max_frame_size;
uint8_t os_dev_name[32];
uint8_t host_name[256];
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
uint8_t port_sym_name[128];
__be32 port_type;
__be32 port_supported_cos;
uint8_t fabric_name[WWN_SIZE];
uint8_t port_fc4_type[32];
__be32 port_state;
__be32 num_ports;
__be32 port_id;
uint8_t smartsan_service[24];
uint8_t smartsan_guid[16];
uint8_t smartsan_version[24];
uint8_t smartsan_prod_name[16];
__be32 smartsan_port_info;
__be32 smartsan_qos_support;
__be32 smartsan_security_support;
} a;
};
struct ct_fdmi1_port_attributes {
__be32 count;
struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
};
struct ct_fdmi2_port_attributes {
__be32 count;
struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
};
#define FDMI_ATTR_TYPELEN(obj) \
(sizeof((obj)->type) + sizeof((obj)->len))
#define FDMI_ATTR_ALIGNMENT(len) \
(4 - ((len) & 3))
/* FDMI register call options */
#define CALLOPT_FDMI1 0
#define CALLOPT_FDMI2 1
#define CALLOPT_FDMI2_SMARTSAN 2
/* FDMI definitions. */
#define GRHL_CMD 0x100
#define GHAT_CMD 0x101
#define GRPL_CMD 0x102
#define GPAT_CMD 0x110
#define RHBA_CMD 0x200
#define RHBA_RSP_SIZE 16
#define RHAT_CMD 0x201
#define RPRT_CMD 0x210
#define RPRT_RSP_SIZE 24
#define RPA_CMD 0x211
#define RPA_RSP_SIZE 16
#define SMARTSAN_RPA_RSP_SIZE 24
#define DHBA_CMD 0x300
#define DHBA_REQ_SIZE (16 + 8)
#define DHBA_RSP_SIZE 16
#define DHAT_CMD 0x301
#define DPRT_CMD 0x310
#define DPA_CMD 0x311
/* CT command header -- request/response common fields */
struct ct_cmd_hdr {
uint8_t revision;
uint8_t in_id[3];
uint8_t gs_type;
uint8_t gs_subtype;
uint8_t options;
uint8_t reserved;
};
/* CT command request */
struct ct_sns_req {
struct ct_cmd_hdr header;
__be16 command;
__be16 max_rsp_size;
uint8_t fragment_id;
uint8_t reserved[3];
union {
/* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
struct {
uint8_t reserved;
be_id_t port_id;
} port_id;
struct {
uint8_t reserved;
uint8_t domain;
uint8_t area;
uint8_t port_type;
} gpn_ft;
struct {
uint8_t port_type;
uint8_t domain;
uint8_t area;
uint8_t reserved;
} gid_pt;
struct {
uint8_t reserved;
be_id_t port_id;
uint8_t fc4_types[32];
} rft_id;
struct {
uint8_t reserved;
be_id_t port_id;
uint16_t reserved2;
uint8_t fc4_feature;
uint8_t fc4_type;
} rff_id;
struct {
uint8_t reserved;
be_id_t port_id;
uint8_t node_name[8];
} rnn_id;
struct {
uint8_t node_name[8];
uint8_t name_len;
uint8_t sym_node_name[255];
} rsnn_nn;
struct {
uint8_t hba_identifier[8];
} ghat;
struct {
uint8_t hba_identifier[8];
__be32 entry_count;
uint8_t port_name[8];
struct ct_fdmi2_hba_attributes attrs;
} rhba;
struct {
uint8_t hba_identifier[8];
struct ct_fdmi1_hba_attributes attrs;
} rhat;
struct {
uint8_t port_name[8];
struct ct_fdmi2_port_attributes attrs;
} rpa;
struct {
uint8_t hba_identifier[8];
uint8_t port_name[8];
struct ct_fdmi2_port_attributes attrs;
} rprt;
struct {
uint8_t port_name[8];
} dhba;
struct {
uint8_t port_name[8];
} dhat;
struct {
uint8_t port_name[8];
} dprt;
struct {
uint8_t port_name[8];
} dpa;
struct {
uint8_t port_name[8];
} gpsc;
struct {
uint8_t reserved;
uint8_t port_id[3];
} gff_id;
struct {
uint8_t port_name[8];
} gid_pn;
} req;
};
/* CT command response header */
struct ct_rsp_hdr {
struct ct_cmd_hdr header;
__be16 response;
uint16_t residual;
uint8_t fragment_id;
uint8_t reason_code;
uint8_t explanation_code;
uint8_t vendor_unique;
};
struct ct_sns_gid_pt_data {
uint8_t control_byte;
be_id_t port_id;
};
/* It's the same for both GPN_FT and GNN_FT */
struct ct_sns_gpnft_rsp {
struct {
struct ct_cmd_hdr header;
uint16_t response;
uint16_t residual;
uint8_t fragment_id;
uint8_t reason_code;
uint8_t explanation_code;
uint8_t vendor_unique;
};
/* Assume the largest number of targets for the union */
struct ct_sns_gpn_ft_data {
u8 control_byte;
u8 port_id[3];
u32 reserved;
u8 port_name[8];
} entries[1];
};
/* CT command response */
struct ct_sns_rsp {
struct ct_rsp_hdr header;
union {
struct {
uint8_t port_type;
be_id_t port_id;
uint8_t port_name[8];
uint8_t sym_port_name_len;
uint8_t sym_port_name[255];
uint8_t node_name[8];
uint8_t sym_node_name_len;
uint8_t sym_node_name[255];
uint8_t init_proc_assoc[8];
uint8_t node_ip_addr[16];
uint8_t class_of_service[4];
uint8_t fc4_types[32];
uint8_t ip_address[16];
uint8_t fabric_port_name[8];
uint8_t reserved;
uint8_t hard_address[3];
} ga_nxt;
struct {
/* Assume the largest number of targets for the union */
struct ct_sns_gid_pt_data
entries[MAX_FIBRE_DEVICES_MAX];
} gid_pt;
struct {
uint8_t port_name[8];
} gpn_id;
struct {
uint8_t node_name[8];
} gnn_id;
struct {
uint8_t fc4_types[32];
} gft_id;
struct {
uint32_t entry_count;
uint8_t port_name[8];
struct ct_fdmi1_hba_attributes attrs;
} ghat;
struct {
uint8_t port_name[8];
} gfpn_id;
struct {
__be16 speeds;
__be16 speed;
} gpsc;
#define GFF_FCP_SCSI_OFFSET 7
#define GFF_NVME_OFFSET 23 /* type = 28h */
struct {
uint8_t fc4_features[128];
#define FC4_FF_TARGET BIT_0
#define FC4_FF_INITIATOR BIT_1
} gff_id;
struct {
uint8_t reserved;
uint8_t port_id[3];
} gid_pn;
} rsp;
};
struct ct_sns_pkt {
union {
struct ct_sns_req req;
struct ct_sns_rsp rsp;
} p;
};
struct ct_sns_gpnft_pkt {
union {
struct ct_sns_req req;
struct ct_sns_gpnft_rsp rsp;
} p;
};
enum scan_flags_t {
SF_SCANNING = BIT_0,
SF_QUEUED = BIT_1,
};
enum fc4type_t {
FS_FC4TYPE_FCP = BIT_0,
FS_FC4TYPE_NVME = BIT_1,
FS_FCP_IS_N2N = BIT_7,
};
struct fab_scan_rp {
port_id_t id;
enum fc4type_t fc4type;
u8 port_name[8];
u8 node_name[8];
};
struct fab_scan {
struct fab_scan_rp *l;
u32 size;
u16 scan_retry;
#define MAX_SCAN_RETRIES 5
enum scan_flags_t scan_flags;
struct delayed_work scan_work;
};
/*
* SNS command structures -- for 2200 compatibility.
*/
#define RFT_ID_SNS_SCMD_LEN 22
#define RFT_ID_SNS_CMD_SIZE 60
#define RFT_ID_SNS_DATA_SIZE 16
#define RNN_ID_SNS_SCMD_LEN 10
#define RNN_ID_SNS_CMD_SIZE 36
#define RNN_ID_SNS_DATA_SIZE 16
#define GA_NXT_SNS_SCMD_LEN 6
#define GA_NXT_SNS_CMD_SIZE 28
#define GA_NXT_SNS_DATA_SIZE (620 + 16)
#define GID_PT_SNS_SCMD_LEN 6
#define GID_PT_SNS_CMD_SIZE 28
/*
* Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
* adapters.
*/
#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
#define GPN_ID_SNS_SCMD_LEN 6
#define GPN_ID_SNS_CMD_SIZE 28
#define GPN_ID_SNS_DATA_SIZE (8 + 16)
#define GNN_ID_SNS_SCMD_LEN 6
#define GNN_ID_SNS_CMD_SIZE 28
#define GNN_ID_SNS_DATA_SIZE (8 + 16)
struct sns_cmd_pkt {
union {
struct {
__le16 buffer_length;
__le16 reserved_1;
__le64 buffer_address __packed;
__le16 subcommand_length;
__le16 reserved_2;
__le16 subcommand;
__le16 size;
uint32_t reserved_3;
uint8_t param[36];
} cmd;
uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
} p;
};
struct fw_blob {
char *name;
uint32_t segs[4];
const struct firmware *fw;
};
/* Return data from MBC_GET_ID_LIST call. */
struct gid_list_info {
uint8_t al_pa;
uint8_t area;
uint8_t domain;
uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
__le16 loop_id; /* ISP23XX -- 6 bytes. */
uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
};
/* NPIV */
typedef struct vport_info {
uint8_t port_name[WWN_SIZE];
uint8_t node_name[WWN_SIZE];
int vp_id;
uint16_t loop_id;
unsigned long host_no;
uint8_t port_id[3];
int loop_state;
} vport_info_t;
typedef struct vport_params {
uint8_t port_name[WWN_SIZE];
uint8_t node_name[WWN_SIZE];
uint32_t options;
#define VP_OPTS_RETRY_ENABLE BIT_0
#define VP_OPTS_VP_DISABLE BIT_1
} vport_params_t;
/* NPIV - return codes of VP create and modify */
#define VP_RET_CODE_OK 0
#define VP_RET_CODE_FATAL 1
#define VP_RET_CODE_WRONG_ID 2
#define VP_RET_CODE_WWPN 3
#define VP_RET_CODE_RESOURCES 4
#define VP_RET_CODE_NO_MEM 5
#define VP_RET_CODE_NOT_FOUND 6
struct qla_hw_data;
struct rsp_que;
/*
* ISP operations
*/
struct isp_operations {
int (*pci_config) (struct scsi_qla_host *);
int (*reset_chip)(struct scsi_qla_host *);
int (*chip_diag) (struct scsi_qla_host *);
void (*config_rings) (struct scsi_qla_host *);
int (*reset_adapter)(struct scsi_qla_host *);
int (*nvram_config) (struct scsi_qla_host *);
void (*update_fw_options) (struct scsi_qla_host *);
int (*load_risc) (struct scsi_qla_host *, uint32_t *);
char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
irq_handler_t intr_handler;
void (*enable_intrs) (struct qla_hw_data *);
void (*disable_intrs) (struct qla_hw_data *);
int (*abort_command) (srb_t *);
int (*target_reset) (struct fc_port *, uint64_t, int);
int (*lun_reset) (struct fc_port *, uint64_t, int);
int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
uint8_t, uint8_t, uint16_t *, uint8_t);
int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
uint8_t, uint8_t);
uint16_t (*calc_req_entries) (uint16_t);
void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
uint32_t);
uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
uint32_t);
void (*fw_dump)(struct scsi_qla_host *vha);
void (*mpi_fw_dump)(struct scsi_qla_host *, int);
/* Context: task, might sleep */
int (*beacon_on) (struct scsi_qla_host *);
int (*beacon_off) (struct scsi_qla_host *);
void (*beacon_blink) (struct scsi_qla_host *);
void *(*read_optrom)(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
uint32_t);
int (*get_flash_version) (struct scsi_qla_host *, void *);
int (*start_scsi) (srb_t *);
int (*start_scsi_mq) (srb_t *);
/* Context: task, might sleep */
int (*abort_isp) (struct scsi_qla_host *);
int (*iospace_config)(struct qla_hw_data *);
int (*initialize_adapter)(struct scsi_qla_host *);
};
/* MSI-X Support *************************************************************/
#define QLA_MSIX_CHIP_REV_24XX 3
#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
#define QLA_BASE_VECTORS 2 /* default + RSP */
#define QLA_MSIX_RSP_Q 0x01
#define QLA_ATIO_VECTOR 0x02
#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
#define QLA_MIDX_DEFAULT 0
#define QLA_MIDX_RSP_Q 1
#define QLA_PCI_MSIX_CONTROL 0xa2
#define QLA_83XX_PCI_MSIX_CONTROL 0x92
struct scsi_qla_host;
#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
struct qla_msix_entry {
int have_irq;
int in_use;
uint32_t vector;
uint32_t vector_base0;
uint16_t entry;
char name[30];
void *handle;
int cpuid;
};
#define WATCH_INTERVAL 1 /* number of seconds */
/* Work events. */
enum qla_work_type {
QLA_EVT_AEN,
QLA_EVT_IDC_ACK,
QLA_EVT_ASYNC_LOGIN,
QLA_EVT_ASYNC_LOGOUT,
QLA_EVT_ASYNC_ADISC,
QLA_EVT_UEVENT,
QLA_EVT_AENFX,
QLA_EVT_GPNID,
QLA_EVT_UNMAP,
QLA_EVT_NEW_SESS,
QLA_EVT_GPDB,
QLA_EVT_PRLI,
QLA_EVT_GPSC,
QLA_EVT_GNL,
QLA_EVT_NACK,
QLA_EVT_RELOGIN,
QLA_EVT_ASYNC_PRLO,
QLA_EVT_ASYNC_PRLO_DONE,
QLA_EVT_GPNFT,
QLA_EVT_GPNFT_DONE,
QLA_EVT_GNNFT_DONE,
QLA_EVT_GNNID,
QLA_EVT_GFPNID,
QLA_EVT_SP_RETRY,
QLA_EVT_IIDMA,
QLA_EVT_ELS_PLOGI,
QLA_EVT_SA_REPLACE,
};
struct qla_work_evt {
struct list_head list;
enum qla_work_type type;
u32 flags;
#define QLA_EVT_FLAG_FREE 0x1
union {
struct {
enum fc_host_event_code code;
u32 data;
} aen;
struct {
#define QLA_IDC_ACK_REGS 7
uint16_t mb[QLA_IDC_ACK_REGS];
} idc_ack;
struct {
struct fc_port *fcport;
#define QLA_LOGIO_LOGIN_RETRIED BIT_0
u16 data[2];
} logio;
struct {
u32 code;
#define QLA_UEVENT_CODE_FW_DUMP 0
} uevent;
struct {
uint32_t evtcode;
uint32_t mbx[8];
uint32_t count;
} aenfx;
struct {
srb_t *sp;
} iosb;
struct {
port_id_t id;
} gpnid;
struct {
port_id_t id;
u8 port_name[8];
u8 node_name[8];
void *pla;
u8 fc4_type;
} new_sess;
struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
fc_port_t *fcport;
u8 opt;
} fcport;
struct {
fc_port_t *fcport;
u8 iocb[IOCB_SIZE];
int type;
} nack;
struct {
u8 fc4_type;
srb_t *sp;
} gpnft;
struct {
struct edif_sa_ctl *sa_ctl;
fc_port_t *fcport;
uint16_t nport_handle;
} sa_update;
} u;
};
struct qla_chip_state_84xx {
struct list_head list;
struct kref kref;
void *bus;
spinlock_t access_lock;
struct mutex fw_update_mutex;
uint32_t fw_update;
uint32_t op_fw_version;
uint32_t op_fw_size;
uint32_t op_fw_seq_size;
uint32_t diag_fw_version;
uint32_t gold_fw_version;
};
struct qla_dif_statistics {
uint64_t dif_input_bytes;
uint64_t dif_output_bytes;
uint64_t dif_input_requests;
uint64_t dif_output_requests;
uint32_t dif_guard_err;
uint32_t dif_ref_tag_err;
uint32_t dif_app_tag_err;
};
struct qla_statistics {
uint32_t total_isp_aborts;
uint64_t input_bytes;
uint64_t output_bytes;
uint64_t input_requests;
uint64_t output_requests;
uint32_t control_requests;
uint64_t jiffies_at_last_reset;
uint32_t stat_max_pend_cmds;
uint32_t stat_max_qfull_cmds_alloc;
uint32_t stat_max_qfull_cmds_dropped;
struct qla_dif_statistics qla_dif_stats;
};
struct bidi_statistics {
unsigned long long io_count;
unsigned long long transfer_bytes;
};
struct qla_tc_param {
struct scsi_qla_host *vha;
uint32_t blk_sz;
uint32_t bufflen;
struct scatterlist *sg;
struct scatterlist *prot_sg;
struct crc_context *ctx;
uint8_t *ctx_dsd_alloced;
};
/* Multi queue support */
#define MBC_INITIALIZE_MULTIQ 0x1f
#define QLA_QUE_PAGE 0X1000
#define QLA_MQ_SIZE 32
#define QLA_MAX_QUEUES 256
#define ISP_QUE_REG(ha, id) \
((ha->mqenable || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
((void __iomem *)ha->iobase))
#define QLA_REQ_QUE_ID(tag) \
((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
#define QLA_DEFAULT_QUE_QOS 5
#define QLA_PRECONFIG_VPORTS 32
#define QLA_MAX_VPORTS_QLA24XX 128
#define QLA_MAX_VPORTS_QLA25XX 256
struct qla_tgt_counters {
uint64_t qla_core_sbt_cmd;
uint64_t core_qla_que_buf;
uint64_t qla_core_ret_ctio;
uint64_t core_qla_snd_status;
uint64_t qla_core_ret_sta_ctio;
uint64_t core_qla_free_cmd;
uint64_t num_q_full_sent;
uint64_t num_alloc_iocb_failed;
uint64_t num_term_xchg_sent;
};
struct qla_counters {
uint64_t input_bytes;
uint64_t input_requests;
uint64_t output_bytes;
uint64_t output_requests;
};
struct qla_qpair;
/* Response queue data structure */
struct rsp_que {
dma_addr_t dma;
response_t *ring;
response_t *ring_ptr;
__le32 __iomem *rsp_q_in; /* FWI2-capable only. */
__le32 __iomem *rsp_q_out;
uint16_t ring_index;
uint16_t out_ptr;
uint16_t *in_ptr; /* queue shadow in index */
uint16_t length;
uint16_t options;
uint16_t rid;
uint16_t id;
uint16_t vp_idx;
struct qla_hw_data *hw;
struct qla_msix_entry *msix;
struct req_que *req;
srb_t *status_srb; /* status continuation entry */
struct qla_qpair *qpair;
dma_addr_t dma_fx00;
response_t *ring_fx00;
uint16_t length_fx00;
uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
};
/* Request queue data structure */
struct req_que {
dma_addr_t dma;
request_t *ring;
request_t *ring_ptr;
__le32 __iomem *req_q_in; /* FWI2-capable only. */
__le32 __iomem *req_q_out;
uint16_t ring_index;
uint16_t in_ptr;
uint16_t *out_ptr; /* queue shadow out index */
uint16_t cnt;
uint16_t length;
uint16_t options;
uint16_t rid;
uint16_t id;
uint16_t qos;
uint16_t vp_idx;
struct rsp_que *rsp;
srb_t **outstanding_cmds;
uint32_t current_outstanding_cmd;
uint16_t num_outstanding_cmds;
int max_q_depth;
dma_addr_t dma_fx00;
request_t *ring_fx00;
uint16_t length_fx00;
uint8_t req_pkt[REQUEST_ENTRY_SIZE];
};
struct qla_fw_resources {
u16 iocbs_total;
u16 iocbs_limit;
u16 iocbs_qp_limit;
u16 iocbs_used;
u16 exch_total;
u16 exch_limit;
u16 exch_used;
u16 pad;
};
struct qla_fw_res {
u16 iocb_total;
u16 iocb_limit;
atomic_t iocb_used;
u16 exch_total;
u16 exch_limit;
atomic_t exch_used;
};
#define QLA_IOCB_PCT_LIMIT 95
/*Queue pair data structure */
struct qla_qpair {
spinlock_t qp_lock;
atomic_t ref_count;
uint32_t lun_cnt;
/*
* For qpair 0, qp_lock_ptr will point at hardware_lock due to
* legacy code. For other Qpair(s), it will point at qp_lock.
*/
spinlock_t *qp_lock_ptr;
struct scsi_qla_host *vha;
u32 chip_reset;
/* distill these fields down to 'online=0/1'
* ha->flags.eeh_busy
* ha->flags.pci_channel_io_perm_failure
* base_vha->loop_state
*/
uint32_t online:1;
/* move vha->flags.difdix_supported here */
uint32_t difdix_supported:1;
uint32_t delete_in_progress:1;
uint32_t fw_started:1;
uint32_t enable_class_2:1;
uint32_t enable_explicit_conf:1;
uint32_t use_shadow_reg:1;
uint32_t rcv_intr:1;
uint16_t id; /* qp number used with FW */
uint16_t vp_idx; /* vport ID */
mempool_t *srb_mempool;
struct pci_dev *pdev;
void (*reqq_start_iocbs)(struct qla_qpair *);
/* to do: New driver: move queues to here instead of pointers */
struct req_que *req;
struct rsp_que *rsp;
struct atio_que *atio;
struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
struct qla_hw_data *hw;
struct work_struct q_work;
struct qla_counters counters;
struct list_head qp_list_elem; /* vha->qp_list */
struct list_head hints_list;
uint16_t retry_term_cnt;
__le32 retry_term_exchg_addr;
uint64_t retry_term_jiff;
struct qla_tgt_counters tgt_counters;
uint16_t cpuid;
bool cpu_mapped;
struct qla_fw_resources fwres ____cacheline_aligned;
u32 cmd_cnt;
u32 cmd_completion_cnt;
u32 prev_completion_cnt;
};
/* Place holder for FW buffer parameters */
struct qlfc_fw {
void *fw_buf;
dma_addr_t fw_dma;
uint32_t len;
};
struct rdp_req_payload {
uint32_t els_request;
uint32_t desc_list_len;
/* NPIV descriptor */
struct {
uint32_t desc_tag;
uint32_t desc_len;
uint8_t reserved;
uint8_t nport_id[3];
} npiv_desc;
};
struct rdp_rsp_payload {
struct {
__be32 cmd;
__be32 len;
} hdr;
/* LS Request Info descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be32 req_payload_word_0;
} ls_req_info_desc;
/* LS Request Info descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be32 req_payload_word_0;
} ls_req_info_desc2;
/* SFP diagnostic param descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be16 temperature;
__be16 vcc;
__be16 tx_bias;
__be16 tx_power;
__be16 rx_power;
__be16 sfp_flags;
} sfp_diag_desc;
/* Port Speed Descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be16 speed_capab;
__be16 operating_speed;
} port_speed_desc;
/* Link Error Status Descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be32 link_fail_cnt;
__be32 loss_sync_cnt;
__be32 loss_sig_cnt;
__be32 prim_seq_err_cnt;
__be32 inval_xmit_word_cnt;
__be32 inval_crc_cnt;
uint8_t pn_port_phy_type;
uint8_t reserved[3];
} ls_err_desc;
/* Port name description with diag param */
struct {
__be32 desc_tag;
__be32 desc_len;
uint8_t WWNN[WWN_SIZE];
uint8_t WWPN[WWN_SIZE];
} port_name_diag_desc;
/* Port Name desc for Direct attached Fx_Port or Nx_Port */
struct {
__be32 desc_tag;
__be32 desc_len;
uint8_t WWNN[WWN_SIZE];
uint8_t WWPN[WWN_SIZE];
} port_name_direct_desc;
/* Buffer Credit descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be32 fcport_b2b;
__be32 attached_fcport_b2b;
__be32 fcport_rtt;
} buffer_credit_desc;
/* Optical Element Data Descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
__be16 high_alarm;
__be16 low_alarm;
__be16 high_warn;
__be16 low_warn;
__be32 element_flags;
} optical_elmt_desc[5];
/* Optical Product Data Descriptor */
struct {
__be32 desc_tag;
__be32 desc_len;
uint8_t vendor_name[16];
uint8_t part_number[16];
uint8_t serial_number[16];
uint8_t revision[4];
uint8_t date[8];
} optical_prod_desc;
};
#define RDP_DESC_LEN(obj) \
(sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
#define RDP_PORT_SPEED_1GB BIT_15
#define RDP_PORT_SPEED_2GB BIT_14
#define RDP_PORT_SPEED_4GB BIT_13
#define RDP_PORT_SPEED_10GB BIT_12
#define RDP_PORT_SPEED_8GB BIT_11
#define RDP_PORT_SPEED_16GB BIT_10
#define RDP_PORT_SPEED_32GB BIT_9
#define RDP_PORT_SPEED_64GB BIT_8
#define RDP_PORT_SPEED_UNKNOWN BIT_0
struct scsi_qlt_host {
void *target_lport_ptr;
struct mutex tgt_mutex;
struct mutex tgt_host_action_mutex;
struct qla_tgt *qla_tgt;
};
struct qlt_hw_data {
/* Protected by hw lock */
uint32_t node_name_set:1;
dma_addr_t atio_dma; /* Physical address. */
struct atio *atio_ring; /* Base virtual address */
struct atio *atio_ring_ptr; /* Current address. */
uint16_t atio_ring_index; /* Current index. */
uint16_t atio_q_length;
__le32 __iomem *atio_q_in;
__le32 __iomem *atio_q_out;
const struct qla_tgt_func_tmpl *tgt_ops;
struct qla_tgt_vp_map *tgt_vp_map;
int saved_set;
__le16 saved_exchange_count;
__le32 saved_firmware_options_1;
__le32 saved_firmware_options_2;
__le32 saved_firmware_options_3;
uint8_t saved_firmware_options[2];
uint8_t saved_add_firmware_options[2];
uint8_t tgt_node_name[WWN_SIZE];
struct dentry *dfs_tgt_sess;
struct dentry *dfs_tgt_port_database;
struct dentry *dfs_naqp;
struct list_head q_full_list;
uint32_t num_pend_cmds;
uint32_t num_qfull_cmds_alloc;
uint32_t num_qfull_cmds_dropped;
spinlock_t q_full_lock;
uint32_t leak_exchg_thresh_hold;
spinlock_t sess_lock;
int num_act_qpairs;
#define DEFAULT_NAQP 2
spinlock_t atio_lock ____cacheline_aligned;
};
#define MAX_QFULL_CMDS_ALLOC 8192
#define Q_FULL_THRESH_HOLD_PERCENT 90
#define Q_FULL_THRESH_HOLD(ha) \
((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
struct qla_hw_data_stat {
u32 num_fw_dump;
u32 num_mpi_reset;
};
/* refer to pcie_do_recovery reference */
typedef enum {
QLA_PCI_RESUME,
QLA_PCI_ERR_DETECTED,
QLA_PCI_MMIO_ENABLED,
QLA_PCI_SLOT_RESET,
} pci_error_state_t;
/*
* Qlogic host adapter specific data structure.
*/
struct qla_hw_data {
struct pci_dev *pdev;
/* SRB cache. */
#define SRB_MIN_REQ 128
mempool_t *srb_mempool;
u8 port_name[WWN_SIZE];
volatile struct {
uint32_t mbox_int :1;
uint32_t mbox_busy :1;
uint32_t disable_risc_code_load :1;
uint32_t enable_64bit_addressing :1;
uint32_t enable_lip_reset :1;
uint32_t enable_target_reset :1;
uint32_t enable_lip_full_login :1;
uint32_t enable_led_scheme :1;
uint32_t msi_enabled :1;
uint32_t msix_enabled :1;
uint32_t disable_serdes :1;
uint32_t gpsc_supported :1;
uint32_t npiv_supported :1;
uint32_t pci_channel_io_perm_failure :1;
uint32_t fce_enabled :1;
uint32_t fac_supported :1;
uint32_t chip_reset_done :1;
uint32_t running_gold_fw :1;
uint32_t eeh_busy :1;
uint32_t disable_msix_handshake :1;
uint32_t fcp_prio_enabled :1;
uint32_t isp82xx_fw_hung:1;
uint32_t nic_core_hung:1;
uint32_t quiesce_owner:1;
uint32_t nic_core_reset_hdlr_active:1;
uint32_t nic_core_reset_owner:1;
uint32_t isp82xx_no_md_cap:1;
uint32_t host_shutting_down:1;
uint32_t idc_compl_status:1;
uint32_t mr_reset_hdlr_active:1;
uint32_t mr_intr_valid:1;
uint32_t dport_enabled:1;
uint32_t fawwpn_enabled:1;
uint32_t exlogins_enabled:1;
uint32_t exchoffld_enabled:1;
uint32_t lip_ae:1;
uint32_t n2n_ae:1;
uint32_t fw_started:1;
uint32_t fw_init_done:1;
uint32_t lr_detected:1;
uint32_t rida_fmt2:1;
uint32_t purge_mbox:1;
uint32_t n2n_bigger:1;
uint32_t secure_adapter:1;
uint32_t secure_fw:1;
/* Supported by Adapter */
uint32_t scm_supported_a:1;
/* Supported by Firmware */
uint32_t scm_supported_f:1;
/* Enabled in Driver */
uint32_t scm_enabled:1;
uint32_t edif_hw:1;
uint32_t edif_enabled:1;
uint32_t n2n_fw_acc_sec:1;
uint32_t plogi_template_valid:1;
uint32_t port_isolated:1;
uint32_t eeh_flush:2;
#define EEH_FLUSH_RDY 1
#define EEH_FLUSH_DONE 2
} flags;
uint16_t max_exchg;
uint16_t lr_distance; /* 32G & above */
#define LR_DISTANCE_5K 1
#define LR_DISTANCE_10K 0
/* This spinlock is used to protect "io transactions", you must
* acquire it before doing any IO to the card, eg with RD_REG*() and
* WRT_REG*() for the duration of your entire commandtransaction.
*
* This spinlock is of lower priority than the io request lock.
*/
spinlock_t hardware_lock ____cacheline_aligned;
int bars;
int mem_only;
device_reg_t *iobase; /* Base I/O address */
resource_size_t pio_address;
#define MIN_IOBASE_LEN 0x100
dma_addr_t bar0_hdl;
void __iomem *cregbase;
dma_addr_t bar2_hdl;
#define BAR0_LEN_FX00 (1024 * 1024)
#define BAR2_LEN_FX00 (128 * 1024)
uint32_t rqstq_intr_code;
uint32_t mbx_intr_code;
uint32_t req_que_len;
uint32_t rsp_que_len;
uint32_t req_que_off;
uint32_t rsp_que_off;
unsigned long eeh_jif;
/* Multi queue data structs */
device_reg_t *mqiobase;
device_reg_t *msixbase;
uint16_t msix_count;
uint8_t mqenable;
struct req_que **req_q_map;
struct rsp_que **rsp_q_map;
struct qla_qpair **queue_pair_map;
struct qla_qpair **qp_cpu_map;
unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
/ sizeof(unsigned long)];
uint8_t max_req_queues;
uint8_t max_rsp_queues;
uint8_t max_qpairs;
uint8_t num_qpairs;
struct qla_qpair *base_qpair;
struct qla_npiv_entry *npiv_info;
uint16_t nvram_npiv_size;
uint16_t switch_cap;
#define FLOGI_SEQ_DEL BIT_8
#define FLOGI_MID_SUPPORT BIT_10
#define FLOGI_VSAN_SUPPORT BIT_12
#define FLOGI_SP_SUPPORT BIT_13
uint8_t port_no; /* Physical port of adapter */
uint8_t exch_starvation;
/* Timeout timers. */
uint8_t loop_down_abort_time; /* port down timer */
atomic_t loop_down_timer; /* loop down timer */
uint8_t link_down_timeout; /* link down timeout */
uint16_t max_loop_id;
uint16_t max_fibre_devices; /* Maximum number of targets */
uint16_t fb_rev;
uint16_t min_external_loopid; /* First external loop Id */
#define PORT_SPEED_UNKNOWN 0xFFFF
#define PORT_SPEED_1GB 0x00
#define PORT_SPEED_2GB 0x01
#define PORT_SPEED_AUTO 0x02
#define PORT_SPEED_4GB 0x03
#define PORT_SPEED_8GB 0x04
#define PORT_SPEED_16GB 0x05
#define PORT_SPEED_32GB 0x06
#define PORT_SPEED_64GB 0x07
#define PORT_SPEED_10GB 0x13
uint16_t link_data_rate; /* F/W operating speed */
uint16_t set_data_rate; /* Set by user */
uint8_t current_topology;
uint8_t prev_topology;
#define ISP_CFG_NL 1
#define ISP_CFG_N 2
#define ISP_CFG_FL 4
#define ISP_CFG_F 8
uint8_t operating_mode; /* F/W operating mode */
#define LOOP 0
#define P2P 1
#define LOOP_P2P 2
#define P2P_LOOP 3
uint8_t interrupts_on;
uint32_t isp_abort_cnt;
#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
uint32_t isp_type;
#define DT_ISP2100 BIT_0
#define DT_ISP2200 BIT_1
#define DT_ISP2300 BIT_2
#define DT_ISP2312 BIT_3
#define DT_ISP2322 BIT_4
#define DT_ISP6312 BIT_5
#define DT_ISP6322 BIT_6
#define DT_ISP2422 BIT_7
#define DT_ISP2432 BIT_8
#define DT_ISP5422 BIT_9
#define DT_ISP5432 BIT_10
#define DT_ISP2532 BIT_11
#define DT_ISP8432 BIT_12
#define DT_ISP8001 BIT_13
#define DT_ISP8021 BIT_14
#define DT_ISP2031 BIT_15
#define DT_ISP8031 BIT_16
#define DT_ISPFX00 BIT_17
#define DT_ISP8044 BIT_18
#define DT_ISP2071 BIT_19
#define DT_ISP2271 BIT_20
#define DT_ISP2261 BIT_21
#define DT_ISP2061 BIT_22
#define DT_ISP2081 BIT_23
#define DT_ISP2089 BIT_24
#define DT_ISP2281 BIT_25
#define DT_ISP2289 BIT_26
#define DT_ISP_LAST (DT_ISP2289 << 1)
uint32_t device_type;
#define DT_T10_PI BIT_25
#define DT_IIDMA BIT_26
#define DT_FWI2 BIT_27
#define DT_ZIO_SUPPORTED BIT_28
#define DT_OEM_001 BIT_29
#define DT_ISP2200A BIT_30
#define DT_EXTENDED_IDS BIT_31
#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
#define IS_QLA81XX(ha) (IS_QLA8001(ha))
#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
IS_QLA6312(ha) || IS_QLA6322(ha))
#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
#define IS_QLA25XX(ha) (IS_QLA2532(ha))
#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
#define IS_QLA84XX(ha) (IS_QLA8432(ha))
#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
IS_QLA84XX(ha))
#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
IS_QLA8031(ha) || IS_QLA8044(ha))
#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
IS_QLA8044(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
#define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_BIDI_CAPABLE(ha) \
(IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
/* Bit 21 of fw_attributes decides the MCTP capabilities */
#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
((ha)->fw_attributes_ext[0] & BIT_0))
#define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
#define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
#define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
#define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
#define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
(QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
#define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
(QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
#define QLA_ABTS_WAIT_ENABLED(_sp) \
(QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
(((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_EXCHG_OFFLD_CAPABLE(ha) \
(IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
(IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_ZIO_THRESHOLD_CAPABLE(ha) \
((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
(ha->zio_mode == QLA_ZIO_MODE_6))
/* HBA serial number */
uint8_t serial0;
uint8_t serial1;
uint8_t serial2;
/* NVRAM configuration data */
#define MAX_NVRAM_SIZE 4096
#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
uint16_t nvram_size;
uint16_t nvram_base;
void *nvram;
uint16_t vpd_size;
uint16_t vpd_base;
void *vpd;
uint16_t loop_reset_delay;
uint8_t retry_count;
uint8_t login_timeout;
uint16_t r_a_tov;
int port_down_retry_count;
uint8_t mbx_count;
uint8_t aen_mbx_count;
atomic_t num_pend_mbx_stage1;
atomic_t num_pend_mbx_stage2;
uint16_t frame_payload_size;
uint32_t login_retry_count;
/* SNS command interfaces. */
ms_iocb_entry_t *ms_iocb;
dma_addr_t ms_iocb_dma;
struct ct_sns_pkt *ct_sns;
dma_addr_t ct_sns_dma;
/* SNS command interfaces for 2200. */
struct sns_cmd_pkt *sns_cmd;
dma_addr_t sns_cmd_dma;
#define SFP_DEV_SIZE 512
#define SFP_BLOCK_SIZE 64
#define SFP_RTDI_LEN SFP_BLOCK_SIZE
void *sfp_data;
dma_addr_t sfp_data_dma;
struct qla_flt_header *flt;
dma_addr_t flt_dma;
#define XGMAC_DATA_SIZE 4096
void *xgmac_data;
dma_addr_t xgmac_data_dma;
#define DCBX_TLV_DATA_SIZE 4096
void *dcbx_tlv;
dma_addr_t dcbx_tlv_dma;
struct task_struct *dpc_thread;
uint8_t dpc_active; /* DPC routine is active */
dma_addr_t gid_list_dma;
struct gid_list_info *gid_list;
int gid_list_info_size;
/* Small DMA pool allocations -- maximum 256 bytes in length. */
#define DMA_POOL_SIZE 256
struct dma_pool *s_dma_pool;
dma_addr_t init_cb_dma;
init_cb_t *init_cb;
int init_cb_size;
dma_addr_t ex_init_cb_dma;
struct ex_init_cb_81xx *ex_init_cb;
dma_addr_t sf_init_cb_dma;
struct init_sf_cb *sf_init_cb;
void *scm_fpin_els_buff;
uint64_t scm_fpin_els_buff_size;
bool scm_fpin_valid;
bool scm_fpin_payload_size;
void *async_pd;
dma_addr_t async_pd_dma;
#define ENABLE_EXTENDED_LOGIN BIT_7
/* Extended Logins */
void *exlogin_buf;
dma_addr_t exlogin_buf_dma;
uint32_t exlogin_size;
#define ENABLE_EXCHANGE_OFFLD BIT_2
/* Exchange Offload */
void *exchoffld_buf;
dma_addr_t exchoffld_buf_dma;
int exchoffld_size;
int exchoffld_count;
/* n2n */
struct fc_els_flogi plogi_els_payld;
#define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
void *swl;
/* These are used by mailbox operations. */
uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
mbx_cmd_t *mcp;
struct mbx_cmd_32 *mcp32;
unsigned long mbx_cmd_flags;
#define MBX_INTERRUPT 1
#define MBX_INTR_WAIT 2
#define MBX_UPDATE_FLASH_ACTIVE 3
struct mutex vport_lock; /* Virtual port synchronization */
spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
struct mutex mq_lock; /* multi-queue synchronization */
struct completion mbx_cmd_comp; /* Serialize mbx access */
struct completion mbx_intr_comp; /* Used for completion notification */
struct completion dcbx_comp; /* For set port config notification */
struct completion lb_portup_comp; /* Used to wait for link up during
* loopback */
#define DCBX_COMP_TIMEOUT 20
#define LB_PORTUP_COMP_TIMEOUT 10
int notify_dcbx_comp;
int notify_lb_portup_comp;
struct mutex selflogin_lock;
/* Basic firmware related information. */
uint16_t fw_major_version;
uint16_t fw_minor_version;
uint16_t fw_subminor_version;
uint16_t fw_attributes;
uint16_t fw_attributes_h;
#define FW_ATTR_H_NVME_FBURST BIT_1
#define FW_ATTR_H_NVME BIT_10
#define FW_ATTR_H_NVME_UPDATED BIT_14
/* About firmware SCM support */
#define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
/* Brocade fabric attached */
#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
/* Cisco fabric attached */
#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
#define FW_ATTR_EXT0_NVME2 BIT_13
#define FW_ATTR_EXT0_EDIF BIT_5
uint16_t fw_attributes_ext[2];
uint32_t fw_memory_size;
uint32_t fw_transfer_size;
uint32_t fw_srisc_address;
#define RISC_START_ADDRESS_2100 0x1000
#define RISC_START_ADDRESS_2300 0x800
#define RISC_START_ADDRESS_2400 0x100000
uint16_t orig_fw_tgt_xcb_count;
uint16_t cur_fw_tgt_xcb_count;
uint16_t orig_fw_xcb_count;
uint16_t cur_fw_xcb_count;
uint16_t orig_fw_iocb_count;
uint16_t cur_fw_iocb_count;
uint16_t fw_max_fcf_count;
uint32_t fw_shared_ram_start;
uint32_t fw_shared_ram_end;
uint32_t fw_ddr_ram_start;
uint32_t fw_ddr_ram_end;
uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
uint8_t fw_seriallink_options[4];
__le16 fw_seriallink_options24[4];
uint8_t serdes_version[3];
uint8_t mpi_version[3];
uint32_t mpi_capabilities;
uint8_t phy_version[3];
uint8_t pep_version[3];
/* Firmware dump template */
struct fwdt {
void *template;
ulong length;
ulong dump_size;
} fwdt[2];
struct qla2xxx_fw_dump *fw_dump;
uint32_t fw_dump_len;
u32 fw_dump_alloc_len;
bool fw_dumped;
unsigned long fw_dump_cap_flags;
#define RISC_PAUSE_CMPL 0
#define DMA_SHUTDOWN_CMPL 1
#define ISP_RESET_CMPL 2
#define RISC_RDY_AFT_RESET 3
#define RISC_SRAM_DUMP_CMPL 4
#define RISC_EXT_MEM_DUMP_CMPL 5
#define ISP_MBX_RDY 6
#define ISP_SOFT_RESET_CMPL 7
int fw_dump_reading;
void *mpi_fw_dump;
u32 mpi_fw_dump_len;
unsigned int mpi_fw_dump_reading:1;
unsigned int mpi_fw_dumped:1;
int prev_minidump_failed;
dma_addr_t eft_dma;
void *eft;
/* Current size of mctp dump is 0x086064 bytes */
#define MCTP_DUMP_SIZE 0x086064
dma_addr_t mctp_dump_dma;
void *mctp_dump;
int mctp_dumped;
int mctp_dump_reading;
uint32_t chain_offset;
struct dentry *dfs_dir;
struct dentry *dfs_fce;
struct dentry *dfs_tgt_counters;
struct dentry *dfs_fw_resource_cnt;
dma_addr_t fce_dma;
void *fce;
uint32_t fce_bufs;
uint16_t fce_mb[8];
uint64_t fce_wr, fce_rd;
struct mutex fce_mutex;
uint32_t pci_attr;
uint16_t chip_revision;
uint16_t product_id[4];
uint8_t model_number[16+1];
char model_desc[80];
uint8_t adapter_id[16+1];
/* Option ROM information. */
char *optrom_buffer;
uint32_t optrom_size;
int optrom_state;
#define QLA_SWAITING 0
#define QLA_SREADING 1
#define QLA_SWRITING 2
uint32_t optrom_region_start;
uint32_t optrom_region_size;
struct mutex optrom_mutex;
/* PCI expansion ROM image information. */
#define ROM_CODE_TYPE_BIOS 0
#define ROM_CODE_TYPE_FCODE 1
#define ROM_CODE_TYPE_EFI 3
uint8_t bios_revision[2];
uint8_t efi_revision[2];
uint8_t fcode_revision[16];
uint32_t fw_revision[4];
uint32_t gold_fw_version[4];
/* Offsets for flash/nvram access (set to ~0 if not used). */
uint32_t flash_conf_off;
uint32_t flash_data_off;
uint32_t nvram_conf_off;
uint32_t nvram_data_off;
uint32_t fdt_wrt_disable;
uint32_t fdt_wrt_enable;
uint32_t fdt_erase_cmd;
uint32_t fdt_block_size;
uint32_t fdt_unprotect_sec_cmd;
uint32_t fdt_protect_sec_cmd;
uint32_t fdt_wrt_sts_reg_cmd;
struct {
uint32_t flt_region_flt;
uint32_t flt_region_fdt;
uint32_t flt_region_boot;
uint32_t flt_region_boot_sec;
uint32_t flt_region_fw;
uint32_t flt_region_fw_sec;
uint32_t flt_region_vpd_nvram;
uint32_t flt_region_vpd_nvram_sec;
uint32_t flt_region_vpd;
uint32_t flt_region_vpd_sec;
uint32_t flt_region_nvram;
uint32_t flt_region_nvram_sec;
uint32_t flt_region_npiv_conf;
uint32_t flt_region_gold_fw;
uint32_t flt_region_fcp_prio;
uint32_t flt_region_bootload;
uint32_t flt_region_img_status_pri;
uint32_t flt_region_img_status_sec;
uint32_t flt_region_aux_img_status_pri;
uint32_t flt_region_aux_img_status_sec;
};
uint8_t active_image;
uint8_t active_tmf;
#define MAX_ACTIVE_TMF 8
/* Needed for BEACON */
uint16_t beacon_blink_led;
uint8_t beacon_color_state;
#define QLA_LED_GRN_ON 0x01
#define QLA_LED_YLW_ON 0x02
#define QLA_LED_ABR_ON 0x04
#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
/* ISP2322: red, green, amber. */
uint16_t zio_mode;
uint16_t zio_timer;
struct qla_msix_entry *msix_entries;
struct list_head tmf_pending;
struct list_head tmf_active;
struct list_head vp_list; /* list of VP */
unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
sizeof(unsigned long)];
uint16_t num_vhosts; /* number of vports created */
uint16_t num_vsans; /* number of vsan created */
uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
int cur_vport_count;
struct qla_chip_state_84xx *cs84xx;
struct isp_operations *isp_ops;
struct workqueue_struct *wq;
struct work_struct heartbeat_work;
struct qlfc_fw fw_buf;
unsigned long last_heartbeat_run_jiffies;
/* FCP_CMND priority support */
struct qla_fcp_prio_cfg *fcp_prio_cfg;
struct dma_pool *dl_dma_pool;
#define DSD_LIST_DMA_POOL_SIZE 512
struct dma_pool *fcp_cmnd_dma_pool;
mempool_t *ctx_mempool;
#define FCP_CMND_DMA_POOL_SIZE 512
void __iomem *nx_pcibase; /* Base I/O address */
void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
uint32_t crb_win;
uint32_t curr_window;
uint32_t ddr_mn_window;
unsigned long mn_win_crb;
unsigned long ms_win_crb;
int qdr_sn_window;
uint32_t fcoe_dev_init_timeout;
uint32_t fcoe_reset_timeout;
rwlock_t hw_lock;
uint16_t portnum; /* port number */
int link_width;
struct fw_blob *hablob;
struct qla82xx_legacy_intr_set nx_legacy_intr;
uint16_t gbl_dsd_inuse;
uint16_t gbl_dsd_avail;
struct list_head gbl_dsd_list;
#define NUM_DSD_CHAIN 4096
uint8_t fw_type;
uint32_t file_prd_off; /* File firmware product offset */
uint32_t md_template_size;
void *md_tmplt_hdr;
dma_addr_t md_tmplt_hdr_dma;
void *md_dump;
uint32_t md_dump_size;
void *loop_id_map;
/* QLA83XX IDC specific fields */
uint32_t idc_audit_ts;
uint32_t idc_extend_tmo;
/* DPC low-priority workqueue */
struct workqueue_struct *dpc_lp_wq;
struct work_struct idc_aen;
/* DPC high-priority workqueue */
struct workqueue_struct *dpc_hp_wq;
struct work_struct nic_core_reset;
struct work_struct idc_state_handler;
struct work_struct nic_core_unrecoverable;
struct work_struct board_disable;
struct mr_data_fx00 mr;
uint32_t chip_reset;
struct qlt_hw_data tgt;
int allow_cna_fw_dump;
uint32_t fw_ability_mask;
uint16_t min_supported_speed;
uint16_t max_supported_speed;
/* DMA pool for the DIF bundling buffers */
struct dma_pool *dif_bundl_pool;
#define DIF_BUNDLING_DMA_POOL_SIZE 1024
struct {
struct {
struct list_head head;
uint count;
} good;
struct {
struct list_head head;
uint count;
} unusable;
} pool;
unsigned long long dif_bundle_crossed_pages;
unsigned long long dif_bundle_reads;
unsigned long long dif_bundle_writes;
unsigned long long dif_bundle_kallocs;
unsigned long long dif_bundle_dma_allocs;
atomic_t nvme_active_aen_cnt;
uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
uint8_t fc4_type_priority;
atomic_t zio_threshold;
uint16_t last_zio_threshold;
#define DEFAULT_ZIO_THRESHOLD 5
struct qla_hw_data_stat stat;
pci_error_state_t pci_error_state;
struct dma_pool *purex_dma_pool;
struct btree_head32 host_map;
#define EDIF_NUM_SA_INDEX 512
#define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX
void *edif_rx_sa_id_map;
void *edif_tx_sa_id_map;
spinlock_t sadb_fp_lock;
struct list_head sadb_tx_index_list;
struct list_head sadb_rx_index_list;
spinlock_t sadb_lock; /* protects list */
struct els_reject elsrej;
u8 edif_post_stop_cnt_down;
struct qla_fw_res fwres ____cacheline_aligned;
};
#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
struct active_regions {
uint8_t global;
struct {
uint8_t board_config;
uint8_t vpd_nvram;
uint8_t npiv_config_0_1;
uint8_t npiv_config_2_3;
uint8_t nvme_params;
} aux;
};
#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
#define FW_ABILITY_MAX_SPEED_16G 0x0
#define FW_ABILITY_MAX_SPEED_32G 0x1
#define FW_ABILITY_MAX_SPEED(ha) \
(ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
#define QLA_GET_DATA_RATE 0
#define QLA_SET_DATA_RATE_NOLR 1
#define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
#define QLA_DEFAULT_PAYLOAD_SIZE 64
/*
* This item might be allocated with a size > sizeof(struct purex_item).
* The "size" variable gives the size of the payload (which
* is variable) starting at "iocb".
*/
struct purex_item {
struct list_head list;
struct scsi_qla_host *vha;
void (*process_item)(struct scsi_qla_host *vha,
struct purex_item *pkt);
atomic_t in_use;
uint16_t size;
struct {
uint8_t iocb[64];
} iocb;
};
#include "qla_edif.h"
#define SCM_FLAG_RDF_REJECT 0x00
#define SCM_FLAG_RDF_COMPLETED 0x01
#define QLA_CON_PRIMITIVE_RECEIVED 0x1
#define QLA_CONGESTION_ARB_WARNING 0x1
#define QLA_CONGESTION_ARB_ALARM 0X2
/*
* Qlogic scsi host structure
*/
typedef struct scsi_qla_host {
struct list_head list;
struct list_head vp_fcports; /* list of fcports */
struct list_head work_list;
spinlock_t work_lock;
struct work_struct iocb_work;
/* Commonly used flags and state information. */
struct Scsi_Host *host;
unsigned long host_no;
uint8_t host_str[16];
volatile struct {
uint32_t init_done :1;
uint32_t online :1;
uint32_t reset_active :1;
uint32_t management_server_logged_in :1;
uint32_t process_response_queue :1;
uint32_t difdix_supported:1;
uint32_t delete_progress:1;
uint32_t fw_tgt_reported:1;
uint32_t bbcr_enable:1;
uint32_t qpairs_available:1;
uint32_t qpairs_req_created:1;
uint32_t qpairs_rsp_created:1;
uint32_t nvme_enabled:1;
uint32_t nvme_first_burst:1;
uint32_t nvme2_enabled:1;
} flags;
atomic_t loop_state;
#define LOOP_TIMEOUT 1
#define LOOP_DOWN 2
#define LOOP_UP 3
#define LOOP_UPDATE 4
#define LOOP_READY 5
#define LOOP_DEAD 6
unsigned long relogin_jif;
unsigned long dpc_flags;
#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
#define RESET_ACTIVE 1
#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
#define LOOP_RESYNC_ACTIVE 5
#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
#define RSCN_UPDATE 7 /* Perform an RSCN update. */
#define RELOGIN_NEEDED 8
#define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
#define ISP_ABORT_RETRY 10 /* ISP aborted. */
#define BEACON_BLINK_NEEDED 11
#define REGISTER_FDMI_NEEDED 12
#define FCPORT_UPDATE_NEEDED 13
#define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
#define UNLOADING 15
#define NPIV_CONFIG_NEEDED 16
#define ISP_UNRECOVERABLE 17
#define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
#define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
#define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
#define N2N_LINK_RESET 21
#define PORT_UPDATE_NEEDED 22
#define FX00_RESET_RECOVERY 23
#define FX00_TARGET_SCAN 24
#define FX00_CRITEMP_RECOVERY 25
#define FX00_HOST_INFO_RESEND 26
#define QPAIR_ONLINE_CHECK_NEEDED 27
#define DO_EEH_RECOVERY 28
#define DETECT_SFP_CHANGE 29
#define N2N_LOGIN_NEEDED 30
#define IOCB_WORK_ACTIVE 31
#define SET_ZIO_THRESHOLD_NEEDED 32
#define ISP_ABORT_TO_ROM 33
#define VPORT_DELETE 34
#define PROCESS_PUREX_IOCB 63
unsigned long pci_flags;
#define PFLG_DISCONNECTED 0 /* PCI device removed */
#define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
#define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
uint32_t device_flags;
#define SWITCH_FOUND BIT_0
#define DFLG_NO_CABLE BIT_1
#define DFLG_DEV_FAILED BIT_5
/* ISP configuration data. */
uint16_t loop_id; /* Host adapter loop id */
uint16_t self_login_loop_id; /* host adapter loop id
* get it on self login
*/
fc_port_t bidir_fcport; /* fcport used for bidir cmnds
* no need of allocating it for
* each command
*/
port_id_t d_id; /* Host adapter port id */
uint8_t marker_needed;
uint16_t mgmt_svr_loop_id;
/* Timeout timers. */
uint8_t loop_down_abort_time; /* port down timer */
atomic_t loop_down_timer; /* loop down timer */
uint8_t link_down_timeout; /* link down timeout */
uint32_t timer_active;
struct timer_list timer;
uint8_t node_name[WWN_SIZE];
uint8_t port_name[WWN_SIZE];
uint8_t fabric_node_name[WWN_SIZE];
uint8_t fabric_port_name[WWN_SIZE];
struct nvme_fc_local_port *nvme_local_port;
struct completion nvme_del_done;
uint16_t fcoe_vlan_id;
uint16_t fcoe_fcf_idx;
uint8_t fcoe_vn_port_mac[6];
/* list of commands waiting on workqueue */
struct list_head qla_cmd_list;
struct list_head unknown_atio_list;
spinlock_t cmd_list_lock;
struct delayed_work unknown_atio_work;
/* Counter to detect races between ELS and RSCN events */
atomic_t generation_tick;
/* Time when global fcport update has been scheduled */
int total_fcport_update_gen;
/* List of pending LOGOs, protected by tgt_mutex */
struct list_head logo_list;
/* List of pending PLOGI acks, protected by hw lock */
struct list_head plogi_ack_list;
struct list_head qp_list;
uint32_t vp_abort_cnt;
struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
uint16_t vp_idx; /* vport ID */
struct qla_qpair *qpair; /* base qpair */
unsigned long vp_flags;
#define VP_IDX_ACQUIRED 0 /* bit no 0 */
#define VP_CREATE_NEEDED 1
#define VP_BIND_NEEDED 2
#define VP_DELETE_NEEDED 3
#define VP_SCR_NEEDED 4 /* State Change Request registration */
#define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
atomic_t vp_state;
#define VP_OFFLINE 0
#define VP_ACTIVE 1
#define VP_FAILED 2
// #define VP_DISABLE 3
uint16_t vp_err_state;
uint16_t vp_prev_err_state;
#define VP_ERR_UNKWN 0
#define VP_ERR_PORTDWN 1
#define VP_ERR_FAB_UNSUPPORTED 2
#define VP_ERR_FAB_NORESOURCES 3
#define VP_ERR_FAB_LOGOUT 4
#define VP_ERR_ADAP_NORESOURCES 5
struct qla_hw_data *hw;
struct scsi_qlt_host vha_tgt;
struct req_que *req;
int fw_heartbeat_counter;
int seconds_since_last_heartbeat;
struct fc_host_statistics fc_host_stat;
struct qla_statistics qla_stats;
struct bidi_statistics bidi_stats;
atomic_t vref_count;
struct qla8044_reset_template reset_tmplt;
uint16_t bbcr;
uint16_t u_ql2xexchoffld;
uint16_t u_ql2xiniexchg;
uint16_t qlini_mode;
uint16_t ql2xexchoffld;
uint16_t ql2xiniexchg;
struct dentry *dfs_rport_root;
struct purex_list {
struct list_head head;
spinlock_t lock;
} purex_list;
struct purex_item default_item;
struct name_list_extended gnl;
/* Count of active session/fcport */
int fcport_count;
wait_queue_head_t fcport_waitQ;
wait_queue_head_t vref_waitq;
uint8_t min_supported_speed;
uint8_t n2n_node_name[WWN_SIZE];
uint8_t n2n_port_name[WWN_SIZE];
uint16_t n2n_id;
__le16 dport_data[4];
struct list_head gpnid_list;
struct fab_scan scan;
uint8_t scm_fabric_connection_flags;
unsigned int irq_offset;
u64 hw_err_cnt;
u64 interface_err_cnt;
u64 cmd_timeout_cnt;
u64 reset_cmd_err_cnt;
u64 link_down_time;
u64 short_link_down_cnt;
struct edif_dbell e_dbell;
struct pur_core pur_cinfo;
#define DPORT_DIAG_IN_PROGRESS BIT_0
#define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1
uint16_t dport_status;
} scsi_qla_host_t;
struct qla27xx_image_status {
uint8_t image_status_mask;
__le16 generation;
uint8_t ver_major;
uint8_t ver_minor;
uint8_t bitmap; /* 28xx only */
uint8_t reserved[2];
__le32 checksum;
__le32 signature;
} __packed;
/* 28xx aux image status bimap values */
#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
#define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4
#define SET_VP_IDX 1
#define SET_AL_PA 2
#define RESET_VP_IDX 3
#define RESET_AL_PA 4
struct qla_tgt_vp_map {
uint8_t idx;
scsi_qla_host_t *vha;
};
struct qla2_sgx {
dma_addr_t dma_addr; /* OUT */
uint32_t dma_len; /* OUT */
uint32_t tot_bytes; /* IN */
struct scatterlist *cur_sg; /* IN */
/* for book keeping, bzero on initial invocation */
uint32_t bytes_consumed;
uint32_t num_bytes;
uint32_t tot_partial;
/* for debugging */
uint32_t num_sg;
srb_t *sp;
};
#define QLA_FW_STARTED(_ha) { \
int i; \
_ha->flags.fw_started = 1; \
_ha->base_qpair->fw_started = 1; \
for (i = 0; i < _ha->max_qpairs; i++) { \
if (_ha->queue_pair_map[i]) \
_ha->queue_pair_map[i]->fw_started = 1; \
} \
}
#define QLA_FW_STOPPED(_ha) { \
int i; \
_ha->flags.fw_started = 0; \
_ha->base_qpair->fw_started = 0; \
for (i = 0; i < _ha->max_qpairs; i++) { \
if (_ha->queue_pair_map[i]) \
_ha->queue_pair_map[i]->fw_started = 0; \
} \
}
#define SFUB_CHECKSUM_SIZE 4
struct secure_flash_update_block {
uint32_t block_info;
uint32_t signature_lo;
uint32_t signature_hi;
uint32_t signature_upper[0x3e];
};
struct secure_flash_update_block_pk {
uint32_t block_info;
uint32_t signature_lo;
uint32_t signature_hi;
uint32_t signature_upper[0x3e];
uint32_t public_key[0x41];
};
/*
* Macros to help code, maintain, etc.
*/
#define LOOP_TRANSITION(ha) \
(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
atomic_read(&ha->loop_state) == LOOP_DOWN)
#define STATE_TRANSITION(ha) \
(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha)
{
atomic_inc(&vha->vref_count);
mb();
if (vha->flags.delete_progress) {
atomic_dec(&vha->vref_count);
wake_up(&vha->vref_waitq);
return true;
}
return false;
}
#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
atomic_dec(&__vha->vref_count); \
wake_up(&__vha->vref_waitq); \
} while (0) \
#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
atomic_inc(&__qpair->ref_count); \
mb(); \
if (__qpair->delete_in_progress) { \
atomic_dec(&__qpair->ref_count); \
__bail = 1; \
} else { \
__bail = 0; \
} \
} while (0)
#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
atomic_dec(&__qpair->ref_count)
#define QLA_ENA_CONF(_ha) {\
int i;\
_ha->base_qpair->enable_explicit_conf = 1; \
for (i = 0; i < _ha->max_qpairs; i++) { \
if (_ha->queue_pair_map[i]) \
_ha->queue_pair_map[i]->enable_explicit_conf = 1; \
} \
}
#define QLA_DIS_CONF(_ha) {\
int i;\
_ha->base_qpair->enable_explicit_conf = 0; \
for (i = 0; i < _ha->max_qpairs; i++) { \
if (_ha->queue_pair_map[i]) \
_ha->queue_pair_map[i]->enable_explicit_conf = 0; \
} \
}
/*
* qla2x00 local function return status codes
*/
#define MBS_MASK 0x3fff
#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
#define QLA_FUNCTION_TIMEOUT 0x100
#define QLA_FUNCTION_PARAMETER_ERROR 0x101
#define QLA_FUNCTION_FAILED 0x102
#define QLA_MEMORY_ALLOC_FAILED 0x103
#define QLA_LOCK_TIMEOUT 0x104
#define QLA_ABORTED 0x105
#define QLA_SUSPENDED 0x106
#define QLA_BUSY 0x107
#define QLA_ALREADY_REGISTERED 0x109
#define QLA_OS_TIMER_EXPIRED 0x10a
#define QLA_ERR_NO_QPAIR 0x10b
#define QLA_ERR_NOT_FOUND 0x10c
#define QLA_ERR_FROM_FW 0x10d
#define NVRAM_DELAY() udelay(10)
/*
* Flash support definitions
*/
#define OPTROM_SIZE_2300 0x20000
#define OPTROM_SIZE_2322 0x100000
#define OPTROM_SIZE_24XX 0x100000
#define OPTROM_SIZE_25XX 0x200000
#define OPTROM_SIZE_81XX 0x400000
#define OPTROM_SIZE_82XX 0x800000
#define OPTROM_SIZE_83XX 0x1000000
#define OPTROM_SIZE_28XX 0x2000000
#define OPTROM_BURST_SIZE 0x1000
#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
#define QLA_DSDS_PER_IOCB 37
#define QLA_SG_ALL 1024
enum nexus_wait_type {
WAIT_HOST = 0,
WAIT_TARGET,
WAIT_LUN,
};
#define INVALID_EDIF_SA_INDEX 0xffff
#define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe
#define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE
/* edif hash element */
struct edif_list_entry {
uint16_t handle; /* nport_handle */
uint32_t update_sa_index;
uint32_t delete_sa_index;
uint32_t count; /* counter for filtering sa_index */
#define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */
uint32_t flags; /* used by sadb cleanup code */
fc_port_t *fcport; /* needed by rx delay timer function */
struct timer_list timer; /* rx delay timer */
struct list_head next;
};
#define EDIF_TX_INDX_BASE 512
#define EDIF_RX_INDX_BASE 0
#define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */
/* entry in the sa_index free pool */
struct sa_index_pair {
uint16_t sa_index;
uint32_t spi;
};
/* edif sa_index data structure */
struct edif_sa_index_entry {
struct sa_index_pair sa_pair[2];
fc_port_t *fcport;
uint16_t handle;
struct list_head next;
};
/* Refer to SNIA SFF 8247 */
struct sff_8247_a0 {
u8 txid; /* transceiver id */
u8 ext_txid;
u8 connector;
/* compliance code */
u8 eth_infi_cc3; /* ethernet, inifiband */
u8 sonet_cc4[2];
u8 eth_cc6;
/* link length */
#define FC_LL_VL BIT_7 /* very long */
#define FC_LL_S BIT_6 /* Short */
#define FC_LL_I BIT_5 /* Intermidiate*/
#define FC_LL_L BIT_4 /* Long */
#define FC_LL_M BIT_3 /* Medium */
#define FC_LL_SA BIT_2 /* ShortWave laser */
#define FC_LL_LC BIT_1 /* LongWave laser */
#define FC_LL_EL BIT_0 /* Electrical inter enclosure */
u8 fc_ll_cc7;
/* FC technology */
#define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
#define FC_TEC_SN BIT_6 /* short wave w/o OFC */
#define FC_TEC_SL BIT_5 /* short wave with OFC */
#define FC_TEC_LL BIT_4 /* Longwave Laser */
#define FC_TEC_ACT BIT_3 /* Active cable */
#define FC_TEC_PAS BIT_2 /* Passive cable */
u8 fc_tec_cc8;
/* Transmission Media */
#define FC_MED_TW BIT_7 /* Twin Ax */
#define FC_MED_TP BIT_6 /* Twited Pair */
#define FC_MED_MI BIT_5 /* Min Coax */
#define FC_MED_TV BIT_4 /* Video Coax */
#define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
#define FC_MED_M5 BIT_2 /* Multimode, 50um */
#define FC_MED_SM BIT_0 /* Single Mode */
u8 fc_med_cc9;
/* speed FC_SP_12: 12*100M = 1200 MB/s */
#define FC_SP_12 BIT_7
#define FC_SP_8 BIT_6
#define FC_SP_16 BIT_5
#define FC_SP_4 BIT_4
#define FC_SP_32 BIT_3
#define FC_SP_2 BIT_2
#define FC_SP_1 BIT_0
u8 fc_sp_cc10;
u8 encode;
u8 bitrate;
u8 rate_id;
u8 length_km; /* offset 14/eh */
u8 length_100m;
u8 length_50um_10m;
u8 length_62um_10m;
u8 length_om4_10m;
u8 length_om3_10m;
#define SFF_VEN_NAME_LEN 16
u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
u8 tx_compat;
u8 vendor_oui[3];
#define SFF_PART_NAME_LEN 16
u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
u8 vendor_rev[4];
u8 wavelength[2];
u8 resv;
u8 cc_base;
u8 options[2]; /* offset 64 */
u8 br_max;
u8 br_min;
u8 vendor_sn[16];
u8 date_code[8];
u8 diag;
u8 enh_options;
u8 sff_revision;
u8 cc_ext;
u8 vendor_specific[32];
u8 resv2[128];
};
/* BPM -- Buffer Plus Management support. */
#define IS_BPM_CAPABLE(ha) \
(IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_BPM_RANGE_CAPABLE(ha) \
(IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_BPM_ENABLED(vha) \
(ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
(IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
#define SAVE_TOPO(_ha) { \
if (_ha->current_topology) \
_ha->prev_topology = _ha->current_topology; \
}
#define N2N_TOPO(ha) \
((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
ha->current_topology == ISP_CFG_N || \
!ha->current_topology)
#define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
#define NVME_TYPE(fcport) \
(fcport->fc4_type & FS_FC4TYPE_NVME) \
#define FCP_TYPE(fcport) \
(fcport->fc4_type & FS_FC4TYPE_FCP) \
#define NVME_ONLY_TARGET(fcport) \
(NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
#define NVME_FCP_TARGET(fcport) \
(FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
#define NVME_PRIORITY(ha, fcport) \
(NVME_FCP_TARGET(fcport) && \
(ha->fc4_type_priority == FC4_PRIORITY_NVME))
#define NVME_TARGET(ha, fcport) \
(fcport->do_prli_nvme || \
NVME_ONLY_TARGET(fcport)) \
#define PRLI_PHASE(_cls) \
((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
enum ql_vnd_host_stat_action {
QLA_STOP = 0,
QLA_START,
QLA_CLEAR,
};
struct ql_vnd_mng_host_stats_param {
u32 stat_type;
enum ql_vnd_host_stat_action action;
} __packed;
struct ql_vnd_mng_host_stats_resp {
u32 status;
} __packed;
struct ql_vnd_stats_param {
u32 stat_type;
} __packed;
struct ql_vnd_tgt_stats_param {
s32 tgt_id;
u32 stat_type;
} __packed;
enum ql_vnd_host_port_action {
QLA_ENABLE = 0,
QLA_DISABLE,
};
struct ql_vnd_mng_host_port_param {
enum ql_vnd_host_port_action action;
} __packed;
struct ql_vnd_mng_host_port_resp {
u32 status;
} __packed;
struct ql_vnd_stat_entry {
u32 stat_type; /* Failure type */
u32 tgt_num; /* Target Num */
u64 cnt; /* Counter value */
} __packed;
struct ql_vnd_stats {
u64 entry_count; /* Num of entries */
u64 rservd;
struct ql_vnd_stat_entry entry[]; /* Place holder of entries */
} __packed;
struct ql_vnd_host_stats_resp {
u32 status;
struct ql_vnd_stats stats;
} __packed;
struct ql_vnd_tgt_stats_resp {
u32 status;
struct ql_vnd_stats stats;
} __packed;
#include "qla_target.h"
#include "qla_gbl.h"
#include "qla_dbg.h"
#include "qla_inline.h"
#define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \
_fcport->disc_state == DSC_DELETED)
#define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \
"%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \
__func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \
_fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \
_fp->flags
#define TMF_NOT_READY(_fcport) \
(!_fcport || IS_SESSION_DELETED(_fcport) || atomic_read(&_fcport->state) != FCS_ONLINE || \
!_fcport->vha->hw->flags.fw_started)
#endif
|