From 7b6e527f440cd7e6f8be2b07cee320ee6ca18786 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Mon, 29 Apr 2024 06:41:38 +0200 Subject: Adding upstream version 1.0.1. Signed-off-by: Daniel Baumann --- test cases/fpga/1 simple/meson.build | 8 ++++++++ test cases/fpga/1 simple/spin.pcf | 6 ++++++ test cases/fpga/1 simple/spin.v | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) create mode 100644 test cases/fpga/1 simple/meson.build create mode 100644 test cases/fpga/1 simple/spin.pcf create mode 100644 test cases/fpga/1 simple/spin.v (limited to 'test cases/fpga') diff --git a/test cases/fpga/1 simple/meson.build b/test cases/fpga/1 simple/meson.build new file mode 100644 index 0000000..536244e --- /dev/null +++ b/test cases/fpga/1 simple/meson.build @@ -0,0 +1,8 @@ +project('lattice', 'c') + +is = import('unstable-icestorm') + +is.project('spin', + 'spin.v', + constraint_file : 'spin.pcf', +) diff --git a/test cases/fpga/1 simple/spin.pcf b/test cases/fpga/1 simple/spin.pcf new file mode 100644 index 0000000..de06f5d --- /dev/null +++ b/test cases/fpga/1 simple/spin.pcf @@ -0,0 +1,6 @@ +set_io LED1 99 +set_io LED2 98 +set_io LED3 97 +set_io LED4 96 +set_io LED5 95 +set_io clk 21 diff --git a/test cases/fpga/1 simple/spin.v b/test cases/fpga/1 simple/spin.v new file mode 100644 index 0000000..2143d30 --- /dev/null +++ b/test cases/fpga/1 simple/spin.v @@ -0,0 +1,32 @@ + +module top(input clk, output LED1, output LED2, output LED3, output LED4, output LED5); + + reg ready = 0; + reg [23:0] divider; + reg [3:0] spin; + + always @(posedge clk) begin + if (ready) + begin + if (divider == 6000000) + begin + divider <= 0; + spin <= {spin[2], spin[3], spin[0], spin[1]}; + end + else + divider <= divider + 1; + end + else + begin + ready <= 1; + spin <= 4'b1010; + divider <= 0; + end + end + + assign LED1 = spin[0]; + assign LED2 = spin[1]; + assign LED3 = spin[2]; + assign LED4 = spin[3]; + assign LED5 = 1; +endmodule -- cgit v1.2.3