diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:24:33 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:24:33 +0000 |
commit | 7a19c99f661602b67db95fd1d8aca5fe3a387441 (patch) | |
tree | 215ff04ec522779fa83acf394d296c2356c6b382 /tests/cap-pcie-1 | |
parent | Initial commit. (diff) | |
download | pciutils-7a19c99f661602b67db95fd1d8aca5fe3a387441.tar.xz pciutils-7a19c99f661602b67db95fd1d8aca5fe3a387441.zip |
Adding upstream version 1:3.9.0.upstream/1%3.9.0upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tests/cap-pcie-1')
-rw-r--r-- | tests/cap-pcie-1 | 312 |
1 files changed, 312 insertions, 0 deletions
diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1 new file mode 100644 index 0000000..b69184f --- /dev/null +++ b/tests/cap-pcie-1 @@ -0,0 +1,312 @@ +00:01.0 PCI bridge: Intel Corporation QuickPath Architecture I/O Hub PCI Express Root Port 1 (rev 12) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- + Latency: 0, Cache Line Size: 64 bytes + Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 + I/O behind bridge: 00001000-00001fff + Memory behind bridge: e0000000-e09fffff + Prefetchable memory behind bridge: 00000000c7800000-00000000c7ffffff + Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- + BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Subsystem: Intel Corporation Device 4f53 + Capabilities: [60] MSI: Mask+ 64bit- Count=1/2 Enable- + Address: 00000020 Data: 0000 + Masking: 00000000 Pending: 00000000 + Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us + ExtTag+ RBE+ FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 256 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- + LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us + ClockPM- Surprise+ LLActRep+ BwNot+ + LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- + SltCap: AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surprise- + Slot # 40, PowerLimit 0.000000; Interlock+ NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- + Control: AttnInd Off, PwrInd Off, Power+ Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet+ LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ + DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis+ ARIFwd+ + LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance+ SpeedDis-, Selectable De-emphasis: -6dB + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance De-emphasis: -6dB + LnkSta2: Current De-emphasis Level: -6dB + Capabilities: [e0] Power Management version 3 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ + AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + Capabilities: [150] Access Control Services + ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- + ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + Capabilities: [160] Vendor Specific Information <?> +00: 86 80 08 34 47 01 10 00 12 00 04 06 10 00 01 00 +10: 00 00 00 00 00 00 00 00 00 01 01 00 10 10 00 00 +20: 00 e0 90 e0 81 c7 f1 c7 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 +40: 0d 60 00 00 86 80 53 4f 00 00 00 00 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