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path: root/tests/cap-exp-dev2
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diff --git a/tests/cap-exp-dev2 b/tests/cap-exp-dev2
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+00:1c.0 Class 0604: Device 8086:9d10 (rev f1)
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 255
+ Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
+ I/O behind bridge: None
+ Memory behind bridge: f1100000-f11fffff [size=1M]
+ Prefetchable memory behind bridge: None
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity- SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
+ LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us
+ ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s (downgraded), Width x1 (ok)
+ TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState+
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+
+ AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
+ AtomicOpsCtl: ReqEn- EgressBlck-
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit-
+ Address: 00000000 Data: 0000
+ Capabilities: [90] Subsystem: Device 17aa:2238
+ Capabilities: [a0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ RootCmd: CERptEn- NFERptEn- FERptEn-
+ RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
+ FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
+ ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
+ Capabilities: [140 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Capabilities: [200 v1] L1 PM Substates
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
+ T_CommonMode=60us LTR1.2_Threshold=163840ns
+ L1SubCtl2: T_PwrOn=60us
+ Capabilities: [220 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+ LaneErrStat: 0
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