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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
| commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
| tree | a94efe259b9009378be6d90eb30d2b019d95c194 /tools/perf/pmu-events/arch/x86/broadwellx/other.json | |
| parent | Initial commit. (diff) | |
| download | linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.tar.xz linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.zip | |
Adding upstream version 5.10.209.upstream/5.10.209
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellx/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellx/other.json | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json new file mode 100644 index 000000000..4475249ea --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -0,0 +1,44 @@ +[ + { + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterMask": "1", + "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x1", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
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