// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. */ #include #include #include / { compatible = "microchip,sparx5"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <1>; aliases { spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; }; chosen { stdout-path = "serial0:115200n8"; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; }; }; arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; interrupt-affinity = <&cpu0>, <&cpu1>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; lcpll_clk: lcpll-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <2500000000>; }; clks: clock-controller@61110000c { compatible = "microchip,sparx5-dpll"; #clock-cells = <1>; clocks = <&lcpll_clk>; reg = <0x6 0x1110000c 0x24>; }; ahb_clk: ahb-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; sys_clk: sys-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <625000000>; }; axi: axi@600000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges; gic: interrupt-controller@600300000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; interrupt-controller; reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ <0x6 0x00340000 0xc0000>, /* GICR */ <0x6 0x00200000 0x2000>, /* GICC */ <0x6 0x00210000 0x2000>, /* GICV */ <0x6 0x00220000 0x2000>; /* GICH */ interrupts = ; }; cpu_ctrl: syscon@600000000 { compatible = "microchip,sparx5-cpu-syscon", "syscon", "simple-mfd"; reg = <0x6 0x00000000 0xd0>; mux: mux-controller { compatible = "mmio-mux"; #mux-control-cells = <0>; /* * SI_OWNER and SI2_OWNER in GENERAL_CTRL * SPI: value 9 - (SIMC,SIBM) = 0b1001 * SPI2: value 6 - (SIBM,SIMC) = 0b0110 */ mux-reg-masks = <0x88 0xf0>; }; }; uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; reg-io-width = <4>; reg-shift = <2>; interrupts = ; status = "disabled"; }; uart1: serial@600102000 { pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; reg-io-width = <4>; reg-shift = <2>; interrupts = ; status = "disabled"; }; spi0: spi@600104000 { #address-cells = <1>; #size-cells = <0>; compatible = "microchip,sparx5-spi"; reg = <0x6 0x00104000 0x40>; num-cs = <16>; reg-io-width = <4>; reg-shift = <2>; clocks = <&ahb_clk>; interrupts = ; status = "disabled"; }; timer1: timer@600105000 { compatible = "snps,dw-apb-timer"; reg = <0x6 0x00105000 0x1000>; clocks = <&ahb_clk>; clock-names = "timer"; interrupts = ; }; sdhci0: mmc@600800000 { compatible = "microchip,dw-sparx5-sdhci"; status = "disabled"; reg = <0x6 0x00800000 0x1000>; pinctrl-0 = <&emmc_pins>; pinctrl-names = "default"; clocks = <&clks CLK_ID_AUX1>; clock-names = "core"; assigned-clocks = <&clks CLK_ID_AUX1>; assigned-clock-rates = <800000000>; interrupts = ; bus-width = <8>; }; gpio: pinctrl@6110101e0 { compatible = "microchip,sparx5-pinctrl"; reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 64>; interrupt-controller; interrupts = ; #interrupt-cells = <2>; cs1_pins: cs1-pins { pins = "GPIO_16"; function = "si"; }; cs2_pins: cs2-pins { pins = "GPIO_17"; function = "si"; }; cs3_pins: cs3-pins { pins = "GPIO_18"; function = "si"; }; si2_pins: si2-pins { pins = "GPIO_39", "GPIO_40", "GPIO_41"; function = "si2"; }; uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; }; uart2_pins: uart2-pins { pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; i2c_pins: i2c-pins { pins = "GPIO_14", "GPIO_15"; function = "twi"; }; i2c2_pins: i2c2-pins { pins = "GPIO_28", "GPIO_29"; function = "twi2"; }; emmc_pins: emmc-pins { pins = "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41", "GPIO_42", "GPIO_43", "GPIO_44", "GPIO_45", "GPIO_46", "GPIO_47"; function = "emmc"; }; }; i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; pinctrl-0 = <&i2c_pins>; pinctrl-names = "default"; reg = <0x6 0x00101000 0x100>; #address-cells = <1>; #size-cells = <0>; interrupts = ; i2c-sda-hold-time-ns = <300>; clock-frequency = <100000>; clocks = <&ahb_clk>; }; i2c1: i2c@600103000 { compatible = "snps,designware-i2c"; status = "disabled"; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; reg = <0x6 0x00103000 0x100>; #address-cells = <1>; #size-cells = <0>; interrupts = ; i2c-sda-hold-time-ns = <300>; clock-frequency = <100000>; clocks = <&ahb_clk>; }; tmon0: tmon@610508110 { compatible = "microchip,sparx5-temp"; reg = <0x6 0x10508110 0xc>; #thermal-sensor-cells = <0>; clocks = <&ahb_clk>; }; }; };