blob: c81dbc3e89601e34fca766c9b0ea55427d115702 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Hantro G1 VPU codecs implemented on Rockchip SoCs
maintainers:
- Ezequiel Garcia <ezequiel@collabora.com>
description:
Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
properties:
compatible:
enum:
- rockchip,rk3288-vpu
- rockchip,rk3328-vpu
- rockchip,rk3399-vpu
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
oneOf:
- const: vdpu
- items:
- const: vepu
- const: vdpu
clocks:
maxItems: 2
clock-names:
items:
- const: aclk
- const: hclk
power-domains:
maxItems: 1
iommus:
maxItems: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3288-power.h>
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0xff9a0000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIDEO>;
iommus = <&vpu_mmu>;
};
|