1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QCA AR71XX MAC
allOf:
- $ref: ethernet-controller.yaml#
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
properties:
compatible:
oneOf:
- items:
- enum:
- qca,ar7100-eth # Atheros AR7100
- qca,ar7240-eth # Atheros AR7240
- qca,ar7241-eth # Atheros AR7241
- qca,ar7242-eth # Atheros AR7242
- qca,ar9130-eth # Atheros AR9130
- qca,ar9330-eth # Atheros AR9330
- qca,ar9340-eth # Atheros AR9340
- qca,qca9530-eth # Qualcomm Atheros QCA9530
- qca,qca9550-eth # Qualcomm Atheros QCA9550
- qca,qca9560-eth # Qualcomm Atheros QCA9560
reg:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
description: number of address cells for the MDIO bus
const: 1
'#size-cells':
description: number of size cells on the MDIO bus
const: 0
clocks:
items:
- description: MAC main clock
- description: MDIO clock
clock-names:
items:
- const: eth
- const: mdio
resets:
items:
- description: MAC reset
- description: MDIO reset
reset-names:
items:
- const: mac
- const: mdio
required:
- compatible
- reg
- interrupts
- phy-mode
- clocks
- clock-names
- resets
- reset-names
unevaluatedProperties: false
examples:
# Lager board
- |
eth0: ethernet@19000000 {
compatible = "qca,ar9330-eth";
reg = <0x19000000 0x200>;
interrupts = <4>;
resets = <&rst 9>, <&rst 22>;
reset-names = "mac", "mdio";
clocks = <&pll 1>, <&pll 2>;
clock-names = "eth", "mdio";
qca,ethcfg = <ðcfg>;
phy-mode = "mii";
phy-handle = <&phy_port4>;
};
eth1: ethernet@1a000000 {
compatible = "qca,ar9330-eth";
reg = <0x1a000000 0x200>;
interrupts = <5>;
resets = <&rst 13>, <&rst 23>;
reset-names = "mac", "mdio";
clocks = <&pll 1>, <&pll 2>;
clock-names = "eth", "mdio";
phy-mode = "gmii";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch10: switch@10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qca,ar9331-switch";
reg = <0x10>;
resets = <&rst 8>;
reset-names = "switch";
interrupt-parent = <&miscintc>;
interrupts = <12>;
interrupt-controller;
#interrupt-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch_port0: port@0 {
reg = <0x0>;
label = "cpu";
ethernet = <ð1>;
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch_port1: port@1 {
reg = <0x1>;
phy-handle = <&phy_port0>;
phy-mode = "internal";
status = "disabled";
};
switch_port2: port@2 {
reg = <0x2>;
phy-handle = <&phy_port1>;
phy-mode = "internal";
status = "disabled";
};
switch_port3: port@3 {
reg = <0x3>;
phy-handle = <&phy_port2>;
phy-mode = "internal";
status = "disabled";
};
switch_port4: port@4 {
reg = <0x4>;
phy-handle = <&phy_port3>;
phy-mode = "internal";
status = "disabled";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&switch10>;
phy_port0: phy@0 {
reg = <0x0>;
interrupts = <0>;
status = "disabled";
};
phy_port1: phy@1 {
reg = <0x1>;
interrupts = <0>;
status = "disabled";
};
phy_port2: phy@2 {
reg = <0x2>;
interrupts = <0>;
status = "disabled";
};
phy_port3: phy@3 {
reg = <0x3>;
interrupts = <0>;
status = "disabled";
};
phy_port4: phy@4 {
reg = <0x4>;
interrupts = <0>;
status = "disabled";
};
};
};
};
};
|
