blob: 9047ec6bd3cf82dceffd67e3d2d2bfc318e6a55b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for SERDES MUX for TI SoCs
*/
#ifndef _DT_BINDINGS_MUX_TI_SERDES
#define _DT_BINDINGS_MUX_TI_SERDES
/* J721E */
#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
#define J721E_SERDES0_LANE1_USB3_0 0x2
#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
#define J721E_SERDES1_LANE1_USB3_1 0x2
#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
#define J721E_SERDES2_LANE1_USB3_1 0x2
#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
#define J721E_SERDES3_LANE1_USB3_0 0x2
#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
/* J7200 */
#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
#define J7200_SERDES0_LANE3_USB 0x2
#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
|
