diff options
Diffstat (limited to 'tests/expected/lscpu/lscpu-vmware_fpe')
| -rw-r--r-- | tests/expected/lscpu/lscpu-vmware_fpe | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-vmware_fpe b/tests/expected/lscpu/lscpu-vmware_fpe new file mode 100644 index 0000000..2b68db2 --- /dev/null +++ b/tests/expected/lscpu/lscpu-vmware_fpe @@ -0,0 +1,76 @@ +CPU op-mode(s): 32-bit, 64-bit +Address sizes: 48 bits physical, 48 bits virtual +CPU(s): 16 +On-line CPU(s) list: 0-15 +Thread(s) per core: 2 +Core(s) per socket: 4 +Socket(s): 2 +NUMA node(s): 4 +Vendor ID: AuthenticAMD +CPU family: 21 +Model: 2 +Model name: AMD Opteron(tm) Processor 6328 +Stepping: 0 +Frequency boost: enabled +CPU MHz: 1605.776 +CPU max MHz: 3200.0000 +CPU min MHz: 1400.0000 +BogoMIPS: 6399.69 +Virtualization: AMD-V +L1d cache: 128 KiB +L1i cache: 512 KiB +L2 cache: 16 MiB +L3 cache: 24 MiB +NUMA node0 CPU(s): 0-3 +NUMA node1 CPU(s): 4-7 +NUMA node2 CPU(s): 8-11 +NUMA node3 CPU(s): 12-15 +Vulnerability L1tf: Not affected +Vulnerability Mds: Not affected +Vulnerability Meltdown: Not affected +Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp +Vulnerability Spectre v1: Mitigation; __user pointer sanitization +Vulnerability Spectre v2: Mitigation; Full AMD retpoline, IBPB conditional, STIBP disabled, RSB filling +Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid amd_dcm aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate ssbd ibpb vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,0,0,0,,1,0,0,0 +2,1,0,0,,2,1,1,0 +3,1,0,0,,3,1,1,0 +4,2,0,1,,4,2,2,1 +5,2,0,1,,5,2,2,1 +6,3,0,1,,6,3,3,1 +7,3,0,1,,7,3,3,1 +8,4,1,2,,8,4,4,2 +9,4,1,2,,9,4,4,2 +10,5,1,2,,10,5,5,2 +11,5,1,2,,11,5,5,2 +12,6,1,3,,12,6,6,3 +13,6,1,3,,13,6,6,3 +14,7,1,3,,14,7,7,3 +15,7,1,3,,15,7,7,3 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,1,0,0,,1,0,0,0 +2,2,0,0,,2,1,1,0 +3,3,0,0,,3,1,1,0 +4,0,0,1,,4,2,2,1 +5,1,0,1,,5,2,2,1 +6,2,0,1,,6,3,3,1 +7,3,0,1,,7,3,3,1 +8,0,1,2,,8,4,4,2 +9,1,1,2,,9,4,4,2 +10,2,1,2,,10,5,5,2 +11,3,1,2,,11,5,5,2 +12,0,1,3,,12,6,6,3 +13,1,1,3,,13,6,6,3 +14,2,1,3,,14,7,7,3 +15,3,1,3,,15,7,7,3 |