diff options
Diffstat (limited to 'src/spdk/dpdk/config')
30 files changed, 1958 insertions, 0 deletions
diff --git a/src/spdk/dpdk/config/arm/arm64_armv8_linuxapp_gcc b/src/spdk/dpdk/config/arm/arm64_armv8_linuxapp_gcc new file mode 100644 index 00000000..987c02fb --- /dev/null +++ b/src/spdk/dpdk/config/arm/arm64_armv8_linuxapp_gcc @@ -0,0 +1,24 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = 'generic' + +# Valid options for Arm's implementor_pn: +# 'default': valid for all armv8-a architectures (default value) +# '0xd03': cortex-a53 +# '0xd04': cortex-a35 +# '0xd07': cortex-a57 +# '0xd08': cortex-a72 +# '0xd09': cortex-a73 +# '0xd0a': cortex-a75 +implementor_pn = 'default' diff --git a/src/spdk/dpdk/config/arm/arm64_dpaa2_linuxapp_gcc b/src/spdk/dpdk/config/arm/arm64_dpaa2_linuxapp_gcc new file mode 100644 index 00000000..7ec74ec4 --- /dev/null +++ b/src/spdk/dpdk/config/arm/arm64_dpaa2_linuxapp_gcc @@ -0,0 +1,15 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-ar' +as = 'aarch64-linux-gnu-as' +strip = 'aarch64-linux-gnu-strip' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = 'dpaa2' diff --git a/src/spdk/dpdk/config/arm/arm64_dpaa_linuxapp_gcc b/src/spdk/dpdk/config/arm/arm64_dpaa_linuxapp_gcc new file mode 100644 index 00000000..73a8f0b8 --- /dev/null +++ b/src/spdk/dpdk/config/arm/arm64_dpaa_linuxapp_gcc @@ -0,0 +1,15 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-ar' +as = 'aarch64-linux-gnu-as' +strip = 'aarch64-linux-gnu-strip' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = 'dpaa' diff --git a/src/spdk/dpdk/config/arm/arm64_thunderx_linuxapp_gcc b/src/spdk/dpdk/config/arm/arm64_thunderx_linuxapp_gcc new file mode 100644 index 00000000..967d9d46 --- /dev/null +++ b/src/spdk/dpdk/config/arm/arm64_thunderx_linuxapp_gcc @@ -0,0 +1,14 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x43' diff --git a/src/spdk/dpdk/config/arm/armv8_machine.py b/src/spdk/dpdk/config/arm/armv8_machine.py new file mode 100755 index 00000000..404866d2 --- /dev/null +++ b/src/spdk/dpdk/config/arm/armv8_machine.py @@ -0,0 +1,18 @@ +#!/usr/bin/python +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Cavium, Inc + +ident = [] +fname = '/sys/devices/system/cpu/cpu0/regs/identification/midr_el1' +with open(fname) as f: + content = f.read() + +midr_el1 = (int(content.rstrip('\n'), 16)) + +ident.append(hex((midr_el1 >> 24) & 0xFF)) # Implementer +ident.append(hex((midr_el1 >> 20) & 0xF)) # Variant +ident.append(hex((midr_el1 >> 16) & 0XF)) # Architecture +ident.append(hex((midr_el1 >> 4) & 0xFFF)) # Primary Part number +ident.append(hex(midr_el1 & 0xF)) # Revision + +print(' '.join(ident)) diff --git a/src/spdk/dpdk/config/arm/meson.build b/src/spdk/dpdk/config/arm/meson.build new file mode 100644 index 00000000..40dbc87f --- /dev/null +++ b/src/spdk/dpdk/config/arm/meson.build @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation. +# Copyright(c) 2017 Cavium, Inc + +# for checking defines we need to use the correct compiler flags +march_opt = '-march=@0@'.format(machine) + +arm_force_native_march = false + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']], +] +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88']], + ['0xa2', ['-mcpu=thunderxt81']], + ['0xa3', ['-mcpu=thunderxt83']]] + +flags_common_default = [ + # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) + # to determine the best threshold in code. Refer to notes in source file + # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info. + ['RTE_ARCH_ARM64_MEMCPY', false], + # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048], + # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512], + # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're + # strong reasons. + # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false], + # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], + # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], + + ['RTE_LIBRTE_FM10K_PMD', false], + ['RTE_LIBRTE_SFC_EFX_PMD', false], + ['RTE_LIBRTE_AVP_PMD', false], + + ['RTE_SCHED_VECTOR', false], +] + +flags_generic = [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_CACHE_LINE_SIZE', 128]] +flags_cavium = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_CACHE_LINE_SIZE', 128], + ['RTE_MAX_NUMA_NODES', 2], + ['RTE_MAX_LCORE', 96], + ['RTE_MAX_VFIO_GROUPS', 128], + ['RTE_RING_USE_C11_MEM_MODEL', false]] +flags_dpaa = [ + ['RTE_MACHINE', '"dpaa"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 16]] +flags_dpaa2 = [ + ['RTE_MACHINE', '"dpaa2"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 16], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] + +## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) +impl_generic = ['Generic armv8', flags_generic, machine_args_generic] +impl_0x41 = ['Arm', flags_generic, machine_args_generic] +impl_0x42 = ['Broadcom', flags_generic, machine_args_generic] +impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium] +impl_0x44 = ['DEC', flags_generic, machine_args_generic] +impl_0x49 = ['Infineon', flags_generic, machine_args_generic] +impl_0x4d = ['Motorola', flags_generic, machine_args_generic] +impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic] +impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic] +impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic] +impl_0x53 = ['Samsung', flags_generic, machine_args_generic] +impl_0x56 = ['Marvell', flags_generic, machine_args_generic] +impl_0x69 = ['Intel', flags_generic, machine_args_generic] +impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic] +impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic] + +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) + +if cc.sizeof('void *') != 8 + dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) + dpdk_conf.set('RTE_ARCH_ARM', 1) + dpdk_conf.set('RTE_ARCH_ARMv7', 1) +else + dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128) + dpdk_conf.set('RTE_ARCH_ARM64', 1) + dpdk_conf.set('RTE_ARCH_64', 1) + + machine = [] + cmd_generic = ['generic', '', '', 'default', ''] + cmd_output = cmd_generic # Set generic by default + machine_args = [] # Clear previous machine args + if not meson.is_cross_build() + # The script returns ['Implementer', 'Variant', 'Architecture', + # 'Primary Part number', 'Revision'] + detect_vendor = find_program(join_paths( + meson.current_source_dir(), 'armv8_machine.py')) + cmd = run_command(detect_vendor.path()) + if cmd.returncode() == 0 + cmd_output = cmd.stdout().to_lower().strip().split(' ') + endif + # Set to generic if variable is not found + machine = get_variable('impl_' + cmd_output[0], 'generic') + if machine == 'generic' + machine = impl_generic + cmd_output = cmd_generic + endif + impl_pn = cmd_output[3] + if arm_force_native_march == true + impl_pn = 'native' + endif + else + impl_id = meson.get_cross_property('implementor_id', 'generic') + impl_pn = meson.get_cross_property('implementor_pn', 'default') + machine = get_variable('impl_' + impl_id) + endif + + # Apply Common Defaults. These settings may be overwritten by machine + # settings later. + foreach flag: flags_common_default + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif + endforeach + + message('Implementer : ' + machine[0]) + foreach flag: machine[1] + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif + endforeach + # Primary part number based mcpu flags are supported + # for gcc versions > 7 + if cc.version().version_compare( + '<7.0') or cmd_output.length() == 0 + if not meson.is_cross_build() and arm_force_native_march == true + impl_pn = 'native' + else + impl_pn = 'default' + endif + endif + foreach marg: machine[2] + if marg[0] == impl_pn + foreach f: marg[1] + machine_args += f + endforeach + endif + endforeach +endif +message(machine_args) + +if cc.get_define('__ARM_NEON', args: machine_args) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] +endif + +if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_CRC32'] +endif + +if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1) + dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1) + dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1) + dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL', + 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2'] +endif diff --git a/src/spdk/dpdk/config/common_armv8a_linuxapp b/src/spdk/dpdk/config/common_armv8a_linuxapp new file mode 100644 index 00000000..111c0056 --- /dev/null +++ b/src/spdk/dpdk/config/common_armv8a_linuxapp @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Cavium, Inc +# + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="armv8a" + +CONFIG_RTE_ARCH="arm64" +CONFIG_RTE_ARCH_ARM64=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_FORCE_INTRINSICS=y + +# Maximum available cache line size in arm64 implementations. +# Setting to maximum available cache line size in generic config +# to address minimum DMA alignment across all arm64 implementations. +CONFIG_RTE_CACHE_LINE_SIZE=128 + +# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) +# to determine the best threshold in code. Refer to notes in source file +# (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info. +CONFIG_RTE_ARCH_ARM64_MEMCPY=n +#CONFIG_RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD=2048 +#CONFIG_RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD=512 +# Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're +# strong reasons. +#CONFIG_RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK=n +#CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF +#CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n + +CONFIG_RTE_RING_USE_C11_MEM_MODEL=y + +CONFIG_RTE_LIBRTE_FM10K_PMD=n +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n +CONFIG_RTE_LIBRTE_AVP_PMD=n + +CONFIG_RTE_SCHED_VECTOR=n diff --git a/src/spdk/dpdk/config/common_base b/src/spdk/dpdk/config/common_base new file mode 100644 index 00000000..d5fbb3a4 --- /dev/null +++ b/src/spdk/dpdk/config/common_base @@ -0,0 +1,912 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2017 Intel Corporation + +# +# define executive environment +# RTE_EXEC_ENV values are the directories in mk/exec-env/ +# +CONFIG_RTE_EXEC_ENV= + +# +# define the architecture we compile for. +# RTE_ARCH values are the directories in mk/arch/ +# +CONFIG_RTE_ARCH= + +# +# machine can define specific variables or action for a specific board +# RTE_MACHINE values are the directories in mk/machine/ +# +CONFIG_RTE_MACHINE= + +# +# The compiler we use. +# RTE_TOOLCHAIN values are the directories in mk/toolchain/ +# +CONFIG_RTE_TOOLCHAIN= + +# +# Use intrinsics or assembly code for key routines +# +CONFIG_RTE_FORCE_INTRINSICS=n + +# +# Machine forces strict alignment constraints. +# +CONFIG_RTE_ARCH_STRICT_ALIGN=n + +# +# Compile to share library +# +CONFIG_RTE_BUILD_SHARED_LIB=n + +# +# Use newest code breaking previous ABI +# +CONFIG_RTE_NEXT_ABI=y + +# +# Major ABI to overwrite library specific LIBABIVER +# +CONFIG_RTE_MAJOR_ABI= + +# +# Machine's cache line size +# +CONFIG_RTE_CACHE_LINE_SIZE=64 + +# +# Compile Environment Abstraction Layer +# +CONFIG_RTE_LIBRTE_EAL=y +CONFIG_RTE_MAX_LCORE=128 +CONFIG_RTE_MAX_NUMA_NODES=8 +CONFIG_RTE_MAX_MEMSEG_LISTS=64 +# each memseg list will be limited to either RTE_MAX_MEMSEG_PER_LIST pages +# or RTE_MAX_MEM_MB_PER_LIST megabytes worth of memory, whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_LIST=8192 +CONFIG_RTE_MAX_MEM_MB_PER_LIST=32768 +# a "type" is a combination of page size and NUMA node. total number of memseg +# lists per type will be limited to either RTE_MAX_MEMSEG_PER_TYPE pages (split +# over multiple lists of RTE_MAX_MEMSEG_PER_LIST pages), or +# RTE_MAX_MEM_MB_PER_TYPE megabytes of memory (split over multiple lists of +# RTE_MAX_MEM_MB_PER_LIST), whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_TYPE=32768 +CONFIG_RTE_MAX_MEM_MB_PER_TYPE=131072 +# global maximum usable amount of VA, in megabytes +CONFIG_RTE_MAX_MEM_MB=524288 +CONFIG_RTE_MAX_MEMZONE=2560 +CONFIG_RTE_MAX_TAILQ=32 +CONFIG_RTE_ENABLE_ASSERT=n +CONFIG_RTE_LOG_DP_LEVEL=RTE_LOG_INFO +CONFIG_RTE_LOG_HISTORY=256 +CONFIG_RTE_BACKTRACE=y +CONFIG_RTE_LIBEAL_USE_HPET=n +CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n +CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n +#CONFIG_RTE_EAL_IGB_UIO=n +CONFIG_RTE_EAL_VFIO=n +CONFIG_RTE_MAX_VFIO_GROUPS=64 +CONFIG_RTE_MAX_VFIO_CONTAINERS=64 +CONFIG_RTE_MALLOC_DEBUG=n +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_USE_LIBBSD=n + +# +# Recognize/ignore the AVX/AVX512 CPU flags for performance/power testing. +# AVX512 is marked as experimental for now, will enable it after enough +# field test and possible optimization. +# +CONFIG_RTE_ENABLE_AVX=y +CONFIG_RTE_ENABLE_AVX512=n + +# Default driver path (or "" to disable) +CONFIG_RTE_EAL_PMD_PATH="" + +# +# Compile Environment Abstraction Layer to support Vmware TSC map +# +CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=y + +# +# Compile the PCI library +# +CONFIG_RTE_LIBRTE_PCI=y + +# +# Compile the argument parser library +# +CONFIG_RTE_LIBRTE_KVARGS=y + +# +# Compile generic ethernet library +# +CONFIG_RTE_LIBRTE_ETHER=y +CONFIG_RTE_LIBRTE_ETHDEV_DEBUG=n +CONFIG_RTE_MAX_ETHPORTS=32 +CONFIG_RTE_MAX_QUEUES_PER_PORT=1024 +CONFIG_RTE_LIBRTE_IEEE1588=n +CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16 +CONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y +CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n + +# +# Turn off Tx preparation stage +# +# Warning: rte_eth_tx_prepare() can be safely disabled only if using a +# driver which do not implement any Tx preparation. +# +CONFIG_RTE_ETHDEV_TX_PREPARE_NOOP=n + +# +# Compile the Intel FPGA bus +# +CONFIG_RTE_LIBRTE_IFPGA_BUS=n + +# +# Compile PCI bus driver +# +CONFIG_RTE_LIBRTE_PCI_BUS=y + +# +# Compile the vdev bus +# +CONFIG_RTE_LIBRTE_VDEV_BUS=y + +# +# Compile ARK PMD +# +CONFIG_RTE_LIBRTE_ARK_PMD=n +CONFIG_RTE_LIBRTE_ARK_PAD_TX=y +CONFIG_RTE_LIBRTE_ARK_DEBUG_RX=n +CONFIG_RTE_LIBRTE_ARK_DEBUG_TX=n +CONFIG_RTE_LIBRTE_ARK_DEBUG_STATS=n +CONFIG_RTE_LIBRTE_ARK_DEBUG_TRACE=n + +# +# Compile AMD PMD +# +CONFIG_RTE_LIBRTE_AXGBE_PMD=n +CONFIG_RTE_LIBRTE_AXGBE_PMD_DEBUG=n + +# +# Compile burst-oriented Broadcom PMD driver +# +CONFIG_RTE_LIBRTE_BNX2X_PMD=n +CONFIG_RTE_LIBRTE_BNX2X_DEBUG_RX=n +CONFIG_RTE_LIBRTE_BNX2X_DEBUG_TX=n +CONFIG_RTE_LIBRTE_BNX2X_MF_SUPPORT=n +CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n + +# +# Compile burst-oriented Broadcom BNXT PMD driver +# +CONFIG_RTE_LIBRTE_BNXT_PMD=n + +# +# Compile burst-oriented Chelsio Terminator (CXGBE) PMD +# +CONFIG_RTE_LIBRTE_CXGBE_PMD=n +CONFIG_RTE_LIBRTE_CXGBE_DEBUG=n +CONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG=n +CONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX=n +CONFIG_RTE_LIBRTE_CXGBE_DEBUG_TX=n +CONFIG_RTE_LIBRTE_CXGBE_DEBUG_RX=n +CONFIG_RTE_LIBRTE_CXGBE_TPUT=y + +# NXP DPAA Bus +CONFIG_RTE_LIBRTE_DPAA_BUS=n +CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=n +CONFIG_RTE_LIBRTE_DPAA_PMD=n +CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n + +# +# Compile NXP DPAA2 FSL-MC Bus +# +CONFIG_RTE_LIBRTE_FSLMC_BUS=n + +# +# Compile Support Libraries for NXP DPAA2 +# +CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=n +CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y + +# +# Compile burst-oriented NXP DPAA2 PMD driver +# +CONFIG_RTE_LIBRTE_DPAA2_PMD=n +CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n + +# +# Compile burst-oriented Amazon ENA PMD driver +# +CONFIG_RTE_LIBRTE_ENA_PMD=n +CONFIG_RTE_LIBRTE_ENA_DEBUG_RX=n +CONFIG_RTE_LIBRTE_ENA_DEBUG_TX=n +CONFIG_RTE_LIBRTE_ENA_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_ENA_COM_DEBUG=n + +# +# Compile burst-oriented Cisco ENIC PMD driver +# +CONFIG_RTE_LIBRTE_ENIC_PMD=n + +# +# Compile burst-oriented IGB & EM PMD drivers +# +CONFIG_RTE_LIBRTE_EM_PMD=n +CONFIG_RTE_LIBRTE_IGB_PMD=n +CONFIG_RTE_LIBRTE_E1000_DEBUG_RX=n +CONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n +CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n + +# +# Compile burst-oriented IXGBE PMD driver +# +CONFIG_RTE_LIBRTE_IXGBE_PMD=n +CONFIG_RTE_LIBRTE_IXGBE_DEBUG_RX=n +CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX=n +CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n +CONFIG_RTE_IXGBE_INC_VECTOR=y +CONFIG_RTE_LIBRTE_IXGBE_BYPASS=n + +# +# Compile burst-oriented I40E PMD driver +# +CONFIG_RTE_LIBRTE_I40E_PMD=n +CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n +CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n +CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y +CONFIG_RTE_LIBRTE_I40E_INC_VECTOR=y +CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n +CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF=64 +CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4 + +# +# Compile burst-oriented FM10K PMD +# +CONFIG_RTE_LIBRTE_FM10K_PMD=n +CONFIG_RTE_LIBRTE_FM10K_DEBUG_RX=n +CONFIG_RTE_LIBRTE_FM10K_DEBUG_TX=n +CONFIG_RTE_LIBRTE_FM10K_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y +CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR=y + +# +# Compile burst-oriented AVF PMD driver +# +CONFIG_RTE_LIBRTE_AVF_PMD=n +CONFIG_RTE_LIBRTE_AVF_INC_VECTOR=y +CONFIG_RTE_LIBRTE_AVF_DEBUG_TX=n +CONFIG_RTE_LIBRTE_AVF_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_AVF_DEBUG_RX=n +CONFIG_RTE_LIBRTE_AVF_16BYTE_RX_DESC=n + +# +# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD +# +CONFIG_RTE_LIBRTE_MLX4_PMD=n +CONFIG_RTE_LIBRTE_MLX4_DEBUG=n +CONFIG_RTE_LIBRTE_MLX4_DLOPEN_DEPS=n + +# +# Compile burst-oriented Mellanox ConnectX-4, ConnectX-5 & Bluefield +# (MLX5) PMD +# +CONFIG_RTE_LIBRTE_MLX5_PMD=n +CONFIG_RTE_LIBRTE_MLX5_DEBUG=n +CONFIG_RTE_LIBRTE_MLX5_DLOPEN_DEPS=n + +# +# Compile burst-oriented Netronome NFP PMD driver +# +CONFIG_RTE_LIBRTE_NFP_PMD=n +CONFIG_RTE_LIBRTE_NFP_DEBUG_TX=n +CONFIG_RTE_LIBRTE_NFP_DEBUG_RX=n + +# QLogic 10G/25G/40G/50G/100G PMD +# +CONFIG_RTE_LIBRTE_QEDE_PMD=n +CONFIG_RTE_LIBRTE_QEDE_DEBUG_TX=n +CONFIG_RTE_LIBRTE_QEDE_DEBUG_RX=n +#Provides abs path/name of the firmware file. +#Empty string denotes driver will use default firmware +CONFIG_RTE_LIBRTE_QEDE_FW="" + +# +# Compile burst-oriented Solarflare libefx-based PMD +# +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n +CONFIG_RTE_LIBRTE_SFC_EFX_DEBUG=n + +# +# Compile software PMD backed by SZEDATA2 device +# +CONFIG_RTE_LIBRTE_PMD_SZEDATA2=n + +# +# Compile burst-oriented Cavium Thunderx NICVF PMD driver +# +CONFIG_RTE_LIBRTE_THUNDERX_NICVF_PMD=n +CONFIG_RTE_LIBRTE_THUNDERX_NICVF_DEBUG_RX=n +CONFIG_RTE_LIBRTE_THUNDERX_NICVF_DEBUG_TX=n + +# +# Compile burst-oriented Cavium LiquidIO PMD driver +# +CONFIG_RTE_LIBRTE_LIO_PMD=n +CONFIG_RTE_LIBRTE_LIO_DEBUG_RX=n +CONFIG_RTE_LIBRTE_LIO_DEBUG_TX=n +CONFIG_RTE_LIBRTE_LIO_DEBUG_MBOX=n +CONFIG_RTE_LIBRTE_LIO_DEBUG_REGS=n + +# +# Compile burst-oriented Cavium OCTEONTX network PMD driver +# +CONFIG_RTE_LIBRTE_OCTEONTX_PMD=n + +# +# Compile WRS accelerated virtual port (AVP) guest PMD driver +# +CONFIG_RTE_LIBRTE_AVP_PMD=n +CONFIG_RTE_LIBRTE_AVP_DEBUG_RX=n +CONFIG_RTE_LIBRTE_AVP_DEBUG_TX=n +CONFIG_RTE_LIBRTE_AVP_DEBUG_BUFFERS=n + +# +# Compile burst-oriented VIRTIO PMD driver +# +CONFIG_RTE_LIBRTE_VIRTIO_PMD=n +CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_RX=n +CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_TX=n +CONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DUMP=n + +# +# Compile virtio device emulation inside virtio PMD driver +# +CONFIG_RTE_VIRTIO_USER=n + +# +# Compile burst-oriented VMXNET3 PMD driver +# +CONFIG_RTE_LIBRTE_VMXNET3_PMD=n +CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_RX=n +CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX=n +CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE=n + +# +# Compile software PMD backed by AF_PACKET sockets (Linux only) +# +CONFIG_RTE_LIBRTE_PMD_AF_PACKET=n + +# +# Compile link bonding PMD library +# +CONFIG_RTE_LIBRTE_PMD_BOND=n +CONFIG_RTE_LIBRTE_BOND_DEBUG_ALB=n +CONFIG_RTE_LIBRTE_BOND_DEBUG_ALB_L1=n + +# +# Compile fail-safe PMD +# +CONFIG_RTE_LIBRTE_PMD_FAILSAFE=n + +# +# Compile Marvell PMD driver +# +CONFIG_RTE_LIBRTE_MRVL_PMD=n + +# +# Compile support for VMBus library +# +CONFIG_RTE_LIBRTE_VMBUS=n + +# +# Compile native PMD for Hyper-V/Azure +# +CONFIG_RTE_LIBRTE_NETVSC_PMD=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_RX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_TX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_DUMP=n + +# +# Compile virtual device driver for NetVSC on Hyper-V/Azure +# +CONFIG_RTE_LIBRTE_VDEV_NETVSC_PMD=n + +# +# Compile null PMD +# +CONFIG_RTE_LIBRTE_PMD_NULL=n + +# +# Compile software PMD backed by PCAP files +# +CONFIG_RTE_LIBRTE_PMD_PCAP=n + +# +# Compile example software rings based PMD +# +CONFIG_RTE_LIBRTE_PMD_RING=n +CONFIG_RTE_PMD_RING_MAX_RX_RINGS=16 +CONFIG_RTE_PMD_RING_MAX_TX_RINGS=16 + +# +# Compile SOFTNIC PMD +# +CONFIG_RTE_LIBRTE_PMD_SOFTNIC=n + +# +# Compile the TAP PMD +# It is enabled by default for Linux only. +# +CONFIG_RTE_LIBRTE_PMD_TAP=n + +# +# Do prefetch of packet data within PMD driver receive function +# +CONFIG_RTE_PMD_PACKET_PREFETCH=y + +# Compile generic wireless base band device library +# EXPERIMENTAL: API may change without prior notice +# +CONFIG_RTE_LIBRTE_BBDEV=n +CONFIG_RTE_BBDEV_MAX_DEVS=128 +CONFIG_RTE_BBDEV_OFFLOAD_COST=n + +# +# Compile PMD for NULL bbdev device +# +CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL=n + +# +# Compile PMD for turbo software bbdev device +# +CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=n + +# +# Compile generic crypto device library +# +#CONFIG_RTE_LIBRTE_CRYPTODEV=n +CONFIG_RTE_CRYPTO_MAX_DEVS=64 + +# +# Compile PMD for ARMv8 Crypto device +# +CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=n +CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO_DEBUG=n + +# +# Compile NXP DPAA2 crypto sec driver for CAAM HW +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n + +# +# NXP DPAA caam - crypto driver +# +CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n +CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 + +# +# Compile PMD for QuickAssist based devices - see docs for details +# +#CONFIG_RTE_LIBRTE_PMD_QAT=n +#CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n +# +# Max. number of QuickAssist devices, which can be detected and attached +# +CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 +CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16 + +# +# Compile PMD for virtio crypto devices +# +CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO=n +# +# Number of maximum virtio crypto devices +# +CONFIG_RTE_MAX_VIRTIO_CRYPTO=32 + +# +# Compile PMD for AESNI backed device +# +#CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n + +# +# Compile PMD for Software backed device +# +CONFIG_RTE_LIBRTE_PMD_OPENSSL=n + +# +# Compile PMD for AESNI GCM device +# +CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=n + +# +# Compile PMD for SNOW 3G device +# +CONFIG_RTE_LIBRTE_PMD_SNOW3G=n +CONFIG_RTE_LIBRTE_PMD_SNOW3G_DEBUG=n + +# +# Compile PMD for KASUMI device +# +CONFIG_RTE_LIBRTE_PMD_KASUMI=n + +# +# Compile PMD for ZUC device +# +CONFIG_RTE_LIBRTE_PMD_ZUC=n + +# Compile PMD for Crypto Scheduler device +# +CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n + +# +# Compile PMD for NULL Crypto device +# +CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=n + +# +# Compile PMD for AMD CCP crypto device +# +CONFIG_RTE_LIBRTE_PMD_CCP=n + +# +# Compile PMD for Marvell Crypto device +# +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO_DEBUG=n + +# +# Compile generic security library +# +CONFIG_RTE_LIBRTE_SECURITY=n + +# +# Compile generic compression device library +# +CONFIG_RTE_LIBRTE_COMPRESSDEV=n +CONFIG_RTE_COMPRESS_MAX_DEVS=64 + +# +# Compile compressdev unit test +# +CONFIG_RTE_COMPRESSDEV_TEST=n + +# +# Compile PMD for Octeontx ZIPVF compression device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF=n + +# +# Compile PMD for ISA-L compression device +# +CONFIG_RTE_LIBRTE_PMD_ISAL=n + +# +# Compile PMD for ZLIB compression device +# +CONFIG_RTE_LIBRTE_PMD_ZLIB=n + +# +# Compile generic event device library +# +CONFIG_RTE_LIBRTE_EVENTDEV=n +CONFIG_RTE_LIBRTE_EVENTDEV_DEBUG=n +CONFIG_RTE_EVENT_MAX_DEVS=16 +CONFIG_RTE_EVENT_MAX_QUEUES_PER_DEV=64 +CONFIG_RTE_EVENT_TIMER_ADAPTER_NUM_MAX=32 +CONFIG_RTE_EVENT_ETH_INTR_RING_SIZE=1024 +CONFIG_RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE=32 + +# +# Compile PMD for skeleton event device +# +CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV=n +CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV_DEBUG=n + +# +# Compile PMD for software event device +# +CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV=n + +# +# Compile PMD for octeontx sso event device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF=n + +# +# Compile PMD for OPDL event device +# +CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV=n + +# +# Compile PMD for NXP DPAA event device +# +CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n + +# +# Compile PMD for NXP DPAA2 event device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n + +# +# Compile raw device support +# EXPERIMENTAL: API may change without prior notice +# +CONFIG_RTE_LIBRTE_RAWDEV=n +CONFIG_RTE_RAWDEV_MAX_DEVS=10 +CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV=y + +# +# Compile PMD for NXP DPAA2 CMDIF raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV=n + +# +# Compile PMD for NXP DPAA2 QDMA raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n + +# +# Compile PMD for Intel FPGA raw device +# +CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n + +# +# Compile librte_ring +# +CONFIG_RTE_LIBRTE_RING=y +CONFIG_RTE_RING_USE_C11_MEM_MODEL=n + +# +# Compile librte_mempool +# +CONFIG_RTE_LIBRTE_MEMPOOL=y +CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE=512 +CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n + +# +# Compile Mempool drivers +# +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET=y +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB=64 +CONFIG_RTE_DRIVER_MEMPOOL_RING=y +CONFIG_RTE_DRIVER_MEMPOOL_STACK=n + +# +# Compile PMD for octeontx fpa mempool device +# +CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL=n + +# +# Compile librte_mbuf +# +CONFIG_RTE_LIBRTE_MBUF=y +CONFIG_RTE_LIBRTE_MBUF_DEBUG=n +CONFIG_RTE_MBUF_DEFAULT_MEMPOOL_OPS="ring_mp_mc" +CONFIG_RTE_MBUF_REFCNT_ATOMIC=y +CONFIG_RTE_PKTMBUF_HEADROOM=128 + +# +# Compile librte_timer +# +CONFIG_RTE_LIBRTE_TIMER=n +CONFIG_RTE_LIBRTE_TIMER_DEBUG=n + +# +# Compile librte_cfgfile +# +CONFIG_RTE_LIBRTE_CFGFILE=n + +# +# Compile librte_cmdline +# +CONFIG_RTE_LIBRTE_CMDLINE=n +CONFIG_RTE_LIBRTE_CMDLINE_DEBUG=n + +# +# Compile librte_hash +# +CONFIG_RTE_LIBRTE_HASH=n +CONFIG_RTE_LIBRTE_HASH_DEBUG=n + +# +# Compile librte_efd +# +CONFIG_RTE_LIBRTE_EFD=n + +# +# Compile librte_member +# +CONFIG_RTE_LIBRTE_MEMBER=n + +# +# Compile librte_jobstats +# +CONFIG_RTE_LIBRTE_JOBSTATS=n + +# +# Compile the device metrics library +# +CONFIG_RTE_LIBRTE_METRICS=n + +# +# Compile the bitrate statistics library +# +CONFIG_RTE_LIBRTE_BITRATE=n + +# +# Compile the latency statistics library +# +CONFIG_RTE_LIBRTE_LATENCY_STATS=n + +# +# Compile librte_lpm +# +CONFIG_RTE_LIBRTE_LPM=n +CONFIG_RTE_LIBRTE_LPM_DEBUG=n + +# +# Compile librte_acl +# +CONFIG_RTE_LIBRTE_ACL=n +CONFIG_RTE_LIBRTE_ACL_DEBUG=n + +# +# Compile librte_power +# +CONFIG_RTE_LIBRTE_POWER=n +CONFIG_RTE_LIBRTE_POWER_DEBUG=n +CONFIG_RTE_MAX_LCORE_FREQS=64 + +# +# Compile librte_net +# +CONFIG_RTE_LIBRTE_NET=y + +# +# Compile librte_ip_frag +# +CONFIG_RTE_LIBRTE_IP_FRAG=n +CONFIG_RTE_LIBRTE_IP_FRAG_DEBUG=n +CONFIG_RTE_LIBRTE_IP_FRAG_MAX_FRAG=4 +CONFIG_RTE_LIBRTE_IP_FRAG_TBL_STAT=n + +# +# Compile GRO library +# +CONFIG_RTE_LIBRTE_GRO=n + +# +# Compile GSO library +# +CONFIG_RTE_LIBRTE_GSO=n + +# +# Compile librte_meter +# +CONFIG_RTE_LIBRTE_METER=n + +# +# Compile librte_classify +# +CONFIG_RTE_LIBRTE_FLOW_CLASSIFY=n + +# +# Compile librte_sched +# +CONFIG_RTE_LIBRTE_SCHED=n +CONFIG_RTE_SCHED_DEBUG=n +CONFIG_RTE_SCHED_RED=n +CONFIG_RTE_SCHED_COLLECT_STATS=n +CONFIG_RTE_SCHED_SUBPORT_TC_OV=n +CONFIG_RTE_SCHED_PORT_N_GRINDERS=8 +CONFIG_RTE_SCHED_VECTOR=n + +# +# Compile the distributor library +# +CONFIG_RTE_LIBRTE_DISTRIBUTOR=n + +# +# Compile the reorder library +# +#CONFIG_RTE_LIBRTE_REORDER=n + +# +# Compile librte_port +# +CONFIG_RTE_LIBRTE_PORT=n +CONFIG_RTE_PORT_STATS_COLLECT=n +CONFIG_RTE_PORT_PCAP=n + +# +# Compile librte_table +# +CONFIG_RTE_LIBRTE_TABLE=n +CONFIG_RTE_TABLE_STATS_COLLECT=n + +# +# Compile librte_pipeline +# +CONFIG_RTE_LIBRTE_PIPELINE=n +CONFIG_RTE_PIPELINE_STATS_COLLECT=n + +# +# Compile librte_kni +# +CONFIG_RTE_LIBRTE_KNI=n +CONFIG_RTE_LIBRTE_PMD_KNI=n +CONFIG_RTE_KNI_KMOD=n +CONFIG_RTE_KNI_KMOD_ETHTOOL=n +CONFIG_RTE_KNI_PREEMPT_DEFAULT=y + +# +# Compile the pdump library +# +CONFIG_RTE_LIBRTE_PDUMP=n + +# +# Compile vhost user library +# +CONFIG_RTE_LIBRTE_VHOST=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n +CONFIG_RTE_LIBRTE_VHOST_DEBUG=n + +# +# Compile vhost PMD +# To compile, CONFIG_RTE_LIBRTE_VHOST should be enabled. +# +CONFIG_RTE_LIBRTE_PMD_VHOST=n + +# +# Compile IFCVF driver +# To compile, CONFIG_RTE_LIBRTE_VHOST and CONFIG_RTE_EAL_VFIO +# should be enabled. +# +CONFIG_RTE_LIBRTE_IFCVF_VDPA_PMD=n + +# +# Compile librte_bpf +# +CONFIG_RTE_LIBRTE_BPF=n +# allow load BPF from ELF files (requires libelf) +CONFIG_RTE_LIBRTE_BPF_ELF=n + +# +# Compile the test application +# +CONFIG_RTE_APP_TEST=n +CONFIG_RTE_APP_TEST_RESOURCE_TAR=n + +# +# Compile the procinfo application +# +CONFIG_RTE_PROC_INFO=n + +# +# Compile the PMD test application +# +CONFIG_RTE_TEST_PMD=n +CONFIG_RTE_TEST_PMD_RECORD_CORE_CYCLES=n +CONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n + +# +# Compile the bbdev test application +# +CONFIG_RTE_TEST_BBDEV=n + +# +# Compile the crypto performance application +# +CONFIG_RTE_APP_CRYPTO_PERF=n + +# +# Compile the eventdev application +# +CONFIG_RTE_APP_EVENTDEV=n diff --git a/src/spdk/dpdk/config/common_bsdapp b/src/spdk/dpdk/config/common_bsdapp new file mode 100644 index 00000000..3399246e --- /dev/null +++ b/src/spdk/dpdk/config/common_bsdapp @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2016 Intel Corporation + +#include "common_base" + +CONFIG_RTE_EXEC_ENV="bsdapp" +CONFIG_RTE_EXEC_ENV_BSDAPP=y + +# +# FreeBSD contiguous memory driver settings +# +CONFIG_RTE_CONTIGMEM_MAX_NUM_BUFS=64 +CONFIG_RTE_CONTIGMEM_DEFAULT_NUM_BUFS=2 +CONFIG_RTE_CONTIGMEM_DEFAULT_BUF_SIZE=1024*1024*1024 diff --git a/src/spdk/dpdk/config/common_linuxapp b/src/spdk/dpdk/config/common_linuxapp new file mode 100644 index 00000000..0c490627 --- /dev/null +++ b/src/spdk/dpdk/config/common_linuxapp @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2016 Intel Corporation + +#include "common_base" + +CONFIG_RTE_EXEC_ENV="linuxapp" +CONFIG_RTE_EXEC_ENV_LINUXAPP=y + +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=y +#CONFIG_RTE_EAL_IGB_UIO=n +CONFIG_RTE_EAL_VFIO=y +CONFIG_RTE_KNI_KMOD=n +CONFIG_RTE_LIBRTE_KNI=n +CONFIG_RTE_LIBRTE_PMD_KNI=n +CONFIG_RTE_LIBRTE_VHOST=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=y +CONFIG_RTE_LIBRTE_PMD_VHOST=n +CONFIG_RTE_LIBRTE_IFC_PMD=n +CONFIG_RTE_LIBRTE_PMD_AF_PACKET=n +CONFIG_RTE_LIBRTE_PMD_SOFTNIC=n +CONFIG_RTE_LIBRTE_PMD_TAP=n +CONFIG_RTE_LIBRTE_AVP_PMD=n +CONFIG_RTE_LIBRTE_VDEV_NETVSC_PMD=n +CONFIG_RTE_LIBRTE_NFP_PMD=n +CONFIG_RTE_LIBRTE_POWER=n +CONFIG_RTE_VIRTIO_USER=n +CONFIG_RTE_PROC_INFO=n + +CONFIG_RTE_LIBRTE_VMBUS=n +CONFIG_RTE_LIBRTE_NETVSC_PMD=n + +# NXP DPAA BUS and drivers +CONFIG_RTE_LIBRTE_DPAA_BUS=n +CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y +CONFIG_RTE_LIBRTE_DPAA_PMD=n +CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y +CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y + +# NXP FSLMC BUS and DPAA2 drivers +CONFIG_RTE_LIBRTE_FSLMC_BUS=n +CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y +CONFIG_RTE_LIBRTE_DPAA2_PMD=n +CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y +CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y +CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV=y +CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=y diff --git a/src/spdk/dpdk/config/defconfig_arm-armv7a-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm-armv7a-linuxapp-gcc new file mode 100644 index 00000000..13be308d --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm-armv7a-linuxapp-gcc @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2015 RehiveTech. All right reserved. + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="armv7a" + +CONFIG_RTE_ARCH="arm" +CONFIG_RTE_ARCH_ARM=y +CONFIG_RTE_ARCH_ARMv7=y +CONFIG_RTE_ARCH_ARM_TUNE="cortex-a9" + +# Accelerate memcpy operations. Consider enabling for Cortex-A15. +# For Cortex-A7 and Cortex-A9, It might accelerate short data copies (< 64 B). +CONFIG_RTE_ARCH_ARM_NEON_MEMCPY=n + +CONFIG_RTE_FORCE_INTRINSICS=y +CONFIG_RTE_ARCH_STRICT_ALIGN=y + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y + +# NUMA is not supported on ARM +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n + +# ARM doesn't have support for vmware TSC map +CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n + +# KNI is not supported on 32-bit +CONFIG_RTE_LIBRTE_KNI=n + +# PCI is usually not used on ARM +CONFIG_RTE_EAL_IGB_UIO=n + +# fails to compile on ARM +CONFIG_RTE_SCHED_VECTOR=n + +# cannot use those on ARM +CONFIG_RTE_KNI_KMOD=n +CONFIG_RTE_LIBRTE_ARK_PMD=n +CONFIG_RTE_LIBRTE_EM_PMD=n +CONFIG_RTE_LIBRTE_IGB_PMD=n +CONFIG_RTE_LIBRTE_CXGBE_PMD=n +CONFIG_RTE_LIBRTE_E1000_PMD=n +CONFIG_RTE_LIBRTE_ENIC_PMD=n +CONFIG_RTE_LIBRTE_FM10K_PMD=n +CONFIG_RTE_LIBRTE_I40E_PMD=n +CONFIG_RTE_LIBRTE_IXGBE_PMD=n +CONFIG_RTE_LIBRTE_MLX4_PMD=n +CONFIG_RTE_LIBRTE_VMXNET3_PMD=n +CONFIG_RTE_LIBRTE_BNX2X_PMD=n +CONFIG_RTE_LIBRTE_QEDE_PMD=n +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n +CONFIG_RTE_LIBRTE_AVP_PMD=n diff --git a/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-clang b/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-clang new file mode 100644 index 00000000..487714ea --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-clang @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Cavium, Inc +# + +#include "common_armv8a_linuxapp" + +CONFIG_RTE_TOOLCHAIN="clang" +CONFIG_RTE_TOOLCHAIN_CLANG=y diff --git a/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-gcc new file mode 100644 index 00000000..18427443 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-armv8a-linuxapp-gcc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2015 Cavium, Inc +# + +#include "common_armv8a_linuxapp" + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y diff --git a/src/spdk/dpdk/config/defconfig_arm64-dpaa-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-dpaa-linuxapp-gcc new file mode 100644 index 00000000..c47aec0a --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-dpaa-linuxapp-gcc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2016 Freescale Semiconductor, Inc. +# Copyright 2017 NXP + +#include "defconfig_arm64-armv8a-linuxapp-gcc" + +# NXP (Freescale) - Soc Architecture with FMAN, QMAN & BMAN support +CONFIG_RTE_MACHINE="dpaa" +CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72" +CONFIG_RTE_LIBRTE_VHOST_NUMA=n +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n + +# +# Compile Environment Abstraction Layer +# +CONFIG_RTE_MAX_LCORE=16 +CONFIG_RTE_MAX_NUMA_NODES=1 +CONFIG_RTE_CACHE_LINE_SIZE=64 +CONFIG_RTE_PKTMBUF_HEADROOM=128 + +# NXP DPAA Bus +CONFIG_RTE_LIBRTE_DPAA_DEBUG_DRIVER=n +CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n diff --git a/src/spdk/dpdk/config/defconfig_arm64-dpaa2-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-dpaa2-linuxapp-gcc new file mode 100644 index 00000000..96f478a0 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-dpaa2-linuxapp-gcc @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2016 NXP +# + +#include "defconfig_arm64-armv8a-linuxapp-gcc" + +# NXP (Freescale) - Soc Architecture with WRIOP and QBMAN support +CONFIG_RTE_MACHINE="dpaa2" +CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72" + +CONFIG_RTE_MAX_LCORE=16 +CONFIG_RTE_MAX_NUMA_NODES=1 +CONFIG_RTE_CACHE_LINE_SIZE=64 + +CONFIG_RTE_PKTMBUF_HEADROOM=128 + +# Doesn't support NUMA +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n + +CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=n diff --git a/src/spdk/dpdk/config/defconfig_arm64-stingray-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-stingray-linuxapp-gcc new file mode 100644 index 00000000..99925072 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-stingray-linuxapp-gcc @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) Broadcom 2017-2018. All rights reserved. +# + +#include "defconfig_arm64-armv8a-linuxapp-gcc" + +# Broadcom - Stingray +CONFIG_RTE_MACHINE="armv8a" +CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72" + +# Doesn't support NUMA +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n + +CONFIG_RTE_EAL_IGB_UIO=y +CONFIG_RTE_KNI_KMOD=n diff --git a/src/spdk/dpdk/config/defconfig_arm64-thunderx-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-thunderx-linuxapp-gcc new file mode 100644 index 00000000..2bed66c6 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-thunderx-linuxapp-gcc @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2015 Cavium, Inc +# + +#include "defconfig_arm64-armv8a-linuxapp-gcc" + +CONFIG_RTE_MACHINE="thunderx" + +CONFIG_RTE_CACHE_LINE_SIZE=128 +CONFIG_RTE_MAX_NUMA_NODES=2 +CONFIG_RTE_MAX_LCORE=96 +CONFIG_RTE_MAX_VFIO_GROUPS=128 +CONFIG_RTE_RING_USE_C11_MEM_MODEL=n + +# +# Compile PMD for octeontx sso event device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF=y diff --git a/src/spdk/dpdk/config/defconfig_arm64-xgene1-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_arm64-xgene1-linuxapp-gcc new file mode 100644 index 00000000..a2dd465b --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_arm64-xgene1-linuxapp-gcc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2015 Cavium, Inc +# + +#include "defconfig_arm64-armv8a-linuxapp-gcc" + +CONFIG_RTE_MACHINE="xgene1" +CONFIG_RTE_CACHE_LINE_SIZE=64 diff --git a/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-gcc new file mode 100644 index 00000000..1178fe35 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-gcc @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="i686" +CONFIG_RTE_ARCH_I686=y +CONFIG_RTE_ARCH_X86=y + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y + +# +# KNI is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_KNI=n + +# +# Solarflare PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n + +# +# AES-NI multi-buffer PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n + +# +# AES-NI GCM PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=n + +# +# KASUMI PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_KASUMI=n + +# +# ZUC PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_ZUC=n + +# +# AVP PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_AVP_PMD=n + +# 32-bit doesn't break up memory in lists, but does have VA allocation limit +CONFIG_RTE_MAX_MEM_MB=2048 diff --git a/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-icc b/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-icc new file mode 100644 index 00000000..016c73f3 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_i686-native-linuxapp-icc @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="i686" +CONFIG_RTE_ARCH_I686=y +CONFIG_RTE_ARCH_X86=y + +CONFIG_RTE_TOOLCHAIN="icc" +CONFIG_RTE_TOOLCHAIN_ICC=y + +# +# KNI is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_KNI=n + +# +# Solarflare PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n + +# +# AES-NI multi-buffer PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n + +# +# AES-NI GCM PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=n + +# +# KASUMI PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_KASUMI=n + +# +# ZUC PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_PMD_ZUC=n + +# +# AVP PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_AVP_PMD=n + +# 32-bit doesn't break up memory in lists, but does have VA allocation limit +CONFIG_RTE_MAX_MEM_MB=2048 diff --git a/src/spdk/dpdk/config/defconfig_ppc_64-power8-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_ppc_64-power8-linuxapp-gcc new file mode 100644 index 00000000..a52e22ef --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -0,0 +1,57 @@ +# BSD LICENSE +# +# Copyright (C) IBM Corporation 2014. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of IBM Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="power8" + +CONFIG_RTE_ARCH="ppc_64" +CONFIG_RTE_ARCH_PPC_64=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_MAX_LCORE=256 +CONFIG_RTE_MAX_NUMA_NODES=32 +CONFIG_RTE_CACHE_LINE_SIZE=128 + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y + +# Note: Power doesn't have this support +CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n + +# Note: Initially, all of the PMD drivers compilation are turned off on Power +# Will turn on them only after the successful testing on Power +CONFIG_RTE_LIBRTE_IXGBE_PMD=n +CONFIG_RTE_LIBRTE_VIRTIO_PMD=y +CONFIG_RTE_LIBRTE_VMXNET3_PMD=n +CONFIG_RTE_LIBRTE_ENIC_PMD=n +CONFIG_RTE_LIBRTE_FM10K_PMD=n +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n +CONFIG_RTE_LIBRTE_AVP_PMD=n diff --git a/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-clang b/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-clang new file mode 100644 index 00000000..8d2d10b4 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-clang @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_bsdapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_64" +CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_X86=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_TOOLCHAIN="clang" +CONFIG_RTE_TOOLCHAIN_CLANG=y diff --git a/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-gcc b/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-gcc new file mode 100644 index 00000000..174a74b0 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_64-native-bsdapp-gcc @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_bsdapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_64" +CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_X86=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y diff --git a/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-clang b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-clang new file mode 100644 index 00000000..52d0d22f --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-clang @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_64" +CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_X86=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_TOOLCHAIN="clang" +CONFIG_RTE_TOOLCHAIN_CLANG=y diff --git a/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-gcc new file mode 100644 index 00000000..afa5d478 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-gcc @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_64" +CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_X86=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y diff --git a/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-icc b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-icc new file mode 100644 index 00000000..59783111 --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_64-native-linuxapp-icc @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_64" +CONFIG_RTE_ARCH_X86_64=y +CONFIG_RTE_ARCH_X86=y +CONFIG_RTE_ARCH_64=y + +CONFIG_RTE_TOOLCHAIN="icc" +CONFIG_RTE_TOOLCHAIN_ICC=y + +# +# Solarflare PMD build is not supported using icc toolchain +# +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n diff --git a/src/spdk/dpdk/config/defconfig_x86_x32-native-linuxapp-gcc b/src/spdk/dpdk/config/defconfig_x86_x32-native-linuxapp-gcc new file mode 100644 index 00000000..57d000dc --- /dev/null +++ b/src/spdk/dpdk/config/defconfig_x86_x32-native-linuxapp-gcc @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2014 Intel Corporation + +#include "common_linuxapp" + +CONFIG_RTE_MACHINE="native" + +CONFIG_RTE_ARCH="x86_x32" +CONFIG_RTE_ARCH_X86_X32=y +CONFIG_RTE_ARCH_X86=y + +CONFIG_RTE_TOOLCHAIN="gcc" +CONFIG_RTE_TOOLCHAIN_GCC=y + +# +# KNI is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_KNI=n + +# +# Solarflare PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n + +# +# AVP PMD is not supported on 32-bit +# +CONFIG_RTE_LIBRTE_AVP_PMD=n + +# 32-bit doesn't break up memory in lists, but does have VA allocation limit +CONFIG_RTE_MAX_MEM_MB=2048 diff --git a/src/spdk/dpdk/config/meson.build b/src/spdk/dpdk/config/meson.build new file mode 100644 index 00000000..4d755323 --- /dev/null +++ b/src/spdk/dpdk/config/meson.build @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation + +# set the machine type and cflags for it +if meson.is_cross_build() + machine = host_machine.cpu() +else + machine = get_option('machine') +endif +dpdk_conf.set('RTE_MACHINE', machine) +machine_args = [] +machine_args += '-march=' + machine + +toolchain = cc.get_id() +dpdk_conf.set_quoted('RTE_TOOLCHAIN', toolchain) +dpdk_conf.set('RTE_TOOLCHAIN_' + toolchain.to_upper(), 1) + +# use pthreads +add_project_link_arguments('-pthread', language: 'c') +dpdk_extra_ldflags += '-pthread' + +# some libs depend on maths lib +add_project_link_arguments('-lm', language: 'c') +dpdk_extra_ldflags += '-lm' + +# for linux link against dl, for bsd execinfo +if host_machine.system() == 'linux' + link_lib = 'dl' +else + link_lib = 'execinfo' +endif +add_project_link_arguments('-l' + link_lib, language: 'c') +dpdk_extra_ldflags += '-l' + link_lib + +# check for libraries used in multiple places in DPDK +has_libnuma = 0 +numa_dep = cc.find_library('numa', required: false) +if numa_dep.found() and cc.has_header('numaif.h') + dpdk_conf.set10('RTE_HAS_LIBNUMA', true) + has_libnuma = 1 + add_project_link_arguments('-lnuma', language: 'c') + dpdk_extra_ldflags += '-lnuma' +endif + +# check for strlcpy +if host_machine.system() == 'linux' and cc.find_library('bsd', + required: false).found() and cc.has_header('bsd/string.h') + dpdk_conf.set('RTE_USE_LIBBSD', 1) + add_project_link_arguments('-lbsd', language: 'c') + dpdk_extra_ldflags += '-lbsd' +endif + +# add -include rte_config to cflags +add_project_arguments('-include', 'rte_config.h', language: 'c') + +# enable extra warnings and disable any unwanted warnings +warning_flags = [ + '-Wsign-compare', + '-Wcast-qual', + '-Wno-address-of-packed-member' +] +if cc.sizeof('void *') == 4 +# for 32-bit, don't warn about casting a 32-bit pointer to 64-bit int - it's fine!! + warning_flags += '-Wno-pointer-to-int-cast' +endif +foreach arg: warning_flags + if cc.has_argument(arg) + add_project_arguments(arg, language: 'c') + endif +endforeach + +# set other values pulled from the build options +dpdk_conf.set('RTE_MAX_LCORE', get_option('max_lcores')) +dpdk_conf.set('RTE_MAX_NUMA_NODES', get_option('max_numa_nodes')) +dpdk_conf.set('RTE_LIBEAL_USE_HPET', get_option('use_hpet')) +dpdk_conf.set('RTE_EAL_ALLOW_INV_SOCKET_ID', get_option('allow_invalid_socket_id')) +# values which have defaults which may be overridden +dpdk_conf.set('RTE_MAX_VFIO_GROUPS', 64) +dpdk_conf.set('RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB', 64) +dpdk_conf.set('RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', true) + +compile_time_cpuflags = [] +if host_machine.cpu_family().startswith('x86') + arch_subdir = 'x86' +elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().startswith('aarch') + arch_subdir = 'arm' +endif +subdir(arch_subdir) +dpdk_conf.set('RTE_COMPILE_TIME_CPUFLAGS', ','.join(compile_time_cpuflags)) + +# set the install path for the drivers +dpdk_conf.set_quoted('RTE_EAL_PMD_PATH', eal_pmd_path) + +install_headers('rte_config.h', subdir: get_option('include_subdir_arch')) diff --git a/src/spdk/dpdk/config/rte_config.h b/src/spdk/dpdk/config/rte_config.h new file mode 100644 index 00000000..a8e47977 --- /dev/null +++ b/src/spdk/dpdk/config/rte_config.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Intel Corporation + */ + +/** + * @file Header file containing DPDK compilation parameters + * + * Header file containing DPDK compilation parameters. Also include the + * meson-generated header file containing the detected parameters that + * are variable across builds or build environments. + * + * NOTE: This file is only used for meson+ninja builds. For builds done + * using make/gmake, the rte_config.h file is autogenerated from the + * defconfig_* files in the config directory. + */ +#ifndef _RTE_CONFIG_H_ +#define _RTE_CONFIG_H_ + +#include <rte_build_config.h> + +/****** library defines ********/ + +/* EAL defines */ +#define RTE_MAX_MEMSEG_LISTS 128 +#define RTE_MAX_MEMSEG_PER_LIST 8192 +#define RTE_MAX_MEM_MB_PER_LIST 32768 +#define RTE_MAX_MEMSEG_PER_TYPE 32768 +#define RTE_MAX_MEM_MB_PER_TYPE 65536 +#define RTE_MAX_MEM_MB 524288 +#define RTE_MAX_MEMZONE 2560 +#define RTE_MAX_TAILQ 32 +#define RTE_LOG_DP_LEVEL RTE_LOG_INFO +#define RTE_BACKTRACE 1 +#define RTE_EAL_VFIO 1 +#define RTE_MAX_VFIO_CONTAINERS 64 + +/* bsd module defines */ +#define RTE_CONTIGMEM_MAX_NUM_BUFS 64 +#define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 +#define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) + +/* mempool defines */ +#define RTE_MEMPOOL_CACHE_MAX_SIZE 512 + +/* mbuf defines */ +#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" +#define RTE_MBUF_REFCNT_ATOMIC 1 +#define RTE_PKTMBUF_HEADROOM 128 + +/* ether defines */ +#define RTE_MAX_ETHPORTS 32 +#define RTE_MAX_QUEUES_PER_PORT 1024 +#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 +#define RTE_ETHDEV_RXTX_CALLBACKS 1 + +/* cryptodev defines */ +#define RTE_CRYPTO_MAX_DEVS 64 +#define RTE_CRYPTODEV_NAME_LEN 64 + +/* compressdev defines */ +#define RTE_COMPRESS_MAX_DEVS 64 + +/* eventdev defines */ +#define RTE_EVENT_MAX_DEVS 16 +#define RTE_EVENT_MAX_QUEUES_PER_DEV 64 +#define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 +#define RTE_EVENT_ETH_INTR_RING_SIZE 1024 +#define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 + +/* rawdev defines */ +#define RTE_RAWDEV_MAX_DEVS 10 + +/* ip_fragmentation defines */ +#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4 +#undef RTE_LIBRTE_IP_FRAG_TBL_STAT + +/* rte_power defines */ +#define RTE_MAX_LCORE_FREQS 64 + +/* rte_sched defines */ +#undef RTE_SCHED_RED +#undef RTE_SCHED_COLLECT_STATS +#undef RTE_SCHED_SUBPORT_TC_OV +#define RTE_SCHED_PORT_N_GRINDERS 8 +#undef RTE_SCHED_VECTOR + +/****** driver defines ********/ + +/* QuickAssist device */ +/* Max. number of QuickAssist devices which can be attached */ +#define RTE_PMD_QAT_MAX_PCI_DEVICES 48 +#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 + +/* virtio crypto defines */ +#define RTE_MAX_VIRTIO_CRYPTO 32 + +/* DPAA SEC max cryptodev devices*/ +#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 + +/* fm10k defines */ +#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 + +/* i40e defines */ +#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 +#undef RTE_LIBRTE_I40E_16BYTE_RX_DESC +#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 +#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 +#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 +/* interval up to 8160 us, aligned to 2 (or default value) */ +#define RTE_LIBRTE_I40E_ITR_INTERVAL -1 + +/* Ring net PMD settings */ +#define RTE_PMD_RING_MAX_RX_RINGS 16 +#define RTE_PMD_RING_MAX_TX_RINGS 16 + +#endif /* _RTE_CONFIG_H_ */ diff --git a/src/spdk/dpdk/config/x86/meson.build b/src/spdk/dpdk/config/x86/meson.build new file mode 100644 index 00000000..33efb5e5 --- /dev/null +++ b/src/spdk/dpdk/config/x86/meson.build @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation + +# for checking defines we need to use the correct compiler flags +march_opt = '-march=@0@'.format(machine) + +# we require SSE4.2 for DPDK +sse_errormsg = '''SSE4.2 instruction set is required for DPDK. +Please set the machine type to "nehalem" or "corei7" or higher value''' + +if cc.get_define('__SSE4_2__', args: march_opt) == '' + error(sse_errormsg) +endif + +base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2'] +foreach f:base_flags + dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1) + compile_time_cpuflags += ['RTE_CPUFLAG_' + f] +endforeach + +dpdk_conf.set('RTE_ARCH_X86', 1) +if (host_machine.cpu_family() == 'x86_64') + dpdk_conf.set('RTE_ARCH_X86_64', 1) + dpdk_conf.set('RTE_ARCH', 'x86_64') + dpdk_conf.set('RTE_ARCH_64', 1) +else + dpdk_conf.set('RTE_ARCH_I686', 1) + dpdk_conf.set('RTE_ARCH', 'i686') +endif + +if cc.get_define('__AES__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AES'] +endif +if cc.get_define('__PCLMUL__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_PCLMULQDQ', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_PCLMULQDQ'] +endif +if cc.get_define('__AVX__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AVX'] +endif +if cc.get_define('__AVX2__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AVX2'] +endif +if cc.get_define('__AVX512F__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F'] +endif + +dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) |