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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
| commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
| tree | a94efe259b9009378be6d90eb30d2b019d95c194 /Documentation/devicetree/bindings/arm | |
| parent | Initial commit. (diff) | |
| download | linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.tar.xz linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.zip | |
Adding upstream version 5.10.209.upstream/5.10.209upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
224 files changed, 16335 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml new file mode 100644 index 000000000..02dc72c97 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/actions.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/actions.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi platforms device tree bindings + +maintainers: + - Andreas Färber <afaerber@suse.de> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + $nodename: + const: "/" + compatible: + oneOf: + # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC. + - items: + - enum: + - allo,sparky # Allo.com Sparky + - cubietech,cubieboard6 # Cubietech CubieBoard6 + - roseapplepi,roseapplepi # RoseapplePi.org RoseapplePi + - const: actions,s500 + - items: + - enum: + - caninos,labrador-base-m # Labrador Base Board M v1 + - const: caninos,labrador-v2 # Labrador Core v2 + - const: actions,s500 + - items: + - enum: + - lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B + - const: lemaker,guitar + - const: actions,s500 + + # The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC. + - items: + - enum: + - caninos,labrador-base-m2 # Labrador Base Board M v2 + - const: caninos,labrador-v3 # Labrador Core v3 + - const: actions,s700 + - items: + - enum: + - cubietech,cubieboard7 # Cubietech CubieBoard7 + - const: actions,s700 + + # The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC. + - items: + - enum: + - ucrobotics,bubblegum-96 # uCRobotics Bubblegum-96 + - const: actions,s900 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml new file mode 100644 index 000000000..c15c92fdf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/altera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera's SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + $nodename: + const: "/" + compatible: + items: + - enum: + - altr,socfpga-cyclone5 + - altr,socfpga-arria5 + - altr,socfpga-arria10 + - const: altr,socfpga + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml new file mode 100644 index 000000000..572381306 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA Clock Manager + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +description: test + +properties: + compatible: + items: + - const: altr,clk-mgr + reg: + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt new file mode 100644 index 000000000..77ca63576 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Controller + +Required properties: +- compatible : Should contain "altr,sdr-ctl" and "syscon". + syscon is required by the Altera SOCFPGA SDRAM EDAC. +- reg : Should contain 1 register range (address and length) + +Example: + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 000000000..f5ad0ff69 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt @@ -0,0 +1,15 @@ +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] +The EDAC accesses a range of registers in the SDRAM controller. + +Required properties: +- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" +- altr,sdr-syscon : phandle of the sdr module +- interrupts : Should contain the SDRAM ECC IRQ in the + appropriate format for the IRQ controller. + +Example: + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt new file mode 100644 index 000000000..82edbaaa3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt @@ -0,0 +1,25 @@ +Altera SOCFPGA System Manager + +Required properties: +- compatible : "altr,sys-mgr" +- reg : Should contain 1 register ranges(address and length) +- cpu1-start-addr : CPU1 start address in hex. + +Example: + sysmgr@ffd08000 { + compatible = "altr,sys-mgr"; + reg = <0xffd08000 0x1000>; + cpu1-start-addr = <0xffd080c4>; + }; + +ARM64 - Stratix10 +Required properties: +- compatible : "altr,sys-mgr-s10" +- reg : Should contain 1 register range(address and length) + for system manager register. + +Example: + sysmgr@ffd12000 { + compatible = "altr,sys-mgr-s10"; + reg = <0xffd12000 0x228>; + }; diff --git a/Documentation/devicetree/bindings/arm/amazon,al.yaml b/Documentation/devicetree/bindings/arm/amazon,al.yaml new file mode 100644 index 000000000..0f03135d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amazon,al.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amazon,al.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings + +maintainers: + - Hanna Hawa <hhhawa@amazon.com> + - Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com> + - Ronen Krupnik <ronenk@amazon.com> + +properties: + compatible: + oneOf: + - description: Boards with Alpine V1 SoC + items: + - const: al,alpine + + - description: Boards with Alpine V2 SoC + items: + - enum: + - al,alpine-v2-evp + - const: al,alpine-v2 + + - description: Boards with Alpine V3 SoC + items: + - enum: + - amazon,al-alpine-v3-evp + - const: amazon,al-alpine-v3 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt new file mode 100644 index 000000000..5ab59da05 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -0,0 +1,27 @@ +System Control and Power Interface (SCPI) Message Protocol +(in addition to the standard binding in [0]) +---------------------------------------------------------- +Required properties + +- compatible : should be "amlogic,meson-gxbb-scpi" + +AMLOGIC SRAM and Shared Memory for SCPI +------------------------------------ + +Required properties: +- compatible : should be "amlogic,meson-gxbb-sram" + +Each sub-node represents the reserved area for SCPI. + +Required sub-node properties: +- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared + memory on Amlogic GXBB SoC. + +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "amlogic,meson-gxbb-scpi-sensors". + +[0] Documentation/devicetree/bindings/arm/arm,scpi.txt diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml new file mode 100644 index 000000000..3341788d1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic MesonX device tree bindings + +maintainers: + - Kevin Hilman <khilman@baylibre.com> + +description: |+ + Work in progress statement: + + Device tree files and bindings applying to Amlogic SoCs and boards are + considered "unstable". Any Amlogic device tree binding may change at + any time. Be sure to use a device tree binary and a kernel image + generated from the same source tree. + + Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a + stable binding/ABI. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Boards with the Amlogic Meson6 SoC + items: + - enum: + - geniatech,atv1200 + - const: amlogic,meson6 + + - description: Boards with the Amlogic Meson8 SoC + items: + - enum: + - minix,neo-x8 + - const: amlogic,meson8 + + - description: Boards with the Amlogic Meson8m2 SoC + items: + - enum: + - tronsmart,mxiii-plus + - const: amlogic,meson8m2 + + - description: Boards with the Amlogic Meson8b SoC + items: + - enum: + - endless,ec100 + - hardkernel,odroid-c1 + - tronfy,mxq + - const: amlogic,meson8b + + - description: Boards with the Amlogic Meson GXBaby SoC + items: + - enum: + - amlogic,p200 + - amlogic,p201 + - friendlyarm,nanopi-k2 + - hardkernel,odroid-c2 + - nexbox,a95x + - videostrong,kii-pro + - wetek,hub + - wetek,play2 + - const: amlogic,meson-gxbb + + - description: Tronsmart Vega S95 devices + items: + - enum: + - tronsmart,vega-s95-pro + - tronsmart,vega-s95-meta + - tronsmart,vega-s95-telos + - const: tronsmart,vega-s95 + - const: amlogic,meson-gxbb + + - description: Boards with the Amlogic Meson GXL S805X SoC + items: + - enum: + - amlogic,p241 + - libretech,aml-s805x-ac + - const: amlogic,s805x + - const: amlogic,meson-gxl + + - description: Boards with the Amlogic Meson GXL S905W SoC + items: + - enum: + - amlogic,p281 + - oranth,tx3-mini + - const: amlogic,s905w + - const: amlogic,meson-gxl + + - description: Boards with the Amlogic Meson GXL S905X SoC + items: + - enum: + - amlogic,p212 + - hwacom,amazetv + - khadas,vim + - libretech,aml-s905x-cc + - libretech,aml-s905x-cc-v2 + - nexbox,a95x + - const: amlogic,s905x + - const: amlogic,meson-gxl + + - description: Boards with the Amlogic Meson GXL S905D SoC + items: + - enum: + - amlogic,p230 + - amlogic,p231 + - libretech,aml-s905d-pc + - phicomm,n1 + - smartlabs,sml5442tw + - const: amlogic,s905d + - const: amlogic,meson-gxl + + - description: Boards with the Amlogic Meson GXM S912 SoC + items: + - enum: + - amlogic,q200 + - amlogic,q201 + - khadas,vim2 + - kingnovel,r-box-pro + - libretech,aml-s912-pc + - nexbox,a1 + - tronsmart,vega-s96 + - wetek,core2 + - const: amlogic,s912 + - const: amlogic,meson-gxm + + - description: Boards with the Amlogic Meson AXG A113D SoC + items: + - enum: + - amlogic,s400 + - const: amlogic,a113d + - const: amlogic,meson-axg + + - description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC + items: + - enum: + - amediatech,x96-max + - amlogic,u200 + - seirobotics,sei510 + - const: amlogic,g12a + + - description: Boards with the Amlogic Meson G12B A311D SoC + items: + - enum: + - khadas,vim3 + - const: amlogic,a311d + - const: amlogic,g12b + + - description: Boards with the Amlogic Meson G12B S922X SoC + items: + - enum: + - azw,gtking + - azw,gtking-pro + - hardkernel,odroid-n2 + - hardkernel,odroid-n2-plus + - khadas,vim3 + - ugoos,am6 + - const: amlogic,s922x + - const: amlogic,g12b + + - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC + items: + - enum: + - seirobotics,sei610 + - khadas,vim3l + - hardkernel,odroid-c4 + - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC + items: + - enum: + - amlogic,ad401 + - const: amlogic,a1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml new file mode 100644 index 000000000..6cc74523e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson Firmware registers Interface + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +description: | + The Meson SoCs have a register bank with status and data shared with the + secure firmware. + +# We need a select here so we don't match all nodes with 'syscon' +select: + properties: + compatible: + contains: + const: amlogic,meson-gx-ao-secure + required: + - compatible + +properties: + compatible: + items: + - const: amlogic,meson-gx-ao-secure + - const: syscon + + reg: + maxItems: 1 + + amlogic,has-chip-id: + description: | + A firmware register encodes the SoC type, package and revision + information on the Meson GX SoCs. If present, the interface gives + the current SoC version. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x140 0x140>; + amlogic,has-chip-id; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt new file mode 100644 index 000000000..101dc2101 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt @@ -0,0 +1,20 @@ +Amlogic Meson8 and Meson8b "analog top" registers: +-------------------------------------------------- + +The analog top registers contain information about the so-called +"metal revision" (which encodes the "minor version") of the SoC. + +Required properties: +- reg: the register range of the analog top registers +- compatible: depending on the SoC this should be one of: + - "amlogic,meson8-analog-top" + - "amlogic,meson8b-analog-top" + along with "syscon" + + +Example: + + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/assist.txt b/Documentation/devicetree/bindings/arm/amlogic/assist.txt new file mode 100644 index 000000000..7656812b6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/assist.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b assist registers: +----------------------------------------------- + +The assist registers contain basic information about the SoC, +for example the encoded SoC part number. + +Required properties: +- reg: the register range of the assist registers +- compatible: should be "amlogic,meson-mx-assist" along with "syscon" + + +Example: + + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt new file mode 100644 index 000000000..407e27f23 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b bootrom: +-------------------------------------- + +The bootrom register area can be used to access SoC specific +information, such as the "misc version". + +Required properties: +- reg: the register range of the bootrom registers +- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" + + +Example: + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file mode 100644 index 000000000..72f8d0819 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt @@ -0,0 +1,18 @@ +Amlogic Meson8 and Meson8b power-management-unit: +------------------------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : depending on the SoC this should be one of: + "amlogic,meson8-pmu" + "amlogic,meson8b-pmu" +- reg : physical base address and the size of the registers window + +Example: + + pmu@c81000e4 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xc81000e0 0x18>; + }; diff --git a/Documentation/devicetree/bindings/arm/apm/scu.txt b/Documentation/devicetree/bindings/arm/apm/scu.txt new file mode 100644 index 000000000..b45be0662 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/apm/scu.txt @@ -0,0 +1,17 @@ +APM X-GENE SoC series SCU Registers + +This system clock unit contain various register that control block resets, +clock enable/disables, clock divisors and other deepsleep registers. + +Properties: + - compatible : should contain two values. First value must be: + - "apm,xgene-scu" + second value must be always "syscon". + + - reg : offset and length of the register set. + +Example : + scu: system-clk-controller@17000000 { + compatible = "apm,xgene-scu","syscon"; + reg = <0x0 0x17000000 0x0 0x400>; + }; diff --git a/Documentation/devicetree/bindings/arm/arm,integrator.yaml b/Documentation/devicetree/bindings/arm/arm,integrator.yaml new file mode 100644 index 000000000..528eee642 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,integrator.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,integrator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Integrator Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + These were the first ARM platforms officially supported by ARM Ltd. + They are ARMv4, ARMv5 and ARMv6-capable using different core tiles, + so the system is modular and can host a variety of CPU tiles called + "core tiles" and referred to in the device tree as "core modules". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM Integrator Application Platform, this board has a PCI + host and several PCI slots, as well as a number of slots for logical + expansion modules, it is referred to as an "ASIC Development + Motherboard" and is extended with custom FPGA and is intended for + rapid prototyping. See ARM DUI 0098B. This board can physically come + pre-packaged in a PC Tower form factor called Integrator/PP1 or a + special metal fixture called Integrator/PP2, see ARM DUI 0169A. + items: + - const: arm,integrator-ap + - description: ARM Integrator Compact Platform (HBI-0086), this board has + a compact form factor and mainly consists of the bare minimum + peripherals to make use of the core module. See ARM DUI 0159B. + items: + - const: arm,integrator-cp + - description: ARM Integrator Standard Development Board (SDB) Platform, + this board is a PCI-based board conforming to the Microsoft SDB + (HARP) specification. See ARM DUI 0099A. + items: + - const: arm,integrator-sp + + core-module@10000000: + type: object + description: the root node in the Integrator platforms must contain + a core module child node. They are always at physical address + 0x10000000 in all the Integrator variants. + properties: + compatible: + items: + - const: arm,core-module-integrator + - const: syscon + - const: simple-mfd + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + description: All Integrator boards must provide a system controller as a + node in the root of the device tree. + type: object + properties: + compatible: + items: + - enum: + - arm,integrator-ap-syscon + - arm,integrator-cp-syscon + - arm,integrator-sp-syscon + - const: syscon + reg: + maxItems: 1 + + required: + - compatible + - reg + + +required: + - compatible + - core-module@10000000 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/arm,realview.yaml b/Documentation/devicetree/bindings/arm/arm,realview.yaml new file mode 100644 index 000000000..4f9b21f49 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,realview.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,realview.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM RealView Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + The ARM RealView series of reference designs were built to explore the ARM + 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to + the earlier CPUs such as TrustZone and multicore (MPCore). + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: ARM RealView Emulation Baseboard (HBI-0140) was created + as a generic platform to test different FPGA designs, and has + pluggable CPU modules, see ARM DUI 0303E. + items: + - const: arm,realview-eb + - description: ARM RealView Platform Baseboard for ARM1176JZF-S + (HBI-0147) was created as a development board to test ARM TrustZone, + CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F. + items: + - const: arm,realview-pb1176 + - description: ARM RealView Platform Baseboard for ARM 11 MPCore + (HBI-0159, HBI-0175 and HBI-0176) was created to showcase + multiprocessing with ARM11 using MPCore using symmetric + multiprocessing (SMP). See ARM DUI 0351E. + items: + - const: arm,realview-pb11mp + - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178, + HBI-0176 and HBI-0175) was the first reference platform for the + Cortex CPU family, including a Cortex-A8 test chip. + items: + - const: arm,realview-pba8 + - description: ARM RealView Platform Baseboard Explore for Cortex-A9 + (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9 + CPU. + items: + - const: arm,realview-pbx + + soc: + description: All RealView boards must provide a soc node in the root of the + device tree, representing the System-on-Chip since these test chips are + rather complex. + type: object + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb-soc + - const: simple-bus + - items: + - const: arm,realview-pb1176-soc + - const: simple-bus + - items: + - const: arm,realview-pb11mp-soc + - const: simple-bus + - items: + - const: arm,realview-pba8-soc + - const: simple-bus + - items: + - const: arm,realview-pbx-soc + - const: simple-bus + + patternProperties: + "^.*syscon@[0-9a-f]+$": + type: object + description: All RealView boards must provide a syscon system controller + node inside the soc node. + properties: + compatible: + oneOf: + - items: + - const: arm,realview-eb11mp-revb-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb11mp-revc-syscon + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-eb-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb1176-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pb11mp-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pba8-syscon + - const: syscon + - const: simple-mfd + - items: + - const: arm,realview-pbx-syscon + - const: syscon + - const: simple-mfd + + required: + - compatible + - reg + + required: + - compatible + +required: + - compatible + - soc + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt new file mode 100644 index 000000000..55deb6823 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -0,0 +1,197 @@ +System Control and Management Interface (SCMI) Message Protocol +---------------------------------------------------------- + +The SCMI is intended to allow agents such as OSPM to manage various functions +that are provided by the hardware platform it is running on, including power +and performance functions. + +This binding is intended to define the interface the firmware implementing +the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control +and Management Interface Platform Design Document")[0] provide for OSPM in +the device tree. + +Required properties: + +The scmi node with the following properties shall be under the /firmware/ node. + +- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports +- mboxes: List of phandle and mailbox channel specifiers. It should contain + exactly one or two mailboxes, one for transmitting messages("tx") + and another optional for receiving the notifications("rx") if + supported. +- shmem : List of phandle pointing to the shared memory(SHM) area as per + generic mailbox client binding. +- #address-cells : should be '1' if the device has sub-nodes, maps to + protocol identifier for a given sub-node. +- #size-cells : should be '0' as 'reg' property doesn't have any size + associated with it. +- arm,smc-id : SMC id required when using smc or hvc transports + +Optional properties: + +- mbox-names: shall be "tx" or "rx" depending on mboxes entries. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details +about the generic mailbox controller and client driver bindings. + +The mailbox is the only permitted method of calling the SCMI firmware. +Mailbox doorbell is used as a mechanism to alert the presence of a +messages and/or notification. + +Each protocol supported shall have a sub-node with corresponding compatible +as described in the following sections. If the platform supports dedicated +communication channel for a particular protocol, the 3 properties namely: +mboxes, mbox-names and shmem shall be present in the sub-node corresponding +to that protocol. + +Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol +------------------------------------------------------------ + +This binding uses the common clock binding[1]. + +Required properties: +- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. + +Power domain bindings for the power domains based on SCMI Message Protocol +------------------------------------------------------------ + +This binding for the SCMI power domain providers uses the generic power +domain binding[2]. + +Required properties: + - #power-domain-cells : Should be 1. Contains the device or the power + domain ID value used by SCMI commands. + +Sensor bindings for the sensors based on SCMI Message Protocol +-------------------------------------------------------------- +SCMI provides an API to access the various sensors on the SoC. + +Required properties: +- #thermal-sensor-cells: should be set to 1. This property follows the + thermal device tree bindings[3]. + + Valid cell values are raw identifiers (Sensor ID) + as used by the firmware. Refer to platform details + for your implementation for the IDs to use. + +Reset signal bindings for the reset domains based on SCMI Message Protocol +------------------------------------------------------------ + +This binding for the SCMI reset domain providers uses the generic reset +signal binding[5]. + +Required properties: + - #reset-cells : Should be 1. Contains the reset domain ID value used + by SCMI commands. + +SRAM and Shared Memory for SCMI +------------------------------- + +A small area of SRAM is reserved for SCMI communication between application +processors and SCP. + +The properties should follow the generic mmio-sram description found in [4] + +Each sub-node represents the reserved area for SCMI. + +Required sub-node properties: +- reg : The base offset and size of the reserved area with the SRAM +- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based + shared memory + +[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/power/power-domain.yaml +[3] Documentation/devicetree/bindings/thermal/thermal*.yaml +[4] Documentation/devicetree/bindings/sram/sram.yaml +[5] Documentation/devicetree/bindings/reset/reset.txt + +Example: + +sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; +}; + +mailbox@40000000 { + .... + #mbox-cells = <1>; + reg = <0x0 0x40000000 0x0 0x10000>; +}; + +firmware { + + ... + + scmi { + compatible = "arm,scmi"; + mboxes = <&mailbox 0 &mailbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; +}; + +cpu@0 { + ... + reg = <0 0>; + clocks = <&scmi_dvfs 0>; +}; + +hdlcd@7ff60000 { + ... + reg = <0 0x7ff60000 0 0x1000>; + clocks = <&scmi_clk 4>; + power-domains = <&scmi_devpd 1>; + resets = <&scmi_reset 10>; +}; + +thermal-zones { + soc_thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + /* sensor ID */ + thermal-sensors = <&scmi_sensors0 3>; + ... + }; +}; diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt new file mode 100644 index 000000000..bcd6c3ec4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -0,0 +1,219 @@ +System Control and Power Interface (SCPI) Message Protocol +---------------------------------------------------------- + +Firmware implementing the SCPI described in ARM document number ARM DUI 0922B +("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used +by Linux to initiate various system control and power operations. + +Required properties: + +- compatible : should be + * "arm,scpi" : For implementations complying to SCPI v1.0 or above + * "arm,scpi-pre-1.0" : For implementations complying to all + unversioned releases prior to SCPI v1.0 +- mboxes: List of phandle and mailbox channel specifiers + All the channels reserved by remote SCP firmware for use by + SCPI message protocol should be specified in any order +- shmem : List of phandle pointing to the shared memory(SHM) area between the + processors using these mailboxes for IPC, one for each mailbox + SHM can be any memory reserved for the purpose of this communication + between the processors. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt +for more details about the generic mailbox controller and +client driver bindings. + +Clock bindings for the clocks based on SCPI Message Protocol +------------------------------------------------------------ + +This binding uses the common clock binding[1]. + +Container Node +============== +Required properties: +- compatible : should be "arm,scpi-clocks" + All the clocks provided by SCP firmware via SCPI message + protocol much be listed as sub-nodes under this node. + +Sub-nodes +========= +Required properties: +- compatible : shall include one of the following + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based. + These clocks don't provide an entire range of values between the + limits but only discrete points within the range. The firmware + provides the mapping for each such operating frequency and the + index associated with it. The firmware also manages the + voltage scaling appropriately with the clock scaling. + "arm,scpi-variable-clocks" - all the clocks that are variable and provide full + range within the specified range. The firmware provides the + range of values within a specified range. + +Other required properties for all clocks(all from common clock binding): +- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands. +- clock-output-names : shall be the corresponding names of the outputs. +- clock-indices: The identifying number for the clocks(i.e.clock_id) in the + node. It can be non linear and hence provide the mapping of identifiers + into the clock-output-names array. + +SRAM and Shared Memory for SCPI +------------------------------- + +A small area of SRAM is reserved for SCPI communication between application +processors and SCP. + +The properties should follow the generic mmio-sram description found in [3] + +Each sub-node represents the reserved area for SCPI. + +Required sub-node properties: +- reg : The base offset and size of the reserved area with the SRAM +- compatible : should be "arm,scp-shmem" for Non-secure SRAM based + shared memory + +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "arm,scpi-sensors". +- #thermal-sensor-cells: should be set to 1. This property follows the + thermal device tree bindings[2]. + + Valid cell values are raw identifiers (Sensor ID) + as used by the firmware. Refer to platform details + for your implementation for the IDs to use. + +Power domain bindings for the power domains based on SCPI Message Protocol +------------------------------------------------------------ + +This binding uses the generic power domain binding[4]. + +PM domain providers +=================== + +Required properties: + - #power-domain-cells : Should be 1. Contains the device or the power + domain ID value used by SCPI commands. + - num-domains: Total number of power domains provided by SCPI. This is + needed as the SCPI message protocol lacks a mechanism to + query this information at runtime. + +PM domain consumers +=================== + +Required properties: + - power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. + +[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/thermal/thermal*.yaml +[3] Documentation/devicetree/bindings/sram/sram.yaml +[4] Documentation/devicetree/bindings/power/power-domain.yaml + +Example: + +sram: sram@50000000 { + compatible = "arm,juno-sram-ns", "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,juno-scp-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "arm,juno-scp-shmem"; + reg = <0x200 0x200>; + }; +}; + +mailbox: mailbox0@40000000 { + .... + #mbox-cells = <1>; +}; + +scpi_protocol: scpi@2e000000 { + compatible = "arm,scpi"; + mboxes = <&mailbox 0 &mailbox 1>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "atlclk", "aplclk","gpuclk"; + }; + scpi_clk: scpi_clocks@3 { + compatible = "arm,scpi-variable-clocks"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + }; + + scpi_sensors0: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + + scpi_devpd: scpi-power-domains { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; +}; + +cpu@0 { + ... + reg = <0 0>; + clocks = <&scpi_dvfs 0>; +}; + +hdlcd@7ff60000 { + ... + reg = <0 0x7ff60000 0 0x1000>; + clocks = <&scpi_clk 4>; + power-domains = <&scpi_devpd 1>; +}; + +thermal-zones { + soc_thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + /* sensor ID */ + thermal-sensors = <&scpi_sensors0 3>; + ... + }; +}; + +In the above example, the #clock-cells is set to 1 as required. +scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0, +1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 +and pxlclk1 with 3 and 4 as clock-indices. + +The first consumer in the example is cpu@0 and it has '0' as the clock +specifier which points to the first entry in the output clocks of +scpi_dvfs i.e. "atlclk". + +Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input +clock. '4' in the clock specifier here points to the second entry +in the output clocks of scpi_clocks i.e. "pxlclk1" + +The thermal-sensors property in the soc_thermal node uses the +temperature sensor provided by SCP firmware to setup a thermal +zone. The ID "3" is the sensor identifier for the temperature sensor +as used by the firmware. + +The num-domains property in scpi-power-domains domain specifies that +SCPI provides 2 power domains. The hdlcd node uses the power domain with +domain ID 1. diff --git a/Documentation/devicetree/bindings/arm/arm,versatile.yaml b/Documentation/devicetree/bindings/arm/arm,versatile.yaml new file mode 100644 index 000000000..34b437c72 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,versatile.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,versatile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Boards Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards + with various pluggable interface boards, in essence the Versatile PB version + is a superset of the Versatile AB version. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The ARM Versatile Application Baseboard (HBI-0118) is an + evaluation board specifically for the ARM926EJ-S. It can be connected + to an IB1 interface board for a touchscreen-type use case or an IB2 + for a candybar phone-type use case. See ARM DUI 0225D. + items: + - const: arm,versatile-ab + - description: The ARM Versatile Platform Baseboard (HBI-0117) is an + extension of the Versatile Application Baseboard that includes a + PCI host controller. Like the sibling board, it is done specifically + for ARM926EJ-S. See ARM DUI 0224B. + items: + - const: arm,versatile-pb + + core-module@10000000: + type: object + description: the root node in the Versatile platforms must contain + a core module child node. They are always at physical address + 0x10000000 in all the Versatile variants. + properties: + compatible: + items: + - const: arm,core-module-versatile + - const: syscon + - const: simple-mfd + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + type: object + description: When fitted with the IB2 Interface Board, the Versatile + AB will present an optional system controller node which controls the + extra peripherals on the interface board. + properties: + compatible: + contains: + const: arm,versatile-ib2-syscon + required: + - compatible + - reg + +required: + - compatible + - core-module@10000000 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml new file mode 100644 index 000000000..55ef656d1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express and Juno Boards Device Tree Bindings + +maintainers: + - Sudeep Holla <sudeep.holla@arm.com> + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + ARM's Versatile Express platform were built as reference designs for exploring + multicore Cortex-A class systems. The Versatile Express family contains both + 32 bit (Aarch32) and 64 bit (Aarch64) systems. + + The board consist of a motherboard and one or more daughterboards (tiles). The + motherboard provides a set of peripherals. Processor and RAM "live" on the + tiles. + + The motherboard and each core tile should be described by a separate Device + Tree source file, with the tile's description including the motherboard file + using an include directive. As the motherboard can be initialized in one of + two different configurations ("memory maps"), care must be taken to include + the correct one. + + When a new generation of boards were introduced under the name "Juno", these + shared to many common characteristics with the Versatile Express that the + "arm,vexpress" compatible was retained in the root node, and these are + included in this binding schema as well. + + The root node indicates the CPU SoC on the core tile, and this + is a daughterboard to the main motherboard. The name used in the compatible + string shall match the name given in the core tile's technical reference + manual, followed by "arm,vexpress" as an additional compatible value. If + further subvariants are released of the core tile, even more fine-granular + compatible strings with up to three compatible strings are used. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores + in MPCore configuration in a test chip on the core tile. See ARM + DUI 0448I. This was the first Versatile Express platform. + items: + - const: arm,vexpress,v2p-ca9 + - const: arm,vexpress + - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores + in a test chip on the core tile. It is intended to evaluate NEON, FPU + and Jazelle support in the Cortex A5 family. See ARM DUI 0541C. + items: + - const: arm,vexpress,v2p-ca5s + - const: arm,vexpress + - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU + cores in a MPCore configuration in a test chip on the core tile. See + ARM DUI 0604F. + items: + - const: arm,vexpress,v2p-ca15 + - const: arm,vexpress + - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex + A15 CPU cores in a test chip on the core tile. This is the first test + chip called "TC1". + items: + - const: arm,vexpress,v2p-ca15,tc1 + - const: arm,vexpress,v2p-ca15 + - const: arm,vexpress + - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15 + CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration + in a test chip on the core tile. See ARM DDI 0503I. + items: + - const: arm,vexpress,v2p-ca15_a7 + - const: arm,vexpress + - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU + cores in a test chip on the core tile. See ARM DDI 0498D. + items: + - const: arm,vexpress,v2f-1xv7,ca53x2 + - const: arm,vexpress,v2f-1xv7 + - const: arm,vexpress + - description: Arm Versatile Express Juno "r0" (the first Juno board, + V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on + AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53 + cores in a big.LITTLE configuration. It also features the MALI T624 + GPU. See ARM document 100113_0000_07_en. + items: + - const: arm,juno + - const: arm,vexpress + - description: Arm Versatile Express Juno r1 Development Platform + (V2M-Juno r1) was introduced mainly aimed at development of PCIe + based systems. Juno r1 also has support for AXI masters placed on + the TLX connectors to join the coherency domain. Otherwise it is the + same configuration as Juno r0. See ARM document 100122_0100_06_en. + items: + - const: arm,juno-r1 + - const: arm,juno + - const: arm,vexpress + - description: Arm Versatile Express Juno r2 Development Platform + (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See + ARM document 100114_0200_04_en. + items: + - const: arm,juno-r2 + - const: arm,juno + - const: arm,vexpress + - description: Arm AEMv8a Versatile Express Real-Time System Model + (VE RTSM) is a programmers view of the Versatile Express with Arm + v8A hardware. See ARM DUI 0575D. + items: + - const: arm,rtsm_ve,aemv8a + - const: arm,vexpress + - description: Arm FVP (Fixed Virtual Platform) base model revision C + See ARM Document 100964_1190_00_en. + items: + - const: arm,fvp-base-revc + - const: arm,vexpress + - description: Arm Foundation model for Aarch64 + items: + - const: arm,foundation-aarch64 + - const: arm,vexpress + + arm,hbi: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: This indicates the ARM HBI (Hardware Board ID), this is + ARM's unique board model ID, visible on the PCB's silkscreen. + + arm,vexpress,site: + description: As Versatile Express can be configured in number of physically + different setups, the device tree should describe platform topology. + For this reason the root node and main motherboard node must define this + property, describing the physical location of the children nodes. + 0 means motherboard site, while 1 and 2 are daughterboard sites, and + 0xf means "sisterboard" which is the site containing the main CPU tile. + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 15 + + arm,vexpress,position: + description: When daughterboards are stacked on one site, their position + in the stack be be described this attribute. + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 3 + + arm,vexpress,dcc: + description: When describing tiles consisting of more than one DCC, its + number can be specified with this attribute. + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 3 + +patternProperties: + "^bus@[0-9a-f]+$": + description: Static Memory Bus (SMB) node, if this exists it describes + the connection between the motherboard and any tiles. Sometimes the + compatible is placed directly under this node, sometimes it is placed + in a subnode named "motherboard". Sometimes the compatible includes + "arm,vexpress,v2?-p1" sometimes (on software models) is is just + "simple-bus". If the compatible is placed in the "motherboard" node, + it is stricter and always has two compatibles. + type: object + $ref: '/schemas/simple-bus.yaml' + + properties: + compatible: + oneOf: + - items: + - enum: + - arm,vexpress,v2m-p1 + - arm,vexpress,v2p-p1 + - const: simple-bus + - const: simple-bus + motherboard: + type: object + description: The motherboard description provides a single "motherboard" + node using 2 address cells corresponding to the Static Memory Bus + used between the motherboard and the tile. The first cell defines the + Chip Select (CS) line number, the second cell address offset within + the CS. All interrupt lines between the motherboard and the tile + are active high and are described using single cell. + properties: + "#address-cells": + const: 2 + "#size-cells": + const: 1 + compatible: + items: + - enum: + - arm,vexpress,v2m-p1 + - arm,vexpress,v2p-p1 + - const: simple-bus + arm,v2m-memory-map: + description: This describes the memory map type. + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - rs1 + - rs2 + + required: + - compatible + required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + enum: + - arm,vexpress,v2p-ca9 + - arm,vexpress,v2p-ca5s + - arm,vexpress,v2p-ca15 + - arm,vexpress,v2p-ca15_a7 + - arm,vexpress,v2f-1xv7,ca53x2 + then: + required: + - arm,hbi + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt new file mode 100644 index 000000000..6efabba53 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt @@ -0,0 +1,27 @@ +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores +with a shared L3 memory system, control logic and external interfaces to +form a multicore cluster. The PMU enables to gather various statistics on +the operations of the DSU. The PMU provides independent 32bit counters that +can count any of the supported events, along with a 64bit cycle counter. +The PMU is accessed via CPU system registers and has no MMIO component. + +** DSU PMU required properties: + +- compatible : should be one of : + + "arm,dsu-pmu" + +- interrupts : Exactly 1 SPI must be listed. + +- cpus : List of phandles for the CPUs connected to this DSU instance. + + +** Example: + +dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&cpu_0>, <&cpu_1>; +}; diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml new file mode 100644 index 000000000..6fc5a22ad --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel-at91.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91 device tree bindings. + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Ludovic Desroches <ludovic.desroches@microchip.com> + +description: | + Boards with a SoC of the Atmel AT91 or SMART family shall have the following + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: atmel,at91rm9200 + - items: + - enum: + - olimex,sam9-l9260 + - enum: + - atmel,at91sam9260 + - atmel,at91sam9261 + - atmel,at91sam9263 + - atmel,at91sam9g20 + - atmel,at91sam9g45 + - atmel,at91sam9n12 + - atmel,at91sam9rl + - atmel,at91sam9xe + - atmel,at91sam9x60 + - const: atmel,at91sam9 + + - items: + - enum: + - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board + - overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board + - overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN + - overkiz,smartkiz # Overkiz SmartKiz Board + - gardena,smart-gateway-at91sam # GARDENA smart Gateway (Article No. 19000) + - const: atmel,at91sam9g25 + - const: atmel,at91sam9x5 + - const: atmel,at91sam9 + + - items: + - enum: + - atmel,at91sam9g15 + - atmel,at91sam9g25 + - atmel,at91sam9g35 + - atmel,at91sam9x25 + - atmel,at91sam9x35 + - const: atmel,at91sam9x5 + - const: atmel,at91sam9 + + - description: Overkiz kizbox3 board + items: + - const: overkiz,kizbox3-hs + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Microchip SAMA5D27 WLSOM1 + items: + - const: microchip,sama5d27-wlsom1 + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Microchip SAMA5D27 WLSOM1 Evaluation Kit + items: + - const: microchip,sama5d27-wlsom1-ek + - const: microchip,sama5d27-wlsom1 + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - items: + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Microchip SAMA5D2 Industrial Connectivity Platform + items: + - const: microchip,sama5d2-icp + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: SAM9X60-EK board + items: + - const: microchip,sam9x60ek + - const: microchip,sam9x60 + - const: atmel,at91sam9 + + - description: Nattis v2 board with Natte v2 power board + items: + - const: axentia,nattis-2 + - const: axentia,natte-2 + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - description: TSE-850 v3 board + items: + - const: axentia,tse850v3 + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - description: Overkiz kizbox2 board with two heads + items: + - const: overkiz,kizbox2-2 + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sama5d31 + - atmel,sama5d33 + - atmel,sama5d34 + - atmel,sama5d35 + - atmel,sama5d36 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sama5d41 + - atmel,sama5d42 + - atmel,sama5d43 + - atmel,sama5d44 + - const: atmel,sama5d4 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sams70j19 + - atmel,sams70j20 + - atmel,sams70j21 + - atmel,sams70n19 + - atmel,sams70n20 + - atmel,sams70n21 + - atmel,sams70q19 + - atmel,sams70q20 + - atmel,sams70q21 + - const: atmel,sams70 + - const: atmel,samv7 + + - items: + - enum: + - atmel,samv70j19 + - atmel,samv70j20 + - atmel,samv70n19 + - atmel,samv70n20 + - atmel,samv70q19 + - atmel,samv70q20 + - const: atmel,samv70 + - const: atmel,samv7 + + - items: + - enum: + - atmel,samv71j19 + - atmel,samv71j20 + - atmel,samv71j21 + - atmel,samv71n19 + - atmel,samv71n20 + - atmel,samv71n21 + - atmel,samv71q19 + - atmel,samv71q20 + - atmel,samv71q21 + - const: atmel,samv71 + - const: atmel,samv7 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt new file mode 100644 index 000000000..62cd4e898 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -0,0 +1,193 @@ +Atmel system registers + +Chipid required properties: +- compatible: Should be "atmel,sama5d2-chipid" +- reg : Should contain registers location and length + +PIT Timer required properties: +- compatible: Should be "atmel,at91sam9260-pit" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for the PIT which is the IRQ line + shared across all System Controller members. + +PIT64B Timer required properties: +- compatible: Should be "microchip,sam9x60-pit64b" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for PIT64B timer +- clocks: Should contain the available clock sources for PIT64B timer. + +System Timer (ST) required properties: +- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for the ST which is the IRQ line + shared across all System Controller members. +- clocks: phandle to input clock. +Its subnodes can be: +- watchdog: compatible should be "atmel,at91rm9200-wdt" + +RSTC Reset Controller required properties: +- compatible: Should be "atmel,<chip>-rstc". + <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" + it also can be "microchip,sam9x60-rstc" +- reg: Should contain registers location and length +- clocks: phandle to input clock. + +Example: + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + +RAMC SDRAM/DDR Controller required properties: +- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" + "atmel,at91sam9260-sdramc", + "atmel,at91sam9g45-ddramc", + "atmel,sama5d3-ddramc", + "microchip,sam9x60-ddramc" +- reg: Should contain registers location and length + +Examples: + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + +SHDWC Shutdown Controller + +required properties: +- compatible: Should be "atmel,<chip>-shdwc". + <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". +- reg: Should contain registers location and length +- clocks: phandle to input clock. + +optional properties: +- atmel,wakeup-mode: String, operation mode of the wakeup mode. + Supported values are: "none", "high", "low", "any". +- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). + +optional at91sam9260 properties: +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9rl properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9x5 properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. + +Example: + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + +SHDWC SAMA5D2-Compatible Shutdown Controller + +1) shdwc node + +required properties: +- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc". +- reg: should contain registers location and length +- clocks: phandle to input clock. +- #address-cells: should be one. The cell is the wake-up input index. +- #size-cells: should be zero. + +optional properties: + +- debounce-delay-us: minimum wake-up inputs debouncer period in + microseconds. It's usually a board-related property. +- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. + +optional microchip,sam9x60-shdwc properties: +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +The node contains child nodes for each wake-up input that the platform uses. + +2) input nodes + +Wake-up input nodes are usually described in the "board" part of the Device +Tree. Note also that input 0 is linked to the wake-up pin and is frequently +used. + +Required properties: +- reg: should contain the wake-up input index [0 - 15]. + +Optional properties: +- atmel,wakeup-active-high: boolean, the corresponding wake-up input described + by the child, forces the wake-up of the core power supply on a high level. + The default is to be active low. + +Example: + +On the SoC side: + shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + +On the board side: + shdwc@f8048010 { + debounce-delay-us = <976>; + + input@0 { + reg = <0>; + }; + + input@1 { + reg = <1>; + atmel,wakeup-active-high; + }; + }; + +Special Function Registers (SFR) + +Special Function Registers (SFR) manage specific aspects of the integrated +memory, bridge implementations, processor and other functionality not controlled +elsewhere. + +required properties: +- compatible: Should be "atmel,<chip>-sfr", "syscon" or + "atmel,<chip>-sfrbu", "syscon" + <chip> can be "sama5d3", "sama5d4" or "sama5d2". + It also can be "microchip,sam9x60-sfr", "syscon". +- reg: Should contain registers location and length + + sfr@f0038000 { + compatible = "atmel,sama5d3-sfr", "syscon"; + reg = <0xf0038000 0x60>; + }; + +Security Module (SECUMOD) + +The Security Module macrocell provides all necessary secure functions to avoid +voltage, temperature, frequency and mechanical attacks on the chip. It also +embeds secure memories that can be scrambled. + +The Security Module also offers the PIOBU pins which can be used as GPIO pins. +Note that they maintain their voltage during Backup/Self-refresh. + +required properties: +- compatible: Should be "atmel,<chip>-secumod", "syscon". + <chip> can be "sama5d2". +- reg: Should contain registers location and length +- gpio-controller: Marks the port as GPIO controller. +- #gpio-cells: There are 2. The pin number is the + first, the second represents additional + parameters such as GPIO_ACTIVE_HIGH/LOW. + + + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt new file mode 100644 index 000000000..ae345e1c8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.txt @@ -0,0 +1,29 @@ +Axis Communications AB +ARTPEC series SoC Device Tree Bindings + +ARTPEC-6 ARM SoC +================ + +Required root node properties: +- compatible = "axis,artpec6"; + +ARTPEC-6 System Controller +-------------------------- + +The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe +and resets. + +Required properties: +- compatible: "axis,artpec6-syscon", "syscon" +- reg: Address and length of the register bank. + +Example: + syscon { + compatible = "axis,artpec6-syscon", "syscon"; + reg = <0xf8000000 0x48>; + }; + +ARTPEC-6 Development board: +--------------------------- +Required root node properties: +- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axxia.yaml b/Documentation/devicetree/bindings/arm/axxia.yaml new file mode 100644 index 000000000..e0d2bb71c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axxia.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axxia.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axxia AXM55xx device tree bindings + +maintainers: + - Anders Berg <anders.berg@lsi.com> + +properties: + $nodename: + const: "/" + compatible: + description: LSI AXM5516 Validation board (Amarillo) + items: + - const: lsi,axm5516-amarillo + - const: lsi,axm5516 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml new file mode 100644 index 000000000..812ae8cc5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings + +maintainers: + - Eric Anholt <eric@anholt.net> + - Stefan Wahren <wahrenst@gmx.net> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM2711 based Boards + items: + - enum: + - raspberrypi,4-model-b + - const: brcm,bcm2711 + + - description: BCM2835 based Boards + items: + - enum: + - raspberrypi,model-a + - raspberrypi,model-a-plus + - raspberrypi,model-b + - raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5) + - raspberrypi,model-b-rev2 + - raspberrypi,model-b-plus + - raspberrypi,compute-module + - raspberrypi,model-zero + - raspberrypi,model-zero-w + - const: brcm,bcm2835 + + - description: BCM2836 based Boards + items: + - enum: + - raspberrypi,2-model-b + - const: brcm,bcm2836 + + - description: BCM2837 based Boards + items: + - enum: + - raspberrypi,3-model-a-plus + - raspberrypi,3-model-b + - raspberrypi,3-model-b-plus + - raspberrypi,3-compute-module + - raspberrypi,3-compute-module-lite + - const: brcm,bcm2837 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml new file mode 100644 index 000000000..c60324357 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM11351 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm28155-ap + - const: brcm,bcm11351 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml new file mode 100644 index 000000000..b30207573 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm21664-garnet + - const: brcm,bcm21664 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml new file mode 100644 index 000000000..37f3a6fcd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM23550 device tree bindings + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm23550-sparrow + - const: brcm,bcm23550 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml new file mode 100644 index 000000000..434d3c6db --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4708 device tree bindings + +description: + Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based + on the iProc architecture (Northstar). + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Hauke Mehrtens <hauke@hauke-m.de> + - Rafal Milecki <zajec5@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM4708 based boards + items: + - enum: + - asus,rt-ac56u + - asus,rt-ac68u + - buffalo,wzr-1750dhp + - linksys,ea6300-v1 + - linksys,ea6500-v2 + - luxul,xap-1510v1 + - luxul,xwc-1000 + - netgear,r6250v1 + - netgear,r6300v2 + - smartrg,sr400ac + - brcm,bcm94708 + - const: brcm,bcm4708 + + - description: BCM47081 based boards + items: + - enum: + - asus,rt-n18u + - buffalo,wzr-600dhp2 + - buffalo,wzr-900dhp + - luxul,xap-1410v1 + - luxul,xwr-1200v1 + - tplink,archer-c5-v2 + - const: brcm,bcm47081 + - const: brcm,bcm4708 + + - description: BCM4709 based boards + items: + - enum: + - asus,rt-ac87u + - buffalo,wxr-1900dhp + - linksys,ea9200 + - netgear,r7000 + - netgear,r8000 + - tplink,archer-c9-v1 + - brcm,bcm94709 + - const: brcm,bcm4709 + - const: brcm,bcm4708 + + - description: BCM47094 based boards + items: + - enum: + - dlink,dir-885l + - linksys,panamera + - luxul,abr-4500-v1 + - luxul,xap-1610-v1 + - luxul,xbr-4500-v1 + - luxul,xwc-2000-v1 + - luxul,xwr-3100v1 + - luxul,xwr-3150-v1 + - netgear,r8500 + - phicomm,k3 + - const: brcm,bcm47094 + - const: brcm,bcm4708 + + - description: BCM53012 based boards + items: + - enum: + - brcm,bcm953012er + - brcm,bcm953012hr + - brcm,bcm953012k + - meraki,mr32 + - const: brcm,brcm53012 + - const: brcm,brcm53016 + - const: brcm,bcm4708 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt new file mode 100644 index 000000000..8c7a4908a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt @@ -0,0 +1,85 @@ +Broadcom BCM63138 DSL System-on-a-Chip device tree bindings +----------------------------------------------------------- + +Boards compatible with the BCM63138 DSL System-on-a-Chip should have the +following properties: + +Required root node property: + +compatible: should be "brcm,bcm63138" + +An optional Boot lookup table Device Tree node is required for secondary CPU +initialization as well as a 'resets' phandle to the correct PMB controller as +defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an +'enable-method' property. + +Required properties for the Boot lookup table node: +- compatible: should be "brcm,bcm63138-bootlut" +- reg: register base address and length for the Boot Lookup table + +Optional properties for the primary CPU node: +- enable-method: should be "brcm,bcm63138" + +Optional properties for the secondary CPU node: +- enable-method: should be "brcm,bcm63138" +- resets: phandle to the relevant PMB controller, one integer indicating the internal + bus number, and a second integer indicating the address of the CPU in the PMB + internal bus number. + +Example: + + cpus { + cpu@0 { + compatible = "arm,cotex-a9"; + reg = <0>; + ... + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + ... + enable-method = "brcm,bcm63138"; + resets = <&pmb0 4 1>; + }; + }; + + bootlut: bootlut@8000 { + compatible = "brcm,bcm63138-bootlut"; + reg = <0x8000 0x50>; + }; + +======= +reboot +------ +Two nodes are required for software reboot: a timer node and a syscon-reboot node. + +Timer node: + +- compatible: Must be "brcm,bcm6328-timer", "syscon" +- reg: Register base address and length + +Syscon reboot node: + +See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the +detailed list of properties, the two values defined below are specific to the +BCM6328-style timer: + +- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register + from the beginning of the TIMER block +- mask: Should be 1 for the SoftRst bit. + +Example: + + timer: timer@80 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x80 0x3c>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <0x1>; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt new file mode 100644 index 000000000..104cc9b41 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -0,0 +1,265 @@ +ARM Broadcom STB platforms Device Tree Bindings +----------------------------------------------- +Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants) +SoC shall have the following DT organization: + +Required root node properties: + - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb" + +example: +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Broadcom STB (bcm7445)"; + compatible = "brcm,bcm7445", "brcm,brcmstb"; + +Further, syscon nodes that map platform-specific registers used for general +system control is required: + + - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon" + - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl", + "brcm,brcmstb-cpu-biu-ctrl", + "syscon" + - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon" + +cpu-biu-ctrl node +------------------- +SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a +specific Bus Interface Unit (BIU) block which controls and interfaces the CPU +complex to the different Memory Controller Ports (MCP), one per memory +controller (MEMC). This BIU block offers a feature called Write Pairing which +consists in collapsing two adjacent cache lines into a single (bursted) write +transaction towards the memory controller (MEMC) to maximize write bandwidth. + +Required properties: + + - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon" + +Optional properties: + + - brcm,write-pairing: + Boolean property, which when present indicates that the chip + supports write-pairing. + +example: + rdb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x00 0xf0000000 0x1000000>; + + sun_top_ctrl: syscon@404000 { + compatible = "brcm,bcm7445-sun-top-ctrl", "syscon"; + reg = <0x404000 0x51c>; + }; + + hif_cpubiuctrl: syscon@3e2400 { + compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"; + reg = <0x3e2400 0x5b4>; + brcm,write-pairing; + }; + + hif_continuation: syscon@452000 { + compatible = "brcm,bcm7445-hif-continuation", "syscon"; + reg = <0x452000 0x100>; + }; + }; + +Nodes that allow for support of SMP initialization and reboot are required: + +smpboot +------- +Required properties: + + - compatible + The string "brcm,brcmstb-smpboot". + + - syscon-cpu + A phandle / integer array property which lets the BSP know the location + of certain CPU power-on registers. + + The layout of the property is as follows: + o a phandle to the "hif_cpubiuctrl" syscon node + o offset to the base CPU power zone register + o offset to the base CPU reset register + + - syscon-cont + A phandle pointing to the syscon node which describes the CPU boot + continuation registers. + o a phandle to the "hif_continuation" syscon node + +example: + smpboot { + compatible = "brcm,brcmstb-smpboot"; + syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; + syscon-cont = <&hif_continuation>; + }; + +reboot +------- +Required properties + + - compatible + The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with + the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm + chips with the old SUN_TOP_CTRL interface. + + - syscon + A phandle / integer array that points to the syscon node which describes + the general system reset registers. + o a phandle to "sun_top_ctrl" + o offset to the "reset source enable" register + o offset to the "software master reset" register + +example: + reboot { + compatible = "brcm,brcmstb-reboot"; + syscon = <&sun_top_ctrl 0x304 0x308>; + }; + + + +Power management +---------------- + +For power management (particularly, S2/S3/S5 system suspend), the following SoC +components are needed: + += Always-On control block (AON CTRL) + +This hardware provides control registers for the "always-on" (even in low-power +modes) hardware, such as the Power Management State Machine (PMSM). + +Required properties: +- compatible : should contain "brcm,brcmstb-aon-ctrl" +- reg : the register start and length for the AON CTRL block + +Example: + +aon-ctrl@410000 { + compatible = "brcm,brcmstb-aon-ctrl"; + reg = <0x410000 0x400>; +}; + += Memory controllers + +A Broadcom STB SoC typically has a number of independent memory controllers, +each of which may have several associated hardware blocks, which are versioned +independently (control registers, DDR PHYs, etc.). One might consider +describing these controllers as a parent "memory controllers" block, which +contains N sub-nodes (one for each controller in the system), each of which is +associated with a number of hardware register resources (e.g., its PHY). See +the example device tree snippet below. + +== MEMC (MEMory Controller) + +Represents a single memory controller instance. + +Required properties: +- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" + +Should contain subnodes for any of the following relevant hardware resources: + +== DDR PHY control + +Control registers for this memory controller's DDR PHY. + +Required properties: +- compatible : should contain one of these + "brcm,brcmstb-ddr-phy-v71.1" + "brcm,brcmstb-ddr-phy-v72.0" + "brcm,brcmstb-ddr-phy-v225.1" + "brcm,brcmstb-ddr-phy-v240.1" + "brcm,brcmstb-ddr-phy-v240.2" + +- reg : the DDR PHY register range + +== DDR SHIMPHY + +Control registers for this memory controller's DDR SHIMPHY. + +Required properties: +- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0" +- reg : the DDR SHIMPHY register range + +== MEMC DDR control + +Sequencer DRAM parameters and control registers. Used for Self-Refresh +Power-Down (SRPD), among other things. + +Required properties: +- compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" + "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" + "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" + "brcm,brcmstb-memc-ddr" +- reg : the MEMC DDR register range + +Example: + +memory_controllers { + ranges; + compatible = "simple-bus"; + + memc@0 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + ranges; + + ddr-phy@f1106000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0xf1106000 0x21c>; + }; + + shimphy@f1108000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0xf1108000 0xe4>; + }; + + memc-ddr@f1102000 { + reg = <0xf1102000 0x800>; + compatible = "brcm,brcmstb-memc-ddr"; + }; + }; + + memc@1 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + ranges; + + ddr-phy@f1186000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0xf1186000 0x21c>; + }; + + shimphy@f1188000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0xf1188000 0xe4>; + }; + + memc-ddr@f1182000 { + reg = <0xf1182000 0x800>; + compatible = "brcm,brcmstb-memc-ddr"; + }; + }; + + memc@2 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + ranges; + + ddr-phy@f1206000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0xf1206000 0x21c>; + }; + + shimphy@f1208000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0xf1208000 0xe4>; + }; + + memc-ddr@f1202000 { + reg = <0xf1202000 0x800>; + compatible = "brcm,brcmstb-memc-ddr"; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml new file mode 100644 index 000000000..432ccf990 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Cygnus device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm11300 + - brcm,bcm11320 + - brcm,bcm11350 + - brcm,bcm11360 + - brcm,bcm58300 + - brcm,bcm58302 + - brcm,bcm58303 + - brcm,bcm58305 + - const: brcm,cygnus + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml new file mode 100644 index 000000000..294948399 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Hurricane 2 device tree bindings + +description: + Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs + are based on Broadcom's iProc SoC architecture and feature a single core Cortex + A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND + flash and a PCIe attached integrated switching engine. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - ubnt,unifi-switch8 + - const: brcm,bcm53342 + - const: brcm,hr2 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml new file mode 100644 index 000000000..c4847abbe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom North Star 2 (NS2) device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,ns2-svk + - brcm,ns2-xmc + - const: brcm,ns2 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml new file mode 100644 index 000000000..476bc23a7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar Plus device tree bindings + +description: + Broadcom Northstar Plus family of SoCs are used for switching control + and management applications as well as residential router/gateway + applications. The SoC features dual core Cortex A9 ARM CPUs, integrating + several peripheral interfaces including multiple Gigabit Ethernet PHYs, + DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, + SATA and several other IO controllers. + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm58522 + - brcm,bcm58525 + - brcm,bcm58535 + - brcm,bcm58622 + - brcm,bcm58623 + - brcm,bcm58625 + - brcm,bcm88312 + - const: brcm,nsp + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml new file mode 100644 index 000000000..c638e04eb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Stingray device tree bindings + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,bcm958742k + - brcm,bcm958742t + - brcm,bcm958802a802x + - const: brcm,stingray + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml new file mode 100644 index 000000000..4eba182ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Vulcan device tree bindings + +maintainers: + - Robert Richter <rrichter@marvell.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - brcm,vulcan-eval + - cavium,thunderx2-cn9900 + - const: brcm,vulcan-soc + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml new file mode 100644 index 000000000..a2c63c8b1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi VideoCore firmware driver + +maintainers: + - Eric Anholt <eric@anholt.net> + - Stefan Wahren <wahrenst@gmx.net> + +select: + properties: + compatible: + contains: + const: raspberrypi,bcm2835-firmware + + required: + - compatible + +properties: + compatible: + items: + - const: raspberrypi,bcm2835-firmware + - const: simple-mfd + + mboxes: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Phandle to the firmware device's Mailbox. + (See: ../mailbox/mailbox.txt for more information) + + clocks: + type: object + + properties: + compatible: + const: raspberrypi,firmware-clocks + + "#clock-cells": + const: 1 + description: > + The argument is the ID of the clocks contained by the + firmware messages. + + required: + - compatible + - "#clock-cells" + + reset: + type: object + + properties: + compatible: + const: raspberrypi,firmware-reset + + "#reset-cells": + const: 1 + description: > + The argument is the ID of the firmware reset line to affect. + + required: + - compatible + - "#reset-cells" + + additionalProperties: false + +required: + - compatible + - mboxes + +additionalProperties: false + +examples: + - | + firmware { + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + mboxes = <&mailbox>; + + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/bitmain.yaml b/Documentation/devicetree/bindings/arm/bitmain.yaml new file mode 100644 index 000000000..90ba02be4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bitmain.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bitmain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain platform device tree bindings + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + $nodename: + const: "/" + compatible: + items: + - enum: + - bitmain,sophon-edge + - const: bitmain,bm1880 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/calxeda.yaml b/Documentation/devicetree/bindings/arm/calxeda.yaml new file mode 100644 index 000000000..46f78adde --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Platforms Device Tree Bindings + +maintainers: + - Rob Herring <robh@kernel.org> +description: |+ + Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC + or Cortex-A15 based ECX-2000 SOCs + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - calxeda,highbank + - calxeda,ecx-2000 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml new file mode 100644 index 000000000..dfdc97083 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank system registers + +description: | + The Calxeda Highbank system has a block of MMIO registers controlling + several generic system aspects. Those can be used to control some power + management, they also contain some gate and PLL clocks. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + compatible: + const: calxeda,hb-sregs + + reg: + maxItems: 1 + + clocks: + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 000000000..a9fe01238 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + items: + - description: single bit error interrupt + - description: double bit error interrupt + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt new file mode 100644 index 000000000..6f63a5866 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt @@ -0,0 +1,10 @@ +Cavium Thunder platform device tree bindings +-------------------------------------------- + +Boards with Cavium's Thunder SoC shall have following properties. + +Root Node +--------- +Required root node properties: + + - compatible = "cavium,thunder-88xx"; diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 000000000..dc5dd65cb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt new file mode 100644 index 000000000..9600761f2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -0,0 +1,224 @@ +======================================================= +ARM CCI cache coherent interconnect binding description +======================================================= + +ARM multi-cluster systems maintain intra-cluster coherency through a +cache coherent interconnect (CCI) that is capable of monitoring bus +transactions and manage coherency, TLB invalidations and memory barriers. + +It allows snooping and distributed virtual memory message broadcast across +clusters, through memory mapped interface, with a global control register +space and multiple sets of interface control registers, one per slave +interface. + +* CCI interconnect node + + Description: Describes a CCI cache coherent Interconnect component + + Node name must be "cci". + Node's parent must be the root node /, and the address space visible + through the CCI interconnect is the same as the one seen from the + root node (ie from CPUs perspective as per DT standard). + Every CCI node has to define the following properties: + + - compatible + Usage: required + Value type: <string> + Definition: must contain one of the following: + "arm,cci-400" + "arm,cci-500" + "arm,cci-550" + + - reg + Usage: required + Value type: Integer cells. A register entry, expressed as a pair + of cells, containing base and size. + Definition: A standard property. Specifies base physical + address of CCI control registers common to all + interfaces. + + - ranges: + Usage: required + Value type: Integer cells. An array of range entries, expressed + as a tuple of cells, containing child address, + parent address and the size of the region in the + child address space. + Definition: A standard property. Follow rules in the Devicetree + Specification for hierarchical bus addressing. CCI + interfaces addresses refer to the parent node + addressing scheme to declare their register bases. + + CCI interconnect node can define the following child nodes: + + - CCI control interface nodes + + Node name must be "slave-if". + Parent node must be CCI interconnect node. + + A CCI control interface node must contain the following + properties: + + - compatible + Usage: required + Value type: <string> + Definition: must be set to + "arm,cci-400-ctrl-if" + + - interface-type: + Usage: required + Value type: <string> + Definition: must be set to one of {"ace", "ace-lite"} + depending on the interface type the node + represents. + + - reg: + Usage: required + Value type: Integer cells. A register entry, expressed + as a pair of cells, containing base and + size. + Definition: the base address and size of the + corresponding interface programming + registers. + + - CCI PMU node + + Parent node must be CCI interconnect node. + + A CCI pmu node must contain the following properties: + + - compatible + Usage: required + Value type: <string> + Definition: Must contain one of: + "arm,cci-400-pmu,r0" + "arm,cci-400-pmu,r1" + "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has + secure access to CCI registers + "arm,cci-500-pmu,r0" + "arm,cci-550-pmu,r0" + - reg: + Usage: required + Value type: Integer cells. A register entry, expressed + as a pair of cells, containing base and + size. + Definition: the base address and size of the + corresponding interface programming + registers. + + - interrupts: + Usage: required + Value type: Integer cells. Array of interrupt specifier + entries, as defined in + ../interrupt-controller/interrupts.txt. + Definition: list of counter overflow interrupts, one per + counter. The interrupts must be specified + starting with the cycle counter overflow + interrupt, followed by counter0 overflow + interrupt, counter1 overflow interrupt,... + ,counterN overflow interrupt. + + The CCI PMU has an interrupt signal for each + counter. The number of interrupts must be + equal to the number of counters. + +* CCI interconnect bus masters + + Description: masters in the device tree connected to a CCI port + (inclusive of CPUs and their cpu nodes). + + A CCI interconnect bus master node must contain the following + properties: + + - cci-control-port: + Usage: required + Value type: <phandle> + Definition: a phandle containing the CCI control interface node + the master is connected to. + +Example: + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x1>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x100>; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x101>; + }; + + }; + + dma0: dma@3000000 { + compatible = "arm,pl330", "arm,primecell"; + cci-control-port = <&cci_control0>; + reg = <0x0 0x3000000 0x0 0x1000>; + interrupts = <10>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu"; + reg = <0x9000 0x5000>; + interrupts = <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>, + <0 105 4>; + }; + }; + +This CCI node corresponds to a CCI component whose control registers sits +at address 0x000000002c090000. +CCI slave interface @0x000000002c091000 is connected to dma controller dma0. +CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1}; +CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3}; diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 000000000..f1de3247c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,49 @@ +* CoreSight CPU Debug Component: + +CoreSight CPU debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be "arm,coresight-cpu-debug"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the CPU phandle the debug module is affined to. Do not assume it + to default to CPU0 if omitted. + +Optional properties: + +- power-domains: a phandle to the debug power domain. We use "power-domains" + binding to turn on the debug logic if it has own dedicated + power domain and if necessary to use "cpuidle.off=1" or + "nohlt" in the kernel command line or sysfs node to + constrain idle states to ensure registers in the CPU power + domain are accessible. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/coresight-cti.yaml new file mode 100644 index 000000000..21e351549 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cti.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Cross Trigger Interface (CTI) device. + +description: | + The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected + to one or more CoreSight components and/or a CPU, with CTIs interconnected in + a star topology via the Cross Trigger Matrix (CTM), which is not programmable. + The ECT components are not part of the trace generation data path and are thus + not part of the CoreSight graph described in the general CoreSight bindings + file coresight.txt. + + The CTI component properties define the connections between the individual + CTI and the components it is directly connected to, consisting of input and + output hardware trigger signals. CTIs can have a maximum number of input and + output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The + number is defined at design time, the maximum of each defined in the DEVID + register. + + CTIs are interconnected in a star topology via the CTM, using a number of + programmable channels, usually 4, but again implementation defined and + described in the DEVID register. The star topology is not required to be + described in the bindings as the actual connections are software + programmable. + + In general the connections between CTI and components via the trigger signals + are implementation defined, except when the CTI is connected to an ARM v8 + architecture core and optional ETM. + + In this case the ARM v8 architecture defines the required signal connections + between CTI and the CPU core and ETM if present. In the case of a v8 + architecturally connected CTI an additional compatible string is used to + indicate this feature (arm,coresight-cti-v8-arch). + + When CTI trigger connection information is unavailable then a minimal driver + binding can be declared with no explicit trigger signals. This will result + the driver detecting the maximum available triggers and channels from the + DEVID register and make them all available for use as a single default + connection. Any user / client application will require additional information + on the connections between the CTI and other components for correct operation. + This information might be found by enabling the Integration Test registers in + the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel + configuration). These registers may be used to explore the trigger connections + between CTI and other CoreSight components. + + Certain triggers between CoreSight devices and the CTI have specific types + and usages. These can be defined along with the signal indexes with the + constants defined in <dt-bindings/arm/coresight-cti-dt.h> + + For example a CTI connected to a core will usually have a DBGREQ signal. This + is defined in the binding as type PE_EDBGREQ. These types will appear in an + optional array alongside the signal indexes. Omitting types will default all + signals to GEN_IO. + + Note that some hardware trigger signals can be connected to non-CoreSight + components (e.g. UART etc) depending on hardware implementation. + +maintainers: + - Mike Leach <mike.leach@linaro.org> + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - arm,coresight-cti + required: + - compatible + +properties: + $nodename: + pattern: "^cti(@[0-9a-f]+)$" + compatible: + oneOf: + - items: + - const: arm,coresight-cti + - const: arm,primecell + - items: + - const: arm,coresight-cti-v8-arch + - const: arm,coresight-cti + - const: arm,primecell + + reg: + maxItems: 1 + + cpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Handle to cpu this device is associated with. This must appear in the + base cti node if compatible string arm,coresight-cti-v8-arch is used, + or may appear in a trig-conns child node when appropriate. + + arm,cti-ctm-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the CTM this CTI is connected to, in large systems with multiple + separate CTI/CTM nets. Typically multi-socket systems where the CTM is + propagated between sockets. + + arm,cs-dev-assoc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + defines a phandle reference to an associated CoreSight trace device. + When the associated trace device is enabled, then the respective CTI + will be enabled. Use in a trig-conns node, or in CTI base node when + compatible string arm,coresight-cti-v8-arch used. If the associated + device has not been registered then the node name will be stored as + the connection name for later resolution. If the associated device is + not a CoreSight device or not registered then the node name will remain + the connection name and automatic enabling will not occur. + + # size cells and address cells required if trig-conns node present. + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + +patternProperties: + '^trig-conns@([0-9]+)$': + type: object + description: + A trigger connections child node which describes the trigger signals + between this CTI and another hardware device. This device may be a CPU, + CoreSight device, any other hardware device or simple external IO lines. + The connection may have both input and output triggers, or only one or the + other. + + properties: + reg: + maxItems: 1 + + arm,trig-in-sigs: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger in signal numbers in use by a trig-conns node. + + arm,trig-in-types: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger in + signals. Types in this array match to the corresponding signal in the + arm,trig-in-sigs array. If the -types array is smaller, or omitted + completely, then the types will default to GEN_IO. + + arm,trig-out-sigs: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signal numbers in use by a trig-conns node. + + arm,trig-out-types: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger out + signals. Types in this array match to the corresponding signal + in the arm,trig-out-sigs array. If the "-types" array is smaller, + or omitted completely, then the types will default to GEN_IO. + + arm,trig-filters: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signals that will be blocked from becoming + active, unless filtering is disabled on the driver. + + arm,trig-conn-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Defines a connection name that will be displayed, if the cpu or + arm,cs-dev-assoc properties are not being used in this connection. + Principle use for CTI that are connected to non-CoreSight devices, or + external IO. + + anyOf: + - required: + - arm,trig-in-sigs + - required: + - arm,trig-out-sigs + oneOf: + - required: + - arm,trig-conn-name + - required: + - cpu + - required: + - arm,cs-dev-assoc + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + const: arm,coresight-cti-v8-arch + +then: + required: + - cpu + +unevaluatedProperties: false + +examples: + # minimum CTI definition. DEVID register used to set number of triggers. + - | + cti@20020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20020000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + # v8 architecturally defined CTI - CPU + ETM connections generated by the + # driver according to the v8 architecture specification. + - | + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + # Implementation defined CTI - CPU + ETM connections explicitly defined.. + # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h + # #size-cells and #address-cells are required if trig-conns@ nodes present. + - | + #include <dt-bindings/arm/coresight-cti-dt.h> + + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + arm,cti-ctm-id = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <ETM_EXTOUT + ETM_EXTOUT + ETM_EXTOUT + ETM_EXTOUT>; + arm,trig-out-sigs = <4 5 6 7>; + arm,trig-out-types = <ETM_EXTIN + ETM_EXTIN + ETM_EXTIN + ETM_EXTIN>; + arm,cs-dev-assoc = <&etm0>; + }; + + trig-conns@1 { + reg = <1>; + cpu = <&CPU0>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <PE_DBGTRIGGER + PE_PMUIRQ>; + arm,trig-out-sigs=<0 1 2 >; + arm,trig-out-types = <PE_EDBGREQ + PE_DBGRESTART + PE_CTIIRQ>; + + arm,trig-filters = <0>; + }; + }; + # Implementation defined CTI - non CoreSight component connections. + - | + cti@20110000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20110000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=<GEN_INTREQ>; + arm,trig-out-sigs=<0>; + arm,trig-out-types=<GEN_HALTREQ>; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<1 6>; + arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "g_counter"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt new file mode 100644 index 000000000..d711676b4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -0,0 +1,394 @@ +* CoreSight Components: + +CoreSight components are compliant with the ARM CoreSight architecture +specification and can be connected in various topologies to suit a particular +SoCs tracing needs. These trace components can generally be classified as +sinks, links and sources. Trace data produced by one or more sources flows +through the intermediate links connecting the source to the currently selected +sink. Each CoreSight component device should use these properties to describe +its hardware characteristcs. + +* Required properties for all components *except* non-configurable replicators + and non-configurable funnels: + + * compatible: These have to be supplemented with "arm,primecell" as + drivers are using the AMBA bus interface. Possible values include: + - Embedded Trace Buffer (version 1.0): + "arm,coresight-etb10", "arm,primecell"; + + - Trace Port Interface Unit: + "arm,coresight-tpiu", "arm,primecell"; + + - Trace Memory Controller, used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) + configuration. The configuration mode (ETB, ETF, ETR) is + discovered at boot time when the device is probed. + "arm,coresight-tmc", "arm,primecell"; + + - Trace Programmable Funnel: + "arm,coresight-dynamic-funnel", "arm,primecell"; + "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For + backward compatibility and will be removed) + + - Embedded Trace Macrocell (version 3.x) and + Program Flow Trace Macrocell: + "arm,coresight-etm3x", "arm,primecell"; + + - Embedded Trace Macrocell (version 4.x): + "arm,coresight-etm4x", "arm,primecell"; + + - Coresight programmable Replicator : + "arm,coresight-dynamic-replicator", "arm,primecell"; + + - System Trace Macrocell: + "arm,coresight-stm", "arm,primecell"; [1] + - Coresight Address Translation Unit (CATU) + "arm,coresight-catu", "arm,primecell"; + + - Coresight Cross Trigger Interface (CTI): + "arm,coresight-cti", "arm,primecell"; + See coresight-cti.yaml for full CTI definitions. + + * reg: physical base address and length of the register + set(s) of the component. + + * clocks: the clocks associated to this component. + + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. + + * port or ports: see "Graph bindings for Coresight" below. + +* Additional required property for Embedded Trace Macrocell (version 3.x and + version 4.x): + * cpu: the cpu phandle this ETM/PTM is affined to. Do not + assume it to default to CPU0 if omitted. + +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + +* Required properties for Coresight Cross Trigger Interface (CTI) + See coresight-cti.yaml for full CTI definitions. + +* Required properties for devices that don't show up on the AMBA bus, such as + non-configurable replicators and non-configurable funnels: + + * compatible: Currently supported value is (note the absence of the + AMBA markee): + - Coresight Non-configurable Replicator: + "arm,coresight-static-replicator"; + "arm,coresight-replicator"; (OBSOLETE. For backward + compatibility and will be removed) + + - Coresight Non-configurable Funnel: + "arm,coresight-static-funnel"; + + * port or ports: see "Graph bindings for Coresight" below. + +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + +* Optional properties for ETM/PTMs: + + * arm,cp14: must be present if the system accesses ETM/PTM management + registers via co-processor 14. + + * qcom,skip-power-up: boolean. Indicates that an implementation can + skip powering up the trace unit. TRCPDCR.PU does not have to be set + on Qualcomm Technologies Inc. systems since ETMs are in the same power + domain as their CPU cores. This property is required to identify such + systems with hardware errata where the CPU watchdog counter is stopped + when TRCPDCR.PU is set. + +* Optional property for TMC: + + * arm,buffer-size: size of contiguous buffer space for TMC ETR + (embedded trace router). This property is obsolete. The buffer size + can be configured dynamically via buffer_size property in sysfs. + + * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely + use the SG mode on this system. + +* Optional property for CATU : + * interrupts : Exactly one SPI may be listed for reporting the address + error + +* Optional property for configurable replicators: + + * qcom,replicator-loses-context: boolean. Indicates that the replicator + will lose register context when AMBA clock is removed which is observed + in some replicator designs. + +Graph bindings for Coresight +------------------------------- + +Coresight components are interconnected to create a data path for the flow of +trace data generated from the "sources" to their collection points "sink". +Each coresight component must describe the "input" and "output" connections. +The connections must be described via generic DT graph bindings as described +by the "bindings/graph.txt", where each "port" along with an "endpoint" +component represents a hardware port and the connection. + + * All output ports must be listed inside a child node named "out-ports" + * All input ports must be listed inside a child node named "in-ports". + * Port address must match the hardware port number. + +Example: + +1. Sinks + etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in_port: endpoint@0 { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint@0 { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + + out-ports { + port { + etr_out_port: endpoint { + remote-endpoint = <&catu_in_port>; + }; + }; + }; + }; + +2. Links + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; + + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + combo_funnel_out: endpoint { + remote-endpoint = <&top_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + combo_funnel_in0: endpoint { + remote-endpoint = <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + combo_funnel_in1: endpoint { + remote-endpoint = <&cluster1_etf_out>; + }; + }; + }; + }; + + funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel_out_port0: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + }; + }; + +3. Sources + ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201c000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201d000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + }; + +5. CATU + + catu@207e0000 { + compatible = "arm,coresight-catu", "arm,primecell"; + reg = <0 0x207e0000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + in-ports { + port { + catu_in_port: endpoint { + remote-endpoint = <&etr_out_port>; + }; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name. diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/arm/cpu-capacity.txt new file mode 100644 index 000000000..380e21c5f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-capacity.txt @@ -0,0 +1,238 @@ +========================================== +ARM CPUs capacity bindings +========================================== + +========================================== +1 - Introduction +========================================== + +ARM systems may be configured to have cpus with different power/performance +characteristics within the same chip. In this case, additional information has +to be made available to the kernel for it to be aware of such differences and +take decisions accordingly. + +========================================== +2 - CPU capacity definition +========================================== + +CPU capacity is a number that provides the scheduler information about CPUs +heterogeneity. Such heterogeneity can come from micro-architectural differences +(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run +(e.g., SMP systems with multiple frequency domains). Heterogeneity in this +context is about differing performance characteristics; this binding tries to +capture a first-order approximation of the relative performance of CPUs. + +CPU capacities are obtained by running a suitable benchmark. This binding makes +no guarantees on the validity or suitability of any particular benchmark, the +final capacity should, however, be: + +* A "single-threaded" or CPU affine benchmark +* Divided by the running frequency of the CPU executing the benchmark +* Not subject to dynamic frequency scaling of the CPU + +For the time being we however advise usage of the Dhrystone benchmark. What +above thus becomes: + +CPU capacities are obtained by running the Dhrystone benchmark on each CPU at +max frequency (with caches enabled). The obtained DMIPS score is then divided +by the frequency (in MHz) at which the benchmark has been run, so that +DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest +score obtained in the system. + +========================================== +3 - capacity-dmips-mhz +========================================== + +capacity-dmips-mhz is an optional cpu node [1] property: u32 value +representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the +maximum frequency available to the cpu is then used to calculate the capacity +value internally used by the kernel. + +capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu +node, it has to be specified for every other cpu nodes, or the system will +fall back to the default capacity value for every CPU. If cpufreq is not +available, final capacities are calculated by directly using capacity-dmips- +mhz values (normalized w.r.t. the highest value found while parsing the DT). + +=========================================== +4 - Examples +=========================================== + +Example 1 (ARM 64-bit, 6-cpu system, two clusters): +The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024) +are 1024 and 578 for cluster0 and cluster1. Further normalization +is done by the operating system based on cluster0@max-freq=1100 and +custer1@max-freq=850, final capacities are 1024 for cluster0 and +446 for cluster1 (576*850/1100). + +cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <800>; + exit-latency-us = <700>; + min-residency-us = <2500>; + }; + }; + + A57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + }; + + A57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + }; + + A53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; + }; + + A57_L2: l2-cache0 { + compatible = "cache"; + }; + + A53_L2: l2-cache1 { + compatible = "cache"; + }; +}; + +Example 2 (ARM 32-bit, 4-cpu system, two clusters, + cpus 0,1@1GHz, cpus 2,3@500MHz): +capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first +cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency) + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + capacity-dmips-mhz = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + capacity-dmips-mhz = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + capacity-dmips-mhz = <1>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + capacity-dmips-mhz = <1>; + }; +}; + +=========================================== +5 - References +=========================================== + +[1] ARM Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/arm/cpus.yaml diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp new file mode 100644 index 000000000..35e5afb6d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp @@ -0,0 +1,80 @@ +======================================================== +Secondary CPU enable-method "al,alpine-smp" binding +======================================================== + +This document describes the "al,alpine-smp" method for +enabling secondary CPUs. To apply to all CPUs, a single +"al,alpine-smp" enable method should be defined in the +"cpus" node. + +Enable method name: "al,alpine-smp" +Compatible machines: "al,alpine" +Compatible CPUs: "arm,cortex-a15" +Related properties: (none) + +Note: +This enable method requires valid nodes compatible with +"al,alpine-cpu-resume" and "al,alpine-nb-service". + + +* Alpine CPU resume registers + +The CPU resume register are used to define required resume address after +reset. + +Properties: +- compatible : Should contain "al,alpine-cpu-resume". +- reg : Offset and length of the register set for the device + + +* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". +- reg : Offset and length of the register set for the device + + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; +}; + +cpu_resume { + compatible = "al,alpine-cpu-resume"; + reg = <0xfbff5ed0 0x30>; +}; + +nb_service { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0xfb070000 0x10000>; +}; diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp new file mode 100644 index 000000000..cd236b727 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp @@ -0,0 +1,41 @@ +======================================================== +Secondary CPU enable-method "marvell,berlin-smp" binding +======================================================== + +This document describes the "marvell,berlin-smp" method for enabling secondary +CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should +be defined in the "cpus" node. + +Enable method name: "marvell,berlin-smp" +Compatible machines: "marvell,berlin2" and "marvell,berlin2q" +Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"marvell,berlin-cpu-ctrl"[1]. + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,berlin-smp"; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + }; + +-- +[1] arm/marvell,berlin.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp new file mode 100644 index 000000000..8e043301e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp @@ -0,0 +1,42 @@ +========================================================= +Secondary CPU enable-method "nuvoton,npcm750-smp" binding +========================================================= + +To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be +defined in the "cpus" node. + +Enable method name: "nuvoton,npcm750-smp" +Compatible machines: "nuvoton,npcm750" +Compatible CPUs: "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"nuvoton,npcm750-gcr". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml new file mode 100644 index 000000000..14cd727d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -0,0 +1,537 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CPUs bindings + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + + with updates for 32-bit and 64-bit ARM systems provided in this document. + + ================================ + Convention used in this document + ================================ + + This document follows the conventions described in the Devicetree + Specification, with the addition: + + - square brackets define bitfields, eg reg[7:0] value of the bitfield in + the reg property contained in bits 7 down to 0 + + ===================================== + cpus and cpu node bindings definition + ===================================== + + The ARM architecture, in accordance with the Devicetree Specification, + requires the cpus and cpu nodes to be present and contain the properties + described below. + +properties: + reg: + maxItems: 1 + description: | + Usage and definition depend on ARM architecture version and + configuration: + + On uniprocessor ARM architectures previous to v7 + this property is required and must be set to 0. + + On ARM 11 MPcore based systems this property is + required and matches the CPUID[11:0] register bits. + + Bits [11:0] in the reg cell must be set to + bits [11:0] in CPU ID register. + + All other bits in the reg cell must be set to 0. + + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. + + On ARM v8 64-bit systems this property is required + and matches the MPIDR_EL1 register affinity bits. + + * If cpus node's #address-cells property is set to 2 + + The first reg cell bits [7:0] must be set to + bits [39:32] of MPIDR_EL1. + + The second reg cell bits [23:0] must be set to + bits [23:0] of MPIDR_EL1. + + * If cpus node's #address-cells property is set to 1 + + The reg cell bits [23:0] must be set to bits [23:0] + of MPIDR_EL1. + + All other bits in the reg cells must be set to 0. + + compatible: + enum: + - arm,arm710t + - arm,arm720t + - arm,arm740t + - arm,arm7ej-s + - arm,arm7tdmi + - arm,arm7tdmi-s + - arm,arm9es + - arm,arm9ej-s + - arm,arm920t + - arm,arm922t + - arm,arm925 + - arm,arm926e-s + - arm,arm926ej-s + - arm,arm940t + - arm,arm946e-s + - arm,arm966e-s + - arm,arm968e-s + - arm,arm9tdmi + - arm,arm1020e + - arm,arm1020t + - arm,arm1022e + - arm,arm1026ej-s + - arm,arm1136j-s + - arm,arm1136jf-s + - arm,arm1156t2-s + - arm,arm1156t2f-s + - arm,arm1176jzf + - arm,arm1176jz-s + - arm,arm1176jzf-s + - arm,arm11mpcore + - arm,armv8 # Only for s/w models + - arm,cortex-a5 + - arm,cortex-a7 + - arm,cortex-a8 + - arm,cortex-a9 + - arm,cortex-a12 + - arm,cortex-a15 + - arm,cortex-a17 + - arm,cortex-a32 + - arm,cortex-a34 + - arm,cortex-a35 + - arm,cortex-a53 + - arm,cortex-a55 + - arm,cortex-a57 + - arm,cortex-a65 + - arm,cortex-a72 + - arm,cortex-a73 + - arm,cortex-a75 + - arm,cortex-a76 + - arm,cortex-a77 + - arm,cortex-m0 + - arm,cortex-m0+ + - arm,cortex-m1 + - arm,cortex-m3 + - arm,cortex-m4 + - arm,cortex-r4 + - arm,cortex-r5 + - arm,cortex-r7 + - arm,neoverse-e1 + - arm,neoverse-n1 + - brcm,brahma-b15 + - brcm,brahma-b53 + - brcm,vulcan + - cavium,thunder + - cavium,thunder2 + - faraday,fa526 + - intel,sa110 + - intel,sa1100 + - marvell,feroceon + - marvell,mohawk + - marvell,pj4a + - marvell,pj4b + - marvell,sheeva-v5 + - marvell,sheeva-v7 + - nvidia,tegra132-denver + - nvidia,tegra186-denver + - nvidia,tegra194-carmel + - qcom,krait + - qcom,kryo + - qcom,kryo260 + - qcom,kryo280 + - qcom,kryo385 + - qcom,kryo468 + - qcom,kryo485 + - qcom,scorpion + + enable-method: + $ref: '/schemas/types.yaml#/definitions/string' + oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - aspeed,ast2600-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - marvell,mmp3-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp + - ste,dbx500-smp + - ti,am3352 + - ti,am4372 + + cpu-release-addr: + $ref: '/schemas/types.yaml#/definitions/uint64' + + description: + Required for systems that have an "enable-method" + property value of "spin-table". + On ARM v8 64-bit systems must be a two cell + property identifying a 64-bit zero-initialised + memory location. + + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + List of phandles to idle state nodes supported + by this cpu (see ./idle-states.yaml). + + capacity-dmips-mhz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + u32 value representing CPU capacity (see ./cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the CPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider (see also ../power_domain.txt). + + power-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of power domain name strings sorted in the same order as the + power-domains property. + + For PSCI based platforms, the name corresponding to the index of the PSCI + PM domain provider, must be "psci". + + qcom,saw: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the SAW* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,saw2.txt + + qcom,acc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the ACC* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,kpss-acc.txt + + rockchip,pmu: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the syscon node controlling the cpu core power domains. + + Optional for systems that have an "enable-method" + property value of "rockchip,rk3066-smp" + While optional, it is the preferred way to get access to + the cpu-core power-domains. + + secondary-boot-reg: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Required for systems that have an "enable-method" property value of + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". + + This includes the following SoCs: | + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + + The secondary-boot-reg property is a u32 value that specifies the + physical address of the register used to request the ROM holding pen + code release a secondary CPU. The value written to the register is + formed by encoding the target CPU id into the low bits of the + physical start address it should jump to. + +if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + +then: + required: + - secondary-boot-reg + +required: + - device_type + - reg + - compatible + +dependencies: + rockchip,pmu: [enable-method] + +additionalProperties: true + +examples: + - | + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + }; + }; + + - | + // Example 2 (Cortex-A8 uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + - | + // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + - | + // Example 4 (ARM Cortex-A57 64-bit system): + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/digicolor.yaml b/Documentation/devicetree/bindings/arm/digicolor.yaml new file mode 100644 index 000000000..a35de3c9e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/digicolor.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/digicolor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor Platforms Device Tree Bindings + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +properties: + $nodename: + const: "/" + compatible: + const: cnxt,cx92755 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt new file mode 100644 index 000000000..d38834c67 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt @@ -0,0 +1,31 @@ +OP-TEE Device Tree Bindings + +OP-TEE is a piece of software using hardware features to provide a Trusted +Execution Environment. The security can be provided with ARM TrustZone, but +also by virtualization or a separate chip. + +We're using "linaro" as the first part of the compatible property for +the reference implementation maintained by Linaro. + +* OP-TEE based on ARM TrustZone required properties: + +- compatible : should contain "linaro,optee-tz" + +- method : The method of calling the OP-TEE Trusted OS. Permitted + values are: + + "smc" : SMC #0, with the register assignments specified + in drivers/tee/optee/optee_smc.h + + "hvc" : HVC #0, with the register assignments specified + in drivers/tee/optee/optee_smc.h + + + +Example: + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/firmware/sdei.txt b/Documentation/devicetree/bindings/arm/firmware/sdei.txt new file mode 100644 index 000000000..ee3f0ff49 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/sdei.txt @@ -0,0 +1,42 @@ +* Software Delegated Exception Interface (SDEI) + +Firmware implementing the SDEI functions described in ARM document number +ARM DEN 0054A ("Software Delegated Exception Interface") can be used by +Linux to receive notification of events such as those generated by +firmware-first error handling, or from an IRQ that has been promoted to +a firmware-assisted NMI. + +The interface provides a number of API functions for registering callbacks +and enabling/disabling events. Functions are invoked by trapping to the +privilege level of the SDEI firmware (specified as part of the binding +below) and passing arguments in a manner specified by the "SMC Calling +Convention (ARM DEN 0028B): + + r0 => 32-bit Function ID / return value + {r1 - r3} => Parameters + +Note that the immediate field of the trapping instruction must be set +to #0. + +The SDEI_EVENT_REGISTER function registers a callback in the kernel +text to handle the specified event number. + +The sdei node should be a child node of '/firmware' and have required +properties: + + - compatible : should contain: + * "arm,sdei-1.0" : For implementations complying to SDEI version 1.x. + + - method : The method of calling the SDEI firmware. Permitted + values are: + * "smc" : SMC #0, with the register assignments specified in this + binding. + * "hvc" : HVC #0, with the register assignments specified in this + binding. +Example: + firmware { + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt new file mode 100644 index 000000000..780d0392a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt @@ -0,0 +1,20 @@ +Trusted Foundations +------------------- + +Boards that use the Trusted Foundations secure monitor can signal its +presence by declaring a node compatible with "tlm,trusted-foundations" +under the /firmware/ node + +Required properties: +- compatible: "tlm,trusted-foundations" +- tlm,version-major: major version number of Trusted Foundations firmware +- tlm,version-minor: minor version number of Trusted Foundations firmware + +Example: + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml new file mode 100644 index 000000000..3b26040f8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP Power Management Components + +maintainers: + - A.s. Dong <aisheng.dong@nxp.com> + +description: | + The Multi-System Mode Controller (MSMC) is responsible for sequencing + the MCU into and out of all stop and run power modes. Specifically, it + monitors events to trigger transitions between power modes while + controlling the power, clocks, and memories of the MCU to achieve the + power consumption and functionality of that mode. + + The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or + Standby modes for either Cortex family. Run, Wait, and Stop are the + common terms used for the primary operating modes of Kinetis + microcontrollers. + +properties: + compatible: + const: fsl,imx7ulp-smc1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml new file mode 100644 index 000000000..526f508cb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP System Integration Module + +maintainers: + - Anson Huang <anson.huang@nxp.com> + +description: | + The system integration module (SIM) provides system control and chip configuration + registers. In this module, chip revision information is located in JTAG ID register, + and a set of registers have been made available in DGO domain for SW use, with the + objective to maintain its value between system resets. + +properties: + compatible: + items: + - const: fsl,imx7ulp-sim + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt new file mode 100644 index 000000000..b5cb374dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt @@ -0,0 +1,19 @@ +Freescale DCFG + +DCFG is the device configuration unit, that provides general purpose +configuration and status for the device. Such as setting the secondary +core start address and release the secondary core from holdoff and startup. + +Required properties: + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,<chip>-dcfg", + The following <chip>s are known to be supported: + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + + - reg : should contain base address and length of DCFG memory-mapped registers + +Example: + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt new file mode 100644 index 000000000..0ab67b0b2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt @@ -0,0 +1,19 @@ +Freescale SCFG + +SCFG is the supplemental configuration unit, that provides SoC specific +configuration and status registers for the chip. Such as getting PEX port +status. + +Required properties: + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,<chip>-scfg", + The following <chip>s are known to be supported: + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + + - reg: should contain base address and length of SCFG memory-mapped registers + +Example: + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt new file mode 100644 index 000000000..6064d98b1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -0,0 +1,270 @@ +NXP i.MX System Controller Firmware (SCFW) +-------------------------------------------------------------------- + +The System Controller Firmware (SCFW) is a low-level system function +which runs on a dedicated Cortex-M core to provide power, clock, and +resource management. It exists on some i.MX8 processors. e.g. i.MX8QM +(QM, QP), and i.MX8QX (QXP, DX). + +The AP communicates with the SC using a multi-ported MU module found +in the LSIO subsystem. The current definition of this MU module provides +5 remote AP connections to the SC to support up to 5 execution environments +(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces +with the LSIO DSC IP bus. The SC firmware will communicate with this MU +using the MSI bus. + +System Controller Device Node: +============================================================ + +The scu node with the following properties shall be under the /firmware/ node. + +Required properties: +------------------- +- compatible: should be "fsl,imx-scu". +- mbox-names: should include "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3"; + include "gip3" if want to support general MU interrupt. +- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for + rx, and 1 optional MU channel for general interrupt. + All MU channels must be in the same MU instance. + Cross instances are not allowed. The MU instance can only + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need + to make sure use the one which is not conflict with other + execution environments. e.g. ATF. + Note: + Channel 0 must be "tx0" or "rx0". + Channel 1 must be "tx1" or "rx1". + Channel 2 must be "tx2" or "rx2". + Channel 3 must be "tx3" or "rx3". + General interrupt rx channel must be "gip3". + e.g. + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml + for detailed mailbox binding. + +Note: Each mu which supports general interrupt should have an alias correctly +numbered in "aliases" node. +e.g. +aliases { + mu1 = &lsio_mu1; +}; + +i.MX SCU Client Device Node: +============================================================ + +Client nodes are maintained as children of the relevant IMX-SCU device node. + +Power domain bindings based on SCU Message Protocol +------------------------------------------------------------ + +This binding for the SCU power domain providers uses the generic power +domain binding[2]. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qm-scu-pd", + "fsl,imx8qxp-scu-pd" + followed by "fsl,scu-pd" + +- #power-domain-cells: Must be 1. Contains the Resource ID used by + SCU commands. + See detailed Resource ID list from: + include/dt-bindings/firmware/imx/rsrc.h + +Clock bindings based on SCU Message Protocol +------------------------------------------------------------ + +This binding uses the common clock binding[1]. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qm-clock" + "fsl,imx8qxp-clock" + followed by "fsl,scu-clk" +- #clock-cells: Should be 1. Contains the Clock ID value. +- clocks: List of clock specifiers, must contain an entry for + each required entry in clock-names +- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. + +See the full list of clock IDs from: +include/dt-bindings/clock/imx8qxp-clock.h + +Pinctrl bindings based on SCU Message Protocol +------------------------------------------------------------ + +This binding uses the i.MX common pinctrl binding[3]. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qm-iomuxc", + "fsl,imx8qxp-iomuxc", + "fsl,imx8dxl-iomuxc". + +Required properties for Pinctrl sub nodes: +- fsl,pins: Each entry consists of 3 integers which represents + the mux and config setting for one pin. The first 2 + integers <pin_id mux_mode> are specified using a + PIN_FUNC_ID macro, which can be found in + <dt-bindings/pinctrl/pads-imx8qm.h>, + <dt-bindings/pinctrl/pads-imx8qxp.h>, + <dt-bindings/pinctrl/pads-imx8dxl.h>. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX8QXP Reference Manual for detailed + CONFIG settings. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/power/power-domain.yaml +[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + +RTC bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be "fsl,imx8qxp-sc-rtc"; + +OCOTP bindings based on SCU Message Protocol +------------------------------------------------------------ +Required properties: +- compatible: Should be one of: + "fsl,imx8qm-scu-ocotp", + "fsl,imx8qxp-scu-ocotp". +- #address-cells: Must be 1. Contains byte index +- #size-cells: Must be 1. Contains byte length + +Optional Child nodes: + +- Data cells of ocotp: + Detailed bindings are described in bindings/nvmem/nvmem.txt + +Watchdog bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be: + "fsl,imx8qxp-sc-wdt" + followed by "fsl,imx-sc-wdt"; +Optional properties: +- timeout-sec: contains the watchdog timeout in seconds. + +SCU key bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be: + "fsl,imx8qxp-sc-key" + followed by "fsl,imx-sc-key"; +- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml + +Thermal bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: Should be : + "fsl,imx8qxp-sc-thermal" + followed by "fsl,imx-sc-thermal"; + +- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml + for a description. + +Example (imx8qxp): +------------- +aliases { + mu1 = &lsio_mu1; +}; + +lsio_mu1: mailbox@5d1c0000 { + ... + #mbox-cells = <2>; +}; + +firmware { + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + clk: clk { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <1>; + }; + + iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + ... + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 8>; + }; + }; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; + + scu_key: scu-key { + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycodes = <KEY_POWER>; + }; + + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; +}; + +serial@5a060000 { + ... + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; +}; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt new file mode 100644 index 000000000..44aa3c451 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt @@ -0,0 +1,14 @@ +Freescale Vybrid Miscellaneous System Control - CPU Configuration + +The MSCM IP contains multiple sub modules, this binding describes the first +block of registers which contains CPU configuration information. + +Required properties: +- compatible: "fsl,vf610-mscm-cpucfg", "syscon" +- reg: the register range of the MSCM CPU configuration registers + +Example: + mscm_cpucfg: cpucfg@40001000 { + compatible = "fsl,vf610-mscm-cpucfg", "syscon"; + reg = <0x40001000 0x800>; + } diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt new file mode 100644 index 000000000..6dd6f3992 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt @@ -0,0 +1,30 @@ +Freescale Vybrid Miscellaneous System Control - Interrupt Router + +The MSCM IP contains multiple sub modules, this binding describes the second +block of registers which control the interrupt router. The interrupt router +allows to configure the recipient of each peripheral interrupt. Furthermore +it controls the directed processor interrupts. The module is available in all +Vybrid SoC's but is only really useful in dual core configurations (VF6xx +which comes with a Cortex-A5/Cortex-M4 combination). + +Required properties: +- compatible: "fsl,vf610-mscm-ir" +- reg: the register range of the MSCM Interrupt Router +- fsl,cpucfg: The handle to the MSCM CPU configuration node, required + to get the current CPU ID +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: Two cells, interrupt number and cells. + The hardware interrupt number according to interrupt + assignment of the interrupt router is required. + Flags get passed only when using GIC as parent. Flags + encoding as documented by the GIC bindings. + +Example: + mscm_ir: interrupt-controller@40001800 { + compatible = "fsl,vf610-mscm-ir"; + reg = <0x40001800 0x400>; + fsl,cpucfg = <&mscm_cpucfg>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + } diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt new file mode 100644 index 000000000..93bd7b867 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/m4if.txt @@ -0,0 +1,12 @@ +* Freescale Multi Master Multi Memory Interface (M4IF) module + +Required properties: +- compatible : Should be "fsl,imx51-m4if" +- reg : Address and length of the register set for the device + +Example: + +m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt new file mode 100644 index 000000000..19e2aad63 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt @@ -0,0 +1,12 @@ +* Freescale Tigerp platform module + +Required properties: +- compatible : Should be "fsl,imx51-tigerp" +- reg : Address and length of the register set for the device + +Example: + +tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; +}; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml new file mode 100644 index 000000000..934289446 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -0,0 +1,626 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/fsl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Platforms Device Tree Bindings + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + - Li Yang <leoyang.li@nxp.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: i.MX1 based Boards + items: + - enum: + - armadeus,imx1-apf9328 + - fsl,imx1ads + - const: fsl,imx1 + + - description: i.MX23 based Boards + items: + - enum: + - fsl,imx23-evk + - olimex,imx23-olinuxino + - const: fsl,imx23 + + - description: i.MX25 Product Development Kit + items: + - enum: + - fsl,imx25-pdk + - const: fsl,imx25 + + - description: i.MX27 Product Development Kit + items: + - enum: + - armadeus,imx27-apf27 # APF27 SoM + - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board + - fsl,imx27-pdk + - const: fsl,imx27 + + - description: i.MX28 based Boards + items: + - enum: + - armadeus,imx28-apf28 # APF28 SoM + - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board + - fsl,imx28-evk + - i2se,duckbill + - i2se,duckbill-2 + - technologic,imx28-ts4600 + - const: fsl,imx28 + - description: i.MX28 Duckbill 2 based Boards + items: + - enum: + - i2se,duckbill-2-485 + - i2se,duckbill-2-enocean + - i2se,duckbill-2-spi + - const: i2se,duckbill-2 + - const: fsl,imx28 + + - description: i.MX31 based Boards + items: + - enum: + - buglabs,imx31-bug + - logicpd,imx31-lite + - const: fsl,imx31 + + - description: i.MX35 based Boards + items: + - enum: + - fsl,imx35-pdk + - const: fsl,imx35 + + - description: i.MX35 Eukrea CPUIMX35 Board + items: + - const: eukrea,mbimxsd35-baseboard + - const: eukrea,cpuimx35 + - const: fsl,imx35 + + - description: i.MX50 based Boards + items: + - enum: + - fsl,imx50-evk + - kobo,aura + - const: fsl,imx50 + + - description: i.MX51 Babbage Board + items: + - enum: + - armadeus,imx51-apf51 # APF51 SoM + - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board + - fsl,imx51-babbage + - technologic,imx51-ts4800 + - const: fsl,imx51 + + - description: i.MX53 based Boards + items: + - enum: + - bhf,cx9020 + - fsl,imx53-ard + - fsl,imx53-evk + - fsl,imx53-qsb + - fsl,imx53-smd + - menlo,m53menlo + - const: fsl,imx53 + + - description: i.MX6Q based Boards + items: + - enum: + - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM + - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board + - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM + - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base + - fsl,imx6q-arm2 + - fsl,imx6q-sabreauto + - fsl,imx6q-sabrelite + - fsl,imx6q-sabresd + - kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module + - logicpd,imx6q-logicpd + - prt,prti6q # Protonic PRTI6Q board + - prt,prtwd2 # Protonic WD2 board + - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf + - technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit + - technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph + - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi + - technologic,imx6q-ts4900 + - technologic,imx6q-ts7970 + - toradex,apalis_imx6q # Apalis iMX6 Module + - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board + - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora + - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1 + - variscite,dt6customboard + - const: fsl,imx6q + + - description: i.MX6Q Gateworks Ventana Boards + items: + - enum: + - gw,imx6q-gw51xx + - gw,imx6q-gw52xx + - gw,imx6q-gw53xx + - gw,imx6q-gw5400-a + - gw,imx6q-gw54xx + - gw,imx6q-gw551x + - gw,imx6q-gw552x + - gw,imx6q-gw553x + - gw,imx6q-gw560x + - gw,imx6q-gw5903 + - gw,imx6q-gw5904 + - gw,imx6q-gw5907 + - gw,imx6q-gw5910 + - gw,imx6q-gw5912 + - gw,imx6q-gw5913 + - const: gw,ventana + - const: fsl,imx6q + + - description: i.MX6Q PHYTEC phyBOARD-Mira + items: + - enum: + - phytec,imx6q-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK + - phytec,imx6q-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK + - const: phytec,imx6q-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6q + + - description: i.MX6Q PHYTEC phyFLEX-i.MX6 + items: + - const: phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board + - const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad + - const: fsl,imx6q + + - description: i.MX6QP based Boards + items: + - enum: + - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board + - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board + - const: fsl,imx6qp + + - description: i.MX6QP PHYTEC phyBOARD-Mira + items: + - const: phytec,imx6qp-pbac06-nand + - const: phytec,imx6qp-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6qp + + - description: i.MX6DL based Boards + items: + - enum: + - armadeus,imx6dl-apf6 # APF6 (Solo) SoM + - armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board + - eckelmann,imx6dl-ci4x10 + - emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM + - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base + - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board + - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module + - prt,prtrvt # Protonic RVT board + - prt,prtvt7 # Protonic VT7 board + - technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf + - technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit + - technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph + - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi + - technologic,imx6dl-ts4900 + - technologic,imx6dl-ts7970 + - toradex,colibri_imx6dl # Colibri iMX6 Module + - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1 + - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 + - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3 + - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board + - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board + - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board + - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board + - const: fsl,imx6dl + + - description: i.MX6DL Gateworks Ventana Boards + items: + - enum: + - gw,imx6dl-gw51xx + - gw,imx6dl-gw52xx + - gw,imx6dl-gw53xx + - gw,imx6dl-gw54xx + - gw,imx6dl-gw551x + - gw,imx6dl-gw552x + - gw,imx6dl-gw553x + - gw,imx6dl-gw560x + - gw,imx6dl-gw5903 + - gw,imx6dl-gw5904 + - gw,imx6dl-gw5907 + - gw,imx6dl-gw5910 + - gw,imx6dl-gw5912 + - gw,imx6dl-gw5913 + - const: gw,ventana + - const: fsl,imx6dl + + - description: i.MX6DL PHYTEC phyBOARD-Mira + items: + - enum: + - phytec,imx6dl-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK + - phytec,imx6dl-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK + - const: phytec,imx6dl-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6dl + + - description: i.MX6DL PHYTEC phyFLEX-i.MX6 + items: + - const: phytec,imx6dl-pbab01 # PHYTEC phyFLEX carrier board + - const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad + - const: fsl,imx6dl + + - description: i.MX6SL based Boards + items: + - enum: + - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board + - kobo,tolino-shine2hd + - kobo,tolino-shine3 + - const: fsl,imx6sl + + - description: i.MX6SLL based Boards + items: + - enum: + - fsl,imx6sll-evk + - kobo,clarahd + - const: fsl,imx6sll + + - description: i.MX6SX based Boards + items: + - enum: + - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board + - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board + - fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board + - const: fsl,imx6sx + + - description: i.MX6UL based Boards + items: + - enum: + - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM + - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board + - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board + - kontron,imx6ul-n6310-som # Kontron N6310 SOM + - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf + - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit + - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi + - const: fsl,imx6ul + + - description: i.MX6UL PHYTEC phyBOARD-Segin + items: + - enum: + - phytec,imx6ul-pbacd10-emmc + - phytec,imx6ul-pbacd10-nand + - const: phytec,imx6ul-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 UL + - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL + - const: fsl,imx6ul + + - description: Kontron N6310 S Board + items: + - const: kontron,imx6ul-n6310-s + - const: kontron,imx6ul-n6310-som + - const: fsl,imx6ul + + - description: Kontron N6311 S Board + items: + - const: kontron,imx6ul-n6311-s + - const: kontron,imx6ul-n6311-som + - const: fsl,imx6ul + + - description: Kontron N6310 S 43 Board + items: + - const: kontron,imx6ul-n6310-s-43 + - const: kontron,imx6ul-n6310-s + - const: kontron,imx6ul-n6310-som + - const: fsl,imx6ul + + - description: i.MX6ULL based Boards + items: + - enum: + - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM + - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board + - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - kontron,imx6ull-n6411-som # Kontron N6411 SOM + - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board + - const: fsl,imx6ull + + - description: i.MX6ULL PHYTEC phyBOARD-Segin + items: + - enum: + - phytec,imx6ull-pbacd10-emmc + - phytec,imx6ull-pbacd10-nand + - const: phytec,imx6ull-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + + - description: Kontron N6411 S Board + items: + - const: kontron,imx6ull-n6411-s + - const: kontron,imx6ull-n6411-som + - const: fsl,imx6ull + + - description: i.MX6ULZ based Boards + items: + - enum: + - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board + - const: fsl,imx6ull # This seems odd. Should be last? + - const: fsl,imx6ulz + + - description: i.MX7S based Boards + items: + - enum: + - toradex,colibri-imx7s # Colibri iMX7 Solo Module + - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board + - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 + - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM + - const: fsl,imx7s + + - description: i.MX7D based Boards + items: + - enum: + - fsl,imx7d-sdb # i.MX7 SabreSD Board + - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board + - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board + - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf + - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit + - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph + - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi + - toradex,colibri-imx7d # Colibri iMX7 Dual Module + - toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board + - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module + - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on + # Aster Carrier Board + - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on + # Colibri Evaluation Board V3 + - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on + # Colibri Evaluation Board V3 + - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM + - zii,imx7d-rmu2 # ZII RMU2 Board + - zii,imx7d-rpu2 # ZII RPU2 Board + - const: fsl,imx7d + + - description: + Compulab SBC-iMX7 is a single board computer based on the + Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with + the CL-SOM-iMX7 System-on-Module providing most of the functions, + and SB-SOM-iMX7 carrier board providing additional peripheral + functions and connectors. + items: + - const: compulab,sbc-imx7 + - const: compulab,cl-som-imx7 + - const: fsl,imx7d + + - description: i.MX7ULP based Boards + items: + - enum: + - ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board + - fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit + - const: fsl,imx7ulp + + - description: i.MX8MM based Boards + items: + - enum: + - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit + - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board + - fsl,imx8mm-evk # i.MX8MM EVK Board + - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module + - const: fsl,imx8mm + + - description: Variscite VAR-SOM-MX8MM based boards + items: + - const: variscite,var-som-mx8mm-symphony + - const: variscite,var-som-mx8mm + - const: fsl,imx8mm + + - description: i.MX8MN based Boards + items: + - enum: + - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board + - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board + - const: fsl,imx8mn + + - description: Variscite VAR-SOM-MX8MN based boards + items: + - const: variscite,var-som-mx8mn-symphony + - const: variscite,var-som-mx8mn + - const: fsl,imx8mn + + - description: i.MX8MP based Boards + items: + - enum: + - fsl,imx8mp-evk # i.MX8MP EVK Board + - const: fsl,imx8mp + + - description: i.MX8MQ based Boards + items: + - enum: + - boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board + - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board + - fsl,imx8mq-evk # i.MX8MQ EVK Board + - google,imx8mq-phanbell # Google Coral Edge TPU + - purism,librem5-devkit # Purism Librem5 devkit + - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse + - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk + - const: fsl,imx8mq + + - description: Purism Librem5 phones + items: + - enum: + - purism,librem5r2 # Purism Librem5 phone "Chestnut" + - purism,librem5r3 # Purism Librem5 phone "Dogwood" + - const: purism,librem5 + - const: fsl,imx8mq + + - description: Zodiac Inflight Innovations Ultra Boards + items: + - enum: + - zii,imx8mq-ultra-rmb3 + - zii,imx8mq-ultra-zest + - const: zii,imx8mq-ultra + - const: fsl,imx8mq + + - description: i.MX8QXP based Boards + items: + - enum: + - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board + - fsl,imx8qxp-mek # i.MX8QXP MEK Board + - toradex,colibri-imx8x # Colibri iMX8X Module + - const: fsl,imx8qxp + + - description: Toradex Colibri i.MX8 Evaluation Board + items: + - enum: + - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 + - const: toradex,colibri-imx8x + - const: fsl,imx8qxp + + - description: + Freescale Vybrid Platform Device Tree Bindings + + For the Vybrid SoC familiy all variants with DDR controller are supported, + which is the VF5xx and VF6xx series. Out of historical reasons, in most + places the kernel uses vf610 to refer to the whole familiy. + The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 + core support. + items: + - enum: + - fsl,vf500 + - fsl,vf510 + - fsl,vf600 + - fsl,vf610 + - fsl,vf610m4 + - toradex,vf500-colibri_vf50 # Colibri VF50 Module + - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board + - toradex,vf610-colibri_vf61 # Colibri VF61 Module + - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board + + - description: ZII's VF610 based Boards + items: + - enum: + - zii,vf610cfu1 # ZII VF610 CFU1 Board + - zii,vf610dev-c # ZII VF610 Development Board, Rev C + - zii,vf610dev-b # ZII VF610 Development Board, Rev B + - zii,vf610scu4-aib # ZII VF610 SCU4 AIB + - zii,vf610dtu # ZII VF610 SSMB DTU Board + - zii,vf610spu3 # ZII VF610 SSMB SPU3 Board + - zii,vf610spb4 # ZII VF610 SPB4 Board + - const: zii,vf610dev + - const: fsl,vf610 + + - description: LS1012A based Boards + items: + - enum: + - ebs-systart,oxalis + - fsl,ls1012a-rdb + - fsl,ls1012a-frdm + - fsl,ls1012a-qds + - const: fsl,ls1012a + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1021a-moxa-uc-8410a + - fsl,ls1021a-qds + - fsl,ls1021a-twr + - const: fsl,ls1021a + + - description: LS1028A based Boards + items: + - enum: + - fsl,ls1028a-qds + - fsl,ls1028a-rdb + - const: fsl,ls1028a + + - description: Kontron KBox A-230-LS + items: + - const: kontron,kbox-a-230-ls + - const: kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + - description: + Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0 + items: + - enum: + - kontron,sl28-var2-ads2 + - kontron,sl28-var3-ads2 + - kontron,sl28-var4-ads2 + - enum: + - kontron,sl28-var2 + - kontron,sl28-var3 + - kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + + - description: + Kontron SMARC-sAL28 board (on a generic/undefined carrier) + items: + - enum: + - kontron,sl28-var2 + - kontron,sl28-var3 + - kontron,sl28-var4 + - const: kontron,sl28 + - const: fsl,ls1028a + + - description: + Kontron SMARC-sAL28 board (base). This is used in the base device + tree which is compatible with the overlays provided by the + vendor. + items: + - const: kontron,sl28 + - const: fsl,ls1028a + + - description: LS1043A based Boards + items: + - enum: + - fsl,ls1043a-rdb + - fsl,ls1043a-qds + - const: fsl,ls1043a + + - description: LS1046A based Boards + items: + - enum: + - fsl,ls1046a-frwy + - fsl,ls1046a-qds + - fsl,ls1046a-rdb + - const: fsl,ls1046a + + - description: LS1088A based Boards + items: + - enum: + - fsl,ls1088a-qds + - fsl,ls1088a-rdb + - const: fsl,ls1088a + + - description: LS2080A based Boards + items: + - enum: + - fsl,ls2080a-simu + - fsl,ls2080a-qds + - fsl,ls2080a-rdb + - const: fsl,ls2080a + + - description: LS2088A based Boards + items: + - enum: + - fsl,ls2088a-qds + - fsl,ls2088a-rdb + - const: fsl,ls2088a + + - description: LX2160A based Boards + items: + - enum: + - fsl,lx2160a-qds + - fsl,lx2160a-rdb + - const: fsl,lx2160a + + - description: S32V234 based Boards + items: + - enum: + - fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board + - const: fsl,s32v234 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt b/Documentation/devicetree/bindings/arm/fw-cfg.txt new file mode 100644 index 000000000..fd54e1db2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/fw-cfg.txt @@ -0,0 +1,38 @@ +* QEMU Firmware Configuration bindings for ARM + +QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets +provide the following Firmware Configuration interface on the "virt" machine +type: + +- A write-only, 16-bit wide selector (or control) register, +- a read-write, 64-bit wide data register. + +QEMU exposes the control and data register to ARM guests as memory mapped +registers; their location is communicated to the guest's UEFI firmware in the +DTB that QEMU places at the bottom of the guest's DRAM. + +The authoritative guest-side hardware interface documentation to the fw_cfg +device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. + + +Required properties: + +- compatible: "qemu,fw-cfg-mmio". + +- reg: the MMIO region used by the device. + * Bytes 0x0 to 0x7 cover the data register. + * Bytes 0x8 to 0x9 cover the selector register. + * Further registers may be appended to the region in case of future interface + revisions / feature bits. + +Example: + +/ { + #size-cells = <0x2>; + #address-cells = <0x2>; + + fw-cfg@9020000 { + compatible = "qemu,fw-cfg-mmio"; + reg = <0x0 0x9020000 0x0 0xa>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/gemini.txt b/Documentation/devicetree/bindings/arm/gemini.txt new file mode 100644 index 000000000..55bf7ce96 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/gemini.txt @@ -0,0 +1,108 @@ +Cortina systems Gemini platforms + +The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally +produced by Storlink Semiconductor around 2005. The company was renamed +later renamed Storm Semiconductor. The chip product name is Storlink SL3516. +It was derived from earlier products from Storm named SL3316 (Centroid) and +SL3512 (Bulverde). + +Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was +produced and used for NAS and similar usecases. In 2014 Cortina Systems was +in turn acquired by Inphi, who seem to have discontinued this product family. + +Many of the IP blocks used in the SoC comes from Faraday Technology. + +Required properties (in root node): + compatible = "cortina,gemini"; + +Required nodes: + +- soc: the SoC should be represented by a simple bus encompassing all the + onchip devices, this is referred to as the soc bus node. + +- syscon: the soc bus node must have a system controller node pointing to the + global control registers, with the compatible string + "cortina,gemini-syscon", "syscon"; + + Required properties on the syscon: + - reg: syscon register location and size. + - #clock-cells: should be set to <1> - the system controller is also a + clock provider. + - #reset-cells: should be set to <1> - the system controller is also a + reset line provider. + + The clock sources have shorthand defines in the include file: + <dt-bindings/clock/cortina,gemini-clock.h> + + The reset lines have shorthand defines in the include file: + <dt-bindings/reset/cortina,gemini-reset.h> + +- timer: the soc bus node must have a timer node pointing to the SoC timer + block, with the compatible string "cortina,gemini-timer" + See: clocksource/cortina,gemini-timer.txt + +- interrupt-controller: the sob bus node must have an interrupt controller + node pointing to the SoC interrupt controller block, with the compatible + string "cortina,gemini-interrupt-controller" + See interrupt-controller/cortina,gemini-interrupt-controller.txt + +Example: + +/ { + model = "Foo Gemini Machine"; + compatible = "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + interrupt-parent = <&intcon>; + + syscon: syscon@40000000 { + compatible = "cortina,gemini-syscon", "syscon"; + reg = <0x40000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + uart0: serial@42000000 { + compatible = "ns16550a"; + reg = <0x42000000 0x100>; + resets = <&syscon GEMINI_RESET_UART>; + clocks = <&syscon GEMINI_CLK_UART>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + }; + + timer@43000000 { + compatible = "cortina,gemini-timer"; + reg = <0x43000000 0x1000>; + interrupt-parent = <&intcon>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + resets = <&syscon GEMINI_RESET_TIMER>; + /* APB clock or RTC clock */ + clocks = <&syscon GEMINI_CLK_APB>, + <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; + syscon = <&syscon>; + }; + + intcon: interrupt-controller@48000000 { + compatible = "cortina,gemini-interrupt-controller"; + reg = <0x48000000 0x1000>; + resets = <&syscon GEMINI_RESET_INTCON0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml new file mode 100644 index 000000000..528dad4cd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + cpuctrl@a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml new file mode 100644 index 000000000..cba1937aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg 42>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg 42>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <4>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml new file mode 100644 index 000000000..6ea6d7ee7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 domain controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + Hisilicon designs some special domain controllers for mobile platform, + such as: the power Always On domain controller, the Media domain + controller(e.g. codec, G3D ...) and the Power Management domain + controller. + + The compatible names of each domain controller are as follows: + Power Always ON domain controller --> hisilicon,hi6220-aoctrl + Media domain controller --> hisilicon,hi6220-mediactrl + Power Management domain controller --> hisilicon,hi6220-pmctrl + +properties: + compatible: + items: + - enum: + - hisilicon,hi6220-aoctrl + - hisilicon,hi6220-mediactrl + - hisilicon,hi6220-pmctrl + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; + + pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml new file mode 100644 index 000000000..7378159e6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml new file mode 100644 index 000000000..60c516a04 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml new file mode 100644 index 000000000..6d5065872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml new file mode 100644 index 000000000..5a53d433b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - enum: + - hisilicon,sysctrl + - hisilicon,hi6220-sysctrl + - hisilicon,hi3519-sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + + reg: + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + /* Hisilicon system controller */ + system-controller@802000 { + compatible = "hisilicon,sysctrl", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x802000 0x1000>; + reg = <0x802000 0x1000>; + + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + + clock: clock@0 { + compatible = "hisilicon,hi3620-clock"; + reg = <0 0x10000>; + #clock-cells = <1>; + }; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000..b38458022 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 based boards. + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 based boards. + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 based boards. + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 based boards. + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 based boards. + items: + - const: hisilicon,hip01-ca9x2 + - const: hisilicon,hip01 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 + + - description: SD5203 based boards + items: + - const: H836ASDJ + - const: hisilicon,sd5203 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml new file mode 100644 index 000000000..3b36e683b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP06 Low Pin Count device + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + HiP06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/idle-states.yaml b/Documentation/devicetree/bindings/arm/idle-states.yaml new file mode 100644 index 000000000..ea805c1e6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/idle-states.yaml @@ -0,0 +1,661 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/idle-states.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM idle states binding description + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: |+ + ========================================== + 1 - Introduction + ========================================== + + ARM systems contain HW capable of managing power consumption dynamically, + where cores can be put in different low-power states (ranging from simple wfi + to power gating) according to OS PM policies. The CPU states representing the + range of dynamic idle states that a processor can enter at run-time, can be + specified through device tree bindings representing the parameters required to + enter/exit specific idle states on a given processor. + + According to the Server Base System Architecture document (SBSA, [3]), the + power states an ARM CPU can be put into are identified by the following list: + + - Running + - Idle_standby + - Idle_retention + - Sleep + - Off + + The power states described in the SBSA document define the basic CPU states on + top of which ARM platforms implement power management schemes that allow an OS + PM implementation to put the processor in different idle states (which include + states listed above; "off" state is not an idle state since it does not have + wake-up capabilities, hence it is not considered in this document). + + Idle state parameters (e.g. entry latency) are platform specific and need to + be characterized with bindings that provide the required information to OS PM + code so that it can build the required tables and use them at runtime. + + The device tree binding definition for ARM idle states is the subject of this + document. + + =========================================== + 2 - idle-states definitions + =========================================== + + Idle states are characterized for a specific system through a set of + timing and energy related properties, that underline the HW behaviour + triggered upon idle states entry and exit. + + The following diagram depicts the CPU execution phases and related timing + properties required to enter and exit an idle state: + + ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. + | | | | | + + |<------ entry ------->| + | latency | + |<- exit ->| + | latency | + |<-------- min-residency -------->| + |<------- wakeup-latency ------->| + + Diagram 1: CPU idle state execution phases + + EXEC: Normal CPU execution. + + PREP: Preparation phase before committing the hardware to idle mode + like cache flushing. This is abortable on pending wake-up + event conditions. The abort latency is assumed to be negligible + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU + goes back to EXEC. This phase is optional. If not abortable, + this should be included in the ENTRY phase instead. + + ENTRY: The hardware is committed to idle mode. This period must run + to completion up to IDLE before anything else can happen. + + IDLE: This is the actual energy-saving idle period. This may last + between 0 and infinite time, until a wake-up event occurs. + + EXIT: Period during which the CPU is brought back to operational + mode (EXEC). + + entry-latency: Worst case latency required to enter the idle state. The + exit-latency may be guaranteed only after entry-latency has passed. + + min-residency: Minimum period, including preparation and entry, for a given + idle state to be worthwhile energywise. + + wakeup-latency: Maximum delay between the signaling of a wake-up event and the + CPU being able to execute normal code again. If not specified, this is assumed + to be entry-latency + exit-latency. + + These timing parameters can be used by an OS in different circumstances. + + An idle CPU requires the expected min-residency time to select the most + appropriate idle state based on the expected expiry time of the next IRQ + (i.e. wake-up) that causes the CPU to return to the EXEC phase. + + An operating system scheduler may need to compute the shortest wake-up delay + for CPUs in the system by detecting how long will it take to get a CPU out + of an idle state, e.g.: + + wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) + + In other words, the scheduler can make its scheduling decision by selecting + (e.g. waking-up) the CPU with the shortest wake-up delay. + The wake-up delay must take into account the entry latency if that period + has not expired. The abortable nature of the PREP period can be ignored + if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than + the worst case since it depends on the CPU operating conditions, i.e. caches + state). + + An OS has to reliably probe the wakeup-latency since some devices can enforce + latency constraint guarantees to work properly, so the OS has to detect the + worst case wake-up latency it can incur if a CPU is allowed to enter an + idle state, and possibly to prevent that to guarantee reliable device + functioning. + + The min-residency time parameter deserves further explanation since it is + expressed in time units but must factor in energy consumption coefficients. + + The energy consumption of a cpu when it enters a power state can be roughly + characterised by the following graph: + + | + | + | + e | + n | /--- + e | /------ + r | /------ + g | /----- + y | /------ + | ---- + | /| + | / | + | / | + | / | + | / | + | / | + |/ | + -----|-------+---------------------------------- + 0| 1 time(ms) + + Graph 1: Energy vs time example + + The graph is split in two parts delimited by time 1ms on the X-axis. + The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope + and denotes the energy costs incurred while entering and leaving the idle + state. + The graph curve in the area delimited by X-axis values = {x | x > 1ms } has + shallower slope and essentially represents the energy consumption of the idle + state. + + min-residency is defined for a given idle state as the minimum expected + residency time for a state (inclusive of preparation and entry) after + which choosing that state become the most energy efficient option. A good + way to visualise this, is by taking the same graph above and comparing some + states energy consumptions plots. + + For sake of simplicity, let's consider a system with two idle states IDLE1, + and IDLE2: + + | + | + | + | /-- IDLE1 + e | /--- + n | /---- + e | /--- + r | /-----/--------- IDLE2 + g | /-------/--------- + y | ------------ /---| + | / /---- | + | / /--- | + | / /---- | + | / /--- | + | --- | + | / | + | / | + |/ | time + ---/----------------------------+------------------------ + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy + | + IDLE2-min-residency + + Graph 2: idle states min-residency example + + In graph 2 above, that takes into account idle states entry/exit energy + costs, it is clear that if the idle state residency time (i.e. time till next + wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state + choice energywise. + + This is mainly down to the fact that IDLE1 entry/exit energy costs are lower + than IDLE2. + + However, the lower power consumption (i.e. shallower energy curve slope) of + idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy + efficient. + + The time at which IDLE2 becomes more energy efficient than IDLE1 (and other + shallower states in a system with multiple idle states) is defined + IDLE2-min-residency and corresponds to the time when energy consumption of + IDLE1 and IDLE2 states breaks even. + + The definitions provided in this section underpin the idle states + properties specification that is the subject of the following sections. + + =========================================== + 3 - idle-states node + =========================================== + + ARM processor idle states are defined within the idle-states node, which is + a direct child of the cpus node [1] and provides a container where the + processor idle states, defined as device tree nodes, are listed. + + On ARM systems, it is a container of processor idle states nodes. If the + system does not provide CPU power management capabilities, or the processor + just supports idle_standby, an idle-states node is not required. + + =========================================== + 4 - References + =========================================== + + [1] ARM Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/arm/cpus.yaml + + [2] ARM Linux Kernel documentation - PSCI bindings + Documentation/devicetree/bindings/arm/psci.yaml + + [3] ARM Server Base System Architecture (SBSA) + http://infocenter.arm.com/help/index.jsp + + [4] ARM Architecture Reference Manuals + http://infocenter.arm.com/help/index.jsp + + [6] ARM Linux Kernel documentation - Booting AArch64 Linux + Documentation/arm64/booting.rst + +properties: + $nodename: + const: idle-states + + entry-method: + description: | + Usage and definition depend on ARM architecture version. + + On ARM v8 64-bit this property is required. + On ARM 32-bit systems this property is optional + + This assumes that the "enable-method" property is set to "psci" in the cpu + node[6] that is responsible for setting up CPU idle management in the OS + implementation. + const: psci + +patternProperties: + "^(cpu|cluster)-": + type: object + description: | + Each state node represents an idle state description and must be defined + as follows. + + The idle state entered by executing the wfi instruction (idle_standby + SBSA,[3][4]) is considered standard on all ARM platforms and therefore + must not be listed. + + In addition to the properties listed above, a state node may require + additional properties specific to the entry-method defined in the + idle-states node. Please refer to the entry-method bindings + documentation for properties definitions. + + properties: + compatible: + const: arm,idle-state + + local-timer-stop: + description: + If present the CPU local timer control logic is + lost on state entry, otherwise it is retained. + type: boolean + + entry-latency-us: + description: + Worst case latency in microseconds required to enter the idle state. + + exit-latency-us: + description: + Worst case latency in microseconds required to exit the idle state. + The exit-latency-us duration may be guaranteed only after + entry-latency-us has passed. + + min-residency-us: + description: + Minimum residency duration in microseconds, inclusive of preparation + and entry, for this idle state to be considered worthwhile energy wise + (refer to section 2 of this document for a complete description). + + wakeup-latency-us: + description: | + Maximum delay between the signaling of a wake-up event and the CPU + being able to execute normal code again. If omitted, this is assumed + to be equal to: + + entry-latency-us + exit-latency-us + + It is important to supply this value on systems where the duration of + PREP phase (see diagram 1, section 2) is non-neglibigle. In such + systems entry-latency-us + exit-latency-us will exceed + wakeup-latency-us by this duration. + + idle-state-name: + $ref: /schemas/types.yaml#definitions/string + description: + A string used as a descriptive name for the idle state. + + required: + - compatible + - entry-latency-us + - exit-latency-us + - min-residency-us + +additionalProperties: false + +examples: + - | + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + idle-states { + entry-method = "psci"; + + CPU_RETENTION_0_0: cpu-retention-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CLUSTER_RETENTION_0: cluster-retention-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CPU_SLEEP_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + CPU_RETENTION_1_0: cpu-retention-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <90>; + }; + + CLUSTER_RETENTION_1: cluster-retention-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <270>; + wakeup-latency-us = <100>; + }; + + CPU_SLEEP_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <100>; + min-residency-us = <300>; + wakeup-latency-us = <150>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1200>; + min-residency-us = <3500>; + wakeup-latency-us = <1300>; + }; + }; + }; + + - | + // Example 2 (ARM 32-bit, 8-cpu system, two clusters): + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + idle-states { + cpu_sleep_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <200>; + exit-latency-us = <100>; + min-residency-us = <400>; + wakeup-latency-us = <250>; + }; + + cluster_sleep_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <1500>; + min-residency-us = <2500>; + wakeup-latency-us = <1700>; + }; + + cpu_sleep_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <500>; + min-residency-us = <900>; + wakeup-latency-us = <600>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <800>; + exit-latency-us = <2000>; + min-residency-us = <6500>; + wakeup-latency-us = <2300>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml new file mode 100644 index 000000000..69cd30872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keem Bay platform device tree bindings + +maintainers: + - Paul J. Murphy <paul.j.murphy@intel.com> + - Daniele Alessandrelli <daniele.alessandrelli@intel.com> + +properties: + compatible: + items: + - enum: + - intel,keembay-evm + - const: intel,keembay + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml new file mode 100644 index 000000000..d72e92bdf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Device Tree Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - linksys,nslu2 + - const: intel,ixp42x + - items: + - enum: + - gateworks,gw2358 + - const: intel,ixp43x + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt new file mode 100644 index 000000000..2ace8696b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/juno,scpi.txt @@ -0,0 +1,26 @@ +System Control and Power Interface (SCPI) Message Protocol +(in addition to the standard binding in [0]) + +Juno SRAM and Shared Memory for SCPI +------------------------------------ + +Required properties: +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM + +Each sub-node represents the reserved area for SCPI. + +Required sub-node properties: +- reg : The base offset and size of the reserved area with the SRAM +- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based + shared memory on Juno platforms + +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +Required properties: +- compatible : should be "arm,scpi-sensors". +- #thermal-sensor-cells: should be set to 1. + For Juno R0 and Juno R1 refer to [1] for the + sensor identifiers + +[0] Documentation/devicetree/bindings/arm/arm,scpi.txt +[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt new file mode 100644 index 000000000..f310bad04 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt @@ -0,0 +1,42 @@ +TI Keystone Platforms Device Tree Bindings +----------------------------------------------- + +Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the +following properties. + +Required properties: + - compatible: All TI specific devices present in Keystone SOC should be in + the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 + type UART should use the specified compatible for those devices. + +SoC families: + +- Keystone 2 generic SoC: + compatible = "ti,keystone" + +SoCs: + +- Keystone 2 Hawking/Kepler + compatible = "ti,k2hk", "ti,keystone" +- Keystone 2 Lamarr + compatible = "ti,k2l", "ti,keystone" +- Keystone 2 Edison + compatible = "ti,k2e", "ti,keystone" +- K2G + compatible = "ti,k2g", "ti,keystone" + +Boards: +- Keystone 2 Hawking/Kepler EVM + compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" + +- Keystone 2 Lamarr EVM + compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" + +- Keystone 2 Edison EVM + compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" + +- K2G EVM + compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" + +- K2G Industrial Communication Engine EVM + compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml new file mode 100644 index 000000000..5cbcacaeb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common K3 TI-SCI bindings + +maintainers: + - Nishanth Menon <nm@ti.com> + +description: | + The TI K3 family of SoCs usually have a central System Controller Processor + that is responsible for managing various SoC-level resources like clocks, + resets, interrupts etc. The communication with that processor is performed + through the TI-SCI protocol. + + Each specific device management node like a clock controller node, a reset + controller node or an interrupt-controller node should define a common set + of properties that enables them to implement the corresponding functionality + over the TI-SCI protocol. The following are some of the common properties + needed by such individual nodes. The required properties for each device + management node is defined in the respective binding. + +properties: + ti,sci: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Should be a phandle to the TI-SCI System Controller node + + ti,sci-dev-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should contain the TI-SCI device id corresponding to the device. Please + refer to the corresponding System Controller documentation for valid + values for the desired device. + + ti,sci-proc-ids: + description: Should contain a single tuple of <proc_id host_id>. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: TI-SCI processor id for the remote processor device + - description: TI-SCI host id to which processor control ownership + should be transferred to + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt new file mode 100644 index 000000000..6f0cd31c1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt @@ -0,0 +1,86 @@ +Texas Instruments System Control Interface (TI-SCI) Message Protocol +-------------------------------------------------------------------- + +Texas Instrument's processors including those belonging to Keystone generation +of processors have separate hardware entity which is now responsible for the +management of the System on Chip (SoC) system. These include various system +level functions as well. + +An example of such an SoC is K2G, which contains the system control hardware +block called Power Management Micro Controller (PMMC). This hardware block is +initialized early into boot process and provides services to Operating Systems +on multiple processors including ones running Linux. + +See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. + +TI-SCI controller Device Node: +============================= + +The TI-SCI node describes the Texas Instrument's System Controller entity node. +This parent node may optionally have additional children nodes which describe +specific functionality such as clocks, power domain, reset or additional +functionality as may be required for the SoC. This hierarchy also describes the +relationship between the TI-SCI parent node to the child node. + +Required properties: +------------------- +- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC + should be "ti,am654-sci" for for TI AM654 SoC +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details +about the generic mailbox controller and client driver bindings. Also see +Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical +controller that is used to communicate with this System controllers. + +Optional Properties: +------------------- +- reg-names: + debug_messages - Map the Debug message region +- reg: register space corresponding to the debug_messages +- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot +- ti,host-id: Integer value corresponding to the host ID assigned by Firmware + for identification of host processing entities such as virtual + machines + +Example (K2G): +------------- + pmmc: pmmc { + compatible = "ti,k2g-sci"; + ti,host-id = <2>; + mbox-names = "rx", "tx"; + mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>, + <&msgmgr &msgmgr_proxy_pmmc_tx>; + reg-names = "debug_messages"; + reg = <0x02921800 0x800>; + }; + + +TI-SCI Client Device Node: +========================= + +Client nodes are maintained as children of the relevant TI-SCI device node. + +Example (K2G): +------------- + pmmc: pmmc { + compatible = "ti,k2g-sci"; + ... + + my_clk_node: clk_node { + ... + ... + }; + + my_pd_node: pd_node { + ... + ... + }; + }; diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml new file mode 100644 index 000000000..6b8f4d4fa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM L2 Cache Controller + +maintainers: + - Rob Herring <robh@kernel.org> + +description: |+ + ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ + PL220/PL310 and variants) based level 2 cache controller. All these various + implementations of the L2 cache controller have compatible programming + models (Note 1). Some of the properties that are just prefixed "cache-*" are + taken from section 3.7.3 of the Devicetree Specification which can be found + at: + https://www.devicetree.org/specifications/ + + Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - arm,pl310-cache + - arm,l220-cache + - arm,l210-cache + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + - bcm,bcm11351-a2-pl310-cache + # For Broadcom bcm11351 chipset where an + # offset needs to be added to the address before passing down to the L2 + # cache controller + - brcm,bcm11351-a2-pl310-cache + # Marvell Controller designed to be + # compatible with the ARM one, with system cache mode (meaning + # maintenance operations on L1 are broadcasted to the L2 and L2 + # performs the same operation). + - marvell,aurora-system-cache + # Marvell Controller designed to be + # compatible with the ARM one with outer cache mode. + - marvell,aurora-outer-cache + - items: + # Marvell Tauros3 cache controller, compatible + # with arm,pl310-cache controller. + - const: marvell,tauros3-cache + - const: arm,pl310-cache + + cache-level: + const: 2 + + cache-unified: true + cache-size: true + cache-sets: true + cache-block-size: true + cache-line-size: true + + reg: + maxItems: 1 + + arm,data-latency: + description: Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,tag-latency: + description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,dirty-latency: + description: Cycles of latency for Dirty RAMs. This is a single cell. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + + arm,filter-ranges: + description: <start length> Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 2 + maxItems: 2 + + arm,io-coherent: + description: indicates that the system is operating in an hardware + I/O coherent mode. Valid only when the arm,pl310-cache compatible + string is used. + type: boolean + + interrupts: + # Either a single combined interrupt or up to 9 individual interrupts + minItems: 1 + maxItems: 9 + + cache-id-part: + description: cache id part number to be used if it is not present + on hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + wt-override: + description: If present then L2 is forced to Write through mode + type: boolean + + arm,double-linefill: + description: Override double linefill enable setting. Enable if + non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,double-linefill-incr: + description: Override double linefill on INCR read. Enable + if non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,double-linefill-wrap: + description: Override double linefill on WRAP read. Enable + if non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,prefetch-drop: + description: Override prefetch drop enable setting. Enable if non-zero, + disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,prefetch-offset: + description: Override prefetch offset value. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] + + arm,shared-override: + description: The default behavior of the L220 or PL310 cache + controllers with respect to the shareable attribute is to transform "normal + memory non-cacheable transactions" into "cacheable no allocate" (for reads) + or "write through no write allocate" (for writes). + On systems where this may cause DMA buffer corruption, this property must + be specified to indicate that such transforms are precluded. + type: boolean + + arm,parity-enable: + description: enable parity checking on the L2 cache (L220 or PL310). + type: boolean + + arm,parity-disable: + description: disable parity checking on the L2 cache (L220 or PL310). + type: boolean + + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + + arm,outer-sync-disable: + description: disable the outer sync operation on the L2 cache. + Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that + will randomly hang unless outer sync operations are disabled. + type: boolean + + prefetch-data: + description: | + Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + prefetch-instr: + description: | + Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,dynamic-clock-gating: + description: | + L2 dynamic clock gating. Value: <0> (forcibly + disable), <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,standby-mode: + description: L2 standby mode enable. Value <0> (forcibly disable), + <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,early-bresp-disable: + description: Disable the CA9 optimization Early BRESP (PL310) + type: boolean + + arm,full-line-zero-disable: + description: Disable the CA9 optimization Full line of zero + write (PL310) + type: boolean + +required: + - compatible + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@fff12000 { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt new file mode 100644 index 000000000..26eb9d3aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt @@ -0,0 +1,16 @@ +Resume Control +-------------- +Available on Marvell SOCs: 98DX3336 and 98DX4251 + +Required properties: + +- compatible: must be "marvell,98dx3336-resume-ctrl" + +- reg: Should contain resume control registers location and length + +Example: + +resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt new file mode 100644 index 000000000..64e8c73fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt @@ -0,0 +1,23 @@ +Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings +---------------------------------------------------------------------- + +Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families +shall have the following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp-98dx3236" + +In addition, boards using the Marvell 98DX3336 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp-98dx3336" + +In addition, boards using the Marvell 98DX4251 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp-98dx4251" diff --git a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt new file mode 100644 index 000000000..e31511255 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -0,0 +1,177 @@ +Marvell Armada AP80x System Controller +====================================== + +The AP806/AP807 is one of the two core HW blocks of the Marvell Armada +7K/8K/931x SoCs. It contains system controllers, which provide several +registers giving access to numerous features: clocks, pin-muxing and +many other SoC configuration items. This DT binding allows to describe +these system controllers. + +For the top level node: + - compatible: must be: "syscon", "simple-mfd"; + - reg: register area of the AP80x system controller + +SYSTEM CONTROLLER 0 +=================== + +Clocks: +------- + + +The Device Tree node representing the AP806/AP807 system controller +provides a number of clocks: + + - 0: reference clock of CPU cluster 0 + - 1: reference clock of CPU cluster 1 + - 2: fixed PLL at 1200 Mhz + - 3: MSS clock, derived from the fixed PLL + +Required properties: + + - compatible: must be one of: + * "marvell,ap806-clock" + * "marvell,ap807-clock" + - #clock-cells: must be set to 1 + +Pinctrl: +-------- + +For common binding part and usage, refer to +Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. + +Required properties: +- compatible must be "marvell,ap806-pinctrl", + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, sdio(clk), spi0(clk) +mpp1 1 gpio, sdio(cmd), spi0(miso) +mpp2 2 gpio, sdio(d0), spi0(mosi) +mpp3 3 gpio, sdio(d1), spi0(cs0n) +mpp4 4 gpio, sdio(d2), i2c0(sda) +mpp5 5 gpio, sdio(d3), i2c0(sdk) +mpp6 6 gpio, sdio(ds) +mpp7 7 gpio, sdio(d4), uart1(rxd) +mpp8 8 gpio, sdio(d5), uart1(txd) +mpp9 9 gpio, sdio(d6), spi0(cs1n) +mpp10 10 gpio, sdio(d7) +mpp11 11 gpio, uart0(txd) +mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) +mpp13 13 gpio +mpp14 14 gpio +mpp15 15 gpio +mpp16 16 gpio +mpp17 17 gpio +mpp18 18 gpio +mpp19 19 gpio, uart0(rxd), sdio(pw_off) + +GPIO: +----- +For common binding part and usage, refer to +Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. + +Required properties: + +- compatible: "marvell,armada-8k-gpio" + +- offset: offset address inside the syscon block + +Example: +ap_syscon: system-controller@6f4000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f4000 0x1000>; + + ap_clk: clock { + compatible = "marvell,ap806-clock"; + #clock-cells = <1>; + }; + + ap_pinctrl: pinctrl { + compatible = "marvell,ap806-pinctrl"; + }; + + ap_gpio: gpio { + compatible = "marvell,armada-8k-gpio"; + offset = <0x1040>; + ngpios = <19>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ap_pinctrl 0 0 19>; + }; +}; + +SYSTEM CONTROLLER 1 +=================== + +Thermal: +-------- + +For common binding part and usage, refer to +Documentation/devicetree/bindings/thermal/thermal*.yaml + +The thermal IP can probe the temperature all around the processor. It +may feature several channels, each of them wired to one sensor. + +It is possible to setup an overheat interrupt by giving at least one +critical point to any subnode of the thermal-zone node. + +Required properties: +- compatible: must be one of: + * marvell,armada-ap806-thermal +- reg: register range associated with the thermal functions. + +Optional properties: +- interrupts: overheat interrupt handle. Should point to line 18 of the + SEI irqchip. See interrupt-controller/interrupts.txt +- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer + to this IP and represents the channel ID. There is one sensor per + channel. O refers to the thermal IP internal channel, while positive + IDs refer to each CPU. + +Example: +ap_syscon1: system-controller@6f8000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + ap_thermal: thermal-sensor@80 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x80 0x10>; + interrupt-parent = <&sei>; + interrupts = <18>; + #thermal-sensor-cells = <1>; + }; +}; + +Cluster clocks: +--------------- + +Device Tree Clock bindings for cluster clock of Marvell +AP806/AP807. Each cluster contain up to 2 CPUs running at the same +frequency. + +Required properties: + - compatible: must be one of: + * "marvell,ap806-cpu-clock" + * "marvell,ap807-cpu-clock" +- #clock-cells : should be set to 1. + +- clocks : shall be the input parent clock(s) phandle for the clock + (one per cluster) + +- reg: register range associated with the cluster clocks + +ap_syscon1: system-controller@6f8000 { + compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + cpu_clk: clock-cpu@278 { + compatible = "marvell,ap806-cpu-clock"; + clocks = <&ap_clk 0>, <&ap_clk 1>; + #clock-cells = <1>; + reg = <0x278 0xa30>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt new file mode 100644 index 000000000..26799ef56 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt @@ -0,0 +1,21 @@ +Power Management Service Unit(PMSU) +----------------------------------- +Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP + +Required properties: + +- compatible: should be one of: + - "marvell,armada-370-pmsu" for Armada 370 or Armada XP + - "marvell,armada-380-pmsu" for Armada 38x + - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now + deprecated and will be removed + +- reg: Should contain PMSU registers location and length. + +Example: + +armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; +}; + diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt new file mode 100644 index 000000000..c6ed90ea6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt @@ -0,0 +1,24 @@ +Marvell Armada 370 and Armada XP Platforms Device Tree Bindings +--------------------------------------------------------------- + +Boards with a SoC of the Marvell Armada 370 and Armada XP families +shall have the following property: + +Required root node property: + +compatible: must contain "marvell,armada-370-xp" + +In addition, boards using the Marvell Armada 370 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armada370" + +In addition, boards using the Marvell Armada XP SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp" + diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt new file mode 100644 index 000000000..867d0b80c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt @@ -0,0 +1,9 @@ +Marvell Armada 375 Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 375 family shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armada375" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt new file mode 100644 index 000000000..f6d6642d8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt @@ -0,0 +1,58 @@ +Marvell Armada 37xx Platforms Device Tree Bindings +-------------------------------------------------- + +Boards using a SoC of the Marvell Armada 37xx family must carry the +following root node property: + + - compatible: must contain "marvell,armada3710" + +In addition, boards using the Marvell Armada 3720 SoC shall have the +following property before the previous one: + + - compatible: must contain "marvell,armada3720" + +Example: + +compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; + + +Power management +---------------- + +For power management (particularly DVFS and AVS), the North Bridge +Power Management component is needed: + +Required properties: +- compatible : should contain "marvell,armada-3700-nb-pm", "syscon"; +- reg : the register start and length for the North Bridge + Power Management + +Example: + +nb_pm: syscon@14000 { + compatible = "marvell,armada-3700-nb-pm", "syscon"; + reg = <0x14000 0x60>; +} + +AVS +--- + +For AVS an other component is needed: + +Required properties: +- compatible : should contain "marvell,armada-3700-avs", "syscon"; +- reg : the register start and length for the AVS + +Example: +avs: avs@11500 { + compatible = "marvell,armada-3700-avs", "syscon"; + reg = <0x11500 0x40>; +} + + +CZ.NIC's Turris Mox SOHO router Device Tree Bindings +---------------------------------------------------- + +Required root node property: + + - compatible: must contain "cznic,turris-mox" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt new file mode 100644 index 000000000..878107302 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt @@ -0,0 +1,14 @@ +Marvell Armada 38x CA9 MPcore SoC Controller +============================================ + +Required properties: + +- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". + +- reg: should be the register base and length as documented in the + datasheet for the CA9 MPcore SoC Control registers + +mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt new file mode 100644 index 000000000..202953f18 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt @@ -0,0 +1,27 @@ +Marvell Armada 38x Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 38x family shall have the +following property: + +Required root node property: + + - compatible: must contain "marvell,armada380" + +In addition, boards using the Marvell Armada 385 SoC shall have the +following property before the previous one: + +Required root node property: + +compatible: must contain "marvell,armada385" + +In addition, boards using the Marvell Armada 388 SoC shall have the +following property before the previous one: + +Required root node property: + +compatible: must contain "marvell,armada388" + +Example: + +compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt new file mode 100644 index 000000000..89468664f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt @@ -0,0 +1,31 @@ +Marvell Armada 39x Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 39x family shall have the +following property: + +Required root node property: + + - compatible: must contain "marvell,armada390" + +In addition, boards using the Marvell Armada 395 SoC shall have the +following property before the common "marvell,armada390" one: + +Required root node property: + +compatible: must contain "marvell,armada395" + +Example: + +compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; + +Boards using the Marvell Armada 398 SoC shall have the following +property before the common "marvell,armada390" one: + +Required root node property: + +compatible: must contain "marvell,armada398" + +Example: + +compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml new file mode 100644 index 000000000..e9bf30545 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR X11) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K Platforms Device Tree Bindings + +maintainers: + - Gregory CLEMENT <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Armada 7020 SoC + items: + - const: marvell,armada7020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 7040 SoC + items: + - const: marvell,armada7040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8020 SoC + items: + - const: marvell,armada8020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 8040 SoC + items: + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada CN9130 SoC with no external CP + items: + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9131 SoC with one external CP + items: + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9132 SoC with two external CPs + items: + - const: marvell,cn9132 + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt new file mode 100644 index 000000000..f3e962453 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt @@ -0,0 +1,15 @@ +Marvell Armada 8KPlus Platforms Device Tree Bindings +---------------------------------------------------- + +Boards using a SoC of the Marvell Armada 8KP families must carry +the following root node property: + + - compatible, with one of the following values: + + - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" + when the SoC being used is the Armada 8080 + +Example: + +compatible = "marvell,armada-8080-db", "marvell,armada-8080", + "marvell,armada-ap810-octa", "marvell,armada-ap810" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt new file mode 100644 index 000000000..b63a7b6ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt @@ -0,0 +1,14 @@ +Marvell Armada CPU reset controller +=================================== + +Required properties: + +- compatible: Should be "marvell,armada-370-cpu-reset". + +- reg: should be register base and length as documented in the + datasheet for the CPU reset registers + +cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt new file mode 100644 index 000000000..9b5c3f620 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt @@ -0,0 +1,48 @@ +Coherency fabric +---------------- +Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP + +Required properties: + +- compatible: the possible values are: + + * "marvell,coherency-fabric", to be used for the coherency fabric of + the Armada 370 and Armada XP. + + * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency + fabric. + + * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency + fabric. + +- reg: Should contain coherency fabric registers location and + length. + + * For "marvell,coherency-fabric", the first pair for the coherency + fabric registers, second pair for the per-CPU fabric registers. + + * For "marvell,armada-375-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. + + * For "marvell,armada-380-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. + +Optional properties: + +- broken-idle: boolean to set when the Idle mode is not supported by the + hardware. + +Examples: + +coherency-fabric@d0020200 { + compatible = "marvell,coherency-fabric"; + reg = <0xd0020200 0xb0>, + <0xd0021810 0x1c>; + +}; + +coherency-fabric@21810 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21810 0x1c>; +}; + diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt new file mode 100644 index 000000000..a21f77095 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -0,0 +1,234 @@ +Marvell Armada CP110 System Controller +====================================== + +The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K +SoCs. It contains system controllers, which provide several registers +giving access to numerous features: clocks, pin-muxing and many other +SoC configuration items. This DT binding allows to describe these +system controllers. + +For the top level node: + - compatible: must be: "syscon", "simple-mfd"; + - reg: register area of the CP110 system controller + +SYSTEM CONTROLLER 0 +=================== + +Clocks: +------- + +The Device Tree node representing this System Controller 0 provides a +number of clocks: + + - a set of core clocks + - a set of gatable clocks + +Those clocks can be referenced by other Device Tree nodes using two +cells: + - The first cell must be 0 or 1. 0 for the core clocks and 1 for the + gatable clocks. + - The second cell identifies the particular core clock or gatable + clocks. + +The following clocks are available: + - Core clocks + - 0 0 APLL + - 0 1 PPv2 core + - 0 2 EIP + - 0 3 Core + - 0 4 NAND core + - 0 5 SDIO core + - Gatable clocks + - 1 0 Audio + - 1 1 Comm Unit + - 1 2 NAND + - 1 3 PPv2 + - 1 4 SDIO + - 1 5 MG Domain + - 1 6 MG Core + - 1 7 XOR1 + - 1 8 XOR0 + - 1 9 GOP DP + - 1 11 PCIe x1 0 + - 1 12 PCIe x1 1 + - 1 13 PCIe x4 + - 1 14 PCIe / XOR + - 1 15 SATA + - 1 16 SATA USB + - 1 17 Main + - 1 18 SD/MMC/GOP + - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) + - 1 22 USB3H0 + - 1 23 USB3H1 + - 1 24 USB3 Device + - 1 25 EIP150 + - 1 26 EIP197 + +Required properties: + + - compatible: must be: + "marvell,cp110-clock" + - #clock-cells: must be set to 2 + +Pinctrl: +-------- + +For common binding part and usage, refer to the file +Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. + +Required properties: + +- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl" + depending on the specific variant of the SoC being used. + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio) +mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc) +mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc) +mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio) +mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc) +mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio) +mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse) +mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk) +mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk) +mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk) +mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act) +mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act) +mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk) +mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso) +mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn) +mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp) +mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk) +mpp17 17 gpio, dev(ad5), ge0(txd3) +mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp) +mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp) +mpp20 20 gpio, dev(ad2), ge0(txd0) +mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp) +mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp) +mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp) +mpp24 24 gpio, dev(a0), au(i2slrclk) +mpp25 25 gpio, dev(oen), au(i2sdo_spdifo) +mpp26 26 gpio, dev(wen0), au(i2sbclk) +mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp) +mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data) +mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb) +mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk) +mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc) +mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0 +mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1 +mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2 +mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3 +mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5 +mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp) +mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp) +mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0 +mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1 +mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp) +mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4 +mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp) +mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp) +mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn) +mpp46 46 gpio, ge1(txd1), uart1(rts) +mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc) +mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp) +mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp) +mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11) +mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10) +mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq) +mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led) +mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect) +mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect) +mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk) +mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd) +mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0) +mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1) +mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2) +mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3) +mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc) + +GPIO: +----- + +For common binding part and usage, refer to +Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. + +Required properties: + +- compatible: "marvell,armada-8k-gpio" + +- offset: offset address inside the syscon block + +Example: + +CP110_LABEL(syscon0): system-controller@440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x440000 0x1000>; + + CP110_LABEL(clk): clock { + compatible = "marvell,cp110-clock"; + #clock-cells = <2>; + }; + + CP110_LABEL(pinctrl): pinctrl { + compatible = "marvell,armada-8k-cpm-pinctrl"; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x100>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; + }; + +}; + +SYSTEM CONTROLLER 1 +=================== + +Thermal: +-------- + +The thermal IP can probe the temperature all around the processor. It +may feature several channels, each of them wired to one sensor. + +It is possible to setup an overheat interrupt by giving at least one +critical point to any subnode of the thermal-zone node. + +For common binding part and usage, refer to +Documentation/devicetree/bindings/thermal/thermal*.yaml + +Required properties: +- compatible: must be one of: + * marvell,armada-cp110-thermal +- reg: register range associated with the thermal functions. + +Optional properties: +- interrupts-extended: overheat interrupt handle. Should point to + a line of the ICU-SEI irqchip (116 is what is usually used by the + firmware). The ICU-SEI will redirect towards interrupt line #37 of the + AP SEI which is shared across all CPs. + See interrupt-controller/interrupts.txt +- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer + to this IP and represents the channel ID. There is one sensor per + channel. O refers to the thermal IP internal channel. + +Example: +CP110_LABEL(syscon1): system-controller@6f8000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + CP110_LABEL(thermal): thermal-sensor@70 { + compatible = "marvell,armada-cp110-thermal"; + reg = <0x70 0x10>; + interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt new file mode 100644 index 000000000..98cce9a65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt @@ -0,0 +1,27 @@ +Marvell Kirkwood Platforms Device Tree Bindings +----------------------------------------------- + +Boards with a SoC of the Marvell Kirkwood +shall have the following property: + +Required root node property: + +compatible: must contain "marvell,kirkwood"; + +In order to support the kirkwood cpufreq driver, there must be a node +cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave", +where the "powersave" clock is a gating clock used to switch the CPU +between the "cpu_clk" and the "ddrclk". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-88SV131"; + clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; + clock-names = "cpu_clk", "ddrclk", "powersave"; + }; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt new file mode 100644 index 000000000..aaaf64c56 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt @@ -0,0 +1,22 @@ +Marvell Dove Platforms Device Tree Bindings +----------------------------------------------- + +Boards with a Marvell Dove SoC shall have the following properties: + +Required root node property: +- compatible: must contain "marvell,dove"; + +* Global Configuration registers + +Global Configuration registers of Dove SoC are shared by a syscon node. + +Required properties: +- compatible: must contain "marvell,dove-global-config" and "syscon". +- reg: base address and size of the Global Configuration registers. + +Example: + +gconf: global-config@e802c { + compatible = "marvell,dove-global-config", "syscon"; + reg = <0xe802c 0x14>; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt new file mode 100644 index 000000000..7d28fe4bf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt @@ -0,0 +1,105 @@ +Marvell Kirkwood SoC Family Device Tree Bindings +------------------------------------------------ + +Boards with a SoC of the Marvell Kirkwook family, eg 88f6281 + +* Required root node properties: +compatible: must contain "marvell,kirkwood" + +In addition, the above compatible shall be extended with the specific +SoC. Currently known SoC compatibles are: + +"marvell,kirkwood-88f6192" +"marvell,kirkwood-88f6281" +"marvell,kirkwood-88f6282" +"marvell,kirkwood-88f6283" +"marvell,kirkwood-88f6702" +"marvell,kirkwood-98DX4122" + +And in addition, the compatible shall be extended with the specific +board. Currently known boards are: + +"buffalo,linkstation-lsqvl" +"buffalo,linkstation-lsvl" +"buffalo,linkstation-lswsxl" +"buffalo,linkstation-lswxl" +"buffalo,linkstation-lswvl" +"buffalo,lschlv2" +"buffalo,lsxhl" +"buffalo,lsxl" +"cloudengines,pogo02" +"cloudengines,pogoplugv4" +"dlink,dns-320" +"dlink,dns-320-a1" +"dlink,dns-325" +"dlink,dns-325-a1" +"dlink,dns-kirkwood" +"excito,b3" +"globalscale,dreamplug-003-ds2001" +"globalscale,guruplug" +"globalscale,guruplug-server-plus" +"globalscale,sheevaplug" +"globalscale,sheevaplug" +"globalscale,sheevaplug-esata" +"globalscale,sheevaplug-esata-rev13" +"iom,iconnect" +"iom,iconnect-1.1" +"iom,ix2-200" +"keymile,km_kirkwood" +"lacie,cloudbox" +"lacie,inetspace_v2" +"lacie,laplug" +"lacie,nas2big" +"lacie,netspace_lite_v2" +"lacie,netspace_max_v2" +"lacie,netspace_mini_v2" +"lacie,netspace_v2" +"marvell,db-88f6281-bp" +"marvell,db-88f6282-bp" +"marvell,mv88f6281gtw-ge" +"marvell,rd88f6281" +"marvell,rd88f6281" +"marvell,rd88f6281-a0" +"marvell,rd88f6281-a1" +"mpl,cec4" +"mpl,cec4-10" +"netgear,readynas" +"netgear,readynas" +"netgear,readynas-duo-v2" +"netgear,readynas-nv+-v2" +"plathome,openblocks-a6" +"plathome,openblocks-a7" +"raidsonic,ib-nas6210" +"raidsonic,ib-nas6210-b" +"raidsonic,ib-nas6220" +"raidsonic,ib-nas6220-b" +"raidsonic,ib-nas62x0" +"seagate,dockstar" +"seagate,goflexnet" +"synology,ds109" +"synology,ds110jv10" +"synology,ds110jv20" +"synology,ds110jv30" +"synology,ds111" +"synology,ds209" +"synology,ds210jv10" +"synology,ds210jv20" +"synology,ds212" +"synology,ds212jv10" +"synology,ds212jv20" +"synology,ds212pv10" +"synology,ds409" +"synology,ds409slim" +"synology,ds410j" +"synology,ds411" +"synology,ds411j" +"synology,ds411slim" +"synology,ds413jv10" +"synology,rs212" +"synology,rs409" +"synology,rs411" +"synology,rs812" +"usi,topkick" +"usi,topkick-1281P2" +"zyxel,nsa310" +"zyxel,nsa310a" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt new file mode 100644 index 000000000..748a8f287 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -0,0 +1,25 @@ +Marvell Orion SoC Family Device Tree Bindings +--------------------------------------------- + +Boards with a SoC of the Marvell Orion family, eg 88f5181 + +* Required root node properties: +compatible: must contain "marvell,orion5x" + +In addition, the above compatible shall be extended with the specific +SoC. Currently known SoC compatibles are: + +"marvell,orion5x-88f5181" +"marvell,orion5x-88f5182" + +And in addition, the compatible shall be extended with the specific +board. Currently known boards are: + +"buffalo,lsgl" +"buffalo,lswsgl" +"buffalo,lswtgl" +"lacie,ethernet-disk-mini-v2" +"lacie,d2-network" +"marvell,rd-88f5182-nas" +"maxtor,shared-storage-2" +"netgear,wnr854t" diff --git a/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt b/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt new file mode 100644 index 000000000..2cdcd716d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt @@ -0,0 +1,20 @@ +MVEBU CPU Config registers +-------------------------- + +MVEBU (Marvell SOCs: Armada 370/XP) + +Required properties: + +- compatible: one of: + - "marvell,armada-370-cpu-config" + - "marvell,armada-xp-cpu-config" + +- reg: Should contain CPU config registers location and length, in + their per-CPU variant + +Example: + + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; + }; diff --git a/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt new file mode 100644 index 000000000..d24ab2ebf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt @@ -0,0 +1,18 @@ +MVEBU System Controller +----------------------- +MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x) + +Required properties: + +- compatible: one of: + - "marvell,orion-system-controller" + - "marvell,armada-370-xp-system-controller" + - "marvell,armada-375-system-controller" +- reg: Should contain system controller registers location and length. + +Example: + + system-controller@d0018200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0xd0018200 0x500>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml new file mode 100644 index 000000000..f736e8c85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC based Platforms Device Tree Bindings + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + - Matthias Brugger <matthias.bgg@gmail.com> +description: | + Boards with a MediaTek SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-evb + - const: mediatek,mt2701 + + - items: + - enum: + - mediatek,mt2712-evb + - const: mediatek,mt2712 + - items: + - enum: + - mediatek,mt6580-evbp1 + - const: mediatek,mt6580 + - items: + - enum: + - mundoreader,bq-aquaris5 + - const: mediatek,mt6589 + - items: + - enum: + - mediatek,mt6592-evb + - const: mediatek,mt6592 + - items: + - enum: + - mediatek,mt6755-evb + - const: mediatek,mt6755 + - items: + - enum: + - mediatek,mt6765-evb + - const: mediatek,mt6765 + - items: + - enum: + - mediatek,mt6779-evb + - const: mediatek,mt6779 + - items: + - enum: + - mediatek,mt6795-evb + - const: mediatek,mt6795 + - items: + - enum: + - archermind,mt6797-x20-dev + - mediatek,mt6797-evb + - const: mediatek,mt6797 + - items: + - enum: + - bananapi,bpi-r64 + - mediatek,mt7622-rfb1 + - const: mediatek,mt7622 + - items: + - enum: + - mediatek,mt7623a-rfb-emmc + - mediatek,mt7623a-rfb-nand + - mediatek,mt7623n-rfb-emmc + - bananapi,bpi-r2 + - const: mediatek,mt7623 + + - items: + - enum: + - mediatek,mt7629-rfb + - const: mediatek,mt7629 + - items: + - enum: + - mediatek,mt8127-moose + - const: mediatek,mt8127 + - items: + - enum: + - mediatek,mt8135-evbp1 + - const: mediatek,mt8135 + - description: Google Elm (Acer Chromebook R13) + items: + - const: google,elm-rev8 + - const: google,elm-rev7 + - const: google,elm-rev6 + - const: google,elm-rev5 + - const: google,elm-rev4 + - const: google,elm-rev3 + - const: google,elm + - const: mediatek,mt8173 + - description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...) + items: + - const: google,hana-rev6 + - const: google,hana-rev5 + - const: google,hana-rev4 + - const: google,hana-rev3 + - const: google,hana + - const: mediatek,mt8173 + - description: Google Hana rev7 (Poin2 Chromebook 11C) + items: + - const: google,hana-rev7 + - const: mediatek,mt8173 + - items: + - enum: + - mediatek,mt8173-evb + - const: mediatek,mt8173 + - items: + - enum: + - mediatek,mt8183-evb + - const: mediatek,mt8183 + - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) + items: + - const: google,krane-sku176 + - const: google,krane + - const: mediatek,mt8183 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt new file mode 100644 index 000000000..ea827e876 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -0,0 +1,34 @@ +Mediatek apmixedsys controller +============================== + +The Mediatek apmixedsys controller provides the PLLs to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-apmixedsys" + - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6765-apmixedsys", "syscon" + - "mediatek,mt6779-apmixedsys", "syscon" + - "mediatek,mt6797-apmixedsys" + - "mediatek,mt7622-apmixedsys" + - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" + - "mediatek,mt7629-apmixedsys" + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8167-apmixedsys", "syscon" + - "mediatek,mt8173-apmixedsys" + - "mediatek,mt8183-apmixedsys", "syscon" + - "mediatek,mt8516-apmixedsys" +- #clock-cells: Must be 1 + +The apmixedsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt new file mode 100644 index 000000000..b32d37419 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -0,0 +1,38 @@ +MediaTek AUDSYS controller +============================ + +The MediaTek AUDSYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt6765-audsys", "syscon" + - "mediatek,mt6779-audio", "syscon" + - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt8167-audiosys", "syscon" + - "mediatek,mt8183-audiosys", "syscon" + - "mediatek,mt8516-audsys", "syscon" +- #clock-cells: Must be 1 + +The AUDSYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Required sub-nodes: +------- +For common binding part and usage, refer to +../sonud/mt2701-afe-pcm.txt. + +Example: + + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + ... + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt new file mode 100644 index 000000000..149567a38 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt @@ -0,0 +1,24 @@ +Mediatek bdpsys controller +============================ + +The Mediatek bdpsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-bdpsys", "syscon" + - "mediatek,mt2712-bdpsys", "syscon" + - "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon" +- #clock-cells: Must be 1 + +The bdpsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +bdpsys: clock-controller@1c000000 { + compatible = "mediatek,mt2701-bdpsys", "syscon"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt new file mode 100644 index 000000000..a0ce82085 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt @@ -0,0 +1,24 @@ +MediaTek CAMSYS controller +============================ + +The MediaTek camsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-camsys", "syscon" + - "mediatek,mt6779-camsys", "syscon" + - "mediatek,mt8183-camsys", "syscon" +- #clock-cells: Must be 1 + +The camsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +camsys: camsys@1a000000 { + compatible = "mediatek,mt8183-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt new file mode 100644 index 000000000..6b7e8067e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -0,0 +1,27 @@ +Mediatek ethsys controller +============================ + +The Mediatek ethsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7622-ethsys", "syscon" + - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7629-ethsys", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The ethsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ethsys: clock-controller@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt new file mode 100644 index 000000000..7de43bf41 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt @@ -0,0 +1,30 @@ +MediaTek g3dsys controller +============================ + +The MediaTek g3dsys controller provides various clocks and reset controller to +the GPU. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-g3dsys", "syscon": + for MT2701 SoC + - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": + for MT7623 SoC +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The g3dsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +g3dsys: clock-controller@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt new file mode 100644 index 000000000..323905af8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt @@ -0,0 +1,26 @@ +Mediatek hifsys controller +============================ + +The Mediatek hifsys controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-hifsys", "syscon" + - "mediatek,mt7622-hifsys", "syscon" + - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" +- #clock-cells: Must be 1 + +The hifsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +hifsys: clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt new file mode 100644 index 000000000..dce4c9241 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -0,0 +1,30 @@ +Mediatek imgsys controller +============================ + +The Mediatek imgsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt2712-imgsys", "syscon" + - "mediatek,mt6765-imgsys", "syscon" + - "mediatek,mt6779-imgsys", "syscon" + - "mediatek,mt6797-imgsys", "syscon" + - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt8167-imgsys", "syscon" + - "mediatek,mt8173-imgsys", "syscon" + - "mediatek,mt8183-imgsys", "syscon" +- #clock-cells: Must be 1 + +The imgsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8173-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt new file mode 100644 index 000000000..eb3523c7a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -0,0 +1,41 @@ +Mediatek infracfg controller +============================ + +The Mediatek infracfg controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6765-infracfg", "syscon" + - "mediatek,mt6779-infracfg_ao", "syscon" + - "mediatek,mt6797-infracfg", "syscon" + - "mediatek,mt7622-infracfg", "syscon" + - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt7629-infracfg", "syscon" + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8167-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" + - "mediatek,mt8183-infracfg", "syscon" + - "mediatek,mt8516-infracfg", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The infracfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Also it uses the common reset controller binding from +Documentation/devicetree/bindings/reset/reset.txt. +The available reset outputs are defined in +dt-bindings/reset/mt*-resets.h + +Example: + +infracfg: power-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt new file mode 100644 index 000000000..2ce889b02 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt @@ -0,0 +1,22 @@ +Mediatek ipesys controller +============================ + +The Mediatek ipesys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6779-ipesys", "syscon" +- #clock-cells: Must be 1 + +The ipesys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt new file mode 100644 index 000000000..aabc8c5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt @@ -0,0 +1,43 @@ +Mediatek IPU controller +============================ + +The Mediatek ipu controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt8183-ipu_conn", "syscon" + - "mediatek,mt8183-ipu_adl", "syscon" + - "mediatek,mt8183-ipu_core0", "syscon" + - "mediatek,mt8183-ipu_core1", "syscon" +- #clock-cells: Must be 1 + +The ipu controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ipu_conn: syscon@19000000 { + compatible = "mediatek,mt8183-ipu_conn", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_adl: syscon@19010000 { + compatible = "mediatek,mt8183-ipu_adl", "syscon"; + reg = <0 0x19010000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_core0: syscon@19180000 { + compatible = "mediatek,mt8183-ipu_core0", "syscon"; + reg = <0 0x19180000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_core1: syscon@19280000 { + compatible = "mediatek,mt8183-ipu_core1", "syscon"; + reg = <0 0x19280000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt new file mode 100644 index 000000000..2df799cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt @@ -0,0 +1,22 @@ +Mediatek jpgdecsys controller +============================ + +The Mediatek jpgdecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2712-jpgdecsys", "syscon" +- #clock-cells: Must be 1 + +The jpgdecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +jpgdecsys: syscon@19000000 { + compatible = "mediatek,mt2712-jpgdecsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt new file mode 100644 index 000000000..2b882b7ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt @@ -0,0 +1,23 @@ +Mediatek mcucfg controller +============================ + +The Mediatek mcucfg controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2712-mcucfg", "syscon" + - "mediatek,mt8183-mcucfg", "syscon" +- #clock-cells: Must be 1 + +The mcucfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +mcucfg: syscon@10220000 { + compatible = "mediatek,mt2712-mcucfg", "syscon"; + reg = <0 0x10220000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt new file mode 100644 index 000000000..054424fb6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -0,0 +1,25 @@ +Mediatek mfgcfg controller +============================ + +The Mediatek mfgcfg controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2712-mfgcfg", "syscon" + - "mediatek,mt6779-mfgcfg", "syscon" + - "mediatek,mt8167-mfgcfg", "syscon" + - "mediatek,mt8183-mfgcfg", "syscon" +- #clock-cells: Must be 1 + +The mfgcfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +mfgcfg: syscon@13000000 { + compatible = "mediatek,mt2712-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt new file mode 100644 index 000000000..8be5978f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt @@ -0,0 +1,28 @@ +Mediatek mipi0a (mipi_rx_ana_csi0a) controller +============================ + +The Mediatek mipi0a controller provides various clocks +to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-mipi0a", "syscon" +- #clock-cells: Must be 1 + +The mipi0a controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The mipi0a controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +mipi0a: clock-controller@11c10000 { + compatible = "mediatek,mt6765-mipi0a", "syscon"; + reg = <0 0x11c10000 0 0x1000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt new file mode 100644 index 000000000..d8c9108c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -0,0 +1,30 @@ +Mediatek mmsys controller +============================ + +The Mediatek mmsys system controller provides clock control, routing control, +and miscellaneous control in mmsys partition. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt2712-mmsys", "syscon" + - "mediatek,mt6765-mmsys", "syscon" + - "mediatek,mt6779-mmsys", "syscon" + - "mediatek,mt6797-mmsys", "syscon" + - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt8173-mmsys", "syscon" + - "mediatek,mt8183-mmsys", "syscon" +- #clock-cells: Must be 1 + +For the clock control, the mmsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +mmsys: syscon@14000000 { + compatible = "mediatek,mt8173-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt new file mode 100644 index 000000000..d179a6153 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt @@ -0,0 +1,25 @@ +MediaTek PCIESYS controller +============================ + +The MediaTek PCIESYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-pciesys", "syscon" + - "mediatek,mt7629-pciesys", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The PCIESYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +pciesys: pciesys@1a100800 { + compatible = "mediatek,mt7622-pciesys", "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml new file mode 100644 index 000000000..8723dfe34 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Peripheral Configuration Controller + +maintainers: + - Bartosz Golaszewski <bgolaszewski@baylibre.com> + +description: + The Mediatek pericfg controller provides various clocks and reset outputs + to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pericfg + - mediatek,mt2712-pericfg + - mediatek,mt6765-pericfg + - mediatek,mt7622-pericfg + - mediatek,mt7629-pericfg + - mediatek,mt8135-pericfg + - mediatek,mt8173-pericfg + - mediatek,mt8183-pericfg + - mediatek,mt8516-pericfg + - const: syscon + - items: + # Special case for mt7623 for backward compatibility + - const: mediatek,mt7623-pericfg + - const: mediatek,mt2701-pericfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pericfg@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + pericfg@10003000 { + compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt new file mode 100644 index 000000000..30cb645c0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -0,0 +1,23 @@ +MediaTek SGMIISYS controller +============================ + +The MediaTek SGMIISYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-sgmiisys", "syscon" + - "mediatek,mt7629-sgmiisys", "syscon" +- #clock-cells: Must be 1 + +The SGMIISYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", "syscon"; + reg = <0 0x1b128000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt new file mode 100644 index 000000000..7cb02c930 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt @@ -0,0 +1,25 @@ +MediaTek SSUSBSYS controller +============================ + +The MediaTek SSUSBSYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-ssusbsys", "syscon" + - "mediatek,mt7629-ssusbsys", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The SSUSBSYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt new file mode 100644 index 000000000..5ce7578cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -0,0 +1,34 @@ +Mediatek topckgen controller +============================ + +The Mediatek topckgen controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-topckgen" + - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6765-topckgen", "syscon" + - "mediatek,mt6779-topckgen", "syscon" + - "mediatek,mt6797-topckgen" + - "mediatek,mt7622-topckgen" + - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" + - "mediatek,mt7629-topckgen" + - "mediatek,mt8135-topckgen" + - "mediatek,mt8167-topckgen", "syscon" + - "mediatek,mt8173-topckgen" + - "mediatek,mt8183-topckgen", "syscon" + - "mediatek,mt8516-topckgen" +- #clock-cells: Must be 1 + +The topckgen controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +topckgen: power-controller@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt new file mode 100644 index 000000000..c877bcc1a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt @@ -0,0 +1,27 @@ +Mediatek vcodecsys controller +============================ + +The Mediatek vcodecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-vcodecsys", "syscon" +- #clock-cells: Must be 1 + +The vcodecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The vcodecsys controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +venc_gcon: clock-controller@17000000 { + compatible = "mediatek,mt6765-vcodecsys", "syscon"; + reg = <0 0x17000000 0 0x10000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt new file mode 100644 index 000000000..981951691 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt @@ -0,0 +1,29 @@ +Mediatek vdecsys controller +============================ + +The Mediatek vdecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2701-vdecsys", "syscon" + - "mediatek,mt2712-vdecsys", "syscon" + - "mediatek,mt6779-vdecsys", "syscon" + - "mediatek,mt6797-vdecsys", "syscon" + - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" + - "mediatek,mt8167-vdecsys", "syscon" + - "mediatek,mt8173-vdecsys", "syscon" + - "mediatek,mt8183-vdecsys", "syscon" +- #clock-cells: Must be 1 + +The vdecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt8173-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt new file mode 100644 index 000000000..3cc299fd7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt @@ -0,0 +1,22 @@ +Mediatek vencltsys controller +============================ + +The Mediatek vencltsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8173-vencltsys", "syscon" +- #clock-cells: Must be 1 + +The vencltsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +vencltsys: clock-controller@19000000 { + compatible = "mediatek,mt8173-vencltsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt new file mode 100644 index 000000000..6a6a14e15 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt @@ -0,0 +1,26 @@ +Mediatek vencsys controller +============================ + +The Mediatek vencsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2712-vencsys", "syscon" + - "mediatek,mt6779-vencsys", "syscon" + - "mediatek,mt6797-vencsys", "syscon" + - "mediatek,mt8173-vencsys", "syscon" + - "mediatek,mt8183-vencsys", "syscon" +- #clock-cells: Must be 1 + +The vencsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +vencsys: clock-controller@18000000 { + compatible = "mediatek,mt8173-vencsys", "syscon"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml new file mode 100644 index 000000000..6193388c6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Boards Device Tree Bindings + +maintainers: + - Lars Povlsen <lars.povlsen@microchip.com> + +description: |+ + The Microchip Sparx5 SoC is a ARMv8-based used in a family of + gigabit TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of switching + features such as advanced TCAM-based VLAN and QoS processing + enabling delivery of differentiated services, and security through + TCAM-based frame processing using versatile content aware processor + (VCAP) + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The Sparx5 pcb125 board is a modular board, + which has both spi-nor and eMMC storage. The modular design + allows for connection of different network ports. + items: + - const: microchip,sparx5-pcb125 + - const: microchip,sparx5 + + - description: The Sparx5 pcb134 is a pizzabox form factor + gigabit switch with 20 SFP ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb134 + - const: microchip,sparx5 + + - description: The Sparx5 pcb135 is a pizzabox form factor + gigabit switch with 48+4 Cu ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb135 + - const: microchip,sparx5 + + axi@600000000: + type: object + description: the root node in the Sparx5 platforms must contain + an axi bus child node. They are always at physical address + 0x600000000 in all the Sparx5 variants. + properties: + compatible: + items: + - const: simple-bus + + required: + - compatible + +required: + - compatible + - axi@600000000 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/moxart.yaml b/Documentation/devicetree/bindings/arm/moxart.yaml new file mode 100644 index 000000000..670d24ce8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/moxart.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/moxart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MOXA ART device tree bindings + +maintainers: + - Jonas Jensen <jonas.jensen@gmail.com> + +properties: + compatible: + description: UC-7112-LX embedded computer + items: + - const: moxa,moxart-uc-7112-lx + - const: moxa,moxart + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000..0d244b999 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml new file mode 100644 index 000000000..d58116136 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Platforms Device Tree Bindings + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: PXA168 Aspenite Board + items: + - enum: + - mrvl,pxa168-aspenite + - const: mrvl,pxa168 + - description: PXA910 DKB Board + items: + - enum: + - mrvl,pxa910-dkb + - const: mrvl,pxa910 + - description: MMP2 based boards + items: + - enum: + - mrvl,mmp2-brownstone + - olpc,xo-1.75 + - const: mrvl,mmp2 + - description: MMP3 based boards + items: + - enum: + - dell,wyse-ariel + - const: marvell,mmp3 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt new file mode 100644 index 000000000..31af1cbb6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt @@ -0,0 +1,17 @@ +* Marvell Tauros2 Cache + +Required properties: +- compatible : Should be "marvell,tauros2-cache". +- marvell,tauros2-cache-features : Specify the features supported for the + tauros2 cache. + The features including + CACHE_TAUROS2_PREFETCH_ON (1 << 0) + CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + The definition can be found at + arch/arm/include/asm/hardware/cache-tauros2.h + +Example: + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file mode 100644 index 000000000..6ce0b212e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -0,0 +1,84 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * Standby + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +Standby: Standby does a little more in addition to architectural clock gating. +When the WFI instruction is executed the ARM core would gate its internal +clocks. In addition to gating the clocks, QCOM cpus use this instruction as a +trigger to execute the SPM state machine. The SPM state machine waits for the +interrupt to trigger the core back in to active. This triggers the cache +hierarchy to enter standby states, when all cpus are idle. An interrupt brings +the SPM state machine out of its wait, the next step is to ensure that the +cache hierarchy is also out of standby, and then the cpu is allowed to resume +execution. This state is defined as a generic ARM WFI state by the ARM cpuidle +driver and is not defined in the DT. The SPM state machine should be +configured to execute this state by default and after executing every other +state below. + +Retention: Retention is a low power state where the core is clock gated and +the memory and the registers associated with the core are retained. The +voltage may be reduced to the minimum value needed to keep the processor +registers active. The SPM should be configured to execute the retention +sequence and would wait for interrupt, before restoring the cpu to execution +state. Retention may have a slightly higher latency than Standby. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between the time it enters idle and the next known wake up. SPC mode is used +to indicate a core entering a power down state without consulting any other +cpu or the system resources. This helps save power only on that core. The SPM +sequence for this idle state is programmed to power down the supply to the +core, wait for the interrupt, restore power to the core, and ensure the +system state including cache hierarchy is ready before allowing core to +resume. Applying power and resetting the core causes the core to warmboot +back into Elevation Level (EL) which trampolines the control back to the +kernel. Entering a power down state for the cpu, needs to be done by trapping +into a EL. Failing to do so, would result in a crash enforced by the warm boot +code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to +be flushed in s/w, before powering down the core. + +Power Collapse: This state is similar to the SPC mode, but distinguishes +itself in that the cpu acknowledges and permits the SoC to enter deeper sleep +modes. In a hierarchical power domain SoC, this means L2 and other caches can +be flushed, system bus, clocks - lowered, and SoC main XO clock gated and +voltages reduced, provided all cpus enter this state. Since the span of low +power modes possible at this state is vast, the exit latency and the residency +of this low power mode would be considered high even though at a cpu level, +this essentially is cpu power down. The SPM in this state also may handshake +with the Resource power manager (RPM) processor in the SoC to indicate a +complete application processor subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the idle-states device node. + +The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be one of - + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + and "arm,idle-state". + +Other required and optional properties are specified in [1]. + +Example: + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + +[1]. Documentation/devicetree/bindings/arm/idle-states.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt new file mode 100644 index 000000000..7f696362a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt @@ -0,0 +1,49 @@ +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. +There is one ACC register region per CPU within the KPSS remapped region as +well as an alias register region that remaps accesses to the ACC associated +with the CPU accessing the region. + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "qcom,kpss-acc-v1" + "qcom,kpss-acc-v2" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the first element specifies the base address and size of + the register region. An optional second element specifies + the base address and size of the alias register region. + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: reference to the pll parents. + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: must be "pll8_vote", "pxo". + +- clock-output-names: + Usage: optional + Value type: <string> + Definition: Name of the output clock. Typically acpuX_aux where X is a + CPU number starting at 0. + +Example: + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x02088000 0x1000>, + <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt new file mode 100644 index 000000000..e62875895 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt @@ -0,0 +1,44 @@ +Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: should be one of the following. The generic compatible + "qcom,kpss-gcc" should also be included. + "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" + "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" + "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" + "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: base address and size of the register region + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: reference to the pll parents. + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: must be "pll8_vote", "pxo". + +- clock-output-names: + Usage: required + Value type: <string> + Definition: Name of the output clock. Typically acpu_l2_aux indicating + an L2 cache auxiliary clock. + +Example: + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml new file mode 100644 index 000000000..c3a8604df --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Last Level Cache Controller + +maintainers: + - Rishabh Bhatnagar <rishabhb@codeaurora.org> + - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + +description: | + LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, + that can be shared by multiple clients. Clients here are different cores in the + SoC, the idea is to minimize the local caches at the clients and migrate to + common pool of memory. Cache memory is divided into partitions called slices + which are assigned to clients. Clients can query the slice details, activate + and deactivate them. + +properties: + compatible: + enum: + - qcom,sc7180-llcc + - qcom,sdm845-llcc + + reg: + items: + - description: LLCC base register region + - description: LLCC broadcast base register region + + reg-names: + items: + - const: llcc_base + - const: llcc_broadcast_base + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt new file mode 100644 index 000000000..ae4afc6dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt @@ -0,0 +1,57 @@ +SPM AVS Wrapper 2 (SAW2) + +The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the +Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable +power-controller that transitions a piece of hardware (like a processor or +subsystem) into and out of low power modes via a direct connection to +the PMIC. It can also be wired up to interact with other processors in the +system, notifying them when a low power state is entered or exited. + +Multiple revisions of the SAW hardware are supported using these Device Nodes. +SAW2 revisions differ in the register offset and configuration data. Also, the +same revision of the SAW in different SoCs may have different configuration +data due the the differences in hardware capabilities. Hence the SoC name, the +version of the SAW hardware in that SoC and the distinction between cpu (big +or Little) or cache, may be needed to uniquely identify the SAW register +configuration and initialization data. The compatible string is used to +indicate this parameter. + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: Must have + "qcom,saw2" + A more specific value could be one of: + "qcom,apq8064-saw2-v1.1-cpu" + "qcom,msm8974-saw2-v2.1-cpu" + "qcom,apq8084-saw2-v2.1-cpu" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the first element specifies the base address and size of + the register region. An optional second element specifies + the base address and size of the alias register region. + +- regulator: + Usage: optional + Value type: boolean + Definition: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached + to. + +Example 1: + + power-controller@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + +Example 2: + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/ssbi.txt b/Documentation/devicetree/bindings/arm/msm/ssbi.txt new file mode 100644 index 000000000..54fd5ced3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/ssbi.txt @@ -0,0 +1,18 @@ +* Qualcomm SSBI + +Some Qualcomm MSM devices contain a point-to-point serial bus used to +communicate with a limited range of devices (mostly power management +chips). + +These require the following properties: + +- compatible: "qcom,ssbi" + +- qcom,controller-type + indicates the SSBI bus variant the controller should use to talk + with the slave device. This should be one of "ssbi", "ssbi2", or + "pmic-arbiter". The type chosen is determined by the attached + slave. + +The slave device should be the single child node of the ssbi device +with a compatible field. diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml new file mode 100644 index 000000000..6816bd68f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml new file mode 100644 index 000000000..7c787405b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar platforms device tree bindings + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: infinity boards + items: + - enum: + - thingyjp,breadbee-crust # thingy.jp BreadBee Crust + - const: mstar,infinity + + - description: infinity3 boards + items: + - enum: + - thingyjp,breadbee # thingy.jp BreadBee + - const: mstar,infinity3 + + - description: mercury5 boards + items: + - enum: + - 70mai,midrived08 # 70mai midrive d08 + - const: mstar,mercury5 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt new file mode 100644 index 000000000..2d87d9ece --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt @@ -0,0 +1,6 @@ +NPCM Platforms Device Tree Bindings +----------------------------------- +NPCM750 SoC +Required root node properties: + - compatible = "nuvoton,npcm750"; + diff --git a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml new file mode 100644 index 000000000..c9675c4cd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 CPU Complex device tree bindings + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + - Sumit Gupta <sumitg@nvidia.com> + +description: |+ + Tegra194 SOC has homogeneous architecture where each cluster has two + symmetric cores. Compatible string in "cpus" node represents the CPU + Complex having all clusters. + +properties: + $nodename: + const: cpus + + compatible: + enum: + - nvidia,tegra194-ccplex + + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the bpmp node that needs to be queried to get + operating point data for all CPUs. + +additionalProperties: true + +examples: + - | + cpus { + compatible = "nvidia,tegra194-ccplex"; + nvidia,bpmp = <&bpmp>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0_0: cpu@0 { + compatible = "nvidia,tegra194-carmel"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu0_1: cpu@1 { + compatible = "nvidia,tegra194-carmel"; + device_type = "cpu"; + reg = <0x001>; + enable-method = "psci"; + }; + + cpu1_0: cpu@100 { + compatible = "nvidia,tegra194-carmel"; + device_type = "cpu"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu1_1: cpu@101 { + compatible = "nvidia,tegra194-carmel"; + device_type = "cpu"; + reg = <0x101>; + enable-method = "psci"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml new file mode 100644 index 000000000..214c97bc3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/nxp/lpc32xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx Platforms Device Tree Bindings + +maintainers: + - Roland Stigge <stigge@antcom.de> + +properties: + compatible: + oneOf: + - enum: + - nxp,lpc3220 + - nxp,lpc3230 + - nxp,lpc3240 + - items: + - enum: + - ea,ea3250 + - phytec,phy3250 + - const: nxp,lpc3250 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt new file mode 100644 index 000000000..5bd8aa091 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/counter.txt @@ -0,0 +1,15 @@ +OMAP Counter-32K bindings + +Required properties: +- compatible: Must be "ti,omap-counter32k" for OMAP controllers +- reg: Contains timer register address range (base address and length) +- ti,hwmods: Name of the hwmod associated to the counter, which is typically + "counter_32k" + +Example: + +counter32k: counter@4a304000 { + compatible = "ti,omap-counter32k"; + reg = <0x4a304000 0x20>; + ti,hwmods = "counter_32k"; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt new file mode 100644 index 000000000..a43e4c7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt @@ -0,0 +1,55 @@ +Some socs have a large number of interrupts requests to service +the needs of its many peripherals and subsystems. All of the +interrupt lines from the subsystems are not needed at the same +time, so they have to be muxed to the irq-controller appropriately. +In such places a interrupt controllers are preceded by an CROSSBAR +that provides flexibility in muxing the device requests to the controller +inputs. + +Required properties: +- compatible : Should be "ti,irq-crossbar" +- reg: Base address and the size of the crossbar registers. +- interrupt-controller: indicates that this block is an interrupt controller. +- ti,max-irqs: Total number of irqs available at the parent interrupt controller. +- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. +- ti,reg-size: Size of a individual register in bytes. Every individual + register is assumed to be of same size. Valid sizes are 1, 2, 4. +- ti,irqs-reserved: List of the reserved irq lines that are not muxed using + crossbar. These interrupt lines are reserved in the soc, + so crossbar bar driver should not consider them as free + lines. + +Optional properties: +- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for + SOC-specific hard-wiring of those irqs which unexpectedly bypasses the + crossbar. These irqs have a crossbar register, but still cannot be used. + +- ti,irqs-safe-map: integer which maps to a safe configuration to use + when the interrupt controller irq is unused (when not provided, default is 0) + +Examples: + crossbar_mpu: crossbar@4a002a48 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = <400>; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + }; + +Consumer: +======== +See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and +Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for +further details. + +An interrupt consumer on an SoC using crossbar will use: + interrupts = <GIC_SPI request_number interrupt_level> + +Example: + device_x@4a023000 { + /* Crossbar 8 used */ + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + ... + }; diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt new file mode 100644 index 000000000..f35b77920 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -0,0 +1,82 @@ +OMAP Control Module bindings + +Control Module contains miscellaneous features under it based on SoC type. +Pincontrol is one common feature, and it has a specialized support +described in [1]. Typically some clock nodes are also under control module. +Syscon is used to share register level access to drivers external to +control module driver itself. + +See [2] for documentation about clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +[2] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-scm" + "ti,am4-scm" + "ti,dm814-scrm" + "ti,dm816-scrm" + "ti,omap2-scm" + "ti,omap3-scm" + "ti,omap4-scm-core" + "ti,omap4-scm-padconf-core" + "ti,omap4-scm-wkup" + "ti,omap4-scm-padconf-wkup" + "ti,omap5-scm-core" + "ti,omap5-scm-padconf-core" + "ti,omap5-scm-wkup-pad-conf" + "ti,dra7-scm-core" +- reg: Contains Control Module register address range + (base address and length) + +Optional properties: +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Examples: + +scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x230>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; +} + +&scm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt new file mode 100644 index 000000000..8bd6d0a23 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/dmm.txt @@ -0,0 +1,22 @@ +OMAP Dynamic Memory Manager (DMM) bindings + +The dynamic memory manager (DMM) is a module located immediately in front of the +SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory +accesses such as priority generation amongst initiators, configuration of SDRAM +interleaving, optimizing transfer of 2D block objects, and provide MMU-like page +translation for initiators which need contiguous dma bus addresses. + +Required properties: +- compatible: Should contain "ti,omap4-dmm" for OMAP4 family + Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family +- reg: Contains DMM register address range (base address and length) +- interrupts: Should contain an interrupt-specifier for DMM_IRQ. +- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" + +Example: + +dmm@4e000000 { + compatible = "ti,omap4-dmm"; + reg = <0x4e000000 0x800>; + ti,hwmods = "dmm"; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt new file mode 100644 index 000000000..d3830a32c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/dsp.txt @@ -0,0 +1,14 @@ +* TI - DSP (Digital Signal Processor) + +TI DSP included in OMAP SoC + +Required properties: +- compatible : Should be "ti,omap3-c64" for OMAP3 & 4 +- ti,hwmods: "dsp" + +Examples: + +dsp { + compatible = "ti,omap3-c64"; + ti,hwmods = "dsp"; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt new file mode 100644 index 000000000..6d6295171 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/iva.txt @@ -0,0 +1,19 @@ +* TI - IVA (Imaging and Video Accelerator) subsystem + +The IVA contain various audio, video or imaging HW accelerator +depending of the version. + +Required properties: +- compatible : Should be: + - "ti,ivahd" for OMAP4 + - "ti,iva2.2" for OMAP3 + - "ti,iva2.1" for OMAP2430 + - "ti,iva1" for OMAP2420 +- ti,hwmods: "iva" + +Examples: + +iva { + compatible = "ti,ivahd", "ti,iva"; + ti,hwmods = "iva"; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt new file mode 100644 index 000000000..161448da9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt @@ -0,0 +1,23 @@ +* TI - L3 Network On Chip (NoC) + +This version is an implementation of the generic NoC IP +provided by Arteris. + +Required properties: +- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family + Should be "ti,omap4-l3-noc" for OMAP4 family + Should be "ti,omap5-l3-noc" for OMAP5 family + Should be "ti,dra7-l3-noc" for DRA7 family + Should be "ti,am4372-l3-noc" for AM43 family +- reg: Contains L3 register address range for each noc domain. +- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. + +Examples: + +ocp { + compatible = "ti,omap4-l3-noc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt new file mode 100644 index 000000000..6816adcdc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -0,0 +1,37 @@ +L4 interconnect bindings + +These bindings describe the OMAP SoCs L4 interconnect bus. + +Required properties: +- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus + Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus + Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus + Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus + Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus + Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus + Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus + Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus + Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus + Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus + Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus + Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus +- ranges : contains the IO map range for the bus +- reg : registers link agent and interconnect agent and access protection +- reg-names : "la" for link agent, "ia0" to "ia3" for one to three + interconnect agent instances, "ap" for access if it exists + +Examples: + +l4: interconnect@48000000 { + compatible "ti,omap4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt new file mode 100644 index 000000000..e41490e69 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt @@ -0,0 +1,54 @@ +* TI - MPU (Main Processor Unit) subsystem + +The MPU subsystem contain one or several ARM cores +depending of the version. +The MPU contain CPUs, GIC, L2 cache and a local PRCM. + +Required properties: +- compatible : Should be "ti,omap3-mpu" for OMAP3 + Should be "ti,omap4-mpu" for OMAP4 + Should be "ti,omap5-mpu" for OMAP5 +- ti,hwmods: "mpu" + +Optional properties: +- sram: Phandle to the ocmcram node + +am335x and am437x only: +- pm-sram: Phandles to ocmcram nodes to be used for power management. + First should be type 'protect-exec' for the driver to use to copy + and run PM functions, second should be regular pool to be used for + data region for code. See Documentation/devicetree/bindings/sram/sram.yaml + for more details. + +Examples: + +- For an OMAP5 SMP system: + +mpu { + compatible = "ti,omap5-mpu"; + ti,hwmods = "mpu" +}; + +- For an OMAP4 SMP system: + +mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; +}; + + +- For an OMAP3 monocore system: + +mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; +}; + +- For an AM335x system: + +mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt new file mode 100644 index 000000000..fa8b31660 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -0,0 +1,225 @@ +* Texas Instruments OMAP + +OMAP is currently using a static file per SoC family to describe the +IPs present in the SoC. +On top of that an omap_device is created to extend the platform_device +capabilities and to allow binding with one or several hwmods. +The hwmods will contain all the information to build the device: +address range, irq lines, dma lines, interconnect, PRCM register, +clock domain, input clocks. +For the moment just point to the existing hwmod, the next step will be +to move data from hwmod to device-tree representation. + + +Required properties: +- compatible: Every devices present in OMAP SoC should be in the + form: "ti,XXX" +- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP + HW documentation, attached to a device. Must contain at least + one hwmod. + +Optional properties: +- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module + during suspend. +- ti,no-reset-on-init: When present, the module should not be reset at init +- ti,no-idle-on-init: When present, the module should not be idled at init +- ti,no-idle: When present, the module is never allowed to idle. + +Example: + +spinlock@1 { + compatible = "ti,omap4-spinlock"; + ti,hwmods = "spinlock"; +}; + +SoC Type (optional): + +- General Purpose devices + compatible = "ti,gp" +- High Security devices + compatible = "ti,hs" + +SoC Families: + +- OMAP2 generic - defaults to OMAP2420 + compatible = "ti,omap2" +- OMAP3 generic + compatible = "ti,omap3" +- OMAP4 generic - defaults to OMAP4430 + compatible = "ti,omap4" +- OMAP5 generic - defaults to OMAP5430 + compatible = "ti,omap5" +- DRA7 generic - defaults to DRA742 + compatible = "ti,dra7" +- AM33x generic + compatible = "ti,am33xx" +- AM43x generic - defaults to AM4372 + compatible = "ti,am43" + +SoCs: + +- OMAP2420 + compatible = "ti,omap2420", "ti,omap2" +- OMAP2430 + compatible = "ti,omap2430", "ti,omap2" + +- OMAP3430 + compatible = "ti,omap3430", "ti,omap3" + legacy: "ti,omap34xx" - please do not use any more +- AM3517 + compatible = "ti,am3517", "ti,omap3" +- OMAP3630 + compatible = "ti,omap3630", "ti,omap3" + legacy: "ti,omap36xx" - please do not use any more +- AM335x + compatible = "ti,am33xx" + +- OMAP4430 + compatible = "ti,omap4430", "ti,omap4" +- OMAP4460 + compatible = "ti,omap4460", "ti,omap4" + +- OMAP5430 + compatible = "ti,omap5430", "ti,omap5" +- OMAP5432 + compatible = "ti,omap5432", "ti,omap5" + +- DRA762 + compatible = "ti,dra762", "ti,dra7" + +- DRA742 + compatible = "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 + compatible = "ti,dra722", "ti,dra72", "ti,dra7" + +- DRA718 + compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" + +- AM5748 + compatible = "ti,am5748", "ti,dra762", "ti,dra7" + +- AM5728 + compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5726 + compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5718 + compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7" + +- AM5716 + compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7" + +- AM4372 + compatible = "ti,am4372", "ti,am43" + +Boards (incomplete list of examples): + +- OMAP3 BeagleBoard : Low cost community board + compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" + +- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3" + +- OMAP3 Tobi with Overo : Commercial expansion board with daughter board + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" + +- OMAP4 SDP : Software Development Board + compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4" + +- OMAP4 PandaBoard : Low cost community board + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4" + +- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board + compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + +- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN + compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + +- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen + compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + +- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x + compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3" + +- AM335X EVM : Software Development Board for AM335x + compatible = "ti,am335x-evm", "ti,am33xx" + +- AM335X Bone : Low cost community board + compatible = "ti,am335x-bone", "ti,am33xx" + +- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM. + compatible = "ti,am3359-icev2", "ti,am33xx" + +- AM335X OrionLXm : Substation Automation Platform + compatible = "novatech,am335x-lxm", "ti,am33xx" + +- AM335X phyBOARD-WEGA: Single Board Computer dev kit + compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx" + +- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4 + compatible = "compulab,cm-t335", "ti,am33xx" + +- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4 + compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx" + +- AM335X phyCORE-AM335x: Development kit + compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx" + +- AM335x phyBOARD-REGOR: Single Board Computer + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx" + +- AM335X UC-8100-ME-T: Communication-centric industrial computing platform + compatible = "moxa,uc-8100-me-t", "ti,am33xx"; + +- OMAP5 EVM : Evaluation Module + compatible = "ti,omap5-evm", "ti,omap5" + +- AM437x CM-T43 + compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" + +- AM437x SBC-T43 + compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" + +- AM43x EPOS EVM + compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x" + +- AM437x GP EVM + compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" + +- AM437x SK EVM: AM437x StarterKit Evaluation Module + compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" + +- AM57XX CL-SOM-AM57x + compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM57XX SBC-AM57x + compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5748 IDK + compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; + +- AM5728 IDK + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5718 IDK + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7" + +- DRA762 EVM: Software Development Board for DRA762 + compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7" + +- DRA742 EVM: Software Development Board for DRA742 + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 EVM: Software Development Board for DRA722 + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" + +- DRA718 EVM: Software Development Board for DRA718 + compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" + +- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" + +- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3" diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt new file mode 100644 index 000000000..3eb6d7aff --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -0,0 +1,63 @@ +OMAP PRCM bindings + +Power Reset and Clock Manager lists the device clocks and clockdomains under +a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it, +each describing one module and the clock hierarchy under it. see [1] for +documentation about the individual clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-prcm" + "ti,am4-prcm" + "ti,omap2-prcm" + "ti,omap3-prm" + "ti,omap3-cm" + "ti,omap4-cm1" + "ti,omap4-prm" + "ti,omap4-cm2" + "ti,omap4-scrm" + "ti,omap5-prm" + "ti,omap5-cm-core-aon" + "ti,omap5-scrm" + "ti,omap5-cm-core" + "ti,dra7-prm" + "ti,dra7-cm-core-aon" + "ti,dra7-cm-core" + "ti,dm814-prcm" + "ti,dm816-prcm" +- reg: Contains PRCM module register address range + (base address and length) +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Example: + +cm: cm@48004000 { + compatible = "ti,omap3-cm"; + reg = <0x48004000 0x4000>; + + cm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_clockdomains: clockdomains { + }; +} + +&cm_clocks { + omap2_32k_fck: omap_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000..42db138e0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,31 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must contain one of the following: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" + and additionally must contain: + "ti,omap-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #power-domain-cells: Should be 0 if the instance is a power domain provider. +- #reset-cells: Should be 1 if the PRM instance in question supports resets. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b00 0x40>; + #power-domain-cells = <0>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt new file mode 100644 index 000000000..ac64e60f9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/oxnas.txt @@ -0,0 +1,14 @@ +Oxford Semiconductor OXNAS SoCs Family device tree bindings +------------------------------------------- + +Boards with the OX810SE SoC shall have the following properties: + Required root node property: + compatible: "oxsemi,ox810se" + +Boards with the OX820 SoC shall have the following properties: + Required root node property: + compatible: "oxsemi,ox820" + +Board compatible values: + - "wd,mbwe" (OX810SE) + - "cloudengines,pogoplugv3" (OX820) diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt new file mode 100644 index 000000000..e75c0ef51 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/picoxcell.txt @@ -0,0 +1,24 @@ +Picochip picoXcell device tree bindings. +======================================== + +Required root node properties: + - compatible: + - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. + - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. + - "picochip,pc3x3" : picoXcell PC3X3 device based board. + - "picochip,pc3x2" : picoXcell PC3X2 device based board. + +Timers required properties: + - compatible = "picochip,pc3x2-timer" + - interrupts : The single IRQ line for the timer. + - clock-freq : The frequency in HZ of the timer. + - reg : The register bank for the timer. + +Note: two timers are required - one for the scheduler clock and one for the +event tick/NOHZ. + +VIC required properties: + - compatible = "arm,pl192-vic". + - interrupt-controller. + - reg : The register bank for the device. + - #interrupt-cells : Must be 1. diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml new file mode 100644 index 000000000..693ef3f18 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Performance Monitor Units + +maintainers: + - Mark Rutland <mark.rutland@arm.com> + - Will Deacon <will.deacon@arm.com> + +description: |+ + ARM cores often have a PMU for counting cpu and cache events like cache misses + and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU + representation in the device tree should be done as under:- + +properties: + compatible: + items: + - enum: + - apm,potenza-pmu + - arm,armv8-pmuv3 # Only for s/w models + - arm,arm1136-pmu + - arm,arm1176-pmu + - arm,arm11mpcore-pmu + - arm,cortex-a5-pmu + - arm,cortex-a7-pmu + - arm,cortex-a8-pmu + - arm,cortex-a9-pmu + - arm,cortex-a12-pmu + - arm,cortex-a15-pmu + - arm,cortex-a17-pmu + - arm,cortex-a32-pmu + - arm,cortex-a34-pmu + - arm,cortex-a35-pmu + - arm,cortex-a53-pmu + - arm,cortex-a55-pmu + - arm,cortex-a57-pmu + - arm,cortex-a65-pmu + - arm,cortex-a72-pmu + - arm,cortex-a73-pmu + - arm,cortex-a75-pmu + - arm,cortex-a76-pmu + - arm,cortex-a77-pmu + - arm,neoverse-e1-pmu + - arm,neoverse-n1-pmu + - brcm,vulcan-pmu + - cavium,thunder-pmu + - qcom,krait-pmu + - qcom,scorpion-pmu + - qcom,scorpion-mp-pmu + + interrupts: + # Don't know how many CPUs, so no constraints to specify + description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. + + interrupt-affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + qcom,no-pc-write: + type: boolean + description: + Indicates that this PMU doesn't support the 0xc and 0xd events. + + secure-reg-access: + type: boolean + description: + Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +required: + - compatible + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/arm/primecell.yaml b/Documentation/devicetree/bindings/arm/primecell.yaml new file mode 100644 index 000000000..e15fe00aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/primecell.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/primecell.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Primecell Peripherals + +maintainers: + - Rob Herring <robh@kernel.org> + +description: |+ + ARM, Ltd. Primecell peripherals have a standard id register that can be used to + identify the peripheral type, vendor, and revision. This value can be used for + driver matching. + +properties: + compatible: + contains: + const: arm,primecell + description: + Should be a specific name for the peripheral followed by "arm,primecell". + The specific name will match the ARM engineering name for the logic block + in the form "arm,pl???" + + arm,primecell-periphid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Value to override the h/w ID value + clocks: + minItems: 1 + maxItems: 32 + clock-names: + contains: + const: apb_pclk + additionalItems: true + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml new file mode 100644 index 000000000..8b77cf83a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -0,0 +1,268 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/psci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Power State Coordination Interface (PSCI) + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: |+ + Firmware implementing the PSCI functions described in ARM document number + ARM DEN 0022A ("Power State Coordination Interface System Software on ARM + processors") can be used by Linux to initiate various CPU-centric power + operations. + + Issue A of the specification describes functions for CPU suspend, hotplug + and migration of secure software. + + Functions are invoked by trapping to the privilege level of the PSCI + firmware (specified as part of the binding below) and passing arguments + in a manner similar to that specified by AAPCS: + + r0 => 32-bit Function ID / return value + {r1 - r3} => Parameters + + Note that the immediate field of the trapping instruction must be set + to #0. + + [2] Power State Coordination Interface (PSCI) specification + http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf + +properties: + $nodename: + const: psci + + compatible: + oneOf: + - description: + For implementations complying to PSCI versions prior to 0.2. + const: arm,psci + + - description: + For implementations complying to PSCI 0.2. + const: arm,psci-0.2 + + - description: + For implementations complying to PSCI 0.2. + Function IDs are not required and should be ignored by an OS with + PSCI 0.2 support, but are permitted to be present for compatibility + with existing software when "arm,psci" is later in the compatible + list. + items: + - const: arm,psci-0.2 + - const: arm,psci + + - description: + For implementations complying to PSCI 1.0. + const: arm,psci-1.0 + + - description: + For implementations complying to PSCI 1.0. + PSCI 1.0 is backward compatible with PSCI 0.2 with minor + specification updates, as defined in the PSCI specification[2]. + items: + - const: arm,psci-1.0 + - const: arm,psci-0.2 + + method: + description: The method of calling the PSCI firmware. + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + # HVC #0, with the register assignments specified in this binding. + - hvc + + cpu_suspend: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Function ID for CPU_SUSPEND operation + + cpu_off: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Function ID for CPU_OFF operation + + cpu_on: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Function ID for CPU_ON operation + + migrate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Function ID for MIGRATE operation + + arm,psci-suspend-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + power_state parameter to pass to the PSCI suspend call. + + Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie + idle state nodes with entry-method property is set to "psci", as per + bindings in [1]) must specify this property. + + [1] Kernel documentation - ARM idle states bindings + Documentation/devicetree/bindings/arm/idle-states.yaml + +patternProperties: + "^power-domain-": + $ref: "../power/power-domain.yaml#" + + type: object + description: | + ARM systems can have multiple cores, sometimes in an hierarchical + arrangement. This often, but not always, maps directly to the processor + power topology of the system. Individual nodes in a topology have their + own specific power states and can be better represented hierarchically. + + For these cases, the definitions of the idle states for the CPUs and the + CPU topology, must conform to the binding in [3]. The idle states + themselves must conform to the binding in [4] and must specify the + arm,psci-suspend-param property. + + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated + (OSI) CPU suspend mode is introduced. Using a hierarchical representation + helps to implement support for OSI mode and OS implementations may choose + to mandate it. + + [3] Documentation/devicetree/bindings/power/power-domain.yaml + [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml + +required: + - compatible + - method + +allOf: + - if: + properties: + compatible: + contains: + const: arm,psci + then: + required: + - cpu_off + - cpu_on + +additionalProperties: false + +examples: + - |+ + + // Case 1: PSCI v0.1 only. + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x95c10000>; + cpu_off = <0x95c10001>; + cpu_on = <0x95c10002>; + migrate = <0x95c10003>; + }; + + - |+ + + // Case 2: PSCI v0.2 only + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + + - |+ + + // Case 3: PSCI v0.2 and PSCI v0.1. + + /* + * A DTB may provide IDs for use by kernels without PSCI 0.2 support, + * enabling firmware and hypervisors to support existing and new kernels. + * These IDs will be ignored by kernels with PSCI 0.2 support, which will + * use the standard PSCI 0.2 IDs exclusively. + */ + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "hvc"; + + cpu_on = <0x95c10002>; + cpu_off = <0x95c10001>; + }; + + - |+ + + // Case 4: CPUs and CPU idle states described using the hierarchical model. + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + }; + + domain-idle-states { + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml new file mode 100644 index 000000000..42ec1d5fe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM device tree bindings + +maintainers: + - Stephen Boyd <sboyd@codeaurora.org> + +description: | + Some qcom based bootloaders identify the dtb blob based on a set of + device properties like SoC and platform and revisions of those components. + To support this scheme, we encode this information into the board compatible + string. + + Each board must specify a top-level board compatible string with the following + format: + + compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]" + + The 'SoC' and 'board' elements are required. All other elements are optional. + + The 'SoC' element must be one of the following strings: + + apq8016 + apq8074 + apq8084 + apq8096 + ipq6018 + ipq8074 + mdm9615 + msm8916 + msm8974 + msm8992 + msm8994 + msm8996 + sc7180 + sdm630 + sdm660 + sdm845 + sm8250 + + The 'board' element must be one of the following strings: + + cdp + cp01-c1 + dragonboard + hk01 + hk10-c1 + hk10-c2 + idp + liquid + mtp + qrd + sbc + + The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> + where the minor number may be omitted when it's zero, i.e. v1.0 is the same + as v1. If all versions of the 'board_version' elements match, then a + wildcard '*' should be used, e.g. 'v*'. + + The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. + + Examples: + + "qcom,msm8916-v1-cdp-pm8916-v2.1" + + A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version + 2.1. + + "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" + + A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in + foundry 2. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - qcom,apq8016-sbc + - const: qcom,apq8016 + + - items: + - enum: + - qcom,apq8064-cm-qs600 + - qcom,apq8064-ifc6410 + - const: qcom,apq8064 + + - items: + - enum: + - qcom,apq8074-dragonboard + - const: qcom,apq8074 + + - items: + - enum: + - qcom,apq8060-dragonboard + - qcom,msm8660-surf + - const: qcom,msm8660 + + - items: + - enum: + - qcom,apq8084-mtp + - qcom,apq8084-sbc + - const: qcom,apq8084 + + - items: + - enum: + - qcom,msm8960-cdp + - const: qcom,msm8960 + + - items: + - enum: + - fairphone,fp2 + - lge,hammerhead + - sony,xperia-amami + - sony,xperia-castor + - sony,xperia-honami + - const: qcom,msm8974 + + - items: + - const: qcom,msm8916-mtp + - const: qcom,msm8916-mtp/1 + - const: qcom,msm8916 + + - items: + - enum: + - longcheer,l8150 + - samsung,a3u-eur + - samsung,a5u-eur + - const: qcom,msm8916 + + - items: + - const: qcom,msm8996-mtp + + - items: + - enum: + - qcom,ipq4019-ap-dk04.1-c3 + - qcom,ipq4019-ap-dk07.1-c1 + - qcom,ipq4019-ap-dk07.1-c2 + - qcom,ipq4019-dk04.1-c1 + - const: qcom,ipq4019 + + - items: + - enum: + - qcom,ipq8064-ap148 + - const: qcom,ipq8064 + + - items: + - enum: + - qcom,ipq8074-hk01 + - qcom,ipq8074-hk10-c1 + - qcom,ipq8074-hk10-c2 + - const: qcom,ipq8074 + + - items: + - enum: + - qcom,sc7180-idp + - const: qcom,sc7180 + + - items: + - enum: + - xiaomi,lavender + - const: qcom,sdm660 + + - items: + - enum: + - qcom,ipq6018-cp01-c1 + - const: qcom,ipq6018 + + - items: + - enum: + - qcom,qrb5165-rb5 + - qcom,sm8250-mtp + - const: qcom,sm8250 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/rda.yaml b/Documentation/devicetree/bindings/arm/rda.yaml new file mode 100644 index 000000000..a5c0444aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rda.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro platforms device tree bindings + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + $nodename: + const: "/" + compatible: + items: + - enum: + - xunlong,orangepi-2g-iot # Orange Pi 2G-IoT + - xunlong,orangepi-i96 # Orange Pi i96 + - const: rda,8810pl + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml new file mode 100644 index 000000000..9fb0297fe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/realtek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek platforms device tree bindings + +maintainers: + - Andreas Färber <afaerber@suse.de> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + # RTD1195 SoC based boards + - items: + - enum: + - mele,x1000 # MeLE X1000 + - realtek,horseradish # Realtek Horseradish EVB + - const: realtek,rtd1195 + + # RTD1293 SoC based boards + - items: + - enum: + - synology,ds418j # Synology DiskStation DS418j + - const: realtek,rtd1293 + + # RTD1295 SoC based boards + - items: + - enum: + - mele,v9 # MeLE V9 + - probox2,ava # ProBox2 AVA + - xnano,x5 # Xnano X5 + - zidoo,x9s # Zidoo X9S + - const: realtek,rtd1295 + + # RTD1296 SoC based boards + - items: + - enum: + - synology,ds418 # Synology DiskStation DS418 + - const: realtek,rtd1296 + + # RTD1395 SoC based boards + - items: + - enum: + - bananapi,bpi-m4 # Banana Pi BPI-M4 + - realtek,lion-skin # Realtek Lion Skin EVB + - const: realtek,rtd1395 + + # RTD1619 SoC based boards + - items: + - enum: + - realtek,mjolnir # Realtek Mjolnir EVB + - const: realtek,rtd1619 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml new file mode 100644 index 000000000..1f80767da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/renesas,prr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Product Register + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: | + Most Renesas ARM SoCs have a Product Register or Boundary Scan ID + Register that allows to retrieve SoC product and revision information. + If present, a device node for this register should be added. + +properties: + compatible: + enum: + - renesas,prr + - renesas,bsid + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0xff000044 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml new file mode 100644 index 000000000..ff94c45ee --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -0,0 +1,304 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/renesas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Emma Mobile EV2 + items: + - enum: + - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual + - const: renesas,emev2 + + - description: RZ/A1H (R7S72100) + items: + - enum: + - renesas,genmai # Genmai (RTK772100BC00000BR) + - renesas,gr-peach # GR-Peach (X28A-M01-E/F) + - renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE) + - const: renesas,r7s72100 + + - description: RZ/A2 (R7S9210) + items: + - enum: + - renesas,rza2mevb # RZ/A2M Eval Board (RTK7921053S00000BE) + - const: renesas,r7s9210 + + - description: SH-Mobile AG5 (R8A73A00/SH73A0) + items: + - enum: + - renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT + - const: renesas,sh73a0 + + - description: R-Mobile APE6 (R8A73A40) + items: + - enum: + - renesas,ape6evm + - const: renesas,r8a73a4 + + - description: R-Mobile A1 (R8A77400) + items: + - enum: + - renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA + - const: renesas,r8a7740 + + - description: RZ/G1H (R8A77420) + items: + - enum: + # iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven) + - iwave,g21m + - const: renesas,r8a7742 + + - items: + - enum: + # iWave Systems RZ/G1H Qseven Development Platform (iW-RainboW-G21D-Qseven) + - iwave,g21d + - const: iwave,g21m + - const: renesas,r8a7742 + + - description: RZ/G1M (R8A77430) + items: + - enum: + # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7743 + + - items: + - enum: + # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE) + - const: renesas,r8a7743 + + - description: RZ/G1N (R8A77440) + items: + - enum: + # iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7744 + + - items: + - enum: + # iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - const: renesas,r8a7744 + + - description: RZ/G1E (R8A77450) + items: + - enum: + - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) + - renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE) + - const: renesas,r8a7745 + + - description: iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) + items: + - const: iwave,g22d + - const: iwave,g22m + - const: renesas,r8a7745 + + - description: RZ/G1C (R8A77470) + items: + - enum: + - iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + - const: renesas,r8a77470 + + - description: RZ/G2M (R8A774A1) + items: + - enum: + - hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform + - beacon,beacon-rzg2m # Beacon EmbeddedWorks RZ/G2M Kit + - const: renesas,r8a774a1 + + - items: + - enum: + - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms + - const: hoperun,hihope-rzg2m + - const: renesas,r8a774a1 + + - description: RZ/G2N (R8A774B1) + items: + - enum: + - hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform + - const: renesas,r8a774b1 + + - items: + - enum: + - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms + - const: hoperun,hihope-rzg2n + - const: renesas,r8a774b1 + + - description: RZ/G2E (R8A774C0) + items: + - enum: + - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874) + - const: renesas,r8a774c0 + + - items: + - enum: + - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875) + - const: si-linux,cat874 + - const: renesas,r8a774c0 + + - description: RZ/G2H (R8A774E1) + items: + - enum: + - hoperun,hihope-rzg2h # HopeRun HiHope RZ/G2H platform + - const: renesas,r8a774e1 + + - items: + - enum: + - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms + - const: hoperun,hihope-rzg2h + - const: renesas,r8a774e1 + + - description: R-Car M1A (R8A77781) + items: + - enum: + - renesas,bockw + - const: renesas,r8a7778 + + - description: R-Car H1 (R8A77790) + items: + - enum: + - renesas,marzen # Marzen (R0P7779A00010S) + - const: renesas,r8a7779 + + - description: R-Car H2 (R8A77900) + items: + - enum: + - renesas,lager # Lager (RTP0RC7790SEB00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) + - const: renesas,r8a7790 + + - description: R-Car M2-W (R8A77910) + items: + - enum: + - renesas,henninger + - renesas,koelsch # Koelsch (RTP0RC7791SEB00010S) + - renesas,porter # Porter (M2-LCDP) + - const: renesas,r8a7791 + + - description: R-Car V2H (R8A77920) + items: + - enum: + - renesas,blanche # Blanche (RTP0RC7792SEB00010S) + - renesas,wheat # Wheat (RTP0RC7792ASKB0000JE) + - const: renesas,r8a7792 + + - description: R-Car M2-N (R8A77930) + items: + - enum: + - renesas,gose # Gose (RTP0RC7793SEB00010S) + - const: renesas,r8a7793 + + - description: R-Car E2 (R8A77940) + items: + - enum: + - renesas,alt # Alt (RTP0RC7794SEB00010S) + - renesas,silk # SILK (RTP0RC7794LCB00011S) + - const: renesas,r8a7794 + + - description: R-Car H3 (R8A77950) + items: + - enum: + # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) + # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) + - renesas,h3ulcb + - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) + - const: renesas,r8a7795 + + - description: R-Car M3-W (R8A77960) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) + - const: renesas,r8a7796 + + - description: R-Car M3-W+ (R8A77961) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP8J77961ASKB0SK0SA05A (M3 ES3.0)) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A) + - const: renesas,r8a77961 + + - description: Kingfisher (SBEV-RCAR-KF-M03) + items: + - const: shimafuji,kingfisher + - enum: + - renesas,h3ulcb + - renesas,m3ulcb + - renesas,m3nulcb + - enum: + - renesas,r8a7795 + - renesas,r8a7796 + - renesas,r8a77965 + + - description: R-Car M3-N (R8A77965) + items: + - enum: + - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N)) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) + - const: renesas,r8a77965 + + - description: R-Car V3M (R8A77970) + items: + - enum: + - renesas,eagle # Eagle (RTP0RC77970SEB0010S) + - renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10) + - const: renesas,r8a77970 + + - description: R-Car V3H (R8A77980) + items: + - enum: + - renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) + - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) + - const: renesas,r8a77980 + + - description: R-Car E3 (R8A77990) + items: + - enum: + - renesas,ebisu # Ebisu (RTP0RC77990SEB0010S) + - const: renesas,r8a77990 + + - description: R-Car D3 (R8A77995) + items: + - enum: + - renesas,draak # Draak (RTP0RC77995SEB0010S) + - const: renesas,r8a77995 + + - description: R-Car V3U (R8A779A0) + items: + - enum: + - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S) + - const: renesas,r8a779a0 + + - items: + - enum: + - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S) + - const: renesas,falcon-cpu + - const: renesas,r8a779a0 + + - description: RZ/N1D (R9A06G032) + items: + - enum: + - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) + - const: renesas,r9a06g032 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml new file mode 100644 index 000000000..b621752aa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -0,0 +1,575 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip platforms device tree bindings + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) + items: + - const: vamrs,ficus + - const: rockchip,rk3399 + + - description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + items: + - const: vamrs,rock960 + - const: rockchip,rk3399 + + - description: Amarula Vyasa RK3288 + items: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + - const: rockchip,rk3288 + + - description: Asus Tinker board S + items: + - const: asus,rk3288-tinker-s + - const: rockchip,rk3288 + + - description: Beelink A1 + items: + - const: azw,beelink-a1 + - const: rockchip,rk3328 + + - description: bq Curie 2 tablet + items: + - const: mundoreader,bq-curie2 + - const: rockchip,rk3066a + + - description: bq Edison 2 Quad-Core tablet + items: + - const: mundoreader,bq-edison2qc + - const: rockchip,rk3188 + + - description: ChipSPARK PopMetal-RK3288 + items: + - const: chipspark,popmetal-rk3288 + - const: rockchip,rk3288 + + - description: ChipSPARK Rayeager PX2 + items: + - const: chipspark,rayeager-px2 + - const: rockchip,rk3066a + + - description: Elgin RV1108 R1 + items: + - const: elgin,rv1108-r1 + - const: rockchip,rv1108 + + - description: Firefly Firefly-RK3288 + items: + - enum: + - firefly,firefly-rk3288 + - firefly,firefly-rk3288-beta + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3288 Reload + items: + - const: firefly,firefly-rk3288-reload + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3399 + items: + - const: firefly,firefly-rk3399 + - const: rockchip,rk3399 + + - description: Firefly ROC-RK3308-CC + items: + - const: firefly,roc-rk3308-cc + - const: rockchip,rk3308 + + - description: Firefly roc-rk3328-cc + items: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + + - description: Firefly ROC-RK3399-PC + items: + - enum: + - firefly,roc-rk3399-pc + - firefly,roc-rk3399-pc-mezzanine + - const: rockchip,rk3399 + + - description: FriendlyElec NanoPi R2S + items: + - const: friendlyarm,nanopi-r2s + - const: rockchip,rk3328 + + - description: FriendlyElec NanoPi4 series boards + items: + - enum: + - friendlyarm,nanopc-t4 + - friendlyarm,nanopi-m4 + - friendlyarm,nanopi-neo4 + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + items: + - const: geekbuying,geekbox + - const: rockchip,rk3368 + + - description: Google Bob (Asus Chromebook Flip C101PA) + items: + - const: google,bob-rev13 + - const: google,bob-rev12 + - const: google,bob-rev11 + - const: google,bob-rev10 + - const: google,bob-rev9 + - const: google,bob-rev8 + - const: google,bob-rev7 + - const: google,bob-rev6 + - const: google,bob-rev5 + - const: google,bob-rev4 + - const: google,bob + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Brain (dev-board) + items: + - const: google,veyron-brain-rev0 + - const: google,veyron-brain + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Fievel (AOPEN Chromebox Mini) + items: + - const: google,veyron-fievel-rev8 + - const: google,veyron-fievel-rev7 + - const: google,veyron-fievel-rev6 + - const: google,veyron-fievel-rev5 + - const: google,veyron-fievel-rev4 + - const: google,veyron-fievel-rev3 + - const: google,veyron-fievel-rev2 + - const: google,veyron-fievel-rev1 + - const: google,veyron-fievel-rev0 + - const: google,veyron-fievel + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Gru (dev-board) + items: + - const: google,gru-rev15 + - const: google,gru-rev14 + - const: google,gru-rev13 + - const: google,gru-rev12 + - const: google,gru-rev11 + - const: google,gru-rev10 + - const: google,gru-rev9 + - const: google,gru-rev8 + - const: google,gru-rev7 + - const: google,gru-rev6 + - const: google,gru-rev5 + - const: google,gru-rev4 + - const: google,gru-rev3 + - const: google,gru-rev2 + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Jaq (Haier Chromebook 11 and more w/ uSD) + items: + - const: google,veyron-jaq-rev5 + - const: google,veyron-jaq-rev4 + - const: google,veyron-jaq-rev3 + - const: google,veyron-jaq-rev2 + - const: google,veyron-jaq-rev1 + - const: google,veyron-jaq + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jerry (Hisense Chromebook C11 and more) + items: + - const: google,veyron-jerry-rev15 + - const: google,veyron-jerry-rev14 + - const: google,veyron-jerry-rev13 + - const: google,veyron-jerry-rev12 + - const: google,veyron-jerry-rev11 + - const: google,veyron-jerry-rev10 + - const: google,veyron-jerry-rev7 + - const: google,veyron-jerry-rev6 + - const: google,veyron-jerry-rev5 + - const: google,veyron-jerry-rev4 + - const: google,veyron-jerry-rev3 + - const: google,veyron-jerry + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Kevin (Samsung Chromebook Plus) + items: + - const: google,kevin-rev15 + - const: google,kevin-rev14 + - const: google,kevin-rev13 + - const: google,kevin-rev12 + - const: google,kevin-rev11 + - const: google,kevin-rev10 + - const: google,kevin-rev9 + - const: google,kevin-rev8 + - const: google,kevin-rev7 + - const: google,kevin-rev6 + - const: google,kevin + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Mickey (Asus Chromebit CS10) + items: + - const: google,veyron-mickey-rev8 + - const: google,veyron-mickey-rev7 + - const: google,veyron-mickey-rev6 + - const: google,veyron-mickey-rev5 + - const: google,veyron-mickey-rev4 + - const: google,veyron-mickey-rev3 + - const: google,veyron-mickey-rev2 + - const: google,veyron-mickey-rev1 + - const: google,veyron-mickey-rev0 + - const: google,veyron-mickey + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Mighty (Haier Chromebook 11 and more w/ SD) + items: + - const: google,veyron-mighty-rev5 + - const: google,veyron-mighty-rev4 + - const: google,veyron-mighty-rev3 + - const: google,veyron-mighty-rev2 + - const: google,veyron-mighty-rev1 + - const: google,veyron-mighty + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Minnie (Asus Chromebook Flip C100P) + items: + - const: google,veyron-minnie-rev4 + - const: google,veyron-minnie-rev3 + - const: google,veyron-minnie-rev2 + - const: google,veyron-minnie-rev1 + - const: google,veyron-minnie-rev0 + - const: google,veyron-minnie + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Pinky (dev-board) + items: + - const: google,veyron-pinky-rev2 + - const: google,veyron-pinky + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku7 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku7 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku7 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku7 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku7 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku7 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku7 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku7 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku7 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku7 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku7 + - const: google,scarlet-rev4 + - const: google,scarlet-rev3-sku7 + - const: google,scarlet-rev3 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Speedy (Asus C201 Chromebook) + items: + - const: google,veyron-speedy-rev9 + - const: google,veyron-speedy-rev8 + - const: google,veyron-speedy-rev7 + - const: google,veyron-speedy-rev6 + - const: google,veyron-speedy-rev5 + - const: google,veyron-speedy-rev4 + - const: google,veyron-speedy-rev3 + - const: google,veyron-speedy-rev2 + - const: google,veyron-speedy + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Tiger (AOpen Chromebase Mini) + items: + - const: google,veyron-tiger-rev8 + - const: google,veyron-tiger-rev7 + - const: google,veyron-tiger-rev6 + - const: google,veyron-tiger-rev5 + - const: google,veyron-tiger-rev4 + - const: google,veyron-tiger-rev3 + - const: google,veyron-tiger-rev2 + - const: google,veyron-tiger-rev1 + - const: google,veyron-tiger-rev0 + - const: google,veyron-tiger + - const: google,veyron + - const: rockchip,rk3288 + + - description: Haoyu MarsBoard RK3066 + items: + - const: haoyu,marsboard-rk3066 + - const: rockchip,rk3066a + + - description: Hardkernel Odroid Go Advance + items: + - const: hardkernel,rk3326-odroid-go2 + - const: rockchip,rk3326 + + - description: Hugsun X99 TV Box + items: + - const: hugsun,x99 + - const: rockchip,rk3399 + + - description: Khadas Edge series boards + items: + - enum: + - khadas,edge + - khadas,edge-captain + - khadas,edge-v + - const: rockchip,rk3399 + + - description: Mecer Xtreme Mini S6 + items: + - const: mecer,xms6 + - const: rockchip,rk3229 + + - description: Leez RK3399 P710 + items: + - const: leez,p710 + - const: rockchip,rk3399 + + - description: mqmaker MiQi + items: + - const: mqmaker,miqi + - const: rockchip,rk3288 + + - description: Netxeon R89 board + items: + - const: netxeon,r89 + - const: rockchip,rk3288 + + - description: Orange Pi RK3399 board + items: + - const: rockchip,rk3399-orangepi + - const: rockchip,rk3399 + + - description: Phytec phyCORE-RK3288 Rapid Development Kit + items: + - const: phytec,rk3288-pcm-947 + - const: phytec,rk3288-phycore-som + - const: rockchip,rk3288 + + - description: Pine64 PinebookPro + items: + - const: pine64,pinebook-pro + - const: rockchip,rk3399 + + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + - const: rockchip,rk3328 + + - description: Pine64 RockPro64 + items: + - enum: + - pine64,rockpro64-v2.1 + - pine64,rockpro64-v2.0 + - const: pine64,rockpro64 + - const: rockchip,rk3399 + + - description: Radxa Rock + items: + - const: radxa,rock + - const: rockchip,rk3188 + + - description: Radxa ROCK Pi 4A/B/C + items: + - enum: + - radxa,rockpi4a + - radxa,rockpi4b + - radxa,rockpi4c + - const: radxa,rockpi4 + - const: rockchip,rk3399 + + - description: Radxa ROCK Pi N8 + items: + - const: radxa,rockpi-n8 + - const: vamrs,rk3288-vmarc-som + - const: rockchip,rk3288 + + - description: Radxa ROCK Pi N10 + items: + - const: radxa,rockpi-n10 + - const: vamrs,rk3399pro-vmarc-som + - const: rockchip,rk3399pro + + - description: Radxa Rock2 Square + items: + - const: radxa,rock2-square + - const: rockchip,rk3288 + + - description: Rikomagic MK808 v1 + items: + - const: rikomagic,mk808 + - const: rockchip,rk3066a + + - description: Rockchip Kylin + items: + - const: rockchip,rk3036-kylin + - const: rockchip,rk3036 + + - description: Rockchip PX3 Evaluation board + items: + - const: rockchip,px3-evb + - const: rockchip,px3 + - const: rockchip,rk3188 + + - description: Rockchip PX30 Evaluation board + items: + - const: rockchip,px30-evb + - const: rockchip,px30 + + - description: Rockchip PX5 Evaluation board + items: + - const: rockchip,px5-evb + - const: rockchip,px5 + - const: rockchip,rk3368 + + - description: Rockchip R88 + items: + - const: rockchip,r88 + - const: rockchip,rk3368 + + - description: Rockchip RK3036 Evaluation board + items: + - const: rockchip,rk3036-evb + - const: rockchip,rk3036 + + - description: Rockchip RK3228 Evaluation board + items: + - const: rockchip,rk3228-evb + - const: rockchip,rk3228 + + - description: Rockchip RK3229 Evaluation board + items: + - const: rockchip,rk3229-evb + - const: rockchip,rk3229 + + - description: Rockchip RK3288 Evaluation board + items: + - enum: + - rockchip,rk3288-evb-act8846 + - rockchip,rk3288-evb-rk808 + - const: rockchip,rk3288 + + - description: Rockchip RK3308 Evaluation board + items: + - const: rockchip,rk3308-evb + - const: rockchip,rk3308 + + - description: Rockchip RK3328 Evaluation board + items: + - const: rockchip,rk3328-evb + - const: rockchip,rk3328 + + - description: Rockchip RK3368 Evaluation board (act8846 pmic) + items: + - const: rockchip,rk3368-evb-act8846 + - const: rockchip,rk3368 + + - description: Rockchip RK3399 Evaluation board + items: + - const: rockchip,rk3399-evb + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire standalone + items: + - const: rockchip,rk3399-sapphire + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire with Excavator Baseboard + items: + - const: rockchip,rk3399-sapphire-excavator + - const: rockchip,rk3399 + + - description: Rockchip RV1108 Evaluation board + items: + - const: rockchip,rv1108-evb + - const: rockchip,rv1108 + + - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard + items: + - const: tsd,rk3368-lion-haikou + - const: rockchip,rk3368 + + - description: Theobroma Systems RK3399-Q7 with Haikou baseboard + items: + - const: tsd,rk3399-puma-haikou + - const: rockchip,rk3399 + + - description: Tronsmart Orion R68 Meta + items: + - const: tronsmart,orion-r68-meta + - const: rockchip,rk3368 + + - description: Zkmagic A95X Z2 + items: + - const: zkmagic,a95x-z2 + - const: rockchip,rk3318 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt new file mode 100644 index 000000000..3ee9b428b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt @@ -0,0 +1,16 @@ +Rockchip power-management-unit: +------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : = "rockchip,rk3066-pmu"; +- reg : physical base address and the size of the registers window + +Example: + + pmu@20004000 { + compatible = "rockchip,rk3066-pmu"; + reg = <0x20004000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt new file mode 100644 index 000000000..3b8fbf3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt @@ -0,0 +1,19 @@ +ARM Dual Cluster System Configuration Block +------------------------------------------- + +The Dual Cluster System Configuration Block (DCSCB) provides basic +functionality for controlling clocks, resets and configuration pins in +the Dual Cluster System implemented by the Real-Time System Model (RTSM). + +Required properties: + +- compatible : should be "arm,rtsm,dcscb" + +- reg : physical base address and the size of the registers window + +Example: + + dcscb@60000000 { + compatible = "arm,rtsm,dcscb"; + reg = <0x60000000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml new file mode 100644 index 000000000..f99c0c6df --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Chipid driver + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + items: + - const: samsung,exynos4210-chipid + + reg: + maxItems: 1 + + samsung,asv-bin: + description: + Adaptive Supply Voltage bin selection. This can be used + to determine the ASV bin of an SoC if respective information + is missing in the CHIPID registers or in the OTP memory. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + samsung,asv-bin = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml new file mode 100644 index 000000000..17678d968 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Power Management Unit (PMU) + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - samsung-s5pv210-pmu + required: + - compatible + +properties: + compatible: + items: + - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - samsung-s5pv210-pmu + - const: syscon + + reg: + maxItems: 1 + + assigned-clock-parents: true + assigned-clocks: true + + '#clock-cells': + const: 1 + + clock-names: + description: + List of clock names for particular CLKOUT mux inputs + minItems: 1 + maxItems: 32 + items: + pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$' + + clocks: + minItems: 1 + maxItems: 32 + + interrupt-controller: + description: + Some PMUs are capable of behaving as an interrupt controller (mostly + to wake up a suspended PMU). + + '#interrupt-cells': + description: + Must be identical to the that of the parent interrupt controller. + const: 3 + + syscon-poweroff: + $ref: "../../power/reset/syscon-poweroff.yaml#" + type: object + description: + Node for power off method + + syscon-reboot: + $ref: "../../power/reset/syscon-reboot.yaml#" + type: object + description: + Node for reboot method + +required: + - compatible + - reg + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + then: + required: + - '#clock-cells' + - clock-names + - clocks + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "syscon"; + reg = <0x10040000 0x5000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml new file mode 100644 index 000000000..272508010 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos and S5P SoC based boards + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: S5PV210 based boards + items: + - enum: + - aesop,torbreck # aESOP Torbreck based on S5PV210 + - samsung,aquila # Samsung Aquila based on S5PC110 + - samsung,goni # Samsung Goni based on S5PC110 + - yic,smdkc110 # YIC System SMDKC110 based on S5PC110 + - yic,smdkv210 # YIC System SMDKV210 based on S5PV210 + - const: samsung,s5pv210 + + - description: S5PV210 based Aries boards + items: + - enum: + - samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P) + - samsung,galaxys # Samsung Galaxy S (i9000) + - const: samsung,aries + - const: samsung,s5pv210 + + - description: Exynos3250 based boards + items: + - enum: + - samsung,monk # Samsung Simband + - samsung,rinato # Samsung Gear2 + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Samsung ARTIK5 boards + items: + - enum: + - samsung,artik5-eval # Samsung ARTIK5 eval board + - const: samsung,artik5 # Samsung ARTIK5 module + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Exynos4210 based boards + items: + - enum: + - insignal,origen # Insignal Origen + - samsung,i9100 # Samsung Galaxy S2 (GT-I9100) + - samsung,smdkv310 # Samsung SMDKV310 eval + - samsung,trats # Samsung Tizen Reference + - samsung,universal_c210 # Samsung C210 + - const: samsung,exynos4210 + - const: samsung,exynos4 + + - description: Exynos4412 based boards + items: + - enum: + - friendlyarm,tiny4412 # FriendlyARM TINY4412 + - hardkernel,odroid-u3 # Hardkernel Odroid U3 + - hardkernel,odroid-x # Hardkernel Odroid X + - hardkernel,odroid-x2 # Hardkernel Odroid X2 + - insignal,origen4412 # Insignal Origen + - samsung,smdk4412 # Samsung SMDK4412 eval + - topeet,itop4412-elite # TOPEET Elite base + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Samsung Midas family boards + items: + - enum: + - samsung,i9300 # Samsung GT-I9300 + - samsung,i9305 # Samsung GT-I9305 + - samsung,n710x # Samsung GT-N7100/GT-N7105 + - samsung,trats2 # Samsung Tizen Reference + - const: samsung,midas + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Exynos5250 based boards + items: + - enum: + - google,snow-rev5 # Google Snow Rev 5+ + - google,spring # Google Spring + - insignal,arndale # Insignal Arndale + - samsung,smdk5250 # Samsung SMDK5250 eval + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Google Snow Boards (Rev 4+) + items: + - const: google,snow-rev4 + - const: google,snow + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Exynos5260 based boards + items: + - enum: + - samsung,xyref5260 # Samsung Xyref5260 eval + - const: samsung,exynos5260 + - const: samsung,exynos5 + + - description: Exynos5410 based boards + items: + - enum: + - hardkernel,odroid-xu # Hardkernel Odroid XU + - samsung,smdk5410 # Samsung SMDK5410 eval + - const: samsung,exynos5410 + - const: samsung,exynos5 + + - description: Exynos5420 based boards + items: + - enum: + - insignal,arndale-octa # Insignal Arndale Octa + - samsung,smdk5420 # Samsung SMDK5420 eval + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Google Peach Pit Boards (Rev 6+) + items: + - const: google,pit-rev16 + - const: google,pit-rev15 + - const: google,pit-rev14 + - const: google,pit-rev13 + - const: google,pit-rev12 + - const: google,pit-rev11 + - const: google,pit-rev10 + - const: google,pit-rev9 + - const: google,pit-rev8 + - const: google,pit-rev7 + - const: google,pit-rev6 + - const: google,pit + - const: google,peach + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Exynos5800 based boards + items: + - enum: + - hardkernel,odroid-xu3 # Hardkernel Odroid XU3 + - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite + - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 + - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Google Peach Pi Boards (Rev 10+) + items: + - const: google,pi-rev16 + - const: google,pi-rev15 + - const: google,pi-rev14 + - const: google,pi-rev13 + - const: google,pi-rev12 + - const: google,pi-rev11 + - const: google,pi-rev10 + - const: google,pi + - const: google,peach + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Exynos5433 based boards + items: + - enum: + - samsung,tm2 # Samsung TM2 + - samsung,tm2e # Samsung TM2E + - const: samsung,exynos5433 + + - description: Exynos7 based boards + items: + - enum: + - samsung,exynos7-espresso # Samsung Exynos7 Espresso + - const: samsung,exynos7 + +required: + - compatible + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml new file mode 100644 index 000000000..3d9abad3c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Secure Firmware + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + items: + - const: samsung,secure-firmware + + reg: + description: + Address of non-secure SYSRAM used for communication with firmware. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + firmware@203f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt new file mode 100644 index 000000000..74d0a780c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/scu.txt @@ -0,0 +1,28 @@ +* ARM Snoop Control Unit (SCU) + +As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided +with a Snoop Control Unit. The register range is usually 256 (0x100) +bytes. + +References: + +- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual + Revision r2p0 +- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual + Revision r0p1 +- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference + Manial Revision r2p0 + +- compatible : Should be: + "arm,cortex-a9-scu" + "arm,cortex-a5-scu" + "arm,arm11mp-scu" + +- reg : Specify the base address and the size of the SCU register window. + +Example: + +scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; +}; diff --git a/Documentation/devicetree/bindings/arm/secure.txt b/Documentation/devicetree/bindings/arm/secure.txt new file mode 100644 index 000000000..f27bbff2c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/secure.txt @@ -0,0 +1,70 @@ +* ARM Secure world bindings + +ARM CPUs with TrustZone support have two distinct address spaces, +"Normal" and "Secure". Most devicetree consumers (including the Linux +kernel) are not TrustZone aware and run entirely in either the Normal +world or the Secure world. However some devicetree consumers are +TrustZone aware and need to be able to determine whether devices are +visible only in the Secure address space, only in the Normal address +space, or visible in both. (One example of that situation would be a +virtual machine which boots Secure firmware and wants to tell the +firmware about the layout of the machine via devicetree.) + +The general principle of the naming scheme for Secure world bindings +is that any property that needs a different value in the Secure world +can be supported by prefixing the property name with "secure-". So for +instance "secure-foo" would override "foo". For property names with +a vendor prefix, the Secure variant of "vendor,foo" would be +"vendor,secure-foo". If there is no "secure-" property then the Secure +world value is the same as specified for the Normal world by the +non-prefixed property. However, only the properties listed below may +validly have "secure-" versions; this list will be enlarged on a +case-by-case basis. + +Defining the bindings in this way means that a device tree which has +been annotated to indicate the presence of Secure-only devices can +still be processed unmodified by existing Non-secure software (and in +particular by the kernel). + +Note that it is still valid for bindings intended for purely Secure +world consumers (like kernels that run entirely in Secure) to simply +describe the view of Secure world using the standard bindings. These +secure- bindings only need to be used where both the Secure and Normal +world views need to be described in a single device tree. + +Valid Secure world properties +----------------------------- + +- secure-status : specifies whether the device is present and usable + in the secure world. The combination of this with "status" allows + the various possible combinations of device visibility to be + specified. If "secure-status" is not specified it defaults to the + same value as "status"; if "status" is not specified either then + both default to "okay". This means the following combinations are + possible: + + /* Neither specified: default to visible in both S and NS */ + secure-status = "okay"; /* visible in both */ + status = "okay"; /* visible in both */ + status = "okay"; secure-status = "okay"; /* visible in both */ + secure-status = "disabled"; /* NS-only */ + status = "okay"; secure-status = "disabled"; /* NS-only */ + status = "disabled"; secure-status = "okay"; /* S-only */ + status = "disabled"; /* disabled in both */ + status = "disabled"; secure-status = "disabled"; /* disabled in both */ + +The secure-chosen node +---------------------- + +Similar to the /chosen node which serves as a place for passing data +between firmware and the operating system, the /secure-chosen node may +be used to pass data to the Secure OS. Only the properties defined +below may appear in the /secure-chosen node. + +- stdout-path : specifies the device to be used by the Secure OS for + its console output. The syntax is the same as for /chosen/stdout-path. + If the /secure-chosen node exists but the stdout-path property is not + present, the Secure OS should not perform any console output. If + /secure-chosen does not exist, the Secure OS should use the value of + /chosen/stdout-path instead (that is, use the same device as the + Normal world OS). diff --git a/Documentation/devicetree/bindings/arm/sirf.yaml b/Documentation/devicetree/bindings/arm/sirf.yaml new file mode 100644 index 000000000..b25eb35d1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sirf.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sirf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CSR SiRFprimaII and SiRFmarco device tree bindings. + +maintainers: + - Binghua Duan <binghua.duan@csr.com> + - Barry Song <Baohua.Song@csr.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sirf,atlas6-cb + - const: sirf,atlas6 + - items: + - const: sirf,atlas7-cb + - const: sirf,atlas7 + - items: + - const: sirf,prima2-cb + - const: sirf,prima2 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 000000000..aa1d4afbc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya <sugaya.taichi@socionext.com> + - Takao Orito <orito.takao@socionext.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml new file mode 100644 index 000000000..2e765bb3e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier outer cache controller + +description: | + UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache + controller system. All of them have a level 2 cache controller, and some + have a level 3 cache controller as well. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-system-cache + + reg: + description: | + should contain 3 regions: control register, revision register, + operation register, in this order. + minItems: 3 + maxItems: 3 + + interrupts: + description: | + Interrupts can be used to notify the completion of cache operations. + The number of interrupts should match to the number of CPU cores. + The specified interrupts correspond to CPU0, CPU1, ... in this order. + minItems: 1 + maxItems: 4 + + cache-unified: true + + cache-size: true + + cache-sets: true + + cache-line-size: true + + cache-level: + minimum: 2 + maximum: 3 + + next-level-cache: true + +allOf: + - $ref: /schemas/cache-controller.yaml# + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-unified + - cache-size + - cache-sets + - cache-line-size + - cache-level + +examples: + - | + // System with L2. + cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x140000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + - | + // System with L2 and L3. + // L2 should specify the next level cache by 'next-level-cache'. + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: cache-controller@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml new file mode 100644 index 000000000..8c0e91658 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier platform device tree bindings + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + $nodename: + const: / + compatible: + oneOf: + - description: LD4 SoC boards + items: + - enum: + - socionext,uniphier-ld4-ref + - const: socionext,uniphier-ld4 + - description: Pro4 SoC boards + items: + - enum: + - socionext,uniphier-pro4-ace + - socionext,uniphier-pro4-ref + - socionext,uniphier-pro4-sanji + - const: socionext,uniphier-pro4 + - description: sLD8 SoC boards + items: + - enum: + - socionext,uniphier-sld8-ref + - const: socionext,uniphier-sld8 + - description: PXs2 SoC boards + items: + - enum: + - socionext,uniphier-pxs2-gentil + - socionext,uniphier-pxs2-vodka + - const: socionext,uniphier-pxs2 + - description: LD6b SoC boards + items: + - enum: + - socionext,uniphier-ld6b-ref + - const: socionext,uniphier-ld6b + - description: LD11 SoC boards + items: + - enum: + - socionext,uniphier-ld11-global + - socionext,uniphier-ld11-ref + - const: socionext,uniphier-ld11 + - description: LD20 SoC boards + items: + - enum: + - socionext,uniphier-ld20-akebi96 + - socionext,uniphier-ld20-global + - socionext,uniphier-ld20-ref + - const: socionext,uniphier-ld20 + - description: PXs3 SoC boards + items: + - enum: + - socionext,uniphier-pxs3-ref + - const: socionext,uniphier-pxs3 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt new file mode 100644 index 000000000..46652bf65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sp810.txt @@ -0,0 +1,46 @@ +SP810 System Controller +----------------------- + +Required properties: + +- compatible: standard compatible string for a Primecell peripheral, + see Documentation/devicetree/bindings/arm/primecell.yaml + for more details + should be: "arm,sp810", "arm,primecell" + +- reg: standard registers property, physical address and size + of the control registers + +- clock-names: from the common clock bindings, for more details see + Documentation/devicetree/bindings/clock/clock-bindings.txt; + should be: "refclk", "timclk", "apb_pclk" + +- clocks: from the common clock bindings, phandle and clock + specifier pairs for the entries of clock-names property + +- #clock-cells: from the common clock bindings; + should be: <1> + +- clock-output-names: from the common clock bindings; + should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" + +- assigned-clocks: from the common clock binding; + should be: clock specifier for each output clock of this + provider node + +- assigned-clock-parents: from the common clock binding; + should be: phandle of input clock listed in clocks + property with the highest frequency + +Example: + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + + }; diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt new file mode 100644 index 000000000..93372f2a7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -0,0 +1,20 @@ +* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU) + +ARMv8.2 introduces the optional Statistical Profiling Extension for collecting +performance sample data using an in-memory trace buffer. + +** SPE Required properties: + +- compatible : should be one of: + "arm,statistical-profiling-extension-v1" + +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where + SPE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + +** Example: + +spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>; +}; diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt new file mode 100644 index 000000000..e404e2556 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spear-misc.txt @@ -0,0 +1,9 @@ +SPEAr Misc configuration +=========================== +SPEAr SOCs have some miscellaneous registers which are used to configure +few properties of different peripheral controllers. + +misc node required properties: + +- compatible Should be "st,spear1340-misc", "syscon". +- reg: Address range of misc space up to 8K diff --git a/Documentation/devicetree/bindings/arm/spear.yaml b/Documentation/devicetree/bindings/arm/spear.yaml new file mode 100644 index 000000000..605ad3f88 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spear.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/spear.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST SPEAr Platforms Device Tree Bindings + +maintainers: + - Viresh Kumar <vireshk@kernel.org> + - Stefan Roese <sr@denx.de> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - st,spear600 + - st,spear300 + - st,spear310 + - st,spear320 + - st,spear1310 + - st,spear1340 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml new file mode 100644 index 000000000..7b6ae3070 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc platforms device tree bindings + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sprd,sc9836-openphone + - const: sprd,sc9836 + - items: + - enum: + - sprd,sp9860g-1h10 + - const: sprd,sc9860 + - items: + - enum: + - sprd,sp9863a-1h10 + - const: sprd,sc9863a + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt new file mode 100644 index 000000000..2fdff5a80 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt @@ -0,0 +1,38 @@ +ST-Ericsson Nomadik Device Tree Bindings + +For various board the "board" node may contain specific properties +that pertain to this particular board, such as board-specific GPIOs. + +Required root node property: src +- Nomadik System and reset controller used for basic chip control, clock + and reset line control. +- compatible: must be "stericsson,nomadik,src" + +Boards with the Nomadik SoC include: + +Nomadik NHK-15 board manufactured by ST Microelectronics: + +Required root node property: + +compatible="st,nomadik-nhk-15"; + +S8815 "MiniKit" manufactured by Calao Systems: + +Required root node property: + +compatible="calaosystems,usb-s8815"; + +Required node: usb-s8815 + +Example: + +usb-s8815 { + ethernet-gpio { + gpios = <&gpio3 19 0x1>; + interrupts = <19 0x1>; + interrupt-parent = <&gpio3>; + }; + mmcsd-gpio { + gpios = <&gpio3 16 0x1>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt new file mode 100644 index 000000000..d11d80006 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ste-u300.txt @@ -0,0 +1,46 @@ +ST-Ericsson U300 Device Tree Bindings + +For various board the "board" node may contain specific properties +that pertain to this particular board, such as board-specific GPIOs +or board power regulator supplies. + +Required root node property: + +compatible="stericsson,u300"; + +Required node: syscon +This contains the system controller. +- compatible: must be "stericsson,u300-syscon". +- reg: the base address and size of the system controller. + +Boards with the U300 SoC include: + +S365 "Small Board U365": + +Required node: s365 +This contains the board-specific information. +- compatible: must be "stericsson,s365". +- vana15-supply: the regulator supplying the 1.5V to drive the + board. +- syscon: a pointer to the syscon node so we can access the + syscon registers to set the board as self-powered. + +Example: + +/ { + model = "ST-Ericsson U300"; + compatible = "stericsson,u300"; + #address-cells = <1>; + #size-cells = <1>; + + s365 { + compatible = "stericsson,s365"; + vana15-supply = <&ab3100_ldo_d_reg>; + syscon = <&syscon>; + }; + + syscon: syscon@c0011000 { + compatible = "stericsson,u300-syscon"; + reg = <0xc0011000 0x1000>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml new file mode 100644 index 000000000..b1f28d16d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST STi Platforms Device Tree Bindings + +maintainers: + - Patrice Chotard <patrice.chotard@st.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - st,stih415 + - st,stih416 + - st,stih407 + - st,stih410 + - st,stih418 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml new file mode 100644 index 000000000..8e711bd20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 ML-AHB interconnect bindings + +maintainers: + - Fabien Dessenne <fabien.dessenne@st.com> + - Arnaud Pouliquen <arnaud.pouliquen@st.com> + +description: | + These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects + a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory + parts can be accessed through different addresses (see "RAM aliases" in [1]) + using different buses (see [2]): balancing the Cortex-M firmware accesses + among those ports allows to tune the system performance. + [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf + [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + enum: + - st,mlahb + + dma-ranges: + description: | + Describe memory addresses translation between the local CPU and the + remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + maxItems: 3 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - '#address-cells' + - '#size-cells' + - dma-ranges + +unevaluatedProperties: false + +examples: + - | + mlahb: ahb@38000000 { + compatible = "st,mlahb", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x40000>; + ranges; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + reg = <0x10000000 0x40000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml new file mode 100644 index 000000000..6f1cd0103 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 Platforms System Controller bindings + +maintainers: + - Alexandre Torgue <alexandre.torgue@st.com> + - Christophe Roullier <christophe.roullier@st.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - st,stm32mp157-syscfg + - st,stm32mp151-pwr-mcu + - st,stm32-syscfg + - st,stm32-power-config + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg +then: + required: + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml new file mode 100644 index 000000000..009b424e4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/stm32/stm32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Platforms Device Tree Bindings + +maintainers: + - Alexandre Torgue <alexandre.torgue@st.com> + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - st,stm32f429i-disco + - st,stm32429i-eval + - const: st,stm32f429 + - items: + - enum: + - st,stm32f469i-disco + - const: st,stm32f469 + - items: + - enum: + - st,stm32f746-disco + - st,stm32746g-eval + - const: st,stm32f746 + - items: + - enum: + - st,stm32f769-disco + - const: st,stm32f769 + - items: + - enum: + - st,stm32h743i-disco + - st,stm32h743i-eval + - const: st,stm32h743 + - items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - lxa,stm32mp157c-mc1 + - shiratech,stm32mp157a-iot-box # IoT Box + - shiratech,stm32mp157a-stinger96 # Stinger96 + - st,stm32mp157c-ed1 + - st,stm32mp157a-dk1 + - st,stm32mp157c-dk2 + + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards + items: + - enum: + - seeed,stm32mp157c-odyssey + - const: seeed,stm32mp157c-odyssey-som + - const: st,stm32mp157 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml new file mode 100644 index 000000000..cab8e1b64 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -0,0 +1,897 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR X11) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner platforms device tree bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Allwinner A100 Perf1 Board + items: + - const: allwinner,a100-perf1 + - const: allwinner,sun50i-a100 + + - description: Allwinner A23 Evaluation Board + items: + - const: allwinner,sun8i-a23-evb + - const: allwinner,sun8i-a23 + + - description: Allwinner A31 APP4 Evaluation Board + items: + - const: allwinner,app4-evb1 + - const: allwinner,sun6i-a31 + + - description: Allwinner A83t Homlet Evaluation Board v2 + items: + - const: allwinner,h8homlet-v2 + - const: allwinner,sun8i-a83t + + - description: Allwinner GA10H Quad Core Tablet v1.1 + items: + - const: allwinner,ga10h-v1.1 + - const: allwinner,sun8i-a33 + + - description: Allwinner GT90H Tablet v4 + items: + - const: allwinner,gt90h-v4 + - const: allwinner,sun8i-a23 + + - description: Allwinner R16 EVB (Parrot) + items: + - const: allwinner,parrot + - const: allwinner,sun8i-a33 + + - description: Amarula A64 Relic + items: + - const: amarula,a64-relic + - const: allwinner,sun50i-a64 + + - description: Auxtek T003 A10s HDMI TV Stick + items: + - const: allwinner,auxtek-t003 + - const: allwinner,sun5i-a10s + + - description: Auxtek T004 A10s HDMI TV Stick + items: + - const: allwinner,auxtek-t004 + - const: allwinner,sun5i-a10s + + - description: BA10 TV Box + items: + - const: allwinner,ba10-tvbox + - const: allwinner,sun4i-a10 + + - description: BananaPi + items: + - const: lemaker,bananapi + - const: allwinner,sun7i-a20 + + - description: BananaPi M1 Plus + items: + - const: sinovoip,bpi-m1-plus + - const: allwinner,sun7i-a20 + + - description: BananaPi M2 + items: + - const: sinovoip,bpi-m2 + - const: allwinner,sun6i-a31s + + - description: BananaPi M2 Berry + items: + - const: sinovoip,bpi-m2-berry + - const: allwinner,sun8i-r40 + + - description: BananaPi M2 Plus + items: + - const: sinovoip,bpi-m2-plus + - const: allwinner,sun8i-h3 + + - description: BananaPi M2 Plus + items: + - const: sinovoip,bpi-m2-plus + - const: allwinner,sun50i-h5 + + - description: BananaPi M2 Plus v1.2 + items: + - const: bananapi,bpi-m2-plus-v1.2 + - const: allwinner,sun8i-h3 + + - description: BananaPi M2 Plus v1.2 + items: + - const: bananapi,bpi-m2-plus-v1.2 + - const: allwinner,sun50i-h5 + + - description: BananaPi M2 Magic + items: + - const: sinovoip,bananapi-m2m + - const: allwinner,sun8i-a33 + + - description: BananaPi M2 Ultra + items: + - const: sinovoip,bpi-m2-ultra + - const: allwinner,sun8i-r40 + + - description: BananaPi M2 Zero + items: + - const: sinovoip,bpi-m2-zero + - const: allwinner,sun8i-h2-plus + + - description: BananaPi M3 + items: + - const: sinovoip,bpi-m3 + - const: allwinner,sun8i-a83t + + - description: BananaPi M64 + items: + - const: sinovoip,bananapi-m64 + - const: allwinner,sun50i-a64 + + - description: BananaPro + items: + - const: lemaker,bananapro + - const: allwinner,sun7i-a20 + + - description: Beelink GS1 + items: + - const: azw,beelink-gs1 + - const: allwinner,sun50i-h6 + + - description: Beelink X2 + items: + - const: roofull,beelink-x2 + - const: allwinner,sun8i-h3 + + - description: Chuwi V7 CW0825 + items: + - const: chuwi,v7-cw0825 + - const: allwinner,sun4i-a10 + + - description: Colorfly E708 Q1 Tablet + items: + - const: colorfly,e708-q1 + - const: allwinner,sun6i-a31s + + - description: CSQ CS908 Set Top Box + items: + - const: csq,cs908 + - const: allwinner,sun6i-a31s + + - description: Cubietech Cubieboard + items: + - const: cubietech,a10-cubieboard + - const: allwinner,sun4i-a10 + + - description: Cubietech Cubieboard2 + items: + - const: cubietech,cubieboard2 + - const: allwinner,sun7i-a20 + + - description: Cubietech Cubieboard4 + items: + - const: cubietech,a80-cubieboard4 + - const: allwinner,sun9i-a80 + + - description: Cubietech Cubietruck + items: + - const: cubietech,cubietruck + - const: allwinner,sun7i-a20 + + - description: Cubietech Cubietruck Plus + items: + - const: cubietech,cubietruck-plus + - const: allwinner,sun8i-a83t + + - description: Difrnce DIT4350 + items: + - const: difrnce,dit4350 + - const: allwinner,sun5i-a13 + + - description: Dserve DSRV9703C + items: + - const: dserve,dsrv9703c + - const: allwinner,sun4i-a10 + + - description: Empire Electronix D709 Tablet + items: + - const: empire-electronix,d709 + - const: allwinner,sun5i-a13 + + - description: Empire Electronix M712 Tablet + items: + - const: empire-electronix,m712 + - const: allwinner,sun5i-a13 + + - description: FriendlyARM NanoPi A64 + items: + - const: friendlyarm,nanopi-a64 + - const: allwinner,sun50i-a64 + + - description: FriendlyARM NanoPi Duo2 + items: + - const: friendlyarm,nanopi-duo2 + - const: allwinner,sun8i-h3 + + - description: FriendlyARM NanoPi M1 + items: + - const: friendlyarm,nanopi-m1 + - const: allwinner,sun8i-h3 + + - description: FriendlyARM NanoPi M1 Plus + items: + - const: friendlyarm,nanopi-m1-plus + - const: allwinner,sun8i-h3 + + - description: FriendlyARM NanoPi Neo + items: + - const: friendlyarm,nanopi-neo + - const: allwinner,sun8i-h3 + + - description: FriendlyARM NanoPi Neo 2 + items: + - const: friendlyarm,nanopi-neo2 + - const: allwinner,sun50i-h5 + + - description: FriendlyARM NanoPi Neo Air + items: + - const: friendlyarm,nanopi-neo-air + - const: allwinner,sun8i-h3 + + - description: FriendlyARM NanoPi Neo Plus2 + items: + - const: friendlyarm,nanopi-neo-plus2 + - const: allwinner,sun50i-h5 + + - description: Gemei G9 Tablet + items: + - const: gemei,g9 + - const: allwinner,sun4i-a10 + + - description: Hyundai A7HD + items: + - const: hyundai,a7hd + - const: allwinner,sun4i-a10 + + - description: HSG H702 + items: + - const: hsg,h702 + - const: allwinner,sun5i-a13 + + - description: I12 TV Box + items: + - const: allwinner,i12-tvbox + - const: allwinner,sun7i-a20 + + - description: ICNova A20 SWAC + items: + - const: incircuit,icnova-a20-swac + - const: incircuit,icnova-a20 + - const: allwinner,sun7i-a20 + + - description: INet-1 + items: + - const: inet-tek,inet1 + - const: allwinner,sun4i-a10 + + - description: iNet-86DZ Rev 01 + items: + - const: primux,inet86dz + - const: allwinner,sun8i-a23 + + - description: iNet-9F Rev 03 + items: + - const: inet-tek,inet9f-rev03 + - const: allwinner,sun4i-a10 + + - description: iNet-97F Rev 02 + items: + - const: primux,inet97fv2 + - const: allwinner,sun4i-a10 + + - description: iNet-98V Rev 02 + items: + - const: primux,inet98v-rev2 + - const: allwinner,sun5i-a13 + + - description: iNet D978 Rev 02 Tablet + items: + - const: primux,inet-d978-rev2 + - const: allwinner,sun8i-a33 + + - description: iNet Q972 Tablet + items: + - const: inet-tek,inet-q972 + - const: allwinner,sun6i-a31s + + - description: Itead Ibox A20 + items: + - const: itead,itead-ibox-a20 + - const: allwinner,sun7i-a20 + + - description: Itead Iteaduino Plus A10 + items: + - const: itead,iteaduino-plus-a10 + - const: allwinner,sun4i-a10 + + - description: Jesurun Q5 + items: + - const: jesurun,q5 + - const: allwinner,sun4i-a10 + + - description: Lamobo R1 + items: + - const: lamobo,lamobo-r1 + - const: allwinner,sun7i-a20 + + - description: Libre Computer Board ALL-H3-CC H2+ + items: + - const: libretech,all-h3-cc-h2-plus + - const: allwinner,sun8i-h2-plus + + - description: Libre Computer Board ALL-H3-CC H3 + items: + - const: libretech,all-h3-cc-h3 + - const: allwinner,sun8i-h3 + + - description: Libre Computer Board ALL-H3-CC H5 + items: + - const: libretech,all-h3-cc-h5 + - const: allwinner,sun50i-h5 + + - description: Libre Computer Board ALL-H3-IT H5 + items: + - const: libretech,all-h3-it-h5 + - const: allwinner,sun50i-h5 + + - description: Libre Computer Board ALL-H5-CC H5 + items: + - const: libretech,all-h5-cc-h5 + - const: allwinner,sun50i-h5 + + - description: Lichee Pi One + items: + - const: licheepi,licheepi-one + - const: allwinner,sun5i-a13 + + - description: Lichee Pi Zero + items: + - const: licheepi,licheepi-zero + - const: allwinner,sun8i-v3s + + - description: Lichee Pi Zero (with Dock) + items: + - const: licheepi,licheepi-zero-dock + - const: licheepi,licheepi-zero + - const: allwinner,sun8i-v3s + + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: sochip,s3 + - const: allwinner,sun8i-v3 + + - description: Linksprite PCDuino + items: + - const: linksprite,a10-pcduino + - const: allwinner,sun4i-a10 + + - description: Linksprite PCDuino2 + items: + - const: linksprite,a10-pcduino2 + - const: allwinner,sun4i-a10 + + - description: Linksprite PCDuino3 + items: + - const: linksprite,pcduino3 + - const: allwinner,sun7i-a20 + + - description: Linksprite PCDuino3 Nano + items: + - const: linksprite,pcduino3-nano + - const: allwinner,sun7i-a20 + + - description: Linutronix Testbox v2 + items: + - const: linutronix,testbox-v2 + - const: lamobo,lamobo-r1 + - const: allwinner,sun7i-a20 + + - description: HAOYU Electronics Marsboard A10 + items: + - const: haoyu,a10-marsboard + - const: allwinner,sun4i-a10 + + - description: MapleBoard MP130 + items: + - const: mapleboard,mp130 + - const: allwinner,sun8i-h3 + + - description: Mele A1000 + items: + - const: mele,a1000 + - const: allwinner,sun4i-a10 + + - description: Mele A1000G Quad Set Top Box + items: + - const: mele,a1000g-quad + - const: allwinner,sun6i-a31 + + - description: Mele I7 Quad Set Top Box + items: + - const: mele,i7 + - const: allwinner,sun6i-a31 + + - description: Mele M3 + items: + - const: mele,m3 + - const: allwinner,sun7i-a20 + + - description: Mele M9 Set Top Box + items: + - const: mele,m9 + - const: allwinner,sun6i-a31 + + - description: Merrii A20 Hummingboard + items: + - const: merrii,a20-hummingbird + - const: allwinner,sun7i-a20 + + - description: Merrii A31 Hummingboard + items: + - const: merrii,a31-hummingbird + - const: allwinner,sun6i-a31 + + - description: Merrii A80 Optimus + items: + - const: merrii,a80-optimus + - const: allwinner,sun9i-a80 + + - description: Miniand Hackberry + items: + - const: miniand,hackberry + - const: allwinner,sun4i-a10 + + - description: MK802 + items: + - const: allwinner,mk802 + - const: allwinner,sun4i-a10 + + - description: MK802-A10s + items: + - const: allwinner,a10s-mk802 + - const: allwinner,sun5i-a10s + + - description: MK802-II + items: + - const: allwinner,mk802ii + - const: allwinner,sun4i-a10 + + - description: MK808c + items: + - const: allwinner,mk808c + - const: allwinner,sun7i-a20 + + - description: MSI Primo81 Tablet + items: + - const: msi,primo81 + - const: allwinner,sun6i-a31s + + - description: Emlid Neutis N5 Developper Board + items: + - const: emlid,neutis-n5-devboard + - const: emlid,neutis-n5 + - const: allwinner,sun50i-h5 + + - description: Emlid Neutis N5H3 Developper Board + items: + - const: emlid,neutis-n5h3-devboard + - const: emlid,neutis-n5h3 + - const: allwinner,sun8i-h3 + + - description: NextThing Co. CHIP + items: + - const: nextthing,chip + - const: allwinner,sun5i-r8 + - const: allwinner,sun5i-a13 + + - description: NextThing Co. CHIP Pro + items: + - const: nextthing,chip-pro + - const: nextthing,gr8 + + - description: NextThing Co. GR8 Evaluation Board + items: + - const: nextthing,gr8-evb + - const: nextthing,gr8 + + - description: Nintendo NES Classic + items: + - const: nintendo,nes-classic + - const: allwinner,sun8i-r16 + - const: allwinner,sun8i-a33 + + - description: Nintendo Super NES Classic + items: + - const: nintendo,super-nes-classic + - const: nintendo,nes-classic + - const: allwinner,sun8i-r16 + - const: allwinner,sun8i-a33 + + - description: Oceanic 5inMFD (5205) + items: + - const: oceanic,5205-5inmfd + - const: allwinner,sun50i-a64 + + - description: Olimex A10-OlinuXino LIME + items: + - const: olimex,a10-olinuxino-lime + - const: allwinner,sun4i-a10 + + - description: Olimex A10s-OlinuXino Micro + items: + - const: olimex,a10s-olinuxino-micro + - const: allwinner,sun5i-a10s + + - description: Olimex A13-OlinuXino + items: + - const: olimex,a13-olinuxino + - const: allwinner,sun5i-a13 + + - description: Olimex A13-OlinuXino Micro + items: + - const: olimex,a13-olinuxino-micro + - const: allwinner,sun5i-a13 + + - description: Olimex A20-Olimex SOM Evaluation Board + items: + - const: olimex,a20-olimex-som-evb + - const: allwinner,sun7i-a20 + + - description: Olimex A20-Olimex SOM Evaluation Board (with eMMC) + items: + - const: olimex,a20-olimex-som-evb-emmc + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino LIME + items: + - const: olimex,a20-olinuxino-lime + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino LIME (with eMMC) + items: + - const: olimex,a20-olinuxino-lime-emmc + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino LIME2 + items: + - const: olimex,a20-olinuxino-lime2 + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino LIME2 (with eMMC) + items: + - const: olimex,a20-olinuxino-lime2-emmc + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino Micro + items: + - const: olimex,a20-olinuxino-micro + - const: allwinner,sun7i-a20 + + - description: Olimex A20-OlinuXino Micro (with eMMC) + items: + - const: olimex,a20-olinuxino-micro-emmc + - const: allwinner,sun7i-a20 + + - description: Olimex A20-SOM204 Evaluation Board + items: + - const: olimex,a20-olimex-som204-evb + - const: allwinner,sun7i-a20 + + - description: Olimex A20-SOM204 Evaluation Board (with eMMC) + items: + - const: olimex,a20-olimex-som204-evb-emmc + - const: allwinner,sun7i-a20 + + - description: Olimex A33-OlinuXino + items: + - const: olimex,a33-olinuxino + - const: allwinner,sun8i-a33 + + - description: Olimex A64-OlinuXino + items: + - const: olimex,a64-olinuxino + - const: allwinner,sun50i-a64 + + - description: Olimex A64-OlinuXino (with eMMC) + items: + - const: olimex,a64-olinuxino-emmc + - const: allwinner,sun50i-a64 + + - description: Olimex A64 Teres-I + items: + - const: olimex,a64-teres-i + - const: allwinner,sun50i-a64 + + - description: Pine64 + items: + - const: pine64,pine64 + - const: allwinner,sun50i-a64 + + - description: Pine64+ + items: + - const: pine64,pine64-plus + - const: allwinner,sun50i-a64 + + - description: Pine64 PineCube + items: + - const: pine64,pinecube + - const: allwinner,sun8i-s3 + + - description: Pine64 PineH64 model A + items: + - const: pine64,pine-h64 + - const: allwinner,sun50i-h6 + + - description: Pine64 PineH64 model B + items: + - const: pine64,pine-h64-model-b + - const: allwinner,sun50i-h6 + + - description: Pine64 LTS + items: + - const: pine64,pine64-lts + - const: allwinner,sun50i-r18 + - const: allwinner,sun50i-a64 + + - description: Pine64 Pinebook + items: + - const: pine64,pinebook + - const: allwinner,sun50i-a64 + + - description: Pine64 PinePhone Developer Batch (1.0) + items: + - const: pine64,pinephone-1.0 + - const: allwinner,sun50i-a64 + + - description: Pine64 PinePhone Braveheart (1.1) + items: + - const: pine64,pinephone-1.1 + - const: allwinner,sun50i-a64 + + - description: Pine64 PinePhone (1.2) + items: + - const: pine64,pinephone-1.2 + - const: allwinner,sun50i-a64 + + - description: Pine64 PineTab + items: + - const: pine64,pinetab + - const: allwinner,sun50i-a64 + + - description: Pine64 SoPine Baseboard + items: + - const: pine64,sopine-baseboard + - const: pine64,sopine + - const: allwinner,sun50i-a64 + + - description: PineRiver Mini X-Plus + items: + - const: pineriver,mini-xplus + - const: allwinner,sun4i-a10 + + - description: PocketBook Touch Lux 3 + items: + - const: pocketbook,touch-lux-3 + - const: allwinner,sun5i-a13 + + - description: Point of View Protab2-IPS9 + items: + - const: pov,protab2-ips9 + - const: allwinner,sun4i-a10 + + - description: Polaroid MID2407PXE03 Tablet + items: + - const: polaroid,mid2407pxe03 + - const: allwinner,sun8i-a23 + + - description: Polaroid MID2809PXE04 Tablet + items: + - const: polaroid,mid2809pxe04 + - const: allwinner,sun8i-a23 + + - description: Q8 A13 Tablet + items: + - const: allwinner,q8-a13 + - const: allwinner,sun5i-a13 + + - description: Q8 A23 Tablet + items: + - const: allwinner,q8-a23 + - const: allwinner,sun8i-a23 + + - description: Q8 A33 Tablet + items: + - const: allwinner,q8-a33 + - const: allwinner,sun8i-a33 + + - description: Qihua CQA3T BV3 + items: + - const: qihua,t3-cqa3t-bv3 + - const: allwinner,sun8i-t3 + - const: allwinner,sun8i-r40 + + - description: R7 A10s HDMI TV Stick + items: + - const: allwinner,r7-tv-dongle + - const: allwinner,sun5i-a10s + + - description: RerVision H3-DVK + items: + - const: rervision,h3-dvk + - const: allwinner,sun8i-h3 + + - description: Sinlinx SinA31s Core Board + items: + - const: sinlinx,sina31s + - const: allwinner,sun6i-a31s + + - description: Sinlinx SinA31s Development Board + items: + - const: sinlinx,sina31s-sdk + - const: allwinner,sun6i-a31s + + - description: Sinlinx SinA33 + items: + - const: sinlinx,sina33 + - const: allwinner,sun8i-a33 + + - description: Tanix TX6 + items: + - const: oranth,tanix-tx6 + - const: allwinner,sun50i-h6 + + - description: TBS A711 Tablet + items: + - const: tbs-biometrics,a711 + - const: allwinner,sun8i-a83t + + - description: Utoo P66 + items: + - const: utoo,p66 + - const: allwinner,sun5i-a13 + + - description: Wexler TAB7200 + items: + - const: wexler,tab7200 + - const: allwinner,sun7i-a20 + + - description: WITS A31 Colombus Evaluation Board + items: + - const: wits,colombus + - const: allwinner,sun6i-a31 + + - description: WITS Pro A20 DKT + items: + - const: wits,pro-a20-dkt + - const: allwinner,sun7i-a20 + + - description: Wobo i5 + items: + - const: wobo,a10s-wobo-i5 + - const: allwinner,sun5i-a10s + + - description: Yones TopTech BS1078 v2 Tablet + items: + - const: yones-toptech,bs1078-v2 + - const: allwinner,sun6i-a31s + + - description: Xunlong OrangePi + items: + - const: xunlong,orangepi + - const: allwinner,sun7i-a20 + + - description: Xunlong OrangePi 2 + items: + - const: xunlong,orangepi-2 + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi 3 + items: + - const: xunlong,orangepi-3 + - const: allwinner,sun50i-h6 + + - description: Xunlong OrangePi Lite + items: + - const: xunlong,orangepi-lite + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi Lite2 + items: + - const: xunlong,orangepi-lite2 + - const: allwinner,sun50i-h6 + + - description: Xunlong OrangePi Mini + items: + - const: xunlong,orangepi-mini + - const: allwinner,sun7i-a20 + + - description: Xunlong OrangePi One + items: + - const: xunlong,orangepi-one + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi One Plus + items: + - const: xunlong,orangepi-one-plus + - const: allwinner,sun50i-h6 + + - description: Xunlong OrangePi PC + items: + - const: xunlong,orangepi-pc + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi PC 2 + items: + - const: xunlong,orangepi-pc2 + - const: allwinner,sun50i-h5 + + - description: Xunlong OrangePi PC Plus + items: + - const: xunlong,orangepi-pc-plus + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi Plus + items: + - const: xunlong,orangepi-plus + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi Plus 2E + items: + - const: xunlong,orangepi-plus2e + - const: allwinner,sun8i-h3 + + - description: Xunlong OrangePi Prime + items: + - const: xunlong,orangepi-prime + - const: allwinner,sun50i-h5 + + - description: Xunlong OrangePi R1 + items: + - const: xunlong,orangepi-r1 + - const: allwinner,sun8i-h2-plus + + - description: Xunlong OrangePi Win + items: + - const: xunlong,orangepi-win + - const: allwinner,sun50i-a64 + + - description: Xunlong OrangePi Zero + items: + - const: xunlong,orangepi-zero + - const: allwinner,sun8i-h2-plus + + - description: Xunlong OrangePi Zero Plus + items: + - const: xunlong,orangepi-zero-plus + - const: allwinner,sun50i-h5 + + - description: Xunlong OrangePi Zero Plus2 + items: + - const: xunlong,orangepi-zero-plus2 + - const: allwinner,sun50i-h5 + + - description: Xunlong OrangePi Zero Plus2 + items: + - const: xunlong,orangepi-zero-plus2-h3 + - const: allwinner,sun8i-h3 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml new file mode 100644 index 000000000..e713a6fe4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Memory Bus (MBUS) controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The MBUS controller drives the MBUS that other devices in the SoC + will use to perform DMA. It also has a register interface that + allows to monitor and control the bandwidth and priorities for + masters on that bus. + + Each device having to perform their DMA through the MBUS must have + the interconnects and interconnect-names properties set to the MBUS + controller and with "dma-mem" as the interconnect name. + +properties: + "#interconnect-cells": + const: 1 + description: + The content of the cell is the MBUS ID. + + compatible: + enum: + - allwinner,sun5i-a13-mbus + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + dma-ranges: + description: + See section 2.3.9 of the DeviceTree Specification. + + '#address-cells': true + + '#size-cells': true + +required: + - "#interconnect-cells" + - compatible + - reg + - clocks + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun5i-ccu.h> + + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/swir.txt b/Documentation/devicetree/bindings/arm/swir.txt new file mode 100644 index 000000000..042be73a9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/swir.txt @@ -0,0 +1,12 @@ +Sierra Wireless Modules device tree bindings +-------------------------------------------- + +Supported Modules : + - WP8548 : Includes MDM9615 and PM8018 in a module + +Sierra Wireless modules shall have the following properties : + Required root node property + - compatible: "swir,wp8548" for the WP8548 CF3 Module + +Board compatible values: + - "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt new file mode 100644 index 000000000..d8b48f2ed --- /dev/null +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -0,0 +1,105 @@ +Synaptics SoC Device Tree Bindings + +According to https://www.synaptics.com/company/news/conexant-marvell +Synaptics has acquired the Multimedia Solutions Business of Marvell, so +berlin SoCs are now Synaptics' SoCs now. + +--------------------------------------------------------------- + +Work in progress statement: + +Device tree files and bindings applying to Marvell Berlin SoCs and boards are +considered "unstable". Any Marvell Berlin device tree binding may change at any +time. Be sure to use a device tree binary and a kernel image generated from the +same source tree. + +Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a +stable binding/ABI. + +--------------------------------------------------------------- + +Boards with the Synaptics AS370 SoC shall have the following properties: + Required root node property: + compatible: "syna,as370" + +Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 +shall have the following properties: + +* Required root node properties: +compatible: must contain "marvell,berlin" + +In addition, the above compatible shall be extended with the specific +SoC and board used. Currently known SoC compatibles are: + "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), + "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) + "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) + "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) + +* Example: + +/ { + model = "Sony NSZ-GS7"; + compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; + + ... +} + +* Marvell Berlin CPU control bindings + +CPU control register allows various operations on CPUs, like resetting them +independently. + +Required properties: +- compatible: should be "marvell,berlin-cpu-ctrl" +- reg: address and length of the register set + +Example: + +cpu-ctrl@f7dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xf7dd0000 0x10000>; +}; + +* Marvell Berlin2 chip control binding + +Marvell Berlin SoCs have a chip control register set providing several +individual registers dealing with pinmux, padmux, clock, reset, and secondary +CPU boot address. Unfortunately, the individual registers are spread among the +chip control registers, so there should be a single DT node only providing the +different functions which are described below. + +Required properties: +- compatible: + * the first and second values must be: + "simple-mfd", "syscon" +- reg: address and length of following register sets for + BG2/BG2CD: chip control register set + BG2Q: chip control register set and cpu pll registers + +* Marvell Berlin2 system control binding + +Marvell Berlin SoCs have a system control register set providing several +individual registers dealing with pinmux, padmux, and reset. + +Required properties: +- compatible: + * the first and second values must be: + "simple-mfd", "syscon" +- reg: address and length of the system control register set + +Example: + +chip: chip-control@ea0000 { + compatible = "simple-mfd", "syscon"; + reg = <0xea0000 0x400>; + + /* sub-device nodes */ +}; + +sysctrl: system-controller@d000 { + compatible = "simple-mfd", "syscon"; + reg = <0xd000 0x100>; + + /* sub-device nodes */ +}; diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml new file mode 100644 index 000000000..2c6911c77 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra device tree bindings + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - compal,paz00 + - compulab,trimslice + - nvidia,harmony + - nvidia,seaboard + - nvidia,ventana + - const: nvidia,tegra20 + - items: + - enum: + - ad,medcom-wide + - ad,plutux + - ad,tec + - const: ad,tamonten + - const: nvidia,tegra20 + - items: + - enum: + - toradex,colibri_t20-eval-v3 + - toradex,colibri_t20-iris + - const: toradex,colibri_t20 + - const: nvidia,tegra20 + - items: + - const: acer,picasso + - const: nvidia,tegra20 + - items: + - enum: + - nvidia,beaver + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,cardhu-a02 + - nvidia,cardhu-a04 + - const: nvidia,cardhu + - const: nvidia,tegra30 + - items: + - const: toradex,apalis_t30-eval + - const: toradex,apalis_t30 + - const: nvidia,tegra30 + - items: + - const: toradex,apalis_t30-v1.1-eval + - const: toradex,apalis_t30-eval + - const: toradex,apalis_t30-v1.1 + - const: toradex,apalis_t30 + - const: nvidia,tegra30 + - items: + - enum: + - toradex,colibri_t30-eval-v3 + - const: toradex,colibri_t30 + - const: nvidia,tegra30 + - items: + - const: asus,grouper + - const: nvidia,tegra30 + - items: + - const: asus,tilapia + - const: asus,grouper + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,dalmore + - nvidia,roth + - nvidia,tn7 + - const: nvidia,tegra114 + - items: + - enum: + - nvidia,jetson-tk1 + - nvidia,venice2 + - const: nvidia,tegra124 + - items: + - const: toradex,apalis-tk1-eval + - const: toradex,apalis-tk1 + - const: nvidia,tegra124 + - items: + - const: toradex,apalis-tk1-v1.2-eval + - const: toradex,apalis-tk1-eval + - const: toradex,apalis-tk1-v1.2 + - const: toradex,apalis-tk1 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,norrin + - const: nvidia,tegra132 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,darcy + - nvidia,p2371-0000 + - nvidia,p2371-2180 + - nvidia,p2571 + - nvidia,p2894-0050-a08 + - const: nvidia,tegra210 + - items: + - enum: + - nvidia,p2771-0000 + - const: nvidia,tegra186 + - items: + - enum: + - nvidia,p2972-0000 + - const: nvidia,tegra194 + - description: Jetson Xavier NX + items: + - const: nvidia,p3668-0000 + - const: nvidia,tegra194 + - description: Jetson Xavier NX Developer Kit + items: + - const: nvidia,p3509-0000+p3668-0000 + - const: nvidia,tegra194 + - items: + - enum: + - nvidia,tegra234-vdk + - const: nvidia,tegra234 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt new file mode 100644 index 000000000..5ae601e7f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt @@ -0,0 +1,21 @@ +NVIDIA compliant embedded controller + +Required properties: +- compatible : should be "nvidia,nvec". +- reg : the iomem of the i2c slave controller +- interrupts : the interrupt line of the i2c slave controller +- clock-frequency : the frequency of the i2c bus +- gpios : the gpio used for ec request +- slave-addr: the i2c address of the slave controller +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + Tegra20/Tegra30: + - div-clk + - fast-clk + Tegra114: + - div-clk +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - i2c diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt new file mode 100644 index 000000000..576462fae --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -0,0 +1,133 @@ +NVIDIA Tegra Power Management Controller (PMC) + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-pmc": for Tegra186 + - "nvidia,tegra194-pmc": for Tegra194 + - "nvidia,tegra234-pmc": for Tegra234 +- reg: Must contain an (offset, length) pair of the register set for each + entry in reg-names. +- reg-names: Must include the following entries: + - "pmc" + - "wake" + - "aotag" + - "scratch" + - "misc" (Only for Tegra194 and later) + +Optional properties: +- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Example: + +SoC DTSI: + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0 0x0c360000 0 0x10000>, + <0 0x0c370000 0 0x10000>, + <0 0x0c380000 0 0x10000>, + <0 0x0c390000 0 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + }; + +Board DTS: + + pmc@c360000 { + nvidia,invert-interrupt; + }; + +== Pad Control == + +On Tegra SoCs a pad is a set of pins which are configured as a group. +The pin grouping is a fixed attribute of the hardware. The PMC can be +used to set pad power state and signaling voltage. A pad can be either +in active or power down mode. The support for power state and signaling +voltage configuration varies depending on the pad in question. 3.3 V and +1.8 V signaling voltages are supported on pins where software +controllable signaling voltage switching is available. + +Pad configurations are described with pin configuration nodes which +are placed under the pmc node and they are referred to by the pinctrl +client properties. For more information see +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. + +The following pads are present on Tegra186: +csia csib dsi mipi-bias +pex-clk-bias pex-clk3 pex-clk2 pex-clk1 +usb0 usb1 usb2 usb-bias +uart audio hsic dbg +hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv +sdmmc4 cam dsib dsic +dsid csic csid csie +dsif spi ufs dmic-hv +edp sdmmc1-hv sdmmc3-hv conn +audio-hv ao-hv + +Required pin configuration properties: + - pins: A list of strings, each of which contains the name of a pad + to be configured. + +Optional pin configuration properties: + - low-power-enable: Configure the pad into power down mode + - low-power-disable: Configure the pad into active mode + - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. + The values are defined in + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. + +Note: The power state can be configured on all of the above pads except + for ao-hv. Following pads have software configurable signaling + voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, + ao-hv. + +Pad configuration state example: + pmc: pmc@7000e400 { + compatible = "nvidia,tegra186-pmc"; + reg = <0 0x0c360000 0 0x10000>, + <0 0x0c370000 0 0x10000>, + <0 0x0c380000 0 0x10000>, + <0 0x0c390000 0 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + + ... + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + hdmi_off: hdmi-off { + pins = "hdmi"; + low-power-enable; + } + + hdmi_on: hdmi-on { + pins = "hdmi"; + low-power-disable; + } + }; + +Pinctrl client example: + sdmmc1: sdhci@3400000 { + ... + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; + + ... + + sor0: sor@15540000 { + ... + pinctrl-0 = <&hdmi_off>; + pinctrl-1 = <&hdmi_on>; + pinctrl-names = "hdmi-on", "hdmi-off"; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt new file mode 100644 index 000000000..9a4295b54 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt @@ -0,0 +1,17 @@ +NVIDIA Tegra AHB + +Required properties: +- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For + Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain + '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124, + tegra132, or tegra210. +- reg : Should contain 1 register ranges(address and length). For + Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004 + 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should + be be <0x6000c000 0x150>. + +Example (for a Tegra20 chip): + ahb: ahb@6000c004 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt new file mode 100644 index 000000000..a855c1bff --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt @@ -0,0 +1,18 @@ +NVIDIA Tegra Flow Controller + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra20-flowctrl": for Tegra20 + - "nvidia,tegra30-flowctrl": for Tegra30 + - "nvidia,tegra114-flowctrl": for Tegra114 + - "nvidia,tegra124-flowctrl": for Tegra124 + - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132 + - "nvidia,tegra210-flowctrl": for Tegra210 +- reg: Should contain one register range (address and length) + +Example: + + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml new file mode 100644 index 000000000..43fd2f892 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -0,0 +1,355 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra20-pmc + - nvidia,tegra20-pmc + - nvidia,tegra30-pmc + - nvidia,tegra114-pmc + - nvidia,tegra124-pmc + - nvidia,tegra210-pmc + + reg: + maxItems: 1 + description: + Offset and length of the register set for the device. + + clock-names: + items: + - const: pclk + - const: clk32k_in + description: + Must includes entries pclk and clk32k_in. + pclk is the Tegra clock of that name and clk32k_in is 32KHz clock + input to Tegra. + + clocks: + maxItems: 2 + description: + Must contain an entry for each entry in clock-names. + See ../clocks/clocks-bindings.txt for details. + + '#clock-cells': + const: 1 + description: + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. + PMC also has blink control which allows 32Khz clock output to + Tegra blink pad. + Consumer of PMC clock should specify the desired clock by having + the clock ID in its "clocks" phandle cell with pmc clock provider. + See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC + clock IDs. + + '#interrupt-cells': + const: 2 + description: + Specifies number of cells needed to encode an interrupt source. + The value must be 2. + + interrupt-controller: true + + nvidia,invert-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Inverts the PMU interrupt signal. + The PMU is an external Power Management Unit, whose interrupt output + signal is fed into the PMC. This signal is optionally inverted, and + then fed into the ARM GIC. The PMC is not involved in the detection + or handling of this interrupt signal, merely its inversion. + + nvidia,core-power-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: Core power request active-high. + + nvidia,sys-clock-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: System clock request active-high. + + nvidia,combined-power-req: + $ref: /schemas/types.yaml#/definitions/flag + description: combined power request for CPU and Core. + + nvidia,cpu-pwr-good-en: + $ref: /schemas/types.yaml#/definitions/flag + description: + CPU power good signal from external PMIC to PMC is enabled. + + nvidia,suspend-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + The suspend mode that the platform should use. + Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh + Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh + Mode 2 is for LP2, CPU voltage off + + nvidia,cpu-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power good time in uSec. + + nvidia,cpu-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power off time in uSec. + + nvidia,core-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <Oscillator-stable-time Power-stable-time> + Core power good time in uSec. + + nvidia,core-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Core power off time in uSec. + + nvidia,lp0-vec: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <start length> Starting address and length of LP0 vector. + The LP0 vector contains the warm boot code that is executed + by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and + always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed + from the deep sleep mode, the warm boot code will restore + some PLLs, clocks and then brings up CPU0 for resuming the + system. + + i2c-thermtrip: + type: object + description: + On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, + hardware-triggered thermal reset will be enabled. + + properties: + nvidia,i2c-controller-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 + "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference + Manual. + + nvidia,bus-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus address of the PMU on the I2C bus. + + nvidia,reg-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PMU I2C register address to issue poweroff command. + + nvidia,reg-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Poweroff command to write to PMU. + + nvidia,pinmux-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pinmux used by the hardware when issuing Poweroff command. + Defaults to 0. Valid values are described in section 12.5.2 + "Pinmux Support" of the Tegra4 Technical Reference Manual. + + required: + - nvidia,i2c-controller-id + - nvidia,bus-addr + - nvidia,reg-addr + - nvidia,reg-data + + additionalProperties: false + + powergates: + type: object + description: | + This node contains a hierarchy of power domain nodes, which should + match the powergates on the Tegra SoC. Each powergate node + represents a power-domain on the Tegra SoC that can be power-gated + by the Tegra PMC. + Hardware blocks belonging to a power domain should contain + "power-domains" property that is a phandle pointing to corresponding + powergate node. + The name of the powergate node should be one of the below. Note that + not every powergate is applicable to all Tegra devices and the following + list shows which powergates are applicable to which devices. + Please refer to Tegra TRM for mode details on the powergate nodes to + use for each power-gate block inside Tegra. + Name Description Devices Applicable + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 + + patternProperties: + "^[a-z0-9]+$": + type: object + + patternProperties: + clocks: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each clock required by the PMC + for controlling a power-gate. + See ../clocks/clock-bindings.txt document for more details. + + resets: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each reset required by the PMC + for controlling a power-gate. + See ../reset/reset.txt for more details. + + '#power-domain-cells': + const: 0 + description: Must be 0. + + required: + - clocks + - resets + - '#power-domain-cells' + + additionalProperties: false + +patternProperties: + "^[a-f0-9]+-[a-f0-9]+$": + type: object + description: + This is a Pad configuration node. On Tegra SOCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power state + and signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages + are supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and they + are referred to by the pinctrl client properties. For more information + see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132 + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, + hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. + + The following pads are present on Tegra210 + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, + hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. + The values are defined in + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. + Power state can be configured on all Tegra124 and Tegra132 + pads. None of the Tegra124 or Tegra132 pads support signaling + voltage switching. + All of the listed Tegra210 pads except pex-cntrl support power + state configuration. Signaling voltage switching is supported + on below Tegra210 pads. + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, and uart. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - clock-names + - clocks + - '#clock-cells' + +additionalProperties: false + +dependencies: + "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] + "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] + "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] + +examples: + - | + + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> + #include <dt-bindings/soc/tegra-pmc.h> + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt new file mode 100644 index 000000000..ea670a5d7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra Activity Monitor + +The activity monitor block collects statistics about the behaviour of other +components in the system. This information can be used to derive the rate at +which the external memory needs to be clocked in order to serve all requests +from the monitored clients. + +Required properties: +- compatible: should be "nvidia,tegra<chip>-actmon" +- reg: offset and length of the register set for the device +- interrupts: standard interrupt property +- clocks: Must contain a phandle and clock specifier pair for each entry in +clock-names. See ../../clock/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - actmon + - emc +- resets: Must contain an entry for each entry in reset-names. See +../../reset/reset.txt for details. +- reset-names: Must include the following entries: + - actmon + +Example: + actmon@6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + }; diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml new file mode 100644 index 000000000..c6e1c1e63 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/k3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 Multicore SoC architecture device tree bindings + +maintainers: + - Nishanth Menon <nm@ti.com> + +description: | + Platforms based on Texas Instruments K3 Multicore SoC architecture + shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: K3 AM654 SoC + items: + - enum: + - ti,am654-evm + - const: ti,am654 + + - description: K3 J721E SoC + items: + - const: ti,j721e + + - description: K3 J7200 SoC + items: + - const: ti,j7200 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ti/nspire.yaml b/Documentation/devicetree/bindings/arm/ti/nspire.yaml new file mode 100644 index 000000000..cc2023bb7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/nspire.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/nspire.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE calculators + +maintainers: + - Daniel Tang <dt.tangr@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + # CX models + - ti,nspire-cx + # Touchpad models + - ti,nspire-tp + # Clickpad models + - ti,nspire-clp + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml b/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml new file mode 100644 index 000000000..c022d325f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/ti,davinci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DaVinci Platforms Device Tree Bindings + +maintainers: + - Sekhar Nori <nsekhar@ti.com> + +description: + DA850/OMAP-L138/AM18x based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - ti,da850-evm # DA850/OMAP-L138/AM18x Evaluation Module (EVM) board + - ti,da850-lcdk # DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board + - enbw,cmc # EnBW AM1808 based CMC board + - lego,ev3 # LEGO MINDSTORMS EV3 (AM1808 based) + - const: ti,da850 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml new file mode 100644 index 000000000..001bbbcd1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/toshiba.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti Platform Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Visconti5 TMPV7708 + items: + - enum: + - toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board + - const: toshiba,tmpv7708 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml new file mode 100644 index 000000000..5db7cfba8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ux500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ux500 platforms device tree bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: ST-Ericsson HREF (pre-v60) + items: + - const: st-ericsson,mop500 + - const: st-ericsson,u8500 + + - description: ST-Ericsson HREF (v60+) + items: + - const: st-ericsson,hrefv60+ + - const: st-ericsson,u8500 + + - description: Calao Systems Snowball + items: + - const: calaosystems,snowball-a9500 + - const: st-ericsson,u9500 + + - description: Samsung Galaxy S III mini (GT-I8190) + items: + - const: samsung,golden + - const: st-ericsson,u8500 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt new file mode 100644 index 000000000..89408de55 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt @@ -0,0 +1,83 @@ +ST-Ericsson Ux500 boards +------------------------ + +Required properties (in root node) one of these: + compatible = "st-ericsson,mop500" (legacy) + compatible = "st-ericsson,u8500" + +Required node (under root node): + +soc: represents the system-on-chip and contains the chip +peripherals + +Required property of soc node, one of these: + compatible = "stericsson,db8500" + +Required subnodes under soc node: + +backupram: (used for CPU spin tables and for storing data +during retention, system won't boot without this): + compatible = "ste,dbx500-backupram" + +scu: + see binding for arm/scu.txt + +interrupt-controller: + see binding for interrupt-controller/arm,gic.txt + +timer: + see binding for timer/arm,twd.txt + +clocks: + see binding for clocks/ux500.txt + +Example: + +/dts-v1/; + +/ { + model = "ST-Ericsson HREF (pre-v60) and ST UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ + clocks = <&smp_twd_clk>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/ux500/power_domain.txt b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt new file mode 100644 index 000000000..5679d1742 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt @@ -0,0 +1,35 @@ +* ST-Ericsson UX500 PM Domains + +UX500 supports multiple PM domains which are used to gate power to one or +more peripherals on the SOC. + +The implementation of PM domains for UX500 are based upon the generic PM domain +and use the corresponding DT bindings. + +==PM domain providers== + +Required properties: + - compatible: Must be "stericsson,ux500-pm-domains". + - #power-domain-cells : Number of cells in a power domain specifier, must be 1. + +Example: + pm_domains: pm_domains0 { + compatible = "stericsson,ux500-pm-domains"; + #power-domain-cells = <1>; + }; + +==PM domain consumers== + +Required properties: + - power-domains: A phandle and PM domain specifier. Below are the list of + valid specifiers: + + Index Specifier + ----- --------- + 0 DOMAIN_VAPE + +Example: + sdi0_per1@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + power-domains = <&pm_domains DOMAIN_VAPE> + }; diff --git a/Documentation/devicetree/bindings/arm/versatile-sysreg.txt b/Documentation/devicetree/bindings/arm/versatile-sysreg.txt new file mode 100644 index 000000000..a4f15262d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/versatile-sysreg.txt @@ -0,0 +1,10 @@ +ARM Versatile system registers +-------------------------------------- + +This is a system control registers block, providing multiple low level +platform functions like board detection and identification, software +interrupt generation, MMC and NOR Flash control etc. + +Required node properties: +- compatible value : = "arm,versatile-sysreg", "syscon" +- reg : physical base address and the size of the registers window diff --git a/Documentation/devicetree/bindings/arm/vexpress-scc.txt b/Documentation/devicetree/bindings/arm/vexpress-scc.txt new file mode 100644 index 000000000..ae5043e42 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vexpress-scc.txt @@ -0,0 +1,33 @@ +ARM Versatile Express Serial Configuration Controller +----------------------------------------------------- + +Test chips for ARM Versatile Express platform implement SCC (Serial +Configuration Controller) interface, used to set initial conditions +for the test chip. + +In some cases its registers are also mapped in normal address space +and can be used to obtain runtime information about the chip internals +(like silicon temperature sensors) and as interface to other subsystems +like platform configuration control and power management. + +Required properties: + +- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc"; + where <model> is the full tile model name (as used + in the tile's Technical Reference Manual), + eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7): + compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + +Optional properties: + +- reg: when the SCC is memory mapped, physical address and size of the + registers window +- interrupts: when the SCC can generate a system-level interrupt + +Example: + + scc@7fff0000 { + compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + reg = <0 0x7fff0000 0 0x1000>; + interrupts = <0 95 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt new file mode 100644 index 000000000..50095802f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt @@ -0,0 +1,103 @@ +ARM Versatile Express system registers +-------------------------------------- + +This is a system control registers block, providing multiple low level +platform functions like board detection and identification, software +interrupt generation, MMC and NOR Flash control etc. + +Required node properties: +- compatible value : = "arm,vexpress,sysreg"; +- reg : physical base address and the size of the registers window + +Deprecated properties, replaced by GPIO subnodes (see below): +- gpio-controller : specifies that the node is a GPIO controller +- #gpio-cells : size of the GPIO specifier, should be 2: + - first cell is the pseudo-GPIO line number: + 0 - MMC CARDIN + 1 - MMC WPROT + 2 - NOR FLASH WPn + - second cell can take standard GPIO flags (currently ignored). + +Control registers providing pseudo-GPIO lines must be represented +by subnodes, each of them requiring the following properties: +- compatible value : one of + "arm,vexpress-sysreg,sys_led" + "arm,vexpress-sysreg,sys_mci" + "arm,vexpress-sysreg,sys_flash" +- gpio-controller : makes the node a GPIO controller +- #gpio-cells : size of the GPIO specifier, must be 2: + - first cell is the function number: + - for sys_led : 0..7 = LED 0..7 + - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT + - for sys_flash : 0 = NOR FLASH WPn + - second cell can take standard GPIO flags (currently ignored). + +Example: + v2m_sysreg: sysreg@10000000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x10000000 0x1000>; + + v2m_led_gpios: sys_led@8 { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +This block also can also act a bridge to the platform's configuration +bus via "system control" interface, addressing devices with site number, +position in the board stack, config controller, function and device +numbers - see motherboard's TRM for more details. All configuration +controller accessible via this interface must reference the sysreg +node via "arm,vexpress,config-bridge" phandle and define appropriate +topology properties - see main vexpress node documentation for more +details. Each child of such node describes one function and must +define the following properties: +- compatible value : must be one of (corresponding to the TRM): + "arm,vexpress-amp" + "arm,vexpress-dvimode" + "arm,vexpress-energy" + "arm,vexpress-muxfpga" + "arm,vexpress-osc" + "arm,vexpress-power" + "arm,vexpress-reboot" + "arm,vexpress-reset" + "arm,vexpress-scc" + "arm,vexpress-shutdown" + "arm,vexpress-temp" + "arm,vexpress-volt" +- arm,vexpress-sysreg,func : must contain a set of two cells long groups: + - first cell of each group defines the function number + (eg. 1 for clock generator, 2 for voltage regulators etc.) + - second cell of each group defines device number (eg. osc 0, + osc 1 etc.) + - some functions (eg. energy meter, with its 64 bit long counter) + are using more than one function/device number pair + +Example: + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + }; + + energy@0 { + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>, <13 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml new file mode 100644 index 000000000..29ff39955 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/vt8500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings + +maintainers: + - Tony Prisk <linux@prisktech.co.nz> +description: test + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - via,vt8500 + - wm,wm8505 + - wm,wm8650 + - wm,wm8750 + - wm,wm8850 + +additionalProperties: true + diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt new file mode 100644 index 000000000..521b9c7de --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt @@ -0,0 +1,13 @@ +VIA/Wondermedia VT8500 Power Management Controller +----------------------------------------------------- + +Required properties: +- compatible : "via,vt8500-pmc" +- reg : Should contain 1 register ranges(address and length) + +Example: + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt new file mode 100644 index 000000000..db5c56db3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/xen.txt @@ -0,0 +1,60 @@ +* Xen hypervisor device tree bindings + +Xen ARM virtual platforms shall have a top-level "hypervisor" node with +the following properties: + +- compatible: + compatible = "xen,xen-<version>", "xen,xen"; + where <version> is the version of the Xen ABI of the platform. + +- reg: specifies the base physical address and size of a region in + memory where the grant table should be mapped to, using an + HYPERVISOR_memory_op hypercall. The memory region is large enough to map + the whole grant table (it is larger or equal to gnttab_max_grant_frames()). + This property is unnecessary when booting Dom0 using ACPI. + +- interrupts: the interrupt used by Xen to inject event notifications. + A GIC node is also required. + This property is unnecessary when booting Dom0 using ACPI. + +To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node +under /hypervisor with following parameters: + +________________________________________________________________________________ +Name | Size | Description +================================================================================ +xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System + | | Table. +-------------------------------------------------------------------------------- +xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory + | | map. +-------------------------------------------------------------------------------- +xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map + | | pointed to in previous entry. +-------------------------------------------------------------------------------- +xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI + | | memory map. +-------------------------------------------------------------------------------- +xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format. +-------------------------------------------------------------------------------- + +Example (assuming #address-cells = <2> and #size-cells = <2>): + +hypervisor { + compatible = "xen,xen-4.3", "xen,xen"; + reg = <0 0xb0000000 0 0x20000>; + interrupts = <1 15 0xf08>; + uefi { + xen,uefi-system-table = <0xXXXXXXXX>; + xen,uefi-mmap-start = <0xXXXXXXXX>; + xen,uefi-mmap-size = <0xXXXXXXXX>; + xen,uefi-mmap-desc-size = <0xXXXXXXXX>; + xen,uefi-mmap-desc-ver = <0xXXXXXXXX>; + }; +}; + +The format and meaning of the "xen,uefi-*" parameters are similar to those in +Documentation/arm/uefi.rst, which are provided by the regular UEFI stub. However +they differ because they are provided by the Xen hypervisor, together with a set +of UEFI runtime services implemented via hypercalls, see +http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html. diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml new file mode 100644 index 000000000..e0c6787f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/xilinx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Platforms Device Tree Bindings + +maintainers: + - Michal Simek <michal.simek@xilinx.com> + +description: | + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - adapteva,parallella + - digilent,zynq-zybo + - digilent,zynq-zybo-z7 + - xlnx,zynq-cc108 + - xlnx,zynq-zc702 + - xlnx,zynq-zc706 + - xlnx,zynq-zc770-xm010 + - xlnx,zynq-zc770-xm011 + - xlnx,zynq-zc770-xm012 + - xlnx,zynq-zc770-xm013 + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-microzed + - const: xlnx,zynq-microzed + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-zed + - const: xlnx,zynq-zed + - const: xlnx,zynq-7000 + + - items: + - enum: + - xlnx,zynqmp-zc1751 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1232 + items: + - const: xlnx,zynqmp-zc1232-revA + - const: xlnx,zynqmp-zc1232 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1254 + items: + - const: xlnx,zynqmp-zc1254-revA + - const: xlnx,zynqmp-zc1254 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1275 + items: + - const: xlnx,zynqmp-zc1275-revA + - const: xlnx,zynqmp-zc1275 + - const: xlnx,zynqmp + + - description: Xilinx 96boards compatible board zcu100 + items: + - const: xlnx,zynqmp-zcu100-revC + - const: xlnx,zynqmp-zcu100 + - const: xlnx,zynqmp + + - description: Xilinx 96boards compatible board Ultra96 + items: + - const: avnet,ultra96-rev1 + - const: avnet,ultra96 + - const: xlnx,zynqmp-zcu100-revC + - const: xlnx,zynqmp-zcu100 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu102 + items: + - enum: + - xlnx,zynqmp-zcu102-revA + - xlnx,zynqmp-zcu102-revB + - xlnx,zynqmp-zcu102-rev1.0 + - const: xlnx,zynqmp-zcu102 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu104 + items: + - enum: + - xlnx,zynqmp-zcu104-revA + - xlnx,zynqmp-zcu104-rev1.0 + - const: xlnx,zynqmp-zcu104 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu106 + items: + - enum: + - xlnx,zynqmp-zcu106-revA + - xlnx,zynqmp-zcu106-rev1.0 + - const: xlnx,zynqmp-zcu106 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu111 + items: + - enum: + - xlnx,zynqmp-zcu111-revA + - xlnx,zynqmp-zcu11-rev1.0 + - const: xlnx,zynqmp-zcu111 + - const: xlnx,zynqmp + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/zte,sysctrl.txt b/Documentation/devicetree/bindings/arm/zte,sysctrl.txt new file mode 100644 index 000000000..7e66b7f7b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte,sysctrl.txt @@ -0,0 +1,30 @@ +ZTE sysctrl Registers + +Registers for 'zte,zx296702' SoC: + +System management required properties: + - compatible = "zte,sysctrl" + +Low power management required properties: + - compatible = "zte,zx296702-pcu" + +Bus matrix required properties: + - compatible = "zte,zx-bus-matrix" + + +Registers for 'zte,zx296718' SoC: + +System management required properties: + - compatible = "zte,zx296718-aon-sysctrl" + - compatible = "zte,zx296718-sysctrl" + +Example: +aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; +}; + +sysctrl: sysctrl@1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000..672f8129c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE platforms device tree bindings + +maintainers: + - Jun Nie <jun.nie@linaro.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - zte,zx296702-ad1 + - const: zte,zx296702 + - items: + - enum: + - zte,zx296718-evb + - const: zte,zx296718 + +additionalProperties: true + +... |