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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
tree | a94efe259b9009378be6d90eb30d2b019d95c194 /Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml | |
parent | Initial commit. (diff) | |
download | linux-430c2fc249ea5c0536abd21c23382884005c9093.tar.xz linux-430c2fc249ea5c0536abd21c23382884005c9093.zip |
Adding upstream version 5.10.209.upstream/5.10.209upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml new file mode 100644 index 000000000..fe0ce191a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - ingenic,jz4740-nemc + - ingenic,jz4780-nemc + - items: + - const: ingenic,jz4725b-nemc + - const: ingenic,jz4740-nemc + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: true + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + ".*@[0-9]+$": + type: object + properties: + reg: + minItems: 1 + maxItems: 255 + + ingenic,nemc-bus-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + description: Specifies the bus width in bits. + + ingenic,nemc-tAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address setup time in nanoseconds. + + ingenic,nemc-tAH: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address hold time in nanoseconds. + + ingenic,nemc-tBP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Burst pitch time in nanoseconds. + + ingenic,nemc-tAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address wait time in nanoseconds. + + ingenic,nemc-tSTRV: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Static memory recovery time in nanoseconds. + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/jz4780-cgu.h> + #include <dt-bindings/gpio/gpio.h> + nemc: memory-controller@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000>, + <2 0 0x1a000000 0x1000000>, + <3 0 0x19000000 0x1000000>, + <4 0 0x18000000 0x1000000>, + <5 0 0x17000000 0x1000000>, + <6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + ethernet@6 { + compatible = "davicom,dm9000"; + davicom,no-eeprom; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc_cs6>; + + reg = <6 0 1>, /* addr */ + <6 2 1>; /* data */ + + ingenic,nemc-tAS = <15>; + ingenic,nemc-tAH = <10>; + ingenic,nemc-tBP = <20>; + ingenic,nemc-tAW = <50>; + ingenic,nemc-tSTRV = <100>; + + reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; + vcc-supply = <ð0_power>; + + interrupt-parent = <&gpe>; + interrupts = <19 4>; + }; + }; |