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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
tree | a94efe259b9009378be6d90eb30d2b019d95c194 /Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | |
parent | Initial commit. (diff) | |
download | linux-upstream/5.10.209.tar.xz linux-upstream/5.10.209.zip |
Adding upstream version 5.10.209.upstream/5.10.209upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml new file mode 100644 index 000000000..5444be766 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive L2 Cache Controller + +maintainers: + - Sagar Kadam <sagar.kadam@sifive.com> + - Yash Shah <yash.shah@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + The SiFive Level 2 Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Level 2 Cache Controller also + acts as directory-based coherency manager. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-ccache + + required: + - compatible + +properties: + compatible: + items: + - const: sifive,fu540-c000-ccache + - const: cache + + cache-block-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + const: 2097152 + + cache-unified: true + + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + minItems: 3 + maxItems: 3 + + reg: + maxItems: 1 + + next-level-cache: true + + memory-region: + description: | + The reference to the reserved-memory for the L2 Loosely Integrated Memory region. + The reserved memory node should be defined as per the bindings in reserved-memory.txt. + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + reg = <0x2010000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <1>, + <2>, + <3>; + next-level-cache = <&L25>; + memory-region = <&l2_lim>; + }; |