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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
| commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
| tree | a94efe259b9009378be6d90eb30d2b019d95c194 /arch/arm/mach-omap2/cm-regbits-24xx.h | |
| parent | Initial commit. (diff) | |
| download | linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.tar.xz linux-5d1646d90e1f2cceb9f0828f4b28318cd0ec7744.zip | |
Adding upstream version 5.10.209.upstream/5.10.209upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-24xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h new file mode 100644 index 000000000..59c14dbb6 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H + +/* + * OMAP24XX Clock Management register bits + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + */ + +#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) +#define OMAP24XX_EN_DSS1_MASK (1 << 0) +#define OMAP24XX_ST_MAILBOXES_SHIFT 30 +#define OMAP24XX_ST_HDQ_SHIFT 23 +#define OMAP2420_ST_I2C2_SHIFT 20 +#define OMAP2430_ST_I2CHS1_SHIFT 19 +#define OMAP2420_ST_I2C1_SHIFT 19 +#define OMAP2430_ST_I2CHS2_SHIFT 20 +#define OMAP24XX_ST_MCBSP2_SHIFT 16 +#define OMAP24XX_ST_MCBSP1_SHIFT 15 +#define OMAP2430_ST_MCBSP5_SHIFT 5 +#define OMAP2430_ST_MCBSP4_SHIFT 4 +#define OMAP2430_ST_MCBSP3_SHIFT 3 +#define OMAP24XX_ST_AES_SHIFT 3 +#define OMAP24XX_ST_RNG_SHIFT 2 +#define OMAP24XX_ST_SHA_SHIFT 1 +#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) +#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) +#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) +#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) +#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) +#define OMAP24XX_ST_MPU_WDT_SHIFT 3 +#define OMAP24XX_ST_32KSYNC_SHIFT 1 +#define OMAP24XX_EN_54M_PLL_SHIFT 6 +#define OMAP24XX_EN_96M_PLL_SHIFT 2 +#define OMAP24XX_ST_54M_APLL_SHIFT 9 +#define OMAP24XX_ST_96M_APLL_SHIFT 8 +#define OMAP24XX_AUTO_54M_MASK (0x3 << 6) +#define OMAP24XX_AUTO_96M_MASK (0x3 << 2) +#define OMAP24XX_AUTO_DPLL_SHIFT 0 +#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) +#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) +#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) +#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) +#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 +#endif |