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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 10:05:51 +0000 |
| commit | 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 (patch) | |
| tree | a94efe259b9009378be6d90eb30d2b019d95c194 /include/media/i2c | |
| parent | Initial commit. (diff) | |
| download | linux-upstream/5.10.209.tar.xz linux-upstream/5.10.209.zip | |
Adding upstream version 5.10.209.upstream/5.10.209upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
48 files changed, 2298 insertions, 0 deletions
diff --git a/include/media/i2c/ad9389b.h b/include/media/i2c/ad9389b.h new file mode 100644 index 000000000..30f9ea9a1 --- /dev/null +++ b/include/media/i2c/ad9389b.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Analog Devices AD9389B/AD9889B video encoder driver header + * + * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef AD9389B_H +#define AD9389B_H + +enum ad9389b_tmds_pll_gear { + AD9389B_TMDS_PLL_GEAR_AUTOMATIC, + AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC, +}; + +/* Platform dependent definitions */ +struct ad9389b_platform_data { + enum ad9389b_tmds_pll_gear tmds_pll_gear ; + /* Differential Data/Clock Output Drive Strength (reg. 0xa2/0xa3) */ + u8 diff_data_drive_strength; + u8 diff_clk_drive_strength; +}; + +/* notify events */ +#define AD9389B_MONITOR_DETECT 0 +#define AD9389B_EDID_DETECT 1 + +struct ad9389b_monitor_detect { + int present; +}; + +struct ad9389b_edid_detect { + int present; + int segment; +}; + +#endif diff --git a/include/media/i2c/adp1653.h b/include/media/i2c/adp1653.h new file mode 100644 index 000000000..096de9130 --- /dev/null +++ b/include/media/i2c/adp1653.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/media/i2c/adp1653.h + * + * Copyright (C) 2008--2011 Nokia Corporation + * + * Contact: Sakari Ailus <sakari.ailus@iki.fi> + * + * Contributors: + * Sakari Ailus <sakari.ailus@iki.fi> + * Tuukka Toivonen <tuukkat76@gmail.com> + */ + +#ifndef ADP1653_H +#define ADP1653_H + +#include <linux/i2c.h> +#include <linux/mutex.h> +#include <linux/videodev2.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-subdev.h> + +#define ADP1653_NAME "adp1653" +#define ADP1653_I2C_ADDR (0x60 >> 1) + +/* Register definitions */ +#define ADP1653_REG_OUT_SEL 0x00 +#define ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN 0x01 +#define ADP1653_REG_OUT_SEL_HPLED_TORCH_MAX 0x0b +#define ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN 0x0c +#define ADP1653_REG_OUT_SEL_HPLED_FLASH_MAX 0x1f +#define ADP1653_REG_OUT_SEL_HPLED_SHIFT 3 +#define ADP1653_REG_OUT_SEL_ILED_MAX 0x07 +#define ADP1653_REG_OUT_SEL_ILED_SHIFT 0 + +#define ADP1653_REG_CONFIG 0x01 +#define ADP1653_REG_CONFIG_TMR_CFG (1 << 4) +#define ADP1653_REG_CONFIG_TMR_SET_MAX 0x0f +#define ADP1653_REG_CONFIG_TMR_SET_SHIFT 0 + +#define ADP1653_REG_SW_STROBE 0x02 +#define ADP1653_REG_SW_STROBE_SW_STROBE (1 << 0) + +#define ADP1653_REG_FAULT 0x03 +#define ADP1653_REG_FAULT_FLT_SCP (1 << 3) +#define ADP1653_REG_FAULT_FLT_OT (1 << 2) +#define ADP1653_REG_FAULT_FLT_TMR (1 << 1) +#define ADP1653_REG_FAULT_FLT_OV (1 << 0) + +#define ADP1653_INDICATOR_INTENSITY_MIN 0 +#define ADP1653_INDICATOR_INTENSITY_STEP 2500 +#define ADP1653_INDICATOR_INTENSITY_MAX \ + (ADP1653_REG_OUT_SEL_ILED_MAX * ADP1653_INDICATOR_INTENSITY_STEP) +#define ADP1653_INDICATOR_INTENSITY_uA_TO_REG(a) \ + ((a) / ADP1653_INDICATOR_INTENSITY_STEP) +#define ADP1653_INDICATOR_INTENSITY_REG_TO_uA(a) \ + ((a) * ADP1653_INDICATOR_INTENSITY_STEP) + +#define ADP1653_FLASH_INTENSITY_BASE 35 +#define ADP1653_FLASH_INTENSITY_STEP 15 +#define ADP1653_FLASH_INTENSITY_MIN \ + (ADP1653_FLASH_INTENSITY_BASE \ + + ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN * ADP1653_FLASH_INTENSITY_STEP) +#define ADP1653_FLASH_INTENSITY_MAX \ + (ADP1653_FLASH_INTENSITY_MIN + \ + (ADP1653_REG_OUT_SEL_HPLED_FLASH_MAX - \ + ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN + 1) * \ + ADP1653_FLASH_INTENSITY_STEP) + +#define ADP1653_FLASH_INTENSITY_mA_TO_REG(a) \ + ((a) < ADP1653_FLASH_INTENSITY_BASE ? 0 : \ + (((a) - ADP1653_FLASH_INTENSITY_BASE) / ADP1653_FLASH_INTENSITY_STEP)) +#define ADP1653_FLASH_INTENSITY_REG_TO_mA(a) \ + ((a) * ADP1653_FLASH_INTENSITY_STEP + ADP1653_FLASH_INTENSITY_BASE) + +#define ADP1653_TORCH_INTENSITY_MIN \ + (ADP1653_FLASH_INTENSITY_BASE \ + + ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN * ADP1653_FLASH_INTENSITY_STEP) +#define ADP1653_TORCH_INTENSITY_MAX \ + (ADP1653_TORCH_INTENSITY_MIN + \ + (ADP1653_REG_OUT_SEL_HPLED_TORCH_MAX - \ + ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN + 1) * \ + ADP1653_FLASH_INTENSITY_STEP) + +struct adp1653_platform_data { + int (*power)(struct v4l2_subdev *sd, int on); + + u32 max_flash_timeout; /* flash light timeout in us */ + u32 max_flash_intensity; /* led intensity, flash mode, mA */ + u32 max_torch_intensity; /* led intensity, torch mode, mA */ + u32 max_indicator_intensity; /* indicator led intensity, uA */ + + struct gpio_desc *enable_gpio; /* for device-tree based boot */ +}; + +#define to_adp1653_flash(sd) container_of(sd, struct adp1653_flash, subdev) + +struct adp1653_flash { + struct v4l2_subdev subdev; + struct adp1653_platform_data *platform_data; + + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *led_mode; + struct v4l2_ctrl *flash_timeout; + struct v4l2_ctrl *flash_intensity; + struct v4l2_ctrl *torch_intensity; + struct v4l2_ctrl *indicator_intensity; + + struct mutex power_lock; + int power_count; + int fault; +}; + +#endif /* ADP1653_H */ diff --git a/include/media/i2c/adv7183.h b/include/media/i2c/adv7183.h new file mode 100644 index 000000000..49faece29 --- /dev/null +++ b/include/media/i2c/adv7183.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * adv7183.h - definition for adv7183 inputs and outputs + * + * Copyright (c) 2011 Analog Devices Inc. + */ + +#ifndef _ADV7183_H_ +#define _ADV7183_H_ + +/* ADV7183 HW inputs */ +#define ADV7183_COMPOSITE0 0 /* CVBS in on AIN1 */ +#define ADV7183_COMPOSITE1 1 /* CVBS in on AIN2 */ +#define ADV7183_COMPOSITE2 2 /* CVBS in on AIN3 */ +#define ADV7183_COMPOSITE3 3 /* CVBS in on AIN4 */ +#define ADV7183_COMPOSITE4 4 /* CVBS in on AIN5 */ +#define ADV7183_COMPOSITE5 5 /* CVBS in on AIN6 */ +#define ADV7183_COMPOSITE6 6 /* CVBS in on AIN7 */ +#define ADV7183_COMPOSITE7 7 /* CVBS in on AIN8 */ +#define ADV7183_COMPOSITE8 8 /* CVBS in on AIN9 */ +#define ADV7183_COMPOSITE9 9 /* CVBS in on AIN10 */ +#define ADV7183_COMPOSITE10 10 /* CVBS in on AIN11 */ + +#define ADV7183_SVIDEO0 11 /* Y on AIN1, C on AIN4 */ +#define ADV7183_SVIDEO1 12 /* Y on AIN2, C on AIN5 */ +#define ADV7183_SVIDEO2 13 /* Y on AIN3, C on AIN6 */ + +#define ADV7183_COMPONENT0 14 /* Y on AIN1, Pr on AIN4, Pb on AIN5 */ +#define ADV7183_COMPONENT1 15 /* Y on AIN2, Pr on AIN3, Pb on AIN6 */ + +/* ADV7183 HW outputs */ +#define ADV7183_8BIT_OUT 0 +#define ADV7183_16BIT_OUT 1 + +#endif diff --git a/include/media/i2c/adv7343.h b/include/media/i2c/adv7343.h new file mode 100644 index 000000000..e4142b1ef --- /dev/null +++ b/include/media/i2c/adv7343.h @@ -0,0 +1,63 @@ +/* + * ADV7343 header file + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ADV7343_H +#define ADV7343_H + +#define ADV7343_COMPOSITE_ID (0) +#define ADV7343_COMPONENT_ID (1) +#define ADV7343_SVIDEO_ID (2) + +/** + * adv7343_power_mode - power mode configuration. + * @sleep_mode: on enable the current consumption is reduced to micro ampere + * level. All DACs and the internal PLL circuit are disabled. + * Registers can be read from and written in sleep mode. + * @pll_control: PLL and oversampling control. This control allows internal + * PLL 1 circuit to be powered down and the oversampling to be + * switched off. + * @dac: array to configure power on/off DAC's 1..6 + * + * Power mode register (Register 0x0), for more info refer REGISTER MAP ACCESS + * section of datasheet[1], table 17 page no 30. + * + * [1] http://www.analog.com/static/imported-files/data_sheets/ADV7342_7343.pdf + */ +struct adv7343_power_mode { + bool sleep_mode; + bool pll_control; + u32 dac[6]; +}; + +/** + * struct adv7343_sd_config - SD Only Output Configuration. + * @sd_dac_out: array configuring SD DAC Outputs 1 and 2 + */ +struct adv7343_sd_config { + /* SD only Output Configuration */ + u32 sd_dac_out[2]; +}; + +/** + * struct adv7343_platform_data - Platform data values and access functions. + * @mode_config: Configuration for power mode. + * @sd_config: SD Only Configuration. + */ +struct adv7343_platform_data { + struct adv7343_power_mode mode_config; + struct adv7343_sd_config sd_config; +}; + +#endif /* End of #ifndef ADV7343_H */ diff --git a/include/media/i2c/adv7393.h b/include/media/i2c/adv7393.h new file mode 100644 index 000000000..b28edf351 --- /dev/null +++ b/include/media/i2c/adv7393.h @@ -0,0 +1,28 @@ +/* + * ADV7393 header file + * + * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/ + * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> + * + * Based on ADV7343 driver, + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ADV7393_H +#define ADV7393_H + +#define ADV7393_COMPOSITE_ID (0) +#define ADV7393_COMPONENT_ID (1) +#define ADV7393_SVIDEO_ID (2) + +#endif /* End of #ifndef ADV7393_H */ diff --git a/include/media/i2c/adv7511.h b/include/media/i2c/adv7511.h new file mode 100644 index 000000000..1874c05f4 --- /dev/null +++ b/include/media/i2c/adv7511.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Analog Devices ADV7511 HDMI Transmitter Device Driver + * + * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef ADV7511_H +#define ADV7511_H + +/* notify events */ +#define ADV7511_MONITOR_DETECT 0 +#define ADV7511_EDID_DETECT 1 + + +struct adv7511_monitor_detect { + int present; +}; + +struct adv7511_edid_detect { + int present; + int segment; + uint16_t phys_addr; +}; + +struct adv7511_platform_data { + u8 i2c_edid; + u8 i2c_cec; + u8 i2c_pktmem; + u32 cec_clk; +}; + +#endif diff --git a/include/media/i2c/adv7604.h b/include/media/i2c/adv7604.h new file mode 100644 index 000000000..77a979912 --- /dev/null +++ b/include/media/i2c/adv7604.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * adv7604 - Analog Devices ADV7604 video decoder driver + * + * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef _ADV7604_ +#define _ADV7604_ + +#include <linux/types.h> + +/* Analog input muxing modes (AFE register 0x02, [2:0]) */ +enum adv7604_ain_sel { + ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0, + ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1, + ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2, + ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3, + ADV7604_AIN9_4_5_6_SYNC_2_1 = 4, +}; + +/* + * Bus rotation and reordering. This is used to specify component reordering on + * the board and describes the components order on the bus when the ADV7604 + * outputs RGB. + */ +enum adv7604_bus_order { + ADV7604_BUS_ORDER_RGB, /* No operation */ + ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */ + ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */ + ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */ + ADV7604_BUS_ORDER_BRG, /* Rotate right */ + ADV7604_BUS_ORDER_GBR, /* Rotate left */ +}; + +/* Input Color Space (IO register 0x02, [7:4]) */ +enum adv76xx_inp_color_space { + ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0, + ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1, + ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, + ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, + ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4, + ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5, + ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, + ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, + ADV76XX_INP_COLOR_SPACE_AUTO = 0xf, +}; + +/* Select output format (IO register 0x03, [4:2]) */ +enum adv7604_op_format_mode_sel { + ADV7604_OP_FORMAT_MODE0 = 0x00, + ADV7604_OP_FORMAT_MODE1 = 0x04, + ADV7604_OP_FORMAT_MODE2 = 0x08, +}; + +enum adv76xx_drive_strength { + ADV76XX_DR_STR_MEDIUM_LOW = 1, + ADV76XX_DR_STR_MEDIUM_HIGH = 2, + ADV76XX_DR_STR_HIGH = 3, +}; + +/* INT1 Configuration (IO register 0x40, [1:0]) */ +enum adv76xx_int1_config { + ADV76XX_INT1_CONFIG_OPEN_DRAIN, + ADV76XX_INT1_CONFIG_ACTIVE_LOW, + ADV76XX_INT1_CONFIG_ACTIVE_HIGH, + ADV76XX_INT1_CONFIG_DISABLED, +}; + +enum adv76xx_page { + ADV76XX_PAGE_IO, + ADV7604_PAGE_AVLINK, + ADV76XX_PAGE_CEC, + ADV76XX_PAGE_INFOFRAME, + ADV7604_PAGE_ESDP, + ADV7604_PAGE_DPP, + ADV76XX_PAGE_AFE, + ADV76XX_PAGE_REP, + ADV76XX_PAGE_EDID, + ADV76XX_PAGE_HDMI, + ADV76XX_PAGE_TEST, + ADV76XX_PAGE_CP, + ADV7604_PAGE_VDP, + ADV76XX_PAGE_MAX, +}; + +/* Platform dependent definition */ +struct adv76xx_platform_data { + /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ + unsigned disable_pwrdnb:1; + + /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ + unsigned disable_cable_det_rst:1; + + int default_input; + + /* Analog input muxing mode */ + enum adv7604_ain_sel ain_sel; + + /* Bus rotation and reordering */ + enum adv7604_bus_order bus_order; + + /* Select output format mode */ + enum adv7604_op_format_mode_sel op_format_mode_sel; + + /* Configuration of the INT1 pin */ + enum adv76xx_int1_config int1_config; + + /* IO register 0x02 */ + unsigned alt_gamma:1; + + /* IO register 0x05 */ + unsigned blank_data:1; + unsigned insert_av_codes:1; + unsigned replicate_av_codes:1; + + /* IO register 0x06 */ + unsigned inv_vs_pol:1; + unsigned inv_hs_pol:1; + unsigned inv_llc_pol:1; + + /* IO register 0x14 */ + enum adv76xx_drive_strength dr_str_data; + enum adv76xx_drive_strength dr_str_clk; + enum adv76xx_drive_strength dr_str_sync; + + /* IO register 0x30 */ + unsigned output_bus_lsb_to_msb:1; + + /* Free run */ + unsigned hdmi_free_run_mode; + + /* i2c addresses: 0 == use default */ + u8 i2c_addresses[ADV76XX_PAGE_MAX]; +}; + +enum adv76xx_pad { + ADV76XX_PAD_HDMI_PORT_A = 0, + ADV7604_PAD_HDMI_PORT_B = 1, + ADV7604_PAD_HDMI_PORT_C = 2, + ADV7604_PAD_HDMI_PORT_D = 3, + ADV7604_PAD_VGA_RGB = 4, + ADV7604_PAD_VGA_COMP = 5, + /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */ + ADV7604_PAD_SOURCE = 6, + ADV7611_PAD_SOURCE = 1, + ADV76XX_PAD_MAX = 7, +}; + +#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) + +/* notify events */ +#define ADV76XX_HOTPLUG 1 + +#endif diff --git a/include/media/i2c/adv7842.h b/include/media/i2c/adv7842.h new file mode 100644 index 000000000..05e01f0dd --- /dev/null +++ b/include/media/i2c/adv7842.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * adv7842 - Analog Devices ADV7842 video decoder driver + * + * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef _ADV7842_ +#define _ADV7842_ + +/* Analog input muxing modes (AFE register 0x02, [2:0]) */ +enum adv7842_ain_sel { + ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0, + ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1, + ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2, + ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3, + ADV7842_AIN9_4_5_6_SYNC_2_1 = 4, +}; + +/* + * Bus rotation and reordering. This is used to specify component reordering on + * the board and describes the components order on the bus when the ADV7842 + * outputs RGB. + */ +enum adv7842_bus_order { + ADV7842_BUS_ORDER_RGB, /* No operation */ + ADV7842_BUS_ORDER_GRB, /* Swap 1-2 */ + ADV7842_BUS_ORDER_RBG, /* Swap 2-3 */ + ADV7842_BUS_ORDER_BGR, /* Swap 1-3 */ + ADV7842_BUS_ORDER_BRG, /* Rotate right */ + ADV7842_BUS_ORDER_GBR, /* Rotate left */ +}; + +/* Input Color Space (IO register 0x02, [7:4]) */ +enum adv7842_inp_color_space { + ADV7842_INP_COLOR_SPACE_LIM_RGB = 0, + ADV7842_INP_COLOR_SPACE_FULL_RGB = 1, + ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, + ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, + ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4, + ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5, + ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, + ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, + ADV7842_INP_COLOR_SPACE_AUTO = 0xf, +}; + +/* Select output format (IO register 0x03, [4:2]) */ +enum adv7842_op_format_mode_sel { + ADV7842_OP_FORMAT_MODE0 = 0x00, + ADV7842_OP_FORMAT_MODE1 = 0x04, + ADV7842_OP_FORMAT_MODE2 = 0x08, +}; + +/* Mode of operation */ +enum adv7842_mode { + ADV7842_MODE_SDP, + ADV7842_MODE_COMP, + ADV7842_MODE_RGB, + ADV7842_MODE_HDMI +}; + +/* Video standard select (IO register 0x00, [5:0]) */ +enum adv7842_vid_std_select { + /* SDP */ + ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01, + ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09, + /* RGB */ + ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07, + /* HDMI GR */ + ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02, + /* HDMI COMP */ + ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e, +}; + +enum adv7842_select_input { + ADV7842_SELECT_HDMI_PORT_A, + ADV7842_SELECT_HDMI_PORT_B, + ADV7842_SELECT_VGA_RGB, + ADV7842_SELECT_VGA_COMP, + ADV7842_SELECT_SDP_CVBS, + ADV7842_SELECT_SDP_YC, +}; + +enum adv7842_drive_strength { + ADV7842_DR_STR_LOW = 0, + ADV7842_DR_STR_MEDIUM_LOW = 1, + ADV7842_DR_STR_MEDIUM_HIGH = 2, + ADV7842_DR_STR_HIGH = 3, +}; + +struct adv7842_sdp_csc_coeff { + bool manual; + u16 scaling; + u16 A1; + u16 A2; + u16 A3; + u16 A4; + u16 B1; + u16 B2; + u16 B3; + u16 B4; + u16 C1; + u16 C2; + u16 C3; + u16 C4; +}; + +struct adv7842_sdp_io_sync_adjustment { + bool adjust; + u16 hs_beg; + u16 hs_width; + u16 de_beg; + u16 de_end; + u8 vs_beg_o; + u8 vs_beg_e; + u8 vs_end_o; + u8 vs_end_e; + u8 de_v_beg_o; + u8 de_v_beg_e; + u8 de_v_end_o; + u8 de_v_end_e; +}; + +/* Platform dependent definition */ +struct adv7842_platform_data { + /* chip reset during probe */ + unsigned chip_reset:1; + + /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ + unsigned disable_pwrdnb:1; + + /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ + unsigned disable_cable_det_rst:1; + + /* Analog input muxing mode */ + enum adv7842_ain_sel ain_sel; + + /* Bus rotation and reordering */ + enum adv7842_bus_order bus_order; + + /* Select output format mode */ + enum adv7842_op_format_mode_sel op_format_mode_sel; + + /* Default mode */ + enum adv7842_mode mode; + + /* Default input */ + unsigned input; + + /* Video standard */ + enum adv7842_vid_std_select vid_std_select; + + /* IO register 0x02 */ + unsigned alt_gamma:1; + + /* IO register 0x05 */ + unsigned blank_data:1; + unsigned insert_av_codes:1; + unsigned replicate_av_codes:1; + + /* IO register 0x30 */ + unsigned output_bus_lsb_to_msb:1; + + /* IO register 0x14 */ + enum adv7842_drive_strength dr_str_data; + enum adv7842_drive_strength dr_str_clk; + enum adv7842_drive_strength dr_str_sync; + + /* + * IO register 0x19: Adjustment to the LLC DLL phase in + * increments of 1/32 of a clock period. + */ + unsigned llc_dll_phase:5; + + /* External RAM for 3-D comb or frame synchronizer */ + unsigned sd_ram_size; /* ram size in MB */ + unsigned sd_ram_ddr:1; /* ddr or sdr sdram */ + + /* HDMI free run, CP-reg 0xBA */ + unsigned hdmi_free_run_enable:1; + /* 0 = Mode 0: run when there is no TMDS clock + 1 = Mode 1: run when there is no TMDS clock or the + video resolution does not match programmed one. */ + unsigned hdmi_free_run_mode:1; + + /* SDP free run, CP-reg 0xDD */ + unsigned sdp_free_run_auto:1; + unsigned sdp_free_run_man_col_en:1; + unsigned sdp_free_run_cbar_en:1; + unsigned sdp_free_run_force:1; + + /* HPA manual (0) or auto (1), affects HDMI register 0x69 */ + unsigned hpa_auto:1; + + struct adv7842_sdp_csc_coeff sdp_csc_coeff; + + struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625; + struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525; + + /* i2c addresses */ + u8 i2c_sdp_io; + u8 i2c_sdp; + u8 i2c_cp; + u8 i2c_vdp; + u8 i2c_afe; + u8 i2c_hdmi; + u8 i2c_repeater; + u8 i2c_edid; + u8 i2c_infoframe; + u8 i2c_cec; + u8 i2c_avlink; +}; + +#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) + +/* custom ioctl, used to test the external RAM that's used by the + * deinterlacer. */ +#define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE) + +#define ADV7842_EDID_PORT_A 0 +#define ADV7842_EDID_PORT_B 1 +#define ADV7842_EDID_PORT_VGA 2 +#define ADV7842_PAD_SOURCE 3 + +#endif diff --git a/include/media/i2c/ak881x.h b/include/media/i2c/ak881x.h new file mode 100644 index 000000000..ff0597131 --- /dev/null +++ b/include/media/i2c/ak881x.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header for AK8813 / AK8814 TV-ecoders from Asahi Kasei Microsystems Co., Ltd. (AKM) + * + * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> + */ + +#ifndef AK881X_H +#define AK881X_H + +#define AK881X_IF_MODE_MASK (3 << 0) +#define AK881X_IF_MODE_BT656 (0 << 0) +#define AK881X_IF_MODE_MASTER (1 << 0) +#define AK881X_IF_MODE_SLAVE (2 << 0) +#define AK881X_FIELD (1 << 2) +#define AK881X_COMPONENT (1 << 3) + +struct ak881x_pdata { + unsigned long flags; +}; + +#endif diff --git a/include/media/i2c/bt819.h b/include/media/i2c/bt819.h new file mode 100644 index 000000000..70aa46bd5 --- /dev/null +++ b/include/media/i2c/bt819.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + bt819.h - bt819 notifications + + Copyright (C) 2009 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _BT819_H_ +#define _BT819_H_ + +#include <linux/ioctl.h> + +/* v4l2_device notifications. */ + +/* Needed to reset the FIFO buffer when changing the input + or the video standard. + + Note: these ioctls that internal to the kernel and are never called + from userspace. */ +#define BT819_FIFO_RESET_LOW _IO('b', 0) +#define BT819_FIFO_RESET_HIGH _IO('b', 1) + +#endif diff --git a/include/media/i2c/cs5345.h b/include/media/i2c/cs5345.h new file mode 100644 index 000000000..d41e4dca3 --- /dev/null +++ b/include/media/i2c/cs5345.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + cs5345.h - definition for cs5345 inputs and outputs + + Copyright (C) 2007 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _CS5345_H_ +#define _CS5345_H_ + +/* CS5345 HW inputs */ +#define CS5345_IN_MIC 0 +#define CS5345_IN_1 1 +#define CS5345_IN_2 2 +#define CS5345_IN_3 3 +#define CS5345_IN_4 4 +#define CS5345_IN_5 5 +#define CS5345_IN_6 6 + +#define CS5345_MCLK_1 0x00 +#define CS5345_MCLK_1_5 0x10 +#define CS5345_MCLK_2 0x20 +#define CS5345_MCLK_3 0x30 +#define CS5345_MCLK_4 0x40 + +#endif diff --git a/include/media/i2c/cs53l32a.h b/include/media/i2c/cs53l32a.h new file mode 100644 index 000000000..52ceb2f91 --- /dev/null +++ b/include/media/i2c/cs53l32a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + cs53l32a.h - definition for cs53l32a inputs and outputs + + Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _CS53L32A_H_ +#define _CS53L32A_H_ + +/* There are 2 physical inputs, but the second input can be + placed in two modes, the first mode bypasses the PGA (gain), + the second goes through the PGA. Hence there are three + possible inputs to choose from. */ + +/* CS53L32A HW inputs */ +#define CS53L32A_IN0 0 +#define CS53L32A_IN1 1 +#define CS53L32A_IN2 2 + +#endif diff --git a/include/media/i2c/ir-kbd-i2c.h b/include/media/i2c/ir-kbd-i2c.h new file mode 100644 index 000000000..9f47d6a48 --- /dev/null +++ b/include/media/i2c/ir-kbd-i2c.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _IR_I2C +#define _IR_I2C + +#include <media/rc-core.h> + +#define DEFAULT_POLLING_INTERVAL 100 /* ms */ + +struct IR_i2c; + +struct IR_i2c { + char *ir_codes; + struct i2c_client *c; + struct rc_dev *rc; + + /* Used to avoid fast repeating */ + unsigned char old; + + u32 polling_interval; /* in ms */ + + struct delayed_work work; + char phys[32]; + int (*get_key)(struct IR_i2c *ir, + enum rc_proto *protocol, + u32 *scancode, u8 *toggle); + /* tx */ + struct i2c_client *tx_c; + struct mutex lock; /* do not poll Rx during Tx */ + unsigned int carrier; + unsigned int duty_cycle; +}; + +enum ir_kbd_get_key_fn { + IR_KBD_GET_KEY_CUSTOM = 0, + IR_KBD_GET_KEY_PIXELVIEW, + IR_KBD_GET_KEY_HAUP, + IR_KBD_GET_KEY_KNC1, + IR_KBD_GET_KEY_FUSIONHDTV, + IR_KBD_GET_KEY_HAUP_XVR, + IR_KBD_GET_KEY_AVERMEDIA_CARDBUS, +}; + +/* Can be passed when instantiating an ir_video i2c device */ +struct IR_i2c_init_data { + char *ir_codes; + const char *name; + u64 type; /* RC_PROTO_BIT_RC5, etc */ + u32 polling_interval; /* 0 means DEFAULT_POLLING_INTERVAL */ + + /* + * Specify either a function pointer or a value indicating one of + * ir_kbd_i2c's internal get_key functions + */ + int (*get_key)(struct IR_i2c *ir, + enum rc_proto *protocol, + u32 *scancode, u8 *toggle); + enum ir_kbd_get_key_fn internal_get_key_func; + + struct rc_dev *rc_dev; +}; +#endif diff --git a/include/media/i2c/lm3560.h b/include/media/i2c/lm3560.h new file mode 100644 index 000000000..770d8c72c --- /dev/null +++ b/include/media/i2c/lm3560.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/media/i2c/lm3560.h + * + * Copyright (C) 2013 Texas Instruments + * + * Contact: Daniel Jeong <gshark.jeong@gmail.com> + * Ldd-Mlp <ldd-mlp@list.ti.com> + */ + +#ifndef __LM3560_H__ +#define __LM3560_H__ + +#include <media/v4l2-subdev.h> + +#define LM3559_NAME "lm3559" +#define LM3560_NAME "lm3560" +#define LM3560_I2C_ADDR (0x53) + +/* FLASH Brightness + * min 62500uA, step 62500uA, max 1000000uA + */ +#define LM3560_FLASH_BRT_MIN 62500 +#define LM3560_FLASH_BRT_STEP 62500 +#define LM3560_FLASH_BRT_MAX 1000000 +#define LM3560_FLASH_BRT_uA_TO_REG(a) \ + ((a) < LM3560_FLASH_BRT_MIN ? 0 : \ + (((a) - LM3560_FLASH_BRT_MIN) / LM3560_FLASH_BRT_STEP)) +#define LM3560_FLASH_BRT_REG_TO_uA(a) \ + ((a) * LM3560_FLASH_BRT_STEP + LM3560_FLASH_BRT_MIN) + +/* FLASH TIMEOUT DURATION + * min 32ms, step 32ms, max 1024ms + */ +#define LM3560_FLASH_TOUT_MIN 32 +#define LM3560_FLASH_TOUT_STEP 32 +#define LM3560_FLASH_TOUT_MAX 1024 +#define LM3560_FLASH_TOUT_ms_TO_REG(a) \ + ((a) < LM3560_FLASH_TOUT_MIN ? 0 : \ + (((a) - LM3560_FLASH_TOUT_MIN) / LM3560_FLASH_TOUT_STEP)) +#define LM3560_FLASH_TOUT_REG_TO_ms(a) \ + ((a) * LM3560_FLASH_TOUT_STEP + LM3560_FLASH_TOUT_MIN) + +/* TORCH BRT + * min 31250uA, step 31250uA, max 250000uA + */ +#define LM3560_TORCH_BRT_MIN 31250 +#define LM3560_TORCH_BRT_STEP 31250 +#define LM3560_TORCH_BRT_MAX 250000 +#define LM3560_TORCH_BRT_uA_TO_REG(a) \ + ((a) < LM3560_TORCH_BRT_MIN ? 0 : \ + (((a) - LM3560_TORCH_BRT_MIN) / LM3560_TORCH_BRT_STEP)) +#define LM3560_TORCH_BRT_REG_TO_uA(a) \ + ((a) * LM3560_TORCH_BRT_STEP + LM3560_TORCH_BRT_MIN) + +enum lm3560_led_id { + LM3560_LED0 = 0, + LM3560_LED1, + LM3560_LED_MAX +}; + +enum lm3560_peak_current { + LM3560_PEAK_1600mA = 0x00, + LM3560_PEAK_2300mA = 0x20, + LM3560_PEAK_3000mA = 0x40, + LM3560_PEAK_3600mA = 0x60 +}; + +/* struct lm3560_platform_data + * + * @peak : peak current + * @max_flash_timeout: flash timeout + * @max_flash_brt: flash mode led brightness + * @max_torch_brt: torch mode led brightness + */ +struct lm3560_platform_data { + enum lm3560_peak_current peak; + + u32 max_flash_timeout; + u32 max_flash_brt[LM3560_LED_MAX]; + u32 max_torch_brt[LM3560_LED_MAX]; +}; + +#endif /* __LM3560_H__ */ diff --git a/include/media/i2c/lm3646.h b/include/media/i2c/lm3646.h new file mode 100644 index 000000000..845f07b89 --- /dev/null +++ b/include/media/i2c/lm3646.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/media/i2c/lm3646.h + * + * Copyright (C) 2014 Texas Instruments + * + * Contact: Daniel Jeong <gshark.jeong@gmail.com> + * Ldd-Mlp <ldd-mlp@list.ti.com> + */ + +#ifndef __LM3646_H__ +#define __LM3646_H__ + +#include <media/v4l2-subdev.h> + +#define LM3646_NAME "lm3646" +#define LM3646_I2C_ADDR_REV1 (0x67) +#define LM3646_I2C_ADDR_REV0 (0x63) + +/* TOTAL FLASH Brightness Max + * min 93350uA, step 93750uA, max 1499600uA + */ +#define LM3646_TOTAL_FLASH_BRT_MIN 93350 +#define LM3646_TOTAL_FLASH_BRT_STEP 93750 +#define LM3646_TOTAL_FLASH_BRT_MAX 1499600 +#define LM3646_TOTAL_FLASH_BRT_uA_TO_REG(a) \ + ((a) < LM3646_TOTAL_FLASH_BRT_MIN ? 0 : \ + ((((a) - LM3646_TOTAL_FLASH_BRT_MIN) / LM3646_TOTAL_FLASH_BRT_STEP))) + +/* TOTAL TORCH Brightness Max + * min 23040uA, step 23430uA, max 187100uA + */ +#define LM3646_TOTAL_TORCH_BRT_MIN 23040 +#define LM3646_TOTAL_TORCH_BRT_STEP 23430 +#define LM3646_TOTAL_TORCH_BRT_MAX 187100 +#define LM3646_TOTAL_TORCH_BRT_uA_TO_REG(a) \ + ((a) < LM3646_TOTAL_TORCH_BRT_MIN ? 0 : \ + ((((a) - LM3646_TOTAL_TORCH_BRT_MIN) / LM3646_TOTAL_TORCH_BRT_STEP))) + +/* LED1 FLASH Brightness + * min 23040uA, step 11718uA, max 1499600uA + */ +#define LM3646_LED1_FLASH_BRT_MIN 23040 +#define LM3646_LED1_FLASH_BRT_STEP 11718 +#define LM3646_LED1_FLASH_BRT_MAX 1499600 +#define LM3646_LED1_FLASH_BRT_uA_TO_REG(a) \ + ((a) <= LM3646_LED1_FLASH_BRT_MIN ? 0 : \ + ((((a) - LM3646_LED1_FLASH_BRT_MIN) / LM3646_LED1_FLASH_BRT_STEP))+1) + +/* LED1 TORCH Brightness + * min 2530uA, step 1460uA, max 187100uA + */ +#define LM3646_LED1_TORCH_BRT_MIN 2530 +#define LM3646_LED1_TORCH_BRT_STEP 1460 +#define LM3646_LED1_TORCH_BRT_MAX 187100 +#define LM3646_LED1_TORCH_BRT_uA_TO_REG(a) \ + ((a) <= LM3646_LED1_TORCH_BRT_MIN ? 0 : \ + ((((a) - LM3646_LED1_TORCH_BRT_MIN) / LM3646_LED1_TORCH_BRT_STEP))+1) + +/* FLASH TIMEOUT DURATION + * min 50ms, step 50ms, max 400ms + */ +#define LM3646_FLASH_TOUT_MIN 50 +#define LM3646_FLASH_TOUT_STEP 50 +#define LM3646_FLASH_TOUT_MAX 400 +#define LM3646_FLASH_TOUT_ms_TO_REG(a) \ + ((a) <= LM3646_FLASH_TOUT_MIN ? 0 : \ + (((a) - LM3646_FLASH_TOUT_MIN) / LM3646_FLASH_TOUT_STEP)) + +/* struct lm3646_platform_data + * + * @flash_timeout: flash timeout + * @led1_flash_brt: led1 flash mode brightness, uA + * @led1_torch_brt: led1 torch mode brightness, uA + */ +struct lm3646_platform_data { + + u32 flash_timeout; + + u32 led1_flash_brt; + u32 led1_torch_brt; +}; + +#endif /* __LM3646_H__ */ diff --git a/include/media/i2c/m52790.h b/include/media/i2c/m52790.h new file mode 100644 index 000000000..3f214fa9b --- /dev/null +++ b/include/media/i2c/m52790.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + m52790.h - definition for m52790 inputs and outputs + + Copyright (C) 2007 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _M52790_H_ +#define _M52790_H_ + +/* Input routing switch 1 */ + +#define M52790_SW1_IN_MASK 0x0003 +#define M52790_SW1_IN_TUNER 0x0000 +#define M52790_SW1_IN_V2 0x0001 +#define M52790_SW1_IN_V3 0x0002 +#define M52790_SW1_IN_V4 0x0003 + +/* Selects component input instead of composite */ +#define M52790_SW1_YCMIX 0x0004 + + +/* Input routing switch 2 */ + +#define M52790_SW2_IN_MASK 0x0300 +#define M52790_SW2_IN_TUNER 0x0000 +#define M52790_SW2_IN_V2 0x0100 +#define M52790_SW2_IN_V3 0x0200 +#define M52790_SW2_IN_V4 0x0300 + +/* Selects component input instead of composite */ +#define M52790_SW2_YCMIX 0x0400 + + +/* Output routing switch 1 */ + +/* Enable 6dB amplifier for composite out */ +#define M52790_SW1_V_AMP 0x0008 + +/* Enable 6dB amplifier for component out */ +#define M52790_SW1_YC_AMP 0x0010 + +/* Audio output mode */ +#define M52790_SW1_AUDIO_MASK 0x00c0 +#define M52790_SW1_AUDIO_MUTE 0x0000 +#define M52790_SW1_AUDIO_R 0x0040 +#define M52790_SW1_AUDIO_L 0x0080 +#define M52790_SW1_AUDIO_STEREO 0x00c0 + + +/* Output routing switch 2 */ + +/* Enable 6dB amplifier for composite out */ +#define M52790_SW2_V_AMP 0x0800 + +/* Enable 6dB amplifier for component out */ +#define M52790_SW2_YC_AMP 0x1000 + +/* Audio output mode */ +#define M52790_SW2_AUDIO_MASK 0xc000 +#define M52790_SW2_AUDIO_MUTE 0x0000 +#define M52790_SW2_AUDIO_R 0x4000 +#define M52790_SW2_AUDIO_L 0x8000 +#define M52790_SW2_AUDIO_STEREO 0xc000 + + +/* Common values */ +#define M52790_IN_TUNER (M52790_SW1_IN_TUNER | M52790_SW2_IN_TUNER) +#define M52790_IN_V2 (M52790_SW1_IN_V2 | M52790_SW2_IN_V2) +#define M52790_IN_V3 (M52790_SW1_IN_V3 | M52790_SW2_IN_V3) +#define M52790_IN_V4 (M52790_SW1_IN_V4 | M52790_SW2_IN_V4) + +#define M52790_OUT_STEREO (M52790_SW1_AUDIO_STEREO | \ + M52790_SW2_AUDIO_STEREO) +#define M52790_OUT_AMP_STEREO (M52790_SW1_AUDIO_STEREO | \ + M52790_SW1_V_AMP | \ + M52790_SW2_AUDIO_STEREO | \ + M52790_SW2_V_AMP) + +#endif diff --git a/include/media/i2c/m5mols.h b/include/media/i2c/m5mols.h new file mode 100644 index 000000000..9cec5a09e --- /dev/null +++ b/include/media/i2c/m5mols.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver header for M-5MOLS 8M Pixel camera sensor with ISP + * + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + * Author: HeungJun Kim <riverful.kim@samsung.com> + * + * Copyright (C) 2009 Samsung Electronics Co., Ltd. + * Author: Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com> + */ + +#ifndef MEDIA_M5MOLS_H +#define MEDIA_M5MOLS_H + +/** + * struct m5mols_platform_data - platform data for M-5MOLS driver + * @gpio_reset: GPIO driving the reset pin of M-5MOLS + * @reset_polarity: active state for gpio_reset pin, 0 or 1 + * @set_power: an additional callback to the board setup code + * to be called after enabling and before disabling + * the sensor's supply regulators + */ +struct m5mols_platform_data { + int gpio_reset; + u8 reset_polarity; + int (*set_power)(struct device *dev, int on); +}; + +#endif /* MEDIA_M5MOLS_H */ diff --git a/include/media/i2c/mt9m032.h b/include/media/i2c/mt9m032.h new file mode 100644 index 000000000..1bd587577 --- /dev/null +++ b/include/media/i2c/mt9m032.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Driver for MT9M032 CMOS Image Sensor from Micron + * + * Copyright (C) 2010-2011 Lund Engineering + * Contact: Gil Lund <gwlund@lundeng.com> + * Author: Martin Hostettler <martin@neutronstar.dyndns.org> + */ + +#ifndef MT9M032_H +#define MT9M032_H + +#define MT9M032_NAME "mt9m032" +#define MT9M032_I2C_ADDR (0xb8 >> 1) + +struct mt9m032_platform_data { + u32 ext_clock; + u32 pix_clock; + bool invert_pixclock; + +}; +#endif /* MT9M032_H */ diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h new file mode 100644 index 000000000..7c29c53aa --- /dev/null +++ b/include/media/i2c/mt9p031.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef MT9P031_H +#define MT9P031_H + +struct v4l2_subdev; + +/* + * struct mt9p031_platform_data - MT9P031 platform data + * @ext_freq: Input clock frequency + * @target_freq: Pixel clock frequency + */ +struct mt9p031_platform_data { + int ext_freq; + int target_freq; +}; + +#endif diff --git a/include/media/i2c/mt9t001.h b/include/media/i2c/mt9t001.h new file mode 100644 index 000000000..4b1090554 --- /dev/null +++ b/include/media/i2c/mt9t001.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _MEDIA_MT9T001_H +#define _MEDIA_MT9T001_H + +struct mt9t001_platform_data { + unsigned int clk_pol:1; + unsigned int ext_clk; +}; + +#endif diff --git a/include/media/i2c/mt9t112.h b/include/media/i2c/mt9t112.h new file mode 100644 index 000000000..cc80d5cc2 --- /dev/null +++ b/include/media/i2c/mt9t112.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* mt9t112 Camera + * + * Copyright (C) 2009 Renesas Solutions Corp. + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + */ + +#ifndef __MT9T112_H__ +#define __MT9T112_H__ + +struct mt9t112_pll_divider { + u8 m, n; + u8 p1, p2, p3, p4, p5, p6, p7; +}; + +/** + * mt9t112_platform_data - mt9t112 driver interface + * @flags: Sensor media bus configuration. + * @divider: Sensor PLL configuration + */ +struct mt9t112_platform_data { +#define MT9T112_FLAG_PCLK_RISING_EDGE BIT(0) + u32 flags; + struct mt9t112_pll_divider divider; +}; + +#endif /* __MT9T112_H__ */ diff --git a/include/media/i2c/mt9v011.h b/include/media/i2c/mt9v011.h new file mode 100644 index 000000000..41c00b3e7 --- /dev/null +++ b/include/media/i2c/mt9v011.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* mt9v011 sensor + * + * Copyright (C) 2011 Hans Verkuil <hverkuil@xs4all.nl> + */ + +#ifndef __MT9V011_H__ +#define __MT9V011_H__ + +struct mt9v011_platform_data { + unsigned xtal; /* Hz */ +}; + +#endif diff --git a/include/media/i2c/mt9v022.h b/include/media/i2c/mt9v022.h new file mode 100644 index 000000000..6966eb538 --- /dev/null +++ b/include/media/i2c/mt9v022.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mt9v022 sensor + */ + +#ifndef __MT9V022_H__ +#define __MT9V022_H__ + +struct mt9v022_platform_data { + unsigned short y_skip_top; /* Lines to skip at the top */ +}; + +#endif diff --git a/include/media/i2c/mt9v032.h b/include/media/i2c/mt9v032.h new file mode 100644 index 000000000..83a37ccfb --- /dev/null +++ b/include/media/i2c/mt9v032.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _MEDIA_MT9V032_H +#define _MEDIA_MT9V032_H + +struct mt9v032_platform_data { + unsigned int clk_pol:1; + + const s64 *link_freqs; + s64 link_def_freq; +}; + +#endif diff --git a/include/media/i2c/noon010pc30.h b/include/media/i2c/noon010pc30.h new file mode 100644 index 000000000..a035d2d9a --- /dev/null +++ b/include/media/i2c/noon010pc30.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver header for NOON010PC30L camera sensor chip. + * + * Copyright (c) 2010 Samsung Electronics, Co. Ltd + * Contact: Sylwester Nawrocki <s.nawrocki@samsung.com> + */ + +#ifndef NOON010PC30_H +#define NOON010PC30_H + +/** + * @clk_rate: the clock frequency in Hz + * @gpio_nreset: GPIO driving nRESET pin + * @gpio_nstby: GPIO driving nSTBY pin + */ + +struct noon010pc30_platform_data { + unsigned long clk_rate; + int gpio_nreset; + int gpio_nstby; +}; + +#endif /* NOON010PC30_H */ diff --git a/include/media/i2c/ov2659.h b/include/media/i2c/ov2659.h new file mode 100644 index 000000000..4216adc1e --- /dev/null +++ b/include/media/i2c/ov2659.h @@ -0,0 +1,34 @@ +/* + * Omnivision OV2659 CMOS Image Sensor driver + * + * Copyright (C) 2015 Texas Instruments, Inc. + * + * Benoit Parrot <bparrot@ti.com> + * Lad, Prabhakar <prabhakar.csengg@gmail.com> + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef OV2659_H +#define OV2659_H + +/** + * struct ov2659_platform_data - ov2659 driver platform data + * @link_frequency: target pixel clock frequency + */ +struct ov2659_platform_data { + s64 link_frequency; +}; + +#endif /* OV2659_H */ diff --git a/include/media/i2c/ov7670.h b/include/media/i2c/ov7670.h new file mode 100644 index 000000000..8686fc212 --- /dev/null +++ b/include/media/i2c/ov7670.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * A V4L2 driver for OmniVision OV7670 cameras. + * + * Copyright 2010 One Laptop Per Child + */ + +#ifndef __OV7670_H +#define __OV7670_H + +struct ov7670_config { + int min_width; /* Filter out smaller sizes */ + int min_height; /* Filter out smaller sizes */ + int clock_speed; /* External clock speed (MHz) */ + bool use_smbus; /* Use smbus I/O instead of I2C */ + bool pll_bypass; /* Choose whether to bypass the PLL */ + bool pclk_hb_disable; /* Disable toggling pixclk during horizontal blanking */ +}; + +#endif diff --git a/include/media/i2c/ov772x.h b/include/media/i2c/ov772x.h new file mode 100644 index 000000000..a1702d420 --- /dev/null +++ b/include/media/i2c/ov772x.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ov772x Camera + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + */ + +#ifndef __OV772X_H__ +#define __OV772X_H__ + +/* for flags */ +#define OV772X_FLAG_VFLIP (1 << 0) /* Vertical flip image */ +#define OV772X_FLAG_HFLIP (1 << 1) /* Horizontal flip image */ + +/* + * for Edge ctrl + * + * strength also control Auto or Manual Edge Control Mode + * see also OV772X_MANUAL_EDGE_CTRL + */ +struct ov772x_edge_ctrl { + unsigned char strength; + unsigned char threshold; + unsigned char upper; + unsigned char lower; +}; + +#define OV772X_MANUAL_EDGE_CTRL 0x80 /* un-used bit of strength */ +#define OV772X_EDGE_STRENGTH_MASK 0x1F +#define OV772X_EDGE_THRESHOLD_MASK 0x0F +#define OV772X_EDGE_UPPER_MASK 0xFF +#define OV772X_EDGE_LOWER_MASK 0xFF + +#define OV772X_AUTO_EDGECTRL(u, l) \ +{ \ + .upper = (u & OV772X_EDGE_UPPER_MASK), \ + .lower = (l & OV772X_EDGE_LOWER_MASK), \ +} + +#define OV772X_MANUAL_EDGECTRL(s, t) \ +{ \ + .strength = (s & OV772X_EDGE_STRENGTH_MASK) | \ + OV772X_MANUAL_EDGE_CTRL, \ + .threshold = (t & OV772X_EDGE_THRESHOLD_MASK), \ +} + +/** + * ov772x_camera_info - ov772x driver interface structure + * @flags: Sensor configuration flags + * @edgectrl: Sensor edge control + */ +struct ov772x_camera_info { + unsigned long flags; + struct ov772x_edge_ctrl edgectrl; +}; + +#endif /* __OV772X_H__ */ diff --git a/include/media/i2c/ov9650.h b/include/media/i2c/ov9650.h new file mode 100644 index 000000000..3ec7e0695 --- /dev/null +++ b/include/media/i2c/ov9650.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * OV9650/OV9652 camera sensors driver + * + * Copyright (C) 2013 Sylwester Nawrocki <sylvester.nawrocki@gmail.com> + */ +#ifndef OV9650_H_ +#define OV9650_H_ + +/** + * struct ov9650_platform_data - ov9650 driver platform data + * @mclk_frequency: the sensor's master clock frequency in Hz + * @gpio_pwdn: number of a GPIO connected to OV965X PWDN pin + * @gpio_reset: number of a GPIO connected to OV965X RESET pin + * + * If any of @gpio_pwdn or @gpio_reset are unused then they should be + * set to a negative value. @mclk_frequency must always be specified. + */ +struct ov9650_platform_data { + unsigned long mclk_frequency; + int gpio_pwdn; + int gpio_reset; +}; +#endif /* OV9650_H_ */ diff --git a/include/media/i2c/rj54n1cb0c.h b/include/media/i2c/rj54n1cb0c.h new file mode 100644 index 000000000..5689c09b9 --- /dev/null +++ b/include/media/i2c/rj54n1cb0c.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * RJ54N1CB0C Private data + * + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de> + */ + +#ifndef __RJ54N1CB0C_H__ +#define __RJ54N1CB0C_H__ + +struct rj54n1_pdata { + unsigned int mclk_freq; + bool ioctl_high; +}; + +#endif diff --git a/include/media/i2c/s5c73m3.h b/include/media/i2c/s5c73m3.h new file mode 100644 index 000000000..ccb9e5448 --- /dev/null +++ b/include/media/i2c/s5c73m3.h @@ -0,0 +1,55 @@ +/* + * Samsung LSI S5C73M3 8M pixel camera driver + * + * Copyright (C) 2012, Samsung Electronics, Co., Ltd. + * Sylwester Nawrocki <s.nawrocki@samsung.com> + * Andrzej Hajda <a.hajda@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef MEDIA_S5C73M3__ +#define MEDIA_S5C73M3__ + +#include <linux/videodev2.h> +#include <media/v4l2-mediabus.h> + +/** + * struct s5c73m3_gpio - data structure describing a GPIO + * @gpio: GPIO number + * @level: indicates active state of the @gpio + */ +struct s5c73m3_gpio { + int gpio; + int level; +}; + +/** + * struct s5c73m3_platform_data - s5c73m3 driver platform data + * @mclk_frequency: sensor's master clock frequency in Hz + * @gpio_reset: GPIO driving RESET pin + * @gpio_stby: GPIO driving STBY pin + * @nlanes: maximum number of MIPI-CSI lanes used + * @horiz_flip: default horizontal image flip value, non zero to enable + * @vert_flip: default vertical image flip value, non zero to enable + */ + +struct s5c73m3_platform_data { + unsigned long mclk_frequency; + + struct s5c73m3_gpio gpio_reset; + struct s5c73m3_gpio gpio_stby; + + enum v4l2_mbus_type bus_type; + u8 nlanes; + u8 horiz_flip; + u8 vert_flip; +}; + +#endif /* MEDIA_S5C73M3__ */ diff --git a/include/media/i2c/s5k4ecgx.h b/include/media/i2c/s5k4ecgx.h new file mode 100644 index 000000000..fccb7be8e --- /dev/null +++ b/include/media/i2c/s5k4ecgx.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * S5K4ECGX image sensor header file + * + * Copyright (C) 2012, Linaro + * Copyright (C) 2012, Samsung Electronics Co., Ltd. + */ + +#ifndef S5K4ECGX_H +#define S5K4ECGX_H + +/** + * struct s5k4ecgx_gpio - data structure describing a GPIO + * @gpio : GPIO number + * @level: indicates active state of the @gpio + */ +struct s5k4ecgx_gpio { + int gpio; + int level; +}; + +/** + * struct ss5k4ecgx_platform_data- s5k4ecgx driver platform data + * @gpio_reset: GPIO driving RESET pin + * @gpio_stby : GPIO driving STBY pin + */ + +struct s5k4ecgx_platform_data { + struct s5k4ecgx_gpio gpio_reset; + struct s5k4ecgx_gpio gpio_stby; +}; + +#endif /* S5K4ECGX_H */ diff --git a/include/media/i2c/s5k6aa.h b/include/media/i2c/s5k6aa.h new file mode 100644 index 000000000..fd78e85e8 --- /dev/null +++ b/include/media/i2c/s5k6aa.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * S5K6AAFX camera sensor driver header + * + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + */ + +#ifndef S5K6AA_H +#define S5K6AA_H + +#include <media/v4l2-mediabus.h> + +/** + * struct s5k6aa_gpio - data structure describing a GPIO + * @gpio: GPIO number + * @level: indicates active state of the @gpio + */ +struct s5k6aa_gpio { + int gpio; + int level; +}; + +/** + * struct s5k6aa_platform_data - s5k6aa driver platform data + * @set_power: an additional callback to the board code, called + * after enabling the regulators and before switching + * the sensor off + * @mclk_frequency: sensor's master clock frequency in Hz + * @gpio_reset: GPIO driving RESET pin + * @gpio_stby: GPIO driving STBY pin + * @nlanes: maximum number of MIPI-CSI lanes used + * @horiz_flip: default horizontal image flip value, non zero to enable + * @vert_flip: default vertical image flip value, non zero to enable + */ + +struct s5k6aa_platform_data { + int (*set_power)(int enable); + unsigned long mclk_frequency; + struct s5k6aa_gpio gpio_reset; + struct s5k6aa_gpio gpio_stby; + enum v4l2_mbus_type bus_type; + u8 nlanes; + u8 horiz_flip; + u8 vert_flip; +}; + +#endif /* S5K6AA_H */ diff --git a/include/media/i2c/saa6588.h b/include/media/i2c/saa6588.h new file mode 100644 index 000000000..bbec05a31 --- /dev/null +++ b/include/media/i2c/saa6588.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + + Types and defines needed for RDS. This is included by + saa6588.c and every driver (e.g. bttv-driver.c) that wants + to use the saa6588 module. + + (c) 2005 by Hans J. Koch + + +*/ + +#ifndef _SAA6588_H +#define _SAA6588_H + +struct saa6588_command { + unsigned int block_count; + bool nonblocking; + int result; + unsigned char __user *buffer; + struct file *instance; + poll_table *event_list; + __poll_t poll_mask; +}; + +/* These ioctls are internal to the kernel */ +#define SAA6588_CMD_CLOSE _IOW('R', 2, int) +#define SAA6588_CMD_READ _IOR('R', 3, int) +#define SAA6588_CMD_POLL _IOR('R', 4, int) + +#endif diff --git a/include/media/i2c/saa7115.h b/include/media/i2c/saa7115.h new file mode 100644 index 000000000..0cd6080d7 --- /dev/null +++ b/include/media/i2c/saa7115.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags + + Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _SAA7115_H_ +#define _SAA7115_H_ + +/* s_routing inputs, outputs, and config */ + +/* SAA7111/3/4/5 HW inputs */ +#define SAA7115_COMPOSITE0 0 +#define SAA7115_COMPOSITE1 1 +#define SAA7115_COMPOSITE2 2 +#define SAA7115_COMPOSITE3 3 +#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */ +#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */ +#define SAA7115_SVIDEO0 6 +#define SAA7115_SVIDEO1 7 +#define SAA7115_SVIDEO2 8 +#define SAA7115_SVIDEO3 9 + +/* outputs */ +#define SAA7115_IPORT_ON 1 +#define SAA7115_IPORT_OFF 0 + +/* SAA7111 specific outputs. */ +#define SAA7111_VBI_BYPASS 2 +#define SAA7111_FMT_YUV422 0x00 +#define SAA7111_FMT_RGB 0x40 +#define SAA7111_FMT_CCIR 0x80 +#define SAA7111_FMT_YUV411 0xc0 + +/* config flags */ +/* + * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit + * controls the IDQ signal polarity which is set to 'inverted' if the bit + * it 1 and to 'default' if it is 0. + */ +#define SAA7115_IDQ_IS_DEFAULT (1 << 0) + +/* s_crystal_freq values and flags */ + +/* SAA7115 v4l2_crystal_freq frequency values */ +#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ +#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ + +/* SAA7115 v4l2_crystal_freq audio clock control flags */ +#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ +#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ +#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ +#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */ + +/* ===== SAA7113 Config enums ===== */ + +/* Register 0x08 "Horizontal time constant" [Bit 3..4]: + * Should be set to "Fast Locking Mode" according to the datasheet, + * and that is the default setting in the gm7113c_init table. + * saa7113_init sets this value to "VTR Mode". */ +enum saa7113_r08_htc { + SAA7113_HTC_TV_MODE = 0x00, + SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */ + SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */ +}; + +/* Register 0x10 "Output format selection" [Bit 6..7]: + * Defaults to ITU_656 as specified in datasheet. */ +enum saa7113_r10_ofts { + SAA7113_OFTS_ITU_656 = 0x0, /* Default */ + SAA7113_OFTS_VFLAG_BY_VREF, + SAA7113_OFTS_VFLAG_BY_DATA_TYPE +}; + +/* + * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]: + * This is used to select what data is output on the RTS0 and RTS1 pins. + * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0) + * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified + * in the datasheet, but is set to HREF_HS in the saa7113_init table. + */ +enum saa7113_r12_rts { + SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */ + SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */ + SAA7113_RTS_GPSW, + SAA7115_RTS_HL, + SAA7113_RTS_VL, + SAA7113_RTS_DL, + SAA7113_RTS_PLIN, + SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */ + SAA7113_RTS_HS, + SAA7113_RTS_HQ, + SAA7113_RTS_ODD, + SAA7113_RTS_VS, + SAA7113_RTS_V123, + SAA7113_RTS_VGATE, + SAA7113_RTS_VREF, + SAA7113_RTS_FID +}; + +/** + * struct saa7115_platform_data - Allow overriding default initialization + * + * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table + * instead of saa7113_init table + * (saa7113 only) + * @saa7113_r08_htc: [R_08 - Bit 3..4] + * @saa7113_r10_vrln: [R_10 - Bit 3] + * default: Disabled for gm7113c_init + * Enabled for saa7113c_init + * @saa7113_r10_ofts: [R_10 - Bit 6..7] + * @saa7113_r12_rts0: [R_12 - Bit 0..3] + * @saa7113_r12_rts1: [R_12 - Bit 4..7] + * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled + */ +struct saa7115_platform_data { + bool saa7113_force_gm7113c_init; + enum saa7113_r08_htc *saa7113_r08_htc; + bool *saa7113_r10_vrln; + enum saa7113_r10_ofts *saa7113_r10_ofts; + enum saa7113_r12_rts *saa7113_r12_rts0; + enum saa7113_r12_rts *saa7113_r12_rts1; + bool *saa7113_r13_adlsb; +}; + +#endif diff --git a/include/media/i2c/saa7127.h b/include/media/i2c/saa7127.h new file mode 100644 index 000000000..53ee999e6 --- /dev/null +++ b/include/media/i2c/saa7127.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + saa7127.h - definition for saa7126/7/8/9 inputs/outputs + + Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _SAA7127_H_ +#define _SAA7127_H_ + +/* Enumeration for the supported input types */ +enum saa7127_input_type { + SAA7127_INPUT_TYPE_NORMAL, + SAA7127_INPUT_TYPE_TEST_IMAGE +}; + +/* Enumeration for the supported output signal types */ +enum saa7127_output_type { + SAA7127_OUTPUT_TYPE_BOTH, + SAA7127_OUTPUT_TYPE_COMPOSITE, + SAA7127_OUTPUT_TYPE_SVIDEO, + SAA7127_OUTPUT_TYPE_RGB, + SAA7127_OUTPUT_TYPE_YUV_C, + SAA7127_OUTPUT_TYPE_YUV_V +}; + +#endif diff --git a/include/media/i2c/sr030pc30.h b/include/media/i2c/sr030pc30.h new file mode 100644 index 000000000..84c602d68 --- /dev/null +++ b/include/media/i2c/sr030pc30.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver header for SR030PC30 camera sensor + * + * Copyright (c) 2010 Samsung Electronics, Co. Ltd + * Contact: Sylwester Nawrocki <s.nawrocki@samsung.com> + */ + +#ifndef SR030PC30_H +#define SR030PC30_H + +struct sr030pc30_platform_data { + unsigned long clk_rate; /* master clock frequency in Hz */ + int (*set_power)(struct device *dev, int on); +}; + +#endif /* SR030PC30_H */ diff --git a/include/media/i2c/tc358743.h b/include/media/i2c/tc358743.h new file mode 100644 index 000000000..b343650c2 --- /dev/null +++ b/include/media/i2c/tc358743.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * tc358743 - Toshiba HDMI to CSI-2 bridge + * + * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +/* + * References (c = chapter, p = page): + * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 + * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls + */ + +#ifndef _TC358743_ +#define _TC358743_ + +enum tc358743_ddc5v_delays { + DDC5V_DELAY_0_MS, + DDC5V_DELAY_50_MS, + DDC5V_DELAY_100_MS, + DDC5V_DELAY_200_MS, +}; + +enum tc358743_hdmi_detection_delay { + HDMI_MODE_DELAY_0_MS, + HDMI_MODE_DELAY_25_MS, + HDMI_MODE_DELAY_50_MS, + HDMI_MODE_DELAY_100_MS, +}; + +struct tc358743_platform_data { + /* System clock connected to REFCLK (pin H5) */ + u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ + + /* DDC +5V debounce delay to avoid spurious interrupts when the cable + * is connected. + * Sets DDC5V_MODE in register DDC_CTL. + * Default: DDC5V_DELAY_0_MS + */ + enum tc358743_ddc5v_delays ddc5v_delay; + + bool enable_hdcp; + + /* + * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO + * level to somewhere in the middle (e.g. 300), so it can cover speed + * mismatches in input and output ports. + */ + u16 fifo_level; + + /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */ + u16 pll_prd; + u16 pll_fbd; + + /* CSI + * Calculate CSI parameters with REF_02 for the highest resolution your + * CSI interface can handle. The driver will adjust the number of CSI + * lanes in use according to the pixel clock. + * + * The values in brackets are calculated with REF_02 when the number of + * bps pr lane is 823.5 MHz, and can serve as a starting point. + */ + u32 lineinitcnt; /* (0x00001770) */ + u32 lptxtimecnt; /* (0x00000005) */ + u32 tclk_headercnt; /* (0x00001d04) */ + u32 tclk_trailcnt; /* (0x00000000) */ + u32 ths_headercnt; /* (0x00000505) */ + u32 twakeup; /* (0x00004650) */ + u32 tclk_postcnt; /* (0x00000000) */ + u32 ths_trailcnt; /* (0x00000004) */ + u32 hstxvregcnt; /* (0x00000005) */ + + /* DVI->HDMI detection delay to avoid unnecessary switching between DVI + * and HDMI mode. + * Sets HDMI_DET_V in register HDMI_DET. + * Default: HDMI_MODE_DELAY_0_MS + */ + enum tc358743_hdmi_detection_delay hdmi_detection_delay; + + /* Reset PHY automatically when TMDS clock goes from DC to AC. + * Sets PHY_AUTO_RST2 in register PHY_CTL2. + * Default: false + */ + bool hdmi_phy_auto_reset_tmds_detected; + + /* Reset PHY automatically when TMDS clock passes 21 MHz. + * Sets PHY_AUTO_RST3 in register PHY_CTL2. + * Default: false + */ + bool hdmi_phy_auto_reset_tmds_in_range; + + /* Reset PHY automatically when TMDS clock is detected. + * Sets PHY_AUTO_RST4 in register PHY_CTL2. + * Default: false + */ + bool hdmi_phy_auto_reset_tmds_valid; + + /* Reset HDMI PHY automatically when hsync period is out of range. + * Sets H_PI_RST in register HV_RST. + * Default: false + */ + bool hdmi_phy_auto_reset_hsync_out_of_range; + + /* Reset HDMI PHY automatically when vsync period is out of range. + * Sets V_PI_RST in register HV_RST. + * Default: false + */ + bool hdmi_phy_auto_reset_vsync_out_of_range; +}; + +/* custom controls */ +/* Audio sample rate in Hz */ +#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0) +/* Audio present status */ +#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1) + +#endif diff --git a/include/media/i2c/tda1997x.h b/include/media/i2c/tda1997x.h new file mode 100644 index 000000000..c6c2a8ae4 --- /dev/null +++ b/include/media/i2c/tda1997x.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tda1997x - NXP HDMI receiver + * + * Copyright 2017 Tim Harvey <tharvey@gateworks.com> + * + */ + +#ifndef _TDA1997X_ +#define _TDA1997X_ + +/* Platform Data */ +struct tda1997x_platform_data { + enum v4l2_mbus_type vidout_bus_type; + u32 vidout_bus_width; + u8 vidout_port_cfg[9]; + /* pin polarity (1=invert) */ + bool vidout_inv_de; + bool vidout_inv_hs; + bool vidout_inv_vs; + bool vidout_inv_pclk; + /* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */ + u8 vidout_delay_hs; + u8 vidout_delay_vs; + u8 vidout_delay_de; + u8 vidout_delay_pclk; + /* sync selections (controls how sync pins are derived) */ + u8 vidout_sel_hs; + u8 vidout_sel_vs; + u8 vidout_sel_de; + + /* Audio Port Output */ + int audout_format; + u32 audout_mclk_fs; /* clock multiplier */ + u32 audout_width; /* 13 or 32 bit */ + u32 audout_layout; /* layout0=AP0 layout1=AP0,AP1,AP2,AP3 */ + bool audout_layoutauto; /* audio layout dictated by pkt header */ + bool audout_invert_clk; /* data valid on rising edge of BCLK */ + bool audio_auto_mute; /* enable hardware audio auto-mute */ +}; + +#endif diff --git a/include/media/i2c/ths7303.h b/include/media/i2c/ths7303.h new file mode 100644 index 000000000..95492d127 --- /dev/null +++ b/include/media/i2c/ths7303.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013 Texas Instruments Inc + * + * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. + * + * Contributors: + * Hans Verkuil <hans.verkuil@cisco.com> + * Lad, Prabhakar <prabhakar.lad@ti.com> + * Martin Bugge <marbugge@cisco.com> + */ + +#ifndef THS7353_H +#define THS7353_H + +/** + * struct ths7303_platform_data - Platform dependent data + * @ch_1: Bias value for channel one. + * @ch_2: Bias value for channel two. + * @ch_3: Bias value for channel three. + */ +struct ths7303_platform_data { + u8 ch_1; + u8 ch_2; + u8 ch_3; +}; + +#endif diff --git a/include/media/i2c/tvaudio.h b/include/media/i2c/tvaudio.h new file mode 100644 index 000000000..42cd3206f --- /dev/null +++ b/include/media/i2c/tvaudio.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + tvaudio.h - definition for tvaudio inputs + + Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _TVAUDIO_H +#define _TVAUDIO_H + +/* + * i2c bus addresses for the chips supported by tvaudio.c + */ + +#define I2C_ADDR_TDA8425 0x82 +#define I2C_ADDR_TDA9840 0x84 +#define I2C_ADDR_TDA9874 0xb0 /* also used by 9875 */ +#define I2C_ADDR_TDA9875 0xb0 +#define I2C_ADDR_TDA8425 0x82 +#define I2C_ADDR_TDA9840 0x84 /* also used by TA8874Z */ +#define I2C_ADDR_TDA985x_L 0xb4 /* also used by 9873 */ +#define I2C_ADDR_TDA985x_H 0xb6 +#define I2C_ADDR_TDA9874 0xb0 /* also used by 9875 */ +#define I2C_ADDR_TEA6300 0x80 /* also used by 6320 */ +#define I2C_ADDR_TEA6420 0x98 +#define I2C_ADDR_PIC16C54 0x96 /* PV951 */ + +/* The tvaudio module accepts the following inputs: */ +#define TVAUDIO_INPUT_TUNER 0 +#define TVAUDIO_INPUT_RADIO 1 +#define TVAUDIO_INPUT_EXTERN 2 +#define TVAUDIO_INPUT_INTERN 3 + +static inline const unsigned short *tvaudio_addrs(void) +{ + static const unsigned short addrs[] = { + I2C_ADDR_TDA8425 >> 1, + I2C_ADDR_TEA6300 >> 1, + I2C_ADDR_TEA6420 >> 1, + I2C_ADDR_TDA9840 >> 1, + I2C_ADDR_TDA985x_L >> 1, + I2C_ADDR_TDA985x_H >> 1, + I2C_ADDR_TDA9874 >> 1, + I2C_ADDR_PIC16C54 >> 1, + I2C_CLIENT_END + }; + + return addrs; +} + +#endif diff --git a/include/media/i2c/tvp514x.h b/include/media/i2c/tvp514x.h new file mode 100644 index 000000000..0c1bb04bd --- /dev/null +++ b/include/media/i2c/tvp514x.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * drivers/media/video/tvp514x.h + * + * Copyright (C) 2008 Texas Instruments Inc + * Author: Vaibhav Hiremath <hvaibhav@ti.com> + * + * Contributors: + * Sivaraj R <sivaraj@ti.com> + * Brijesh R Jadav <brijesh.j@ti.com> + * Hardik Shah <hardik.shah@ti.com> + * Manjunath Hadli <mrh@ti.com> + * Karicheri Muralidharan <m-karicheri2@ti.com> + */ + +#ifndef _TVP514X_H +#define _TVP514X_H + +/* + * Other macros + */ +#define TVP514X_MODULE_NAME "tvp514x" + +#define TVP514X_XCLK_BT656 (27000000) + +/* Number of pixels and number of lines per frame for different standards */ +#define NTSC_NUM_ACTIVE_PIXELS (720) +#define NTSC_NUM_ACTIVE_LINES (480) +#define PAL_NUM_ACTIVE_PIXELS (720) +#define PAL_NUM_ACTIVE_LINES (576) + +/** + * enum tvp514x_input - enum for different decoder input pin + * configuration. + */ +enum tvp514x_input { + /* + * CVBS input selection + */ + INPUT_CVBS_VI1A = 0x0, + INPUT_CVBS_VI1B, + INPUT_CVBS_VI1C, + INPUT_CVBS_VI2A = 0x04, + INPUT_CVBS_VI2B, + INPUT_CVBS_VI2C, + INPUT_CVBS_VI3A = 0x08, + INPUT_CVBS_VI3B, + INPUT_CVBS_VI3C, + INPUT_CVBS_VI4A = 0x0C, + /* + * S-Video input selection + */ + INPUT_SVIDEO_VI2A_VI1A = 0x44, + INPUT_SVIDEO_VI2B_VI1B, + INPUT_SVIDEO_VI2C_VI1C, + INPUT_SVIDEO_VI2A_VI3A = 0x54, + INPUT_SVIDEO_VI2B_VI3B, + INPUT_SVIDEO_VI2C_VI3C, + INPUT_SVIDEO_VI4A_VI1A = 0x4C, + INPUT_SVIDEO_VI4A_VI1B, + INPUT_SVIDEO_VI4A_VI1C, + INPUT_SVIDEO_VI4A_VI3A = 0x5C, + INPUT_SVIDEO_VI4A_VI3B, + INPUT_SVIDEO_VI4A_VI3C, + + /* Need to add entries for + * RGB, YPbPr and SCART. + */ + INPUT_INVALID +}; + +/** + * enum tvp514x_output - enum for output format + * supported. + * + */ +enum tvp514x_output { + OUTPUT_10BIT_422_EMBEDDED_SYNC = 0, + OUTPUT_20BIT_422_SEPERATE_SYNC, + OUTPUT_10BIT_422_SEPERATE_SYNC = 3, + OUTPUT_INVALID +}; + +/** + * struct tvp514x_platform_data - Platform data values and access functions. + * @clk_polarity: Clock polarity of the current interface. + * @hs_polarity: HSYNC Polarity configuration for current interface. + * @vs_polarity: VSYNC Polarity configuration for current interface. + */ +struct tvp514x_platform_data { + /* Interface control params */ + bool clk_polarity; + bool hs_polarity; + bool vs_polarity; +}; + + +#endif /* ifndef _TVP514X_H */ diff --git a/include/media/i2c/tvp7002.h b/include/media/i2c/tvp7002.h new file mode 100644 index 000000000..c31eb0040 --- /dev/null +++ b/include/media/i2c/tvp7002.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics + * Digitizer with Horizontal PLL registers + * + * Copyright (C) 2009 Texas Instruments Inc + * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> + * + * This code is partially based upon the TVP5150 driver + * written by Mauro Carvalho Chehab <mchehab@kernel.org>, + * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> + * and the TVP7002 driver in the TI LSP 2.10.00.14 + */ +#ifndef _TVP7002_H_ +#define _TVP7002_H_ + +#define TVP7002_MODULE_NAME "tvp7002" + +/** + * struct tvp7002_config - Platform dependent data + *@clk_polarity: Clock polarity + * 0 - Data clocked out on rising edge of DATACLK signal + * 1 - Data clocked out on falling edge of DATACLK signal + *@hs_polarity: HSYNC polarity + * 0 - Active low HSYNC output, 1 - Active high HSYNC output + *@vs_polarity: VSYNC Polarity + * 0 - Active low VSYNC output, 1 - Active high VSYNC output + *@fid_polarity: Active-high Field ID polarity. + * 0 - The field ID output is set to logic 1 for an odd field + * (field 1) and set to logic 0 for an even field (field 0). + * 1 - Operation with polarity inverted. + *@sog_polarity: Active high Sync on Green output polarity. + * 0 - Normal operation, 1 - Operation with polarity inverted + */ +struct tvp7002_config { + bool clk_polarity; + bool hs_polarity; + bool vs_polarity; + bool fid_polarity; + bool sog_polarity; +}; +#endif diff --git a/include/media/i2c/tw9910.h b/include/media/i2c/tw9910.h new file mode 100644 index 000000000..92d31bd1a --- /dev/null +++ b/include/media/i2c/tw9910.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * tw9910 Driver header + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * Based on ov772x.h + * + * Copyright (C) Kuninori Morimoto <morimoto.kuninori@renesas.com> + */ + +#ifndef __TW9910_H__ +#define __TW9910_H__ + +/** + * tw9910_mpout_pin - MPOUT (multi-purpose output) pin functions + */ +enum tw9910_mpout_pin { + TW9910_MPO_VLOSS, + TW9910_MPO_HLOCK, + TW9910_MPO_SLOCK, + TW9910_MPO_VLOCK, + TW9910_MPO_MONO, + TW9910_MPO_DET50, + TW9910_MPO_FIELD, + TW9910_MPO_RTCO, +}; + +/** + * tw9910_video_info - tw9910 driver interface structure + * @buswidth: Parallel data bus width (8 or 16). + * @mpout: Selected function of MPOUT (multi-purpose output) pin. + * See &enum tw9910_mpout_pin + */ +struct tw9910_video_info { + unsigned long buswidth; + enum tw9910_mpout_pin mpout; +}; + + +#endif /* __TW9910_H__ */ diff --git a/include/media/i2c/uda1342.h b/include/media/i2c/uda1342.h new file mode 100644 index 000000000..cb412d4c1 --- /dev/null +++ b/include/media/i2c/uda1342.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * uda1342.h - definition for uda1342 inputs + * + * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef _UDA1342_H_ +#define _UDA1342_H_ + +/* The UDA1342 has 2 inputs */ + +#define UDA1342_IN1 1 +#define UDA1342_IN2 2 + +#endif diff --git a/include/media/i2c/upd64031a.h b/include/media/i2c/upd64031a.h new file mode 100644 index 000000000..b6570abc8 --- /dev/null +++ b/include/media/i2c/upd64031a.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * upd64031a - NEC Electronics Ghost Reduction input defines + * + * 2006 by Hans Verkuil (hverkuil@xs4all.nl) + */ + +#ifndef _UPD64031A_H_ +#define _UPD64031A_H_ + +/* Ghost reduction modes */ +#define UPD64031A_GR_ON 0 +#define UPD64031A_GR_OFF 1 +#define UPD64031A_GR_THROUGH 3 + +/* Direct 3D/YCS Connection */ +#define UPD64031A_3DYCS_DISABLE (0 << 2) +#define UPD64031A_3DYCS_COMPOSITE (2 << 2) +#define UPD64031A_3DYCS_SVIDEO (3 << 2) + +/* Composite sync digital separation circuit */ +#define UPD64031A_COMPOSITE_EXTERNAL (1 << 4) + +/* Vertical sync digital separation circuit */ +#define UPD64031A_VERTICAL_EXTERNAL (1 << 5) + +#endif diff --git a/include/media/i2c/upd64083.h b/include/media/i2c/upd64083.h new file mode 100644 index 000000000..17fb7b520 --- /dev/null +++ b/include/media/i2c/upd64083.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * upd6408x - NEC Electronics 3-Dimensional Y/C separation input defines + * + * 2006 by Hans Verkuil (hverkuil@xs4all.nl) + */ + +#ifndef _UPD64083_H_ +#define _UPD64083_H_ + +/* There are two bits of information that the driver needs in order + to select the correct routing: the operating mode and the selection + of the Y input (external or internal). + + The first two operating modes expect a composite signal on the Y input, + the second two operating modes use both the Y and C inputs. + + Normally YCS_MODE is used for tuner and composite inputs, and the + YCNR mode is used for S-Video inputs. + + The external Y-ADC is selected when the composite input comes from a + upd64031a ghost reduction device. If this device is not present, or + the input is a S-Video signal, then the internal Y-ADC input should + be used. */ + +/* Operating modes: */ + +/* YCS mode: Y/C separation (burst locked clocking) */ +#define UPD64083_YCS_MODE 0 +/* YCS+ mode: 2D Y/C separation and YCNR (burst locked clocking) */ +#define UPD64083_YCS_PLUS_MODE 1 + +/* Note: the following two modes cannot be used in combination with the + external Y-ADC. */ +/* MNNR mode: frame comb type YNR+C delay (line locked clocking) */ +#define UPD64083_MNNR_MODE 2 +/* YCNR mode: frame recursive YCNR (burst locked clocking) */ +#define UPD64083_YCNR_MODE 3 + +/* Select external Y-ADC: this should be set if this device is used in + combination with the upd64031a ghost reduction device. + Otherwise leave at 0 (use internal Y-ADC). */ +#define UPD64083_EXT_Y_ADC (1 << 2) + +#endif diff --git a/include/media/i2c/wm8775.h b/include/media/i2c/wm8775.h new file mode 100644 index 000000000..836758176 --- /dev/null +++ b/include/media/i2c/wm8775.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + wm8775.h - definition for wm8775 inputs and outputs + + Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) + +*/ + +#ifndef _WM8775_H_ +#define _WM8775_H_ + +/* The WM8775 has 4 inputs and one output. Zero or more inputs + are multiplexed together to the output. Hence there are + 16 combinations. + If only one input is active (the normal case) then the + input values 1, 2, 4 or 8 should be used. */ + +#define WM8775_AIN1 1 +#define WM8775_AIN2 2 +#define WM8775_AIN3 4 +#define WM8775_AIN4 8 + + +struct wm8775_platform_data { + /* + * FIXME: Instead, we should parametrize the params + * that need different settings between ivtv, pvrusb2, and Nova-S + */ + bool is_nova_s; +}; + +#endif |