diff options
Diffstat (limited to '')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7621.h | 34 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h | 60 |
2 files changed, 94 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h new file mode 100644 index 000000000..e1af1ba50 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * + * Copyright (C) 2015 John Crispin <john@phrozen.org> + */ + +#ifndef _MT7621_REGS_H_ +#define _MT7621_REGS_H_ + +#define MT7621_PALMBUS_BASE 0x1C000000 +#define MT7621_PALMBUS_SIZE 0x03FFFFFF + +#define MT7621_SYSC_BASE 0x1E000000 + +#define SYSC_REG_CHIP_NAME0 0x00 +#define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_CHIP_REV 0x0c +#define SYSC_REG_SYSTEM_CONFIG0 0x10 +#define SYSC_REG_SYSTEM_CONFIG1 0x14 + +#define CHIP_REV_PKG_MASK 0x1 +#define CHIP_REV_PKG_SHIFT 16 +#define CHIP_REV_VER_MASK 0xf +#define CHIP_REV_VER_SHIFT 8 +#define CHIP_REV_ECO_MASK 0xf + +#define MT7621_DRAM_BASE 0x0 +#define MT7621_DDR2_SIZE_MIN 32 +#define MT7621_DDR2_SIZE_MAX 256 + +#define MT7621_CHIP_NAME0 0x3637544D +#define MT7621_CHIP_NAME1 0x20203132 + +#endif diff --git a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h new file mode 100644 index 000000000..168359a0a --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Ralink MT7621 specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H +#define _MT7621_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 1 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#define cpu_has_dc_aliases 0 +#define cpu_has_vtag_icache 0 + +#define cpu_has_rixi 0 +#define cpu_has_tlbinv 0 +#define cpu_has_userlocal 1 + +#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */ |