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| -rw-r--r-- | arch/powerpc/platforms/Kconfig | 299 | ||||
| -rw-r--r-- | arch/powerpc/platforms/Kconfig.cputype | 537 |
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diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig new file mode 100644 index 000000000..7a5e8f454 --- /dev/null +++ b/arch/powerpc/platforms/Kconfig @@ -0,0 +1,299 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Platform support" + +source "arch/powerpc/platforms/powernv/Kconfig" +source "arch/powerpc/platforms/pseries/Kconfig" +source "arch/powerpc/platforms/chrp/Kconfig" +source "arch/powerpc/platforms/512x/Kconfig" +source "arch/powerpc/platforms/52xx/Kconfig" +source "arch/powerpc/platforms/powermac/Kconfig" +source "arch/powerpc/platforms/maple/Kconfig" +source "arch/powerpc/platforms/pasemi/Kconfig" +source "arch/powerpc/platforms/ps3/Kconfig" +source "arch/powerpc/platforms/cell/Kconfig" +source "arch/powerpc/platforms/8xx/Kconfig" +source "arch/powerpc/platforms/82xx/Kconfig" +source "arch/powerpc/platforms/83xx/Kconfig" +source "arch/powerpc/platforms/85xx/Kconfig" +source "arch/powerpc/platforms/86xx/Kconfig" +source "arch/powerpc/platforms/embedded6xx/Kconfig" +source "arch/powerpc/platforms/44x/Kconfig" +source "arch/powerpc/platforms/40x/Kconfig" +source "arch/powerpc/platforms/amigaone/Kconfig" + +config KVM_GUEST + bool "KVM Guest support" + select EPAPR_PARAVIRT + help + This option enables various optimizations for running under the KVM + hypervisor. Overhead for the kernel when not running inside KVM should + be minimal. + + In case of doubt, say Y + +config EPAPR_PARAVIRT + bool "ePAPR para-virtualization support" + help + Enables ePAPR para-virtualization support for guests. + + In case of doubt, say Y + +config PPC_NATIVE + bool + depends on PPC_BOOK3S_32 || PPC64 + help + Support for running natively on the hardware, i.e. without + a hypervisor. This option is not user-selectable but should + be selected by all platforms that need it. + +config PPC_OF_BOOT_TRAMPOLINE + bool "Support booting from Open Firmware or yaboot" + depends on PPC_BOOK3S_32 || PPC64 + default y + help + Support from booting from Open Firmware or yaboot using an + Open Firmware client interface. This enables the kernel to + communicate with open firmware to retrieve system information + such as the device tree. + + In case of doubt, say Y + +config PPC_DT_CPU_FTRS + bool "Device-tree based CPU feature discovery & setup" + depends on PPC_BOOK3S_64 + default y + help + This enables code to use a new device tree binding for describing CPU + compatibility and features. Saying Y here will attempt to use the new + binding if the firmware provides it. Currently only the skiboot + firmware provides this binding. + If you're not sure say Y. + +config UDBG_RTAS_CONSOLE + bool "RTAS based debug console" + depends on PPC_RTAS + +config PPC_SMP_MUXED_IPI + bool + help + Select this option if your platform supports SMP and your + interrupt controller provides less than 4 interrupts to each + cpu. This will enable the generic code to multiplex the 4 + messages on to one ipi. + +config IPIC + bool + +config MPIC + bool + +config MPIC_TIMER + bool "MPIC Global Timer" + depends on MPIC && FSL_SOC + help + The MPIC global timer is a hardware timer inside the + Freescale PIC complying with OpenPIC standard. When the + specified interval times out, the hardware timer generates + an interrupt. The driver currently is only tested on fsl + chip, but it can potentially support other global timers + complying with the OpenPIC standard. + +config FSL_MPIC_TIMER_WAKEUP + tristate "Freescale MPIC global timer wakeup driver" + depends on FSL_SOC && MPIC_TIMER && PM + help + The driver provides a way to wake up the system by MPIC + timer. + e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup" + +config PPC_EPAPR_HV_PIC + bool + select EPAPR_PARAVIRT + +config MPIC_WEIRD + bool + +config MPIC_MSGR + bool "MPIC message register support" + depends on MPIC + help + Enables support for the MPIC message registers. These + registers are used for inter-processor communication. + +config PPC_I8259 + bool + +config U3_DART + bool + depends on PPC64 + +config PPC_RTAS + bool + +config RTAS_ERROR_LOGGING + bool + depends on PPC_RTAS + +config PPC_RTAS_DAEMON + bool + depends on PPC_RTAS + +config RTAS_PROC + bool "Proc interface to RTAS" + depends on PPC_RTAS && PROC_FS + default y + +config RTAS_FLASH + tristate "Firmware flash interface" + depends on PPC64 && RTAS_PROC + +config MMIO_NVRAM + bool + +config MPIC_U3_HT_IRQS + bool + +config MPIC_BROKEN_REGREAD + bool + depends on MPIC + help + This option enables a MPIC driver workaround for some chips + that have a bug that causes some interrupt source information + to not read back properly. It is safe to use on other chips as + well, but enabling it uses about 8KB of memory to keep copies + of the register contents in software. + +config EEH + bool + depends on (PPC_POWERNV || PPC_PSERIES) && PCI + default y + +config PPC_MPC106 + bool + +config PPC_970_NAP + bool + +config PPC_P7_NAP + bool + +config PPC_BOOK3S_IDLE + def_bool y + depends on (PPC_970_NAP || PPC_P7_NAP) + +config PPC_INDIRECT_PIO + bool + select GENERIC_IOMAP + +config PPC_INDIRECT_MMIO + bool + +config PPC_IO_WORKAROUNDS + bool + +source "drivers/cpufreq/Kconfig" + +menu "CPUIdle driver" + +source "drivers/cpuidle/Kconfig" + +endmenu + +config TAU + bool "On-chip CPU temperature sensor support" + depends on PPC_BOOK3S_32 + help + G3 and G4 processors have an on-chip temperature sensor called the + 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die + temperature within 2-4 degrees Celsius. This option shows the current + on-die temperature in /proc/cpuinfo if the cpu supports it. + + Unfortunately, this sensor is very inaccurate when uncalibrated, so + don't assume the cpu temp is actually what /proc/cpuinfo says it is. + +config TAU_INT + bool "Interrupt driven TAU driver (EXPERIMENTAL)" + depends on TAU + help + The TAU supports an interrupt driven mode which causes an interrupt + whenever the temperature goes out of range. This is the fastest way + to get notified the temp has exceeded a range. With this option off, + a timer is used to re-check the temperature periodically. + + If in doubt, say N here. + +config TAU_AVERAGE + bool "Average high and low temp" + depends on TAU + help + The TAU hardware can compare the temperature to an upper and lower + bound. The default behavior is to show both the upper and lower + bound in /proc/cpuinfo. If the range is large, the temperature is + either changing a lot, or the TAU hardware is broken (likely on some + G4's). If the range is small (around 4 degrees), the temperature is + relatively stable. If you say Y here, a single temperature value, + halfway between the upper and lower bounds, will be reported in + /proc/cpuinfo. + + If in doubt, say N here. + +config QE_GPIO + bool "QE GPIO support" + depends on QUICC_ENGINE + select GPIOLIB + help + Say Y here if you're going to use hardware that connects to the + QE GPIOs. + +config CPM2 + bool "Enable support for the CPM2 (Communications Processor Module)" + depends on (FSL_SOC_BOOKE && PPC32) || 8260 + select CPM + select HAVE_PCI + select GPIOLIB + help + The CPM2 (Communications Processor Module) is a coprocessor on + embedded CPUs made by Freescale. Selecting this option means that + you wish to build a kernel for a machine with a CPM2 coprocessor + on it (826x, 827x, 8560). + +config FSL_ULI1575 + bool + select GENERIC_ISA_DMA + help + Supports for the ULI1575 PCIe south bridge that exists on some + Freescale reference boards. The boards all use the ULI in pretty + much the same way. + +config CPM + bool + select GENERIC_ALLOCATOR + +config OF_RTC + bool + help + Uses information from the OF or flattened device tree to instantiate + platform devices for direct mapped RTC chips like the DS1742 or DS1743. + +config GEN_RTC + bool "Use the platform RTC operations from user space" + select RTC_CLASS + select RTC_DRV_GENERIC + help + This option provides backwards compatibility with the old gen_rtc.ko + module that was traditionally used for old PowerPC machines. + Platforms should migrate to enabling the RTC_DRV_GENERIC by hand + replacing their get_rtc_time/set_rtc_time callbacks with + a proper RTC device driver. + +config MCU_MPC8349EMITX + bool "MPC8349E-mITX MCU driver" + depends on I2C=y && PPC_83xx + select GPIOLIB + help + Say Y here to enable soft power-off functionality on the Freescale + boards with the MPC8349E-mITX-compatible MCU chips. This driver will + also register MCU GPIOs with the generic GPIO API, so you'll able + to use MCU pins as GPIOs. + +endmenu diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype new file mode 100644 index 000000000..84f9dd476 --- /dev/null +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -0,0 +1,537 @@ +# SPDX-License-Identifier: GPL-2.0 +config PPC32 + bool + default y if !PPC64 + select KASAN_VMALLOC if KASAN && MODULES + +config PPC64 + bool "64-bit kernel" + select ZLIB_DEFLATE + help + This option selects whether a 32-bit or a 64-bit kernel + will be built. + +config PPC_BOOK3S_32 + bool + +menu "Processor support" +choice + prompt "Processor Type" + depends on PPC32 + help + There are five families of 32 bit PowerPC chips supported. + The most common ones are the desktop and server CPUs (603, + 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their + embedded 512x/52xx/82xx/83xx/86xx counterparts. + The other embedded parts, namely 4xx, 8xx, e200 (55xx) and e500 + (85xx) each form a family of their own that is not compatible + with the others. + + If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. + +config PPC_BOOK3S_6xx + bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" + select PPC_BOOK3S_32 + select PPC_FPU + select PPC_HAVE_PMU_SUPPORT + select PPC_HAVE_KUEP + select PPC_HAVE_KUAP + select HAVE_ARCH_VMAP_STACK + +config PPC_85xx + bool "Freescale 85xx" + select E500 + +config PPC_8xx + bool "Freescale 8xx" + select FSL_SOC + select SYS_SUPPORTS_HUGETLBFS + select PPC_HAVE_KUEP + select PPC_HAVE_KUAP + select HAVE_ARCH_VMAP_STACK + select HUGETLBFS + +config 40x + bool "AMCC 40x" + select PPC_DCR_NATIVE + select PPC_UDBG_16550 + select 4xx_SOC + select HAVE_PCI + +config 44x + bool "AMCC 44x, 46x or 47x" + select PPC_DCR_NATIVE + select PPC_UDBG_16550 + select 4xx_SOC + select HAVE_PCI + select PHYS_64BIT + +config E200 + bool "Freescale e200" + +endchoice + +choice + prompt "Processor Type" + depends on PPC64 + help + There are two families of 64 bit PowerPC chips supported. + The most common ones are the desktop and server CPUs + (POWER5, 970, POWER5+, POWER6, POWER7, POWER8, POWER9 ...) + + The other are the "embedded" processors compliant with the + "Book 3E" variant of the architecture + +config PPC_BOOK3S_64 + bool "Server processors" + select PPC_FPU + select PPC_HAVE_PMU_SUPPORT + select SYS_SUPPORTS_HUGETLBFS + select HAVE_ARCH_TRANSPARENT_HUGEPAGE + select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE + select ARCH_SUPPORTS_NUMA_BALANCING + select IRQ_WORK + select PPC_MM_SLICES + +config PPC_BOOK3E_64 + bool "Embedded processors" + select PPC_FPU # Make it a choice ? + select PPC_SMP_MUXED_IPI + select PPC_DOORBELL + +endchoice + +choice + prompt "CPU selection" + default GENERIC_CPU + help + This will create a kernel which is optimised for a particular CPU. + The resulting kernel may not run on other CPUs, so use this with care. + + If unsure, select Generic. + +config GENERIC_CPU + bool "Generic (POWER4 and above)" + depends on PPC64 && !CPU_LITTLE_ENDIAN + +config GENERIC_CPU + bool "Generic (POWER8 and above)" + depends on PPC64 && CPU_LITTLE_ENDIAN + select ARCH_HAS_FAST_MULTIPLIER + +config POWERPC_CPU + bool "Generic 32 bits powerpc" + depends on PPC32 && !PPC_8xx && !PPC_85xx + +config CELL_CPU + bool "Cell Broadband Engine" + depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN + +config POWER5_CPU + bool "POWER5" + depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN + +config POWER6_CPU + bool "POWER6" + depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN + +config POWER7_CPU + bool "POWER7" + depends on PPC_BOOK3S_64 + select ARCH_HAS_FAST_MULTIPLIER + +config POWER8_CPU + bool "POWER8" + depends on PPC_BOOK3S_64 + select ARCH_HAS_FAST_MULTIPLIER + +config POWER9_CPU + bool "POWER9" + depends on PPC_BOOK3S_64 + select ARCH_HAS_FAST_MULTIPLIER + +config E5500_CPU + bool "Freescale e5500" + depends on PPC64 && E500 + +config E6500_CPU + bool "Freescale e6500" + depends on PPC64 && E500 + +config 860_CPU + bool "8xx family" + depends on PPC_8xx + +config E300C2_CPU + bool "e300c2 (832x)" + depends on PPC_BOOK3S_32 + +config E300C3_CPU + bool "e300c3 (831x)" + depends on PPC_BOOK3S_32 + +config G4_CPU + bool "G4 (74xx)" + depends on PPC_BOOK3S_32 + select ALTIVEC + +config E500_CPU + bool "e500 (8540)" + depends on PPC_85xx && !PPC_E500MC + +config E500MC_CPU + bool "e500mc" + depends on PPC_85xx && PPC_E500MC + +config TOOLCHAIN_DEFAULT_CPU + bool "Rely on the toolchain's implicit default CPU" + depends on PPC32 + +endchoice + +config TARGET_CPU_BOOL + bool + default !GENERIC_CPU && !TOOLCHAIN_DEFAULT_CPU + +config TARGET_CPU + string + depends on TARGET_CPU_BOOL + default "cell" if CELL_CPU + default "power5" if POWER5_CPU + default "power6" if POWER6_CPU + default "power7" if POWER7_CPU + default "power8" if POWER8_CPU + default "power9" if POWER9_CPU + default "860" if 860_CPU + default "e300c2" if E300C2_CPU + default "e300c3" if E300C3_CPU + default "G4" if G4_CPU + default "8540" if E500_CPU + default "e500mc" if E500MC_CPU + default "powerpc" if POWERPC_CPU + +config PPC_BOOK3S + def_bool y + depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 + +config PPC_BOOK3E + def_bool y + depends on PPC_BOOK3E_64 + +config E500 + select FSL_EMB_PERFMON + select PPC_FSL_BOOK3E + bool + +config PPC_E500MC + bool "e500mc Support" + select PPC_FPU + select COMMON_CLK + depends on E500 + help + This must be enabled for running on e500mc (and derivatives + such as e5500/e6500), and must be disabled for running on + e500v1 or e500v2. + +config PPC_FPU + bool + default y if PPC64 + +config FSL_EMB_PERFMON + bool "Freescale Embedded Perfmon" + depends on E500 || PPC_83xx + help + This is the Performance Monitor support found on the e500 core + and some e300 cores (c3 and c4). Select this only if your + core supports the Embedded Performance Monitor APU + +config FSL_EMB_PERF_EVENT + bool + depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS + default y + +config FSL_EMB_PERF_EVENT_E500 + bool + depends on FSL_EMB_PERF_EVENT && E500 + default y + +config 4xx + bool + depends on 40x || 44x + default y + +config BOOKE + bool + depends on E200 || E500 || 44x || PPC_BOOK3E + default y + +config FSL_BOOKE + bool + depends on (E200 || E500) && PPC32 + default y + +# this is for common code between PPC32 & PPC64 FSL BOOKE +config PPC_FSL_BOOK3E + bool + select FSL_EMB_PERFMON + select PPC_SMP_MUXED_IPI + select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 + select PPC_DOORBELL + default y if FSL_BOOKE + +config PTE_64BIT + bool + depends on 44x || E500 || PPC_86xx + default y if PHYS_64BIT + +config PHYS_64BIT + bool 'Large physical address support' if E500 || PPC_86xx + depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx + select PHYS_ADDR_T_64BIT + help + This option enables kernel support for larger than 32-bit physical + addresses. This feature may not be available on all cores. + + If you have more than 3.5GB of RAM or so, you also need to enable + SWIOTLB under Kernel Options for this to work. The actual number + is platform-dependent. + + If in doubt, say N here. + +config ALTIVEC + bool "AltiVec Support" + depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 || (PPC_E500MC && PPC64) + help + This option enables kernel support for the Altivec extensions to the + PowerPC processor. The kernel currently supports saving and restoring + altivec registers, and turning on the 'altivec enable' bit so user + processes can execute altivec instructions. + + This option is only usefully if you have a processor that supports + altivec (G4, otherwise known as 74xx series), but does not have + any affect on a non-altivec cpu (it does, however add code to the + kernel). + + If in doubt, say Y here. + +config VSX + bool "VSX Support" + depends on PPC_BOOK3S_64 && ALTIVEC && PPC_FPU + help + + This option enables kernel support for the Vector Scaler extensions + to the PowerPC processor. The kernel currently supports saving and + restoring VSX registers, and turning on the 'VSX enable' bit so user + processes can execute VSX instructions. + + This option is only useful if you have a processor that supports + VSX (P7 and above), but does not have any affect on a non-VSX + CPUs (it does, however add code to the kernel). + + If in doubt, say Y here. + +config SPE_POSSIBLE + def_bool y + depends on E200 || (E500 && !PPC_E500MC) + +config SPE + bool "SPE Support" + depends on SPE_POSSIBLE + default y + help + This option enables kernel support for the Signal Processing + Extensions (SPE) to the PowerPC processor. The kernel currently + supports saving and restoring SPE registers, and turning on the + 'spe enable' bit so user processes can execute SPE instructions. + + This option is only useful if you have a processor that supports + SPE (e500, otherwise known as 85xx series), but does not have any + effect on a non-spe cpu (it does, however add code to the kernel). + + If in doubt, say Y here. + +config ARCH_ENABLE_SPLIT_PMD_PTLOCK + def_bool y + depends on PPC_BOOK3S_64 + +config PPC_RADIX_MMU + bool "Radix MMU Support" + depends on PPC_BOOK3S_64 + select ARCH_HAS_GIGANTIC_PAGE + select PPC_HAVE_KUEP + select PPC_HAVE_KUAP + default y + help + Enable support for the Power ISA 3.0 Radix style MMU. Currently this + is only implemented by IBM Power9 CPUs, if you don't have one of them + you can probably disable this. + +config PPC_RADIX_MMU_DEFAULT + bool "Default to using the Radix MMU when possible" + depends on PPC_RADIX_MMU + default y + help + When the hardware supports the Radix MMU, default to using it unless + "disable_radix[=yes]" is specified on the kernel command line. + + If this option is disabled, the Hash MMU will be used by default, + unless "disable_radix=no" is specified on the kernel command line. + + If you're unsure, say Y. + +config PPC_HAVE_KUEP + bool + +config PPC_KUEP + bool "Kernel Userspace Execution Prevention" + depends on PPC_HAVE_KUEP + default y if !PPC_BOOK3S_32 + help + Enable support for Kernel Userspace Execution Prevention (KUEP) + + If you're unsure, say Y. + +config PPC_HAVE_KUAP + bool + +config PPC_KUAP + bool "Kernel Userspace Access Protection" + depends on PPC_HAVE_KUAP + default y if !PPC_BOOK3S_32 + help + Enable support for Kernel Userspace Access Protection (KUAP) + + If you're unsure, say Y. + +config PPC_KUAP_DEBUG + bool "Extra debugging for Kernel Userspace Access Protection" + depends on PPC_KUAP && (PPC_RADIX_MMU || PPC32) + help + Add extra debugging for Kernel Userspace Access Protection (KUAP) + If you're unsure, say N. + +config ARCH_ENABLE_HUGEPAGE_MIGRATION + def_bool y + depends on PPC_BOOK3S_64 && HUGETLB_PAGE && MIGRATION + + +config PPC_MMU_NOHASH + def_bool y + depends on !PPC_BOOK3S + +config PPC_MMU_NOHASH_32 + def_bool y + depends on PPC_MMU_NOHASH && PPC32 + +config PPC_BOOK3E_MMU + def_bool y + depends on FSL_BOOKE || PPC_BOOK3E + +config PPC_MM_SLICES + bool + +config PPC_HAVE_PMU_SUPPORT + bool + +config PMU_SYSFS + bool "Create PMU SPRs sysfs file" + default n + help + This option enables sysfs file creation for PMU SPRs like MMCR* and PMC*. + +config PPC_PERF_CTRS + def_bool y + depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT + help + This enables the powerpc-specific perf_event back-end. + +config FORCE_SMP + # Allow platforms to force SMP=y by selecting this + bool + select SMP + +config SMP + depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x + select GENERIC_IRQ_MIGRATION + bool "Symmetric multi-processing support" if !FORCE_SMP + help + This enables support for systems with more than one CPU. If you have + a system with only one CPU, say N. If you have a system with more + than one CPU, say Y. Note that the kernel does not currently + support SMP machines with 603/603e/603ev or PPC750 ("G3") processors + since they have inadequate hardware support for multiprocessor + operation. + + If you say N here, the kernel will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor machine. If + you say Y here, the kernel will run on single-processor machines. + On a single-processor machine, the kernel will run faster if you say + N here. + + If you don't know what to do here, say N. + +config NR_CPUS + int "Maximum number of CPUs (2-8192)" + range 2 8192 + depends on SMP + default "32" if PPC64 + default "4" + +config NOT_COHERENT_CACHE + bool + depends on 4xx || PPC_8xx || E200 || PPC_MPC512x || \ + GAMECUBE_COMMON || AMIGAONE + select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_HAS_SYNC_DMA_FOR_CPU + select DMA_DIRECT_REMAP + default n if PPC_47x + default y + +config CHECK_CACHE_COHERENCY + bool + +config PPC_DOORBELL + bool + +endmenu + +config VDSO32 + def_bool y + depends on PPC32 || COMPAT + help + This symbol controls whether we build the 32-bit VDSO. We obviously + want to do that if we're building a 32-bit kernel. If we're building + a 64-bit kernel then we only want a 32-bit VDSO if we're also enabling + COMPAT. + +choice + prompt "Endianness selection" + default CPU_BIG_ENDIAN + help + This option selects whether a big endian or little endian kernel will + be built. + +config CPU_BIG_ENDIAN + bool "Build big endian kernel" + help + Build a big endian kernel. + + If unsure, select this option. + +config CPU_LITTLE_ENDIAN + bool "Build little endian kernel" + depends on PPC_BOOK3S_64 + select PPC64_BOOT_WRAPPER + help + Build a little endian kernel. + + Note that if cross compiling a little endian kernel, + CROSS_COMPILE must point to a toolchain capable of targeting + little endian powerpc. + +endchoice + +config PPC64_BOOT_WRAPPER + def_bool n + depends on CPU_LITTLE_ENDIAN |