diff options
Diffstat (limited to 'debian/patches/features/arm64/arm64-dts-rockchip-Add-support-for-PCIe-on-helios64.patch')
| -rw-r--r-- | debian/patches/features/arm64/arm64-dts-rockchip-Add-support-for-PCIe-on-helios64.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-support-for-PCIe-on-helios64.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-support-for-PCIe-on-helios64.patch new file mode 100644 index 000000000..6abebd080 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-support-for-PCIe-on-helios64.patch @@ -0,0 +1,113 @@ +From: Uwe Kleine-König <uwe@kleine-koenig.org> +Date: Mon, 10 May 2021 11:09:32 +0200 +Subject: arm64: dts: rockchip: Add support for PCIe on helios64 +Origin: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/patch/?id=5a65adfa2ad1542f856fc7de3999d51f3a35d2e2 + +This is enough to make the SATA controller visible: + +# lspci +00:00.0 PCI bridge: Fuzhou Rockchip Electronics Co., Ltd RK3399 PCI Express Root Port +01:00.0 SATA controller: JMicron Technology Corp. JMB58x AHCI SATA controller + +Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> +Link: https://lore.kernel.org/r/20210510090932.970447-1-uwe@kleine-koenig.org +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../dts/rockchip/rk3399-kobol-helios64.dts | 53 +++++++++++++++++++ + 1 file changed, 53 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index 9d4a0885fd12..037dc5cdc3f3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -23,6 +23,16 @@ aliases { + mmc1 = &sdhci; + }; + ++ avdd_0v9_s0: avdd-0v9-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd_0v9_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc1v8_sys_s3>; ++ }; ++ + avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_1v8_s0"; +@@ -72,6 +82,18 @@ led-1 { + }; + }; + ++ pcie_power: pcie-power { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&pcie_pwr>; ++ pinctrl-names = "default"; ++ regulator-boot-on; ++ regulator-name = "pcie_power"; ++ startup-delay-us = <10000>; ++ vin-supply = <&vcc5v0_perdev>; ++ }; ++ + vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys_s0"; +@@ -109,6 +131,16 @@ regulator-state-mem { + }; + }; + ++ vcc5v0_perdev: vcc5v0-perdev { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_perdev"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -331,6 +363,20 @@ &io_domains { + status = "okay"; + }; + ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ num-lanes = <2>; ++ status = "okay"; ++ ++ vpcie12v-supply = <&vcc12v_dcin>; ++ vpcie3v3-supply = <&pcie_power>; ++ vpcie1v8-supply = <&avdd_1v8_s0>; ++ vpcie0v9-supply = <&avdd_0v9_s0>; ++}; ++ + &pinctrl { + gmac { + gphy_reset: gphy-reset { +@@ -348,6 +394,13 @@ sys_red_led_on: sys-red-led-on { + }; + }; + ++ pcie { ++ pcie_pwr: pcie-pwr { ++ rockchip,pins = ++ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; +-- +2.30.2 + |