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| -rw-r--r-- | drivers/reset/Kconfig | 254 |
1 files changed, 254 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig new file mode 100644 index 000000000..147543ad3 --- /dev/null +++ b/drivers/reset/Kconfig @@ -0,0 +1,254 @@ +# SPDX-License-Identifier: GPL-2.0-only +config ARCH_HAS_RESET_CONTROLLER + bool + +menuconfig RESET_CONTROLLER + bool "Reset Controller Support" + default y if ARCH_HAS_RESET_CONTROLLER + help + Generic Reset Controller support. + + This framework is designed to abstract reset handling of devices + via GPIOs or SoC-internal reset controller modules. + + If unsure, say no. + +if RESET_CONTROLLER + +config RESET_A10SR + tristate "Altera Arria10 System Resource Reset" + depends on MFD_ALTERA_A10SR + help + This option enables support for the external reset functions for + peripheral PHYs on the Altera Arria10 System Resource Chip. + +config RESET_ATH79 + bool "AR71xx Reset Driver" if COMPILE_TEST + default ATH79 + help + This enables the ATH79 reset controller driver that supports the + AR71xx SoC reset controller. + +config RESET_AXS10X + bool "AXS10x Reset Driver" if COMPILE_TEST + default ARC_PLAT_AXS10X + help + This enables the reset controller driver for AXS10x. + +config RESET_BERLIN + bool "Berlin Reset Driver" if COMPILE_TEST + default ARCH_BERLIN + help + This enables the reset controller driver for Marvell Berlin SoCs. + +config RESET_BRCMSTB + tristate "Broadcom STB reset controller" + depends on ARCH_BRCMSTB || COMPILE_TEST + default ARCH_BRCMSTB + help + This enables the reset controller driver for Broadcom STB SoCs using + a SUN_TOP_CTRL_SW_INIT style controller. + +config RESET_BRCMSTB_RESCAL + bool "Broadcom STB RESCAL reset controller" + depends on HAS_IOMEM + depends on ARCH_BRCMSTB || COMPILE_TEST + default ARCH_BRCMSTB + help + This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on + BCM7216. + +config RESET_HSDK + bool "Synopsys HSDK Reset Driver" + depends on HAS_IOMEM + depends on ARC_SOC_HSDK || COMPILE_TEST + help + This enables the reset controller driver for HSDK board. + +config RESET_IMX7 + tristate "i.MX7/8 Reset Driver" + depends on HAS_IOMEM + depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST + default y if SOC_IMX7D + select MFD_SYSCON + help + This enables the reset controller driver for i.MX7 SoCs. + +config RESET_INTEL_GW + bool "Intel Reset Controller Driver" + depends on X86 || COMPILE_TEST + depends on OF && HAS_IOMEM + select REGMAP_MMIO + help + This enables the reset controller driver for Intel Gateway SoCs. + Say Y to control the reset signals provided by reset controller. + Otherwise, say N. + +config RESET_LANTIQ + bool "Lantiq XWAY Reset Driver" if COMPILE_TEST + default SOC_TYPE_XWAY + help + This enables the reset controller driver for Lantiq / Intel XWAY SoCs. + +config RESET_LPC18XX + bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST + default ARCH_LPC18XX + help + This enables the reset controller driver for NXP LPC18xx/43xx SoCs. + +config RESET_MESON + bool "Meson Reset Driver" if COMPILE_TEST + default ARCH_MESON + help + This enables the reset driver for Amlogic Meson SoCs. + +config RESET_MESON_AUDIO_ARB + tristate "Meson Audio Memory Arbiter Reset Driver" + depends on ARCH_MESON || COMPILE_TEST + help + This enables the reset driver for Audio Memory Arbiter of + Amlogic's A113 based SoCs + +config RESET_NPCM + bool "NPCM BMC Reset Driver" if COMPILE_TEST + default ARCH_NPCM + help + This enables the reset controller driver for Nuvoton NPCM + BMC SoCs. + +config RESET_OXNAS + bool + +config RESET_PISTACHIO + bool "Pistachio Reset Driver" if COMPILE_TEST + default MACH_PISTACHIO + help + This enables the reset driver for ImgTec Pistachio SoCs. + +config RESET_QCOM_AOSS + tristate "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This enables the AOSS (always on subsystem) reset driver + for Qualcomm SDM845 SoCs. Say Y if you want to control + reset signals provided by AOSS for Modem, Venus, ADSP, + GPU, Camera, Wireless, Display subsystem. Otherwise, say N. + +config RESET_QCOM_PDC + tristate "Qualcomm PDC Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This enables the PDC (Power Domain Controller) reset driver + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want + to control reset signals provided by PDC for Modem, Compute, + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. + +config RESET_RASPBERRYPI + tristate "Raspberry Pi 4 Firmware Reset Driver" + depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) + default USB_XHCI_PCI + help + Raspberry Pi 4's co-processor controls some of the board's HW + initialization process, but it's up to Linux to trigger it when + relevant. This driver provides a reset controller capable of + interfacing with RPi4's co-processor and model these firmware + initialization routines as reset lines. + +config RESET_SCMI + tristate "Reset driver controlled via ARM SCMI interface" + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST + default ARM_SCMI_PROTOCOL + help + This driver provides support for reset signal/domains that are + controlled by firmware that implements the SCMI interface. + + This driver uses SCMI Message Protocol to interact with the + firmware controlling all the reset signals. + +config RESET_SIMPLE + bool "Simple Reset Controller Driver" if COMPILE_TEST + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + help + This enables a simple reset controller driver for reset lines that + that can be asserted and deasserted by toggling bits in a contiguous, + exclusive register space. + + Currently this driver supports: + - Altera SoCFPGAs + - ASPEED BMC SoCs + - Bitmain BM1880 SoC + - Realtek SoCs + - RCC reset controller in STM32 MCUs + - Allwinner SoCs + - ZTE's zx2967 family + +config RESET_STM32MP157 + bool "STM32MP157 Reset Driver" if COMPILE_TEST + default MACH_STM32MP157 + help + This enables the RCC reset controller driver for STM32 MPUs. + +config RESET_SOCFPGA + bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA + default ARCH_SOCFPGA + select RESET_SIMPLE + help + This enables the reset driver for the SoCFPGA ARMv7 platforms. This + driver gets initialized early during platform init calls. + +config RESET_SUNXI + bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI + default ARCH_SUNXI + select RESET_SIMPLE + help + This enables the reset driver for Allwinner SoCs. + +config RESET_TI_SCI + tristate "TI System Control Interface (TI-SCI) reset driver" + depends on TI_SCI_PROTOCOL + help + This enables the reset driver support over TI System Control Interface + available on some new TI's SoCs. If you wish to use reset resources + managed by the TI System Controller, say Y here. Otherwise, say N. + +config RESET_TI_SYSCON + tristate "TI SYSCON Reset Driver" + depends on HAS_IOMEM + select MFD_SYSCON + help + This enables the reset driver support for TI devices with + memory-mapped reset registers as part of a syscon device node. If + you wish to use the reset framework for such memory-mapped devices, + say Y here. Otherwise, say N. + +config RESET_UNIPHIER + tristate "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on OF && MFD_SYSCON + default ARCH_UNIPHIER + help + Support for reset controllers on UniPhier SoCs. + Say Y if you want to control reset signals provided by System Control + block, Media I/O block, Peripheral Block. + +config RESET_UNIPHIER_GLUE + tristate "Reset driver in glue layer for UniPhier SoCs" + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + default ARCH_UNIPHIER + select RESET_SIMPLE + help + Support for peripheral core reset included in its own glue layer + on UniPhier SoCs. Say Y if you want to control reset signals + provided by the glue layer. + +config RESET_ZYNQ + bool "ZYNQ Reset Driver" if COMPILE_TEST + default ARCH_ZYNQ + help + This enables the reset controller driver for Xilinx Zynq SoCs. + +source "drivers/reset/sti/Kconfig" +source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/tegra/Kconfig" + +endif |